* [igt-dev] [PATCH 1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h
@ 2023-11-09 7:07 Lang Yu
2023-11-09 7:07 ` [igt-dev] [PATCH 2/2] tests/amdgpu: add VPE tests Lang Yu
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Lang Yu @ 2023-11-09 7:07 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Lang Yu
Take from https://anongit.freedesktop.org/git/drm/drm.git.
branch: drm-next
commit: 9ccde17d46554dbb2757c427f2cdf67688701f96
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
include/drm-uapi/amdgpu_drm.h | 50 ++++++++++++++++++++++++++---------
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index f44e140ad..ad21c613f 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -94,6 +94,9 @@ extern "C" {
*
* %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
* for appending data.
+ *
+ * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
+ * signalling user mode queues.
*/
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -101,12 +104,14 @@ extern "C" {
#define AMDGPU_GEM_DOMAIN_GDS 0x8
#define AMDGPU_GEM_DOMAIN_GWS 0x10
#define AMDGPU_GEM_DOMAIN_OA 0x20
+#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
AMDGPU_GEM_DOMAIN_GTT | \
AMDGPU_GEM_DOMAIN_VRAM | \
AMDGPU_GEM_DOMAIN_GDS | \
AMDGPU_GEM_DOMAIN_GWS | \
- AMDGPU_GEM_DOMAIN_OA)
+ AMDGPU_GEM_DOMAIN_OA | \
+ AMDGPU_GEM_DOMAIN_DOORBELL)
/* Flag that CPU access will be required for the case of VRAM domain */
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
@@ -145,7 +150,7 @@ extern "C" {
*/
#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
/* Flag that BO is shared coherently between multiple devices or CPU threads.
- * May depend on GPU instructions to flush caches explicitly
+ * May depend on GPU instructions to flush caches to system scope explicitly.
*
* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
@@ -158,6 +163,14 @@ extern "C" {
* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
*/
#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
+/* Flag that BO should be coherent across devices when using device-level
+ * atomics. May depend on GPU instructions to flush caches to device scope
+ * explicitly, promoting them to system scope automatically.
+ *
+ * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
+ * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
+ */
+#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -236,9 +249,9 @@ union drm_amdgpu_bo_list {
/* unknown cause */
#define AMDGPU_CTX_UNKNOWN_RESET 3
-/* indicate gpu reset occured after ctx created */
+/* indicate gpu reset occurred after ctx created */
#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
-/* indicate vram lost occured after ctx created */
+/* indicate vram lost occurred after ctx created */
#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
/* indicate some job from this context once cause gpu hang */
#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
@@ -259,13 +272,6 @@ union drm_amdgpu_bo_list {
*/
#define AMDGPU_CTX_PRIORITY_HIGH 512
#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
-/* select a stable profiling pstate for perfmon tools */
-#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
-#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
-#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
-#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
-#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
-#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
/* select a stable profiling pstate for perfmon tools */
#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
@@ -588,7 +594,8 @@ struct drm_amdgpu_gem_va {
*/
#define AMDGPU_HW_IP_VCN_ENC 7
#define AMDGPU_HW_IP_VCN_JPEG 8
-#define AMDGPU_HW_IP_NUM 9
+#define AMDGPU_HW_IP_VPE 9
+#define AMDGPU_HW_IP_NUM 10
#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
@@ -799,6 +806,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
#define AMDGPU_INFO_FW_MES 0x1a
/* Subquery id: Query IMU firmware version */
#define AMDGPU_INFO_FW_IMU 0x1b
+ /* Subquery id: Query VPE firmware version */
+ #define AMDGPU_INFO_FW_VPE 0x1c
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
@@ -897,6 +906,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
/* Query the max number of IBs per gang per submission */
#define AMDGPU_INFO_MAX_IBS 0x22
+/* query last page fault info */
+#define AMDGPU_INFO_GPUVM_FAULT 0x23
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -1222,6 +1233,20 @@ struct drm_amdgpu_info_video_caps {
struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
};
+#define AMDGPU_VMHUB_TYPE_MASK 0xff
+#define AMDGPU_VMHUB_TYPE_SHIFT 0
+#define AMDGPU_VMHUB_TYPE_GFX 0
+#define AMDGPU_VMHUB_TYPE_MM0 1
+#define AMDGPU_VMHUB_TYPE_MM1 2
+#define AMDGPU_VMHUB_IDX_MASK 0xff00
+#define AMDGPU_VMHUB_IDX_SHIFT 8
+
+struct drm_amdgpu_info_gpuvm_fault {
+ __u64 addr;
+ __u32 status;
+ __u32 vmhub;
+};
+
/*
* Supported GPU families
*/
@@ -1240,6 +1265,7 @@ struct drm_amdgpu_info_video_caps {
#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */
#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
+#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
#if defined(__cplusplus)
}
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [igt-dev] [PATCH 2/2] tests/amdgpu: add VPE tests
2023-11-09 7:07 [igt-dev] [PATCH 1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h Lang Yu
@ 2023-11-09 7:07 ` Lang Yu
2023-11-09 11:13 ` Kamil Konieczny
2023-11-09 8:24 ` [igt-dev] ✗ Fi.CI.BUILD: failure for series starting with [1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h Patchwork
2023-11-09 11:08 ` [igt-dev] [PATCH 1/2] " Kamil Konieczny
2 siblings, 1 reply; 7+ messages in thread
From: Lang Yu @ 2023-11-09 7:07 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Lang Yu
Add tests for Video Processing Engine,
including fence and blit tests.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
lib/amdgpu/amd_mmd_shared.h | 5 +
tests/amdgpu/amd_vpe.c | 254 ++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
3 files changed, 260 insertions(+)
create mode 100644 tests/amdgpu/amd_vpe.c
diff --git a/lib/amdgpu/amd_mmd_shared.h b/lib/amdgpu/amd_mmd_shared.h
index 82e732509..14f9ecb4d 100644
--- a/lib/amdgpu/amd_mmd_shared.h
+++ b/lib/amdgpu/amd_mmd_shared.h
@@ -54,6 +54,11 @@ struct mmd_context {
bool enc_ring;
/* jpeg */
bool jpeg_direct_reg;
+
+ /*vpe*/
+ uint32_t vpe_ip_version_major;
+ uint32_t vpe_ip_version_minor;
+ bool vpe_ring;
};
struct amdgpu_mmd_bo {
diff --git a/tests/amdgpu/amd_vpe.c b/tests/amdgpu/amd_vpe.c
new file mode 100644
index 000000000..4aeb7395e
--- /dev/null
+++ b/tests/amdgpu/amd_vpe.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+#include "igt.h"
+
+#include <amdgpu.h>
+#include "amdgpu_drm.h"
+#include "lib/amdgpu/amd_mmd_shared.h"
+
+#define IB_SIZE 4096
+#define MAX_RESOURCES 16
+
+#define PLANE_WIDTH 1024
+#define PLANE_HEIGHT 256
+#define PLANE_SIZE (PLANE_WIDTH*PLANE_HEIGHT*4)
+
+#define SRC_PLANE_PATTERN 0x12345678
+#define DST_PLANE_PATTERN 0xff123456
+
+static uint32_t vpe_descriptor[] = {
+0x00000001, 0x33002200, 0xff000021, 0x00000003, 0x33002234, 0xff000021, 0x33002328, 0xff000021,
+0x33002384, 0xff000021, 0x330023c0, 0xff000021,
+};
+
+static uint32_t vpe_config[] = {
+0x00000002, 0x00000000, 0xbeefbe00, 0xff005678, 0x000003ff, 0x00000000, 0x00ff43ff, 0x00000000,
+0xbeefbe00, 0xff005679, 0x000003ff, 0x00000000, 0x00ff43ff, 0x003b0003, 0x00047808, 0x00000809,
+0x0004780c, 0x000000e4, 0x00047d10, 0x00000009, 0x00047d14, 0x00000101, 0x00047d18, 0x00000000,
+0x00047d1c, 0x00000000, 0x00047d20, 0x00000000, 0x00047d24, 0x0001f010, 0x00047d28, 0x0001f010,
+0x00047d2c, 0x0001f010, 0x00547ee9, 0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000,
+0x00002000, 0x00047ee4, 0x00000001, 0x00047ee0, 0x00000000, 0x00047f24, 0x00000000, 0x00047fc4,
+0x00000000, 0x00547f05, 0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00002000,
+0x00047f00, 0x00000001, 0x00049700, 0x00000000, 0x00049704, 0x0000000f, 0x00049f30, 0x00000000,
+0x00049708, 0x00000000, 0x0004970c, 0xffff0462, 0x0004a208, 0x00000000, 0x0004971c, 0x00000000,
+0x00047fc0, 0x0001f000, 0x00150003, 0x00047df8, 0x00000001, 0x00047dfc, 0x00000001, 0x00047da8,
+0x00000006, 0x00047e18, 0x00000000, 0x0004970c, 0xffff0422, 0x00049710, 0x0001f000, 0x00049714,
+0x0001f000, 0x00049718, 0x0001f000, 0x00049720, 0x00000000, 0x00049724, 0x00000000, 0x00049728,
+0x00000000, 0x000d0003, 0x00047810, 0x00000000, 0x00047814, 0x01000400, 0x00047818, 0x00000000,
+0x0004781c, 0x01000400, 0x00047e00, 0x00000000, 0x00047e04, 0x01000400, 0x00047e08, 0x01000400,
+0x00280003, 0x00047820, 0x00000036, 0x00047824, 0x0960f015, 0x0004972c, 0x00000014, 0x0004972c,
+0x00000014, 0x0004972c, 0x00000014, 0x00049f90, 0x00000000, 0x00049f94, 0x00000001, 0x00549f99,
+0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00002000, 0x00049850, 0x00000000,
+0x00049f34, 0x00000000, 0x00049f38, 0x02fff000, 0x00049f3c, 0x00fff000, 0x00049f40, 0x00fff000,
+0x0004aba0, 0xffff0000, 0x0004aba0, 0xffff0000, 0x0004aacc, 0x00000000, 0x0004aad4, 0x00000013,
+0x0004aad4, 0x00000013,
+};
+
+static bool is_vpe_tests_enabled(amdgpu_device_handle device_handle,
+ struct mmd_context *context)
+{
+ struct drm_amdgpu_info_hw_ip info;
+ int r;
+
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VPE, 0, &info);
+ igt_assert_eq(r, 0);
+
+ context->vpe_ip_version_major = info.hw_ip_version_major;
+ context->vpe_ip_version_minor = info.hw_ip_version_minor;
+ context->vpe_ring = !!info.available_rings;
+
+ if (!context->vpe_ring) {
+ igt_info("VPE no available rings");
+ igt_info("VPE fence test disable");
+ igt_info("VPE blit test disable");
+ }
+
+ return true;
+}
+
+static void amdgpu_cs_vpe_fence(amdgpu_device_handle device_handle,
+ struct mmd_context *context);
+static void amdgpu_cs_vpe_blit(amdgpu_device_handle device_handle,
+ struct mmd_context *context);
+
+igt_main
+{
+ struct mmd_context context = {};
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int r;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ igt_require(fd > 0);
+
+ r = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(r == 0);
+
+ igt_info("Initialized amdgpu, driver version %d.%d\n", major, minor);
+
+ r = mmd_context_init(device, &context);
+ igt_require(r == 0);
+
+ igt_skip_on(!is_vpe_tests_enabled(device, &context));
+ }
+
+ igt_describe("Test VPE fence");
+ igt_subtest("vpe-fence-test")
+ amdgpu_cs_vpe_fence(device, &context);
+
+ igt_describe("Test VPE blit");
+ igt_subtest("vpe-blit-test")
+ amdgpu_cs_vpe_blit(device, &context);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ drm_close_driver(fd);
+ }
+
+}
+
+static void amdgpu_cs_vpe_fence(amdgpu_device_handle device_handle,
+ struct mmd_context *context)
+{
+ const uint32_t test_pattern = 0xdeadbeef;
+ uint32_t *ib_cpu = context->ib_cpu;
+ struct amdgpu_mmd_bo test_bo;
+ int r;
+
+ context->num_resources = 0;
+ alloc_resource(device_handle, &test_bo, 4096, AMDGPU_GEM_DOMAIN_GTT);
+ context->resources[context->num_resources++] = test_bo.handle;
+
+ r = amdgpu_bo_cpu_map(test_bo.handle, (void **)&test_bo.ptr);
+ igt_assert_eq(r, 0);
+
+ memset(test_bo.ptr, 0, 4096);
+
+ memset(ib_cpu, 0, IB_SIZE);
+
+ ib_cpu[0] = 0x5;
+ ib_cpu[1] = 0xfffffffc & test_bo.addr;
+ ib_cpu[2] = (0xffffffff00000000 & test_bo.addr) >> 32;
+ ib_cpu[3] = test_pattern;
+ ib_cpu[4] = 0x0;
+ ib_cpu[5] = 0x0;
+ ib_cpu[6] = 0x0;
+ ib_cpu[7] = 0x0;
+
+ context->resources[context->num_resources++] = context->ib_handle;
+
+ r = submit(device_handle, context, 8, AMDGPU_HW_IP_VPE);
+ igt_assert_eq(r, 0);
+
+ igt_assert_eq(((uint32_t *)test_bo.ptr)[0], test_pattern);
+
+ r = amdgpu_bo_cpu_unmap(test_bo.handle);
+ igt_assert_eq(r, 0);
+
+ free_resource(&test_bo);
+}
+
+// a in byte 0, b in byte 1, g in byte 2, r in byte 3
+static void create_rgba8888(void *addr, uint32_t width, uint32_t height)
+{
+ uint32_t *ptr = (uint32_t *)addr;
+
+ for (int i = 0; i < height; i++) {
+ for (int j = 0; j < width; j++)
+ ptr[j] = SRC_PLANE_PATTERN;
+ ptr += width;
+ }
+}
+// b in byte 0, g in byte 1, r in byte 2, a in byte 3
+static int check_argb8888(void *addr, uint32_t width, uint32_t height)
+{
+ uint32_t *ptr = (uint32_t *)addr;
+
+ for (int i = 0; i < height; i++) {
+ for (int j = 0; j < width; j++)
+ if (ptr[j] != DST_PLANE_PATTERN)
+ return 1;
+ ptr += width;
+ }
+
+ return 0;
+}
+
+static void amdgpu_cs_vpe_blit(amdgpu_device_handle device_handle,
+ struct mmd_context *context)
+{
+ const uint32_t vpep_config_offsets[] = {0x34, 0x128, 0x184, 0x1c0};
+ struct amdgpu_mmd_bo vpe_config_bo, src_plane_bo, dst_plane_bo;
+ int r;
+
+ context->num_resources = 0;
+
+ alloc_resource(device_handle, &vpe_config_bo, sizeof(vpe_config), AMDGPU_GEM_DOMAIN_GTT);
+ alloc_resource(device_handle, &src_plane_bo, PLANE_SIZE, AMDGPU_GEM_DOMAIN_GTT);
+ alloc_resource(device_handle, &dst_plane_bo, PLANE_SIZE, AMDGPU_GEM_DOMAIN_GTT);
+
+ r = amdgpu_bo_cpu_map(vpe_config_bo.handle, (void **)&vpe_config_bo.ptr);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_cpu_map(src_plane_bo.handle, (void **)&src_plane_bo.ptr);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_cpu_map(dst_plane_bo.handle, (void **)&dst_plane_bo.ptr);
+ igt_assert_eq(r, 0);
+
+ context->resources[context->num_resources++] = vpe_config_bo.handle;
+ context->resources[context->num_resources++] = src_plane_bo.handle;
+ context->resources[context->num_resources++] = dst_plane_bo.handle;
+
+ // plane config gpu addr
+ *(uint64_t *)(vpe_descriptor + 1) = vpe_config_bo.addr;
+ // vpep config0 gpu addr
+ *(uint64_t *)(vpe_descriptor + 4) = vpe_config_bo.addr + vpep_config_offsets[0];
+ // vpep config1 gpu addr
+ *(uint64_t *)(vpe_descriptor + 6) = vpe_config_bo.addr + vpep_config_offsets[1];
+ // vpep config2 gpu addr
+ *(uint64_t *)(vpe_descriptor + 8) = vpe_config_bo.addr + vpep_config_offsets[2];
+ // vpep config3 gpu addr
+ *(uint64_t *)(vpe_descriptor + 10) = vpe_config_bo.addr + vpep_config_offsets[3];
+
+ memset(src_plane_bo.ptr, 0, PLANE_SIZE);
+ memset(dst_plane_bo.ptr, 0, PLANE_SIZE);
+ create_rgba8888(src_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
+
+ /* gpu address of src */
+ *(uint64_t *)(vpe_config + 2) = src_plane_bo.addr;
+ /* gpu address of dst */
+ *(uint64_t *)(vpe_config + 8) = dst_plane_bo.addr;
+
+ memset(vpe_config_bo.ptr, 0, sizeof(vpe_config));
+ memcpy(vpe_config_bo.ptr, vpe_config, sizeof(vpe_config));
+
+ memset(context->ib_cpu, 0, IB_SIZE);
+ memcpy(context->ib_cpu, vpe_descriptor, sizeof(vpe_descriptor));
+
+ context->resources[context->num_resources++] = context->ib_handle;
+
+ r = submit(device_handle, context, sizeof(vpe_descriptor)/4, AMDGPU_HW_IP_VPE);
+ igt_assert_eq(r, 0);
+
+ r = check_argb8888(dst_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_cpu_unmap(vpe_config_bo.handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_cpu_unmap(src_plane_bo.handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_cpu_unmap(dst_plane_bo.handle);
+ igt_assert_eq(r, 0);
+
+ free_resource(&vpe_config_bo);
+ free_resource(&src_plane_bo);
+ free_resource(&dst_plane_bo);
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index f52fc3645..e82e02701 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -36,6 +36,7 @@ if libdrm_amdgpu.found()
'amd_vrr_range',
'amd_mall',
'amd_odm',
+ 'amd_vpe',
]
if libdrm_amdgpu.version().version_compare('> 2.4.97')
amdgpu_progs +=[ 'amd_syncobj', ]
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [igt-dev] ✗ Fi.CI.BUILD: failure for series starting with [1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h
2023-11-09 7:07 [igt-dev] [PATCH 1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h Lang Yu
2023-11-09 7:07 ` [igt-dev] [PATCH 2/2] tests/amdgpu: add VPE tests Lang Yu
@ 2023-11-09 8:24 ` Patchwork
2023-11-09 11:08 ` [igt-dev] [PATCH 1/2] " Kamil Konieczny
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2023-11-09 8:24 UTC (permalink / raw)
To: Lang Yu; +Cc: igt-dev
== Series Details ==
Series: series starting with [1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h
URL : https://patchwork.freedesktop.org/series/126174/
State : failure
== Summary ==
Applying: include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h
Applying: tests/amdgpu: add VPE tests
Using index info to reconstruct a base tree...
M tests/amdgpu/meson.build
Falling back to patching base and 3-way merge...
Auto-merging tests/amdgpu/meson.build
CONFLICT (content): Merge conflict in tests/amdgpu/meson.build
Patch failed at 0002 tests/amdgpu: add VPE tests
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [igt-dev] [PATCH 1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h
2023-11-09 7:07 [igt-dev] [PATCH 1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h Lang Yu
2023-11-09 7:07 ` [igt-dev] [PATCH 2/2] tests/amdgpu: add VPE tests Lang Yu
2023-11-09 8:24 ` [igt-dev] ✗ Fi.CI.BUILD: failure for series starting with [1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h Patchwork
@ 2023-11-09 11:08 ` Kamil Konieczny
2023-11-10 2:45 ` Yu, Lang
2 siblings, 1 reply; 7+ messages in thread
From: Kamil Konieczny @ 2023-11-09 11:08 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Lang Yu
Hi Lang,
On 2023-11-09 at 15:07:34 +0800, Lang Yu wrote:
> Take from https://anongit.freedesktop.org/git/drm/drm.git.
>
> branch: drm-next
> commit: 9ccde17d46554dbb2757c427f2cdf67688701f96
>
> Signed-off-by: Lang Yu <Lang.Yu@amd.com>
This is already part of igt, see latest i-g-t
commit: 63945e20f drm-uapi/amdgpu: sync with drm-next
so you can safely drop first patch.
Side note: please add i-g-t into subject, so it will look:
[PATCH i-g-t 1/2] your_patch_subject_here
Regards,
Kamil
> ---
> include/drm-uapi/amdgpu_drm.h | 50 ++++++++++++++++++++++++++---------
> 1 file changed, 38 insertions(+), 12 deletions(-)
>
> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
> index f44e140ad..ad21c613f 100644
> --- a/include/drm-uapi/amdgpu_drm.h
> +++ b/include/drm-uapi/amdgpu_drm.h
> @@ -94,6 +94,9 @@ extern "C" {
> *
> * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
> * for appending data.
> + *
> + * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
> + * signalling user mode queues.
> */
> #define AMDGPU_GEM_DOMAIN_CPU 0x1
> #define AMDGPU_GEM_DOMAIN_GTT 0x2
> @@ -101,12 +104,14 @@ extern "C" {
> #define AMDGPU_GEM_DOMAIN_GDS 0x8
> #define AMDGPU_GEM_DOMAIN_GWS 0x10
> #define AMDGPU_GEM_DOMAIN_OA 0x20
> +#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
> #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
> AMDGPU_GEM_DOMAIN_GTT | \
> AMDGPU_GEM_DOMAIN_VRAM | \
> AMDGPU_GEM_DOMAIN_GDS | \
> AMDGPU_GEM_DOMAIN_GWS | \
> - AMDGPU_GEM_DOMAIN_OA)
> + AMDGPU_GEM_DOMAIN_OA | \
> + AMDGPU_GEM_DOMAIN_DOORBELL)
>
> /* Flag that CPU access will be required for the case of VRAM domain */
> #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
> @@ -145,7 +150,7 @@ extern "C" {
> */
> #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
> /* Flag that BO is shared coherently between multiple devices or CPU threads.
> - * May depend on GPU instructions to flush caches explicitly
> + * May depend on GPU instructions to flush caches to system scope explicitly.
> *
> * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
> * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
> @@ -158,6 +163,14 @@ extern "C" {
> * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
> */
> #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
> +/* Flag that BO should be coherent across devices when using device-level
> + * atomics. May depend on GPU instructions to flush caches to device scope
> + * explicitly, promoting them to system scope automatically.
> + *
> + * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
> + * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
> + */
> +#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
>
> struct drm_amdgpu_gem_create_in {
> /** the requested memory size */
> @@ -236,9 +249,9 @@ union drm_amdgpu_bo_list {
> /* unknown cause */
> #define AMDGPU_CTX_UNKNOWN_RESET 3
>
> -/* indicate gpu reset occured after ctx created */
> +/* indicate gpu reset occurred after ctx created */
> #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
> -/* indicate vram lost occured after ctx created */
> +/* indicate vram lost occurred after ctx created */
> #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
> /* indicate some job from this context once cause gpu hang */
> #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
> @@ -259,13 +272,6 @@ union drm_amdgpu_bo_list {
> */
> #define AMDGPU_CTX_PRIORITY_HIGH 512
> #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
> -/* select a stable profiling pstate for perfmon tools */
> -#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
> -#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
> -#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
> -#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
> -#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
> -#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
>
> /* select a stable profiling pstate for perfmon tools */
> #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
> @@ -588,7 +594,8 @@ struct drm_amdgpu_gem_va {
> */
> #define AMDGPU_HW_IP_VCN_ENC 7
> #define AMDGPU_HW_IP_VCN_JPEG 8
> -#define AMDGPU_HW_IP_NUM 9
> +#define AMDGPU_HW_IP_VPE 9
> +#define AMDGPU_HW_IP_NUM 10
>
> #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
>
> @@ -799,6 +806,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
> #define AMDGPU_INFO_FW_MES 0x1a
> /* Subquery id: Query IMU firmware version */
> #define AMDGPU_INFO_FW_IMU 0x1b
> + /* Subquery id: Query VPE firmware version */
> + #define AMDGPU_INFO_FW_VPE 0x1c
>
> /* number of bytes moved for TTM migration */
> #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
> @@ -897,6 +906,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
> #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
> /* Query the max number of IBs per gang per submission */
> #define AMDGPU_INFO_MAX_IBS 0x22
> +/* query last page fault info */
> +#define AMDGPU_INFO_GPUVM_FAULT 0x23
>
> #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
> #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
> @@ -1222,6 +1233,20 @@ struct drm_amdgpu_info_video_caps {
> struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
> };
>
> +#define AMDGPU_VMHUB_TYPE_MASK 0xff
> +#define AMDGPU_VMHUB_TYPE_SHIFT 0
> +#define AMDGPU_VMHUB_TYPE_GFX 0
> +#define AMDGPU_VMHUB_TYPE_MM0 1
> +#define AMDGPU_VMHUB_TYPE_MM1 2
> +#define AMDGPU_VMHUB_IDX_MASK 0xff00
> +#define AMDGPU_VMHUB_IDX_SHIFT 8
> +
> +struct drm_amdgpu_info_gpuvm_fault {
> + __u64 addr;
> + __u32 status;
> + __u32 vmhub;
> +};
> +
> /*
> * Supported GPU families
> */
> @@ -1240,6 +1265,7 @@ struct drm_amdgpu_info_video_caps {
> #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */
> #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
> #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
> +#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
>
> #if defined(__cplusplus)
> }
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [igt-dev] [PATCH 2/2] tests/amdgpu: add VPE tests
2023-11-09 7:07 ` [igt-dev] [PATCH 2/2] tests/amdgpu: add VPE tests Lang Yu
@ 2023-11-09 11:13 ` Kamil Konieczny
2023-11-10 2:46 ` Yu, Lang
0 siblings, 1 reply; 7+ messages in thread
From: Kamil Konieczny @ 2023-11-09 11:13 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Lang Yu
Hi Lang,
On 2023-11-09 at 15:07:35 +0800, Lang Yu wrote:
> Add tests for Video Processing Engine,
> including fence and blit tests.
>
> Signed-off-by: Lang Yu <Lang.Yu@amd.com>
> ---
> lib/amdgpu/amd_mmd_shared.h | 5 +
> tests/amdgpu/amd_vpe.c | 254 ++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 3 files changed, 260 insertions(+)
> create mode 100644 tests/amdgpu/amd_vpe.c
>
> diff --git a/lib/amdgpu/amd_mmd_shared.h b/lib/amdgpu/amd_mmd_shared.h
> index 82e732509..14f9ecb4d 100644
> --- a/lib/amdgpu/amd_mmd_shared.h
> +++ b/lib/amdgpu/amd_mmd_shared.h
> @@ -54,6 +54,11 @@ struct mmd_context {
> bool enc_ring;
> /* jpeg */
> bool jpeg_direct_reg;
> +
> + /*vpe*/
> + uint32_t vpe_ip_version_major;
> + uint32_t vpe_ip_version_minor;
> + bool vpe_ring;
> };
>
> struct amdgpu_mmd_bo {
> diff --git a/tests/amdgpu/amd_vpe.c b/tests/amdgpu/amd_vpe.c
> new file mode 100644
> index 000000000..4aeb7395e
> --- /dev/null
> +++ b/tests/amdgpu/amd_vpe.c
> @@ -0,0 +1,254 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +#include "igt.h"
Put this after "amdgpu_drm.h" - first goes system includes,
then igt ones, all in alphabetical order.
> +
> +#include <amdgpu.h>
Put newline here.
> +#include "amdgpu_drm.h"
> +#include "lib/amdgpu/amd_mmd_shared.h"
Put here global test description:
IGT_TEST_DESCRIPTION("Your test description")
> +
> +#define IB_SIZE 4096
> +#define MAX_RESOURCES 16
> +
> +#define PLANE_WIDTH 1024
> +#define PLANE_HEIGHT 256
> +#define PLANE_SIZE (PLANE_WIDTH*PLANE_HEIGHT*4)
> +
> +#define SRC_PLANE_PATTERN 0x12345678
> +#define DST_PLANE_PATTERN 0xff123456
> +
> +static uint32_t vpe_descriptor[] = {
> +0x00000001, 0x33002200, 0xff000021, 0x00000003, 0x33002234, 0xff000021, 0x33002328, 0xff000021,
> +0x33002384, 0xff000021, 0x330023c0, 0xff000021,
> +};
> +
> +static uint32_t vpe_config[] = {
> +0x00000002, 0x00000000, 0xbeefbe00, 0xff005678, 0x000003ff, 0x00000000, 0x00ff43ff, 0x00000000,
> +0xbeefbe00, 0xff005679, 0x000003ff, 0x00000000, 0x00ff43ff, 0x003b0003, 0x00047808, 0x00000809,
> +0x0004780c, 0x000000e4, 0x00047d10, 0x00000009, 0x00047d14, 0x00000101, 0x00047d18, 0x00000000,
> +0x00047d1c, 0x00000000, 0x00047d20, 0x00000000, 0x00047d24, 0x0001f010, 0x00047d28, 0x0001f010,
> +0x00047d2c, 0x0001f010, 0x00547ee9, 0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000,
> +0x00002000, 0x00047ee4, 0x00000001, 0x00047ee0, 0x00000000, 0x00047f24, 0x00000000, 0x00047fc4,
> +0x00000000, 0x00547f05, 0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00002000,
> +0x00047f00, 0x00000001, 0x00049700, 0x00000000, 0x00049704, 0x0000000f, 0x00049f30, 0x00000000,
> +0x00049708, 0x00000000, 0x0004970c, 0xffff0462, 0x0004a208, 0x00000000, 0x0004971c, 0x00000000,
> +0x00047fc0, 0x0001f000, 0x00150003, 0x00047df8, 0x00000001, 0x00047dfc, 0x00000001, 0x00047da8,
> +0x00000006, 0x00047e18, 0x00000000, 0x0004970c, 0xffff0422, 0x00049710, 0x0001f000, 0x00049714,
> +0x0001f000, 0x00049718, 0x0001f000, 0x00049720, 0x00000000, 0x00049724, 0x00000000, 0x00049728,
> +0x00000000, 0x000d0003, 0x00047810, 0x00000000, 0x00047814, 0x01000400, 0x00047818, 0x00000000,
> +0x0004781c, 0x01000400, 0x00047e00, 0x00000000, 0x00047e04, 0x01000400, 0x00047e08, 0x01000400,
> +0x00280003, 0x00047820, 0x00000036, 0x00047824, 0x0960f015, 0x0004972c, 0x00000014, 0x0004972c,
> +0x00000014, 0x0004972c, 0x00000014, 0x00049f90, 0x00000000, 0x00049f94, 0x00000001, 0x00549f99,
> +0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00002000, 0x00049850, 0x00000000,
> +0x00049f34, 0x00000000, 0x00049f38, 0x02fff000, 0x00049f3c, 0x00fff000, 0x00049f40, 0x00fff000,
> +0x0004aba0, 0xffff0000, 0x0004aba0, 0xffff0000, 0x0004aacc, 0x00000000, 0x0004aad4, 0x00000013,
> +0x0004aad4, 0x00000013,
> +};
> +
> +static bool is_vpe_tests_enabled(amdgpu_device_handle device_handle,
> + struct mmd_context *context)
> +{
> + struct drm_amdgpu_info_hw_ip info;
> + int r;
> +
> + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VPE, 0, &info);
> + igt_assert_eq(r, 0);
> +
> + context->vpe_ip_version_major = info.hw_ip_version_major;
> + context->vpe_ip_version_minor = info.hw_ip_version_minor;
> + context->vpe_ring = !!info.available_rings;
> +
> + if (!context->vpe_ring) {
> + igt_info("VPE no available rings");
> + igt_info("VPE fence test disable");
> + igt_info("VPE blit test disable");
> + }
> +
> + return true;
> +}
> +
> +static void amdgpu_cs_vpe_fence(amdgpu_device_handle device_handle,
> + struct mmd_context *context);
> +static void amdgpu_cs_vpe_blit(amdgpu_device_handle device_handle,
> + struct mmd_context *context);
> +
> +igt_main
Main is useally last one, then you don't need to declare called
functions.
Regards,
Kamil
> +{
> + struct mmd_context context = {};
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int r;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + igt_require(fd > 0);
> +
> + r = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(r == 0);
> +
> + igt_info("Initialized amdgpu, driver version %d.%d\n", major, minor);
> +
> + r = mmd_context_init(device, &context);
> + igt_require(r == 0);
> +
> + igt_skip_on(!is_vpe_tests_enabled(device, &context));
> + }
> +
> + igt_describe("Test VPE fence");
> + igt_subtest("vpe-fence-test")
> + amdgpu_cs_vpe_fence(device, &context);
> +
> + igt_describe("Test VPE blit");
> + igt_subtest("vpe-blit-test")
> + amdgpu_cs_vpe_blit(device, &context);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + drm_close_driver(fd);
> + }
> +
> +}
> +
> +static void amdgpu_cs_vpe_fence(amdgpu_device_handle device_handle,
> + struct mmd_context *context)
> +{
> + const uint32_t test_pattern = 0xdeadbeef;
> + uint32_t *ib_cpu = context->ib_cpu;
> + struct amdgpu_mmd_bo test_bo;
> + int r;
> +
> + context->num_resources = 0;
> + alloc_resource(device_handle, &test_bo, 4096, AMDGPU_GEM_DOMAIN_GTT);
> + context->resources[context->num_resources++] = test_bo.handle;
> +
> + r = amdgpu_bo_cpu_map(test_bo.handle, (void **)&test_bo.ptr);
> + igt_assert_eq(r, 0);
> +
> + memset(test_bo.ptr, 0, 4096);
> +
> + memset(ib_cpu, 0, IB_SIZE);
> +
> + ib_cpu[0] = 0x5;
> + ib_cpu[1] = 0xfffffffc & test_bo.addr;
> + ib_cpu[2] = (0xffffffff00000000 & test_bo.addr) >> 32;
> + ib_cpu[3] = test_pattern;
> + ib_cpu[4] = 0x0;
> + ib_cpu[5] = 0x0;
> + ib_cpu[6] = 0x0;
> + ib_cpu[7] = 0x0;
> +
> + context->resources[context->num_resources++] = context->ib_handle;
> +
> + r = submit(device_handle, context, 8, AMDGPU_HW_IP_VPE);
> + igt_assert_eq(r, 0);
> +
> + igt_assert_eq(((uint32_t *)test_bo.ptr)[0], test_pattern);
> +
> + r = amdgpu_bo_cpu_unmap(test_bo.handle);
> + igt_assert_eq(r, 0);
> +
> + free_resource(&test_bo);
> +}
> +
> +// a in byte 0, b in byte 1, g in byte 2, r in byte 3
> +static void create_rgba8888(void *addr, uint32_t width, uint32_t height)
> +{
> + uint32_t *ptr = (uint32_t *)addr;
> +
> + for (int i = 0; i < height; i++) {
> + for (int j = 0; j < width; j++)
> + ptr[j] = SRC_PLANE_PATTERN;
> + ptr += width;
> + }
> +}
> +// b in byte 0, g in byte 1, r in byte 2, a in byte 3
> +static int check_argb8888(void *addr, uint32_t width, uint32_t height)
> +{
> + uint32_t *ptr = (uint32_t *)addr;
> +
> + for (int i = 0; i < height; i++) {
> + for (int j = 0; j < width; j++)
> + if (ptr[j] != DST_PLANE_PATTERN)
> + return 1;
> + ptr += width;
> + }
> +
> + return 0;
> +}
> +
> +static void amdgpu_cs_vpe_blit(amdgpu_device_handle device_handle,
> + struct mmd_context *context)
> +{
> + const uint32_t vpep_config_offsets[] = {0x34, 0x128, 0x184, 0x1c0};
> + struct amdgpu_mmd_bo vpe_config_bo, src_plane_bo, dst_plane_bo;
> + int r;
> +
> + context->num_resources = 0;
> +
> + alloc_resource(device_handle, &vpe_config_bo, sizeof(vpe_config), AMDGPU_GEM_DOMAIN_GTT);
> + alloc_resource(device_handle, &src_plane_bo, PLANE_SIZE, AMDGPU_GEM_DOMAIN_GTT);
> + alloc_resource(device_handle, &dst_plane_bo, PLANE_SIZE, AMDGPU_GEM_DOMAIN_GTT);
> +
> + r = amdgpu_bo_cpu_map(vpe_config_bo.handle, (void **)&vpe_config_bo.ptr);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_cpu_map(src_plane_bo.handle, (void **)&src_plane_bo.ptr);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_cpu_map(dst_plane_bo.handle, (void **)&dst_plane_bo.ptr);
> + igt_assert_eq(r, 0);
> +
> + context->resources[context->num_resources++] = vpe_config_bo.handle;
> + context->resources[context->num_resources++] = src_plane_bo.handle;
> + context->resources[context->num_resources++] = dst_plane_bo.handle;
> +
> + // plane config gpu addr
> + *(uint64_t *)(vpe_descriptor + 1) = vpe_config_bo.addr;
> + // vpep config0 gpu addr
> + *(uint64_t *)(vpe_descriptor + 4) = vpe_config_bo.addr + vpep_config_offsets[0];
> + // vpep config1 gpu addr
> + *(uint64_t *)(vpe_descriptor + 6) = vpe_config_bo.addr + vpep_config_offsets[1];
> + // vpep config2 gpu addr
> + *(uint64_t *)(vpe_descriptor + 8) = vpe_config_bo.addr + vpep_config_offsets[2];
> + // vpep config3 gpu addr
> + *(uint64_t *)(vpe_descriptor + 10) = vpe_config_bo.addr + vpep_config_offsets[3];
> +
> + memset(src_plane_bo.ptr, 0, PLANE_SIZE);
> + memset(dst_plane_bo.ptr, 0, PLANE_SIZE);
> + create_rgba8888(src_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
> +
> + /* gpu address of src */
> + *(uint64_t *)(vpe_config + 2) = src_plane_bo.addr;
> + /* gpu address of dst */
> + *(uint64_t *)(vpe_config + 8) = dst_plane_bo.addr;
> +
> + memset(vpe_config_bo.ptr, 0, sizeof(vpe_config));
> + memcpy(vpe_config_bo.ptr, vpe_config, sizeof(vpe_config));
> +
> + memset(context->ib_cpu, 0, IB_SIZE);
> + memcpy(context->ib_cpu, vpe_descriptor, sizeof(vpe_descriptor));
> +
> + context->resources[context->num_resources++] = context->ib_handle;
> +
> + r = submit(device_handle, context, sizeof(vpe_descriptor)/4, AMDGPU_HW_IP_VPE);
> + igt_assert_eq(r, 0);
> +
> + r = check_argb8888(dst_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_cpu_unmap(vpe_config_bo.handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_cpu_unmap(src_plane_bo.handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_cpu_unmap(dst_plane_bo.handle);
> + igt_assert_eq(r, 0);
> +
> + free_resource(&vpe_config_bo);
> + free_resource(&src_plane_bo);
> + free_resource(&dst_plane_bo);
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index f52fc3645..e82e02701 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -36,6 +36,7 @@ if libdrm_amdgpu.found()
> 'amd_vrr_range',
> 'amd_mall',
> 'amd_odm',
> + 'amd_vpe',
> ]
> if libdrm_amdgpu.version().version_compare('> 2.4.97')
> amdgpu_progs +=[ 'amd_syncobj', ]
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [igt-dev] [PATCH 1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h
2023-11-09 11:08 ` [igt-dev] [PATCH 1/2] " Kamil Konieczny
@ 2023-11-10 2:45 ` Yu, Lang
0 siblings, 0 replies; 7+ messages in thread
From: Yu, Lang @ 2023-11-10 2:45 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev@lists.freedesktop.org; +Cc: Deucher, Alexander
[Public]
>-----Original Message-----
>From: Kamil Konieczny <kamil.konieczny@linux.intel.com>
>Sent: Thursday, November 9, 2023 7:09 PM
>To: igt-dev@lists.freedesktop.org
>Cc: Yu, Lang <Lang.Yu@amd.com>; Deucher, Alexander
><Alexander.Deucher@amd.com>
>Subject: Re: [igt-dev] [PATCH 1/2] include/drm-uapi/amdgpu_drm.h: update
>amdgpu_drm.h
>
>Hi Lang,
>On 2023-11-09 at 15:07:34 +0800, Lang Yu wrote:
>> Take from https://anongit.freedesktop.org/git/drm/drm.git.
>>
>> branch: drm-next
>> commit: 9ccde17d46554dbb2757c427f2cdf67688701f96
>>
>> Signed-off-by: Lang Yu <Lang.Yu@amd.com>
>
>This is already part of igt, see latest i-g-t
>commit: 63945e20f drm-uapi/amdgpu: sync with drm-next
>
>so you can safely drop first patch.
>Side note: please add i-g-t into subject, so it will look:
>
>[PATCH i-g-t 1/2] your_patch_subject_here
Thanks. Got it.
Regards,
Lang
>Regards,
>Kamil
>
>> ---
>> include/drm-uapi/amdgpu_drm.h | 50
>> ++++++++++++++++++++++++++---------
>> 1 file changed, 38 insertions(+), 12 deletions(-)
>>
>> diff --git a/include/drm-uapi/amdgpu_drm.h
>> b/include/drm-uapi/amdgpu_drm.h index f44e140ad..ad21c613f 100644
>> --- a/include/drm-uapi/amdgpu_drm.h
>> +++ b/include/drm-uapi/amdgpu_drm.h
>> @@ -94,6 +94,9 @@ extern "C" {
>> *
>> * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute
>engines
>> * for appending data.
>> + *
>> + * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region
>for
>> + * signalling user mode queues.
>> */
>> #define AMDGPU_GEM_DOMAIN_CPU 0x1
>> #define AMDGPU_GEM_DOMAIN_GTT 0x2
>> @@ -101,12 +104,14 @@ extern "C" {
>> #define AMDGPU_GEM_DOMAIN_GDS 0x8
>> #define AMDGPU_GEM_DOMAIN_GWS 0x10
>> #define AMDGPU_GEM_DOMAIN_OA 0x20
>> +#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
>> #define AMDGPU_GEM_DOMAIN_MASK
> (AMDGPU_GEM_DOMAIN_CPU | \
>> AMDGPU_GEM_DOMAIN_GTT | \
>> AMDGPU_GEM_DOMAIN_VRAM | \
>> AMDGPU_GEM_DOMAIN_GDS | \
>> AMDGPU_GEM_DOMAIN_GWS | \
>> - AMDGPU_GEM_DOMAIN_OA)
>> + AMDGPU_GEM_DOMAIN_OA | \
>> + AMDGPU_GEM_DOMAIN_DOORBELL)
>>
>> /* Flag that CPU access will be required for the case of VRAM domain */
>> #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
>> @@ -145,7 +150,7 @@ extern "C" {
>> */
>> #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
>> /* Flag that BO is shared coherently between multiple devices or CPU threads.
>> - * May depend on GPU instructions to flush caches explicitly
>> + * May depend on GPU instructions to flush caches to system scope explicitly.
>> *
>> * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
>> * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
>> @@ -158,6 +163,14 @@ extern "C" {
>> * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
>> */
>> #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
>> +/* Flag that BO should be coherent across devices when using
>> +device-level
>> + * atomics. May depend on GPU instructions to flush caches to device
>> +scope
>> + * explicitly, promoting them to system scope automatically.
>> + *
>> + * This influences the choice of MTYPE in the PTEs on GFXv9 and later
>> +GPUs and
>> + * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
>> + */
>> +#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
>>
>> struct drm_amdgpu_gem_create_in {
>> /** the requested memory size */
>> @@ -236,9 +249,9 @@ union drm_amdgpu_bo_list {
>> /* unknown cause */
>> #define AMDGPU_CTX_UNKNOWN_RESET 3
>>
>> -/* indicate gpu reset occured after ctx created */
>> +/* indicate gpu reset occurred after ctx created */
>> #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
>> -/* indicate vram lost occured after ctx created */
>> +/* indicate vram lost occurred after ctx created */
>> #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
>> /* indicate some job from this context once cause gpu hang */
>> #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
>> @@ -259,13 +272,6 @@ union drm_amdgpu_bo_list { */
>> #define AMDGPU_CTX_PRIORITY_HIGH 512
>> #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
>> -/* select a stable profiling pstate for perfmon tools */ -#define
>> AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf -#define
>> AMDGPU_CTX_STABLE_PSTATE_NONE 0 -#define
>> AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 -#define
>> AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 -#define
>> AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 -#define
>> AMDGPU_CTX_STABLE_PSTATE_PEAK 4
>>
>> /* select a stable profiling pstate for perfmon tools */ #define
>> AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf @@ -588,7 +594,8 @@ struct
>> drm_amdgpu_gem_va {
>> */
>> #define AMDGPU_HW_IP_VCN_ENC 7
>> #define AMDGPU_HW_IP_VCN_JPEG 8
>> -#define AMDGPU_HW_IP_NUM 9
>> +#define AMDGPU_HW_IP_VPE 9
>> +#define AMDGPU_HW_IP_NUM 10
>>
>> #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
>>
>> @@ -799,6 +806,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
>> #define AMDGPU_INFO_FW_MES 0x1a
>> /* Subquery id: Query IMU firmware version */
>> #define AMDGPU_INFO_FW_IMU 0x1b
>> + /* Subquery id: Query VPE firmware version */
>> + #define AMDGPU_INFO_FW_VPE 0x1c
>>
>> /* number of bytes moved for TTM migration */
>> #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
>> @@ -897,6 +906,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
>> #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
>> /* Query the max number of IBs per gang per submission */
>> #define AMDGPU_INFO_MAX_IBS 0x22
>> +/* query last page fault info */
>> +#define AMDGPU_INFO_GPUVM_FAULT 0x23
>>
>> #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
>> #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
>> @@ -1222,6 +1233,20 @@ struct drm_amdgpu_info_video_caps {
>> struct drm_amdgpu_info_video_codec_info
>> codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
>> };
>>
>> +#define AMDGPU_VMHUB_TYPE_MASK 0xff
>> +#define AMDGPU_VMHUB_TYPE_SHIFT 0
>> +#define AMDGPU_VMHUB_TYPE_GFX 0
>> +#define AMDGPU_VMHUB_TYPE_MM0 1
>> +#define AMDGPU_VMHUB_TYPE_MM1 2
>> +#define AMDGPU_VMHUB_IDX_MASK 0xff00
>> +#define AMDGPU_VMHUB_IDX_SHIFT 8
>> +
>> +struct drm_amdgpu_info_gpuvm_fault {
>> + __u64 addr;
>> + __u32 status;
>> + __u32 vmhub;
>> +};
>> +
>> /*
>> * Supported GPU families
>> */
>> @@ -1240,6 +1265,7 @@ struct drm_amdgpu_info_video_caps {
>> #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */
>> #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
>> #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
>> +#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC
>11.5.0 */
>>
>> #if defined(__cplusplus)
>> }
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [igt-dev] [PATCH 2/2] tests/amdgpu: add VPE tests
2023-11-09 11:13 ` Kamil Konieczny
@ 2023-11-10 2:46 ` Yu, Lang
0 siblings, 0 replies; 7+ messages in thread
From: Yu, Lang @ 2023-11-10 2:46 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev@lists.freedesktop.org; +Cc: Deucher, Alexander
[AMD Official Use Only - General]
>-----Original Message-----
>From: Kamil Konieczny <kamil.konieczny@linux.intel.com>
>Sent: Thursday, November 9, 2023 7:14 PM
>To: igt-dev@lists.freedesktop.org
>Cc: Yu, Lang <Lang.Yu@amd.com>; Deucher, Alexander
><Alexander.Deucher@amd.com>
>Subject: Re: [igt-dev] [PATCH 2/2] tests/amdgpu: add VPE tests
>
>Hi Lang,
>On 2023-11-09 at 15:07:35 +0800, Lang Yu wrote:
>> Add tests for Video Processing Engine, including fence and blit tests.
>>
>> Signed-off-by: Lang Yu <Lang.Yu@amd.com>
>> ---
>> lib/amdgpu/amd_mmd_shared.h | 5 +
>> tests/amdgpu/amd_vpe.c | 254 ++++++++++++++++++++++++++++++++++++
>> tests/amdgpu/meson.build | 1 +
>> 3 files changed, 260 insertions(+)
>> create mode 100644 tests/amdgpu/amd_vpe.c
>>
>> diff --git a/lib/amdgpu/amd_mmd_shared.h b/lib/amdgpu/amd_mmd_shared.h
>> index 82e732509..14f9ecb4d 100644
>> --- a/lib/amdgpu/amd_mmd_shared.h
>> +++ b/lib/amdgpu/amd_mmd_shared.h
>> @@ -54,6 +54,11 @@ struct mmd_context {
>> bool enc_ring;
>> /* jpeg */
>> bool jpeg_direct_reg;
>> +
>> + /*vpe*/
>> + uint32_t vpe_ip_version_major;
>> + uint32_t vpe_ip_version_minor;
>> + bool vpe_ring;
>> };
>>
>> struct amdgpu_mmd_bo {
>> diff --git a/tests/amdgpu/amd_vpe.c b/tests/amdgpu/amd_vpe.c new file
>> mode 100644 index 000000000..4aeb7395e
>> --- /dev/null
>> +++ b/tests/amdgpu/amd_vpe.c
>> @@ -0,0 +1,254 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright 2023 Advanced Micro Devices, Inc.
>> + */
>> +#include "igt.h"
>
>Put this after "amdgpu_drm.h" - first goes system includes, then igt ones, all in
>alphabetical order.
>
>> +
>> +#include <amdgpu.h>
>
>Put newline here.
>
>> +#include "amdgpu_drm.h"
>> +#include "lib/amdgpu/amd_mmd_shared.h"
>
>Put here global test description:
>
>IGT_TEST_DESCRIPTION("Your test description")
>
>> +
>> +#define IB_SIZE 4096
>> +#define MAX_RESOURCES 16
>> +
>> +#define PLANE_WIDTH 1024
>> +#define PLANE_HEIGHT 256
>> +#define PLANE_SIZE (PLANE_WIDTH*PLANE_HEIGHT*4)
>> +
>> +#define SRC_PLANE_PATTERN 0x12345678
>> +#define DST_PLANE_PATTERN 0xff123456
>> +
>> +static uint32_t vpe_descriptor[] = {
>> +0x00000001, 0x33002200, 0xff000021, 0x00000003, 0x33002234,
>> +0xff000021, 0x33002328, 0xff000021, 0x33002384, 0xff000021,
>> +0x330023c0, 0xff000021, };
>> +
>> +static uint32_t vpe_config[] = {
>> +0x00000002, 0x00000000, 0xbeefbe00, 0xff005678, 0x000003ff,
>> +0x00000000, 0x00ff43ff, 0x00000000, 0xbeefbe00, 0xff005679,
>> +0x000003ff, 0x00000000, 0x00ff43ff, 0x003b0003, 0x00047808,
>> +0x00000809, 0x0004780c, 0x000000e4, 0x00047d10, 0x00000009,
>> +0x00047d14, 0x00000101, 0x00047d18, 0x00000000, 0x00047d1c,
>> +0x00000000, 0x00047d20, 0x00000000, 0x00047d24, 0x0001f010,
>> +0x00047d28, 0x0001f010, 0x00047d2c, 0x0001f010, 0x00547ee9,
>> +0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000,
>> +0x00002000, 0x00047ee4, 0x00000001, 0x00047ee0, 0x00000000,
>> +0x00047f24, 0x00000000, 0x00047fc4, 0x00000000, 0x00547f05,
>> +0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000,
>> +0x00002000, 0x00047f00, 0x00000001, 0x00049700, 0x00000000,
>> +0x00049704, 0x0000000f, 0x00049f30, 0x00000000, 0x00049708,
>> +0x00000000, 0x0004970c, 0xffff0462, 0x0004a208, 0x00000000,
>> +0x0004971c, 0x00000000, 0x00047fc0, 0x0001f000, 0x00150003,
>> +0x00047df8, 0x00000001, 0x00047dfc, 0x00000001, 0x00047da8,
>> +0x00000006, 0x00047e18, 0x00000000, 0x0004970c, 0xffff0422,
>> +0x00049710, 0x0001f000, 0x00049714, 0x0001f000, 0x00049718,
>> +0x0001f000, 0x00049720, 0x00000000, 0x00049724, 0x00000000,
>> +0x00049728, 0x00000000, 0x000d0003, 0x00047810, 0x00000000,
>> +0x00047814, 0x01000400, 0x00047818, 0x00000000, 0x0004781c,
>> +0x01000400, 0x00047e00, 0x00000000, 0x00047e04, 0x01000400,
>> +0x00047e08, 0x01000400, 0x00280003, 0x00047820, 0x00000036,
>> +0x00047824, 0x0960f015, 0x0004972c, 0x00000014, 0x0004972c,
>> +0x00000014, 0x0004972c, 0x00000014, 0x00049f90, 0x00000000,
>> +0x00049f94, 0x00000001, 0x00549f99, 0x00002000, 0x00000000,
>> +0x20000000, 0x00000000, 0x00000000, 0x00002000, 0x00049850,
>> +0x00000000, 0x00049f34, 0x00000000, 0x00049f38, 0x02fff000,
>> +0x00049f3c, 0x00fff000, 0x00049f40, 0x00fff000, 0x0004aba0,
>> +0xffff0000, 0x0004aba0, 0xffff0000, 0x0004aacc, 0x00000000,
>> +0x0004aad4, 0x00000013, 0x0004aad4, 0x00000013, };
>> +
>> +static bool is_vpe_tests_enabled(amdgpu_device_handle device_handle,
>> + struct mmd_context *context) {
>> + struct drm_amdgpu_info_hw_ip info;
>> + int r;
>> +
>> + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VPE, 0,
>&info);
>> + igt_assert_eq(r, 0);
>> +
>> + context->vpe_ip_version_major = info.hw_ip_version_major;
>> + context->vpe_ip_version_minor = info.hw_ip_version_minor;
>> + context->vpe_ring = !!info.available_rings;
>> +
>> + if (!context->vpe_ring) {
>> + igt_info("VPE no available rings");
>> + igt_info("VPE fence test disable");
>> + igt_info("VPE blit test disable");
>> + }
>> +
>> + return true;
>> +}
>> +
>> +static void amdgpu_cs_vpe_fence(amdgpu_device_handle device_handle,
>> + struct mmd_context *context); static
>> +void amdgpu_cs_vpe_blit(amdgpu_device_handle device_handle,
>> + struct mmd_context *context);
>> +
>> +igt_main
>
>Main is useally last one, then you don't need to declare called functions.
Thanks, will send v2.
Regards,
Lang
>Regards,
>Kamil
>
>> +{
>> + struct mmd_context context = {};
>> + amdgpu_device_handle device;
>> + int fd = -1;
>> +
>> + igt_fixture {
>> + uint32_t major, minor;
>> + int r;
>> +
>> + fd = drm_open_driver(DRIVER_AMDGPU);
>> + igt_require(fd > 0);
>> +
>> + r = amdgpu_device_initialize(fd, &major, &minor, &device);
>> + igt_require(r == 0);
>> +
>> + igt_info("Initialized amdgpu, driver version %d.%d\n", major,
>> +minor);
>> +
>> + r = mmd_context_init(device, &context);
>> + igt_require(r == 0);
>> +
>> + igt_skip_on(!is_vpe_tests_enabled(device, &context));
>> + }
>> +
>> + igt_describe("Test VPE fence");
>> + igt_subtest("vpe-fence-test")
>> + amdgpu_cs_vpe_fence(device, &context);
>> +
>> + igt_describe("Test VPE blit");
>> + igt_subtest("vpe-blit-test")
>> + amdgpu_cs_vpe_blit(device, &context);
>> +
>> + igt_fixture {
>> + amdgpu_device_deinitialize(device);
>> + drm_close_driver(fd);
>> + }
>> +
>> +}
>> +
>> +static void amdgpu_cs_vpe_fence(amdgpu_device_handle device_handle,
>> + struct mmd_context *context) {
>> + const uint32_t test_pattern = 0xdeadbeef;
>> + uint32_t *ib_cpu = context->ib_cpu;
>> + struct amdgpu_mmd_bo test_bo;
>> + int r;
>> +
>> + context->num_resources = 0;
>> + alloc_resource(device_handle, &test_bo, 4096,
>AMDGPU_GEM_DOMAIN_GTT);
>> + context->resources[context->num_resources++] =
>> + test_bo.handle;
>> +
>> + r = amdgpu_bo_cpu_map(test_bo.handle, (void **)&test_bo.ptr);
>> + igt_assert_eq(r, 0);
>> +
>> + memset(test_bo.ptr, 0, 4096);
>> +
>> + memset(ib_cpu, 0, IB_SIZE);
>> +
>> + ib_cpu[0] = 0x5;
>> + ib_cpu[1] = 0xfffffffc & test_bo.addr;
>> + ib_cpu[2] = (0xffffffff00000000 & test_bo.addr) >> 32;
>> + ib_cpu[3] = test_pattern;
>> + ib_cpu[4] = 0x0;
>> + ib_cpu[5] = 0x0;
>> + ib_cpu[6] = 0x0;
>> + ib_cpu[7] = 0x0;
>> +
>> + context->resources[context->num_resources++] =
>> + context->ib_handle;
>> +
>> + r = submit(device_handle, context, 8, AMDGPU_HW_IP_VPE);
>> + igt_assert_eq(r, 0);
>> +
>> + igt_assert_eq(((uint32_t *)test_bo.ptr)[0], test_pattern);
>> +
>> + r = amdgpu_bo_cpu_unmap(test_bo.handle);
>> + igt_assert_eq(r, 0);
>> +
>> + free_resource(&test_bo);
>> +}
>> +
>> +// a in byte 0, b in byte 1, g in byte 2, r in byte 3 static void
>> +create_rgba8888(void *addr, uint32_t width, uint32_t height) {
>> + uint32_t *ptr = (uint32_t *)addr;
>> +
>> + for (int i = 0; i < height; i++) {
>> + for (int j = 0; j < width; j++)
>> + ptr[j] = SRC_PLANE_PATTERN;
>> + ptr += width;
>> + }
>> +}
>> +// b in byte 0, g in byte 1, r in byte 2, a in byte 3 static int
>> +check_argb8888(void *addr, uint32_t width, uint32_t height) {
>> + uint32_t *ptr = (uint32_t *)addr;
>> +
>> + for (int i = 0; i < height; i++) {
>> + for (int j = 0; j < width; j++)
>> + if (ptr[j] != DST_PLANE_PATTERN)
>> + return 1;
>> + ptr += width;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void amdgpu_cs_vpe_blit(amdgpu_device_handle device_handle,
>> + struct mmd_context *context) {
>> + const uint32_t vpep_config_offsets[] = {0x34, 0x128, 0x184, 0x1c0};
>> + struct amdgpu_mmd_bo vpe_config_bo, src_plane_bo, dst_plane_bo;
>> + int r;
>> +
>> + context->num_resources = 0;
>> +
>> + alloc_resource(device_handle, &vpe_config_bo, sizeof(vpe_config),
>AMDGPU_GEM_DOMAIN_GTT);
>> + alloc_resource(device_handle, &src_plane_bo, PLANE_SIZE,
>AMDGPU_GEM_DOMAIN_GTT);
>> + alloc_resource(device_handle, &dst_plane_bo, PLANE_SIZE,
>> + AMDGPU_GEM_DOMAIN_GTT);
>> +
>> + r = amdgpu_bo_cpu_map(vpe_config_bo.handle, (void
>**)&vpe_config_bo.ptr);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_cpu_map(src_plane_bo.handle, (void
>**)&src_plane_bo.ptr);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_cpu_map(dst_plane_bo.handle, (void
>**)&dst_plane_bo.ptr);
>> + igt_assert_eq(r, 0);
>> +
>> + context->resources[context->num_resources++] = vpe_config_bo.handle;
>> + context->resources[context->num_resources++] = src_plane_bo.handle;
>> + context->resources[context->num_resources++] =
>> + dst_plane_bo.handle;
>> +
>> + // plane config gpu addr
>> + *(uint64_t *)(vpe_descriptor + 1) = vpe_config_bo.addr;
>> + // vpep config0 gpu addr
>> + *(uint64_t *)(vpe_descriptor + 4) = vpe_config_bo.addr +
>vpep_config_offsets[0];
>> + // vpep config1 gpu addr
>> + *(uint64_t *)(vpe_descriptor + 6) = vpe_config_bo.addr +
>vpep_config_offsets[1];
>> + // vpep config2 gpu addr
>> + *(uint64_t *)(vpe_descriptor + 8) = vpe_config_bo.addr +
>vpep_config_offsets[2];
>> + // vpep config3 gpu addr
>> + *(uint64_t *)(vpe_descriptor + 10) = vpe_config_bo.addr +
>> + vpep_config_offsets[3];
>> +
>> + memset(src_plane_bo.ptr, 0, PLANE_SIZE);
>> + memset(dst_plane_bo.ptr, 0, PLANE_SIZE);
>> + create_rgba8888(src_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
>> +
>> + /* gpu address of src */
>> + *(uint64_t *)(vpe_config + 2) = src_plane_bo.addr;
>> + /* gpu address of dst */
>> + *(uint64_t *)(vpe_config + 8) = dst_plane_bo.addr;
>> +
>> + memset(vpe_config_bo.ptr, 0, sizeof(vpe_config));
>> + memcpy(vpe_config_bo.ptr, vpe_config, sizeof(vpe_config));
>> +
>> + memset(context->ib_cpu, 0, IB_SIZE);
>> + memcpy(context->ib_cpu, vpe_descriptor,
>> + sizeof(vpe_descriptor));
>> +
>> + context->resources[context->num_resources++] =
>> + context->ib_handle;
>> +
>> + r = submit(device_handle, context, sizeof(vpe_descriptor)/4,
>AMDGPU_HW_IP_VPE);
>> + igt_assert_eq(r, 0);
>> +
>> + r = check_argb8888(dst_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_cpu_unmap(vpe_config_bo.handle);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_cpu_unmap(src_plane_bo.handle);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_cpu_unmap(dst_plane_bo.handle);
>> + igt_assert_eq(r, 0);
>> +
>> + free_resource(&vpe_config_bo);
>> + free_resource(&src_plane_bo);
>> + free_resource(&dst_plane_bo); }
>> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build index
>> f52fc3645..e82e02701 100644
>> --- a/tests/amdgpu/meson.build
>> +++ b/tests/amdgpu/meson.build
>> @@ -36,6 +36,7 @@ if libdrm_amdgpu.found()
>> 'amd_vrr_range',
>> 'amd_mall',
>> 'amd_odm',
>> + 'amd_vpe',
>> ]
>> if libdrm_amdgpu.version().version_compare('> 2.4.97')
>> amdgpu_progs +=[ 'amd_syncobj', ]
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
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Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-09 7:07 [igt-dev] [PATCH 1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h Lang Yu
2023-11-09 7:07 ` [igt-dev] [PATCH 2/2] tests/amdgpu: add VPE tests Lang Yu
2023-11-09 11:13 ` Kamil Konieczny
2023-11-10 2:46 ` Yu, Lang
2023-11-09 8:24 ` [igt-dev] ✗ Fi.CI.BUILD: failure for series starting with [1/2] include/drm-uapi/amdgpu_drm.h: update amdgpu_drm.h Patchwork
2023-11-09 11:08 ` [igt-dev] [PATCH 1/2] " Kamil Konieczny
2023-11-10 2:45 ` Yu, Lang
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