* [igt-dev] [PATCH v2] tests/amdgpu: add VPE tests
@ 2023-11-10 2:53 Lang Yu
2023-11-10 3:35 ` [igt-dev] ✓ CI.xeBAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Lang Yu @ 2023-11-10 2:53 UTC (permalink / raw)
To: igt-dev; +Cc: Deucher Alexander, Lang Yu
Add tests for Video Processing Engine,
including fence and blit tests.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
lib/amdgpu/amd_mmd_shared.h | 5 +
tests/amdgpu/amd_vpe.c | 253 ++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
3 files changed, 259 insertions(+)
create mode 100644 tests/amdgpu/amd_vpe.c
diff --git a/lib/amdgpu/amd_mmd_shared.h b/lib/amdgpu/amd_mmd_shared.h
index 82e732509..14f9ecb4d 100644
--- a/lib/amdgpu/amd_mmd_shared.h
+++ b/lib/amdgpu/amd_mmd_shared.h
@@ -54,6 +54,11 @@ struct mmd_context {
bool enc_ring;
/* jpeg */
bool jpeg_direct_reg;
+
+ /*vpe*/
+ uint32_t vpe_ip_version_major;
+ uint32_t vpe_ip_version_minor;
+ bool vpe_ring;
};
struct amdgpu_mmd_bo {
diff --git a/tests/amdgpu/amd_vpe.c b/tests/amdgpu/amd_vpe.c
new file mode 100644
index 000000000..782f10915
--- /dev/null
+++ b/tests/amdgpu/amd_vpe.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <amdgpu.h>
+#include "amdgpu_drm.h"
+
+#include "igt.h"
+
+#include "lib/amdgpu/amd_mmd_shared.h"
+
+IGT_TEST_DESCRIPTION("Test VPE functionality");
+
+#define IB_SIZE 4096
+#define MAX_RESOURCES 16
+
+#define PLANE_WIDTH 1024
+#define PLANE_HEIGHT 256
+#define PLANE_SIZE (PLANE_WIDTH*PLANE_HEIGHT*4)
+
+#define SRC_PLANE_PATTERN 0x12345678
+#define DST_PLANE_PATTERN 0xff123456
+
+static uint32_t vpe_descriptor[] = {
+0x00000001, 0x33002200, 0xff000021, 0x00000003, 0x33002234, 0xff000021, 0x33002328, 0xff000021,
+0x33002384, 0xff000021, 0x330023c0, 0xff000021,
+};
+
+static uint32_t vpe_config[] = {
+0x00000002, 0x00000000, 0xbeefbe00, 0xff005678, 0x000003ff, 0x00000000, 0x00ff43ff, 0x00000000,
+0xbeefbe00, 0xff005679, 0x000003ff, 0x00000000, 0x00ff43ff, 0x003b0003, 0x00047808, 0x00000809,
+0x0004780c, 0x000000e4, 0x00047d10, 0x00000009, 0x00047d14, 0x00000101, 0x00047d18, 0x00000000,
+0x00047d1c, 0x00000000, 0x00047d20, 0x00000000, 0x00047d24, 0x0001f010, 0x00047d28, 0x0001f010,
+0x00047d2c, 0x0001f010, 0x00547ee9, 0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000,
+0x00002000, 0x00047ee4, 0x00000001, 0x00047ee0, 0x00000000, 0x00047f24, 0x00000000, 0x00047fc4,
+0x00000000, 0x00547f05, 0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00002000,
+0x00047f00, 0x00000001, 0x00049700, 0x00000000, 0x00049704, 0x0000000f, 0x00049f30, 0x00000000,
+0x00049708, 0x00000000, 0x0004970c, 0xffff0462, 0x0004a208, 0x00000000, 0x0004971c, 0x00000000,
+0x00047fc0, 0x0001f000, 0x00150003, 0x00047df8, 0x00000001, 0x00047dfc, 0x00000001, 0x00047da8,
+0x00000006, 0x00047e18, 0x00000000, 0x0004970c, 0xffff0422, 0x00049710, 0x0001f000, 0x00049714,
+0x0001f000, 0x00049718, 0x0001f000, 0x00049720, 0x00000000, 0x00049724, 0x00000000, 0x00049728,
+0x00000000, 0x000d0003, 0x00047810, 0x00000000, 0x00047814, 0x01000400, 0x00047818, 0x00000000,
+0x0004781c, 0x01000400, 0x00047e00, 0x00000000, 0x00047e04, 0x01000400, 0x00047e08, 0x01000400,
+0x00280003, 0x00047820, 0x00000036, 0x00047824, 0x0960f015, 0x0004972c, 0x00000014, 0x0004972c,
+0x00000014, 0x0004972c, 0x00000014, 0x00049f90, 0x00000000, 0x00049f94, 0x00000001, 0x00549f99,
+0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00002000, 0x00049850, 0x00000000,
+0x00049f34, 0x00000000, 0x00049f38, 0x02fff000, 0x00049f3c, 0x00fff000, 0x00049f40, 0x00fff000,
+0x0004aba0, 0xffff0000, 0x0004aba0, 0xffff0000, 0x0004aacc, 0x00000000, 0x0004aad4, 0x00000013,
+0x0004aad4, 0x00000013,
+};
+
+static bool is_vpe_tests_enabled(amdgpu_device_handle device_handle,
+ struct mmd_context *context)
+{
+ struct drm_amdgpu_info_hw_ip info;
+ int r;
+
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VPE, 0, &info);
+ igt_assert_eq(r, 0);
+
+ context->vpe_ip_version_major = info.hw_ip_version_major;
+ context->vpe_ip_version_minor = info.hw_ip_version_minor;
+ context->vpe_ring = !!info.available_rings;
+
+ if (!context->vpe_ring) {
+ igt_info("VPE no available rings");
+ igt_info("VPE fence test disable");
+ igt_info("VPE blit test disable");
+ }
+
+ return true;
+}
+
+static void amdgpu_cs_vpe_fence(amdgpu_device_handle device_handle,
+ struct mmd_context *context)
+{
+ const uint32_t test_pattern = 0xdeadbeef;
+ uint32_t *ib_cpu = context->ib_cpu;
+ struct amdgpu_mmd_bo test_bo;
+ int r;
+
+ context->num_resources = 0;
+ alloc_resource(device_handle, &test_bo, 4096, AMDGPU_GEM_DOMAIN_GTT);
+ context->resources[context->num_resources++] = test_bo.handle;
+
+ r = amdgpu_bo_cpu_map(test_bo.handle, (void **)&test_bo.ptr);
+ igt_assert_eq(r, 0);
+
+ memset(test_bo.ptr, 0, 4096);
+
+ memset(ib_cpu, 0, IB_SIZE);
+
+ ib_cpu[0] = 0x5;
+ ib_cpu[1] = 0xfffffffc & test_bo.addr;
+ ib_cpu[2] = (0xffffffff00000000 & test_bo.addr) >> 32;
+ ib_cpu[3] = test_pattern;
+ ib_cpu[4] = 0x0;
+ ib_cpu[5] = 0x0;
+ ib_cpu[6] = 0x0;
+ ib_cpu[7] = 0x0;
+
+ context->resources[context->num_resources++] = context->ib_handle;
+
+ r = submit(device_handle, context, 8, AMDGPU_HW_IP_VPE);
+ igt_assert_eq(r, 0);
+
+ igt_assert_eq(((uint32_t *)test_bo.ptr)[0], test_pattern);
+
+ r = amdgpu_bo_cpu_unmap(test_bo.handle);
+ igt_assert_eq(r, 0);
+
+ free_resource(&test_bo);
+}
+
+// a in byte 0, b in byte 1, g in byte 2, r in byte 3
+static void create_rgba8888(void *addr, uint32_t width, uint32_t height)
+{
+ uint32_t *ptr = (uint32_t *)addr;
+
+ for (int i = 0; i < height; i++) {
+ for (int j = 0; j < width; j++)
+ ptr[j] = SRC_PLANE_PATTERN;
+ ptr += width;
+ }
+}
+// b in byte 0, g in byte 1, r in byte 2, a in byte 3
+static int check_argb8888(void *addr, uint32_t width, uint32_t height)
+{
+ uint32_t *ptr = (uint32_t *)addr;
+
+ for (int i = 0; i < height; i++) {
+ for (int j = 0; j < width; j++)
+ if (ptr[j] != DST_PLANE_PATTERN)
+ return 1;
+ ptr += width;
+ }
+
+ return 0;
+}
+
+static void amdgpu_cs_vpe_blit(amdgpu_device_handle device_handle,
+ struct mmd_context *context)
+{
+ const uint32_t vpep_config_offsets[] = {0x34, 0x128, 0x184, 0x1c0};
+ struct amdgpu_mmd_bo vpe_config_bo, src_plane_bo, dst_plane_bo;
+ int r;
+
+ context->num_resources = 0;
+
+ alloc_resource(device_handle, &vpe_config_bo, sizeof(vpe_config), AMDGPU_GEM_DOMAIN_GTT);
+ alloc_resource(device_handle, &src_plane_bo, PLANE_SIZE, AMDGPU_GEM_DOMAIN_GTT);
+ alloc_resource(device_handle, &dst_plane_bo, PLANE_SIZE, AMDGPU_GEM_DOMAIN_GTT);
+
+ r = amdgpu_bo_cpu_map(vpe_config_bo.handle, (void **)&vpe_config_bo.ptr);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_cpu_map(src_plane_bo.handle, (void **)&src_plane_bo.ptr);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_cpu_map(dst_plane_bo.handle, (void **)&dst_plane_bo.ptr);
+ igt_assert_eq(r, 0);
+
+ context->resources[context->num_resources++] = vpe_config_bo.handle;
+ context->resources[context->num_resources++] = src_plane_bo.handle;
+ context->resources[context->num_resources++] = dst_plane_bo.handle;
+
+ // plane config gpu addr
+ *(uint64_t *)(vpe_descriptor + 1) = vpe_config_bo.addr;
+ // vpep config0 gpu addr
+ *(uint64_t *)(vpe_descriptor + 4) = vpe_config_bo.addr + vpep_config_offsets[0];
+ // vpep config1 gpu addr
+ *(uint64_t *)(vpe_descriptor + 6) = vpe_config_bo.addr + vpep_config_offsets[1];
+ // vpep config2 gpu addr
+ *(uint64_t *)(vpe_descriptor + 8) = vpe_config_bo.addr + vpep_config_offsets[2];
+ // vpep config3 gpu addr
+ *(uint64_t *)(vpe_descriptor + 10) = vpe_config_bo.addr + vpep_config_offsets[3];
+
+ memset(src_plane_bo.ptr, 0, PLANE_SIZE);
+ memset(dst_plane_bo.ptr, 0, PLANE_SIZE);
+ create_rgba8888(src_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
+
+ /* gpu address of src */
+ *(uint64_t *)(vpe_config + 2) = src_plane_bo.addr;
+ /* gpu address of dst */
+ *(uint64_t *)(vpe_config + 8) = dst_plane_bo.addr;
+
+ memset(vpe_config_bo.ptr, 0, sizeof(vpe_config));
+ memcpy(vpe_config_bo.ptr, vpe_config, sizeof(vpe_config));
+
+ memset(context->ib_cpu, 0, IB_SIZE);
+ memcpy(context->ib_cpu, vpe_descriptor, sizeof(vpe_descriptor));
+
+ context->resources[context->num_resources++] = context->ib_handle;
+
+ r = submit(device_handle, context, sizeof(vpe_descriptor)/4, AMDGPU_HW_IP_VPE);
+ igt_assert_eq(r, 0);
+
+ r = check_argb8888(dst_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_cpu_unmap(vpe_config_bo.handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_cpu_unmap(src_plane_bo.handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_cpu_unmap(dst_plane_bo.handle);
+ igt_assert_eq(r, 0);
+
+ free_resource(&vpe_config_bo);
+ free_resource(&src_plane_bo);
+ free_resource(&dst_plane_bo);
+}
+
+igt_main
+{
+ struct mmd_context context = {};
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int r;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ igt_require(fd > 0);
+
+ r = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(r == 0);
+
+ igt_info("Initialized amdgpu, driver version %d.%d\n", major, minor);
+
+ r = mmd_context_init(device, &context);
+ igt_require(r == 0);
+
+ igt_skip_on(!is_vpe_tests_enabled(device, &context));
+ }
+
+ igt_describe("Test VPE fence");
+ igt_subtest("vpe-fence-test")
+ amdgpu_cs_vpe_fence(device, &context);
+
+ igt_describe("Test VPE blit");
+ igt_subtest("vpe-blit-test")
+ amdgpu_cs_vpe_blit(device, &context);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ drm_close_driver(fd);
+ }
+
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index efd911fab..bbb8edc93 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,7 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
'amd_subvp',
+ 'amd_vpe',
]
if libdrm_amdgpu.version().version_compare('> 2.4.97')
amdgpu_progs +=[ 'amd_syncobj', ]
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [igt-dev] ✓ CI.xeBAT: success for tests/amdgpu: add VPE tests
2023-11-10 2:53 [igt-dev] [PATCH v2] tests/amdgpu: add VPE tests Lang Yu
@ 2023-11-10 3:35 ` Patchwork
2023-11-10 3:50 ` [igt-dev] ✗ Fi.CI.BAT: failure " Patchwork
2023-11-12 22:37 ` [igt-dev] [PATCH v2] " vitaly prosyak
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2023-11-10 3:35 UTC (permalink / raw)
To: Lang Yu; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 9904 bytes --]
== Series Details ==
Series: tests/amdgpu: add VPE tests
URL : https://patchwork.freedesktop.org/series/126237/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7581_BAT -> XEIGTPW_10155_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (0 -> 3)
------------------------------
Additional (3): bat-dg2-oem2 bat-adlp-7 bat-atsm-2
Known issues
------------
Here are the changes found in XEIGTPW_10155_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-oem2: NOTRUN -> [SKIP][1] ([Intel XE#623])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-oem2: NOTRUN -> [SKIP][2] ([Intel XE#624])
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@invalid-set-prop-any:
- bat-atsm-2: NOTRUN -> [SKIP][3] ([i915#6077]) +33 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@kms_addfb_basic@invalid-set-prop-any.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-oem2: NOTRUN -> [FAIL][4] ([Intel XE#609]) +1 other test fail
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@kms_addfb_basic@tile-pitch-mismatch.html
- bat-adlp-7: NOTRUN -> [FAIL][5] ([Intel XE#609]) +2 other tests fail
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-adlp-7/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- bat-atsm-2: NOTRUN -> [SKIP][6] ([Intel XE#782]) +5 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- bat-dg2-oem2: NOTRUN -> [FAIL][7] ([i915#2346])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- bat-atsm-2: NOTRUN -> [SKIP][8] ([Intel XE#784])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@kms_dsc@dsc-basic.html
- bat-dg2-oem2: NOTRUN -> [SKIP][9] ([Intel XE#423])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@kms_dsc@dsc-basic.html
- bat-adlp-7: NOTRUN -> [SKIP][10] ([Intel XE#423])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-adlp-7/igt@kms_dsc@dsc-basic.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-atsm-2: NOTRUN -> [SKIP][11] ([Intel XE#541]) +3 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-oem2: NOTRUN -> [SKIP][12] ([i915#5274])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-dg2-oem2: NOTRUN -> [FAIL][13] ([Intel XE#608])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@kms_frontbuffer_tracking@basic.html
- bat-adlp-7: NOTRUN -> [FAIL][14] ([Intel XE#616] / [Intel XE#750])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
- bat-atsm-2: NOTRUN -> [SKIP][15] ([Intel XE#783])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_hdmi_inject@inject-audio:
- bat-atsm-2: NOTRUN -> [SKIP][16] ([Intel XE#540]) +3 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-dp-3:
- bat-dg2-oem2: NOTRUN -> [FAIL][17] ([Intel XE#400] / [Intel XE#616]) +2 other tests fail
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-dp-3.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
- bat-atsm-2: NOTRUN -> [SKIP][18] ([i915#1836]) +6 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html
* igt@kms_prop_blob@basic:
- bat-atsm-2: NOTRUN -> [SKIP][19] ([Intel XE#780])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@kms_prop_blob@basic.html
* igt@kms_psr@primary_page_flip:
- bat-dg2-oem2: NOTRUN -> [SKIP][20] ([Intel XE#535]) +2 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@sprite_plane_onoff:
- bat-atsm-2: NOTRUN -> [SKIP][21] ([Intel XE#535]) +2 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@kms_psr@sprite_plane_onoff.html
* igt@xe_compute@compute-square:
- bat-atsm-2: NOTRUN -> [SKIP][22] ([Intel XE#672])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@xe_compute@compute-square.html
- bat-dg2-oem2: NOTRUN -> [SKIP][23] ([Intel XE#672])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@xe_compute@compute-square.html
* igt@xe_evict@evict-beng-small-external:
- bat-adlp-7: NOTRUN -> [SKIP][24] ([Intel XE#261] / [Intel XE#688]) +15 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-adlp-7/igt@xe_evict@evict-beng-small-external.html
* igt@xe_exec_fault_mode@many-basic:
- bat-dg2-oem2: NOTRUN -> [SKIP][25] ([Intel XE#288]) +17 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@xe_exec_fault_mode@many-basic.html
* igt@xe_exec_fault_mode@twice-userptr-invalidate:
- bat-adlp-7: NOTRUN -> [SKIP][26] ([Intel XE#288]) +17 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-adlp-7/igt@xe_exec_fault_mode@twice-userptr-invalidate.html
* igt@xe_exec_fault_mode@twice-userptr-invalidate-imm:
- bat-atsm-2: NOTRUN -> [SKIP][27] ([Intel XE#288]) +17 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@xe_exec_fault_mode@twice-userptr-invalidate-imm.html
* igt@xe_huc_copy@huc_copy:
- bat-atsm-2: NOTRUN -> [SKIP][28] ([Intel XE#255])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-atsm-2/igt@xe_huc_copy@huc_copy.html
- bat-dg2-oem2: NOTRUN -> [SKIP][29] ([Intel XE#255])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-dg2-oem2/igt@xe_huc_copy@huc_copy.html
* igt@xe_mmap@vram:
- bat-adlp-7: NOTRUN -> [SKIP][30] ([Intel XE#263])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/bat-adlp-7/igt@xe_mmap@vram.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#263]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/263
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/400
[Intel XE#423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/423
[Intel XE#524]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/524
[Intel XE#535]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/535
[Intel XE#540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/540
[Intel XE#541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/541
[Intel XE#608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/608
[Intel XE#609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/609
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#623]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/623
[Intel XE#624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/624
[Intel XE#672]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/672
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#750]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/750
[Intel XE#780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/780
[Intel XE#782]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/782
[Intel XE#783]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/783
[Intel XE#784]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/784
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
Build changes
-------------
* IGT: IGT_7581 -> IGTPW_10155
* Linux: xe-484-b11007e91f8785a96903d9d3c3d1efbe7e969eaf -> xe-485-b3890fb4386dcef68a96888141c4cc773f6241ce
IGTPW_10155: 10155
IGT_7581: 7581
xe-484-b11007e91f8785a96903d9d3c3d1efbe7e969eaf: b11007e91f8785a96903d9d3c3d1efbe7e969eaf
xe-485-b3890fb4386dcef68a96888141c4cc773f6241ce: b3890fb4386dcef68a96888141c4cc773f6241ce
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10155/index.html
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [igt-dev] ✗ Fi.CI.BAT: failure for tests/amdgpu: add VPE tests
2023-11-10 2:53 [igt-dev] [PATCH v2] tests/amdgpu: add VPE tests Lang Yu
2023-11-10 3:35 ` [igt-dev] ✓ CI.xeBAT: success for " Patchwork
@ 2023-11-10 3:50 ` Patchwork
2023-11-12 22:37 ` [igt-dev] [PATCH v2] " vitaly prosyak
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2023-11-10 3:50 UTC (permalink / raw)
To: Lang Yu; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 9034 bytes --]
== Series Details ==
Series: tests/amdgpu: add VPE tests
URL : https://patchwork.freedesktop.org/series/126237/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13859 -> IGTPW_10155
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_10155 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_10155, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/index.html
Participating hosts (33 -> 34)
------------------------------
Additional (1): bat-dg2-9
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_10155:
### IGT changes ###
#### Possible regressions ####
* igt@kms_psr@sprite_plane_onoff:
- bat-jsl-3: [PASS][1] -> [SKIP][2] +3 other tests skip
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13859/bat-jsl-3/igt@kms_psr@sprite_plane_onoff.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-jsl-3/igt@kms_psr@sprite_plane_onoff.html
Known issues
------------
Here are the changes found in IGTPW_10155 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3: [PASS][3] -> [INCOMPLETE][4] ([i915#9275])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13859/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_mmap@basic:
- bat-dg2-9: NOTRUN -> [SKIP][5] ([i915#4083])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-9: NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@gem_mmap_gtt@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-9: NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@gem_render_tiled_blits@basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-9: NOTRUN -> [SKIP][8] ([i915#6621])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][9] -> [DMESG-FAIL][10] ([i915#5334] / [i915#7872])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13859/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3: [PASS][11] -> [FAIL][12] ([fdo#103375])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13859/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][13] ([i915#5190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][14] ([i915#4215] / [i915#5190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9: NOTRUN -> [SKIP][15] ([i915#4212]) +6 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9: NOTRUN -> [SKIP][16] ([i915#4212] / [i915#5608])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9: NOTRUN -> [SKIP][18] ([fdo#109285])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9: NOTRUN -> [SKIP][19] ([i915#5274])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg2-9: NOTRUN -> [SKIP][20] ([i915#1072]) +3 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-9: NOTRUN -> [SKIP][21] ([i915#3555] / [i915#4098])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-9: NOTRUN -> [SKIP][22] ([i915#3708])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-9: NOTRUN -> [SKIP][23] ([i915#3708] / [i915#4077]) +1 other test skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- bat-dg2-9: NOTRUN -> [SKIP][24] ([i915#3291] / [i915#3708]) +2 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-9/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [DMESG-FAIL][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13859/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [ABORT][27] ([i915#8668]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13859/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7581 -> IGTPW_10155
CI-20190529: 20190529
CI_DRM_13859: 9155ae0ae05f320d84eaf2c4e81413bf937a5f3c @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_10155: 10155
IGT_7581: 7581
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10155/index.html
[-- Attachment #2: Type: text/html, Size: 10530 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [igt-dev] [PATCH v2] tests/amdgpu: add VPE tests
2023-11-10 2:53 [igt-dev] [PATCH v2] tests/amdgpu: add VPE tests Lang Yu
2023-11-10 3:35 ` [igt-dev] ✓ CI.xeBAT: success for " Patchwork
2023-11-10 3:50 ` [igt-dev] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-11-12 22:37 ` vitaly prosyak
2023-11-13 2:47 ` Yu, Lang
2 siblings, 1 reply; 6+ messages in thread
From: vitaly prosyak @ 2023-11-12 22:37 UTC (permalink / raw)
To: Lang Yu, igt-dev; +Cc: Deucher Alexander, Liu, Leo
Added Leo.
Hi Lang,
Please, use the checkpatch.pl and fix formatting errors, for example,
vprosyak@desktop-host:~/src/igt-gpu-tools$ ../linux/scripts/checkpatch.pl -f --no-tree /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c
ERROR: code indent should use tabs where possible
#54: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:54:
+ struct mmd_context *context)$
WARNING: please, no spaces at the start of a line
#54: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:54:
+ struct mmd_context *context)$
ERROR: code indent should use tabs where possible
#56: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:56:
+ struct drm_amdgpu_info_hw_ip info;$
WARNING: please, no spaces at the start of a line
#56: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:56:
+ struct drm_amdgpu_info_hw_ip info;$
ERROR: code indent should use tabs where possible
#57: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:57:
+ int r;$
WARNING: please, no spaces at the start of a line
#57: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:57:
+ int r;$
ERROR: code indent should use tabs where possible
#59: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:59:
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VPE, 0, &info);$
Please, see inline below.
Thanks, Vitaly
On 2023-11-09 21:53, Lang Yu wrote:
> Add tests for Video Processing Engine,
> including fence and blit tests.
>
> Signed-off-by: Lang Yu <Lang.Yu@amd.com>
> ---
> lib/amdgpu/amd_mmd_shared.h | 5 +
> tests/amdgpu/amd_vpe.c | 253 ++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 3 files changed, 259 insertions(+)
> create mode 100644 tests/amdgpu/amd_vpe.c
>
> diff --git a/lib/amdgpu/amd_mmd_shared.h b/lib/amdgpu/amd_mmd_shared.h
> index 82e732509..14f9ecb4d 100644
> --- a/lib/amdgpu/amd_mmd_shared.h
> +++ b/lib/amdgpu/amd_mmd_shared.h
> @@ -54,6 +54,11 @@ struct mmd_context {
> bool enc_ring;
> /* jpeg */
> bool jpeg_direct_reg;
> +
> + /*vpe*/
> + uint32_t vpe_ip_version_major;
> + uint32_t vpe_ip_version_minor;
> + bool vpe_ring;
> };
>
> struct amdgpu_mmd_bo {
> diff --git a/tests/amdgpu/amd_vpe.c b/tests/amdgpu/amd_vpe.c
> new file mode 100644
> index 000000000..782f10915
> --- /dev/null
> +++ b/tests/amdgpu/amd_vpe.c
> @@ -0,0 +1,253 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <amdgpu.h>
> +#include "amdgpu_drm.h"
> +
> +#include "igt.h"
> +
> +#include "lib/amdgpu/amd_mmd_shared.h"
> +
> +IGT_TEST_DESCRIPTION("Test VPE functionality");
> +
> +#define IB_SIZE 4096
> +#define MAX_RESOURCES 16
> +
> +#define PLANE_WIDTH 1024
> +#define PLANE_HEIGHT 256
> +#define PLANE_SIZE (PLANE_WIDTH*PLANE_HEIGHT*4)
> +
> +#define SRC_PLANE_PATTERN 0x12345678
> +#define DST_PLANE_PATTERN 0xff123456
Please, use the shared header for such definitions as we did for example into 'AMD_MMD_VCE_IB_H"
unless you are sure that these definitions will be not used in the future for other tests.
> +
> +static uint32_t vpe_descriptor[] = {
> +0x00000001, 0x33002200, 0xff000021, 0x00000003, 0x33002234, 0xff000021, 0x33002328, 0xff000021,
> +0x33002384, 0xff000021, 0x330023c0, 0xff000021,
> +};
> +
> +static uint32_t vpe_config[] = {
> +0x00000002, 0x00000000, 0xbeefbe00, 0xff005678, 0x000003ff, 0x00000000, 0x00ff43ff, 0x00000000,
> +0xbeefbe00, 0xff005679, 0x000003ff, 0x00000000, 0x00ff43ff, 0x003b0003, 0x00047808, 0x00000809,
> +0x0004780c, 0x000000e4, 0x00047d10, 0x00000009, 0x00047d14, 0x00000101, 0x00047d18, 0x00000000,
> +0x00047d1c, 0x00000000, 0x00047d20, 0x00000000, 0x00047d24, 0x0001f010, 0x00047d28, 0x0001f010,
> +0x00047d2c, 0x0001f010, 0x00547ee9, 0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000,
> +0x00002000, 0x00047ee4, 0x00000001, 0x00047ee0, 0x00000000, 0x00047f24, 0x00000000, 0x00047fc4,
> +0x00000000, 0x00547f05, 0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00002000,
> +0x00047f00, 0x00000001, 0x00049700, 0x00000000, 0x00049704, 0x0000000f, 0x00049f30, 0x00000000,
> +0x00049708, 0x00000000, 0x0004970c, 0xffff0462, 0x0004a208, 0x00000000, 0x0004971c, 0x00000000,
> +0x00047fc0, 0x0001f000, 0x00150003, 0x00047df8, 0x00000001, 0x00047dfc, 0x00000001, 0x00047da8,
> +0x00000006, 0x00047e18, 0x00000000, 0x0004970c, 0xffff0422, 0x00049710, 0x0001f000, 0x00049714,
> +0x0001f000, 0x00049718, 0x0001f000, 0x00049720, 0x00000000, 0x00049724, 0x00000000, 0x00049728,
> +0x00000000, 0x000d0003, 0x00047810, 0x00000000, 0x00047814, 0x01000400, 0x00047818, 0x00000000,
> +0x0004781c, 0x01000400, 0x00047e00, 0x00000000, 0x00047e04, 0x01000400, 0x00047e08, 0x01000400,
> +0x00280003, 0x00047820, 0x00000036, 0x00047824, 0x0960f015, 0x0004972c, 0x00000014, 0x0004972c,
> +0x00000014, 0x0004972c, 0x00000014, 0x00049f90, 0x00000000, 0x00049f94, 0x00000001, 0x00549f99,
> +0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00002000, 0x00049850, 0x00000000,
> +0x00049f34, 0x00000000, 0x00049f38, 0x02fff000, 0x00049f3c, 0x00fff000, 0x00049f40, 0x00fff000,
> +0x0004aba0, 0xffff0000, 0x0004aba0, 0xffff0000, 0x0004aacc, 0x00000000, 0x0004aad4, 0x00000013,
> +0x0004aad4, 0x00000013,
> +};
> +
> +static bool is_vpe_tests_enabled(amdgpu_device_handle device_handle,
> + struct mmd_context *context)
> +{
> + struct drm_amdgpu_info_hw_ip info;
> + int r;
> +
> + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VPE, 0, &info);
> + igt_assert_eq(r, 0);
> +
> + context->vpe_ip_version_major = info.hw_ip_version_major;
> + context->vpe_ip_version_minor = info.hw_ip_version_minor;
> + context->vpe_ring = !!info.available_rings;
> +
> + if (!context->vpe_ring) {
> + igt_info("VPE no available rings");
> + igt_info("VPE fence test disable");
> + igt_info("VPE blit test disable");
> + }
> +
Please, fix return from this function
> + return true;
> +}
> +
> +static void amdgpu_cs_vpe_fence(amdgpu_device_handle device_handle,
> + struct mmd_context *context)
> +{
> + const uint32_t test_pattern = 0xdeadbeef;
> + uint32_t *ib_cpu = context->ib_cpu;
> + struct amdgpu_mmd_bo test_bo;
> + int r;
> +
> + context->num_resources = 0;
> + alloc_resource(device_handle, &test_bo, 4096, AMDGPU_GEM_DOMAIN_GTT);
> + context->resources[context->num_resources++] = test_bo.handle;
> +
> + r = amdgpu_bo_cpu_map(test_bo.handle, (void **)&test_bo.ptr);
> + igt_assert_eq(r, 0);
> +
> + memset(test_bo.ptr, 0, 4096);
> +
> + memset(ib_cpu, 0, IB_SIZE);
> +
> + ib_cpu[0] = 0x5;
Please, use macro lower_32_bits & upper_32_bits, as we are using, for example,
ring_context->pm4[i++] = lower_32_bits(ring_context->bo_mc);
ring_context->pm4[i++] = upper_32_bits(ring_context->bo_mc);
> + ib_cpu[1] = 0xfffffffc & test_bo.addr;
> + ib_cpu[2] = (0xffffffff00000000 & test_bo.addr) >> 32;
> + ib_cpu[3] = test_pattern;
> + ib_cpu[4] = 0x0;
> + ib_cpu[5] = 0x0;
> + ib_cpu[6] = 0x0;
> + ib_cpu[7] = 0x0;
> +
> + context->resources[context->num_resources++] = context->ib_handle;
> +
> + r = submit(device_handle, context, 8, AMDGPU_HW_IP_VPE);
> + igt_assert_eq(r, 0);
> +
> + igt_assert_eq(((uint32_t *)test_bo.ptr)[0], test_pattern);
> +
> + r = amdgpu_bo_cpu_unmap(test_bo.handle);
> + igt_assert_eq(r, 0);
> +
> + free_resource(&test_bo);
> +}
> +
> +// a in byte 0, b in byte 1, g in byte 2, r in byte 3
> +static void create_rgba8888(void *addr, uint32_t width, uint32_t height)
> +{
> + uint32_t *ptr = (uint32_t *)addr;
> +
> + for (int i = 0; i < height; i++) {
> + for (int j = 0; j < width; j++)
> + ptr[j] = SRC_PLANE_PATTERN;
> + ptr += width;
> + }
> +}
> +// b in byte 0, g in byte 1, r in byte 2, a in byte 3
> +static int check_argb8888(void *addr, uint32_t width, uint32_t height)
> +{
> + uint32_t *ptr = (uint32_t *)addr;
> +
> + for (int i = 0; i < height; i++) {
> + for (int j = 0; j < width; j++)
> + if (ptr[j] != DST_PLANE_PATTERN)
> + return 1;
> + ptr += width;
> + }
> +
> + return 0;
> +}
> +
> +static void amdgpu_cs_vpe_blit(amdgpu_device_handle device_handle,
> + struct mmd_context *context)
> +{
> + const uint32_t vpep_config_offsets[] = {0x34, 0x128, 0x184, 0x1c0};
> + struct amdgpu_mmd_bo vpe_config_bo, src_plane_bo, dst_plane_bo;
> + int r;
> +
> + context->num_resources = 0;
> +
> + alloc_resource(device_handle, &vpe_config_bo, sizeof(vpe_config), AMDGPU_GEM_DOMAIN_GTT);
> + alloc_resource(device_handle, &src_plane_bo, PLANE_SIZE, AMDGPU_GEM_DOMAIN_GTT);
> + alloc_resource(device_handle, &dst_plane_bo, PLANE_SIZE, AMDGPU_GEM_DOMAIN_GTT);
> +
> + r = amdgpu_bo_cpu_map(vpe_config_bo.handle, (void **)&vpe_config_bo.ptr);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_cpu_map(src_plane_bo.handle, (void **)&src_plane_bo.ptr);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_cpu_map(dst_plane_bo.handle, (void **)&dst_plane_bo.ptr);
> + igt_assert_eq(r, 0);
> +
> + context->resources[context->num_resources++] = vpe_config_bo.handle;
> + context->resources[context->num_resources++] = src_plane_bo.handle;
> + context->resources[context->num_resources++] = dst_plane_bo.handle;
> +
> + // plane config gpu addr
> + *(uint64_t *)(vpe_descriptor + 1) = vpe_config_bo.addr;
> + // vpep config0 gpu addr
> + *(uint64_t *)(vpe_descriptor + 4) = vpe_config_bo.addr + vpep_config_offsets[0];
> + // vpep config1 gpu addr
> + *(uint64_t *)(vpe_descriptor + 6) = vpe_config_bo.addr + vpep_config_offsets[1];
> + // vpep config2 gpu addr
> + *(uint64_t *)(vpe_descriptor + 8) = vpe_config_bo.addr + vpep_config_offsets[2];
> + // vpep config3 gpu addr
> + *(uint64_t *)(vpe_descriptor + 10) = vpe_config_bo.addr + vpep_config_offsets[3];
> +
> + memset(src_plane_bo.ptr, 0, PLANE_SIZE);
> + memset(dst_plane_bo.ptr, 0, PLANE_SIZE);
> + create_rgba8888(src_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
> +
> + /* gpu address of src */
> + *(uint64_t *)(vpe_config + 2) = src_plane_bo.addr;
> + /* gpu address of dst */
> + *(uint64_t *)(vpe_config + 8) = dst_plane_bo.addr;
> +
> + memset(vpe_config_bo.ptr, 0, sizeof(vpe_config));
> + memcpy(vpe_config_bo.ptr, vpe_config, sizeof(vpe_config));
> +
> + memset(context->ib_cpu, 0, IB_SIZE);
> + memcpy(context->ib_cpu, vpe_descriptor, sizeof(vpe_descriptor));
> +
> + context->resources[context->num_resources++] = context->ib_handle;
> +
> + r = submit(device_handle, context, sizeof(vpe_descriptor)/4, AMDGPU_HW_IP_VPE);
> + igt_assert_eq(r, 0);
> +
> + r = check_argb8888(dst_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_cpu_unmap(vpe_config_bo.handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_cpu_unmap(src_plane_bo.handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_cpu_unmap(dst_plane_bo.handle);
> + igt_assert_eq(r, 0);
> +
> + free_resource(&vpe_config_bo);
> + free_resource(&src_plane_bo);
> + free_resource(&dst_plane_bo);
> +}
> +
> +igt_main
> +{
> + struct mmd_context context = {};
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int r;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + igt_require(fd > 0);
> +
> + r = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(r == 0);
> +
> + igt_info("Initialized amdgpu, driver version %d.%d\n", major, minor);
> +
> + r = mmd_context_init(device, &context);
> + igt_require(r == 0);
> +
> + igt_skip_on(!is_vpe_tests_enabled(device, &context));
> + }
> +
> + igt_describe("Test VPE fence");
> + igt_subtest("vpe-fence-test")
> + amdgpu_cs_vpe_fence(device, &context);
> +
> + igt_describe("Test VPE blit");
> + igt_subtest("vpe-blit-test")
> + amdgpu_cs_vpe_blit(device, &context);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + drm_close_driver(fd);
> + }
> +
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index efd911fab..bbb8edc93 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,7 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> 'amd_subvp',
> + 'amd_vpe',
> ]
> if libdrm_amdgpu.version().version_compare('> 2.4.97')
> amdgpu_progs +=[ 'amd_syncobj', ]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [igt-dev] [PATCH v2] tests/amdgpu: add VPE tests
2023-11-12 22:37 ` [igt-dev] [PATCH v2] " vitaly prosyak
@ 2023-11-13 2:47 ` Yu, Lang
2023-11-15 16:54 ` Kamil Konieczny
0 siblings, 1 reply; 6+ messages in thread
From: Yu, Lang @ 2023-11-13 2:47 UTC (permalink / raw)
To: Prosyak, Vitaly, igt-dev@lists.freedesktop.org
Cc: Deucher, Alexander, Liu, Leo
[AMD Official Use Only - General]
>-----Original Message-----
>From: Prosyak, Vitaly <Vitaly.Prosyak@amd.com>
>Sent: Monday, November 13, 2023 6:37 AM
>To: Yu, Lang <Lang.Yu@amd.com>; igt-dev@lists.freedesktop.org
>Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>; Deucher, Alexander
><Alexander.Deucher@amd.com>; Prosyak, Vitaly <Vitaly.Prosyak@amd.com>;
>Chiu, Solomon <Solomon.Chiu@amd.com>; Liu, Leo <Leo.Liu@amd.com>
>Subject: Re: [PATCH v2] tests/amdgpu: add VPE tests
>
>Added Leo.
>
>Hi Lang,
>
>Please, use the checkpatch.pl and fix formatting errors, for example,
Actually, it is strange to use checkpatch.pl to check igt patches.
How do you know the igt test developer is familiar with linux kernel tools?
Anyway I will check the patch with checkpatch.pl.
>
>vprosyak@desktop-host:~/src/igt-gpu-tools$ ../linux/scripts/checkpatch.pl -f --no-
>tree /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c
>ERROR: code indent should use tabs where possible
>#54: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:54:
>+ struct mmd_context *context)$
>
>WARNING: please, no spaces at the start of a line
>#54: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:54:
>+ struct mmd_context *context)$
>
>ERROR: code indent should use tabs where possible
>#56: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:56:
>+ struct drm_amdgpu_info_hw_ip info;$
>
>WARNING: please, no spaces at the start of a line
>#56: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:56:
>+ struct drm_amdgpu_info_hw_ip info;$
>
>ERROR: code indent should use tabs where possible
>#57: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:57:
>+ int r;$
>
>WARNING: please, no spaces at the start of a line
>#57: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:57:
>+ int r;$
>
>ERROR: code indent should use tabs where possible
>#59: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:59:
>+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VPE, 0,
>+&info);$
>
>Please, see inline below.
>
>
>Thanks, Vitaly
>
>On 2023-11-09 21:53, Lang Yu wrote:
>> Add tests for Video Processing Engine, including fence and blit tests.
>>
>> Signed-off-by: Lang Yu <Lang.Yu@amd.com>
>> ---
>> lib/amdgpu/amd_mmd_shared.h | 5 +
>> tests/amdgpu/amd_vpe.c | 253 ++++++++++++++++++++++++++++++++++++
>> tests/amdgpu/meson.build | 1 +
>> 3 files changed, 259 insertions(+)
>> create mode 100644 tests/amdgpu/amd_vpe.c
>>
>> diff --git a/lib/amdgpu/amd_mmd_shared.h b/lib/amdgpu/amd_mmd_shared.h
>> index 82e732509..14f9ecb4d 100644
>> --- a/lib/amdgpu/amd_mmd_shared.h
>> +++ b/lib/amdgpu/amd_mmd_shared.h
>> @@ -54,6 +54,11 @@ struct mmd_context {
>> bool enc_ring;
>> /* jpeg */
>> bool jpeg_direct_reg;
>> +
>> + /*vpe*/
>> + uint32_t vpe_ip_version_major;
>> + uint32_t vpe_ip_version_minor;
>> + bool vpe_ring;
>> };
>>
>> struct amdgpu_mmd_bo {
>> diff --git a/tests/amdgpu/amd_vpe.c b/tests/amdgpu/amd_vpe.c new file
>> mode 100644 index 000000000..782f10915
>> --- /dev/null
>> +++ b/tests/amdgpu/amd_vpe.c
>> @@ -0,0 +1,253 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright 2023 Advanced Micro Devices, Inc.
>> + */
>> +
>> +#include <amdgpu.h>
>> +#include "amdgpu_drm.h"
>> +
>> +#include "igt.h"
>> +
>> +#include "lib/amdgpu/amd_mmd_shared.h"
>> +
>> +IGT_TEST_DESCRIPTION("Test VPE functionality");
>> +
>> +#define IB_SIZE 4096
>> +#define MAX_RESOURCES 16
>> +
>> +#define PLANE_WIDTH 1024
>> +#define PLANE_HEIGHT 256
>> +#define PLANE_SIZE (PLANE_WIDTH*PLANE_HEIGHT*4)
>> +
>> +#define SRC_PLANE_PATTERN 0x12345678
>> +#define DST_PLANE_PATTERN 0xff123456
>
>Please, use the shared header for such definitions as we did for example into
>'AMD_MMD_VCE_IB_H"
>
>unless you are sure that these definitions will be not used in the future for other
>tests.
We should not have others tests and don't want to add another file.
>> +
>> +static uint32_t vpe_descriptor[] = {
>> +0x00000001, 0x33002200, 0xff000021, 0x00000003, 0x33002234,
>> +0xff000021, 0x33002328, 0xff000021, 0x33002384, 0xff000021,
>> +0x330023c0, 0xff000021, };
>> +
>> +static uint32_t vpe_config[] = {
>> +0x00000002, 0x00000000, 0xbeefbe00, 0xff005678, 0x000003ff,
>> +0x00000000, 0x00ff43ff, 0x00000000, 0xbeefbe00, 0xff005679,
>> +0x000003ff, 0x00000000, 0x00ff43ff, 0x003b0003, 0x00047808,
>> +0x00000809, 0x0004780c, 0x000000e4, 0x00047d10, 0x00000009,
>> +0x00047d14, 0x00000101, 0x00047d18, 0x00000000, 0x00047d1c,
>> +0x00000000, 0x00047d20, 0x00000000, 0x00047d24, 0x0001f010,
>> +0x00047d28, 0x0001f010, 0x00047d2c, 0x0001f010, 0x00547ee9,
>> +0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000,
>> +0x00002000, 0x00047ee4, 0x00000001, 0x00047ee0, 0x00000000,
>> +0x00047f24, 0x00000000, 0x00047fc4, 0x00000000, 0x00547f05,
>> +0x00002000, 0x00000000, 0x20000000, 0x00000000, 0x00000000,
>> +0x00002000, 0x00047f00, 0x00000001, 0x00049700, 0x00000000,
>> +0x00049704, 0x0000000f, 0x00049f30, 0x00000000, 0x00049708,
>> +0x00000000, 0x0004970c, 0xffff0462, 0x0004a208, 0x00000000,
>> +0x0004971c, 0x00000000, 0x00047fc0, 0x0001f000, 0x00150003,
>> +0x00047df8, 0x00000001, 0x00047dfc, 0x00000001, 0x00047da8,
>> +0x00000006, 0x00047e18, 0x00000000, 0x0004970c, 0xffff0422,
>> +0x00049710, 0x0001f000, 0x00049714, 0x0001f000, 0x00049718,
>> +0x0001f000, 0x00049720, 0x00000000, 0x00049724, 0x00000000,
>> +0x00049728, 0x00000000, 0x000d0003, 0x00047810, 0x00000000,
>> +0x00047814, 0x01000400, 0x00047818, 0x00000000, 0x0004781c,
>> +0x01000400, 0x00047e00, 0x00000000, 0x00047e04, 0x01000400,
>> +0x00047e08, 0x01000400, 0x00280003, 0x00047820, 0x00000036,
>> +0x00047824, 0x0960f015, 0x0004972c, 0x00000014, 0x0004972c,
>> +0x00000014, 0x0004972c, 0x00000014, 0x00049f90, 0x00000000,
>> +0x00049f94, 0x00000001, 0x00549f99, 0x00002000, 0x00000000,
>> +0x20000000, 0x00000000, 0x00000000, 0x00002000, 0x00049850,
>> +0x00000000, 0x00049f34, 0x00000000, 0x00049f38, 0x02fff000,
>> +0x00049f3c, 0x00fff000, 0x00049f40, 0x00fff000, 0x0004aba0,
>> +0xffff0000, 0x0004aba0, 0xffff0000, 0x0004aacc, 0x00000000,
>> +0x0004aad4, 0x00000013, 0x0004aad4, 0x00000013, };
>> +
>> +static bool is_vpe_tests_enabled(amdgpu_device_handle device_handle,
>> + struct mmd_context *context) {
>> + struct drm_amdgpu_info_hw_ip info;
>> + int r;
>> +
>> + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VPE, 0,
>&info);
>> + igt_assert_eq(r, 0);
>> +
>> + context->vpe_ip_version_major = info.hw_ip_version_major;
>> + context->vpe_ip_version_minor = info.hw_ip_version_minor;
>> + context->vpe_ring = !!info.available_rings;
>> +
>> + if (!context->vpe_ring) {
>> + igt_info("VPE no available rings");
>> + igt_info("VPE fence test disable");
>> + igt_info("VPE blit test disable");
>> + }
>> +
>Please, fix return from this function
Thanks for pointing this out.
>> + return true;
>> +}
>> +
>> +static void amdgpu_cs_vpe_fence(amdgpu_device_handle device_handle,
>> + struct mmd_context *context) {
>> + const uint32_t test_pattern = 0xdeadbeef;
>> + uint32_t *ib_cpu = context->ib_cpu;
>> + struct amdgpu_mmd_bo test_bo;
>> + int r;
>> +
>> + context->num_resources = 0;
>> + alloc_resource(device_handle, &test_bo, 4096,
>AMDGPU_GEM_DOMAIN_GTT);
>> + context->resources[context->num_resources++] =
>> + test_bo.handle;
>> +
>> + r = amdgpu_bo_cpu_map(test_bo.handle, (void **)&test_bo.ptr);
>> + igt_assert_eq(r, 0);
>> +
>> + memset(test_bo.ptr, 0, 4096);
>> +
>> + memset(ib_cpu, 0, IB_SIZE);
>> +
>> + ib_cpu[0] = 0x5;
>
>Please, use macro lower_32_bits & upper_32_bits, as we are using, for example,
Ok, thanks.
Regards,
Lang
> ring_context->pm4[i++] = lower_32_bits(ring_context->bo_mc);
>
> ring_context->pm4[i++] = upper_32_bits(ring_context->bo_mc);
>> + ib_cpu[1] = 0xfffffffc & test_bo.addr;
>> + ib_cpu[2] = (0xffffffff00000000 & test_bo.addr) >> 32;
>> + ib_cpu[3] = test_pattern;
>> + ib_cpu[4] = 0x0;
>> + ib_cpu[5] = 0x0;
>> + ib_cpu[6] = 0x0;
>> + ib_cpu[7] = 0x0;
>> +
>> + context->resources[context->num_resources++] =
>> + context->ib_handle;
>> +
>> + r = submit(device_handle, context, 8, AMDGPU_HW_IP_VPE);
>> + igt_assert_eq(r, 0);
>> +
>> + igt_assert_eq(((uint32_t *)test_bo.ptr)[0], test_pattern);
>> +
>> + r = amdgpu_bo_cpu_unmap(test_bo.handle);
>> + igt_assert_eq(r, 0);
>> +
>> + free_resource(&test_bo);
>> +}
>> +
>> +// a in byte 0, b in byte 1, g in byte 2, r in byte 3 static void
>> +create_rgba8888(void *addr, uint32_t width, uint32_t height) {
>> + uint32_t *ptr = (uint32_t *)addr;
>> +
>> + for (int i = 0; i < height; i++) {
>> + for (int j = 0; j < width; j++)
>> + ptr[j] = SRC_PLANE_PATTERN;
>> + ptr += width;
>> + }
>> +}
>> +// b in byte 0, g in byte 1, r in byte 2, a in byte 3 static int
>> +check_argb8888(void *addr, uint32_t width, uint32_t height) {
>> + uint32_t *ptr = (uint32_t *)addr;
>> +
>> + for (int i = 0; i < height; i++) {
>> + for (int j = 0; j < width; j++)
>> + if (ptr[j] != DST_PLANE_PATTERN)
>> + return 1;
>> + ptr += width;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void amdgpu_cs_vpe_blit(amdgpu_device_handle device_handle,
>> + struct mmd_context *context) {
>> + const uint32_t vpep_config_offsets[] = {0x34, 0x128, 0x184, 0x1c0};
>> + struct amdgpu_mmd_bo vpe_config_bo, src_plane_bo, dst_plane_bo;
>> + int r;
>> +
>> + context->num_resources = 0;
>> +
>> + alloc_resource(device_handle, &vpe_config_bo, sizeof(vpe_config),
>AMDGPU_GEM_DOMAIN_GTT);
>> + alloc_resource(device_handle, &src_plane_bo, PLANE_SIZE,
>AMDGPU_GEM_DOMAIN_GTT);
>> + alloc_resource(device_handle, &dst_plane_bo, PLANE_SIZE,
>> + AMDGPU_GEM_DOMAIN_GTT);
>> +
>> + r = amdgpu_bo_cpu_map(vpe_config_bo.handle, (void
>**)&vpe_config_bo.ptr);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_cpu_map(src_plane_bo.handle, (void
>**)&src_plane_bo.ptr);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_cpu_map(dst_plane_bo.handle, (void
>**)&dst_plane_bo.ptr);
>> + igt_assert_eq(r, 0);
>> +
>> + context->resources[context->num_resources++] = vpe_config_bo.handle;
>> + context->resources[context->num_resources++] = src_plane_bo.handle;
>> + context->resources[context->num_resources++] =
>> + dst_plane_bo.handle;
>> +
>> + // plane config gpu addr
>> + *(uint64_t *)(vpe_descriptor + 1) = vpe_config_bo.addr;
>> + // vpep config0 gpu addr
>> + *(uint64_t *)(vpe_descriptor + 4) = vpe_config_bo.addr +
>vpep_config_offsets[0];
>> + // vpep config1 gpu addr
>> + *(uint64_t *)(vpe_descriptor + 6) = vpe_config_bo.addr +
>vpep_config_offsets[1];
>> + // vpep config2 gpu addr
>> + *(uint64_t *)(vpe_descriptor + 8) = vpe_config_bo.addr +
>vpep_config_offsets[2];
>> + // vpep config3 gpu addr
>> + *(uint64_t *)(vpe_descriptor + 10) = vpe_config_bo.addr +
>> + vpep_config_offsets[3];
>> +
>> + memset(src_plane_bo.ptr, 0, PLANE_SIZE);
>> + memset(dst_plane_bo.ptr, 0, PLANE_SIZE);
>> + create_rgba8888(src_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
>> +
>> + /* gpu address of src */
>> + *(uint64_t *)(vpe_config + 2) = src_plane_bo.addr;
>> + /* gpu address of dst */
>> + *(uint64_t *)(vpe_config + 8) = dst_plane_bo.addr;
>> +
>> + memset(vpe_config_bo.ptr, 0, sizeof(vpe_config));
>> + memcpy(vpe_config_bo.ptr, vpe_config, sizeof(vpe_config));
>> +
>> + memset(context->ib_cpu, 0, IB_SIZE);
>> + memcpy(context->ib_cpu, vpe_descriptor,
>> + sizeof(vpe_descriptor));
>> +
>> + context->resources[context->num_resources++] =
>> + context->ib_handle;
>> +
>> + r = submit(device_handle, context, sizeof(vpe_descriptor)/4,
>AMDGPU_HW_IP_VPE);
>> + igt_assert_eq(r, 0);
>> +
>> + r = check_argb8888(dst_plane_bo.ptr, PLANE_WIDTH, PLANE_HEIGHT);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_cpu_unmap(vpe_config_bo.handle);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_cpu_unmap(src_plane_bo.handle);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_cpu_unmap(dst_plane_bo.handle);
>> + igt_assert_eq(r, 0);
>> +
>> + free_resource(&vpe_config_bo);
>> + free_resource(&src_plane_bo);
>> + free_resource(&dst_plane_bo); }
>> +
>> +igt_main
>> +{
>> + struct mmd_context context = {};
>> + amdgpu_device_handle device;
>> + int fd = -1;
>> +
>> + igt_fixture {
>> + uint32_t major, minor;
>> + int r;
>> +
>> + fd = drm_open_driver(DRIVER_AMDGPU);
>> + igt_require(fd > 0);
>> +
>> + r = amdgpu_device_initialize(fd, &major, &minor, &device);
>> + igt_require(r == 0);
>> +
>> + igt_info("Initialized amdgpu, driver version %d.%d\n", major,
>> +minor);
>> +
>> + r = mmd_context_init(device, &context);
>> + igt_require(r == 0);
>> +
>> + igt_skip_on(!is_vpe_tests_enabled(device, &context));
>> + }
>> +
>> + igt_describe("Test VPE fence");
>> + igt_subtest("vpe-fence-test")
>> + amdgpu_cs_vpe_fence(device, &context);
>> +
>> + igt_describe("Test VPE blit");
>> + igt_subtest("vpe-blit-test")
>> + amdgpu_cs_vpe_blit(device, &context);
>> +
>> + igt_fixture {
>> + amdgpu_device_deinitialize(device);
>> + drm_close_driver(fd);
>> + }
>> +
>> +}
>> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build index
>> efd911fab..bbb8edc93 100644
>> --- a/tests/amdgpu/meson.build
>> +++ b/tests/amdgpu/meson.build
>> @@ -37,6 +37,7 @@ if libdrm_amdgpu.found()
>> 'amd_mall',
>> 'amd_odm',
>> 'amd_subvp',
>> + 'amd_vpe',
>> ]
>> if libdrm_amdgpu.version().version_compare('> 2.4.97')
>> amdgpu_progs +=[ 'amd_syncobj', ]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [igt-dev] [PATCH v2] tests/amdgpu: add VPE tests
2023-11-13 2:47 ` Yu, Lang
@ 2023-11-15 16:54 ` Kamil Konieczny
0 siblings, 0 replies; 6+ messages in thread
From: Kamil Konieczny @ 2023-11-15 16:54 UTC (permalink / raw)
To: igt-dev@lists.freedesktop.org; +Cc: Deucher, Alexander, Yu, Lang, Liu, Leo
Hi Yu,
On 2023-11-13 at 02:47:55 +0000, Yu, Lang wrote:
> [AMD Official Use Only - General]
>
> >-----Original Message-----
> >From: Prosyak, Vitaly <Vitaly.Prosyak@amd.com>
> >Sent: Monday, November 13, 2023 6:37 AM
> >To: Yu, Lang <Lang.Yu@amd.com>; igt-dev@lists.freedesktop.org
> >Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>; Deucher, Alexander
> ><Alexander.Deucher@amd.com>; Prosyak, Vitaly <Vitaly.Prosyak@amd.com>;
> >Chiu, Solomon <Solomon.Chiu@amd.com>; Liu, Leo <Leo.Liu@amd.com>
> >Subject: Re: [PATCH v2] tests/amdgpu: add VPE tests
> >
> >Added Leo.
> >
> >Hi Lang,
> >
> >Please, use the checkpatch.pl and fix formatting errors, for example,
>
> Actually, it is strange to use checkpatch.pl to check igt patches.
> How do you know the igt test developer is familiar with linux kernel tools?
> Anyway I will check the patch with checkpatch.pl.
>
It is a tool which helps with keeping source code in shape, instead of
reinventing our own tool it is better to use it. Some of its errors or
warnings may be ignored but generally I find it usefull.
Regards,
Kamil
> >
> >vprosyak@desktop-host:~/src/igt-gpu-tools$ ../linux/scripts/checkpatch.pl -f --no-
> >tree /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c
> >ERROR: code indent should use tabs where possible
> >#54: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:54:
> >+ struct mmd_context *context)$
> >
> >WARNING: please, no spaces at the start of a line
> >#54: FILE: /home/vprosyak/src/igt-gpu-tools/tests/amdgpu/amd_vpe.c:54:
> >+ struct mmd_context *context)$
> >
[...]
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-11-15 16:54 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-10 2:53 [igt-dev] [PATCH v2] tests/amdgpu: add VPE tests Lang Yu
2023-11-10 3:35 ` [igt-dev] ✓ CI.xeBAT: success for " Patchwork
2023-11-10 3:50 ` [igt-dev] ✗ Fi.CI.BAT: failure " Patchwork
2023-11-12 22:37 ` [igt-dev] [PATCH v2] " vitaly prosyak
2023-11-13 2:47 ` Yu, Lang
2023-11-15 16:54 ` Kamil Konieczny
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