[igt-dev] [PATCH 0/2] Test zero execs/binds with fences

[igt-dev] [PATCH 0/2] Test zero execs/binds with fences

[Matthew Brost]

Tests new Xe driver behavior in [1].

Matt

[1] https://patchwork.freedesktop.org/series/126546/

Matthew Brost (2):
  xe_vm: Add section to test zero number of VM binds
  xe_exec_basic: Add section to test zero number of BB in exec IOCTL

 lib/xe/xe_ioctl.c           |  13 +++++
 lib/xe/xe_ioctl.h           |   2 +
 tests/intel/xe_exec_basic.c | 108 ++++++++++++++++++++++++++++++++++++
 tests/intel/xe_vm.c         |  63 +++++++++++++++++++++
 4 files changed, 186 insertions(+)

-- 
2.34.1

[igt-dev] [PATCH 1/2] xe_vm: Add section to test zero number of VM binds

[Matthew Brost]

Verify the bind queue ordering works wrt out-sync signaling when zero
number of binds passed to VM bind IOCTL.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 lib/xe/xe_ioctl.c   | 13 ++++++++++
 lib/xe/xe_ioctl.h   |  2 ++
 tests/intel/xe_vm.c | 63 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 78 insertions(+)

diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index c91bf25c49..761e91eb3a 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -164,6 +164,19 @@ void xe_vm_bind_async(int fd, uint32_t vm, uint32_t exec_queue, uint32_t bo,
 			    num_syncs, 0, 0);
 }
 
+void xe_vm_bind_zero(int fd, uint32_t vm, uint32_t exec_queue,
+		     struct drm_xe_sync *sync, uint32_t num_syncs)
+{
+	struct drm_xe_vm_bind bind = {
+		.vm_id = vm,
+		.num_syncs = num_syncs,
+		.syncs = (uintptr_t)sync,
+		.exec_queue_id = exec_queue,
+	};
+
+	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind), 0);
+}
+
 void xe_vm_bind_async_flags(int fd, uint32_t vm, uint32_t exec_queue, uint32_t bo,
 			    uint64_t offset, uint64_t addr, uint64_t size,
 			    struct drm_xe_sync *sync, uint32_t num_syncs,
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index 32b34b15a3..a302418544 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -38,6 +38,8 @@ void xe_vm_prefetch_async(int fd, uint32_t vm, uint32_t exec_queue,
 void xe_vm_bind_async(int fd, uint32_t vm, uint32_t exec_queue, uint32_t bo,
 		      uint64_t offset, uint64_t addr, uint64_t size,
 		      struct drm_xe_sync *sync, uint32_t num_syncs);
+void xe_vm_bind_zero(int fd, uint32_t vm, uint32_t exec_queue,
+		     struct drm_xe_sync *sync, uint32_t num_syncs);
 void xe_vm_bind_userptr_async(int fd, uint32_t vm, uint32_t exec_queue,
 			      uint64_t userptr, uint64_t addr, uint64_t size,
 			      struct drm_xe_sync *sync, uint32_t num_syncs);
diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
index fb65793d11..62bf950504 100644
--- a/tests/intel/xe_vm.c
+++ b/tests/intel/xe_vm.c
@@ -730,6 +730,63 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec
 	xe_vm_destroy(fd, vm);
 }
 
+/**
+ * SUBTEST: zero-binds
+ * Description: Test zero binds in IOCTL
+ * Functionality: bind engines
+ * Run type: BAT
+ */
+
+static void test_zero_binds(int fd, struct drm_xe_engine_class_instance *eci)
+{
+	uint32_t vm;
+	uint64_t addr = 0x1a0000;
+	struct drm_xe_sync sync[1] = {
+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+	};
+	size_t bo_size;
+	uint32_t bo = 0;
+	struct xe_cork cork;
+
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
+	bo_size = ALIGN(xe_cs_prefetch_size(fd),
+			xe_get_default_alignment(fd));
+	bo = xe_bo_create(fd, vm, bo_size,
+			  vram_if_possible(fd, eci->gt_id),
+			  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+
+	xe_cork_init(fd, eci, &cork);
+	xe_cork_wait_started(&cork);
+
+	/* Initial bind behind cork */
+	sync[0].handle = cork.syncobj;
+	sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+	xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1);
+
+	/* Bind /w num_binds == 0 */
+	sync[0].handle = syncobj_create(fd, 0);
+	sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+	xe_vm_bind_zero(fd, vm, 0, sync, 1);
+
+	/* Let jobs runs for a bit */
+	usleep(100000);
+
+	/* both binds are waiting */
+	igt_assert(!syncobj_wait(fd, &sync[0].handle, 1, 0, 0, NULL));
+
+	/* Release cork */
+	xe_cork_end(&cork);
+	xe_cork_wait_done(&cork);
+	xe_cork_fini(&cork);
+
+	/* both binds are done */
+	igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+	syncobj_destroy(fd, sync[0].handle);
+	gem_close(fd, bo);
+	xe_vm_destroy(fd, vm);
+}
+
 #define BIND_ARRAY_BIND_EXEC_QUEUE_FLAG	(0x1 << 0)
 
 
@@ -1917,6 +1974,12 @@ igt_main
 		xe_for_each_engine(fd, hwe)
 			test_bind_execqueues_independent(fd, hwe, CONFLICT);
 
+	igt_subtest("zero-binds")
+		xe_for_each_engine(fd, hwe) {
+			test_zero_binds(fd, hwe);
+			break;
+		}
+
 	igt_subtest("bind-array-twice")
 		xe_for_each_engine(fd, hwe)
 			test_bind_array(fd, hwe, 2, 0);
-- 
2.34.1

[igt-dev] [PATCH 2/2] xe_exec_basic: Add section to test zero number of BB in exec IOCTL

[Matthew Brost]

Verify the exec queue ordering works wrt out-sync signaling when zero
number of BB passed to exec IOCTL.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 tests/intel/xe_exec_basic.c | 108 ++++++++++++++++++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c
index 2defd1e358..b20581382c 100644
--- a/tests/intel/xe_exec_basic.c
+++ b/tests/intel/xe_exec_basic.c
@@ -17,6 +17,7 @@
 
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
+#include "xe/xe_spin.h"
 #include <string.h>
 
 #define MAX_N_EXEC_QUEUES 16
@@ -300,6 +301,109 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
 	}
 }
 
+/**
+ * SUBTEST: zero-execs
+ * Description: Test zero execs in IOCTL
+ * Functionality: exec IOCTL
+ * Run type: BAT
+ */
+
+static void test_zero_execs(int fd, struct drm_xe_engine_class_instance *eci,
+			    int n_execs)
+{
+	uint32_t vm;
+	uint64_t addr = 0x1a0000;
+	struct drm_xe_sync sync[2] = {
+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(sync),
+	};
+	size_t bo_size;
+	uint32_t bo = 0;
+	uint32_t syncobj;
+	uint32_t exec_queue;
+	struct xe_cork cork;
+	struct {
+		uint32_t batch[16];
+		uint64_t pad;
+		uint32_t data;
+	} *data;
+	int i, b;
+
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
+	bo_size = sizeof(*data) * n_execs;
+	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
+			xe_get_default_alignment(fd));
+	bo = xe_bo_create(fd, vm, bo_size,
+			  vram_if_possible(fd, eci->gt_id),
+			  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+	data = xe_bo_map(fd, bo, bo_size);
+	exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
+
+	xe_cork_init(fd, eci, &cork);
+	xe_cork_wait_started(&cork);
+
+	/* Initial bind behind cork */
+	sync[0].handle = syncobj = syncobj_create(fd, 0);
+	sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+	sync[1].handle = cork.syncobj;
+	sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+	xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 2);
+
+	/* Exec behind bind */
+	for (i = 0; i < n_execs; i++) {
+		uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
+		uint64_t batch_addr = addr + batch_offset;
+		uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
+		uint64_t sdi_addr = addr + sdi_offset;
+
+		b = 0;
+		data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+		data[i].batch[b++] = sdi_addr;
+		data[i].batch[b++] = sdi_addr >> 32;
+		data[i].batch[b++] = 0xc0ffee;
+		data[i].batch[b++] = MI_BATCH_BUFFER_END;
+		igt_assert(b <= ARRAY_SIZE(data[i].batch));
+
+		sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+
+		exec.exec_queue_id = exec_queue;
+		exec.address = batch_addr;
+		xe_exec(fd, &exec);
+	}
+
+	/* Exec with no batch buffer */
+	sync[0].handle = syncobj_create(fd, 0);
+	sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+	exec.num_batch_buffer = 0;
+	exec.address = 0;
+	xe_exec(fd, &exec);
+
+	/* Let jobs runs for a bit */
+	usleep(100000);
+
+	/* both bind and execs are waiting */
+	igt_assert(!syncobj_wait(fd, &syncobj, 1, 0, 0, NULL));
+	igt_assert(!syncobj_wait(fd, &sync[0].handle, 1, 0, 0, NULL));
+
+	/* Release cork */
+	xe_cork_end(&cork);
+	xe_cork_wait_done(&cork);
+	xe_cork_fini(&cork);
+
+	/* both binds are done */
+	igt_assert(syncobj_wait(fd, &syncobj, 1, INT64_MAX, 0, NULL));
+	igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+	syncobj_destroy(fd, sync[0].handle);
+	gem_close(fd, bo);
+	xe_vm_destroy(fd, vm);
+}
+
 igt_main
 {
 	struct drm_xe_engine_class_instance *hwe;
@@ -369,6 +473,10 @@ igt_main
 				test_exec(fd, hwe, 1, 0, 1, s->flags);
 	}
 
+	igt_subtest("zero-execs")
+		xe_for_each_engine(fd, hwe)
+			test_zero_execs(fd, hwe, 1);
+
 	igt_fixture
 		drm_close_driver(fd);
 }
-- 
2.34.1

Re: [igt-dev] [PATCH 2/2] xe_exec_basic: Add section to test zero number of BB in exec IOCTL

[Ch, Sai Gowtham]

>-----Original Message-----
>From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Matthew
>Brost
>Sent: Wednesday, December 6, 2023 2:12 AM
>To: igt-dev@lists.freedesktop.org
>Subject: [igt-dev] [PATCH 2/2] xe_exec_basic: Add section to test zero number of
>BB in exec IOCTL
>
>Verify the exec queue ordering works wrt out-sync signaling when zero number of
>BB passed to exec IOCTL.
>
>Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>---
> tests/intel/xe_exec_basic.c | 108 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 108 insertions(+)
>
>diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c index
>2defd1e358..b20581382c 100644
>--- a/tests/intel/xe_exec_basic.c
>+++ b/tests/intel/xe_exec_basic.c
>@@ -17,6 +17,7 @@
>
> #include "xe/xe_ioctl.h"
> #include "xe/xe_query.h"
>+#include "xe/xe_spin.h"
> #include <string.h>
>
> #define MAX_N_EXEC_QUEUES 16
>@@ -300,6 +301,109 @@ test_exec(int fd, struct drm_xe_engine_class_instance
>*eci,
> 	}
> }
>
>+/**
>+ * SUBTEST: zero-execs
>+ * Description: Test zero execs in IOCTL
>+ * Functionality: exec IOCTL
>+ * Run type: BAT
>+ */
>+
>+static void test_zero_execs(int fd, struct drm_xe_engine_class_instance *eci,
>+			    int n_execs)
>+{
>+	uint32_t vm;
>+	uint64_t addr = 0x1a0000;
>+	struct drm_xe_sync sync[2] = {
>+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ |
>DRM_XE_SYNC_FLAG_SIGNAL, },
>+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ |
>DRM_XE_SYNC_FLAG_SIGNAL, },
>+	};
>+	struct drm_xe_exec exec = {
>+		.num_batch_buffer = 1,
>+		.num_syncs = 1,
>+		.syncs = to_user_pointer(sync),
>+	};
>+	size_t bo_size;
>+	uint32_t bo = 0;
>+	uint32_t syncobj;
>+	uint32_t exec_queue;
>+	struct xe_cork cork;
>+	struct {
>+		uint32_t batch[16];
>+		uint64_t pad;
>+		uint32_t data;
>+	} *data;
>+	int i, b;
>+
>+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
>+	bo_size = sizeof(*data) * n_execs;
>+	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
>+			xe_get_default_alignment(fd));
>+	bo = xe_bo_create(fd, vm, bo_size,
>+			  vram_if_possible(fd, eci->gt_id),
>+			  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>+	data = xe_bo_map(fd, bo, bo_size);
>+	exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
>+
>+	xe_cork_init(fd, eci, &cork);
>+	xe_cork_wait_started(&cork);
>+
>+	/* Initial bind behind cork */
>+	sync[0].handle = syncobj = syncobj_create(fd, 0);
>+	sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>+	sync[1].handle = cork.syncobj;
>+	sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>+	xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 2);
>+
>+	/* Exec behind bind */
>+	for (i = 0; i < n_execs; i++) {
>+		uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
>+		uint64_t batch_addr = addr + batch_offset;
>+		uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
>+		uint64_t sdi_addr = addr + sdi_offset;
>+
>+		b = 0;
>+		data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
>+		data[i].batch[b++] = sdi_addr;
>+		data[i].batch[b++] = sdi_addr >> 32;
>+		data[i].batch[b++] = 0xc0ffee;
>+		data[i].batch[b++] = MI_BATCH_BUFFER_END;
>+		igt_assert(b <= ARRAY_SIZE(data[i].batch));
>+
>+		sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>+
>+		exec.exec_queue_id = exec_queue;
>+		exec.address = batch_addr;
>+		xe_exec(fd, &exec);
Why are you submitting jobs first ? when the intension is to just check exec IOCTL with zero number of bb,
I could be a simple test with num_batch_buffer = 0 with a dummy workload just submitting  MI_BATCH_BUFFER_END. 

>+	}
>+
>+	/* Exec with no batch buffer */
>+	sync[0].handle = syncobj_create(fd, 0);
>+	sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>+	exec.num_batch_buffer = 0;
What happens if we give valid exec.address with zero number of BB ?

--
Sai Gowtham Ch
>+	exec.address = 0;
>+	xe_exec(fd, &exec);
>+
>+	/* Let jobs runs for a bit */
>+	usleep(100000);
>+
>+	/* both bind and execs are waiting */
>+	igt_assert(!syncobj_wait(fd, &syncobj, 1, 0, 0, NULL));
>+	igt_assert(!syncobj_wait(fd, &sync[0].handle, 1, 0, 0, NULL));
>+
>+	/* Release cork */
>+	xe_cork_end(&cork);
>+	xe_cork_wait_done(&cork);
>+	xe_cork_fini(&cork);
>+
>+	/* both binds are done */
>+	igt_assert(syncobj_wait(fd, &syncobj, 1, INT64_MAX, 0, NULL));
>+	igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
>+
>+	syncobj_destroy(fd, sync[0].handle);
>+	gem_close(fd, bo);
>+	xe_vm_destroy(fd, vm);
>+}
>+
> igt_main
> {
> 	struct drm_xe_engine_class_instance *hwe; @@ -369,6 +473,10 @@
>igt_main
> 				test_exec(fd, hwe, 1, 0, 1, s->flags);
> 	}
>
>+	igt_subtest("zero-execs")
>+		xe_for_each_engine(fd, hwe)
>+			test_zero_execs(fd, hwe, 1);
>+
> 	igt_fixture
> 		drm_close_driver(fd);
> }
>--
>2.34.1

Re: [igt-dev] [PATCH 2/2] xe_exec_basic: Add section to test zero number of BB in exec IOCTL

[Matthew Brost]

On Tue, Dec 05, 2023 at 09:49:00PM -0700, Ch, Sai Gowtham wrote:
> 
> 
> >-----Original Message-----
> >From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Matthew
> >Brost
> >Sent: Wednesday, December 6, 2023 2:12 AM
> >To: igt-dev@lists.freedesktop.org
> >Subject: [igt-dev] [PATCH 2/2] xe_exec_basic: Add section to test zero number of
> >BB in exec IOCTL
> >
> >Verify the exec queue ordering works wrt out-sync signaling when zero number of
> >BB passed to exec IOCTL.
> >
> >Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> >---
> > tests/intel/xe_exec_basic.c | 108 ++++++++++++++++++++++++++++++++++++
> > 1 file changed, 108 insertions(+)
> >
> >diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c index
> >2defd1e358..b20581382c 100644
> >--- a/tests/intel/xe_exec_basic.c
> >+++ b/tests/intel/xe_exec_basic.c
> >@@ -17,6 +17,7 @@
> >
> > #include "xe/xe_ioctl.h"
> > #include "xe/xe_query.h"
> >+#include "xe/xe_spin.h"
> > #include <string.h>
> >
> > #define MAX_N_EXEC_QUEUES 16
> >@@ -300,6 +301,109 @@ test_exec(int fd, struct drm_xe_engine_class_instance
> >*eci,
> > 	}
> > }
> >
> >+/**
> >+ * SUBTEST: zero-execs
> >+ * Description: Test zero execs in IOCTL
> >+ * Functionality: exec IOCTL
> >+ * Run type: BAT
> >+ */
> >+
> >+static void test_zero_execs(int fd, struct drm_xe_engine_class_instance *eci,
> >+			    int n_execs)
> >+{
> >+	uint32_t vm;
> >+	uint64_t addr = 0x1a0000;
> >+	struct drm_xe_sync sync[2] = {
> >+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ |
> >DRM_XE_SYNC_FLAG_SIGNAL, },
> >+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ |
> >DRM_XE_SYNC_FLAG_SIGNAL, },
> >+	};
> >+	struct drm_xe_exec exec = {
> >+		.num_batch_buffer = 1,
> >+		.num_syncs = 1,
> >+		.syncs = to_user_pointer(sync),
> >+	};
> >+	size_t bo_size;
> >+	uint32_t bo = 0;
> >+	uint32_t syncobj;
> >+	uint32_t exec_queue;
> >+	struct xe_cork cork;
> >+	struct {
> >+		uint32_t batch[16];
> >+		uint64_t pad;
> >+		uint32_t data;
> >+	} *data;
> >+	int i, b;
> >+
> >+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
> >+	bo_size = sizeof(*data) * n_execs;
> >+	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> >+			xe_get_default_alignment(fd));
> >+	bo = xe_bo_create(fd, vm, bo_size,
> >+			  vram_if_possible(fd, eci->gt_id),
> >+			  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> >+	data = xe_bo_map(fd, bo, bo_size);
> >+	exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
> >+
> >+	xe_cork_init(fd, eci, &cork);
> >+	xe_cork_wait_started(&cork);
> >+
> >+	/* Initial bind behind cork */
> >+	sync[0].handle = syncobj = syncobj_create(fd, 0);
> >+	sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> >+	sync[1].handle = cork.syncobj;
> >+	sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> >+	xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 2);
> >+
> >+	/* Exec behind bind */
> >+	for (i = 0; i < n_execs; i++) {
> >+		uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
> >+		uint64_t batch_addr = addr + batch_offset;
> >+		uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
> >+		uint64_t sdi_addr = addr + sdi_offset;
> >+
> >+		b = 0;
> >+		data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> >+		data[i].batch[b++] = sdi_addr;
> >+		data[i].batch[b++] = sdi_addr >> 32;
> >+		data[i].batch[b++] = 0xc0ffee;
> >+		data[i].batch[b++] = MI_BATCH_BUFFER_END;
> >+		igt_assert(b <= ARRAY_SIZE(data[i].batch));
> >+
> >+		sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> >+
> >+		exec.exec_queue_id = exec_queue;
> >+		exec.address = batch_addr;
> >+		xe_exec(fd, &exec);
> Why are you submitting jobs first ? when the intension is to just check exec IOCTL with zero number of bb,

It is test that a exec with 0 batches is ordered on the queue behind any
existing batches.  

> I could be a simple test with num_batch_buffer = 0 with a dummy workload just submitting  MI_BATCH_BUFFER_END. 
> 

A workload with MI_BATCH_BUFFER_END is not required, that is the point
of allowinf num_batch_buffer == 0.

> >+	}
> >+
> >+	/* Exec with no batch buffer */
> >+	sync[0].handle = syncobj_create(fd, 0);
> >+	sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> >+	exec.num_batch_buffer = 0;
> What happens if we give valid exec.address with zero number of BB ?
> 

The address is ignored. It can be valid or invalid.

Matt

> --
> Sai Gowtham Ch
> >+	exec.address = 0;
> >+	xe_exec(fd, &exec);
> >+
> >+	/* Let jobs runs for a bit */
> >+	usleep(100000);
> >+
> >+	/* both bind and execs are waiting */
> >+	igt_assert(!syncobj_wait(fd, &syncobj, 1, 0, 0, NULL));
> >+	igt_assert(!syncobj_wait(fd, &sync[0].handle, 1, 0, 0, NULL));
> >+
> >+	/* Release cork */
> >+	xe_cork_end(&cork);
> >+	xe_cork_wait_done(&cork);
> >+	xe_cork_fini(&cork);
> >+
> >+	/* both binds are done */
> >+	igt_assert(syncobj_wait(fd, &syncobj, 1, INT64_MAX, 0, NULL));
> >+	igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> >+
> >+	syncobj_destroy(fd, sync[0].handle);
> >+	gem_close(fd, bo);
> >+	xe_vm_destroy(fd, vm);
> >+}
> >+
> > igt_main
> > {
> > 	struct drm_xe_engine_class_instance *hwe; @@ -369,6 +473,10 @@
> >igt_main
> > 				test_exec(fd, hwe, 1, 0, 1, s->flags);
> > 	}
> >
> >+	igt_subtest("zero-execs")
> >+		xe_for_each_engine(fd, hwe)
> >+			test_zero_execs(fd, hwe, 1);
> >+
> > 	igt_fixture
> > 		drm_close_driver(fd);
> > }
> >--
> >2.34.1
> 

[igt-dev] ✗ Fi.CI.BAT: failure for Test zero execs/binds with fences

[Patchwork]

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== Series Details ==

Series: Test zero execs/binds with fences
URL   : https://patchwork.freedesktop.org/series/127388/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13983 -> IGTPW_10344
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_10344 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_10344, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/index.html

Participating hosts (35 -> 36)
------------------------------

  Additional (2): bat-dg2-8 bat-mtlp-8 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_10344:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_psr@psr_cursor_plane_move:
    - bat-mtlp-8:         NOTRUN -> [SKIP][1] +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@kms_psr@psr_cursor_plane_move.html

  
Known issues
------------

  Here are the changes found in IGTPW_10344 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-mtlp-8:         NOTRUN -> [ABORT][2] ([i915#8213] / [i915#8668])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@core_hotunplug@unbind-rebind.html
    - bat-dg2-8:          NOTRUN -> [ABORT][3] ([i915#8213])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@core_hotunplug@unbind-rebind.html

  * igt@debugfs_test@basic-hwmon:
    - bat-mtlp-8:         NOTRUN -> [SKIP][4] ([i915#9318])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html

  * igt@gem_mmap@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@gem_mmap@basic.html
    - bat-dg2-8:          NOTRUN -> [SKIP][6] ([i915#4083])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@gem_mmap_gtt@basic.html
    - bat-dg2-8:          NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@gem_mmap_gtt@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-dg2-8:          NOTRUN -> [SKIP][10] ([i915#4079]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-mtlp-8:         NOTRUN -> [SKIP][11] ([i915#6621])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
    - bat-dg2-8:          NOTRUN -> [SKIP][12] ([i915#6621])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@i915_pm_rps@basic-api.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][13] ([i915#5190])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-dg2-8:          NOTRUN -> [SKIP][14] ([i915#5190])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][15] ([i915#4212]) +8 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg2-8:          NOTRUN -> [SKIP][16] ([i915#4215] / [i915#5190])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
    - bat-dg2-8:          NOTRUN -> [SKIP][17] ([i915#4212]) +6 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - bat-dg2-8:          NOTRUN -> [SKIP][18] ([i915#4212] / [i915#5608])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][19] ([i915#4213]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-dg2-8:          NOTRUN -> [SKIP][20] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][21] ([i915#3555] / [i915#3840] / [i915#9159])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-mtlp-8:         NOTRUN -> [SKIP][22] ([fdo#109285])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
    - bat-dg2-8:          NOTRUN -> [SKIP][23] ([fdo#109285])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-mtlp-8:         NOTRUN -> [SKIP][24] ([i915#5274])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
    - bat-dg2-8:          NOTRUN -> [SKIP][25] ([i915#5274])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-dg2-8:          NOTRUN -> [SKIP][26] ([i915#5354])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr_cursor_plane_move:
    - bat-dg2-8:          NOTRUN -> [SKIP][27] ([i915#9673] / [i915#9736]) +3 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@kms_psr@psr_cursor_plane_move.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-mtlp-8:         NOTRUN -> [SKIP][28] ([i915#3555] / [i915#8809])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-dg2-8:          NOTRUN -> [SKIP][29] ([i915#3555])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg2-8:          NOTRUN -> [SKIP][30] ([i915#3708])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-dg2-8:          NOTRUN -> [SKIP][31] ([i915#3708] / [i915#4077]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
    - bat-mtlp-8:         NOTRUN -> [SKIP][32] ([i915#3708] / [i915#4077]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - bat-mtlp-8:         NOTRUN -> [SKIP][33] ([i915#3708]) +2 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-write:
    - bat-dg2-8:          NOTRUN -> [SKIP][34] ([i915#3291] / [i915#3708]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/bat-dg2-8/igt@prime_vgem@basic-write.html

  
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
  [i915#9736]: https://gitlab.freedesktop.org/drm/intel/issues/9736


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7622 -> IGTPW_10344

  CI-20190529: 20190529
  CI_DRM_13983: a9d99261a978835b02e248fe18af3026416af3e8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_10344: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/index.html
  IGT_7622: 48a47d91b7727215b965690c69d84159c8fb1aa2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@xe_exec_basic@zero-execs
+igt@xe_vm@zero-binds
-igt@xe_spin_batch@spin-fixed-duration-with-preempter

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/index.html

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[igt-dev] ✓ CI.xeBAT: success for Test zero execs/binds with fences

[Patchwork]

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== Series Details ==

Series: Test zero execs/binds with fences
URL   : https://patchwork.freedesktop.org/series/127388/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7622_BAT -> XEIGTPW_10344_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 3)
------------------------------

  Missing    (1): bat-adlp-7 


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_7622 -> IGTPW_10344

  IGTPW_10344: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10344/index.html
  IGT_7622: 48a47d91b7727215b965690c69d84159c8fb1aa2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-550-ac7b89571d802765762e7c15d78a6dcd5d92c41b: ac7b89571d802765762e7c15d78a6dcd5d92c41b

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10344/index.html

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