* [PATCH i-g-t 0/2] Add Persistent support @ 2023-12-27 12:20 sai.gowtham.ch 2023-12-27 12:20 ` [PATCH i-g-t 1/2] include/intel_gpu_commands: Add persistent batch buffer instruction sai.gowtham.ch 2023-12-27 12:20 ` [PATCH i-g-t 2/2] intel/xe_exec_store: Add Persistent subtest sai.gowtham.ch 0 siblings, 2 replies; 5+ messages in thread From: sai.gowtham.ch @ 2023-12-27 12:20 UTC (permalink / raw) To: igt-dev, sai.gowtham.ch From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> This series has two changes as followes: 1. Add persistent batch buffer instruction to the lib. 2. Add Persistent subtest to xe_exec_store. Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Reviewed-by: Janga Rahul Kumar <janga.rahul.kumar@intel.com> Sai Gowtham Ch (2): include/intel_gpu_commands: Add persistent batch buffer instruction intel/xe_exec_store: Add Persistent subtest include/intel_gpu_commands.h | 1 + tests/intel/xe_exec_store.c | 86 ++++++++++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) -- 2.39.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH i-g-t 1/2] include/intel_gpu_commands: Add persistent batch buffer instruction 2023-12-27 12:20 [PATCH i-g-t 0/2] Add Persistent support sai.gowtham.ch @ 2023-12-27 12:20 ` sai.gowtham.ch 2023-12-27 12:20 ` [PATCH i-g-t 2/2] intel/xe_exec_store: Add Persistent subtest sai.gowtham.ch 1 sibling, 0 replies; 5+ messages in thread From: sai.gowtham.ch @ 2023-12-27 12:20 UTC (permalink / raw) To: igt-dev, sai.gowtham.ch From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Add persistent batct buffer instruction. Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Reviewed-by: Janga Rahul Kumar <janga.rahul.kumar@intel.com> --- include/intel_gpu_commands.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/intel_gpu_commands.h b/include/intel_gpu_commands.h index e10507fa7..5a98fb63f 100644 --- a/include/intel_gpu_commands.h +++ b/include/intel_gpu_commands.h @@ -134,6 +134,7 @@ #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) #define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21)) +#define MI_PRT_BATCH_BUFFER_START (0x39 << 23) #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ #define MI_USE_GGTT (1 << 22) /* g4x+ */ #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) -- 2.39.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH i-g-t 2/2] intel/xe_exec_store: Add Persistent subtest 2023-12-27 12:20 [PATCH i-g-t 0/2] Add Persistent support sai.gowtham.ch 2023-12-27 12:20 ` [PATCH i-g-t 1/2] include/intel_gpu_commands: Add persistent batch buffer instruction sai.gowtham.ch @ 2023-12-27 12:20 ` sai.gowtham.ch 1 sibling, 0 replies; 5+ messages in thread From: sai.gowtham.ch @ 2023-12-27 12:20 UTC (permalink / raw) To: igt-dev, sai.gowtham.ch From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Add persistent subtest to validate MI_PRT_BATCH_BUFFER_START. Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Reviewed-by: Janga Rahul Kumar <janga.rahul.kumar@intel.com> --- tests/intel/xe_exec_store.c | 86 +++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c index ec875cffc..870394d3c 100644 --- a/tests/intel/xe_exec_store.c +++ b/tests/intel/xe_exec_store.c @@ -74,6 +74,24 @@ static void cond_batch(struct data *data, uint64_t addr, int value) data->addr = batch_addr; } +static void persistance_batch(struct data *data, uint64_t addr) +{ + int b; + uint64_t batch_offset = (char *)&(data->batch) - (char *)data; + uint64_t batch_addr = addr + batch_offset; + uint64_t prt_offset = (char *)&(data->data) - (char *)data; + uint64_t prt_addr = addr + prt_offset; + + b = 0; + data->batch[b++] = MI_BATCH_BUFFER_START; + data->batch[b++] = MI_PRT_BATCH_BUFFER_START; + data->batch[b++] = prt_addr; + data->batch[b++] = prt_addr >> 32; + data->batch[b++] = MI_BATCH_BUFFER_END; + + data->addr = batch_addr; + +} /** * SUBTEST: basic-store * Description: Basic test to verify store dword. @@ -246,6 +264,71 @@ static void store_cachelines(int fd, struct drm_xe_engine_class_instance *eci, xe_vm_destroy(fd, vm); } +/** + * SUBTEST: persistent + * DESCRIPTION: Validate MI_PRT_BATCH_BUFFER_START functionality + */ +static void persistent(int fd) +{ + struct drm_xe_sync sync = { + .type = DRM_XE_SYNC_TYPE_SYNCOBJ, + .flags = DRM_XE_SYNC_FLAG_SIGNAL, + }; + struct drm_xe_exec exec = { + .num_batch_buffer = 1, + .num_syncs = 1, + .syncs = to_user_pointer(&sync), + }; + struct data *sd_data; + struct data *prt_data; + struct drm_xe_engine *engine; + uint32_t vm, exec_queue, syncobj; + uint32_t sd_batch, prt_batch; + uint64_t addr = 0x100000; + int value = 0x123456; + size_t batch_size = 4096; + + syncobj = syncobj_create(fd, 0); + sync.handle = syncobj; + + vm = xe_vm_create(fd, 0, 0); + batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd), + xe_get_default_alignment(fd)); + + engine = xe_engine(fd, 1); + sd_batch = xe_bo_create(fd, vm, batch_size, + vram_if_possible(fd, engine->instance.gt_id), + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM); + prt_batch = xe_bo_create(fd, vm, batch_size, + vram_if_possible(fd, engine->instance.gt_id), + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM); + + xe_vm_bind_async(fd, vm, engine->instance.gt_id, sd_batch, 0, addr, batch_size, &sync, 1); + sd_data = xe_bo_map(fd, sd_batch, batch_size); + prt_data = xe_bo_map(fd, prt_batch, batch_size); + + store_dword_batch(sd_data, addr, value); + persistance_batch(prt_data, addr); + + exec_queue = xe_exec_queue_create(fd, vm, &engine->instance, 0); + exec.exec_queue_id = exec_queue; + exec.address = prt_data->addr; + sync.flags &= DRM_XE_SYNC_FLAG_SIGNAL; + xe_exec(fd, &exec); + + igt_assert(syncobj_wait(fd, &syncobj, 1, INT64_MAX, 0, NULL)); + igt_assert_eq(sd_data->data, value); + + syncobj_destroy(fd, syncobj); + munmap(sd_data, batch_size); + munmap(prt_data, batch_size); + gem_close(fd, sd_batch); + gem_close(fd, prt_batch); + + xe_exec_queue_destroy(fd, exec_queue); + xe_vm_destroy(fd, vm); +} + igt_main { struct drm_xe_engine_class_instance *hwe; @@ -285,6 +368,9 @@ igt_main xe_for_each_engine(fd, hwe) store_cachelines(fd, hwe, PAGES); + igt_subtest("persistent") + persistent(fd); + igt_fixture { xe_device_put(fd); close(fd); -- 2.39.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH i-g-t 0/2] Add Persistent support. @ 2023-12-22 10:53 sai.gowtham.ch 2023-12-22 10:53 ` [PATCH i-g-t 1/2] include/intel_gpu_commands: Add persistent batch buffer instruction sai.gowtham.ch 0 siblings, 1 reply; 5+ messages in thread From: sai.gowtham.ch @ 2023-12-22 10:53 UTC (permalink / raw) To: igt-dev, sai.gowtham.ch From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> This series has two changes as followes: 1. Add persistent batch buffer instruction to the lib. 2. Add Persistent subtest to xe_exec_store. Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Sai Gowtham Ch (2): include/intel_gpu_commands: Add persistent batch buffer instruction. intel/xe_exec_store: Add Persistent subtest include/intel_gpu_commands.h | 1 + tests/intel/xe_exec_store.c | 86 ++++++++++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) -- 2.39.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH i-g-t 1/2] include/intel_gpu_commands: Add persistent batch buffer instruction. 2023-12-22 10:53 [PATCH i-g-t 0/2] Add Persistent support sai.gowtham.ch @ 2023-12-22 10:53 ` sai.gowtham.ch 2023-12-26 6:54 ` Kumar, Janga Rahul 0 siblings, 1 reply; 5+ messages in thread From: sai.gowtham.ch @ 2023-12-22 10:53 UTC (permalink / raw) To: igt-dev, sai.gowtham.ch From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> Add persistent batct buffer instruction. Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> --- include/intel_gpu_commands.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/intel_gpu_commands.h b/include/intel_gpu_commands.h index e10507fa7..5a98fb63f 100644 --- a/include/intel_gpu_commands.h +++ b/include/intel_gpu_commands.h @@ -134,6 +134,7 @@ #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) #define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21)) +#define MI_PRT_BATCH_BUFFER_START (0x39 << 23) #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ #define MI_USE_GGTT (1 << 22) /* g4x+ */ #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) -- 2.39.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH i-g-t 1/2] include/intel_gpu_commands: Add persistent batch buffer instruction. 2023-12-22 10:53 ` [PATCH i-g-t 1/2] include/intel_gpu_commands: Add persistent batch buffer instruction sai.gowtham.ch @ 2023-12-26 6:54 ` Kumar, Janga Rahul 0 siblings, 0 replies; 5+ messages in thread From: Kumar, Janga Rahul @ 2023-12-26 6:54 UTC (permalink / raw) To: Ch, Sai Gowtham, igt-dev@lists.freedesktop.org, Ch, Sai Gowtham > -----Original Message----- > From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of > sai.gowtham.ch@intel.com > Sent: Friday, December 22, 2023 4:24 PM > To: igt-dev@lists.freedesktop.org; Ch, Sai Gowtham > <sai.gowtham.ch@intel.com> > Subject: [PATCH i-g-t 1/2] include/intel_gpu_commands: Add persistent batch > buffer instruction. Don't end commit title with "." Correct this in all patches wherever required. Thanks, Rahul > > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com> > > Add persistent batct buffer instruction. > > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com> > --- > include/intel_gpu_commands.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/intel_gpu_commands.h b/include/intel_gpu_commands.h > index e10507fa7..5a98fb63f 100644 > --- a/include/intel_gpu_commands.h > +++ b/include/intel_gpu_commands.h > @@ -134,6 +134,7 @@ > #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) > #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) > #define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21)) > +#define MI_PRT_BATCH_BUFFER_START (0x39 << 23) > #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ > #define MI_USE_GGTT (1 << 22) /* g4x+ */ > #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) > -- > 2.39.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-12-27 12:23 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-12-27 12:20 [PATCH i-g-t 0/2] Add Persistent support sai.gowtham.ch 2023-12-27 12:20 ` [PATCH i-g-t 1/2] include/intel_gpu_commands: Add persistent batch buffer instruction sai.gowtham.ch 2023-12-27 12:20 ` [PATCH i-g-t 2/2] intel/xe_exec_store: Add Persistent subtest sai.gowtham.ch -- strict thread matches above, loose matches on Subject: below -- 2023-12-22 10:53 [PATCH i-g-t 0/2] Add Persistent support sai.gowtham.ch 2023-12-22 10:53 ` [PATCH i-g-t 1/2] include/intel_gpu_commands: Add persistent batch buffer instruction sai.gowtham.ch 2023-12-26 6:54 ` Kumar, Janga Rahul
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox