[PATCH i-g-t] i915/gem_exec_whisper: Limit workload

[PATCH i-g-t] i915/gem_exec_whisper: Limit workload

[Jonathan Cavitt]

From: Chris Wilson <chris.p.wilson@linux.intel.com>

For large machines with lots of cpus and many engines, using a workload
that tries to use every engine from every cpu causes massive
oversaturation. The goal of the test workload is to cause saturation on
both engines and cpus so that we apply some pressure on the scheduler to
maintain order, but to do so we only need to ensure each scheduling
queue is saturated and there is sufficient pressure for the CPU
scheduler to push work across cores. We can impose a limit on the number
of threads such that we ensure that every engine and every core should
be occupied. Furthermore we can scale the amount of work submitted by
each thread to keep the total amount of work under a reasonable time
bound.

Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
CC: Bruce Chang <yu.bruce.chang@intel.com>
---
 tests/intel/gem_exec_whisper.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/tests/intel/gem_exec_whisper.c b/tests/intel/gem_exec_whisper.c
index effb473350..429dfc00d5 100644
--- a/tests/intel/gem_exec_whisper.c
+++ b/tests/intel/gem_exec_whisper.c
@@ -294,6 +294,7 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+	const unsigned int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 	struct drm_i915_gem_exec_object2 batches[QLEN];
 	struct drm_i915_gem_relocation_entry inter[QLEN];
 	struct drm_i915_gem_relocation_entry reloc;
@@ -306,18 +307,19 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 	int fds[64];
 	intel_ctx_cfg_t local_cfg;
 	const intel_ctx_t *contexts[64];
-	unsigned nengine;
 	uint32_t batch[16];
 	unsigned int relocations = 0;
 	unsigned int reloc_migrations = 0;
 	unsigned int reloc_interruptions = 0;
 	unsigned int eb_migrations = 0;
 	struct power_sample sample[2];
+	unsigned int nengine;
+	unsigned int nchild;
+	unsigned int qlen;
 	struct igt_power gpu;
 	uint64_t old_offset;
 	int i, n, loc;
 	int debugfs;
-	int nchild;
 	bool has_relocs = gem_has_relocations(fd);
 
 	if (flags & PRIORITY) {
@@ -356,9 +358,13 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 
 	nchild = 1;
 	if (flags & FORKED)
-		nchild *= sysconf(_SC_NPROCESSORS_ONLN);
+		nchild *= ncpus;
 	if (flags & ALL)
 		nchild *= nengine;
+	nchild = min(nchild, 2 * max(ncpus, nengine));
+	qlen = max(2u, QLEN * nengine / (nchild + nengine - 1));
+	igt_info("Using nchild:%d (out of ncpus:%d and nengine:%d), with a qlen:%d\n",
+		 nchild, ncpus, nengine, qlen);
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_power_get_energy(&gpu, &sample[0]);
@@ -448,19 +454,19 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 		}
 
 		memset(batches, 0, sizeof(batches));
-		for (n = 0; n < QLEN; n++) {
+		for (n = 0; n < qlen; n++) {
 			batches[n].handle = gem_create(fd, 4096);
 			gem_write(fd, batches[n].handle, 0, &bbe, sizeof(bbe));
 		}
 		execbuf.buffers_ptr = to_user_pointer(batches);
-		execbuf.buffer_count = QLEN;
+		execbuf.buffer_count = qlen;
 		gem_execbuf(fd, &execbuf);
 
 		execbuf.buffers_ptr = to_user_pointer(tmp);
 		execbuf.buffer_count = 2;
 
 		old_offset = store.offset;
-		for (n = 0; n < QLEN; n++) {
+		for (n = 0; n < qlen; n++) {
 			if (gen >= 8) {
 				batch[1] = old_offset + loc;
 				batch[2] = (old_offset + loc) >> 32;
@@ -525,8 +531,8 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 					gem_sync(fd, tmp[0].handle);
 				scratch = tmp[0];
 
-				gem_write(fd, batches[QLEN-1].handle, loc, &pass, sizeof(pass));
-				for (n = QLEN; --n >= 1; ) {
+				gem_write(fd, batches[qlen-1].handle, loc, &pass, sizeof(pass));
+				for (n = qlen; --n >= 1; ) {
 					uint32_t handle[2] = {};
 					int this_fd = fd;
 
@@ -648,7 +654,7 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 				gem_vm_destroy(fd, local_cfg.vm);
 			}
 		}
-		for (n = 0; n < QLEN; n++)
+		for (n = 0; n < qlen; n++)
 			gem_close(fd, batches[n].handle);
 		if (flags & FDS) {
 			for (n = 0; n < 64; n++)
-- 
2.25.1

✗ Fi.CI.BAT: failure for i915/gem_exec_whisper: Limit workload

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5259 bytes --]

== Series Details ==

Series: i915/gem_exec_whisper: Limit workload
URL   : https://patchwork.freedesktop.org/series/131448/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14464 -> IGTPW_10877
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_10877 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_10877, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/index.html

Participating hosts (40 -> 36)
------------------------------

  Missing    (4): bat-dg1-7 bat-kbl-2 fi-cfl-8109u fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_10877:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_addfb_basic@addfb25-4-tiled:
    - fi-apl-guc:         [PASS][1] -> [DMESG-WARN][2] +57 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14464/fi-apl-guc/igt@kms_addfb_basic@addfb25-4-tiled.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/fi-apl-guc/igt@kms_addfb_basic@addfb25-4-tiled.html

  
Known issues
------------

  Here are the changes found in IGTPW_10877 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-apl-guc:         [PASS][3] -> [DMESG-WARN][4] ([i915#180] / [i915#8585])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14464/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/fi-apl-guc/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@hangcheck:
    - bat-rpls-3:         [PASS][5] -> [DMESG-WARN][6] ([i915#5591])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14464/bat-rpls-3/igt@i915_selftest@live@hangcheck.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/bat-rpls-3/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@reset:
    - fi-apl-guc:         [PASS][7] -> [DMESG-WARN][8] ([i915#9730]) +36 other tests dmesg-warn
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14464/fi-apl-guc/igt@i915_selftest@live@reset.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/fi-apl-guc/igt@i915_selftest@live@reset.html

  * igt@kms_flip@basic-flip-vs-dpms@c-dp1:
    - fi-apl-guc:         [PASS][9] -> [DMESG-WARN][10] ([i915#8585]) +18 other tests dmesg-warn
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14464/fi-apl-guc/igt@kms_flip@basic-flip-vs-dpms@c-dp1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/fi-apl-guc/igt@kms_flip@basic-flip-vs-dpms@c-dp1.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1:
    - fi-apl-guc:         [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14464/fi-apl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/fi-apl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         NOTRUN -> [SKIP][13] ([i915#9197]) +3 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@vgem_basic@unload:
    - fi-kbl-8809g:       [PASS][14] -> [INCOMPLETE][15] ([i915#10454])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14464/fi-kbl-8809g/igt@vgem_basic@unload.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/fi-kbl-8809g/igt@vgem_basic@unload.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_mocs:
    - bat-dg2-14:         [ABORT][16] ([i915#10366]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14464/bat-dg2-14/igt@i915_selftest@live@gt_mocs.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/bat-dg2-14/igt@i915_selftest@live@gt_mocs.html

  
  [i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
  [i915#10454]: https://gitlab.freedesktop.org/drm/intel/issues/10454
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#8585]: https://gitlab.freedesktop.org/drm/intel/issues/8585
  [i915#9197]: https://gitlab.freedesktop.org/drm/intel/issues/9197
  [i915#9730]: https://gitlab.freedesktop.org/drm/intel/issues/9730


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7775 -> IGTPW_10877

  CI-20190529: 20190529
  CI_DRM_14464: ad4a10c6d0e21df4bd830c20c96b795ae2d03962 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_10877: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/index.html
  IGT_7775: 0ee4074685c1e184f2d3612ea6eb4d126f9a2e23 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/index.html

[-- Attachment #2: Type: text/html, Size: 6143 bytes --]

✓ CI.xeBAT: success for i915/gem_exec_whisper: Limit workload

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1639 bytes --]

== Series Details ==

Series: i915/gem_exec_whisper: Limit workload
URL   : https://patchwork.freedesktop.org/series/131448/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7775_BAT -> XEIGTPW_10877_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_10877_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_frontbuffer_tracking@basic:
    - bat-adlp-7:         [FAIL][1] ([Intel XE#616]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7775/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10877/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html

  
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616


Build changes
-------------

  * IGT: IGT_7775 -> IGTPW_10877
  * Linux: xe-972-0cd99ca612f004f19c35f4966a584f0a729bbc31 -> xe-973-ad4a10c6d0e21df4bd830c20c96b795ae2d03962

  IGTPW_10877: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10877/index.html
  IGT_7775: 0ee4074685c1e184f2d3612ea6eb4d126f9a2e23 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-972-0cd99ca612f004f19c35f4966a584f0a729bbc31: 0cd99ca612f004f19c35f4966a584f0a729bbc31
  xe-973-ad4a10c6d0e21df4bd830c20c96b795ae2d03962: ad4a10c6d0e21df4bd830c20c96b795ae2d03962

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10877/index.html

[-- Attachment #2: Type: text/html, Size: 2216 bytes --]

Re: [PATCH i-g-t] i915/gem_exec_whisper: Limit workload

[Nirmoy Das]

On 3/21/2024 7:30 PM, Jonathan Cavitt wrote:
> From: Chris Wilson <chris.p.wilson@linux.intel.com>
>
> For large machines with lots of cpus and many engines, using a workload
> that tries to use every engine from every cpu causes massive
> oversaturation. The goal of the test workload is to cause saturation on
> both engines and cpus so that we apply some pressure on the scheduler to
> maintain order, but to do so we only need to ensure each scheduling
> queue is saturated and there is sufficient pressure for the CPU
> scheduler to push work across cores. We can impose a limit on the number
> of threads such that we ensure that every engine and every core should
> be occupied. Furthermore we can scale the amount of work submitted by
> each thread to keep the total amount of work under a reasonable time
> bound.
>
> Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>

Need your sign off here. Otherwise

Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>

> CC: Bruce Chang <yu.bruce.chang@intel.com>
> ---
>   tests/intel/gem_exec_whisper.c | 24 +++++++++++++++---------
>   1 file changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/tests/intel/gem_exec_whisper.c b/tests/intel/gem_exec_whisper.c
> index effb473350..429dfc00d5 100644
> --- a/tests/intel/gem_exec_whisper.c
> +++ b/tests/intel/gem_exec_whisper.c
> @@ -294,6 +294,7 @@ static void whisper(int fd, const intel_ctx_t *ctx,
>   {
>   	const uint32_t bbe = MI_BATCH_BUFFER_END;
>   	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> +	const unsigned int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
>   	struct drm_i915_gem_exec_object2 batches[QLEN];
>   	struct drm_i915_gem_relocation_entry inter[QLEN];
>   	struct drm_i915_gem_relocation_entry reloc;
> @@ -306,18 +307,19 @@ static void whisper(int fd, const intel_ctx_t *ctx,
>   	int fds[64];
>   	intel_ctx_cfg_t local_cfg;
>   	const intel_ctx_t *contexts[64];
> -	unsigned nengine;
>   	uint32_t batch[16];
>   	unsigned int relocations = 0;
>   	unsigned int reloc_migrations = 0;
>   	unsigned int reloc_interruptions = 0;
>   	unsigned int eb_migrations = 0;
>   	struct power_sample sample[2];
> +	unsigned int nengine;
> +	unsigned int nchild;
> +	unsigned int qlen;
>   	struct igt_power gpu;
>   	uint64_t old_offset;
>   	int i, n, loc;
>   	int debugfs;
> -	int nchild;
>   	bool has_relocs = gem_has_relocations(fd);
>   
>   	if (flags & PRIORITY) {
> @@ -356,9 +358,13 @@ static void whisper(int fd, const intel_ctx_t *ctx,
>   
>   	nchild = 1;
>   	if (flags & FORKED)
> -		nchild *= sysconf(_SC_NPROCESSORS_ONLN);
> +		nchild *= ncpus;
>   	if (flags & ALL)
>   		nchild *= nengine;
> +	nchild = min(nchild, 2 * max(ncpus, nengine));
> +	qlen = max(2u, QLEN * nengine / (nchild + nengine - 1));
> +	igt_info("Using nchild:%d (out of ncpus:%d and nengine:%d), with a qlen:%d\n",
> +		 nchild, ncpus, nengine, qlen);
>   
>   	intel_detect_and_clear_missed_interrupts(fd);
>   	igt_power_get_energy(&gpu, &sample[0]);
> @@ -448,19 +454,19 @@ static void whisper(int fd, const intel_ctx_t *ctx,
>   		}
>   
>   		memset(batches, 0, sizeof(batches));
> -		for (n = 0; n < QLEN; n++) {
> +		for (n = 0; n < qlen; n++) {
>   			batches[n].handle = gem_create(fd, 4096);
>   			gem_write(fd, batches[n].handle, 0, &bbe, sizeof(bbe));
>   		}
>   		execbuf.buffers_ptr = to_user_pointer(batches);
> -		execbuf.buffer_count = QLEN;
> +		execbuf.buffer_count = qlen;
>   		gem_execbuf(fd, &execbuf);
>   
>   		execbuf.buffers_ptr = to_user_pointer(tmp);
>   		execbuf.buffer_count = 2;
>   
>   		old_offset = store.offset;
> -		for (n = 0; n < QLEN; n++) {
> +		for (n = 0; n < qlen; n++) {
>   			if (gen >= 8) {
>   				batch[1] = old_offset + loc;
>   				batch[2] = (old_offset + loc) >> 32;
> @@ -525,8 +531,8 @@ static void whisper(int fd, const intel_ctx_t *ctx,
>   					gem_sync(fd, tmp[0].handle);
>   				scratch = tmp[0];
>   
> -				gem_write(fd, batches[QLEN-1].handle, loc, &pass, sizeof(pass));
> -				for (n = QLEN; --n >= 1; ) {
> +				gem_write(fd, batches[qlen-1].handle, loc, &pass, sizeof(pass));
> +				for (n = qlen; --n >= 1; ) {
>   					uint32_t handle[2] = {};
>   					int this_fd = fd;
>   
> @@ -648,7 +654,7 @@ static void whisper(int fd, const intel_ctx_t *ctx,
>   				gem_vm_destroy(fd, local_cfg.vm);
>   			}
>   		}
> -		for (n = 0; n < QLEN; n++)
> +		for (n = 0; n < qlen; n++)
>   			gem_close(fd, batches[n].handle);
>   		if (flags & FDS) {
>   			for (n = 0; n < 64; n++)

[PATCH i-g-t] i915/gem_exec_whisper: Limit workload

[Jonathan Cavitt]

From: Chris Wilson <chris.p.wilson@linux.intel.com>

For large machines with lots of cpus and many engines, using a workload
that tries to use every engine from every cpu causes massive
oversaturation. The goal of the test workload is to cause saturation on
both engines and cpus so that we apply some pressure on the scheduler to
maintain order, but to do so we only need to ensure each scheduling
queue is saturated and there is sufficient pressure for the CPU
scheduler to push work across cores. We can impose a limit on the number
of threads such that we ensure that every engine and every core should
be occupied. Furthermore we can scale the amount of work submitted by
each thread to keep the total amount of work under a reasonable time
bound.

Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>

---
 tests/intel/gem_exec_whisper.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/tests/intel/gem_exec_whisper.c b/tests/intel/gem_exec_whisper.c
index effb473350..429dfc00d5 100644
--- a/tests/intel/gem_exec_whisper.c
+++ b/tests/intel/gem_exec_whisper.c
@@ -294,6 +294,7 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+	const unsigned int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 	struct drm_i915_gem_exec_object2 batches[QLEN];
 	struct drm_i915_gem_relocation_entry inter[QLEN];
 	struct drm_i915_gem_relocation_entry reloc;
@@ -306,18 +307,19 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 	int fds[64];
 	intel_ctx_cfg_t local_cfg;
 	const intel_ctx_t *contexts[64];
-	unsigned nengine;
 	uint32_t batch[16];
 	unsigned int relocations = 0;
 	unsigned int reloc_migrations = 0;
 	unsigned int reloc_interruptions = 0;
 	unsigned int eb_migrations = 0;
 	struct power_sample sample[2];
+	unsigned int nengine;
+	unsigned int nchild;
+	unsigned int qlen;
 	struct igt_power gpu;
 	uint64_t old_offset;
 	int i, n, loc;
 	int debugfs;
-	int nchild;
 	bool has_relocs = gem_has_relocations(fd);
 
 	if (flags & PRIORITY) {
@@ -356,9 +358,13 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 
 	nchild = 1;
 	if (flags & FORKED)
-		nchild *= sysconf(_SC_NPROCESSORS_ONLN);
+		nchild *= ncpus;
 	if (flags & ALL)
 		nchild *= nengine;
+	nchild = min(nchild, 2 * max(ncpus, nengine));
+	qlen = max(2u, QLEN * nengine / (nchild + nengine - 1));
+	igt_info("Using nchild:%d (out of ncpus:%d and nengine:%d), with a qlen:%d\n",
+		 nchild, ncpus, nengine, qlen);
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_power_get_energy(&gpu, &sample[0]);
@@ -448,19 +454,19 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 		}
 
 		memset(batches, 0, sizeof(batches));
-		for (n = 0; n < QLEN; n++) {
+		for (n = 0; n < qlen; n++) {
 			batches[n].handle = gem_create(fd, 4096);
 			gem_write(fd, batches[n].handle, 0, &bbe, sizeof(bbe));
 		}
 		execbuf.buffers_ptr = to_user_pointer(batches);
-		execbuf.buffer_count = QLEN;
+		execbuf.buffer_count = qlen;
 		gem_execbuf(fd, &execbuf);
 
 		execbuf.buffers_ptr = to_user_pointer(tmp);
 		execbuf.buffer_count = 2;
 
 		old_offset = store.offset;
-		for (n = 0; n < QLEN; n++) {
+		for (n = 0; n < qlen; n++) {
 			if (gen >= 8) {
 				batch[1] = old_offset + loc;
 				batch[2] = (old_offset + loc) >> 32;
@@ -525,8 +531,8 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 					gem_sync(fd, tmp[0].handle);
 				scratch = tmp[0];
 
-				gem_write(fd, batches[QLEN-1].handle, loc, &pass, sizeof(pass));
-				for (n = QLEN; --n >= 1; ) {
+				gem_write(fd, batches[qlen-1].handle, loc, &pass, sizeof(pass));
+				for (n = qlen; --n >= 1; ) {
 					uint32_t handle[2] = {};
 					int this_fd = fd;
 
@@ -648,7 +654,7 @@ static void whisper(int fd, const intel_ctx_t *ctx,
 				gem_vm_destroy(fd, local_cfg.vm);
 			}
 		}
-		for (n = 0; n < QLEN; n++)
+		for (n = 0; n < qlen; n++)
 			gem_close(fd, batches[n].handle);
 		if (flags & FDS) {
 			for (n = 0; n < 64; n++)
-- 
2.25.1