[PATCH i-g-t 0/2] lib/xe_mmio: Introduce Xe MMIO lib

[PATCH i-g-t 0/2] lib/xe_mmio: Introduce Xe MMIO lib

[Piórkowski, Piotr]

From: Piotr Piórkowski <piotr.piorkowski@intel.com>

The series includes a simple set of helpers, dedicated to Xe, allowing
access to registers and GGTT, on various tile, using MMIO BAR access.

Piotr Piórkowski (2):
  lib/intel_mmio: Map the whole BAR0 for gen12+
  lib/xe_mmio: Introduce Xe MMIO lib

 lib/intel_mmio.c  |   2 +-
 lib/meson.build   |   3 +-
 lib/xe/xe_mmio.c  | 207 ++++++++++++++++++++++++++++++++++++++++++++++
 lib/xe/xe_mmio.h  |  37 +++++++++
 lib/xe/xe_query.c |  19 +++++
 lib/xe/xe_query.h |   1 +
 6 files changed, 267 insertions(+), 2 deletions(-)
 create mode 100644 lib/xe/xe_mmio.c
 create mode 100644 lib/xe/xe_mmio.h

-- 
2.34.1

[PATCH i-g-t 1/2] lib/intel_mmio: Map the whole BAR0 for gen12+

[Piórkowski, Piotr]

From: Piotr Piórkowski <piotr.piorkowski@intel.com>

Previously, we limited BAR0 mapping to register space only because of
the potential conflict with wc mapping for the GTT region.
For gen12+ platforms, the size of BAR0 varies due to the different amount
of tile.
And as for gen11+ platforms, we can already map the whole BAR0 as uc,
so let's map the whole BAR0, without artificial limitations.

Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
---
 lib/intel_mmio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c
index 4b6820787..31975727e 100644
--- a/lib/intel_mmio.c
+++ b/lib/intel_mmio.c
@@ -154,7 +154,7 @@ intel_mmio_use_pci_bar(struct intel_mmio_data *mmio_data, struct pci_device *pci
 
 	gen = intel_gen(devid);
 	if (gen >= 12)
-		mmio_size = 8 * 1024 * 1024;
+		mmio_size = pci_dev->regions[mmio_bar].size;
 	else if (gen >= 5)
 		mmio_size = 2 * 1024 * 1024;
 	else
-- 
2.34.1

[PATCH i-g-t 2/2] lib/xe_mmio: Introduce Xe MMIO lib

[Piórkowski, Piotr]

From: Piotr Piórkowski <piotr.piorkowski@intel.com>

Currently in IGT we have a library intel_mmio for simple MMIO operations
on intel GPU devices, but it is limited only to accessing registers,
has a lot of legacy code related to the i915 and offers no support for
multi tile.
Let's reuse the memory mapping from the previous library and add separate
helpers, dedicated to Xe, for registers and GGTT access that support multi
tile.

Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
---
 lib/meson.build   |   3 +-
 lib/xe/xe_mmio.c  | 207 ++++++++++++++++++++++++++++++++++++++++++++++
 lib/xe/xe_mmio.h  |  37 +++++++++
 lib/xe/xe_query.c |  19 +++++
 lib/xe/xe_query.h |   1 +
 5 files changed, 266 insertions(+), 1 deletion(-)
 create mode 100644 lib/xe/xe_mmio.c
 create mode 100644 lib/xe/xe_mmio.h

diff --git a/lib/meson.build b/lib/meson.build
index 934bac5c6..2f9666846 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -110,6 +110,7 @@ lib_sources = [
 	'igt_dsc.c',
 	'xe/xe_gt.c',
 	'xe/xe_ioctl.c',
+	'xe/xe_mmio.c',
 	'xe/xe_query.c',
 	'xe/xe_spin.c',
 	'xe/xe_util.c',
@@ -162,7 +163,7 @@ if libdrm_amdgpu.found()
 		lib_sources +=[ 'amdgpu/amd_dispatch.c',]
 	else
 		warning('libdrm <= 2.4.99 found, amdgpu_cs_query_reset_state2 not applicable')
-	endif	
+	endif
 endif
 
 if libunwind.found()
diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
new file mode 100644
index 000000000..bd4227f25
--- /dev/null
+++ b/lib/xe/xe_mmio.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2024 Intel Corporation. All rights reserved.
+ */
+
+#include "igt_device.h"
+
+#include "xe/xe_mmio.h"
+#include "xe/xe_query.h"
+
+/**
+ * xe_mmio_vf_access_init:
+ * @pf_fd: xe device file descriptor
+ * @vf_id: PCI virtual function number (0 if native or PF itself)
+ * @mmio: xe mmio structure for IO operations
+ *
+ * This initializes the xe mmio structure, and maps the MMIO BAR owned by
+ * the specified virtual function associated with @pf_fd.
+ */
+void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio)
+{
+	struct pci_device *pci_dev = __igt_device_get_pci_device(pf_fd, vf_id);
+
+	igt_assert_f(pci_dev, "No PCI device found for VF%u\n", vf_id);
+
+	intel_mmio_use_pci_bar(&mmio->intel_mmio, pci_dev);
+
+	igt_assert(!mmio->intel_mmio.igt_mmio);
+
+	mmio->fd = pf_fd;
+	mmio->intel_mmio.safe = false;
+	mmio->intel_mmio.pci_device_id = pci_dev->device_id;
+}
+
+/**
+ * xe_mmio_access_init:
+ * @pf_fd: xe device file descriptor
+ * @mmio: xe mmio structure for IO operations
+ *
+ * This initializes the xe mmio structure, and maps MMIO BAR for @pf_fd device.
+ */
+void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio)
+{
+	xe_mmio_vf_access_init(pf_fd, 0, mmio);
+}
+
+/**
+ * xe_mmio_access_fini:
+ * @mmio: xe mmio structure for IO operations
+ *
+ * Clean up the mmio access helper initialized with
+ * xe_mmio_access_init()/xe_mmio_vf_access_init().
+ */
+void xe_mmio_access_fini(struct xe_mmio *mmio)
+{
+	mmio->intel_mmio.pci_device_id = 0;
+	intel_mmio_unmap_pci_bar(&mmio->intel_mmio);
+	igt_pci_system_cleanup();
+}
+
+/**
+ * xe_mmio_read32:
+ * @mmio: xe mmio structure for IO operations
+ * @reg: mmio register offset
+ *
+ * 32-bit read of the register at @offset.
+ *
+ * Returns:
+ * The value read from the register.
+ */
+uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t reg)
+{
+	return ioread32(mmio->intel_mmio.igt_mmio, reg);
+}
+
+/**
+ * xe_mmio_read64:
+ * @mmio: xe mmio structure for IO operations
+ * @reg: mmio register offset
+ *
+ * 64-bit read of the register at @offset.
+ *
+ * Returns:
+ * The value read from the register.
+ */
+uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t reg)
+{
+	return ioread64(mmio->intel_mmio.igt_mmio, reg);
+}
+
+/**
+ * xe_mmio_write32:
+ * @mmio: xe mmio structure for IO operations
+ * @reg: mmio register offset
+ * @val: value to write
+ *
+ * 32-bit write to the register at @offset.
+ */
+void xe_mmio_write32(struct xe_mmio *mmio, uint32_t reg, uint32_t val)
+{
+	return iowrite32(mmio->intel_mmio.igt_mmio, reg, val);
+}
+
+/**
+ * xe_mmio_write64:
+ * @mmio: xe mmio structure for IO operations
+ * @reg: mmio register offset
+ * @val: value to write
+ *
+ * 64-bit write to the register at @offset.
+ */
+void xe_mmio_write64(struct xe_mmio *mmio, uint32_t reg, uint64_t val)
+{
+	return iowrite64(mmio->intel_mmio.igt_mmio, reg, val);
+}
+
+/**
+ * xe_mmio_gt_read32:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @reg: mmio register offset in tile to which @gt belongs
+ *
+ * 32-bit read of the register at @offset in tile to which @gt belongs.
+ *
+ * Returns:
+ * The value read from the register.
+ */
+uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t reg)
+{
+	return xe_mmio_read32(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
+}
+
+/**
+ * xe_mmio_gt_read64:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @reg: mmio register offset in tile to which @gt belongs
+ *
+ * 64-bit read of the register at @offset in tile to which @gt belongs.
+ *
+ * Returns:
+ * The value read from the register.
+ */
+uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t reg)
+{
+	return xe_mmio_read64(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
+}
+
+/**
+ * xe_mmio_gt_write32:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @reg: mmio register offset
+ * @val: value to write
+ *
+ * 32-bit write to the register at @offset in tile to which @gt belongs.
+ */
+void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t reg, uint32_t val)
+{
+	return xe_mmio_write32(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
+			       val);
+}
+
+/**
+ * xe_mmio_gt_write64:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @reg: mmio register offset
+ * @val: value to write
+ *
+ * 64-bit write to the register at @offset in tile to which @gt belongs.
+ */
+void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t reg, uint64_t val)
+{
+	return xe_mmio_write64(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
+			       val);
+}
+
+/**
+ * xe_mmio_ggtt_read:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
+ *
+ * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
+ *
+ * Returns:
+ * The value read from the register.
+ */
+xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t offset)
+{
+	return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
+}
+
+/**
+ * xe_mmio_ggtt_write:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
+ * @pte: PTE value to write
+ *
+ * Write PTE value at GGTT @offset in tile to which @gt belongs.
+ */
+void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset, xe_ggtt_pte_t pte)
+{
+	return xe_mmio_gt_write64(mmio, gt, offset + GGTT_OFFSET_IN_TILE, pte);
+}
diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
new file mode 100644
index 000000000..ed45040bd
--- /dev/null
+++ b/lib/xe/xe_mmio.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2024 Intel Corporation. All rights reserved.
+ */
+
+#include "lib/intel_io.h"
+#include "lib/igt_sizes.h"
+
+#define TILE_MMIO_SIZE		SZ_16M
+#define GGTT_OFFSET_IN_TILE	SZ_8M
+
+typedef uint64_t xe_ggtt_pte_t;
+
+struct xe_mmio {
+	int fd;
+	unsigned int vf_id;
+	struct intel_mmio_data intel_mmio;
+};
+
+void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio);
+void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio);
+void xe_mmio_access_fini(struct xe_mmio *mmio);
+
+uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t reg);
+uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t reg);
+
+void xe_mmio_write32(struct xe_mmio *mmio, uint32_t reg, uint32_t val);
+void xe_mmio_write64(struct xe_mmio *mmio, uint32_t reg, uint64_t val);
+
+uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t reg);
+uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t reg);
+
+void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t reg, uint32_t val);
+void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t reg, uint64_t val);
+
+xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
+void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 53a2b4386..c885e3a79 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -731,6 +731,25 @@ bool xe_is_media_gt(int fd, int gt)
 	return false;
 }
 
+/**
+ * xe_gt_to_tile_id:
+ * @fd: xe device fd
+ * @gt: gt id
+ *
+ * Returns tile id for given @gt.
+ */
+int xe_gt_get_tile_id(int fd, int gt)
+{
+	struct xe_device *xe_dev;
+
+	xe_dev = find_in_cache(fd);
+
+	igt_assert(xe_dev);
+	igt_assert(gt < xe_number_gt(fd));
+
+	return xe_dev->gt_list->gt_list[gt].tile_id;
+}
+
 igt_constructor
 {
 	xe_device_cache_init();
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 82af2706d..b1b3a989e 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -99,6 +99,7 @@ const char *xe_engine_class_string(uint32_t engine_class);
 bool xe_has_engine_class(int fd, uint16_t engine_class);
 bool xe_has_media_gt(int fd);
 bool xe_is_media_gt(int fd, int gt);
+int xe_gt_get_tile_id(int fd, int gt);
 
 struct xe_device *xe_device_get(int fd);
 void xe_device_put(int fd);
-- 
2.34.1

Re: [PATCH i-g-t 2/2] lib/xe_mmio: Introduce Xe MMIO lib

[Kamil Konieczny]

Hi Piórkowski,,
On 2024-03-25 at 16:57:09 +0100, Piórkowski, Piotr wrote:
> From: Piotr Piórkowski <piotr.piorkowski@intel.com>
> 
> Currently in IGT we have a library intel_mmio for simple MMIO operations
> on intel GPU devices, but it is limited only to accessing registers,
> has a lot of legacy code related to the i915 and offers no support for
> multi tile.
> Let's reuse the memory mapping from the previous library and add separate
> helpers, dedicated to Xe, for registers and GGTT access that support multi
> tile.
> 
> Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
> ---
>  lib/meson.build   |   3 +-
>  lib/xe/xe_mmio.c  | 207 ++++++++++++++++++++++++++++++++++++++++++++++
>  lib/xe/xe_mmio.h  |  37 +++++++++
>  lib/xe/xe_query.c |  19 +++++
>  lib/xe/xe_query.h |   1 +
>  5 files changed, 266 insertions(+), 1 deletion(-)
>  create mode 100644 lib/xe/xe_mmio.c
>  create mode 100644 lib/xe/xe_mmio.h
> 
> diff --git a/lib/meson.build b/lib/meson.build
> index 934bac5c6..2f9666846 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -110,6 +110,7 @@ lib_sources = [
>  	'igt_dsc.c',
>  	'xe/xe_gt.c',
>  	'xe/xe_ioctl.c',
> +	'xe/xe_mmio.c',
>  	'xe/xe_query.c',
>  	'xe/xe_spin.c',
>  	'xe/xe_util.c',
> @@ -162,7 +163,7 @@ if libdrm_amdgpu.found()
>  		lib_sources +=[ 'amdgpu/amd_dispatch.c',]
>  	else
>  		warning('libdrm <= 2.4.99 found, amdgpu_cs_query_reset_state2 not applicable')
> -	endif	
> +	endif
>  endif
>  
>  if libunwind.found()
> diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
> new file mode 100644
> index 000000000..bd4227f25
> --- /dev/null
> +++ b/lib/xe/xe_mmio.c
> @@ -0,0 +1,207 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2024 Intel Corporation. All rights reserved.
> + */
> +
> +#include "igt_device.h"
> +
> +#include "xe/xe_mmio.h"
> +#include "xe/xe_query.h"
> +
> +/**
> + * xe_mmio_vf_access_init:
> + * @pf_fd: xe device file descriptor
> + * @vf_id: PCI virtual function number (0 if native or PF itself)
> + * @mmio: xe mmio structure for IO operations
> + *
> + * This initializes the xe mmio structure, and maps the MMIO BAR owned by
> + * the specified virtual function associated with @pf_fd.
> + */
> +void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio)
> +{
> +	struct pci_device *pci_dev = __igt_device_get_pci_device(pf_fd, vf_id);
> +
> +	igt_assert_f(pci_dev, "No PCI device found for VF%u\n", vf_id);
> +
> +	intel_mmio_use_pci_bar(&mmio->intel_mmio, pci_dev);
> +
> +	igt_assert(!mmio->intel_mmio.igt_mmio);
> +
> +	mmio->fd = pf_fd;
> +	mmio->intel_mmio.safe = false;
> +	mmio->intel_mmio.pci_device_id = pci_dev->device_id;
> +}
> +
> +/**
> + * xe_mmio_access_init:
> + * @pf_fd: xe device file descriptor
> + * @mmio: xe mmio structure for IO operations
> + *
> + * This initializes the xe mmio structure, and maps MMIO BAR for @pf_fd device.
> + */
> +void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio)
> +{
> +	xe_mmio_vf_access_init(pf_fd, 0, mmio);
> +}
> +
> +/**
> + * xe_mmio_access_fini:
> + * @mmio: xe mmio structure for IO operations
> + *
> + * Clean up the mmio access helper initialized with
> + * xe_mmio_access_init()/xe_mmio_vf_access_init().
> + */
> +void xe_mmio_access_fini(struct xe_mmio *mmio)
> +{
> +	mmio->intel_mmio.pci_device_id = 0;
> +	intel_mmio_unmap_pci_bar(&mmio->intel_mmio);
> +	igt_pci_system_cleanup();
> +}
> +
> +/**
> + * xe_mmio_read32:
> + * @mmio: xe mmio structure for IO operations
> + * @reg: mmio register offset
> + *
> + * 32-bit read of the register at @offset.
> + *
> + * Returns:
> + * The value read from the register.
> + */
> +uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t reg)
> +{
> +	return ioread32(mmio->intel_mmio.igt_mmio, reg);
> +}
> +
> +/**
> + * xe_mmio_read64:
> + * @mmio: xe mmio structure for IO operations
> + * @reg: mmio register offset
> + *
> + * 64-bit read of the register at @offset.
> + *
> + * Returns:
> + * The value read from the register.
> + */
> +uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t reg)
> +{
> +	return ioread64(mmio->intel_mmio.igt_mmio, reg);
> +}
> +
> +/**
> + * xe_mmio_write32:
> + * @mmio: xe mmio structure for IO operations
> + * @reg: mmio register offset
> + * @val: value to write
> + *
> + * 32-bit write to the register at @offset.
> + */
> +void xe_mmio_write32(struct xe_mmio *mmio, uint32_t reg, uint32_t val)
> +{
> +	return iowrite32(mmio->intel_mmio.igt_mmio, reg, val);
> +}
> +
> +/**
> + * xe_mmio_write64:
> + * @mmio: xe mmio structure for IO operations
> + * @reg: mmio register offset
> + * @val: value to write
> + *
> + * 64-bit write to the register at @offset.
> + */
> +void xe_mmio_write64(struct xe_mmio *mmio, uint32_t reg, uint64_t val)
> +{
> +	return iowrite64(mmio->intel_mmio.igt_mmio, reg, val);
> +}
> +
> +/**
> + * xe_mmio_gt_read32:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @reg: mmio register offset in tile to which @gt belongs
> + *
> + * 32-bit read of the register at @offset in tile to which @gt belongs.
> + *
> + * Returns:
> + * The value read from the register.
> + */
> +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t reg)
> +{
> +	return xe_mmio_read32(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
> +}
> +
> +/**
> + * xe_mmio_gt_read64:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @reg: mmio register offset in tile to which @gt belongs
> + *
> + * 64-bit read of the register at @offset in tile to which @gt belongs.
> + *
> + * Returns:
> + * The value read from the register.
> + */
> +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t reg)
> +{
> +	return xe_mmio_read64(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
> +}
> +
> +/**
> + * xe_mmio_gt_write32:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @reg: mmio register offset
> + * @val: value to write
> + *
> + * 32-bit write to the register at @offset in tile to which @gt belongs.
> + */
> +void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t reg, uint32_t val)
> +{
> +	return xe_mmio_write32(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
> +			       val);
> +}
> +
> +/**
> + * xe_mmio_gt_write64:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @reg: mmio register offset
> + * @val: value to write
> + *
> + * 64-bit write to the register at @offset in tile to which @gt belongs.
> + */
> +void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t reg, uint64_t val)
> +{
> +	return xe_mmio_write64(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
> +			       val);
> +}
> +
> +/**
> + * xe_mmio_ggtt_read:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
> + *
> + * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
> + *
> + * Returns:
> + * The value read from the register.
> + */
> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t offset)
> +{
> +	return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
> +}
> +
> +/**
> + * xe_mmio_ggtt_write:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
> + * @pte: PTE value to write
> + *
> + * Write PTE value at GGTT @offset in tile to which @gt belongs.
> + */
> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset, xe_ggtt_pte_t pte)
> +{
> +	return xe_mmio_gt_write64(mmio, gt, offset + GGTT_OFFSET_IN_TILE, pte);
> +}
> diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
> new file mode 100644
> index 000000000..ed45040bd
> --- /dev/null
> +++ b/lib/xe/xe_mmio.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2024 Intel Corporation. All rights reserved.
> + */

Add here standard ifdef/define and at end of file endif:

#ifndef IGT_XE_MMIO_H
#define IGT_XE_MMIO_H

Regards,
Kamil

> +
> +#include "lib/intel_io.h"
> +#include "lib/igt_sizes.h"
> +
> +#define TILE_MMIO_SIZE		SZ_16M
> +#define GGTT_OFFSET_IN_TILE	SZ_8M
> +
> +typedef uint64_t xe_ggtt_pte_t;
> +
> +struct xe_mmio {
> +	int fd;
> +	unsigned int vf_id;
> +	struct intel_mmio_data intel_mmio;
> +};
> +
> +void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio);
> +void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio);
> +void xe_mmio_access_fini(struct xe_mmio *mmio);
> +
> +uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t reg);
> +uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t reg);
> +
> +void xe_mmio_write32(struct xe_mmio *mmio, uint32_t reg, uint32_t val);
> +void xe_mmio_write64(struct xe_mmio *mmio, uint32_t reg, uint64_t val);
> +
> +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t reg);
> +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t reg);
> +
> +void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t reg, uint32_t val);
> +void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t reg, uint64_t val);
> +
> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index 53a2b4386..c885e3a79 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -731,6 +731,25 @@ bool xe_is_media_gt(int fd, int gt)
>  	return false;
>  }
>  
> +/**
> + * xe_gt_to_tile_id:
> + * @fd: xe device fd
> + * @gt: gt id
> + *
> + * Returns tile id for given @gt.
> + */
> +int xe_gt_get_tile_id(int fd, int gt)
> +{
> +	struct xe_device *xe_dev;
> +
> +	xe_dev = find_in_cache(fd);
> +
> +	igt_assert(xe_dev);
> +	igt_assert(gt < xe_number_gt(fd));
> +
> +	return xe_dev->gt_list->gt_list[gt].tile_id;
> +}
> +
>  igt_constructor
>  {
>  	xe_device_cache_init();
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index 82af2706d..b1b3a989e 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -99,6 +99,7 @@ const char *xe_engine_class_string(uint32_t engine_class);
>  bool xe_has_engine_class(int fd, uint16_t engine_class);
>  bool xe_has_media_gt(int fd);
>  bool xe_is_media_gt(int fd, int gt);
> +int xe_gt_get_tile_id(int fd, int gt);
>  
>  struct xe_device *xe_device_get(int fd);
>  void xe_device_put(int fd);
> -- 
> 2.34.1
> 

Re: [PATCH i-g-t 2/2] lib/xe_mmio: Introduce Xe MMIO lib

[Piotr Piórkowski]

Kamil Konieczny <kamil.konieczny@linux.intel.com> wrote on pon [2024-mar-25 18:36:06 +0100]:
> Hi Piórkowski,,
> On 2024-03-25 at 16:57:09 +0100, Piórkowski, Piotr wrote:
> > From: Piotr Piórkowski <piotr.piorkowski@intel.com>
> > 
> > Currently in IGT we have a library intel_mmio for simple MMIO operations
> > on intel GPU devices, but it is limited only to accessing registers,
> > has a lot of legacy code related to the i915 and offers no support for
> > multi tile.
> > Let's reuse the memory mapping from the previous library and add separate
> > helpers, dedicated to Xe, for registers and GGTT access that support multi
> > tile.
> > 
> > Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
> > ---
> >  lib/meson.build   |   3 +-
> >  lib/xe/xe_mmio.c  | 207 ++++++++++++++++++++++++++++++++++++++++++++++
> >  lib/xe/xe_mmio.h  |  37 +++++++++
> >  lib/xe/xe_query.c |  19 +++++
> >  lib/xe/xe_query.h |   1 +
> >  5 files changed, 266 insertions(+), 1 deletion(-)
> >  create mode 100644 lib/xe/xe_mmio.c
> >  create mode 100644 lib/xe/xe_mmio.h
> > 
> > diff --git a/lib/meson.build b/lib/meson.build
> > index 934bac5c6..2f9666846 100644
> > --- a/lib/meson.build
> > +++ b/lib/meson.build
> > @@ -110,6 +110,7 @@ lib_sources = [
> >  	'igt_dsc.c',
> >  	'xe/xe_gt.c',
> >  	'xe/xe_ioctl.c',
> > +	'xe/xe_mmio.c',
> >  	'xe/xe_query.c',
> >  	'xe/xe_spin.c',
> >  	'xe/xe_util.c',
> > @@ -162,7 +163,7 @@ if libdrm_amdgpu.found()
> >  		lib_sources +=[ 'amdgpu/amd_dispatch.c',]
> >  	else
> >  		warning('libdrm <= 2.4.99 found, amdgpu_cs_query_reset_state2 not applicable')
> > -	endif	
> > +	endif
> >  endif
> >  
> >  if libunwind.found()
> > diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
> > new file mode 100644
> > index 000000000..bd4227f25
> > --- /dev/null
> > +++ b/lib/xe/xe_mmio.c
> > @@ -0,0 +1,207 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright(c) 2024 Intel Corporation. All rights reserved.
> > + */
> > +
> > +#include "igt_device.h"
> > +
> > +#include "xe/xe_mmio.h"
> > +#include "xe/xe_query.h"
> > +
> > +/**
> > + * xe_mmio_vf_access_init:
> > + * @pf_fd: xe device file descriptor
> > + * @vf_id: PCI virtual function number (0 if native or PF itself)
> > + * @mmio: xe mmio structure for IO operations
> > + *
> > + * This initializes the xe mmio structure, and maps the MMIO BAR owned by
> > + * the specified virtual function associated with @pf_fd.
> > + */
> > +void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio)
> > +{
> > +	struct pci_device *pci_dev = __igt_device_get_pci_device(pf_fd, vf_id);
> > +
> > +	igt_assert_f(pci_dev, "No PCI device found for VF%u\n", vf_id);
> > +
> > +	intel_mmio_use_pci_bar(&mmio->intel_mmio, pci_dev);
> > +
> > +	igt_assert(!mmio->intel_mmio.igt_mmio);
> > +
> > +	mmio->fd = pf_fd;
> > +	mmio->intel_mmio.safe = false;
> > +	mmio->intel_mmio.pci_device_id = pci_dev->device_id;
> > +}
> > +
> > +/**
> > + * xe_mmio_access_init:
> > + * @pf_fd: xe device file descriptor
> > + * @mmio: xe mmio structure for IO operations
> > + *
> > + * This initializes the xe mmio structure, and maps MMIO BAR for @pf_fd device.
> > + */
> > +void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio)
> > +{
> > +	xe_mmio_vf_access_init(pf_fd, 0, mmio);
> > +}
> > +
> > +/**
> > + * xe_mmio_access_fini:
> > + * @mmio: xe mmio structure for IO operations
> > + *
> > + * Clean up the mmio access helper initialized with
> > + * xe_mmio_access_init()/xe_mmio_vf_access_init().
> > + */
> > +void xe_mmio_access_fini(struct xe_mmio *mmio)
> > +{
> > +	mmio->intel_mmio.pci_device_id = 0;
> > +	intel_mmio_unmap_pci_bar(&mmio->intel_mmio);
> > +	igt_pci_system_cleanup();
> > +}
> > +
> > +/**
> > + * xe_mmio_read32:
> > + * @mmio: xe mmio structure for IO operations
> > + * @reg: mmio register offset
> > + *
> > + * 32-bit read of the register at @offset.
> > + *
> > + * Returns:
> > + * The value read from the register.
> > + */
> > +uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t reg)
> > +{
> > +	return ioread32(mmio->intel_mmio.igt_mmio, reg);
> > +}
> > +
> > +/**
> > + * xe_mmio_read64:
> > + * @mmio: xe mmio structure for IO operations
> > + * @reg: mmio register offset
> > + *
> > + * 64-bit read of the register at @offset.
> > + *
> > + * Returns:
> > + * The value read from the register.
> > + */
> > +uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t reg)
> > +{
> > +	return ioread64(mmio->intel_mmio.igt_mmio, reg);
> > +}
> > +
> > +/**
> > + * xe_mmio_write32:
> > + * @mmio: xe mmio structure for IO operations
> > + * @reg: mmio register offset
> > + * @val: value to write
> > + *
> > + * 32-bit write to the register at @offset.
> > + */
> > +void xe_mmio_write32(struct xe_mmio *mmio, uint32_t reg, uint32_t val)
> > +{
> > +	return iowrite32(mmio->intel_mmio.igt_mmio, reg, val);
> > +}
> > +
> > +/**
> > + * xe_mmio_write64:
> > + * @mmio: xe mmio structure for IO operations
> > + * @reg: mmio register offset
> > + * @val: value to write
> > + *
> > + * 64-bit write to the register at @offset.
> > + */
> > +void xe_mmio_write64(struct xe_mmio *mmio, uint32_t reg, uint64_t val)
> > +{
> > +	return iowrite64(mmio->intel_mmio.igt_mmio, reg, val);
> > +}
> > +
> > +/**
> > + * xe_mmio_gt_read32:
> > + * @mmio: xe mmio structure for IO operations
> > + * @gt: gt id
> > + * @reg: mmio register offset in tile to which @gt belongs
> > + *
> > + * 32-bit read of the register at @offset in tile to which @gt belongs.
> > + *
> > + * Returns:
> > + * The value read from the register.
> > + */
> > +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t reg)
> > +{
> > +	return xe_mmio_read32(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
> > +}
> > +
> > +/**
> > + * xe_mmio_gt_read64:
> > + * @mmio: xe mmio structure for IO operations
> > + * @gt: gt id
> > + * @reg: mmio register offset in tile to which @gt belongs
> > + *
> > + * 64-bit read of the register at @offset in tile to which @gt belongs.
> > + *
> > + * Returns:
> > + * The value read from the register.
> > + */
> > +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t reg)
> > +{
> > +	return xe_mmio_read64(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
> > +}
> > +
> > +/**
> > + * xe_mmio_gt_write32:
> > + * @mmio: xe mmio structure for IO operations
> > + * @gt: gt id
> > + * @reg: mmio register offset
> > + * @val: value to write
> > + *
> > + * 32-bit write to the register at @offset in tile to which @gt belongs.
> > + */
> > +void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t reg, uint32_t val)
> > +{
> > +	return xe_mmio_write32(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
> > +			       val);
> > +}
> > +
> > +/**
> > + * xe_mmio_gt_write64:
> > + * @mmio: xe mmio structure for IO operations
> > + * @gt: gt id
> > + * @reg: mmio register offset
> > + * @val: value to write
> > + *
> > + * 64-bit write to the register at @offset in tile to which @gt belongs.
> > + */
> > +void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t reg, uint64_t val)
> > +{
> > +	return xe_mmio_write64(mmio, reg + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
> > +			       val);
> > +}
> > +
> > +/**
> > + * xe_mmio_ggtt_read:
> > + * @mmio: xe mmio structure for IO operations
> > + * @gt: gt id
> > + * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
> > + *
> > + * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
> > + *
> > + * Returns:
> > + * The value read from the register.
> > + */
> > +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t offset)
> > +{
> > +	return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
> > +}
> > +
> > +/**
> > + * xe_mmio_ggtt_write:
> > + * @mmio: xe mmio structure for IO operations
> > + * @gt: gt id
> > + * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
> > + * @pte: PTE value to write
> > + *
> > + * Write PTE value at GGTT @offset in tile to which @gt belongs.
> > + */
> > +void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset, xe_ggtt_pte_t pte)
> > +{
> > +	return xe_mmio_gt_write64(mmio, gt, offset + GGTT_OFFSET_IN_TILE, pte);
> > +}
> > diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
> > new file mode 100644
> > index 000000000..ed45040bd
> > --- /dev/null
> > +++ b/lib/xe/xe_mmio.h
> > @@ -0,0 +1,37 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright(c) 2024 Intel Corporation. All rights reserved.
> > + */
> 
> Add here standard ifdef/define and at end of file endif:
> 
> #ifndef IGT_XE_MMIO_H
> #define IGT_XE_MMIO_H

Oh thanks for catching that.
I'll fix it right away!

- Piotr
> 
> Regards,
> Kamil
> 
> > +
> > +#include "lib/intel_io.h"
> > +#include "lib/igt_sizes.h"
> > +
> > +#define TILE_MMIO_SIZE		SZ_16M
> > +#define GGTT_OFFSET_IN_TILE	SZ_8M
> > +
> > +typedef uint64_t xe_ggtt_pte_t;
> > +
> > +struct xe_mmio {
> > +	int fd;
> > +	unsigned int vf_id;
> > +	struct intel_mmio_data intel_mmio;
> > +};
> > +
> > +void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio);
> > +void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio);
> > +void xe_mmio_access_fini(struct xe_mmio *mmio);
> > +
> > +uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t reg);
> > +uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t reg);
> > +
> > +void xe_mmio_write32(struct xe_mmio *mmio, uint32_t reg, uint32_t val);
> > +void xe_mmio_write64(struct xe_mmio *mmio, uint32_t reg, uint64_t val);
> > +
> > +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t reg);
> > +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t reg);
> > +
> > +void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t reg, uint32_t val);
> > +void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t reg, uint64_t val);
> > +
> > +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
> > +void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
> > diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> > index 53a2b4386..c885e3a79 100644
> > --- a/lib/xe/xe_query.c
> > +++ b/lib/xe/xe_query.c
> > @@ -731,6 +731,25 @@ bool xe_is_media_gt(int fd, int gt)
> >  	return false;
> >  }
> >  
> > +/**
> > + * xe_gt_to_tile_id:
> > + * @fd: xe device fd
> > + * @gt: gt id
> > + *
> > + * Returns tile id for given @gt.
> > + */
> > +int xe_gt_get_tile_id(int fd, int gt)
> > +{
> > +	struct xe_device *xe_dev;
> > +
> > +	xe_dev = find_in_cache(fd);
> > +
> > +	igt_assert(xe_dev);
> > +	igt_assert(gt < xe_number_gt(fd));
> > +
> > +	return xe_dev->gt_list->gt_list[gt].tile_id;
> > +}
> > +
> >  igt_constructor
> >  {
> >  	xe_device_cache_init();
> > diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> > index 82af2706d..b1b3a989e 100644
> > --- a/lib/xe/xe_query.h
> > +++ b/lib/xe/xe_query.h
> > @@ -99,6 +99,7 @@ const char *xe_engine_class_string(uint32_t engine_class);
> >  bool xe_has_engine_class(int fd, uint16_t engine_class);
> >  bool xe_has_media_gt(int fd);
> >  bool xe_is_media_gt(int fd, int gt);
> > +int xe_gt_get_tile_id(int fd, int gt);
> >  
> >  struct xe_device *xe_device_get(int fd);
> >  void xe_device_put(int fd);
> > -- 
> > 2.34.1
> > 

-- 

✗ Fi.CI.BAT: failure for lib/xe_mmio: Introduce Xe MMIO lib

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10288 bytes --]

== Series Details ==

Series: lib/xe_mmio: Introduce Xe MMIO lib
URL   : https://patchwork.freedesktop.org/series/131591/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14479 -> IGTPW_10901
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_10901 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_10901, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/index.html

Participating hosts (38 -> 35)
------------------------------

  Additional (1): fi-bsw-nick 
  Missing    (4): bat-arls-4 bat-kbl-2 fi-snb-2520m fi-kbl-8809g 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_10901:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  
Known issues
------------

  Here are the changes found in IGTPW_10901 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-arls-3:         NOTRUN -> [SKIP][2] ([i915#9318])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@debugfs_test@basic-hwmon.html

  * igt@gem_huc_copy@huc-copy:
    - fi-cfl-8109u:       NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic@lmem0:
    - bat-dg2-11:         [PASS][4] -> [FAIL][5] ([i915#10378])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14479/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-bsw-nick:        NOTRUN -> [SKIP][6] +19 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/fi-bsw-nick/igt@gem_lmem_swapping@parallel-random-engines.html
    - bat-arls-3:         NOTRUN -> [SKIP][7] ([i915#10213]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-cfl-8109u:       NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-arls-3:         NOTRUN -> [SKIP][9] ([i915#4083])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@gem_mmap@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-arls-3:         NOTRUN -> [SKIP][10] ([i915#10197] / [i915#10211] / [i915#4079])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_blits@basic:
    - bat-arls-3:         NOTRUN -> [SKIP][11] ([i915#10196] / [i915#4077]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-arls-3:         NOTRUN -> [SKIP][12] ([i915#10206] / [i915#4079])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-arls-3:         NOTRUN -> [SKIP][13] ([i915#10209])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@execlists:
    - bat-dg2-9:          NOTRUN -> [ABORT][14] ([i915#10366])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-dg2-9/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_timelines:
    - bat-dg2-14:         [PASS][15] -> [ABORT][16] ([i915#10366])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14479/bat-dg2-14/igt@i915_selftest@live@gt_timelines.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-dg2-14/igt@i915_selftest@live@gt_timelines.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - bat-arls-3:         NOTRUN -> [SKIP][17] ([i915#10200]) +9 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - bat-arls-3:         NOTRUN -> [SKIP][18] ([i915#10202]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
    - bat-arls-3:         NOTRUN -> [SKIP][19] ([i915#9886])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-arls-3:         NOTRUN -> [SKIP][20] ([i915#10207])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pm_backlight@basic-brightness:
    - fi-cfl-8109u:       NOTRUN -> [SKIP][21] +11 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/fi-cfl-8109u/igt@kms_pm_backlight@basic-brightness.html
    - bat-arls-3:         NOTRUN -> [SKIP][22] ([i915#9812])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - bat-arls-3:         NOTRUN -> [SKIP][23] ([i915#9732]) +3 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-arls-3:         NOTRUN -> [SKIP][24] ([i915#10208] / [i915#8809])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-arls-3:         NOTRUN -> [SKIP][25] ([i915#10196] / [i915#3708] / [i915#4077]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - bat-arls-3:         NOTRUN -> [SKIP][26] ([i915#10212] / [i915#3708])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-read:
    - bat-arls-3:         NOTRUN -> [SKIP][27] ([i915#10214] / [i915#3708])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - bat-arls-3:         NOTRUN -> [SKIP][28] ([i915#10216] / [i915#3708])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-arls-3/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [ABORT][29] ([i915#10366]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14479/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-dg2-9/igt@i915_selftest@live@workarounds.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - {bat-mtlp-9}:       [DMESG-WARN][31] -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14479/bat-mtlp-9/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/bat-mtlp-9/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10196]: https://gitlab.freedesktop.org/drm/intel/issues/10196
  [i915#10197]: https://gitlab.freedesktop.org/drm/intel/issues/10197
  [i915#10200]: https://gitlab.freedesktop.org/drm/intel/issues/10200
  [i915#10202]: https://gitlab.freedesktop.org/drm/intel/issues/10202
  [i915#10206]: https://gitlab.freedesktop.org/drm/intel/issues/10206
  [i915#10207]: https://gitlab.freedesktop.org/drm/intel/issues/10207
  [i915#10208]: https://gitlab.freedesktop.org/drm/intel/issues/10208
  [i915#10209]: https://gitlab.freedesktop.org/drm/intel/issues/10209
  [i915#10211]: https://gitlab.freedesktop.org/drm/intel/issues/10211
  [i915#10212]: https://gitlab.freedesktop.org/drm/intel/issues/10212
  [i915#10213]: https://gitlab.freedesktop.org/drm/intel/issues/10213
  [i915#10214]: https://gitlab.freedesktop.org/drm/intel/issues/10214
  [i915#10216]: https://gitlab.freedesktop.org/drm/intel/issues/10216
  [i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
  [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/intel/issues/9812
  [i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7781 -> IGTPW_10901

  CI-20190529: 20190529
  CI_DRM_14479: d1ecfbbbb194e8f7941bd84f77f7c938b461ce14 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_10901: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/index.html
  IGT_7781: 7781

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/index.html

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✓ CI.xeBAT: success for lib/xe_mmio: Introduce Xe MMIO lib

[Patchwork]

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== Series Details ==

Series: lib/xe_mmio: Introduce Xe MMIO lib
URL   : https://patchwork.freedesktop.org/series/131591/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7781_BAT -> XEIGTPW_10901_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_10901_BAT that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@xe_evict@evict-beng-mixed-threads-small-multi-vm:
    - bat-dg2-oem2:       [TIMEOUT][1] ([Intel XE#1027] / [Intel XE#1088]) -> [INCOMPLETE][2] ([Intel XE#804])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7781/bat-dg2-oem2/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10901/bat-dg2-oem2/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html

  
  [Intel XE#1027]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1027
  [Intel XE#1088]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1088
  [Intel XE#804]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/804


Build changes
-------------

  * IGT: IGT_7781 -> IGTPW_10901
  * Linux: xe-987-fc736bbab7abcae683f52604591fe16cf2a85b3e -> xe-988-d1ecfbbbb194e8f7941bd84f77f7c938b461ce14

  IGTPW_10901: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10901/index.html
  IGT_7781: 7781
  xe-987-fc736bbab7abcae683f52604591fe16cf2a85b3e: fc736bbab7abcae683f52604591fe16cf2a85b3e
  xe-988-d1ecfbbbb194e8f7941bd84f77f7c938b461ce14: d1ecfbbbb194e8f7941bd84f77f7c938b461ce14

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10901/index.html

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