[PATCH i-g-t,v3 0/2] lib/xe_mmio: Introduce Xe MMIO lib

[PATCH i-g-t,v3 0/2] lib/xe_mmio: Introduce Xe MMIO lib

[Piórkowski, Piotr]

From: Piotr Piórkowski <piotr.piorkowski@intel.com>

The series includes a simple set of helpers, dedicated to Xe, allowing
access to registers and GGTT, on various tile, using MMIO BAR access.

v2:
 - add missing header std ifndef/define in lib/xe_mmio.h (Kamil)
v3:
- remove unused vf_id from struct xe_mmio (Lukasz)
- rename reg to offset in funcs params (Lukasz)
- change return type for xe_gt_get_tile_id (Lukasz)

Piotr Piórkowski (2):
  lib/intel_mmio: Map the whole BAR0 for gen12+
  lib/xe_mmio: Introduce Xe MMIO lib

 lib/intel_mmio.c  |   2 +-
 lib/meson.build   |   1 +
 lib/xe/xe_mmio.c  | 207 ++++++++++++++++++++++++++++++++++++++++++++++
 lib/xe/xe_mmio.h  |  41 +++++++++
 lib/xe/xe_query.c |  19 +++++
 lib/xe/xe_query.h |   1 +
 6 files changed, 270 insertions(+), 1 deletion(-)
 create mode 100644 lib/xe/xe_mmio.c
 create mode 100644 lib/xe/xe_mmio.h

-- 
2.34.1

[PATCH i-g-t,v3 1/2] lib/intel_mmio: Map the whole BAR0 for gen12+

[Piórkowski, Piotr]

From: Piotr Piórkowski <piotr.piorkowski@intel.com>

Previously, we limited BAR0 mapping to register space only because of
the potential conflict with wc mapping for the GTT region.
For gen12+ platforms, the size of BAR0 varies due to the different amount
of tile.
And as for gen11+ platforms, we can already map the whole BAR0 as uc,
so let's map the whole BAR0, without artificial limitations.

Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com>
---
 lib/intel_mmio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c
index 4b6820787..31975727e 100644
--- a/lib/intel_mmio.c
+++ b/lib/intel_mmio.c
@@ -154,7 +154,7 @@ intel_mmio_use_pci_bar(struct intel_mmio_data *mmio_data, struct pci_device *pci
 
 	gen = intel_gen(devid);
 	if (gen >= 12)
-		mmio_size = 8 * 1024 * 1024;
+		mmio_size = pci_dev->regions[mmio_bar].size;
 	else if (gen >= 5)
 		mmio_size = 2 * 1024 * 1024;
 	else
-- 
2.34.1

[PATCH i-g-t,v3 2/2] lib/xe_mmio: Introduce Xe MMIO lib

[Piórkowski, Piotr]

From: Piotr Piórkowski <piotr.piorkowski@intel.com>

Currently in IGT we have a library intel_mmio for simple MMIO operations
on intel GPU devices, but it is limited only to accessing registers,
has a lot of legacy code related to the i915 and offers no support for
multi tile.
Let's reuse the memory mapping from the previous library and add separate
helpers, dedicated to Xe, for registers and GGTT access that support multi
tile.

v2:
 - add missing std ifndef/define in header lib/xe_mmio.h
v3:
- remove vf_id from struct xe_mmio
- rename reg to offset in funcs params
- change return type for xe_gt_get_tile_id

Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
---
 lib/meson.build   |   1 +
 lib/xe/xe_mmio.c  | 207 ++++++++++++++++++++++++++++++++++++++++++++++
 lib/xe/xe_mmio.h  |  41 +++++++++
 lib/xe/xe_query.c |  19 +++++
 lib/xe/xe_query.h |   1 +
 5 files changed, 269 insertions(+)
 create mode 100644 lib/xe/xe_mmio.c
 create mode 100644 lib/xe/xe_mmio.h

diff --git a/lib/meson.build b/lib/meson.build
index a5651571b..e2f740c11 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -111,6 +111,7 @@ lib_sources = [
 	'igt_dsc.c',
 	'xe/xe_gt.c',
 	'xe/xe_ioctl.c',
+	'xe/xe_mmio.c',
 	'xe/xe_query.c',
 	'xe/xe_spin.c',
 	'xe/xe_util.c',
diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
new file mode 100644
index 000000000..57526d7cb
--- /dev/null
+++ b/lib/xe/xe_mmio.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2024 Intel Corporation. All rights reserved.
+ */
+
+#include "igt_device.h"
+
+#include "xe/xe_mmio.h"
+#include "xe/xe_query.h"
+
+/**
+ * xe_mmio_vf_access_init:
+ * @pf_fd: xe device file descriptor
+ * @vf_id: PCI virtual function number (0 if native or PF itself)
+ * @mmio: xe mmio structure for IO operations
+ *
+ * This initializes the xe mmio structure, and maps the MMIO BAR owned by
+ * the specified virtual function associated with @pf_fd.
+ */
+void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio)
+{
+	struct pci_device *pci_dev = __igt_device_get_pci_device(pf_fd, vf_id);
+
+	igt_assert_f(pci_dev, "No PCI device found for VF%u\n", vf_id);
+
+	intel_mmio_use_pci_bar(&mmio->intel_mmio, pci_dev);
+
+	igt_assert(!mmio->intel_mmio.igt_mmio);
+
+	mmio->fd = pf_fd;
+	mmio->intel_mmio.safe = false;
+	mmio->intel_mmio.pci_device_id = pci_dev->device_id;
+}
+
+/**
+ * xe_mmio_access_init:
+ * @pf_fd: xe device file descriptor
+ * @mmio: xe mmio structure for IO operations
+ *
+ * This initializes the xe mmio structure, and maps MMIO BAR for @pf_fd device.
+ */
+void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio)
+{
+	xe_mmio_vf_access_init(pf_fd, 0, mmio);
+}
+
+/**
+ * xe_mmio_access_fini:
+ * @mmio: xe mmio structure for IO operations
+ *
+ * Clean up the mmio access helper initialized with
+ * xe_mmio_access_init()/xe_mmio_vf_access_init().
+ */
+void xe_mmio_access_fini(struct xe_mmio *mmio)
+{
+	mmio->intel_mmio.pci_device_id = 0;
+	intel_mmio_unmap_pci_bar(&mmio->intel_mmio);
+	igt_pci_system_cleanup();
+}
+
+/**
+ * xe_mmio_read32:
+ * @mmio: xe mmio structure for IO operations
+ * @offset: mmio register offset
+ *
+ * 32-bit read of the register at @offset.
+ *
+ * Returns:
+ * The value read from the register.
+ */
+uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t offset)
+{
+	return ioread32(mmio->intel_mmio.igt_mmio, offset);
+}
+
+/**
+ * xe_mmio_read64:
+ * @mmio: xe mmio structure for IO operations
+ * @offset: mmio register offset
+ *
+ * 64-bit read of the register at @offset.
+ *
+ * Returns:
+ * The value read from the register.
+ */
+uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t offset)
+{
+	return ioread64(mmio->intel_mmio.igt_mmio, offset);
+}
+
+/**
+ * xe_mmio_write32:
+ * @mmio: xe mmio structure for IO operations
+ * @offset: mmio register offset
+ * @val: value to write
+ *
+ * 32-bit write to the register at @offset.
+ */
+void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, uint32_t val)
+{
+	return iowrite32(mmio->intel_mmio.igt_mmio, offset, val);
+}
+
+/**
+ * xe_mmio_write64:
+ * @mmio: xe mmio structure for IO operations
+ * @offset: mmio register offset
+ * @val: value to write
+ *
+ * 64-bit write to the register at @offset.
+ */
+void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val)
+{
+	return iowrite64(mmio->intel_mmio.igt_mmio, offset, val);
+}
+
+/**
+ * xe_mmio_gt_read32:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @offset: mmio register offset in tile to which @gt belongs
+ *
+ * 32-bit read of the register at @offset in tile to which @gt belongs.
+ *
+ * Returns:
+ * The value read from the register.
+ */
+uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset)
+{
+	return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
+}
+
+/**
+ * xe_mmio_gt_read64:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @offset: mmio register offset in tile to which @gt belongs
+ *
+ * 64-bit read of the register at @offset in tile to which @gt belongs.
+ *
+ * Returns:
+ * The value read from the register.
+ */
+uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset)
+{
+	return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
+}
+
+/**
+ * xe_mmio_gt_write32:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @offset: mmio register offset
+ * @val: value to write
+ *
+ * 32-bit write to the register at @offset in tile to which @gt belongs.
+ */
+void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val)
+{
+	return xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
+			       val);
+}
+
+/**
+ * xe_mmio_gt_write64:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @offset: mmio register offset
+ * @val: value to write
+ *
+ * 64-bit write to the register at @offset in tile to which @gt belongs.
+ */
+void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val)
+{
+	return xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
+			       val);
+}
+
+/**
+ * xe_mmio_ggtt_read:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
+ *
+ * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
+ *
+ * Returns:
+ * The value read from the register.
+ */
+xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t offset)
+{
+	return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
+}
+
+/**
+ * xe_mmio_ggtt_write:
+ * @mmio: xe mmio structure for IO operations
+ * @gt: gt id
+ * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
+ * @pte: PTE value to write
+ *
+ * Write PTE value at GGTT @offset in tile to which @gt belongs.
+ */
+void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset, xe_ggtt_pte_t pte)
+{
+	return xe_mmio_gt_write64(mmio, gt, offset + GGTT_OFFSET_IN_TILE, pte);
+}
diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
new file mode 100644
index 000000000..f144d4b53
--- /dev/null
+++ b/lib/xe/xe_mmio.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2024 Intel Corporation. All rights reserved.
+ */
+
+#include "lib/intel_io.h"
+#include "lib/igt_sizes.h"
+
+#ifndef XE_MMIO_H
+#define XE_MMIO_H
+
+#define TILE_MMIO_SIZE		SZ_16M
+#define GGTT_OFFSET_IN_TILE	SZ_8M
+
+typedef uint64_t xe_ggtt_pte_t;
+
+struct xe_mmio {
+	int fd;
+	struct intel_mmio_data intel_mmio;
+};
+
+void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio);
+void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio);
+void xe_mmio_access_fini(struct xe_mmio *mmio);
+
+uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t offset);
+uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t offset);
+
+void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, uint32_t val);
+void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val);
+
+uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset);
+uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset);
+
+void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val);
+void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val);
+
+xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
+void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
+
+#endif	/* XE_MMIO_H */
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 53a2b4386..6df8f4264 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -731,6 +731,25 @@ bool xe_is_media_gt(int fd, int gt)
 	return false;
 }
 
+/**
+ * xe_gt_to_tile_id:
+ * @fd: xe device fd
+ * @gt: gt id
+ *
+ * Returns tile id for given @gt.
+ */
+uint16_t xe_gt_get_tile_id(int fd, int gt)
+{
+	struct xe_device *xe_dev;
+
+	xe_dev = find_in_cache(fd);
+
+	igt_assert(xe_dev);
+	igt_assert(gt < xe_number_gt(fd));
+
+	return xe_dev->gt_list->gt_list[gt].tile_id;
+}
+
 igt_constructor
 {
 	xe_device_cache_init();
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 82af2706d..f91d16bdf 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -99,6 +99,7 @@ const char *xe_engine_class_string(uint32_t engine_class);
 bool xe_has_engine_class(int fd, uint16_t engine_class);
 bool xe_has_media_gt(int fd);
 bool xe_is_media_gt(int fd, int gt);
+uint16_t xe_gt_get_tile_id(int fd, int gt);
 
 struct xe_device *xe_device_get(int fd);
 void xe_device_put(int fd);
-- 
2.34.1

Re: [PATCH i-g-t,v3 2/2] lib/xe_mmio: Introduce Xe MMIO lib

[Laguna, Lukasz]

[-- Attachment #1: Type: text/plain, Size: 10575 bytes --]

On 4/3/2024 14:09, Piórkowski, Piotr wrote:
> From: Piotr Piórkowski<piotr.piorkowski@intel.com>
>
> Currently in IGT we have a library intel_mmio for simple MMIO operations
> on intel GPU devices, but it is limited only to accessing registers,
> has a lot of legacy code related to the i915 and offers no support for
> multi tile.
> Let's reuse the memory mapping from the previous library and add separate
> helpers, dedicated to Xe, for registers and GGTT access that support multi
> tile.
>
> v2:
>   - add missing std ifndef/define in header lib/xe_mmio.h
> v3:
> - remove vf_id from struct xe_mmio
> - rename reg to offset in funcs params
> - change return type for xe_gt_get_tile_id
>
> Signed-off-by: Piotr Piórkowski<piotr.piorkowski@intel.com>
> Cc: Kamil Konieczny<kamil.konieczny@linux.intel.com>
> Cc: Lukasz Laguna<lukasz.laguna@intel.com>
> ---
>   lib/meson.build   |   1 +
>   lib/xe/xe_mmio.c  | 207 ++++++++++++++++++++++++++++++++++++++++++++++
>   lib/xe/xe_mmio.h  |  41 +++++++++
>   lib/xe/xe_query.c |  19 +++++
>   lib/xe/xe_query.h |   1 +
>   5 files changed, 269 insertions(+)
>   create mode 100644 lib/xe/xe_mmio.c
>   create mode 100644 lib/xe/xe_mmio.h
>
> diff --git a/lib/meson.build b/lib/meson.build
> index a5651571b..e2f740c11 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -111,6 +111,7 @@ lib_sources = [
>   	'igt_dsc.c',
>   	'xe/xe_gt.c',
>   	'xe/xe_ioctl.c',
> +	'xe/xe_mmio.c',
>   	'xe/xe_query.c',
>   	'xe/xe_spin.c',
>   	'xe/xe_util.c',
> diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
> new file mode 100644
> index 000000000..57526d7cb
> --- /dev/null
> +++ b/lib/xe/xe_mmio.c
> @@ -0,0 +1,207 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2024 Intel Corporation. All rights reserved.
> + */
> +
> +#include "igt_device.h"
> +
> +#include "xe/xe_mmio.h"
> +#include "xe/xe_query.h"
> +
> +/**
> + * xe_mmio_vf_access_init:
> + * @pf_fd: xe device file descriptor
> + * @vf_id: PCI virtual function number (0 if native or PF itself)
> + * @mmio: xe mmio structure for IO operations
> + *
> + * This initializes the xe mmio structure, and maps the MMIO BAR owned by
> + * the specified virtual function associated with @pf_fd.
> + */
> +void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio)
> +{
> +	struct pci_device *pci_dev = __igt_device_get_pci_device(pf_fd, vf_id);
> +
> +	igt_assert_f(pci_dev, "No PCI device found for VF%u\n", vf_id);
> +
> +	intel_mmio_use_pci_bar(&mmio->intel_mmio, pci_dev);
> +
> +	igt_assert(!mmio->intel_mmio.igt_mmio);
> +
> +	mmio->fd = pf_fd;
> +	mmio->intel_mmio.safe = false;
> +	mmio->intel_mmio.pci_device_id = pci_dev->device_id;
> +}
> +
> +/**
> + * xe_mmio_access_init:
> + * @pf_fd: xe device file descriptor
> + * @mmio: xe mmio structure for IO operations
> + *
> + * This initializes the xe mmio structure, and maps MMIO BAR for @pf_fd device.
> + */
> +void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio)
> +{
> +	xe_mmio_vf_access_init(pf_fd, 0, mmio);
> +}
> +
> +/**
> + * xe_mmio_access_fini:
> + * @mmio: xe mmio structure for IO operations
> + *
> + * Clean up the mmio access helper initialized with
> + * xe_mmio_access_init()/xe_mmio_vf_access_init().
> + */
> +void xe_mmio_access_fini(struct xe_mmio *mmio)
> +{
> +	mmio->intel_mmio.pci_device_id = 0;
> +	intel_mmio_unmap_pci_bar(&mmio->intel_mmio);
> +	igt_pci_system_cleanup();
> +}
> +
> +/**
> + * xe_mmio_read32:
> + * @mmio: xe mmio structure for IO operations
> + * @offset: mmio register offset
> + *
> + * 32-bit read of the register at @offset.
> + *
> + * Returns:
> + * The value read from the register.
> + */
> +uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t offset)
> +{
> +	return ioread32(mmio->intel_mmio.igt_mmio, offset);
> +}
> +
> +/**
> + * xe_mmio_read64:
> + * @mmio: xe mmio structure for IO operations
> + * @offset: mmio register offset
> + *
> + * 64-bit read of the register at @offset.
> + *
> + * Returns:
> + * The value read from the register.
> + */
> +uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t offset)
> +{
> +	return ioread64(mmio->intel_mmio.igt_mmio, offset);
> +}
> +
> +/**
> + * xe_mmio_write32:
> + * @mmio: xe mmio structure for IO operations
> + * @offset: mmio register offset
> + * @val: value to write
> + *
> + * 32-bit write to the register at @offset.
> + */
> +void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, uint32_t val)
> +{
> +	return iowrite32(mmio->intel_mmio.igt_mmio, offset, val);
> +}
> +
> +/**
> + * xe_mmio_write64:
> + * @mmio: xe mmio structure for IO operations
> + * @offset: mmio register offset
> + * @val: value to write
> + *
> + * 64-bit write to the register at @offset.
> + */
> +void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val)
> +{
> +	return iowrite64(mmio->intel_mmio.igt_mmio, offset, val);
> +}
> +
> +/**
> + * xe_mmio_gt_read32:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @offset: mmio register offset in tile to which @gt belongs
> + *
> + * 32-bit read of the register at @offset in tile to which @gt belongs.
> + *
> + * Returns:
> + * The value read from the register.
> + */
> +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset)
> +{
> +	return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
> +}
> +
> +/**
> + * xe_mmio_gt_read64:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @offset: mmio register offset in tile to which @gt belongs
> + *
> + * 64-bit read of the register at @offset in tile to which @gt belongs.
> + *
> + * Returns:
> + * The value read from the register.
> + */
> +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset)
> +{
> +	return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
> +}
> +
> +/**
> + * xe_mmio_gt_write32:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @offset: mmio register offset
> + * @val: value to write
> + *
> + * 32-bit write to the register at @offset in tile to which @gt belongs.
> + */
> +void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val)
> +{
> +	return xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
> +			       val);
> +}
> +
> +/**
> + * xe_mmio_gt_write64:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @offset: mmio register offset
> + * @val: value to write
> + *
> + * 64-bit write to the register at @offset in tile to which @gt belongs.
> + */
> +void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val)
> +{
> +	return xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
> +			       val);
> +}
> +
> +/**
> + * xe_mmio_ggtt_read:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
> + *
> + * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
> + *
> + * Returns:
> + * The value read from the register.
> + */
> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t offset)
> +{
> +	return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
> +}
> +
> +/**
> + * xe_mmio_ggtt_write:
> + * @mmio: xe mmio structure for IO operations
> + * @gt: gt id
> + * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
> + * @pte: PTE value to write
> + *
> + * Write PTE value at GGTT @offset in tile to which @gt belongs.
> + */
> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset, xe_ggtt_pte_t pte)
> +{
> +	return xe_mmio_gt_write64(mmio, gt, offset + GGTT_OFFSET_IN_TILE, pte);
> +}
> diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
> new file mode 100644
> index 000000000..f144d4b53
> --- /dev/null
> +++ b/lib/xe/xe_mmio.h
> @@ -0,0 +1,41 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2024 Intel Corporation. All rights reserved.
> + */
> +
> +#include "lib/intel_io.h"
> +#include "lib/igt_sizes.h"
> +
> +#ifndef XE_MMIO_H
> +#define XE_MMIO_H
> +
> +#define TILE_MMIO_SIZE		SZ_16M
> +#define GGTT_OFFSET_IN_TILE	SZ_8M
> +
> +typedef uint64_t xe_ggtt_pte_t;
> +
> +struct xe_mmio {
> +	int fd;
> +	struct intel_mmio_data intel_mmio;
> +};
> +
> +void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio);
> +void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio);
> +void xe_mmio_access_fini(struct xe_mmio *mmio);
> +
> +uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t offset);
> +uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t offset);
> +
> +void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, uint32_t val);
> +void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val);
> +
> +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset);
> +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset);
> +
> +void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val);
> +void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val);
> +
> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
> +
> +#endif	/* XE_MMIO_H */
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index 53a2b4386..6df8f4264 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -731,6 +731,25 @@ bool xe_is_media_gt(int fd, int gt)
>   	return false;
>   }
>   
> +/**
> + * xe_gt_to_tile_id:
> + * @fd: xe device fd
> + * @gt: gt id
> + *
> + * Returns tile id for given @gt.
> + */
> +uint16_t xe_gt_get_tile_id(int fd, int gt)
> +{
> +	struct xe_device *xe_dev;
> +
> +	xe_dev = find_in_cache(fd);
> +
> +	igt_assert(xe_dev);
> +	igt_assert(gt < xe_number_gt(fd));
> +
> +	return xe_dev->gt_list->gt_list[gt].tile_id;
> +}
> +
>   igt_constructor
>   {
>   	xe_device_cache_init();
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index 82af2706d..f91d16bdf 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -99,6 +99,7 @@ const char *xe_engine_class_string(uint32_t engine_class);
>   bool xe_has_engine_class(int fd, uint16_t engine_class);
>   bool xe_has_media_gt(int fd);
>   bool xe_is_media_gt(int fd, int gt);
> +uint16_t xe_gt_get_tile_id(int fd, int gt);
>   
>   struct xe_device *xe_device_get(int fd);
>   void xe_device_put(int fd);

Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com>

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✗ Fi.CI.BAT: failure for lib/xe_mmio: Introduce Xe MMIO lib (rev3)

[Patchwork]

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== Series Details ==

Series: lib/xe_mmio: Introduce Xe MMIO lib (rev3)
URL   : https://patchwork.freedesktop.org/series/131591/
State : failure

== Summary ==

CI Bug Log - changes from IGT_7798 -> IGTPW_10972
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_10972 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_10972, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/index.html

Participating hosts (36 -> 37)
------------------------------

  Additional (4): bat-dg1-7 fi-glk-j4005 bat-jsl-1 bat-arls-3 
  Missing    (3): bat-arls-1 fi-snb-2520m fi-bsw-nick 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_10972:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@reload:
    - bat-dg2-11:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7798/bat-dg2-11/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg2-11/igt@i915_module_load@reload.html

  
Known issues
------------

  Here are the changes found in IGTPW_10972 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-jsl-1:          NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
    - bat-arls-3:         NOTRUN -> [SKIP][4] ([i915#9318])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@debugfs_test@basic-hwmon.html

  * igt@gem_huc_copy@huc-copy:
    - bat-jsl-1:          NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
    - fi-glk-j4005:       NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/fi-glk-j4005/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-glk-j4005:       NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/fi-glk-j4005/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-arls-3:         NOTRUN -> [SKIP][8] ([i915#10213]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-jsl-1:          NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][10] ([i915#4083])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@gem_mmap@basic.html
    - bat-arls-3:         NOTRUN -> [SKIP][11] ([i915#4083])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@gem_mmap@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-arls-3:         NOTRUN -> [SKIP][12] ([i915#10197] / [i915#10211] / [i915#4079])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_blits@basic:
    - bat-arls-3:         NOTRUN -> [SKIP][13] ([i915#10196] / [i915#4077]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][14] ([i915#4077]) +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][15] ([i915#4079]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@gem_tiled_pread_basic.html
    - bat-arls-3:         NOTRUN -> [SKIP][16] ([i915#10206] / [i915#4079])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg1-7:          NOTRUN -> [SKIP][17] ([i915#6621])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@i915_pm_rps@basic-api.html
    - bat-arls-3:         NOTRUN -> [SKIP][18] ([i915#10209])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@i915_pm_rps@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - bat-arls-3:         NOTRUN -> [SKIP][19] ([i915#10200]) +9 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][20] ([i915#4212]) +7 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][21] ([i915#4215])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-glk-j4005:       NOTRUN -> [SKIP][22] +10 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/fi-glk-j4005/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - bat-arls-3:         NOTRUN -> [SKIP][23] ([i915#10202]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-jsl-1:          NOTRUN -> [SKIP][24] ([i915#4103]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-dg1-7:          NOTRUN -> [SKIP][25] ([i915#4103] / [i915#4213]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-arls-3:         NOTRUN -> [SKIP][26] ([i915#9886])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_dsc@dsc-basic.html
    - bat-jsl-1:          NOTRUN -> [SKIP][27] ([i915#3555] / [i915#9886])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@kms_dsc@dsc-basic.html
    - bat-dg1-7:          NOTRUN -> [SKIP][28] ([i915#3555] / [i915#3840])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-arls-3:         NOTRUN -> [SKIP][29] ([i915#10207])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_force_connector_basic@force-load-detect.html
    - bat-jsl-1:          NOTRUN -> [SKIP][30]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html
    - bat-dg1-7:          NOTRUN -> [SKIP][31]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_hdmi_inject@inject-audio:
    - bat-dg1-7:          NOTRUN -> [SKIP][32] ([i915#433])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-dg1-7:          NOTRUN -> [SKIP][33] ([i915#5354])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_pm_backlight@basic-brightness.html
    - bat-arls-3:         NOTRUN -> [SKIP][34] ([i915#9812])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - bat-arls-3:         NOTRUN -> [SKIP][35] ([i915#9732]) +3 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@kms_psr@psr-primary-page-flip:
    - bat-dg1-7:          NOTRUN -> [SKIP][36] ([i915#1072] / [i915#9732]) +3 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-jsl-1:          NOTRUN -> [SKIP][37] ([i915#3555])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-arls-3:         NOTRUN -> [SKIP][38] ([i915#10208] / [i915#8809])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-dg1-7:          NOTRUN -> [SKIP][39] ([i915#3555])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg1-7:          NOTRUN -> [SKIP][40] ([i915#3708]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-dg1-7:          NOTRUN -> [SKIP][41] ([i915#3708] / [i915#4077]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@prime_vgem@basic-fence-mmap.html
    - bat-arls-3:         NOTRUN -> [SKIP][42] ([i915#10196] / [i915#3708] / [i915#4077]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - bat-arls-3:         NOTRUN -> [SKIP][43] ([i915#10212] / [i915#3708])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-read:
    - bat-arls-3:         NOTRUN -> [SKIP][44] ([i915#10214] / [i915#3708])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - bat-arls-3:         NOTRUN -> [SKIP][45] ([i915#10216] / [i915#3708])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@prime_vgem@basic-write.html

  
  [i915#10196]: https://gitlab.freedesktop.org/drm/intel/issues/10196
  [i915#10197]: https://gitlab.freedesktop.org/drm/intel/issues/10197
  [i915#10200]: https://gitlab.freedesktop.org/drm/intel/issues/10200
  [i915#10202]: https://gitlab.freedesktop.org/drm/intel/issues/10202
  [i915#10206]: https://gitlab.freedesktop.org/drm/intel/issues/10206
  [i915#10207]: https://gitlab.freedesktop.org/drm/intel/issues/10207
  [i915#10208]: https://gitlab.freedesktop.org/drm/intel/issues/10208
  [i915#10209]: https://gitlab.freedesktop.org/drm/intel/issues/10209
  [i915#10211]: https://gitlab.freedesktop.org/drm/intel/issues/10211
  [i915#10212]: https://gitlab.freedesktop.org/drm/intel/issues/10212
  [i915#10213]: https://gitlab.freedesktop.org/drm/intel/issues/10213
  [i915#10214]: https://gitlab.freedesktop.org/drm/intel/issues/10214
  [i915#10216]: https://gitlab.freedesktop.org/drm/intel/issues/10216
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/intel/issues/9812
  [i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7798 -> IGTPW_10972

  CI-20190529: 20190529
  CI_DRM_14522: 406e10d886a22211d2866bfa9322aec1727171f8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_10972: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/index.html
  IGT_7798: 5e3263748a636ebc91ecfafbd339870c77e3eed6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/index.html

[-- Attachment #2: Type: text/html, Size: 16258 bytes --]

Re: ✗ Fi.CI.BAT: failure for lib/xe_mmio: Introduce Xe MMIO lib (rev3)

[Piotr Piórkowski]

Patchwork <patchwork@emeril.freedesktop.org> wrote on czw [2024-kwi-04 07:40:55 +0000]:
> == Series Details ==
> 
> Series: lib/xe_mmio: Introduce Xe MMIO lib (rev3)
> URL   : https://patchwork.freedesktop.org/series/131591/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from IGT_7798 -> IGTPW_10972
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with IGTPW_10972 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in IGTPW_10972, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/index.html
> 
> Participating hosts (36 -> 37)
> ------------------------------
> 
>   Additional (4): bat-dg1-7 fi-glk-j4005 bat-jsl-1 bat-arls-3 
>   Missing    (3): bat-arls-1 fi-snb-2520m fi-bsw-nick 
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in IGTPW_10972:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@i915_module_load@reload:
>     - bat-dg2-11:         [PASS][1] -> [ABORT][2]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7798/bat-dg2-11/igt@i915_module_load@reload.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg2-11/igt@i915_module_load@reload.html

Not related:
<4> [212.978405] general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b6dbf: 0000 [#1] PREEMPT SMP NOPTI
<4> [212.978415] CPU: 7 PID: 676 Comm: prometheus-node Not tainted 6.9.0-rc2-CI_DRM_14522-g406e10d886a2+ #1
<4> [212.978419] Hardware name: Intel Corporation Alder Lake Client Platform/AlderLake-P DDR5 RVP, BIOS RPLPFWI1.R00.4035.A00.2301200723 01/20/2023
<4> [212.978422] RIP: 0010:hwm_energy+0x2b/0x100 [i915]
<4> [212.978575] Code: 48 89 e5 41 57 41 56 41 55 41 54 53 48 89 fb 48 83 e4 f0 48 83 ec 10 4c 8b 77 08 4c 8b 2f 8b 7f 34 48 89 74 24 08 85 ff 78 2b <45> 8b bd 54 02 00 00 49 8b 7e 18 e8 d5 e4 ea ff 49 89 c4 48 85 c0
<4> [212.978580] RSP: 0018:ffffc90001927d00 EFLAGS: 00010202
<4> [212.978582] RAX: 0000000000000000 RBX: ffff88811aae6428 RCX: 0000000000000000
<4> [212.978585] RDX: 0000000000000001 RSI: ffffc90001927da0 RDI: 000000006b6b6b6b
<4> [212.978587] RBP: ffffc90001927d40 R08: ffffc90001927da0 R09: 0000000000000001
<4> [212.978589] R10: 0000000000000001 R11: ffff888110af0040 R12: ffff888132d13810
<4> [212.978591] R13: 6b6b6b6b6b6b6b6b R14: 6b6b6b6b6b6b6b6b R15: ffff88811aae6428
<4> [212.978593] FS:  00007fdec2a00700(0000) GS:ffff88849f380000(0000) knlGS:0000000000000000
<4> [212.978595] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4> [212.978598] CR2: 00007fdecad179d0 CR3: 0000000115c16000 CR4: 0000000000f50ef0
<4> [212.978600] PKRU: 55555554
<4> [212.978601] Call Trace:
<4> [212.978604]  <TASK>
<4> [212.978605]  ? __die_body+0x1a/0x60
<4> [212.978610]  ? die_addr+0x38/0x60
<4> [212.978612]  ? exc_general_protection+0x1a1/0x400
<4> [212.978617]  ? asm_exc_general_protection+0x26/0x30
<4> [212.978620]  ? hwm_energy+0x2b/0x100 [i915]
<4> [212.978724]  hwm_read+0x9a/0x310 [i915]
<4> [212.978823]  hwmon_attr_show+0x36/0x140
<4> [212.978828]  dev_attr_show+0x15/0x60
<4> [212.978831]  sysfs_kf_seq_show+0xb5/0x100
<4> [212.978836]  seq_read_iter+0x111/0x450
<4> [212.978840]  ? rcu_is_watching+0x11/0x50
<4> [212.978844]  vfs_read+0x203/0x340
<4> [212.978848]  ksys_read+0x64/0xe0
<4> [212.978851]  do_syscall_64+0x6e/0x140
<4> [212.978853]  entry_SYSCALL_64_after_hwframe+0x71/0x79
<4> [212.978856] RIP: 0033:0x4b10f0
<4> [212.978858] Code: 8b 7c 24 10 48 8b 74 24 18 48 8b 54 24 20 49 c7 c2 00 00 00 00 49 c7 c0 00 00 00 00 49 c7 c1 00 00 00 00 48 8b 44 24 08 0f 05 <48> 3d 01 f0 ff ff 76 20 48 c7 44 24 28 ff ff ff ff 48 c7 44 24 30
<4> [212.978864] RSP: 002b:000000c000111790 EFLAGS: 00000206 ORIG_RAX: 0000000000000000
<4> [212.978867] RAX: ffffffffffffffda RBX: 000000c00003e000 RCX: 00000000004b10f0
<4> [212.978871] RDX: 0000000000000080 RSI: 000000c0000c8d80 RDI: 0000000000000006
<4> [212.978874] RBP: 000000c0001117e0 R08: 0000000000000000 R09: 0000000000000000
<4> [212.978877] R10: 0000000000000000 R11: 0000000000000206 R12: ffffffffffffffff
<4> [212.978880] R13: 000000000000001c R14: 000000000000001b R15: 0000000000000040
<4> [212.978883]  </TASK>
<4> [212.978885] Modules linked in: vgem drm_shmem_helper snd_hda_codec_hdmi snd_intel_dspcfg snd_hda_codec snd_hwdep snd_hda_core snd_pcm mei_gsc i915 prime_numbers i2c_algo_bit ttm drm_buddy r8153_ecm cdc_ether usbnet x86_pkg_temp_thermal coretemp kvm_intel kvm e1000e r8152 crct10dif_pclmul video crc32_pclmul wmi_bmof mii ghash_clmulni_intel ptp mei_me i2c_i801 pps_core i2c_smbus mei intel_lpss_pci wmi [last unloaded: mei_hdcp]
<4> [212.978924] ---[ end trace 0000000000000000 ]---
<4> [213.335121] RIP: 0010:hwm_energy+0x2b/0x100 [i915]
<4> [213.335301] Code: 48 89 e5 41 57 41 56 41 55 41 54 53 48 89 fb 48 83 e4 f0 48 83 ec 10 4c 8b 77 08 4c 8b 2f 8b 7f 34 48 89 74 24 08 85 ff 78 2b <45> 8b bd 54 02 00 00 49 8b 7e 18 e8 d5 e4 ea ff 49 89 c4 48 85 c0
<4> [213.335306] RSP: 0018:ffffc90001927d00 EFLAGS: 00010202
<4> [213.335310] RAX: 0000000000000000 RBX: ffff88811aae6428 RCX: 0000000000000000
<4> [213.335312] RDX: 0000000000000001 RSI: ffffc90001927da0 RDI: 000000006b6b6b6b
<4> [213.335314] RBP: ffffc90001927d40 R08: ffffc90001927da0 R09: 0000000000000001
<4> [213.335317] R10: 0000000000000001 R11: ffff888110af0040 R12: ffff888132d13810
<4> [213.335319] R13: 6b6b6b6b6b6b6b6b R14: 6b6b6b6b6b6b6b6b R15: ffff88811aae6428
<4> [213.335321] FS:  00007fdec2a00700(0000) GS:ffff88849f280000(0000) knlGS:0000000000000000
<4> [213.335324] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4> [213.335326] CR2: 000056031eb95d58 CR3: 0000000115c16000 CR4: 0000000000f50ef0
<4> [213.335328] PKRU: 55555554

- Piotr
> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in IGTPW_10972 that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@debugfs_test@basic-hwmon:
>     - bat-jsl-1:          NOTRUN -> [SKIP][3] ([i915#9318])
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
>     - bat-arls-3:         NOTRUN -> [SKIP][4] ([i915#9318])
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@debugfs_test@basic-hwmon.html
> 
>   * igt@gem_huc_copy@huc-copy:
>     - bat-jsl-1:          NOTRUN -> [SKIP][5] ([i915#2190])
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
>     - fi-glk-j4005:       NOTRUN -> [SKIP][6] ([i915#2190])
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/fi-glk-j4005/igt@gem_huc_copy@huc-copy.html
> 
>   * igt@gem_lmem_swapping@basic:
>     - fi-glk-j4005:       NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/fi-glk-j4005/igt@gem_lmem_swapping@basic.html
> 
>   * igt@gem_lmem_swapping@parallel-random-engines:
>     - bat-arls-3:         NOTRUN -> [SKIP][8] ([i915#10213]) +3 other tests skip
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@gem_lmem_swapping@parallel-random-engines.html
> 
>   * igt@gem_lmem_swapping@verify-random:
>     - bat-jsl-1:          NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html
> 
>   * igt@gem_mmap@basic:
>     - bat-dg1-7:          NOTRUN -> [SKIP][10] ([i915#4083])
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@gem_mmap@basic.html
>     - bat-arls-3:         NOTRUN -> [SKIP][11] ([i915#4083])
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@gem_mmap@basic.html
> 
>   * igt@gem_render_tiled_blits@basic:
>     - bat-arls-3:         NOTRUN -> [SKIP][12] ([i915#10197] / [i915#10211] / [i915#4079])
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@gem_render_tiled_blits@basic.html
> 
>   * igt@gem_tiled_blits@basic:
>     - bat-arls-3:         NOTRUN -> [SKIP][13] ([i915#10196] / [i915#4077]) +2 other tests skip
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@gem_tiled_blits@basic.html
> 
>   * igt@gem_tiled_fence_blits@basic:
>     - bat-dg1-7:          NOTRUN -> [SKIP][14] ([i915#4077]) +2 other tests skip
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@gem_tiled_fence_blits@basic.html
> 
>   * igt@gem_tiled_pread_basic:
>     - bat-dg1-7:          NOTRUN -> [SKIP][15] ([i915#4079]) +1 other test skip
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@gem_tiled_pread_basic.html
>     - bat-arls-3:         NOTRUN -> [SKIP][16] ([i915#10206] / [i915#4079])
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@gem_tiled_pread_basic.html
> 
>   * igt@i915_pm_rps@basic-api:
>     - bat-dg1-7:          NOTRUN -> [SKIP][17] ([i915#6621])
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@i915_pm_rps@basic-api.html
>     - bat-arls-3:         NOTRUN -> [SKIP][18] ([i915#10209])
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@i915_pm_rps@basic-api.html
> 
>   * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
>     - bat-arls-3:         NOTRUN -> [SKIP][19] ([i915#10200]) +9 other tests skip
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
> 
>   * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
>     - bat-dg1-7:          NOTRUN -> [SKIP][20] ([i915#4212]) +7 other tests skip
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
> 
>   * igt@kms_addfb_basic@basic-y-tiled-legacy:
>     - bat-dg1-7:          NOTRUN -> [SKIP][21] ([i915#4215])
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_addfb_basic@basic-y-tiled-legacy.html
> 
>   * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
>     - fi-glk-j4005:       NOTRUN -> [SKIP][22] +10 other tests skip
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/fi-glk-j4005/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>     - bat-arls-3:         NOTRUN -> [SKIP][23] ([i915#10202]) +1 other test skip
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
> 
>   * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
>     - bat-jsl-1:          NOTRUN -> [SKIP][24] ([i915#4103]) +1 other test skip
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
>     - bat-dg1-7:          NOTRUN -> [SKIP][25] ([i915#4103] / [i915#4213]) +1 other test skip
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
> 
>   * igt@kms_dsc@dsc-basic:
>     - bat-arls-3:         NOTRUN -> [SKIP][26] ([i915#9886])
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_dsc@dsc-basic.html
>     - bat-jsl-1:          NOTRUN -> [SKIP][27] ([i915#3555] / [i915#9886])
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@kms_dsc@dsc-basic.html
>     - bat-dg1-7:          NOTRUN -> [SKIP][28] ([i915#3555] / [i915#3840])
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_dsc@dsc-basic.html
> 
>   * igt@kms_force_connector_basic@force-load-detect:
>     - bat-arls-3:         NOTRUN -> [SKIP][29] ([i915#10207])
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_force_connector_basic@force-load-detect.html
>     - bat-jsl-1:          NOTRUN -> [SKIP][30]
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html
>     - bat-dg1-7:          NOTRUN -> [SKIP][31]
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_force_connector_basic@force-load-detect.html
> 
>   * igt@kms_hdmi_inject@inject-audio:
>     - bat-dg1-7:          NOTRUN -> [SKIP][32] ([i915#433])
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_hdmi_inject@inject-audio.html
> 
>   * igt@kms_pm_backlight@basic-brightness:
>     - bat-dg1-7:          NOTRUN -> [SKIP][33] ([i915#5354])
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_pm_backlight@basic-brightness.html
>     - bat-arls-3:         NOTRUN -> [SKIP][34] ([i915#9812])
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_pm_backlight@basic-brightness.html
> 
>   * igt@kms_psr@psr-primary-mmap-gtt:
>     - bat-arls-3:         NOTRUN -> [SKIP][35] ([i915#9732]) +3 other tests skip
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_psr@psr-primary-mmap-gtt.html
> 
>   * igt@kms_psr@psr-primary-page-flip:
>     - bat-dg1-7:          NOTRUN -> [SKIP][36] ([i915#1072] / [i915#9732]) +3 other tests skip
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_psr@psr-primary-page-flip.html
> 
>   * igt@kms_setmode@basic-clone-single-crtc:
>     - bat-jsl-1:          NOTRUN -> [SKIP][37] ([i915#3555])
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-jsl-1/igt@kms_setmode@basic-clone-single-crtc.html
>     - bat-arls-3:         NOTRUN -> [SKIP][38] ([i915#10208] / [i915#8809])
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@kms_setmode@basic-clone-single-crtc.html
>     - bat-dg1-7:          NOTRUN -> [SKIP][39] ([i915#3555])
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@kms_setmode@basic-clone-single-crtc.html
> 
>   * igt@prime_vgem@basic-fence-flip:
>     - bat-dg1-7:          NOTRUN -> [SKIP][40] ([i915#3708]) +3 other tests skip
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@prime_vgem@basic-fence-flip.html
> 
>   * igt@prime_vgem@basic-fence-mmap:
>     - bat-dg1-7:          NOTRUN -> [SKIP][41] ([i915#3708] / [i915#4077]) +1 other test skip
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-dg1-7/igt@prime_vgem@basic-fence-mmap.html
>     - bat-arls-3:         NOTRUN -> [SKIP][42] ([i915#10196] / [i915#3708] / [i915#4077]) +1 other test skip
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@prime_vgem@basic-fence-mmap.html
> 
>   * igt@prime_vgem@basic-fence-read:
>     - bat-arls-3:         NOTRUN -> [SKIP][43] ([i915#10212] / [i915#3708])
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@prime_vgem@basic-fence-read.html
> 
>   * igt@prime_vgem@basic-read:
>     - bat-arls-3:         NOTRUN -> [SKIP][44] ([i915#10214] / [i915#3708])
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@prime_vgem@basic-read.html
> 
>   * igt@prime_vgem@basic-write:
>     - bat-arls-3:         NOTRUN -> [SKIP][45] ([i915#10216] / [i915#3708])
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/bat-arls-3/igt@prime_vgem@basic-write.html
> 
>   
>   [i915#10196]: https://gitlab.freedesktop.org/drm/intel/issues/10196
>   [i915#10197]: https://gitlab.freedesktop.org/drm/intel/issues/10197
>   [i915#10200]: https://gitlab.freedesktop.org/drm/intel/issues/10200
>   [i915#10202]: https://gitlab.freedesktop.org/drm/intel/issues/10202
>   [i915#10206]: https://gitlab.freedesktop.org/drm/intel/issues/10206
>   [i915#10207]: https://gitlab.freedesktop.org/drm/intel/issues/10207
>   [i915#10208]: https://gitlab.freedesktop.org/drm/intel/issues/10208
>   [i915#10209]: https://gitlab.freedesktop.org/drm/intel/issues/10209
>   [i915#10211]: https://gitlab.freedesktop.org/drm/intel/issues/10211
>   [i915#10212]: https://gitlab.freedesktop.org/drm/intel/issues/10212
>   [i915#10213]: https://gitlab.freedesktop.org/drm/intel/issues/10213
>   [i915#10214]: https://gitlab.freedesktop.org/drm/intel/issues/10214
>   [i915#10216]: https://gitlab.freedesktop.org/drm/intel/issues/10216
>   [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
>   [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
>   [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
>   [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
>   [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
>   [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
>   [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
>   [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
>   [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
>   [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
>   [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
>   [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
>   [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
>   [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
>   [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
>   [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
>   [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
>   [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
>   [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
>   [i915#9812]: https://gitlab.freedesktop.org/drm/intel/issues/9812
>   [i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * IGT: IGT_7798 -> IGTPW_10972
> 
>   CI-20190529: 20190529
>   CI_DRM_14522: 406e10d886a22211d2866bfa9322aec1727171f8 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGTPW_10972: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/index.html
>   IGT_7798: 5e3263748a636ebc91ecfafbd339870c77e3eed6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/index.html

-- 

✓ CI.xeBAT: success for lib/xe_mmio: Introduce Xe MMIO lib (rev3)

[Patchwork]

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== Series Details ==

Series: lib/xe_mmio: Introduce Xe MMIO lib (rev3)
URL   : https://patchwork.freedesktop.org/series/131591/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7798_BAT -> XEIGTPW_10972_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (5 -> 5)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_7798 -> IGTPW_10972

  IGTPW_10972: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10972/index.html
  IGT_7798: 5e3263748a636ebc91ecfafbd339870c77e3eed6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1033-406e10d886a22211d2866bfa9322aec1727171f8: 406e10d886a22211d2866bfa9322aec1727171f8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10972/index.html

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