From: "Zbigniew Kempczyński" <zbigniew.kempczynski@intel.com>
To: igt-dev@lists.freedesktop.org
Cc: "Zbigniew Kempczyński" <zbigniew.kempczynski@intel.com>,
"Juha-Pekka Heikkila" <juhapekka.heikkila@gmail.com>
Subject: [PATCH i-g-t v4 07/11] lib/intel_cmds_info: Define tiling macros
Date: Wed, 8 May 2024 14:54:39 +0200 [thread overview]
Message-ID: <20240508125443.404402-8-zbigniew.kempczynski@intel.com> (raw)
In-Reply-To: <20240508125443.404402-1-zbigniew.kempczynski@intel.com>
Blitter tilings don't always matches supported render tilings so
it is necessary to add separate fields for this purpose. To avoid
multiple lines where supported tiling is glued with BIT(tiling)
it is worth to predefine them, especially they will be used in next
patch related to supported render copy tilings.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
v3: Predefine single tiling first, then complex (Karolina)
---
lib/intel_cmds_info.c | 110 +++++++++++++++++-------------------------
1 file changed, 45 insertions(+), 65 deletions(-)
diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c
index 669d3e5006..e7aabf6bfb 100644
--- a/lib/intel_cmds_info.c
+++ b/lib/intel_cmds_info.c
@@ -20,75 +20,59 @@
.flags = _flags, \
}
-static const struct blt_cmd_info src_copy = BLT_INFO(SRC_COPY, BIT(T_LINEAR));
-static const struct blt_cmd_info
- pre_gen6_xy_src_copy = BLT_INFO(XY_SRC_COPY,
- BIT(T_LINEAR) |
- BIT(T_XMAJOR));
-static const struct blt_cmd_info
- gen6_xy_src_copy = BLT_INFO(XY_SRC_COPY,
- BIT(T_LINEAR) |
- BIT(T_XMAJOR) |
- BIT(T_YMAJOR));
-static const struct blt_cmd_info
- gen11_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
- BIT(T_LINEAR) |
- BIT(T_YMAJOR) |
- BIT(T_YFMAJOR) |
- BIT(T_TILE64));
-static const struct blt_cmd_info
- gen12_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
- BIT(T_LINEAR) |
- BIT(T_YMAJOR) |
- BIT(T_TILE4) |
- BIT(T_TILE64));
-static const struct blt_cmd_info
- dg2_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
- BIT(T_LINEAR) |
- BIT(T_XMAJOR) |
- BIT(T_TILE4) |
- BIT(T_TILE64));
-static const struct blt_cmd_info
- pvc_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
- BIT(T_LINEAR) |
- BIT(T_TILE4) |
- BIT(T_TILE64));
-
-static const struct blt_cmd_info
- gen12_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
- BIT(T_LINEAR) |
- BIT(T_YMAJOR));
-static const struct blt_cmd_info
- dg2_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY,
- BIT(T_LINEAR) |
- BIT(T_XMAJOR) |
- BIT(T_TILE4) |
- BIT(T_TILE64),
+#define TILE_4 BIT(T_TILE4)
+#define TILE_64 BIT(T_TILE64)
+#define TILE_L BIT(T_LINEAR)
+#define TILE_X BIT(T_XMAJOR)
+#define TILE_Y BIT(T_YMAJOR)
+#define TILE_Yf BIT(T_YFMAJOR)
+
+#define TILE_L_4_64 (TILE_L | TILE_4 | TILE_64)
+#define TILE_L_X (TILE_L | TILE_X)
+#define TILE_L_X_Y (TILE_L | TILE_X | TILE_Y)
+#define TILE_L_X_4_64 (TILE_L | TILE_X | TILE_4 | TILE_64)
+#define TILE_L_Y (TILE_L | TILE_Y)
+#define TILE_L_Y_4_64 (TILE_L | TILE_Y | TILE_4 | TILE_64)
+#define TILE_L_Y_Yf_64 (TILE_L | TILE_Y | TILE_Yf | TILE_64)
+
+static const struct blt_cmd_info src_copy = BLT_INFO(SRC_COPY, TILE_L);
+static const struct blt_cmd_info
+ pre_gen6_xy_src_copy = BLT_INFO(XY_SRC_COPY, TILE_L_X);
+
+static const struct blt_cmd_info
+ gen6_xy_src_copy = BLT_INFO(XY_SRC_COPY, TILE_L_X_Y);
+
+static const struct blt_cmd_info
+ gen11_xy_fast_copy = BLT_INFO(XY_FAST_COPY, TILE_L_Y_Yf_64);
+
+static const struct blt_cmd_info
+ gen12_xy_fast_copy = BLT_INFO(XY_FAST_COPY, TILE_L_Y_4_64);
+
+static const struct blt_cmd_info
+ dg2_xy_fast_copy = BLT_INFO(XY_FAST_COPY, TILE_L_X_4_64);
+
+static const struct blt_cmd_info
+ pvc_xy_fast_copy = BLT_INFO(XY_FAST_COPY, TILE_L_4_64);
+
+static const struct blt_cmd_info
+ gen12_xy_block_copy = BLT_INFO(XY_BLOCK_COPY, TILE_L_Y);
+
+static const struct blt_cmd_info
+ dg2_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY, TILE_L_X_4_64,
BLT_CMD_EXTENDED |
BLT_CMD_SUPPORTS_COMPRESSION);
static const struct blt_cmd_info
- xe2_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY,
- BIT(T_LINEAR) |
- BIT(T_XMAJOR) |
- BIT(T_TILE4) |
- BIT(T_TILE64),
+ xe2_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY, TILE_L_X_4_64,
BLT_CMD_EXTENDED |
BLT_CMD_SUPPORTS_COMPRESSION);
static const struct blt_cmd_info
- mtl_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY,
- BIT(T_LINEAR) |
- BIT(T_XMAJOR) |
- BIT(T_TILE4) |
- BIT(T_TILE64),
+ mtl_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY, TILE_L_X_4_64,
BLT_CMD_EXTENDED);
static const struct blt_cmd_info
- pvc_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY,
- BIT(T_LINEAR) |
- BIT(T_TILE4) |
- BIT(T_TILE64),
+ pvc_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY, TILE_L_4_64,
BLT_CMD_EXTENDED);
static const struct blt_cmd_info
@@ -102,17 +86,13 @@ static const struct blt_cmd_info
BIT(M_MATRIX));
static const struct blt_cmd_info
- pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT,
- BIT(T_LINEAR) |
- BIT(T_XMAJOR));
+ pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT, TILE_L_X);
static const struct blt_cmd_info
- gen6_xy_color_blt = BLT_INFO_EXT(XY_COLOR_BLT,
- BIT(T_LINEAR) |
- BIT(T_YMAJOR) |
- BIT(T_XMAJOR),
+ gen6_xy_color_blt = BLT_INFO_EXT(XY_COLOR_BLT, TILE_L_X_Y,
BLT_CMD_EXTENDED);
+
const struct intel_cmds_info pre_gen6_cmds_info = {
.blt_cmds = {
[SRC_COPY] = &src_copy,
--
2.34.1
next prev parent reply other threads:[~2024-05-08 12:55 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-08 12:54 [PATCH i-g-t v4 00/11] Add render-copy compression on Xe+ Zbigniew Kempczyński
2024-05-08 12:54 ` [PATCH i-g-t v4 01/11] lib/intel_bufops: Store devid on buffer ops creation Zbigniew Kempczyński
2024-05-08 12:54 ` [PATCH i-g-t v4 02/11] lib/intel_blt: Rename confusing fb tile to i915 tile Zbigniew Kempczyński
2024-05-08 12:54 ` [PATCH i-g-t v4 03/11] lib/intel_blt: Add i915 -> blt tile helper converter Zbigniew Kempczyński
2024-05-08 12:54 ` [PATCH i-g-t v4 04/11] lib/intel_bufops: Restrict tilings on non-flatccs platforms Zbigniew Kempczyński
2024-05-08 12:54 ` [PATCH i-g-t v4 05/11] lib/intel_bufops: Start supporting compression on Xe2+ Zbigniew Kempczyński
2024-05-08 12:54 ` [PATCH i-g-t v4 06/11] lib/rendercopy_gen9: Separate xe and xe2 compression format Zbigniew Kempczyński
2024-05-08 12:54 ` Zbigniew Kempczyński [this message]
2024-05-08 12:54 ` [PATCH i-g-t v4 08/11] lib/intel_cmds_info: Introduce render tilings Zbigniew Kempczyński
2024-05-08 12:54 ` [PATCH i-g-t v4 09/11] lib/intel_blt: Add render tilings and compression support helper Zbigniew Kempczyński
2024-05-08 12:54 ` [PATCH i-g-t v4 10/11] tests/xe_render_copy: Add subtest which exercises compression Zbigniew Kempczyński
2024-05-08 12:54 ` [PATCH i-g-t v4 11/11] tests/xe_intel_bb: Use supported tilings instead hardcoded ones Zbigniew Kempczyński
2024-05-09 5:18 ` Karolina Stolarek
2024-05-08 17:41 ` ✓ CI.xeBAT: success for Add render-copy compression on Xe+ (rev4) Patchwork
2024-05-08 17:48 ` ✓ Fi.CI.BAT: " Patchwork
2024-05-09 3:22 ` ✗ CI.xeFULL: failure " Patchwork
2024-05-09 8:34 ` ✓ Fi.CI.IGT: success " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240508125443.404402-8-zbigniew.kempczynski@intel.com \
--to=zbigniew.kempczynski@intel.com \
--cc=igt-dev@lists.freedesktop.org \
--cc=juhapekka.heikkila@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox