* [PATCH v6 0/5] lib/gpgpu: add shader support
@ 2024-06-11 10:40 Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 1/5] lib/gpu_cmds: add Xe_LP version of emit_vfe_state Andrzej Hajda
` (6 more replies)
0 siblings, 7 replies; 9+ messages in thread
From: Andrzej Hajda @ 2024-06-11 10:40 UTC (permalink / raw)
To: igt-dev
Cc: Kamil Konieczny, Dominik Grzegorzek, Christoph Manszewski,
Zbigniew Kempczyński, Gwan-gyeong Mun, Andrzej Hajda
This patchset adds shader support to mainline IGT.
Together with iga64 inline assembly and demo test using both.
The patches were cherry-picked/trimmed from internal branch,
quite painful process. I hope I have not cut off too much :)
v3:
- bumped minimal meson version,
- use old string literals to satisfy clang
v4:
- bump meson to latest version supported by CI builder
v5:
- just small update, to ping potential reviewers :)
- revert back required meson version, instead use old syntax to make CI happy
v6:
- addressed most Kamil's comments - added docs for public functions,
generator script moved to scripts, added ifdef guards to iga64_macros.h,
fixed docs and description in xe_exec_sip test
To: igt-dev@lists.freedesktop.org
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Christoph Manszewski <christoph.manszewski@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
- Link to v1: https://lore.kernel.org/r/20240429-iga64_inline_ups-v1-0-2e9ac46cf6ba@intel.com
- Link to v2: https://lore.kernel.org/r/20240515-iga64_inline_ups-v2-0-693743cb0985@intel.com
- Link to v3: https://lore.kernel.org/r/20240524-iga64_inline_ups-v3-0-62427617ced3@intel.com
- Link to v4: https://lore.kernel.org/r/20240524-iga64_inline_ups-v4-0-c2e31c55e083@intel.com
- Link to v5: https://lore.kernel.org/r/20240528-iga64_inline_ups-v5-0-fdd8e9dcd64c@intel.com
---
Andrzej Hajda (5):
lib/gpu_cmds: add Xe_LP version of emit_vfe_state
lib/gpgpu_shader: tooling for preparing and running gpgpu shaders
lib/gpgpu_shader: add inline support for iga64 assembly
lib/igt_sysfs: add helpers to access engine sysfs directory
intel/xe_exec_sip: add shader sanity test
lib/gpgpu_shader.c | 313 +++++++++++++++++++++++++++++++++++++++++++
lib/gpgpu_shader.h | 63 +++++++++
lib/gpu_cmds.c | 52 ++++++-
lib/gpu_cmds.h | 6 +
lib/iga64_generated_codes.c | 87 ++++++++++++
lib/iga64_macros.h | 18 +++
lib/igt_sysfs.c | 71 ++++++++++
lib/igt_sysfs.h | 3 +
lib/meson.build | 18 +++
meson.build | 9 +-
scripts/generate_iga64_codes | 115 ++++++++++++++++
scripts/meson.build | 1 +
tests/intel/xe_exec_sip.c | 197 +++++++++++++++++++++++++++
tests/meson.build | 1 +
14 files changed, 944 insertions(+), 10 deletions(-)
---
base-commit: 73618605b4370cf902267aaf1d25666ff5e26112
change-id: 20240425-iga64_inline_ups-438ddfd6023f
Best regards,
--
Andrzej Hajda <andrzej.hajda@intel.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v6 1/5] lib/gpu_cmds: add Xe_LP version of emit_vfe_state
2024-06-11 10:40 [PATCH v6 0/5] lib/gpgpu: add shader support Andrzej Hajda
@ 2024-06-11 10:40 ` Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 2/5] lib/gpgpu_shader: tooling for preparing and running gpgpu shaders Andrzej Hajda
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Andrzej Hajda @ 2024-06-11 10:40 UTC (permalink / raw)
To: igt-dev
Cc: Kamil Konieczny, Dominik Grzegorzek, Christoph Manszewski,
Zbigniew Kempczyński, Gwan-gyeong Mun, Andrzej Hajda
In Xe_LP version there is added argument to control EU thread
dispatching mode. For shaders lagacy mode is used.
v2: added commit description
v6: added public function descriptions
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
---
lib/gpu_cmds.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++------
lib/gpu_cmds.h | 6 ++++++
2 files changed, 52 insertions(+), 6 deletions(-)
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 378fa9166ab8..cd0623dc28a3 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -651,10 +651,10 @@ gen7_emit_vfe_state(struct intel_bb *ibb, uint32_t threads,
intel_bb_out(ibb, 0);
}
-void
-gen8_emit_vfe_state(struct intel_bb *ibb, uint32_t threads,
- uint32_t urb_entries, uint32_t urb_size,
- uint32_t curbe_size)
+static void
+__gen8_emit_vfe_state(struct intel_bb *ibb, uint32_t threads,
+ uint32_t urb_entries, uint32_t urb_size,
+ uint32_t curbe_size, bool legacy_mode)
{
intel_bb_out(ibb, GEN7_MEDIA_VFE_STATE | (9 - 2));
@@ -662,8 +662,8 @@ gen8_emit_vfe_state(struct intel_bb *ibb, uint32_t threads,
intel_bb_out(ibb, 0);
intel_bb_out(ibb, 0);
- /* number of threads & urb entries */
- intel_bb_out(ibb, threads << 16 | urb_entries << 8);
+ /* number of threads & urb entries & eu fusion */
+ intel_bb_out(ibb, threads << 16 | urb_entries << 8 | legacy_mode << 6);
intel_bb_out(ibb, 0);
@@ -676,6 +676,25 @@ gen8_emit_vfe_state(struct intel_bb *ibb, uint32_t threads,
intel_bb_out(ibb, 0);
}
+/**
+ * gen8_emit_vfe_state:
+ * @ibb: batchbuffer
+ * @threads: maximum number of threads
+ * @urb_entries: number of URB entries
+ * @urb_size: URB entry allocation size
+ * @curbe_size: CURBE allocation size
+ *
+ * Emits instruction MEDIA_VFE_STATE for Gen8+ which sets Video Front End (VFE)
+ * state.
+ */
+void gen8_emit_vfe_state(struct intel_bb *ibb, uint32_t threads,
+ uint32_t urb_entries, uint32_t urb_size,
+ uint32_t curbe_size)
+{
+ __gen8_emit_vfe_state(ibb, threads, urb_entries, urb_size, curbe_size,
+ false);
+}
+
void
gen7_emit_curbe_load(struct intel_bb *ibb, uint32_t curbe_buffer)
{
@@ -864,6 +883,27 @@ gen7_emit_media_objects(struct intel_bb *ibb,
gen_emit_media_object(ibb, x + i * 16, y + j * 16);
}
+/**
+ * xelp_emit_vfe_state:
+ * @ibb: pointer to intel_bb
+ * @threads: maximum number of threads
+ * @urb_entries: number of URB entries
+ * @urb_size: URB entry allocation size
+ * @curbe_size: CURBE allocation size
+ * @legacy_mode: if set, threads are dispatched individually (legacy mode),
+ * otherwise they are dispatched in sets(fused EU mode)
+ *
+ * Emits instruction MEDIA_VFE_STATE for XeLP which sets Video Front End (VFE)
+ * state.
+ */
+void xelp_emit_vfe_state(struct intel_bb *ibb, uint32_t threads,
+ uint32_t urb_entries, uint32_t urb_size,
+ uint32_t curbe_size, bool legacy_mode)
+{
+ return __gen8_emit_vfe_state(ibb, threads, urb_entries, urb_size,
+ curbe_size, legacy_mode);
+}
+
/*
* XEHP
*/
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 348c6c9453e9..1b9156a80c7c 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -81,6 +81,12 @@ void
gen8_emit_vfe_state(struct intel_bb *ibb, uint32_t threads,
uint32_t urb_entries, uint32_t urb_size,
uint32_t curbe_size);
+
+void
+xelp_emit_vfe_state(struct intel_bb *ibb, uint32_t threads,
+ uint32_t urb_entries, uint32_t urb_size,
+ uint32_t curbe_size, bool legacy_mode);
+
void
gen7_emit_curbe_load(struct intel_bb *ibb, uint32_t curbe_buffer);
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 2/5] lib/gpgpu_shader: tooling for preparing and running gpgpu shaders
2024-06-11 10:40 [PATCH v6 0/5] lib/gpgpu: add shader support Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 1/5] lib/gpu_cmds: add Xe_LP version of emit_vfe_state Andrzej Hajda
@ 2024-06-11 10:40 ` Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 3/5] lib/gpgpu_shader: add inline support for iga64 assembly Andrzej Hajda
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Andrzej Hajda @ 2024-06-11 10:40 UTC (permalink / raw)
To: igt-dev
Cc: Kamil Konieczny, Dominik Grzegorzek, Christoph Manszewski,
Zbigniew Kempczyński, Gwan-gyeong Mun, Andrzej Hajda
Implement tooling for building shaders for specific generations.
The library allows you to build and run shader from precompiled blocks
and provides an abstraction layer over gpgpu pipeline.
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
lib/gpgpu_shader.c | 211 +++++++++++++++++++++++++++++++++++++++++++++++++++++
lib/gpgpu_shader.h | 38 ++++++++++
lib/meson.build | 1 +
3 files changed, 250 insertions(+)
diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
new file mode 100644
index 000000000000..d14301789421
--- /dev/null
+++ b/lib/gpgpu_shader.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ *
+ * Author: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
+ */
+
+#include <i915_drm.h>
+
+#include "ioctl_wrappers.h"
+#include "gpgpu_shader.h"
+#include "gpu_cmds.h"
+
+#define SUPPORTED_GEN_VER 1200 /* Support TGL and up */
+
+#define PAGE_SIZE 4096
+#define BATCH_STATE_SPLIT 2048
+/* VFE STATE params */
+#define THREADS (1 << 16) /* max value */
+#define GEN8_GPGPU_URB_ENTRIES 1
+#define GPGPU_URB_SIZE 0
+#define GPGPU_CURBE_SIZE 0
+#define GEN7_VFE_STATE_GPGPU_MODE 1
+
+static uint32_t fill_sip(struct intel_bb *ibb,
+ const uint32_t sip[][4],
+ const size_t size)
+{
+ uint32_t *sip_dst;
+ uint32_t offset;
+
+ intel_bb_ptr_align(ibb, 16);
+ sip_dst = intel_bb_ptr(ibb);
+ offset = intel_bb_offset(ibb);
+
+ memcpy(sip_dst, sip, size);
+
+ intel_bb_ptr_add(ibb, size);
+
+ return offset;
+}
+
+static void emit_sip(struct intel_bb *ibb, const uint64_t offset)
+{
+ intel_bb_out(ibb, GEN4_STATE_SIP | (3 - 2));
+ intel_bb_out(ibb, lower_32_bits(offset));
+ intel_bb_out(ibb, upper_32_bits(offset));
+}
+
+static void
+__xelp_gpgpu_execfunc(struct intel_bb *ibb,
+ struct intel_buf *target,
+ unsigned int x_dim, unsigned int y_dim,
+ struct gpgpu_shader *shdr,
+ struct gpgpu_shader *sip,
+ uint64_t ring, bool explicit_engine)
+{
+ uint32_t interface_descriptor, sip_offset;
+ uint64_t engine;
+
+ intel_bb_add_intel_buf(ibb, target, true);
+
+ intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
+
+ interface_descriptor = gen8_fill_interface_descriptor(ibb, target,
+ shdr->instr,
+ 4 * shdr->size);
+
+ if (sip && sip->size)
+ sip_offset = fill_sip(ibb, sip->instr, 4 * sip->size);
+ else
+ sip_offset = 0;
+
+ intel_bb_ptr_set(ibb, 0);
+
+ /* GPGPU pipeline */
+ intel_bb_out(ibb, GEN7_PIPELINE_SELECT | GEN9_PIPELINE_SELECTION_MASK |
+ PIPELINE_SELECT_GPGPU);
+
+ gen9_emit_state_base_address(ibb);
+
+ xelp_emit_vfe_state(ibb, THREADS, GEN8_GPGPU_URB_ENTRIES,
+ GPGPU_URB_SIZE, GPGPU_CURBE_SIZE, true);
+
+ gen7_emit_interface_descriptor_load(ibb, interface_descriptor);
+
+ if (sip_offset)
+ emit_sip(ibb, sip_offset);
+
+ gen8_emit_gpgpu_walk(ibb, 0, 0, x_dim * 16, y_dim);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 32);
+
+ engine = explicit_engine ? ring : I915_EXEC_DEFAULT;
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ engine | I915_EXEC_NO_RELOC, false);
+}
+
+static void
+__xehp_gpgpu_execfunc(struct intel_bb *ibb,
+ struct intel_buf *target,
+ unsigned int x_dim, unsigned int y_dim,
+ struct gpgpu_shader *shdr,
+ struct gpgpu_shader *sip,
+ uint64_t ring, bool explicit_engine)
+{
+ struct xehp_interface_descriptor_data idd;
+ uint32_t sip_offset;
+ uint64_t engine;
+
+ intel_bb_add_intel_buf(ibb, target, true);
+
+ intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
+
+ xehp_fill_interface_descriptor(ibb, target, shdr->instr,
+ 4 * shdr->size, &idd);
+
+ if (sip && sip->size)
+ sip_offset = fill_sip(ibb, sip->instr, 4 * sip->size);
+ else
+ sip_offset = 0;
+
+ intel_bb_ptr_set(ibb, 0);
+
+ /* GPGPU pipeline */
+ intel_bb_out(ibb, GEN7_PIPELINE_SELECT | GEN9_PIPELINE_SELECTION_MASK |
+ PIPELINE_SELECT_GPGPU);
+ xehp_emit_state_base_address(ibb);
+ xehp_emit_state_compute_mode(ibb);
+ xehp_emit_state_binding_table_pool_alloc(ibb);
+ xehp_emit_cfe_state(ibb, THREADS);
+
+ if (sip_offset)
+ emit_sip(ibb, sip_offset);
+
+ xehp_emit_compute_walk(ibb, 0, 0, x_dim * 16, y_dim, &idd, 0x0);
+
+ intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+ intel_bb_ptr_align(ibb, 32);
+
+ engine = explicit_engine ? ring : I915_EXEC_DEFAULT;
+ intel_bb_exec(ibb, intel_bb_offset(ibb),
+ engine | I915_EXEC_NO_RELOC, false);
+
+}
+
+/**
+ * gpgpu_shader_exec:
+ * @ibb: pointer to initialized intel_bb
+ * @target: pointer to initialized intel_buf to be written by shader/sip
+ * @x_dim: gpgpu/compute walker thread group width
+ * @y_dim: gpgpu/compute walker thread group height
+ * @shdr: shader to be executed
+ * @sip: sip to be executed, can be NULL
+ * @ring: engine index
+ * @explicit_engine: whether to use provided engine index
+ *
+ * Execute provided shader in asynchronous fashion. To wait for completion,
+ * caller has to use the provided ibb handle.
+ */
+void gpgpu_shader_exec(struct intel_bb *ibb,
+ struct intel_buf *target,
+ unsigned int x_dim, unsigned int y_dim,
+ struct gpgpu_shader *shdr,
+ struct gpgpu_shader *sip,
+ uint64_t ring, bool explicit_engine)
+{
+ igt_require(shdr->gen_ver >= SUPPORTED_GEN_VER);
+ igt_assert(ibb->size >= PAGE_SIZE);
+ igt_assert(ibb->ptr == ibb->batch);
+
+ if (shdr->gen_ver >= 1250)
+ __xehp_gpgpu_execfunc(ibb, target, x_dim, y_dim, shdr, sip,
+ ring, explicit_engine);
+ else
+ __xelp_gpgpu_execfunc(ibb, target, x_dim, y_dim, shdr, sip,
+ ring, explicit_engine);
+}
+
+/**
+ * gpgpu_shader_create:
+ * @fd: drm fd - i915 or xe
+ *
+ * Creates empty shader.
+ *
+ * Returns: pointer to empty shader struct.
+ */
+struct gpgpu_shader *gpgpu_shader_create(int fd)
+{
+ struct gpgpu_shader *shdr = calloc(1, sizeof(struct gpgpu_shader));
+ const struct intel_device_info *info;
+
+ info = intel_get_device_info(intel_get_drm_devid(fd));
+ shdr->gen_ver = 100 * info->graphics_ver + info->graphics_rel;
+ shdr->max_size = 16 * 4;
+ shdr->code = malloc(4 * shdr->max_size);
+ return shdr;
+}
+
+/**
+ * gpgpu_shader_destroy:
+ * @shdr: pointer to shader struct created with 'gpgpu_shader_create'
+ *
+ * Frees resources of gpgpu_shader struct.
+ */
+void gpgpu_shader_destroy(struct gpgpu_shader *shdr)
+{
+ free(shdr->code);
+ free(shdr);
+}
diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
new file mode 100644
index 000000000000..02f6f1aad1e3
--- /dev/null
+++ b/lib/gpgpu_shader.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef GPGPU_SHADER_H
+#define GPGPU_SHADER_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+struct intel_bb;
+struct intel_buf;
+
+struct gpgpu_shader {
+ uint32_t gen_ver;
+ uint32_t size;
+ uint32_t max_size;
+ union {
+ uint32_t *code;
+ uint32_t (*instr)[4];
+ };
+};
+
+struct gpgpu_shader *gpgpu_shader_create(int fd);
+void gpgpu_shader_destroy(struct gpgpu_shader *shdr);
+
+void gpgpu_shader_dump(struct gpgpu_shader *shdr);
+
+void gpgpu_shader_exec(struct intel_bb *ibb,
+ struct intel_buf *target,
+ unsigned int x_dim, unsigned int y_dim,
+ struct gpgpu_shader *shdr,
+ struct gpgpu_shader *sip,
+ uint64_t ring, bool explicit_engine);
+
+#endif /* GPGPU_SHADER_H */
diff --git a/lib/meson.build b/lib/meson.build
index e2f740c116f8..0a3084f8aea2 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -72,6 +72,7 @@ lib_sources = [
'media_spin.c',
'media_fill.c',
'gpgpu_fill.c',
+ 'gpgpu_shader.c',
'gpu_cmds.c',
'rendercopy_i915.c',
'rendercopy_i830.c',
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 3/5] lib/gpgpu_shader: add inline support for iga64 assembly
2024-06-11 10:40 [PATCH v6 0/5] lib/gpgpu: add shader support Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 1/5] lib/gpu_cmds: add Xe_LP version of emit_vfe_state Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 2/5] lib/gpgpu_shader: tooling for preparing and running gpgpu shaders Andrzej Hajda
@ 2024-06-11 10:40 ` Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 4/5] lib/igt_sysfs: add helpers to access engine sysfs directory Andrzej Hajda
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Andrzej Hajda @ 2024-06-11 10:40 UTC (permalink / raw)
To: igt-dev
Cc: Kamil Konieczny, Dominik Grzegorzek, Christoph Manszewski,
Zbigniew Kempczyński, Gwan-gyeong Mun, Andrzej Hajda
With this patch adding iga64 assembly should be similar to
adding x86 assembly inline. Simple example:
emit_iga64_code(shdr, set_exception, R"ASM(
or (1|M0) cr0.1<1>:ud cr0.1<0;1,0>:ud ARG(0):ud
)ASM", value);
Note presence of 'ARG(0)', it will be replaced by 'value' argument,
multiple arguments are possible.
More sophisticated examples in following patches.
How does it works:
1. Raw string literals (C++ feature available in gcc as extension):
R"ASM(...)ASM" allows to use multiline/unescaped string literals.
If for some reason they cannot be used we could always fallback to
old ugly way of handling multiline strings with escape characters:
emit_iga64_code(shdr, set_exception, "\n\
or (1|M0) cr0.1<1>:ud cr0.1<0;1,0>:ud ARG(0):ud\n\
", value);
2. emit_iga64_code puts the assembly string into special linker section,
and calls __emit_iga64_code with pointer to external variable
which will contain code templates generated from the assembly for all
supported platforms, remaining arguments are put to temporal array
to eventually patch the code with positional arguments.
3. During build phase the linker section is scanned for assemblies.
Every assembly is preprocessed with cpp, to replace ARG(x) macros with
magic numbers, and to provide different code for different platforms
if needed. Then output file is compiled with iga64, and then .c file
is generated with global variables pointing to hexified iga64 codes.
v2:
- fixed meson paths to script,
- added check if compiler supports all platforms,
- include assembly names in MD5 calculations,
- use more specific name for MD5 sum
v3:
- bump minimal meson version to kill "ERROR: Expecting eol got id." bug
v4:
- set minimal meson to 0.49.2 - builder uses it
v5:
- revert back minimal version of meson, instead use old syntax a.contains(b)
v6:
- generate_iga64_codes moved to scripts dir,
- added include guards to iga64_macros.h
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
lib/gpgpu_shader.c | 39 +++++++++++++++
lib/gpgpu_shader.h | 25 ++++++++++
lib/iga64_generated_codes.c | 6 +++
lib/iga64_macros.h | 18 +++++++
lib/meson.build | 17 +++++++
meson.build | 9 ++--
scripts/generate_iga64_codes | 115 +++++++++++++++++++++++++++++++++++++++++++
scripts/meson.build | 1 +
8 files changed, 226 insertions(+), 4 deletions(-)
diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
index d14301789421..3317e9e35c91 100644
--- a/lib/gpgpu_shader.c
+++ b/lib/gpgpu_shader.c
@@ -11,6 +11,9 @@
#include "gpgpu_shader.h"
#include "gpu_cmds.h"
+#define IGA64_ARG0 0xc0ded000
+#define IGA64_ARG_MASK 0xffffff00
+
#define SUPPORTED_GEN_VER 1200 /* Support TGL and up */
#define PAGE_SIZE 4096
@@ -22,6 +25,42 @@
#define GPGPU_CURBE_SIZE 0
#define GEN7_VFE_STATE_GPGPU_MODE 1
+static void gpgpu_shader_extend(struct gpgpu_shader *shdr)
+{
+ shdr->max_size <<= 1;
+ shdr->code = realloc(shdr->code, 4 * shdr->max_size);
+}
+
+void
+__emit_iga64_code(struct gpgpu_shader *shdr, struct iga64_template const *tpls,
+ int argc, uint32_t *argv)
+{
+ uint32_t *ptr;
+
+ igt_require_f(shdr->gen_ver >= SUPPORTED_GEN_VER,
+ "No available shader templates for platforms older than XeLP\n");
+
+ while (shdr->gen_ver < tpls->gen_ver)
+ tpls++;
+
+ while (shdr->max_size < shdr->size + tpls->size)
+ gpgpu_shader_extend(shdr);
+
+ ptr = shdr->code + shdr->size;
+ memcpy(ptr, tpls->code, 4 * tpls->size);
+
+ /* patch the template */
+ for (int n, i = 0; i < tpls->size; ++i) {
+ if ((ptr[i] & IGA64_ARG_MASK) != IGA64_ARG0)
+ continue;
+ n = ptr[i] - IGA64_ARG0;
+ igt_assert(n < argc);
+ ptr[i] = argv[n];
+ }
+
+ shdr->size += tpls->size;
+}
+
static uint32_t fill_sip(struct intel_bb *ibb,
const uint32_t sip[][4],
const size_t size)
diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
index 02f6f1aad1e3..0b997deba8bb 100644
--- a/lib/gpgpu_shader.h
+++ b/lib/gpgpu_shader.h
@@ -23,6 +23,27 @@ struct gpgpu_shader {
};
};
+struct iga64_template {
+ uint32_t gen_ver;
+ uint32_t size;
+ const uint32_t *code;
+};
+
+#pragma GCC diagnostic ignored "-Wnested-externs"
+
+void
+__emit_iga64_code(struct gpgpu_shader *shdr, const struct iga64_template *tpls,
+ int argc, uint32_t *argv);
+
+#define emit_iga64_code(__shdr, __name, __txt, __args...) \
+({ \
+ static const char t[] __attribute__ ((section(".iga64_assembly"),used)) \
+ ="iga64_assembly_" #__name ":" __txt "\n"; \
+ extern struct iga64_template const iga64_code_ ## __name[]; \
+ u32 args[] = { __args }; \
+ __emit_iga64_code(__shdr, iga64_code_ ## __name, ARRAY_SIZE(args), args); \
+})
+
struct gpgpu_shader *gpgpu_shader_create(int fd);
void gpgpu_shader_destroy(struct gpgpu_shader *shdr);
@@ -35,4 +56,8 @@ void gpgpu_shader_exec(struct intel_bb *ibb,
struct gpgpu_shader *sip,
uint64_t ring, bool explicit_engine);
+void gpgpu_shader__eot(struct gpgpu_shader *shdr);
+void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
+ uint32_t y_offset);
+
#endif /* GPGPU_SHADER_H */
diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
new file mode 100644
index 000000000000..219436983585
--- /dev/null
+++ b/lib/iga64_generated_codes.c
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: MIT */
+/* Generated using Intel Graphics Assembler 1.1.0-int */
+
+#include "gpgpu_shader.h"
+
+#define MD5_SUM_IGA64_ASMS 68b329da9893e34099c7d8ad5cb9c940
diff --git a/lib/iga64_macros.h b/lib/iga64_macros.h
new file mode 100644
index 000000000000..149b816c7ca8
--- /dev/null
+++ b/lib/iga64_macros.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2024 Intel Corporation */
+
+/* Header used during pre-process phase of iga64 assembly. */
+
+#ifndef IGA64_MACROS_H
+#define IGA64_MACROS_H
+
+#define ARG(n) (0xc0ded000 + n)
+
+/* send instruction for DG2+ requires 0 length in case src1 is null, BSpec: 47443 */
+#if GEN_VER < 1271
+#define src1_null null
+#else
+#define src1_null null:0
+#endif
+
+#endif
diff --git a/lib/meson.build b/lib/meson.build
index 0a3084f8aea2..82e7dacad153 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -216,7 +216,10 @@ lib_version = vcs_tag(input : 'version.h.in', output : 'version.h',
fallback : 'NO-GIT',
command : vcs_command )
+iga64_assembly_sources = [ 'gpgpu_shader.c' ]
+
lib_intermediates = []
+iga64_assembly_libs = []
foreach f: lib_sources
name = f.underscorify()
lib = static_library('igt-' + name,
@@ -230,8 +233,22 @@ foreach f: lib_sources
])
lib_intermediates += lib
+ if iga64_assembly_sources.contains(f)
+ iga64_assembly_libs += lib
+ endif
endforeach
+iga64_generated_codes = custom_target(
+ 'iga64_generated_codes.c',
+ input : [ 'iga64_generated_codes.c' ] + iga64_assembly_libs,
+ output : 'iga64_generated_codes.c',
+ command : [ generate_iga64_codes, '-o', '@OUTPUT@', '-i', '@INPUT@' ]
+)
+
+lib_intermediates += static_library('igt-iga64_generated_codes.c',
+ [ iga64_generated_codes, lib_version ]
+ )
+
lib_igt_build = shared_library('igt',
['dummy.c'],
link_whole: lib_intermediates,
diff --git a/meson.build b/meson.build
index ab44aadb1fdf..716a4d7bde85 100644
--- a/meson.build
+++ b/meson.build
@@ -341,6 +341,11 @@ else
vmwgfx_rpathdir = ''
endif
+build_testplan = get_option('testplan')
+build_sphinx = get_option('sphinx')
+
+subdir('scripts')
+
subdir('lib')
if build_tests
subdir('tests')
@@ -349,9 +354,6 @@ else
endif
build_info += 'Build tests: @0@'.format(build_tests)
-build_testplan = get_option('testplan')
-build_sphinx = get_option('sphinx')
-
subdir('benchmarks')
subdir('tools')
subdir('runner')
@@ -360,7 +362,6 @@ if libdrm_intel.found()
endif
subdir('overlay')
subdir('man')
-subdir('scripts')
subdir('docs')
message('Build options')
diff --git a/scripts/generate_iga64_codes b/scripts/generate_iga64_codes
new file mode 100755
index 000000000000..4bea6c2382c9
--- /dev/null
+++ b/scripts/generate_iga64_codes
@@ -0,0 +1,115 @@
+#!/bin/bash
+# SPDX-License-Identifier: MIT
+# Copyright © 2024 Intel Corporation
+# Author: Andrzej Hajda <andrzej.hajda@intel.com>
+
+# List of supported platforms, in format gen100:platform, where gen100 equals
+# to minimal GPU generation supported by platform multiplied by 100 and platform
+# is one of platforms supported by -p switch of iga64.
+#
+# Must be in decreasing order, the last one must have gen100 equal 0"
+GEN_VERSIONS="2000:2 1272:12p72 1250:12p5 0:12p1"
+
+warn() {
+ echo -e "$1" >/dev/stderr
+}
+
+die() {
+ warn "DIE: $1"
+ exit 1
+}
+
+# parse args
+while getopts ':i:o:' opt; do
+ case $opt in
+ i) INPUT=$OPTARG;;
+ o) OUTPUT=$OPTARG;;
+ ?) die "Usage: $0 -i pre-generated-iga64-file -o generated-iga64-file libs-with-iga64-assembly [...]"
+ esac
+done
+LIBS=${@:OPTIND}
+
+# read all assemblies into ASMS array
+ASMS=()
+while read -d $'\0' asm; do
+ test -z "$asm" && continue
+ ASMS+=( "$asm" )
+done < <(for f in $LIBS; do objcopy --dump-section .iga64_assembly=/dev/stdout $f.p/*.o; done)
+
+# check if we need to recompile - checksum difference and compiler present
+MD5_ASMS="$(md5sum <<< "${ASMS[@]}" | cut -b1-32)"
+MD5_PRE="$(grep -Po '(?<=^#define MD5_SUM_IGA64_ASMS )\S{32,32}' $INPUT 2>/dev/null)"
+
+if [ "$MD5_ASMS" = "$MD5_PRE" ]; then
+ echo "iga64 assemblies not changed, reusing pre-compiled file $INPUT."
+ cp $INPUT $OUTPUT
+ exit 0
+fi
+
+type iga64 >/dev/null || {
+ warn "WARNING: iga64 assemblies changed, but iga64 compiler not present, CHANGES will have no effect. Install iga64 (libigc-tools package) to re-compile code."
+ cp $INPUT $OUTPUT
+ exit 0
+}
+
+# generate code file
+WD=$OUTPUT.d
+mkdir -p $WD
+
+# check if all required platforms are supported
+touch $WD/empty
+for gen in $GEN_VERSIONS; do
+ gen_name="${gen#*:}"
+ iga64 -p=$gen_name -d $WD/empty 2>/dev/null || {
+ warn "WARNING: iga64 assemblies changed, but iga64 compiler does not support platform '$gen_name', CHANGES will have no effect. Update iga64 (libigc-tools package) to re-compile code."
+ cp $INPUT $OUTPUT
+ exit 0
+ }
+done
+
+# returns count of numbers in strings of format "0x1234, 0x23434, ..."
+dword_count() {
+ n=${1//[^x]}
+ echo ${#n}
+}
+
+echo "Generating new $OUTPUT"
+
+cat <<-EOF >$OUTPUT
+/* SPDX-License-Identifier: MIT */
+/* Generated using $(iga64 |& head -1) */
+
+#include "gpgpu_shader.h"
+
+#define MD5_SUM_IGA64_ASMS $MD5_ASMS
+EOF
+
+for asm in "${ASMS[@]}"; do
+ asm_name="${asm%%:*}"
+ asm_code="${asm_name/assembly/code}"
+ asm_body="${asm#*:}"
+ cur_code=""
+ cur_ver=""
+ echo -e "\nstruct iga64_template const $asm_code[] = {" >>$OUTPUT
+ for gen in $GEN_VERSIONS; do
+ gen_ver="${gen%%:*}"
+ gen_name="${gen#*:}"
+ warn "Generating $asm_code for platform $gen_name"
+ cmd="cpp -P - -o $WD/$asm_name.$gen_name.asm"
+ cmd+=" -DGEN_VER=$gen_ver -imacros ../lib/iga64_macros.h"
+ eval "$cmd" <<<"$asm_body" || die "cpp error for $asm_name.$gen_name\ncmd: $cmd"
+ cmd="iga64 -Xauto-deps -Wall -p=$gen_name"
+ cmd+=" $WD/$asm_name.$gen_name.asm -o $WD/$asm_name.$gen_name.bin"
+ eval "$cmd" || die "iga64 error for $asm_name.$gen_name\ncmd: $cmd"
+ code="$(hexdump -e '"\t\t" 4/4 "0x%08x, " "\n"' $WD/$asm_name.$gen_name.bin)"
+ [ -z "$cur_code" ] && cur_code="$code"
+ [ "$cur_code" != "$code" ] && {
+ echo -e "\t{ .gen_ver = $cur_ver, .size = $(dword_count "$cur_code"), .code = (const uint32_t []) {\n$cur_code\n\t}}," >>$OUTPUT
+ cur_code="$code"
+ }
+ cur_ver=$gen_ver
+ done
+ echo -e "\t{ .gen_ver = $cur_ver, .size = $(dword_count "$cur_code"), .code = (const uint32_t []) {\n$cur_code\n\t}}\n};" >>$OUTPUT
+done
+
+cp $OUTPUT $INPUT
diff --git a/scripts/meson.build b/scripts/meson.build
index 98783222b6fc..6e64065c5ee7 100644
--- a/scripts/meson.build
+++ b/scripts/meson.build
@@ -14,3 +14,4 @@ endif
igt_doc_script = find_program('igt_doc.py', required : build_testplan)
gen_rst_index = find_program('gen_rst_index', required : build_sphinx)
+generate_iga64_codes = find_program('generate_iga64_codes')
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 4/5] lib/igt_sysfs: add helpers to access engine sysfs directory
2024-06-11 10:40 [PATCH v6 0/5] lib/gpgpu: add shader support Andrzej Hajda
` (2 preceding siblings ...)
2024-06-11 10:40 ` [PATCH v6 3/5] lib/gpgpu_shader: add inline support for iga64 assembly Andrzej Hajda
@ 2024-06-11 10:40 ` Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 5/5] intel/xe_exec_sip: add shader sanity test Andrzej Hajda
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Andrzej Hajda @ 2024-06-11 10:40 UTC (permalink / raw)
To: igt-dev
Cc: Kamil Konieczny, Dominik Grzegorzek, Christoph Manszewski,
Zbigniew Kempczyński, Gwan-gyeong Mun, Andrzej Hajda
Helpers follow convention of xe_sysfs_gt_(path|open).
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
lib/igt_sysfs.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
lib/igt_sysfs.h | 3 +++
2 files changed, 74 insertions(+)
diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c
index 0c5817eb1580..e11eecc25aa1 100644
--- a/lib/igt_sysfs.c
+++ b/lib/igt_sysfs.c
@@ -40,7 +40,9 @@
#include <dirent.h>
#include <unistd.h>
#include <fcntl.h>
+#include <xe_drm.h>
+#include "drmtest.h"
#include "igt_core.h"
#include "igt_sysfs.h"
#include "igt_device.h"
@@ -263,6 +265,75 @@ int xe_sysfs_gt_open(int xe_device, int gt)
return open(path, O_RDONLY);
}
+static const char *engine_class_to_str(__u16 class)
+{
+ const char *str[] = {
+ [DRM_XE_ENGINE_CLASS_RENDER] = "rcs",
+ [DRM_XE_ENGINE_CLASS_COPY] = "bcs",
+ [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = "vcs",
+ [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = "vecs",
+ [DRM_XE_ENGINE_CLASS_COMPUTE] = "ccs",
+ };
+
+ if (class < ARRAY_SIZE(str))
+ return str[class];
+
+ return "unk";
+}
+
+/**
+ * xe_sysfs_engine_path:
+ * @xe_device: fd of the device
+ * @gt: gt number
+ * @class: engine class
+ * @path: buffer to fill with the sysfs gt path to the device
+ * @pathlen: length of @path buffer
+ *
+ * Returns:
+ * The directory path, or NULL on failure.
+ */
+char *
+xe_sysfs_engine_path(int xe_device, int gt, int class, char *path, int pathlen)
+{
+ struct stat st;
+ int tile = IS_PONTEVECCHIO(intel_get_drm_devid(xe_device)) ? gt : 0;
+
+ if (xe_device < 0)
+ return NULL;
+
+ if (igt_debug_on(fstat(xe_device, &st)) || igt_debug_on(!S_ISCHR(st.st_mode)))
+ return NULL;
+
+ snprintf(path, pathlen, "/sys/dev/char/%d:%d/device/tile%d/gt%d/engines/%s",
+ major(st.st_rdev), minor(st.st_rdev), tile, gt, engine_class_to_str(class));
+
+ if (!access(path, F_OK))
+ return path;
+
+ return NULL;
+}
+
+/**
+ * xe_sysfs_engine_open:
+ * @xe_device: fd of the device
+ * @gt: gt number
+ * @class: engine class
+ *
+ * This opens the sysfs gt directory corresponding to device and tile for use
+ *
+ * Returns:
+ * The directory fd, or -1 on failure.
+ */
+int xe_sysfs_engine_open(int xe_device, int gt, int class)
+{
+ char path[96];
+
+ if (!xe_sysfs_engine_path(xe_device, gt, class, path, sizeof(path)))
+ return -1;
+
+ return open(path, O_RDONLY);
+}
+
/**
* igt_sysfs_gt_path:
* @device: fd of the device
diff --git a/lib/igt_sysfs.h b/lib/igt_sysfs.h
index f37d80ec130e..6c604d939013 100644
--- a/lib/igt_sysfs.h
+++ b/lib/igt_sysfs.h
@@ -166,4 +166,7 @@ int xe_sysfs_gt_open(int xe_device, int gt);
char *xe_sysfs_tile_path(int xe_device, int tile, char *path, int pathlen);
int xe_sysfs_tile_open(int xe_device, int tile);
int xe_sysfs_get_num_tiles(int xe_device);
+char *xe_sysfs_engine_path(int xe_device, int gt, int class, char *path, int pathlen);
+int xe_sysfs_engine_open(int xe_device, int gt, int class);
+
#endif /* __IGT_SYSFS_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 5/5] intel/xe_exec_sip: add shader sanity test
2024-06-11 10:40 [PATCH v6 0/5] lib/gpgpu: add shader support Andrzej Hajda
` (3 preceding siblings ...)
2024-06-11 10:40 ` [PATCH v6 4/5] lib/igt_sysfs: add helpers to access engine sysfs directory Andrzej Hajda
@ 2024-06-11 10:40 ` Andrzej Hajda
2024-06-11 11:12 ` Grzegorzek, Dominik
2024-06-11 12:02 ` ✗ Fi.CI.BUILD: failure for lib/gpgpu: add shader support (rev6) Patchwork
2024-06-14 12:36 ` ✗ GitLab.Pipeline: warning " Patchwork
6 siblings, 1 reply; 9+ messages in thread
From: Andrzej Hajda @ 2024-06-11 10:40 UTC (permalink / raw)
To: igt-dev
Cc: Kamil Konieczny, Dominik Grzegorzek, Christoph Manszewski,
Zbigniew Kempczyński, Gwan-gyeong Mun, Andrzej Hajda
xe_exec_sip will contain tests for shader and system routine (SIP)
interaction. Shaders (also called kernels) are programs runing on
execution units(EUs).
They can generate exceptions, which should be handled by SIP.
For starters let's implement test checking if shader runs correctly.
v2:
- use introduced helper to access sysfs attributes,
- remove redundant xe_device_get,
- use drm_close_driver
v3:
- switched to old style multiline string literals to satisfy clang
v6:
- updated test description and commit subject
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
lib/gpgpu_shader.c | 63 ++++++++++++++
lib/iga64_generated_codes.c | 83 ++++++++++++++++++-
tests/intel/xe_exec_sip.c | 197 ++++++++++++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
4 files changed, 343 insertions(+), 1 deletion(-)
diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
index 3317e9e35c91..ccc8e1974c5f 100644
--- a/lib/gpgpu_shader.c
+++ b/lib/gpgpu_shader.c
@@ -248,3 +248,66 @@ void gpgpu_shader_destroy(struct gpgpu_shader *shdr)
free(shdr->code);
free(shdr);
}
+
+/**
+ * gpgpu_shader__eot:
+ * @shdr: shader to be modified
+ *
+ * Append end of thread instruction to @shdr.
+ */
+void gpgpu_shader__eot(struct gpgpu_shader *shdr)
+{
+ emit_iga64_code(shdr, eot, " \n\
+(W) mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud \n\
+#if GEN_VER < 1250 \n\
+(W) send.ts (16|M0) null r112 null 0x10000000 0x02000010 {EOT,@1} \n\
+#else \n\
+(W) send.gtwy (8|M0) null r112 src1_null 0 0x02000000 {EOT} \n\
+#endif \n\
+ ");
+}
+
+/**
+ * gpgpu_shader__write_dword:
+ * @shdr: shader to be modified
+ * @value: dword to be written
+ * @y_offset: write target offset within the surface in rows
+ *
+ * Fill dword in (row, column/dword) == (tg_id_y + @y_offset, tg_id_x).
+ */
+void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
+ uint32_t y_offset)
+{
+ emit_iga64_code(shdr, media_block_write, " \n\
+ // Payload \n\
+(W) mov (1|M0) r5.0<1>:ud ARG(3):ud \n\
+(W) mov (1|M0) r5.1<1>:ud ARG(4):ud \n\
+(W) mov (1|M0) r5.2<1>:ud ARG(5):ud \n\
+(W) mov (1|M0) r5.3<1>:ud ARG(6):ud \n\
+#if GEN_VER < 2000 // Media Block Write \n\
+ // X offset of the block in bytes := (thread group id X << ARG(0)) \n\
+(W) shl (1|M0) r4.0<1>:ud r0.1<0;1,0>:ud ARG(0):ud \n\
+ // Y offset of the block in rows := thread group id Y \n\
+(W) mov (1|M0) r4.1<1>:ud r0.6<0;1,0>:ud \n\
+(W) add (1|M0) r4.1<1>:ud r4.1<0;1,0>:ud ARG(1):ud \n\
+ // block width [0,63] representing 1 to 64 bytes \n\
+(W) mov (1|M0) r4.2<1>:ud ARG(2):ud \n\
+ // FFTID := FFTID from R0 header \n\
+(W) mov (1|M0) r4.4<1>:ud r0.5<0;1,0>:ud \n\
+(W) send.dc1 (16|M0) null r4 src1_null 0 0x40A8000 \n\
+#else // Typed 2D Block Store \n\
+ // Load r2.0-3 with tg id X << ARG(0) \n\
+(W) shl (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud ARG(0):ud \n\
+ // Load r2.4-7 with tg id Y + ARG(1):ud \n\
+(W) mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud \n\
+(W) add (1|M0) r2.1<1>:ud r2.1<0;1,0>:ud ARG(1):ud \n\
+ // payload setup \n\
+(W) mov (16|M0) r4.0<1>:ud 0x0:ud \n\
+ // Store X and Y block start (160:191 and 192:223) \n\
+(W) mov (2|M0) r4.5<1>:ud r2.0<2;2,1>:ud \n\
+ // Store X and Y block max_size (224:231 and 232:239) \n\
+(W) mov (1|M0) r4.7<1>:ud ARG(2):ud \n\
+(W) send.tgm (16|M0) null r4 null:0 0 0x64000007 \n\
+#endif \n\
+ ", 2, y_offset, 3, value, value, value, value);
+}
diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
index 219436983585..ece7df94c793 100644
--- a/lib/iga64_generated_codes.c
+++ b/lib/iga64_generated_codes.c
@@ -3,4 +3,85 @@
#include "gpgpu_shader.h"
-#define MD5_SUM_IGA64_ASMS 68b329da9893e34099c7d8ad5cb9c940
+#define MD5_SUM_IGA64_ASMS 2c503cbfbd7b3043e9a52188ae4da7a8
+
+struct iga64_template const iga64_code_media_block_write[] = {
+ { .gen_ver = 2000, .size = 56, .code = (const uint32_t []) {
+ 0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
+ 0x80000061, 0x05154220, 0x00000000, 0xc0ded004,
+ 0x80000061, 0x05254220, 0x00000000, 0xc0ded005,
+ 0x80000061, 0x05354220, 0x00000000, 0xc0ded006,
+ 0x80000069, 0x02058220, 0x02000014, 0xc0ded000,
+ 0x80000061, 0x02150220, 0x00000064, 0x00000000,
+ 0x80001940, 0x02158220, 0x02000214, 0xc0ded001,
+ 0x80100061, 0x04054220, 0x00000000, 0x00000000,
+ 0x80041a61, 0x04550220, 0x00220205, 0x00000000,
+ 0x80000061, 0x04754220, 0x00000000, 0xc0ded002,
+ 0x80132031, 0x00000000, 0xd00e0494, 0x04000000,
+ 0x80000001, 0x00010000, 0x20000000, 0x00000000,
+ 0x80000001, 0x00010000, 0x30000000, 0x00000000,
+ 0x80000901, 0x00010000, 0x00000000, 0x00000000,
+ }},
+ { .gen_ver = 1272, .size = 52, .code = (const uint32_t []) {
+ 0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
+ 0x80000061, 0x05154220, 0x00000000, 0xc0ded004,
+ 0x80000061, 0x05254220, 0x00000000, 0xc0ded005,
+ 0x80000061, 0x05354220, 0x00000000, 0xc0ded006,
+ 0x80000069, 0x04058220, 0x02000014, 0xc0ded000,
+ 0x80000061, 0x04150220, 0x00000064, 0x00000000,
+ 0x80001940, 0x04158220, 0x02000414, 0xc0ded001,
+ 0x80000061, 0x04254220, 0x00000000, 0xc0ded002,
+ 0x80000061, 0x04450220, 0x00000054, 0x00000000,
+ 0x80132031, 0x00000000, 0xc0000414, 0x02a00000,
+ 0x80000001, 0x00010000, 0x20000000, 0x00000000,
+ 0x80000001, 0x00010000, 0x30000000, 0x00000000,
+ 0x80000901, 0x00010000, 0x00000000, 0x00000000,
+ }},
+ { .gen_ver = 1250, .size = 56, .code = (const uint32_t []) {
+ 0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
+ 0x80000061, 0x05254220, 0x00000000, 0xc0ded004,
+ 0x80000061, 0x05454220, 0x00000000, 0xc0ded005,
+ 0x80000061, 0x05654220, 0x00000000, 0xc0ded006,
+ 0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
+ 0x80000061, 0x04250220, 0x000000c4, 0x00000000,
+ 0x80001940, 0x04258220, 0x02000424, 0xc0ded001,
+ 0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
+ 0x80000061, 0x04850220, 0x000000a4, 0x00000000,
+ 0x80001901, 0x00010000, 0x00000000, 0x00000000,
+ 0x80044031, 0x00000000, 0xc0000414, 0x02a00000,
+ 0x80000001, 0x00010000, 0x20000000, 0x00000000,
+ 0x80000001, 0x00010000, 0x30000000, 0x00000000,
+ 0x80000901, 0x00010000, 0x00000000, 0x00000000,
+ }},
+ { .gen_ver = 0, .size = 52, .code = (const uint32_t []) {
+ 0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
+ 0x80000061, 0x05254220, 0x00000000, 0xc0ded004,
+ 0x80000061, 0x05454220, 0x00000000, 0xc0ded005,
+ 0x80000061, 0x05654220, 0x00000000, 0xc0ded006,
+ 0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
+ 0x80000061, 0x04250220, 0x000000c4, 0x00000000,
+ 0x80000140, 0x04258220, 0x02000424, 0xc0ded001,
+ 0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
+ 0x80000061, 0x04850220, 0x000000a4, 0x00000000,
+ 0x80049031, 0x00000000, 0xc0000414, 0x02a00000,
+ 0x80000001, 0x00010000, 0x20000000, 0x00000000,
+ 0x80000001, 0x00010000, 0x30000000, 0x00000000,
+ 0x80000101, 0x00010000, 0x00000000, 0x00000000,
+ }}
+};
+
+struct iga64_template const iga64_code_eot[] = {
+ { .gen_ver = 1272, .size = 8, .code = (const uint32_t []) {
+ 0x800c0061, 0x70050220, 0x00460005, 0x00000000,
+ 0x800f2031, 0x00000004, 0x3000700c, 0x00000000,
+ }},
+ { .gen_ver = 1250, .size = 12, .code = (const uint32_t []) {
+ 0x80030061, 0x70050220, 0x00460005, 0x00000000,
+ 0x80001901, 0x00010000, 0x00000000, 0x00000000,
+ 0x80034031, 0x00000004, 0x3000700c, 0x00000000,
+ }},
+ { .gen_ver = 0, .size = 8, .code = (const uint32_t []) {
+ 0x80030061, 0x70050220, 0x00460005, 0x00000000,
+ 0x80049031, 0x00000004, 0x7020700c, 0x10000000,
+ }}
+};
diff --git a/tests/intel/xe_exec_sip.c b/tests/intel/xe_exec_sip.c
new file mode 100644
index 000000000000..c3ee4db549ad
--- /dev/null
+++ b/tests/intel/xe_exec_sip.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+/**
+ * TEST: Tests for GPGPU shader and system routine (SIP) execution
+ * Category: Software building block
+ * Description: Exercise interaction between GPGPU shader and system routine
+ * (SIP), which should handle exceptions raised on Execution Unit.
+ * Driver requirement: xe
+ * Functionality: system routine
+ * Mega feature: Compute
+ * Sub-category: GPGPU tests
+ * Test category: functionality test
+ */
+
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+
+#include "gpgpu_shader.h"
+#include "igt.h"
+#include "igt_sysfs.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define WIDTH 64
+#define HEIGHT 64
+
+#define COLOR_C4 0xc4
+
+#define SHADER_CANARY 0x01010101
+
+#define NSEC_PER_MSEC (1000 * 1000ull)
+
+static struct intel_buf *
+create_fill_buf(int fd, int width, int height, uint8_t color)
+{
+ struct intel_buf *buf;
+ uint8_t *ptr;
+
+ buf = calloc(1, sizeof(*buf));
+ igt_assert(buf);
+
+ intel_buf_init(buf_ops_create(fd), buf, width / 4, height, 32, 0,
+ I915_TILING_NONE, 0);
+
+ ptr = xe_bo_map(fd, buf->handle, buf->surface[0].size);
+ memset(ptr, color, buf->surface[0].size);
+ munmap(ptr, buf->surface[0].size);
+
+ return buf;
+}
+
+static struct gpgpu_shader *get_shader(int fd)
+{
+ static struct gpgpu_shader *shader;
+
+ shader = gpgpu_shader_create(fd);
+ gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
+ gpgpu_shader__eot(shader);
+ return shader;
+}
+
+static uint32_t gpgpu_shader(int fd, struct intel_bb *ibb, unsigned int threads,
+ unsigned int width, unsigned int height)
+{
+ struct intel_buf *buf = create_fill_buf(fd, width, height, COLOR_C4);
+ struct gpgpu_shader *shader = get_shader(fd);
+
+ gpgpu_shader_exec(ibb, buf, 1, threads, shader, NULL, 0, 0);
+ gpgpu_shader_destroy(shader);
+ return buf->handle;
+}
+
+static void check_fill_buf(uint8_t *ptr, const int width, const int x,
+ const int y, const uint8_t color)
+{
+ const uint8_t val = ptr[y * width + x];
+
+ igt_assert_f(val == color,
+ "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
+ color, val, x, y);
+}
+
+static void check_buf(int fd, uint32_t handle, int width, int height,
+ uint8_t poison_c)
+{
+ unsigned int sz = ALIGN(width * height, 4096);
+ int thread_count = 0;
+ uint32_t *ptr;
+ int i, j;
+
+ ptr = xe_bo_mmap_ext(fd, handle, sz, PROT_READ);
+
+ for (i = 0, j = 0; j < height / 2; ++j) {
+ if (ptr[j * width / 4] == SHADER_CANARY) {
+ ++thread_count;
+ i = 4;
+ }
+
+ for (; i < width; i++)
+ check_fill_buf((uint8_t *)ptr, width, i, j, poison_c);
+
+ i = 0;
+ }
+
+ igt_assert(thread_count);
+
+ munmap(ptr, sz);
+}
+
+static uint64_t
+xe_sysfs_get_job_timeout_ms(int fd, struct drm_xe_engine_class_instance *eci)
+{
+ int engine_fd = -1;
+ uint64_t ret;
+
+ engine_fd = xe_sysfs_engine_open(fd, eci->gt_id, eci->engine_class);
+ ret = igt_sysfs_get_u64(engine_fd, "job_timeout_ms");
+ close(engine_fd);
+
+ return ret;
+}
+
+/**
+ * SUBTEST: sanity
+ * Description: check basic shader with write operation
+ * Run type: BAT
+ *
+ */
+static void test_sip(struct drm_xe_engine_class_instance *eci, uint32_t flags)
+{
+ unsigned int threads = 512;
+ unsigned int height = max_t(threads, HEIGHT, threads * 2);
+ uint32_t exec_queue_id, handle, vm_id;
+ unsigned int width = WIDTH;
+ struct timespec ts = { };
+ uint64_t timeout;
+ struct intel_bb *ibb;
+ int fd;
+
+ igt_debug("Using %s\n", xe_engine_class_string(eci->engine_class));
+
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+
+ vm_id = xe_vm_create(fd, 0, 0);
+
+ /* Get timeout for job, and add 4s to ensure timeout processes in subtest. */
+ timeout = xe_sysfs_get_job_timeout_ms(fd, eci) + 4ull * MSEC_PER_SEC;
+ timeout *= NSEC_PER_MSEC;
+ timeout *= igt_run_in_simulation() ? 10 : 1;
+
+ exec_queue_id = xe_exec_queue_create(fd, vm_id, eci, 0);
+ ibb = intel_bb_create_with_context(fd, exec_queue_id, vm_id, NULL, 4096);
+
+ igt_nsec_elapsed(&ts);
+ handle = gpgpu_shader(fd, ibb, threads, width, height);
+
+ intel_bb_sync(ibb);
+ igt_assert_lt_u64(igt_nsec_elapsed(&ts), timeout);
+
+ check_buf(fd, handle, width, height, COLOR_C4);
+
+ gem_close(fd, handle);
+ intel_bb_destroy(ibb);
+
+ xe_exec_queue_destroy(fd, exec_queue_id);
+ xe_vm_destroy(fd, vm_id);
+ xe_device_put(fd);
+ close(fd);
+}
+
+#define test_render_and_compute(t, __fd, __eci) \
+ igt_subtest_with_dynamic(t) \
+ xe_for_each_engine(__fd, __eci) \
+ if (__eci->engine_class == DRM_XE_ENGINE_CLASS_RENDER || \
+ __eci->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) \
+ igt_dynamic_f("%s%d", xe_engine_class_string(__eci->engine_class), \
+ __eci->engine_instance)
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *eci;
+ int fd;
+
+ igt_fixture
+ fd = drm_open_driver(DRIVER_XE);
+
+ test_render_and_compute("sanity", fd, eci)
+ test_sip(eci, 0);
+
+ igt_fixture
+ drm_close_driver(fd);
+}
diff --git a/tests/meson.build b/tests/meson.build
index 758ae090c927..021421cfe92b 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -292,6 +292,7 @@ intel_xe_progs = [
'xe_exec_fault_mode',
'xe_exec_queue_property',
'xe_exec_reset',
+ 'xe_exec_sip',
'xe_exec_store',
'xe_exec_threads',
'xe_exercise_blt',
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v6 5/5] intel/xe_exec_sip: add shader sanity test
2024-06-11 10:40 ` [PATCH v6 5/5] intel/xe_exec_sip: add shader sanity test Andrzej Hajda
@ 2024-06-11 11:12 ` Grzegorzek, Dominik
0 siblings, 0 replies; 9+ messages in thread
From: Grzegorzek, Dominik @ 2024-06-11 11:12 UTC (permalink / raw)
To: igt-dev@lists.freedesktop.org, Hajda, Andrzej
Cc: Kempczynski, Zbigniew, Mun, Gwan-gyeong, Manszewski, Christoph,
kamil.konieczny@linux.intel.com
On Tue, 2024-06-11 at 12:40 +0200, Andrzej Hajda wrote:
> xe_exec_sip will contain tests for shader and system routine (SIP)
> interaction. Shaders (also called kernels) are programs runing on
> execution units(EUs).
> They can generate exceptions, which should be handled by SIP.
> For starters let's implement test checking if shader runs correctly.
>
> v2:
> - use introduced helper to access sysfs attributes,
> - remove redundant xe_device_get,
> - use drm_close_driver
> v3:
> - switched to old style multiline string literals to satisfy clang
> v6:
> - updated test description and commit subject
>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Haven't spotted anything suspicious, it is:
Reviewed-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> ---
> lib/gpgpu_shader.c | 63 ++++++++++++++
> lib/iga64_generated_codes.c | 83 ++++++++++++++++++-
> tests/intel/xe_exec_sip.c | 197 ++++++++++++++++++++++++++++++++++++++++++++
> tests/meson.build | 1 +
> 4 files changed, 343 insertions(+), 1 deletion(-)
>
> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
> index 3317e9e35c91..ccc8e1974c5f 100644
> --- a/lib/gpgpu_shader.c
> +++ b/lib/gpgpu_shader.c
> @@ -248,3 +248,66 @@ void gpgpu_shader_destroy(struct gpgpu_shader *shdr)
> free(shdr->code);
> free(shdr);
> }
> +
> +/**
> + * gpgpu_shader__eot:
> + * @shdr: shader to be modified
> + *
> + * Append end of thread instruction to @shdr.
> + */
> +void gpgpu_shader__eot(struct gpgpu_shader *shdr)
> +{
> + emit_iga64_code(shdr, eot, " \n\
> +(W) mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud \n\
> +#if GEN_VER < 1250 \n\
> +(W) send.ts (16|M0) null r112 null 0x10000000 0x02000010 {EOT,@1} \n\
> +#else \n\
> +(W) send.gtwy (8|M0) null r112 src1_null 0 0x02000000 {EOT} \n\
> +#endif \n\
> + ");
> +}
> +
> +/**
> + * gpgpu_shader__write_dword:
> + * @shdr: shader to be modified
> + * @value: dword to be written
> + * @y_offset: write target offset within the surface in rows
> + *
> + * Fill dword in (row, column/dword) == (tg_id_y + @y_offset, tg_id_x).
> + */
> +void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
> + uint32_t y_offset)
> +{
> + emit_iga64_code(shdr, media_block_write, " \n\
> + // Payload \n\
> +(W) mov (1|M0) r5.0<1>:ud ARG(3):ud \n\
> +(W) mov (1|M0) r5.1<1>:ud ARG(4):ud \n\
> +(W) mov (1|M0) r5.2<1>:ud ARG(5):ud \n\
> +(W) mov (1|M0) r5.3<1>:ud ARG(6):ud \n\
> +#if GEN_VER < 2000 // Media Block Write \n\
> + // X offset of the block in bytes := (thread group id X << ARG(0)) \n\
> +(W) shl (1|M0) r4.0<1>:ud r0.1<0;1,0>:ud ARG(0):ud \n\
> + // Y offset of the block in rows := thread group id Y \n\
> +(W) mov (1|M0) r4.1<1>:ud r0.6<0;1,0>:ud \n\
> +(W) add (1|M0) r4.1<1>:ud r4.1<0;1,0>:ud ARG(1):ud \n\
> + // block width [0,63] representing 1 to 64 bytes \n\
> +(W) mov (1|M0) r4.2<1>:ud ARG(2):ud \n\
> + // FFTID := FFTID from R0 header \n\
> +(W) mov (1|M0) r4.4<1>:ud r0.5<0;1,0>:ud \n\
> +(W) send.dc1 (16|M0) null r4 src1_null 0 0x40A8000 \n\
> +#else // Typed 2D Block Store \n\
> + // Load r2.0-3 with tg id X << ARG(0) \n\
> +(W) shl (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud ARG(0):ud \n\
> + // Load r2.4-7 with tg id Y + ARG(1):ud \n\
> +(W) mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud \n\
> +(W) add (1|M0) r2.1<1>:ud r2.1<0;1,0>:ud ARG(1):ud \n\
> + // payload setup \n\
> +(W) mov (16|M0) r4.0<1>:ud 0x0:ud \n\
> + // Store X and Y block start (160:191 and 192:223) \n\
> +(W) mov (2|M0) r4.5<1>:ud r2.0<2;2,1>:ud \n\
> + // Store X and Y block max_size (224:231 and 232:239) \n\
> +(W) mov (1|M0) r4.7<1>:ud ARG(2):ud \n\
> +(W) send.tgm (16|M0) null r4 null:0 0 0x64000007 \n\
> +#endif \n\
> + ", 2, y_offset, 3, value, value, value, value);
> +}
> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
> index 219436983585..ece7df94c793 100644
> --- a/lib/iga64_generated_codes.c
> +++ b/lib/iga64_generated_codes.c
> @@ -3,4 +3,85 @@
>
> #include "gpgpu_shader.h"
>
> -#define MD5_SUM_IGA64_ASMS 68b329da9893e34099c7d8ad5cb9c940
> +#define MD5_SUM_IGA64_ASMS 2c503cbfbd7b3043e9a52188ae4da7a8
> +
> +struct iga64_template const iga64_code_media_block_write[] = {
> + { .gen_ver = 2000, .size = 56, .code = (const uint32_t []) {
> + 0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
> + 0x80000061, 0x05154220, 0x00000000, 0xc0ded004,
> + 0x80000061, 0x05254220, 0x00000000, 0xc0ded005,
> + 0x80000061, 0x05354220, 0x00000000, 0xc0ded006,
> + 0x80000069, 0x02058220, 0x02000014, 0xc0ded000,
> + 0x80000061, 0x02150220, 0x00000064, 0x00000000,
> + 0x80001940, 0x02158220, 0x02000214, 0xc0ded001,
> + 0x80100061, 0x04054220, 0x00000000, 0x00000000,
> + 0x80041a61, 0x04550220, 0x00220205, 0x00000000,
> + 0x80000061, 0x04754220, 0x00000000, 0xc0ded002,
> + 0x80132031, 0x00000000, 0xd00e0494, 0x04000000,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 1272, .size = 52, .code = (const uint32_t []) {
> + 0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
> + 0x80000061, 0x05154220, 0x00000000, 0xc0ded004,
> + 0x80000061, 0x05254220, 0x00000000, 0xc0ded005,
> + 0x80000061, 0x05354220, 0x00000000, 0xc0ded006,
> + 0x80000069, 0x04058220, 0x02000014, 0xc0ded000,
> + 0x80000061, 0x04150220, 0x00000064, 0x00000000,
> + 0x80001940, 0x04158220, 0x02000414, 0xc0ded001,
> + 0x80000061, 0x04254220, 0x00000000, 0xc0ded002,
> + 0x80000061, 0x04450220, 0x00000054, 0x00000000,
> + 0x80132031, 0x00000000, 0xc0000414, 0x02a00000,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 1250, .size = 56, .code = (const uint32_t []) {
> + 0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
> + 0x80000061, 0x05254220, 0x00000000, 0xc0ded004,
> + 0x80000061, 0x05454220, 0x00000000, 0xc0ded005,
> + 0x80000061, 0x05654220, 0x00000000, 0xc0ded006,
> + 0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
> + 0x80000061, 0x04250220, 0x000000c4, 0x00000000,
> + 0x80001940, 0x04258220, 0x02000424, 0xc0ded001,
> + 0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
> + 0x80000061, 0x04850220, 0x000000a4, 0x00000000,
> + 0x80001901, 0x00010000, 0x00000000, 0x00000000,
> + 0x80044031, 0x00000000, 0xc0000414, 0x02a00000,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 0, .size = 52, .code = (const uint32_t []) {
> + 0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
> + 0x80000061, 0x05254220, 0x00000000, 0xc0ded004,
> + 0x80000061, 0x05454220, 0x00000000, 0xc0ded005,
> + 0x80000061, 0x05654220, 0x00000000, 0xc0ded006,
> + 0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
> + 0x80000061, 0x04250220, 0x000000c4, 0x00000000,
> + 0x80000140, 0x04258220, 0x02000424, 0xc0ded001,
> + 0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
> + 0x80000061, 0x04850220, 0x000000a4, 0x00000000,
> + 0x80049031, 0x00000000, 0xc0000414, 0x02a00000,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000101, 0x00010000, 0x00000000, 0x00000000,
> + }}
> +};
> +
> +struct iga64_template const iga64_code_eot[] = {
> + { .gen_ver = 1272, .size = 8, .code = (const uint32_t []) {
> + 0x800c0061, 0x70050220, 0x00460005, 0x00000000,
> + 0x800f2031, 0x00000004, 0x3000700c, 0x00000000,
> + }},
> + { .gen_ver = 1250, .size = 12, .code = (const uint32_t []) {
> + 0x80030061, 0x70050220, 0x00460005, 0x00000000,
> + 0x80001901, 0x00010000, 0x00000000, 0x00000000,
> + 0x80034031, 0x00000004, 0x3000700c, 0x00000000,
> + }},
> + { .gen_ver = 0, .size = 8, .code = (const uint32_t []) {
> + 0x80030061, 0x70050220, 0x00460005, 0x00000000,
> + 0x80049031, 0x00000004, 0x7020700c, 0x10000000,
> + }}
> +};
> diff --git a/tests/intel/xe_exec_sip.c b/tests/intel/xe_exec_sip.c
> new file mode 100644
> index 000000000000..c3ee4db549ad
> --- /dev/null
> +++ b/tests/intel/xe_exec_sip.c
> @@ -0,0 +1,197 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +/**
> + * TEST: Tests for GPGPU shader and system routine (SIP) execution
> + * Category: Software building block
> + * Description: Exercise interaction between GPGPU shader and system routine
> + * (SIP), which should handle exceptions raised on Execution Unit.
> + * Driver requirement: xe
> + * Functionality: system routine
> + * Mega feature: Compute
> + * Sub-category: GPGPU tests
> + * Test category: functionality test
> + */
> +
> +#include <dirent.h>
> +#include <fcntl.h>
> +#include <stdio.h>
> +
> +#include "gpgpu_shader.h"
> +#include "igt.h"
> +#include "igt_sysfs.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define WIDTH 64
> +#define HEIGHT 64
> +
> +#define COLOR_C4 0xc4
> +
> +#define SHADER_CANARY 0x01010101
> +
> +#define NSEC_PER_MSEC (1000 * 1000ull)
> +
> +static struct intel_buf *
> +create_fill_buf(int fd, int width, int height, uint8_t color)
> +{
> + struct intel_buf *buf;
> + uint8_t *ptr;
> +
> + buf = calloc(1, sizeof(*buf));
> + igt_assert(buf);
> +
> + intel_buf_init(buf_ops_create(fd), buf, width / 4, height, 32, 0,
> + I915_TILING_NONE, 0);
> +
> + ptr = xe_bo_map(fd, buf->handle, buf->surface[0].size);
> + memset(ptr, color, buf->surface[0].size);
> + munmap(ptr, buf->surface[0].size);
> +
> + return buf;
> +}
> +
> +static struct gpgpu_shader *get_shader(int fd)
> +{
> + static struct gpgpu_shader *shader;
> +
> + shader = gpgpu_shader_create(fd);
> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
> + gpgpu_shader__eot(shader);
> + return shader;
> +}
> +
> +static uint32_t gpgpu_shader(int fd, struct intel_bb *ibb, unsigned int threads,
> + unsigned int width, unsigned int height)
> +{
> + struct intel_buf *buf = create_fill_buf(fd, width, height, COLOR_C4);
> + struct gpgpu_shader *shader = get_shader(fd);
> +
> + gpgpu_shader_exec(ibb, buf, 1, threads, shader, NULL, 0, 0);
> + gpgpu_shader_destroy(shader);
> + return buf->handle;
> +}
> +
> +static void check_fill_buf(uint8_t *ptr, const int width, const int x,
> + const int y, const uint8_t color)
> +{
> + const uint8_t val = ptr[y * width + x];
> +
> + igt_assert_f(val == color,
> + "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
> + color, val, x, y);
> +}
> +
> +static void check_buf(int fd, uint32_t handle, int width, int height,
> + uint8_t poison_c)
> +{
> + unsigned int sz = ALIGN(width * height, 4096);
> + int thread_count = 0;
> + uint32_t *ptr;
> + int i, j;
> +
> + ptr = xe_bo_mmap_ext(fd, handle, sz, PROT_READ);
> +
> + for (i = 0, j = 0; j < height / 2; ++j) {
> + if (ptr[j * width / 4] == SHADER_CANARY) {
> + ++thread_count;
> + i = 4;
> + }
> +
> + for (; i < width; i++)
> + check_fill_buf((uint8_t *)ptr, width, i, j, poison_c);
> +
> + i = 0;
> + }
> +
> + igt_assert(thread_count);
> +
> + munmap(ptr, sz);
> +}
> +
> +static uint64_t
> +xe_sysfs_get_job_timeout_ms(int fd, struct drm_xe_engine_class_instance *eci)
> +{
> + int engine_fd = -1;
> + uint64_t ret;
> +
> + engine_fd = xe_sysfs_engine_open(fd, eci->gt_id, eci->engine_class);
> + ret = igt_sysfs_get_u64(engine_fd, "job_timeout_ms");
> + close(engine_fd);
> +
> + return ret;
> +}
> +
> +/**
> + * SUBTEST: sanity
> + * Description: check basic shader with write operation
> + * Run type: BAT
> + *
> + */
> +static void test_sip(struct drm_xe_engine_class_instance *eci, uint32_t flags)
> +{
> + unsigned int threads = 512;
> + unsigned int height = max_t(threads, HEIGHT, threads * 2);
> + uint32_t exec_queue_id, handle, vm_id;
> + unsigned int width = WIDTH;
> + struct timespec ts = { };
> + uint64_t timeout;
> + struct intel_bb *ibb;
> + int fd;
> +
> + igt_debug("Using %s\n", xe_engine_class_string(eci->engine_class));
> +
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> +
> + vm_id = xe_vm_create(fd, 0, 0);
> +
> + /* Get timeout for job, and add 4s to ensure timeout processes in subtest. */
> + timeout = xe_sysfs_get_job_timeout_ms(fd, eci) + 4ull * MSEC_PER_SEC;
> + timeout *= NSEC_PER_MSEC;
> + timeout *= igt_run_in_simulation() ? 10 : 1;
> +
> + exec_queue_id = xe_exec_queue_create(fd, vm_id, eci, 0);
> + ibb = intel_bb_create_with_context(fd, exec_queue_id, vm_id, NULL, 4096);
> +
> + igt_nsec_elapsed(&ts);
> + handle = gpgpu_shader(fd, ibb, threads, width, height);
> +
> + intel_bb_sync(ibb);
> + igt_assert_lt_u64(igt_nsec_elapsed(&ts), timeout);
> +
> + check_buf(fd, handle, width, height, COLOR_C4);
> +
> + gem_close(fd, handle);
> + intel_bb_destroy(ibb);
> +
> + xe_exec_queue_destroy(fd, exec_queue_id);
> + xe_vm_destroy(fd, vm_id);
> + xe_device_put(fd);
> + close(fd);
> +}
> +
> +#define test_render_and_compute(t, __fd, __eci) \
> + igt_subtest_with_dynamic(t) \
> + xe_for_each_engine(__fd, __eci) \
> + if (__eci->engine_class == DRM_XE_ENGINE_CLASS_RENDER || \
> + __eci->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) \
> + igt_dynamic_f("%s%d", xe_engine_class_string(__eci->engine_class), \
> + __eci->engine_instance)
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *eci;
> + int fd;
> +
> + igt_fixture
> + fd = drm_open_driver(DRIVER_XE);
> +
> + test_render_and_compute("sanity", fd, eci)
> + test_sip(eci, 0);
> +
> + igt_fixture
> + drm_close_driver(fd);
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index 758ae090c927..021421cfe92b 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -292,6 +292,7 @@ intel_xe_progs = [
> 'xe_exec_fault_mode',
> 'xe_exec_queue_property',
> 'xe_exec_reset',
> + 'xe_exec_sip',
> 'xe_exec_store',
> 'xe_exec_threads',
> 'xe_exercise_blt',
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Fi.CI.BUILD: failure for lib/gpgpu: add shader support (rev6)
2024-06-11 10:40 [PATCH v6 0/5] lib/gpgpu: add shader support Andrzej Hajda
` (4 preceding siblings ...)
2024-06-11 10:40 ` [PATCH v6 5/5] intel/xe_exec_sip: add shader sanity test Andrzej Hajda
@ 2024-06-11 12:02 ` Patchwork
2024-06-14 12:36 ` ✗ GitLab.Pipeline: warning " Patchwork
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2024-06-11 12:02 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: igt-dev
== Series Details ==
Series: lib/gpgpu: add shader support (rev6)
URL : https://patchwork.freedesktop.org/series/133020/
State : failure
== Summary ==
IGT patchset build failed on latest successful build
d3d49beb5bbf027618a278d0633ec5182e30c712 tests/intel/xe_create: Don't assert on presi execution
Tail of build.log:
[1643/1687] Generating gem_stress.testlist with a meson_exe.py custom command.
[1644/1687] Linking target tools/intel_reg_checker.
[1645/1687] Linking target tools/intel_gem_info.
[1646/1687] Linking target tools/intel_pm_rpm.
[1647/1687] Linking target runner/testdata/abort-dynamic.
[1648/1687] Linking target runner/testdata/dynamic.
[1649/1687] Linking target tools/intel_reg.
[1650/1687] Linking target tools/intel_perf_counters.
[1651/1687] Linking target tools/intel_vbt_decode.
[1652/1687] Linking target runner/igt_comms_decoder.
[1653/1687] Linking target runner/testdata/skippers.
[1654/1687] Linking target tools/lsgpu.
[1655/1687] Linking target tools/intel_dp_compliance.
[1656/1687] Linking target runner/runner_json_test.
[1657/1687] Linking target tools/intel_l3_parity.
[1658/1687] Linking target tools/msm_dp_compliance.
[1659/1687] Linking target runner/testdata/abort.
[1660/1687] Linking target runner/igt_runner.
[1661/1687] Linking target runner/testdata/abort-simple.
[1662/1687] Linking target runner/testdata/abort-fixture.
[1663/1687] Linking target runner/igt_results.
[1664/1687] Linking target runner/igt_resume.
[1665/1687] Compiling C object 'runner/527aa9f@@runner_test@exe/runner_tests.c.o'.
[1666/1687] Linking target runner/runner_test.
[1667/1687] Compiling C object 'lib/76b5a35@@i915_perf@sha/meson-generated_.._i915_perf_metrics_acmgt2.c.o'.
[1668/1687] Compiling C object 'lib/76b5a35@@i915_perf@sha/meson-generated_.._i915_perf_metrics_acmgt3.c.o'.
[1669/1687] Linking target lib/libi915_perf.so.1.5.
[1670/1687] Generating symbol file 'lib/76b5a35@@i915_perf@sha/libi915_perf.so.1.5.symbols'.
[1671/1687] Linking target tools/i915-perf/i915-perf-configs.
[1672/1687] Linking target tools/i915-perf/i915-perf-recorder.
[1673/1687] Linking target tools/i915-perf/i915-perf-reader.
[1674/1687] Linking target tests/gem_barrier_race.
[1675/1687] Linking target tests/core_hotunplug.
[1676/1687] Linking target tests/perf.
[1677/1687] Generating perf.testlist with a meson_exe.py custom command.
[1678/1687] Generating core_hotunplug.testlist with a meson_exe.py custom command.
[1679/1687] Generating gem_barrier_race.testlist with a meson_exe.py custom command.
[1680/1687] Generating xe_tests.rst with a custom command.
FAILED: docs/testplan/xe_tests.rst
/usr/src/igt-gpu-tools/scripts/igt_doc.py --config /usr/src/igt-gpu-tools/tests/intel/xe_test_config.json --rest docs/testplan/xe_tests.rst --check-testlist --igt-build-path /opt/igt/build
/usr/src/igt-gpu-tools/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /usr/src/igt-gpu-tools/tests/intel/xe_test_config.json?
==> Driver requirement: xe
[1681/1687] Generating intel-ci-tests with a custom command.
FAILED: docs/testplan/intel-ci-tests
/usr/src/igt-gpu-tools/scripts/igt_doc.py --config /usr/src/igt-gpu-tools/tests/intel/i915_test_config.json /usr/src/igt-gpu-tools/tests/intel/kms_test_config.json /usr/src/igt-gpu-tools/tests/intel/xe_test_config.json --intelci-testlist docs/testplan/intel-ci-tests
/usr/src/igt-gpu-tools/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /usr/src/igt-gpu-tools/tests/intel/xe_test_config.json?
==> Driver requirement: xe
[1682/1687] Generating i915_tests.rst with a custom command.
[1683/1687] Generating kms_tests.rst with a custom command.
ninja: build stopped: subcommand failed.
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ GitLab.Pipeline: warning for lib/gpgpu: add shader support (rev6)
2024-06-11 10:40 [PATCH v6 0/5] lib/gpgpu: add shader support Andrzej Hajda
` (5 preceding siblings ...)
2024-06-11 12:02 ` ✗ Fi.CI.BUILD: failure for lib/gpgpu: add shader support (rev6) Patchwork
@ 2024-06-14 12:36 ` Patchwork
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2024-06-14 12:36 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: igt-dev
== Series Details ==
Series: lib/gpgpu: add shader support (rev6)
URL : https://patchwork.freedesktop.org/series/133020/
State : warning
== Summary ==
Pipeline status: FAILED.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/1198675 for the overview.
build:tests-debian-meson has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/59747460):
[1802/1809] Generating i915_tests.rst with a custom command.
[1803/1809] Generating kms_tests.rst with a custom command.
[1804/1809] Compiling C object 'runner/527aa9f@@runner_test@exe/runner_tests.c.o'.
ninja: build stopped: subcommand failed.
ninja: Entering directory `build'
[1/828] Generating version.h with a custom command.
[2/8] Linking target runner/runner_test.
[3/8] Linking target assembler/intel-gen4asm.
[4/8] Generating xe_tests.rst with a custom command.
FAILED: docs/testplan/xe_tests.rst
/builds/gfx-ci/igt-ci-tags/scripts/igt_doc.py --config /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json --rest docs/testplan/xe_tests.rst --check-testlist --igt-build-path /builds/gfx-ci/igt-ci-tags/build
/builds/gfx-ci/igt-ci-tags/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json?
==> Driver requirement: xe
ninja: build stopped: subcommand failed.
section_end:1718107445:step_script
section_start:1718107445:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1718107446:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-debian-meson-arm64 has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/59747464):
[3/13] Linking target runner/igt_runner.
[4/13] Linking target runner/igt_results.
[5/13] Linking target runner/igt_resume.
[6/13] Linking target runner/igt_comms_decoder.
[7/13] Linking target runner/runner_test.
[8/13] Linking target runner/runner_json_test.
[9/13] Generating i915_tests.html with a custom command.
[10/13] Generating kms_tests.html with a custom command.
[11/13] Generating xe_tests.rst with a custom command.
FAILED: docs/testplan/xe_tests.rst
/builds/gfx-ci/igt-ci-tags/scripts/igt_doc.py --config /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json --rest docs/testplan/xe_tests.rst
/builds/gfx-ci/igt-ci-tags/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json?
==> Driver requirement: xe
ninja: build stopped: subcommand failed.
section_end:1718107432:step_script
section_start:1718107432:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1718107432:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-debian-meson-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/59747463):
[3/13] Linking target runner/igt_runner.
[4/13] Linking target runner/igt_results.
[5/13] Linking target runner/igt_resume.
[6/13] Linking target runner/igt_comms_decoder.
[7/13] Linking target runner/runner_test.
[8/13] Linking target runner/runner_json_test.
[9/13] Generating i915_tests.html with a custom command.
[10/13] Generating kms_tests.html with a custom command.
[11/13] Generating xe_tests.rst with a custom command.
FAILED: docs/testplan/xe_tests.rst
/builds/gfx-ci/igt-ci-tags/scripts/igt_doc.py --config /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json --rest docs/testplan/xe_tests.rst
/builds/gfx-ci/igt-ci-tags/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json?
==> Driver requirement: xe
ninja: build stopped: subcommand failed.
section_end:1718107448:step_script
section_start:1718107448:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1718107449:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-debian-meson-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/59747466):
[3/13] Linking target runner/igt_runner.
[4/13] Linking target runner/igt_resume.
[5/13] Linking target runner/igt_results.
[6/13] Linking target runner/igt_comms_decoder.
[7/13] Linking target runner/runner_test.
[8/13] Linking target runner/runner_json_test.
[9/13] Generating i915_tests.html with a custom command.
[10/13] Generating kms_tests.html with a custom command.
[11/13] Generating xe_tests.rst with a custom command.
FAILED: docs/testplan/xe_tests.rst
/builds/gfx-ci/igt-ci-tags/scripts/igt_doc.py --config /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json --rest docs/testplan/xe_tests.rst
/builds/gfx-ci/igt-ci-tags/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json?
==> Driver requirement: xe
ninja: build stopped: subcommand failed.
section_end:1718107454:step_script
section_start:1718107454:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1718107454:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-debian-minimal has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/59747462):
ninja: Entering directory `build'
[1/107] Generating version.h with a custom command.
[2/9] Linking target lib/libi915_perf.so.1.5.
[3/9] Generating symbol file 'lib/76b5a35@@i915_perf@sha/libi915_perf.so.1.5.symbols'.
[4/9] Linking target tools/intel_gpu_top.
[5/9] Linking target tools/i915-perf/i915-perf-configs.
[6/9] Linking target tools/i915-perf/i915-perf-recorder.
[7/9] Linking target tools/i915-perf/i915-perf-reader.
[8/9] Generating xe_tests.rst with a custom command.
FAILED: docs/testplan/xe_tests.rst
/builds/gfx-ci/igt-ci-tags/scripts/igt_doc.py --config /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json --rest docs/testplan/xe_tests.rst
/builds/gfx-ci/igt-ci-tags/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json?
==> Driver requirement: xe
ninja: build stopped: subcommand failed.
section_end:1718107417:step_script
section_start:1718107417:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1718107417:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-fedora has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/59747453):
==> Driver requirement: xe
[1809/1815] Generating i915_tests.rst with a custom command.
[1810/1815] Generating kms_tests.rst with a custom command.
[1811/1815] Compiling C object 'runner/527aa9f@@runner_test@exe/runner_tests.c.o'.
ninja: build stopped: subcommand failed.
ninja: Entering directory `build'
[1/830] Generating version.h with a custom command.
[2/7] Linking target runner/runner_test.
[3/7] Generating intel-ci-tests with a custom command.
FAILED: docs/testplan/intel-ci-tests
/builds/gfx-ci/igt-ci-tags/scripts/igt_doc.py --config /builds/gfx-ci/igt-ci-tags/tests/intel/i915_test_config.json /builds/gfx-ci/igt-ci-tags/tests/intel/kms_test_config.json /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json --intelci-testlist docs/testplan/intel-ci-tests
/builds/gfx-ci/igt-ci-tags/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json?
==> Driver requirement: xe
ninja: build stopped: subcommand failed.
section_end:1718107426:step_script
section_start:1718107426:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1718107428:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-fedora-clang has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/59747459):
==> Driver requirement: xe
[1811/1815] Generating i915_tests.rst with a custom command.
[1812/1815] Generating kms_tests.rst with a custom command.
ninja: build stopped: subcommand failed.
ninja: Entering directory `build'
[1/830] Generating version.h with a custom command.
[2/6] Generating kms_tests.html with a custom command.
[3/6] Generating i915_tests.html with a custom command.
[4/6] Generating intel-ci-tests with a custom command.
FAILED: docs/testplan/intel-ci-tests
/builds/gfx-ci/igt-ci-tags/scripts/igt_doc.py --config /builds/gfx-ci/igt-ci-tags/tests/intel/i915_test_config.json /builds/gfx-ci/igt-ci-tags/tests/intel/kms_test_config.json /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json --intelci-testlist docs/testplan/intel-ci-tests
/builds/gfx-ci/igt-ci-tags/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json?
==> Driver requirement: xe
ninja: build stopped: subcommand failed.
section_end:1718107474:step_script
section_start:1718107474:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1718107474:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-fedora-no-libdrm-nouveau has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/59747457):
==> Driver requirement: xe
[1641/1647] Generating i915_tests.rst with a custom command.
[1642/1647] Generating kms_tests.rst with a custom command.
[1643/1647] Compiling C object 'runner/527aa9f@@runner_test@exe/runner_tests.c.o'.
ninja: build stopped: subcommand failed.
ninja: Entering directory `build'
[1/779] Generating version.h with a custom command.
[2/7] Linking target runner/runner_test.
[3/7] Generating intel-ci-tests with a custom command.
FAILED: docs/testplan/intel-ci-tests
/builds/gfx-ci/igt-ci-tags/scripts/igt_doc.py --config /builds/gfx-ci/igt-ci-tags/tests/intel/i915_test_config.json /builds/gfx-ci/igt-ci-tags/tests/intel/kms_test_config.json /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json --intelci-testlist docs/testplan/intel-ci-tests
/builds/gfx-ci/igt-ci-tags/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json?
==> Driver requirement: xe
ninja: build stopped: subcommand failed.
section_end:1718107427:step_script
section_start:1718107427:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1718107428:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-fedora-no-libunwind has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/59747454):
==> Driver requirement: xe
[1809/1815] Generating i915_tests.rst with a custom command.
[1810/1815] Generating kms_tests.rst with a custom command.
[1811/1815] Compiling C object 'runner/527aa9f@@runner_test@exe/runner_tests.c.o'.
ninja: build stopped: subcommand failed.
ninja: Entering directory `build'
[1/830] Generating version.h with a custom command.
[2/7] Linking target runner/runner_test.
[3/7] Generating intel-ci-tests with a custom command.
FAILED: docs/testplan/intel-ci-tests
/builds/gfx-ci/igt-ci-tags/scripts/igt_doc.py --config /builds/gfx-ci/igt-ci-tags/tests/intel/i915_test_config.json /builds/gfx-ci/igt-ci-tags/tests/intel/kms_test_config.json /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json --intelci-testlist docs/testplan/intel-ci-tests
/builds/gfx-ci/igt-ci-tags/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json?
==> Driver requirement: xe
ninja: build stopped: subcommand failed.
section_end:1718107429:step_script
section_start:1718107429:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1718107431:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-fedora-oldest-meson has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/59747456):
[1810/1815] Generating kms_tests.rst with a custom command.
[1811/1815] Compiling C object 'runner/runner@@runner_test@exe/runner_tests.c.o'.
ninja: build stopped: subcommand failed.
ninja: Entering directory `build'
[1/830] Generating version.h with a custom command.
[2/7] Linking target runner/runner_test.
[3/7] Generating kms_tests.html with a custom command.
[4/7] Generating i915_tests.html with a custom command.
[5/7] Generating intel-ci-tests with a custom command.
FAILED: docs/testplan/intel-ci-tests
/builds/gfx-ci/igt-ci-tags/scripts/igt_doc.py --config /builds/gfx-ci/igt-ci-tags/tests/intel/i915_test_config.json /builds/gfx-ci/igt-ci-tags/tests/intel/kms_test_config.json /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json --intelci-testlist docs/testplan/intel-ci-tests
/builds/gfx-ci/igt-ci-tags/tests/intel/xe_exec_sip.c:11: Error: unrecognized line. Need to add field at /builds/gfx-ci/igt-ci-tags/tests/intel/xe_test_config.json?
==> Driver requirement: xe
ninja: build stopped: subcommand failed.
section_end:1718107432:step_script
section_start:1718107432:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1718107434:cleanup_file_variables
ERROR: Job failed: exit code 1
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/1198675
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2024-06-11 10:40 [PATCH v6 0/5] lib/gpgpu: add shader support Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 1/5] lib/gpu_cmds: add Xe_LP version of emit_vfe_state Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 2/5] lib/gpgpu_shader: tooling for preparing and running gpgpu shaders Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 3/5] lib/gpgpu_shader: add inline support for iga64 assembly Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 4/5] lib/igt_sysfs: add helpers to access engine sysfs directory Andrzej Hajda
2024-06-11 10:40 ` [PATCH v6 5/5] intel/xe_exec_sip: add shader sanity test Andrzej Hajda
2024-06-11 11:12 ` Grzegorzek, Dominik
2024-06-11 12:02 ` ✗ Fi.CI.BUILD: failure for lib/gpgpu: add shader support (rev6) Patchwork
2024-06-14 12:36 ` ✗ GitLab.Pipeline: warning " Patchwork
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