* [PATCH i-g-t v3 1/4] tests/vmwgfx: Removing incorrect assert in mob_repeated_unref
2024-06-28 19:02 [PATCH i-g-t v3 0/4] Add vmwgfx prime tests Zack Rusin
@ 2024-06-28 19:02 ` Zack Rusin
2024-06-28 19:02 ` [PATCH i-g-t v3 2/4] lib/vmwgfx: Allow using any buffer handle as a surface backing Zack Rusin
` (5 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Zack Rusin @ 2024-06-28 19:02 UTC (permalink / raw)
To: igt-dev
Cc: ian.forbes, martin.krastev, maaz.mombasawala, kamil.konieczny,
Maaz Mombasawala, Martin Krastev, Ian Forbes, Zack Rusin
From: Maaz Mombasawala <mombasawalam@vmware.com>
Remove an incorrect assert in test mob_repeated_unref that checked if return
value from multiple unrefs of a mob was 0. This was a bug in the vmwgfx driver,
since after the first unref it should return -EINVAL.
This bug was fixed with buffer rework in the vmwgfx driver and now the unref
ioctl behaves the correct way.
Signed-off-by: Maaz Mombasawala <mombasawalam@vmware.com>
Reviewed-by: Martin Krastev <krastevm@vmware.com>
Reviewed-by: Ian Forbes <iforbes@vmware.com>
Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
---
tests/vmwgfx/vmw_ref_count.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/tests/vmwgfx/vmw_ref_count.c b/tests/vmwgfx/vmw_ref_count.c
index da4b41f89..92d49dbd0 100644
--- a/tests/vmwgfx/vmw_ref_count.c
+++ b/tests/vmwgfx/vmw_ref_count.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/**********************************************************
- * Copyright 2021-2022 VMware, Inc.
+ * Copyright 2021-2023 VMware, Inc.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -256,13 +256,11 @@ igt_main
/* Shouldn't crash on multiple invocations */
for (i = 0; i < 3; i++) {
- int ret;
struct drm_vmw_handle_close_arg arg = {
.handle = mob->handle
};
- ret = drmCommandWrite(fd1, DRM_VMW_HANDLE_CLOSE, &arg,
+ drmCommandWrite(fd1, DRM_VMW_HANDLE_CLOSE, &arg,
sizeof(arg));
- igt_assert_eq(ret, 0);
}
free(mob);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH i-g-t v3 2/4] lib/vmwgfx: Allow using any buffer handle as a surface backing
2024-06-28 19:02 [PATCH i-g-t v3 0/4] Add vmwgfx prime tests Zack Rusin
2024-06-28 19:02 ` [PATCH i-g-t v3 1/4] tests/vmwgfx: Removing incorrect assert in mob_repeated_unref Zack Rusin
@ 2024-06-28 19:02 ` Zack Rusin
2024-07-26 19:00 ` Kamil Konieczny
2024-06-28 19:02 ` [PATCH i-g-t v3 3/4] tests/vmwgfx: Add a prime test Zack Rusin
` (4 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Zack Rusin @ 2024-06-28 19:02 UTC (permalink / raw)
To: igt-dev
Cc: ian.forbes, martin.krastev, maaz.mombasawala, kamil.konieczny,
Zack Rusin
Allow using any buffer handle as a surface backing to allow testing
prime/dma-buf imports. This will allow addition of vmwgfx specific
drm prime tests.
The code always expected a mob structure created via the explicit
alloc dmabuf ioctl which made using buffers created via dumb_buffer
drm interface impossible.
Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
---
lib/igt_vmwgfx.c | 33 ++++++++++++++++-----------------
lib/igt_vmwgfx.h | 12 ++++++++----
tests/vmwgfx/vmw_mob_stress.c | 5 ++++-
tests/vmwgfx/vmw_ref_count.c | 6 +++---
tests/vmwgfx/vmw_surface_copy.c | 8 ++++----
tests/vmwgfx/vmw_tri.c | 12 ++++++++----
6 files changed, 43 insertions(+), 33 deletions(-)
diff --git a/lib/igt_vmwgfx.c b/lib/igt_vmwgfx.c
index 12b07b4a8..d2f699575 100644
--- a/lib/igt_vmwgfx.c
+++ b/lib/igt_vmwgfx.c
@@ -427,7 +427,7 @@ struct vmw_surface *vmw_ioctl_buffer_create(int fd, SVGA3dSurfaceAllFlags flags,
SVGA3dSize surface_size = { .width = size, .height = 1, .depth = 1 };
return vmw_create_surface_simple(fd, flags, SVGA3D_BUFFER, surface_size,
- mob);
+ mob->handle);
}
/**
@@ -454,7 +454,7 @@ struct vmw_surface *vmw_ioctl_create_surface_full(
uint32 multisample_count, SVGA3dMSPattern multisample_pattern,
SVGA3dMSQualityLevel quality_level, SVGA3dTextureFilter autogen_filter,
uint32 num_mip_levels, uint32 array_size, SVGA3dSize size,
- struct vmw_mob *mob, enum drm_vmw_surface_flags surface_flags)
+ uint32 buffer_handle, enum drm_vmw_surface_flags surface_flags)
{
struct vmw_surface *surface;
int32 ret;
@@ -470,10 +470,8 @@ struct vmw_surface *vmw_ioctl_create_surface_full(
arg.req.base.array_size = array_size;
arg.req.base.autogen_filter = autogen_filter;
arg.req.base.drm_surface_flags |= surface_flags;
- if (mob) {
- arg.req.base.buffer_handle = mob->handle;
- } else {
- arg.req.base.buffer_handle = SVGA3D_INVALID_ID;
+ arg.req.base.buffer_handle = buffer_handle;
+ if (buffer_handle != SVGA3D_INVALID_ID) {
arg.req.base.drm_surface_flags |=
drm_vmw_surface_flag_create_buffer;
}
@@ -499,7 +497,6 @@ struct vmw_surface *vmw_ioctl_create_surface_full(
}
surface->base = arg.rep;
- surface->mob = mob;
return surface;
out_err1:
@@ -511,7 +508,7 @@ struct vmw_surface *vmw_create_surface_simple(int fd,
SVGA3dSurfaceAllFlags flags,
SVGA3dSurfaceFormat format,
SVGA3dSize size,
- struct vmw_mob *mob)
+ uint32 buffer_handle)
{
/*
* TODO:
@@ -531,7 +528,7 @@ struct vmw_surface *vmw_create_surface_simple(int fd,
multisample_count,
multisample_pattern, quality_level,
SVGA3D_TEX_FILTER_NONE, 1,
- array_size, size, mob, 0);
+ array_size, size, buffer_handle, 0);
}
/**
@@ -921,14 +918,14 @@ void vmw_create_default_objects(struct vmw_svga_device *device,
device->drm_fd,
SVGA3D_SURFACE_HINT_TEXTURE | SVGA3D_SURFACE_HINT_RENDERTARGET |
SVGA3D_SURFACE_BIND_RENDER_TARGET,
- SVGA3D_R8G8B8A8_UNORM, *rt_size, NULL);
+ SVGA3D_R8G8B8A8_UNORM, *rt_size, SVGA3D_INVALID_ID);
objects->depth_rt = vmw_create_surface_simple(
device->drm_fd,
SVGA3D_SURFACE_HINT_DEPTHSTENCIL |
SVGA3D_SURFACE_HINT_RENDERTARGET |
SVGA3D_SURFACE_BIND_DEPTH_STENCIL,
- SVGA3D_R24G8_TYPELESS, *rt_size, NULL);
+ SVGA3D_R24G8_TYPELESS, *rt_size, SVGA3D_INVALID_ID);
rtv_desc.tex.arraySize = 1;
rtv_desc.tex.firstArraySlice = 0;
@@ -1225,7 +1222,8 @@ void vmw_cmd_surface_copy(struct vmw_execbuf *cmd_buf, SVGA3dSurfaceImageId src,
}
uint8 *vmw_triangle_draw(struct vmw_svga_device *device, int32 cid,
- struct vmw_default_objects *objects, bool do_sync)
+ struct vmw_default_objects *objects,
+ uint32_t draw_flags)
{
struct vmw_execbuf *cmd_buf;
struct drm_vmw_fence_rep cmd_fence;
@@ -1234,7 +1232,7 @@ uint8 *vmw_triangle_draw(struct vmw_svga_device *device, int32 cid,
SVGA3dVertexBuffer vb_binding;
SVGA3dRGBAFloat clear_color;
void *vertex_data;
- uint8 *rendered_img;
+ uint8 *rendered_img = NULL;
struct vmw_vertex vertices[3] = {
{ 0.0, 0.75, 0.5, 1.0, 0.0, 1.0, 0.0, 1.0 },
{ 0.75, -0.75, 0.5, 1.0, 1.0, 0.0, 0.0, 1.0 },
@@ -1281,19 +1279,20 @@ uint8 *vmw_triangle_draw(struct vmw_svga_device *device, int32 cid,
/* Draw */
vmw_cmd_draw(cmd_buf, 3, 0);
- vmw_cmd_draw(cmd_buf, 3, 0);
/* Readback */
- vmw_cmd_readback_gb_surface(cmd_buf, objects->color_rt->base.handle);
+ if (draw_flags & vmw_triangle_draw_flags_readback)
+ vmw_cmd_readback_gb_surface(cmd_buf, objects->color_rt->base.handle);
/* Submit commands */
vmw_execbuf_submit(cmd_buf, &cmd_fence);
- if (do_sync)
+ if (draw_flags & vmw_triangle_draw_flags_sync)
vmw_ioctl_fence_finish(device->drm_fd, &cmd_fence);
vmw_execbuf_destroy(cmd_buf);
/* Read framebuffer into system mem and save */
- rendered_img = vmw_readback_surface(device->drm_fd, objects->color_rt);
+ if (draw_flags & vmw_triangle_draw_flags_readback)
+ rendered_img = vmw_readback_surface(device->drm_fd, objects->color_rt);
vmw_ioctl_surface_unref(device->drm_fd, vertex_buffer);
vmw_ioctl_mob_close_handle(device->drm_fd, vertex_mob);
diff --git a/lib/igt_vmwgfx.h b/lib/igt_vmwgfx.h
index c8ed43bac..961aac389 100644
--- a/lib/igt_vmwgfx.h
+++ b/lib/igt_vmwgfx.h
@@ -115,7 +115,6 @@ struct vmw_mob {
struct vmw_surface {
struct drm_vmw_gb_surface_create_rep base;
struct drm_vmw_gb_surface_create_ext_req params;
- struct vmw_mob *mob;
};
struct vmw_vertex {
@@ -194,13 +193,13 @@ struct vmw_surface *vmw_ioctl_create_surface_full(
uint32 multisample_count, SVGA3dMSPattern multisample_pattern,
SVGA3dMSQualityLevel quality_level, SVGA3dTextureFilter autogen_filter,
uint32 num_mip_levels, uint32 array_size, SVGA3dSize size,
- struct vmw_mob *mob, enum drm_vmw_surface_flags surface_flags);
+ uint32 buffer_handle, enum drm_vmw_surface_flags surface_flags);
struct vmw_surface *vmw_create_surface_simple(int fd,
SVGA3dSurfaceAllFlags flags,
SVGA3dSurfaceFormat format,
SVGA3dSize size,
- struct vmw_mob *mob);
+ uint32 buffer_handle);
struct vmw_execbuf *vmw_execbuf_create(int drm_fd, int32_t cid);
void vmw_execbuf_set_cid(struct vmw_execbuf *execbuf, int32_t cid);
@@ -261,8 +260,13 @@ void vmw_cmd_surface_copy(struct vmw_execbuf *cmd_buf, SVGA3dSurfaceImageId src,
SVGA3dSurfaceImageId dest, const SVGA3dCopyBox *boxes,
uint32 num_boxes);
+enum vmw_triangle_draw_flags {
+ vmw_triangle_draw_flags_none = 0,
+ vmw_triangle_draw_flags_sync = 1 << 0,
+ vmw_triangle_draw_flags_readback = 1 << 1,
+};
uint8 *vmw_triangle_draw(struct vmw_svga_device *device, int32 cid,
- struct vmw_default_objects *objects, bool do_sync);
+ struct vmw_default_objects *objects, uint32_t draw_flags);
void vmw_triangle_assert_values(uint8 *rendered_img,
struct vmw_surface *color_rt);
diff --git a/tests/vmwgfx/vmw_mob_stress.c b/tests/vmwgfx/vmw_mob_stress.c
index 4af23d6f7..2e6a9422c 100644
--- a/tests/vmwgfx/vmw_mob_stress.c
+++ b/tests/vmwgfx/vmw_mob_stress.c
@@ -35,7 +35,10 @@ static void test_triangle_render(struct vmw_svga_device *device, int32 cid)
vmw_create_default_objects(device, cid, &objects,
&vmw_default_rect_size);
- rendered_tri = vmw_triangle_draw(device, cid, &objects, true);
+ rendered_tri =
+ vmw_triangle_draw(device, cid, &objects,
+ vmw_triangle_draw_flags_sync |
+ vmw_triangle_draw_flags_readback);
vmw_triangle_assert_values(rendered_tri, objects.color_rt);
free(rendered_tri);
diff --git a/tests/vmwgfx/vmw_ref_count.c b/tests/vmwgfx/vmw_ref_count.c
index 92d49dbd0..c765f2e70 100644
--- a/tests/vmwgfx/vmw_ref_count.c
+++ b/tests/vmwgfx/vmw_ref_count.c
@@ -72,7 +72,7 @@ create_and_write_shareable_surface(int32 fd, SVGA3dSize surface_size)
surface = vmw_ioctl_create_surface_full(
fd, SVGA3D_SURFACE_HINT_RENDERTARGET, SVGA3D_BUFFER, 0,
SVGA3D_MS_PATTERN_NONE, SVGA3D_MS_QUALITY_NONE,
- SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, NULL,
+ SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, SVGA3D_INVALID_ID,
drm_vmw_surface_flag_shareable);
mob.handle = surface->base.buffer_handle;
@@ -125,7 +125,7 @@ igt_main
surface = vmw_ioctl_create_surface_full(
fd1, SVGA3D_SURFACE_HINT_RENDERTARGET, SVGA3D_BUFFER, 0,
SVGA3D_MS_PATTERN_NONE, SVGA3D_MS_QUALITY_NONE,
- SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, mob,
+ SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, mob->handle,
drm_vmw_surface_flag_shareable);
write_to_mob(fd1, mob);
@@ -274,7 +274,7 @@ igt_main
surface = vmw_ioctl_create_surface_full(
fd1, SVGA3D_SURFACE_HINT_RENDERTARGET, SVGA3D_BUFFER, 0,
SVGA3D_MS_PATTERN_NONE, SVGA3D_MS_QUALITY_NONE,
- SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, NULL,
+ SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, SVGA3D_INVALID_ID,
drm_vmw_surface_flag_shareable);
/* Shouldn't crash on multiple invocations */
diff --git a/tests/vmwgfx/vmw_surface_copy.c b/tests/vmwgfx/vmw_surface_copy.c
index 57e90334f..471de54aa 100644
--- a/tests/vmwgfx/vmw_surface_copy.c
+++ b/tests/vmwgfx/vmw_surface_copy.c
@@ -120,9 +120,9 @@ static void test_invalid_copies(int fd, int32 cid)
vmw_is_format_supported(fd, SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8));
s1 = vmw_create_surface_simple(fd, 0, SVGA3D_A8R8G8B8, surface_size,
- NULL);
+ SVGA3D_INVALID_ID);
s2 = vmw_create_surface_simple(fd, 0, SVGA3D_A8R8G8B8, surface_size,
- NULL);
+ SVGA3D_INVALID_ID);
cmd_buf = vmw_execbuf_create(fd, cid);
box.x = 0;
@@ -271,8 +271,8 @@ static void test_invalid_copies_3d(int fd, int32 cid)
igt_require(vmw_is_format_supported(fd, SVGA3D_DEVCAP_DXFMT_Z_D32));
s1 = vmw_create_surface_simple(fd, 0, SVGA3D_A8R8G8B8, surface_size,
- NULL);
- s2 = vmw_create_surface_simple(fd, 0, SVGA3D_Z_D32, surface_size, NULL);
+ SVGA3D_INVALID_ID);
+ s2 = vmw_create_surface_simple(fd, 0, SVGA3D_Z_D32, surface_size, SVGA3D_INVALID_ID);
cmd_buf = vmw_execbuf_create(fd, cid);
box.x = 0;
diff --git a/tests/vmwgfx/vmw_tri.c b/tests/vmwgfx/vmw_tri.c
index f5a59229c..61c4d5df8 100644
--- a/tests/vmwgfx/vmw_tri.c
+++ b/tests/vmwgfx/vmw_tri.c
@@ -36,7 +36,10 @@ static void draw_triangle(struct vmw_svga_device *device, int32 cid)
vmw_create_default_objects(device, cid, &objects,
&vmw_default_rect_size);
- rendered_img = vmw_triangle_draw(device, cid, &objects, true);
+ rendered_img =
+ vmw_triangle_draw(device, cid, &objects,
+ vmw_triangle_draw_flags_sync |
+ vmw_triangle_draw_flags_readback);
save_status = vmw_save_data_as_png(objects.color_rt, rendered_img,
"vmw_tri.png");
@@ -65,7 +68,7 @@ static void replace_with_coherent_rt(struct vmw_svga_device *device,
SVGA3D_SURFACE_BIND_RENDER_TARGET,
SVGA3D_R8G8B8A8_UNORM, 0, SVGA3D_MS_PATTERN_NONE,
SVGA3D_MS_QUALITY_NONE, SVGA3D_TEX_FILTER_NONE, 1, 1, *rt_size,
- NULL, drm_vmw_surface_flag_coherent);
+ SVGA3D_INVALID_ID, drm_vmw_surface_flag_coherent);
objects->depth_rt = vmw_ioctl_create_surface_full(
device->drm_fd,
@@ -74,7 +77,7 @@ static void replace_with_coherent_rt(struct vmw_svga_device *device,
SVGA3D_SURFACE_BIND_DEPTH_STENCIL,
SVGA3D_R24G8_TYPELESS, 0, SVGA3D_MS_PATTERN_NONE,
SVGA3D_MS_QUALITY_NONE, SVGA3D_TEX_FILTER_NONE, 1, 1, *rt_size,
- NULL, drm_vmw_surface_flag_coherent);
+ SVGA3D_INVALID_ID, drm_vmw_surface_flag_coherent);
cmd_buf = vmw_execbuf_create(device->drm_fd, context_id);
@@ -160,7 +163,8 @@ static void draw_triangle_on_coherent_rt(struct vmw_svga_device *device,
default_ds_view_id = objects.ds_view_id;
replace_with_coherent_rt(device, cid, &objects, &vmw_default_rect_size);
- rendered_img = vmw_triangle_draw(device, cid, &objects, false);
+ rendered_img = vmw_triangle_draw(device, cid, &objects,
+ vmw_triangle_draw_flags_readback);
vmw_triangle_assert_values(rendered_img, objects.color_rt);
--
2.40.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH i-g-t v3 2/4] lib/vmwgfx: Allow using any buffer handle as a surface backing
2024-06-28 19:02 ` [PATCH i-g-t v3 2/4] lib/vmwgfx: Allow using any buffer handle as a surface backing Zack Rusin
@ 2024-07-26 19:00 ` Kamil Konieczny
0 siblings, 0 replies; 12+ messages in thread
From: Kamil Konieczny @ 2024-07-26 19:00 UTC (permalink / raw)
To: igt-dev; +Cc: Zack Rusin, ian.forbes, martin.krastev, maaz.mombasawala
Hi Zack,
On 2024-06-28 at 15:02:41 -0400, Zack Rusin wrote:
> Allow using any buffer handle as a surface backing to allow testing
> prime/dma-buf imports. This will allow addition of vmwgfx specific
> drm prime tests.
>
> The code always expected a mob structure created via the explicit
> alloc dmabuf ioctl which made using buffers created via dumb_buffer
> drm interface impossible.
>
> Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
> ---
> lib/igt_vmwgfx.c | 33 ++++++++++++++++-----------------
> lib/igt_vmwgfx.h | 12 ++++++++----
> tests/vmwgfx/vmw_mob_stress.c | 5 ++++-
> tests/vmwgfx/vmw_ref_count.c | 6 +++---
> tests/vmwgfx/vmw_surface_copy.c | 8 ++++----
> tests/vmwgfx/vmw_tri.c | 12 ++++++++----
> 6 files changed, 43 insertions(+), 33 deletions(-)
>
> diff --git a/lib/igt_vmwgfx.c b/lib/igt_vmwgfx.c
> index 12b07b4a8..d2f699575 100644
> --- a/lib/igt_vmwgfx.c
> +++ b/lib/igt_vmwgfx.c
> @@ -427,7 +427,7 @@ struct vmw_surface *vmw_ioctl_buffer_create(int fd, SVGA3dSurfaceAllFlags flags,
> SVGA3dSize surface_size = { .width = size, .height = 1, .depth = 1 };
>
> return vmw_create_surface_simple(fd, flags, SVGA3D_BUFFER, surface_size,
> - mob);
> + mob->handle);
> }
>
> /**
> @@ -454,7 +454,7 @@ struct vmw_surface *vmw_ioctl_create_surface_full(
> uint32 multisample_count, SVGA3dMSPattern multisample_pattern,
> SVGA3dMSQualityLevel quality_level, SVGA3dTextureFilter autogen_filter,
> uint32 num_mip_levels, uint32 array_size, SVGA3dSize size,
> - struct vmw_mob *mob, enum drm_vmw_surface_flags surface_flags)
> + uint32 buffer_handle, enum drm_vmw_surface_flags surface_flags)
> {
> struct vmw_surface *surface;
> int32 ret;
> @@ -470,10 +470,8 @@ struct vmw_surface *vmw_ioctl_create_surface_full(
> arg.req.base.array_size = array_size;
> arg.req.base.autogen_filter = autogen_filter;
> arg.req.base.drm_surface_flags |= surface_flags;
> - if (mob) {
> - arg.req.base.buffer_handle = mob->handle;
> - } else {
> - arg.req.base.buffer_handle = SVGA3D_INVALID_ID;
> + arg.req.base.buffer_handle = buffer_handle;
> + if (buffer_handle != SVGA3D_INVALID_ID) {
> arg.req.base.drm_surface_flags |=
> drm_vmw_surface_flag_create_buffer;
> }
> @@ -499,7 +497,6 @@ struct vmw_surface *vmw_ioctl_create_surface_full(
> }
>
> surface->base = arg.rep;
> - surface->mob = mob;
> return surface;
>
> out_err1:
> @@ -511,7 +508,7 @@ struct vmw_surface *vmw_create_surface_simple(int fd,
> SVGA3dSurfaceAllFlags flags,
> SVGA3dSurfaceFormat format,
> SVGA3dSize size,
> - struct vmw_mob *mob)
> + uint32 buffer_handle)
> {
> /*
> * TODO:
> @@ -531,7 +528,7 @@ struct vmw_surface *vmw_create_surface_simple(int fd,
> multisample_count,
> multisample_pattern, quality_level,
> SVGA3D_TEX_FILTER_NONE, 1,
> - array_size, size, mob, 0);
> + array_size, size, buffer_handle, 0);
> }
>
> /**
> @@ -921,14 +918,14 @@ void vmw_create_default_objects(struct vmw_svga_device *device,
> device->drm_fd,
> SVGA3D_SURFACE_HINT_TEXTURE | SVGA3D_SURFACE_HINT_RENDERTARGET |
> SVGA3D_SURFACE_BIND_RENDER_TARGET,
> - SVGA3D_R8G8B8A8_UNORM, *rt_size, NULL);
> + SVGA3D_R8G8B8A8_UNORM, *rt_size, SVGA3D_INVALID_ID);
>
> objects->depth_rt = vmw_create_surface_simple(
> device->drm_fd,
> SVGA3D_SURFACE_HINT_DEPTHSTENCIL |
> SVGA3D_SURFACE_HINT_RENDERTARGET |
> SVGA3D_SURFACE_BIND_DEPTH_STENCIL,
> - SVGA3D_R24G8_TYPELESS, *rt_size, NULL);
> + SVGA3D_R24G8_TYPELESS, *rt_size, SVGA3D_INVALID_ID);
>
> rtv_desc.tex.arraySize = 1;
> rtv_desc.tex.firstArraySlice = 0;
> @@ -1225,7 +1222,8 @@ void vmw_cmd_surface_copy(struct vmw_execbuf *cmd_buf, SVGA3dSurfaceImageId src,
> }
>
> uint8 *vmw_triangle_draw(struct vmw_svga_device *device, int32 cid,
> - struct vmw_default_objects *objects, bool do_sync)
> + struct vmw_default_objects *objects,
> + uint32_t draw_flags)
> {
> struct vmw_execbuf *cmd_buf;
> struct drm_vmw_fence_rep cmd_fence;
> @@ -1234,7 +1232,7 @@ uint8 *vmw_triangle_draw(struct vmw_svga_device *device, int32 cid,
> SVGA3dVertexBuffer vb_binding;
> SVGA3dRGBAFloat clear_color;
> void *vertex_data;
> - uint8 *rendered_img;
> + uint8 *rendered_img = NULL;
> struct vmw_vertex vertices[3] = {
> { 0.0, 0.75, 0.5, 1.0, 0.0, 1.0, 0.0, 1.0 },
> { 0.75, -0.75, 0.5, 1.0, 1.0, 0.0, 0.0, 1.0 },
> @@ -1281,19 +1279,20 @@ uint8 *vmw_triangle_draw(struct vmw_svga_device *device, int32 cid,
>
> /* Draw */
> vmw_cmd_draw(cmd_buf, 3, 0);
> - vmw_cmd_draw(cmd_buf, 3, 0);
>
> /* Readback */
> - vmw_cmd_readback_gb_surface(cmd_buf, objects->color_rt->base.handle);
> + if (draw_flags & vmw_triangle_draw_flags_readback)
> + vmw_cmd_readback_gb_surface(cmd_buf, objects->color_rt->base.handle);
>
> /* Submit commands */
> vmw_execbuf_submit(cmd_buf, &cmd_fence);
> - if (do_sync)
> + if (draw_flags & vmw_triangle_draw_flags_sync)
> vmw_ioctl_fence_finish(device->drm_fd, &cmd_fence);
> vmw_execbuf_destroy(cmd_buf);
>
> /* Read framebuffer into system mem and save */
> - rendered_img = vmw_readback_surface(device->drm_fd, objects->color_rt);
> + if (draw_flags & vmw_triangle_draw_flags_readback)
> + rendered_img = vmw_readback_surface(device->drm_fd, objects->color_rt);
>
> vmw_ioctl_surface_unref(device->drm_fd, vertex_buffer);
> vmw_ioctl_mob_close_handle(device->drm_fd, vertex_mob);
> diff --git a/lib/igt_vmwgfx.h b/lib/igt_vmwgfx.h
> index c8ed43bac..961aac389 100644
> --- a/lib/igt_vmwgfx.h
> +++ b/lib/igt_vmwgfx.h
> @@ -115,7 +115,6 @@ struct vmw_mob {
> struct vmw_surface {
> struct drm_vmw_gb_surface_create_rep base;
> struct drm_vmw_gb_surface_create_ext_req params;
> - struct vmw_mob *mob;
> };
>
> struct vmw_vertex {
> @@ -194,13 +193,13 @@ struct vmw_surface *vmw_ioctl_create_surface_full(
> uint32 multisample_count, SVGA3dMSPattern multisample_pattern,
> SVGA3dMSQualityLevel quality_level, SVGA3dTextureFilter autogen_filter,
> uint32 num_mip_levels, uint32 array_size, SVGA3dSize size,
> - struct vmw_mob *mob, enum drm_vmw_surface_flags surface_flags);
> + uint32 buffer_handle, enum drm_vmw_surface_flags surface_flags);
>
> struct vmw_surface *vmw_create_surface_simple(int fd,
> SVGA3dSurfaceAllFlags flags,
> SVGA3dSurfaceFormat format,
> SVGA3dSize size,
> - struct vmw_mob *mob);
> + uint32 buffer_handle);
>
> struct vmw_execbuf *vmw_execbuf_create(int drm_fd, int32_t cid);
> void vmw_execbuf_set_cid(struct vmw_execbuf *execbuf, int32_t cid);
> @@ -261,8 +260,13 @@ void vmw_cmd_surface_copy(struct vmw_execbuf *cmd_buf, SVGA3dSurfaceImageId src,
> SVGA3dSurfaceImageId dest, const SVGA3dCopyBox *boxes,
> uint32 num_boxes);
>
> +enum vmw_triangle_draw_flags {
> + vmw_triangle_draw_flags_none = 0,
> + vmw_triangle_draw_flags_sync = 1 << 0,
> + vmw_triangle_draw_flags_readback = 1 << 1,
> +};
Add newline here.
With that
Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> uint8 *vmw_triangle_draw(struct vmw_svga_device *device, int32 cid,
> - struct vmw_default_objects *objects, bool do_sync);
> + struct vmw_default_objects *objects, uint32_t draw_flags);
>
> void vmw_triangle_assert_values(uint8 *rendered_img,
> struct vmw_surface *color_rt);
> diff --git a/tests/vmwgfx/vmw_mob_stress.c b/tests/vmwgfx/vmw_mob_stress.c
> index 4af23d6f7..2e6a9422c 100644
> --- a/tests/vmwgfx/vmw_mob_stress.c
> +++ b/tests/vmwgfx/vmw_mob_stress.c
> @@ -35,7 +35,10 @@ static void test_triangle_render(struct vmw_svga_device *device, int32 cid)
>
> vmw_create_default_objects(device, cid, &objects,
> &vmw_default_rect_size);
> - rendered_tri = vmw_triangle_draw(device, cid, &objects, true);
> + rendered_tri =
> + vmw_triangle_draw(device, cid, &objects,
> + vmw_triangle_draw_flags_sync |
> + vmw_triangle_draw_flags_readback);
> vmw_triangle_assert_values(rendered_tri, objects.color_rt);
>
> free(rendered_tri);
> diff --git a/tests/vmwgfx/vmw_ref_count.c b/tests/vmwgfx/vmw_ref_count.c
> index 92d49dbd0..c765f2e70 100644
> --- a/tests/vmwgfx/vmw_ref_count.c
> +++ b/tests/vmwgfx/vmw_ref_count.c
> @@ -72,7 +72,7 @@ create_and_write_shareable_surface(int32 fd, SVGA3dSize surface_size)
> surface = vmw_ioctl_create_surface_full(
> fd, SVGA3D_SURFACE_HINT_RENDERTARGET, SVGA3D_BUFFER, 0,
> SVGA3D_MS_PATTERN_NONE, SVGA3D_MS_QUALITY_NONE,
> - SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, NULL,
> + SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, SVGA3D_INVALID_ID,
> drm_vmw_surface_flag_shareable);
>
> mob.handle = surface->base.buffer_handle;
> @@ -125,7 +125,7 @@ igt_main
> surface = vmw_ioctl_create_surface_full(
> fd1, SVGA3D_SURFACE_HINT_RENDERTARGET, SVGA3D_BUFFER, 0,
> SVGA3D_MS_PATTERN_NONE, SVGA3D_MS_QUALITY_NONE,
> - SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, mob,
> + SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, mob->handle,
> drm_vmw_surface_flag_shareable);
>
> write_to_mob(fd1, mob);
> @@ -274,7 +274,7 @@ igt_main
> surface = vmw_ioctl_create_surface_full(
> fd1, SVGA3D_SURFACE_HINT_RENDERTARGET, SVGA3D_BUFFER, 0,
> SVGA3D_MS_PATTERN_NONE, SVGA3D_MS_QUALITY_NONE,
> - SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, NULL,
> + SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, SVGA3D_INVALID_ID,
> drm_vmw_surface_flag_shareable);
>
> /* Shouldn't crash on multiple invocations */
> diff --git a/tests/vmwgfx/vmw_surface_copy.c b/tests/vmwgfx/vmw_surface_copy.c
> index 57e90334f..471de54aa 100644
> --- a/tests/vmwgfx/vmw_surface_copy.c
> +++ b/tests/vmwgfx/vmw_surface_copy.c
> @@ -120,9 +120,9 @@ static void test_invalid_copies(int fd, int32 cid)
> vmw_is_format_supported(fd, SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8));
>
> s1 = vmw_create_surface_simple(fd, 0, SVGA3D_A8R8G8B8, surface_size,
> - NULL);
> + SVGA3D_INVALID_ID);
> s2 = vmw_create_surface_simple(fd, 0, SVGA3D_A8R8G8B8, surface_size,
> - NULL);
> + SVGA3D_INVALID_ID);
> cmd_buf = vmw_execbuf_create(fd, cid);
>
> box.x = 0;
> @@ -271,8 +271,8 @@ static void test_invalid_copies_3d(int fd, int32 cid)
> igt_require(vmw_is_format_supported(fd, SVGA3D_DEVCAP_DXFMT_Z_D32));
>
> s1 = vmw_create_surface_simple(fd, 0, SVGA3D_A8R8G8B8, surface_size,
> - NULL);
> - s2 = vmw_create_surface_simple(fd, 0, SVGA3D_Z_D32, surface_size, NULL);
> + SVGA3D_INVALID_ID);
> + s2 = vmw_create_surface_simple(fd, 0, SVGA3D_Z_D32, surface_size, SVGA3D_INVALID_ID);
> cmd_buf = vmw_execbuf_create(fd, cid);
>
> box.x = 0;
> diff --git a/tests/vmwgfx/vmw_tri.c b/tests/vmwgfx/vmw_tri.c
> index f5a59229c..61c4d5df8 100644
> --- a/tests/vmwgfx/vmw_tri.c
> +++ b/tests/vmwgfx/vmw_tri.c
> @@ -36,7 +36,10 @@ static void draw_triangle(struct vmw_svga_device *device, int32 cid)
>
> vmw_create_default_objects(device, cid, &objects,
> &vmw_default_rect_size);
> - rendered_img = vmw_triangle_draw(device, cid, &objects, true);
> + rendered_img =
> + vmw_triangle_draw(device, cid, &objects,
> + vmw_triangle_draw_flags_sync |
> + vmw_triangle_draw_flags_readback);
>
> save_status = vmw_save_data_as_png(objects.color_rt, rendered_img,
> "vmw_tri.png");
> @@ -65,7 +68,7 @@ static void replace_with_coherent_rt(struct vmw_svga_device *device,
> SVGA3D_SURFACE_BIND_RENDER_TARGET,
> SVGA3D_R8G8B8A8_UNORM, 0, SVGA3D_MS_PATTERN_NONE,
> SVGA3D_MS_QUALITY_NONE, SVGA3D_TEX_FILTER_NONE, 1, 1, *rt_size,
> - NULL, drm_vmw_surface_flag_coherent);
> + SVGA3D_INVALID_ID, drm_vmw_surface_flag_coherent);
>
> objects->depth_rt = vmw_ioctl_create_surface_full(
> device->drm_fd,
> @@ -74,7 +77,7 @@ static void replace_with_coherent_rt(struct vmw_svga_device *device,
> SVGA3D_SURFACE_BIND_DEPTH_STENCIL,
> SVGA3D_R24G8_TYPELESS, 0, SVGA3D_MS_PATTERN_NONE,
> SVGA3D_MS_QUALITY_NONE, SVGA3D_TEX_FILTER_NONE, 1, 1, *rt_size,
> - NULL, drm_vmw_surface_flag_coherent);
> + SVGA3D_INVALID_ID, drm_vmw_surface_flag_coherent);
>
> cmd_buf = vmw_execbuf_create(device->drm_fd, context_id);
>
> @@ -160,7 +163,8 @@ static void draw_triangle_on_coherent_rt(struct vmw_svga_device *device,
> default_ds_view_id = objects.ds_view_id;
> replace_with_coherent_rt(device, cid, &objects, &vmw_default_rect_size);
>
> - rendered_img = vmw_triangle_draw(device, cid, &objects, false);
> + rendered_img = vmw_triangle_draw(device, cid, &objects,
> + vmw_triangle_draw_flags_readback);
>
> vmw_triangle_assert_values(rendered_img, objects.color_rt);
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH i-g-t v3 3/4] tests/vmwgfx: Add a prime test
2024-06-28 19:02 [PATCH i-g-t v3 0/4] Add vmwgfx prime tests Zack Rusin
2024-06-28 19:02 ` [PATCH i-g-t v3 1/4] tests/vmwgfx: Removing incorrect assert in mob_repeated_unref Zack Rusin
2024-06-28 19:02 ` [PATCH i-g-t v3 2/4] lib/vmwgfx: Allow using any buffer handle as a surface backing Zack Rusin
@ 2024-06-28 19:02 ` Zack Rusin
2024-07-26 19:07 ` Kamil Konieczny
2024-06-28 19:02 ` [PATCH i-g-t v3 4/4] tests/vmwgfx: Fix and extend the reference counting test Zack Rusin
` (3 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Zack Rusin @ 2024-06-28 19:02 UTC (permalink / raw)
To: igt-dev
Cc: ian.forbes, martin.krastev, maaz.mombasawala, kamil.konieczny,
Zack Rusin
Add a test that check for various dma-buf/prime related issues that might
show up on vmwgfx.
Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
---
tests/vmwgfx/meson.build | 7 +-
tests/vmwgfx/vmw_prime.c | 599 +++++++++++++++++++++++++++++++++++++++
2 files changed, 603 insertions(+), 3 deletions(-)
create mode 100644 tests/vmwgfx/vmw_prime.c
diff --git a/tests/vmwgfx/meson.build b/tests/vmwgfx/meson.build
index 073905f0a..28163d0f1 100644
--- a/tests/vmwgfx/meson.build
+++ b/tests/vmwgfx/meson.build
@@ -1,10 +1,11 @@
vmwgfx_progs = [
- 'vmw_tri',
'vmw_execution_buffer',
- 'vmw_surface_copy',
'vmw_mob_stress',
- 'vmw_ref_count'
+ 'vmw_prime',
+ 'vmw_ref_count',
+ 'vmw_surface_copy',
+ 'vmw_tri',
]
vmwgfx_deps = test_deps
diff --git a/tests/vmwgfx/vmw_prime.c b/tests/vmwgfx/vmw_prime.c
new file mode 100644
index 000000000..891628b9b
--- /dev/null
+++ b/tests/vmwgfx/vmw_prime.c
@@ -0,0 +1,599 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024 Broadcom. All Rights Reserved. The term
+ * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
+ */
+
+#include "igt_kms.h"
+#include "igt_vmwgfx.h"
+
+IGT_TEST_DESCRIPTION(
+ "Check whether basic DRM prime and dma-buf work correctly.");
+
+static void replace_with_prime_rt(struct vmw_svga_device *device,
+ int32 context_id,
+ uint32 prime_fd,
+ uint32 buffer_handle,
+ struct vmw_default_objects *objects,
+ const SVGA3dSize *rt_size)
+{
+ struct vmw_execbuf *cmd_buf;
+ SVGA3dRenderTargetViewDesc rtv_desc = { 0 };
+ SVGA3dCmdDXDefineRenderTargetView rt_view_define_cmd = { 0 };
+ SVGA3dCmdDXDestroyRenderTargetView rt_view_cmd = {
+ .renderTargetViewId = objects->color_rt_id
+ };
+
+ vmw_ioctl_surface_unref(device->drm_fd, objects->color_rt);
+ objects->color_rt = vmw_ioctl_surface_ref(device->drm_fd, prime_fd, DRM_VMW_HANDLE_PRIME);
+
+ cmd_buf = vmw_execbuf_create(device->drm_fd, context_id);
+
+ rtv_desc.tex.arraySize = 1;
+ rtv_desc.tex.firstArraySlice = 0;
+ rtv_desc.tex.mipSlice = 0;
+ vmw_bitvector_find_next_bit(device->rt_view_bv,
+ &rt_view_define_cmd.renderTargetViewId);
+ rt_view_define_cmd.sid = objects->color_rt->base.handle;
+ rt_view_define_cmd.format = SVGA3D_B8G8R8X8_UNORM;
+ rt_view_define_cmd.resourceDimension = SVGA3D_RESOURCE_TEXTURE2D;
+ rt_view_define_cmd.desc = rtv_desc;
+ vmw_execbuf_append(cmd_buf, SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW,
+ &rt_view_cmd, sizeof(rt_view_cmd), NULL, 0);
+ vmw_execbuf_append(cmd_buf, SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW,
+ &rt_view_define_cmd, sizeof(rt_view_define_cmd),
+ NULL, 0);
+ vmw_execbuf_submit(cmd_buf, NULL);
+ vmw_execbuf_destroy(cmd_buf);
+
+ vmw_bitvector_free_bit(device->rt_view_bv, objects->color_rt_id);
+ objects->color_rt_id = rt_view_define_cmd.renderTargetViewId;
+}
+
+static void replace_with_surface(struct vmw_svga_device *device,
+ int32 context_id, struct vmw_surface *surf,
+ struct vmw_default_objects *objects,
+ const SVGA3dSize *rt_size)
+{
+ struct vmw_execbuf *cmd_buf;
+ SVGA3dRenderTargetViewDesc rtv_desc = { 0 };
+ SVGA3dCmdDXDefineRenderTargetView rt_view_define_cmd = { 0 };
+ SVGA3dCmdDXDestroyRenderTargetView rt_view_cmd = {
+ .renderTargetViewId = objects->color_rt_id
+ };
+
+ vmw_ioctl_surface_unref(device->drm_fd, objects->color_rt);
+ objects->color_rt = vmw_ioctl_surface_ref(device->drm_fd, surf->base.handle, DRM_VMW_HANDLE_LEGACY);
+
+ cmd_buf = vmw_execbuf_create(device->drm_fd, context_id);
+
+ rtv_desc.tex.arraySize = 1;
+ rtv_desc.tex.firstArraySlice = 0;
+ rtv_desc.tex.mipSlice = 0;
+ vmw_bitvector_find_next_bit(device->rt_view_bv,
+ &rt_view_define_cmd.renderTargetViewId);
+ rt_view_define_cmd.sid = objects->color_rt->base.handle;
+ rt_view_define_cmd.format = SVGA3D_B8G8R8X8_UNORM;
+ rt_view_define_cmd.resourceDimension = SVGA3D_RESOURCE_TEXTURE2D;
+ rt_view_define_cmd.desc = rtv_desc;
+ vmw_execbuf_append(cmd_buf, SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW,
+ &rt_view_cmd, sizeof(rt_view_cmd), NULL, 0);
+ vmw_execbuf_append(cmd_buf, SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW,
+ &rt_view_define_cmd, sizeof(rt_view_define_cmd),
+ NULL, 0);
+ vmw_execbuf_submit(cmd_buf, NULL);
+ vmw_execbuf_destroy(cmd_buf);
+
+ vmw_bitvector_free_bit(device->rt_view_bv, objects->color_rt_id);
+ objects->color_rt_id = rt_view_define_cmd.renderTargetViewId;
+}
+
+static void draw_triangle_map_gem(struct vmw_svga_device *mdevice,
+ struct vmw_svga_device *device, int32 cid)
+{
+ struct vmw_default_objects objects;
+ void *ptr;
+ bool save_status;
+ int fd, imported_handle, gem_handle;
+ uint64_t gem_size;
+
+ gem_handle = kmstest_dumb_create(mdevice->drm_fd,
+ vmw_default_rect_size.width,
+ vmw_default_rect_size.height, 32, NULL,
+ &gem_size);
+ fd = prime_handle_to_fd(mdevice->drm_fd, gem_handle);
+ imported_handle = prime_fd_to_handle(device->drm_fd, fd);
+
+ vmw_create_default_objects(device, cid, &objects,
+ &vmw_default_rect_size);
+ replace_with_prime_rt(device, cid, fd, imported_handle, &objects,
+ &vmw_default_rect_size);
+ vmw_triangle_draw(device, cid, &objects,
+ vmw_triangle_draw_flags_sync |
+ vmw_triangle_draw_flags_readback);
+
+ ptr = kmstest_dumb_map_buffer(mdevice->drm_fd, gem_handle, gem_size,
+ PROT_READ);
+
+ save_status = vmw_save_data_as_png(objects.color_rt, ptr,
+ "vmw_prime_tri1.png");
+ igt_assert(save_status);
+
+ munmap(ptr, gem_size);
+
+ vmw_destroy_default_objects(device, &objects);
+ kmstest_dumb_destroy(mdevice->drm_fd, gem_handle);
+}
+
+static void draw_triangle_map_dmabuf(struct vmw_svga_device *mdevice,
+ struct vmw_svga_device *device, int32 cid)
+{
+ struct vmw_default_objects objects;
+ void *ptr;
+ bool save_status;
+ int fd, imported_handle, gem_handle;
+ uint64_t gem_size;
+
+ gem_handle = kmstest_dumb_create(mdevice->drm_fd,
+ vmw_default_rect_size.width,
+ vmw_default_rect_size.height, 32, NULL,
+ &gem_size);
+ fd = prime_handle_to_fd_for_mmap(mdevice->drm_fd, gem_handle);
+ kmstest_dumb_destroy(mdevice->drm_fd, gem_handle);
+ imported_handle = prime_fd_to_handle(device->drm_fd, fd);
+
+ vmw_create_default_objects(device, cid, &objects,
+ &vmw_default_rect_size);
+ replace_with_prime_rt(device, cid, fd, imported_handle, &objects,
+ &vmw_default_rect_size);
+ vmw_triangle_draw(device, cid, &objects,
+ vmw_triangle_draw_flags_sync |
+ vmw_triangle_draw_flags_readback);
+
+ ptr = mmap(NULL, gem_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
+
+ save_status = vmw_save_data_as_png(objects.color_rt, ptr,
+ "vmw_prime_tri2.png");
+ igt_assert(save_status);
+
+ munmap(ptr, gem_size);
+ close(fd);
+
+ vmw_destroy_default_objects(device, &objects);
+}
+
+typedef struct {
+ struct vmw_svga_device mdevice;
+ struct vmw_svga_device rdevice;
+ int32 cid;
+ igt_display_t display;
+ struct igt_fb fb;
+ struct vmw_surface *fb_surface;
+ igt_output_t *output;
+ igt_plane_t *primary;
+ enum pipe pipe;
+ igt_crc_t reference_tri_crc;
+} gpu_process_t;
+
+static void cleanup_crtc(gpu_process_t *gpu)
+{
+ igt_display_t *display = &gpu->display;
+ igt_output_t *output = gpu->output;
+
+ igt_plane_set_fb(gpu->primary, NULL);
+
+ igt_output_set_pipe(output, PIPE_ANY);
+ igt_display_commit(display);
+
+ igt_remove_fb(gpu->mdevice.drm_fd, &gpu->fb);
+ if (gpu->fb_surface) {
+ vmw_ioctl_surface_unref(gpu->mdevice.drm_fd, gpu->fb_surface);
+ gpu->fb_surface = NULL;
+ }
+}
+
+static void prepare_crtc(gpu_process_t *gpu)
+{
+ igt_display_t *display = &gpu->display;
+ igt_output_t *output = gpu->output;
+ drmModeModeInfo *mode;
+ int ret;
+
+ /* select the pipe we want to use */
+ igt_output_set_pipe(output, gpu->pipe);
+
+ mode = igt_output_get_mode(output);
+
+ /* create a white fb and flip to it */
+ igt_create_color_fb(gpu->mdevice.drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_LINEAR, 1.0,
+ 1.0, 1.0, &gpu->fb);
+
+ gpu->primary =
+ igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+
+ igt_plane_set_fb(gpu->primary, &gpu->fb);
+ ret = igt_display_commit(display);
+ igt_assert(ret == 0);
+}
+
+static void prepare_crtc_surface(gpu_process_t *gpu)
+{
+ igt_display_t *display = &gpu->display;
+ igt_output_t *output = gpu->output;
+ drmModeModeInfo *mode;
+ int ret;
+ int prime_fd;
+
+ /* select the pipe we want to use */
+ igt_output_set_pipe(output, gpu->pipe);
+
+ mode = igt_output_get_mode(output);
+
+ /* create a white fb and flip to it */
+ igt_create_color_fb(gpu->mdevice.drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_LINEAR, 1.0,
+ 1.0, 1.0, &gpu->fb);
+ do_or_die(drmModeRmFB(gpu->mdevice.drm_fd, gpu->fb.fb_id));
+
+ prime_fd = prime_handle_to_fd(gpu->mdevice.drm_fd, gpu->fb.gem_handle);
+ gpu->fb_surface = vmw_ioctl_surface_ref(
+ gpu->mdevice.drm_fd, prime_fd, DRM_VMW_HANDLE_PRIME);
+ close(prime_fd);
+
+ do_or_die(__kms_addfb(gpu->fb.fd, gpu->fb_surface->base.handle,
+ gpu->fb.width, gpu->fb.height, gpu->fb.drm_format,
+ gpu->fb.modifier, gpu->fb.strides,
+ gpu->fb.offsets, gpu->fb.num_planes, 0,
+ &gpu->fb.fb_id));
+
+ gpu->primary =
+ igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+
+ igt_plane_set_fb(gpu->primary, &gpu->fb);
+ ret = igt_display_commit(display);
+ igt_assert(ret == 0);
+}
+
+static void run_renderer(struct vmw_svga_device *device, int prime_fd, int cid,
+ int fb_size, int width, int height,
+ uint32_t draw_flags)
+{
+ struct vmw_default_objects objects;
+ int imported_handle;
+ SVGA3dSize rt_size = { 0 };
+
+ rt_size.width = width;
+ rt_size.height = height;
+ rt_size.depth = 1;
+
+ imported_handle = prime_fd_to_handle(device->drm_fd, prime_fd);
+
+ vmw_create_default_objects(device, cid, &objects, &rt_size);
+ replace_with_prime_rt(device, cid, prime_fd, imported_handle, &objects,
+ &rt_size);
+ vmw_triangle_draw(device, cid, &objects, draw_flags);
+
+ vmw_destroy_default_objects(device, &objects);
+}
+
+static void draw_triangle_3d(gpu_process_t *gpu, uint32_t draw_flags)
+{
+ igt_display_t *display = &gpu->display;
+ igt_output_t *output;
+ enum pipe pipe;
+ igt_pipe_crc_t *pipe_crc;
+ igt_crc_t blank_crc, tri_crc;
+ char *blank_crc_str, *tri_crc_str;
+ bool crc_equal;
+
+ for_each_pipe_with_valid_output(display, pipe, output)
+ {
+ int prime_fd;
+
+ gpu->output = output;
+ gpu->pipe = pipe;
+
+ prepare_crtc(gpu);
+ pipe_crc = igt_pipe_crc_new(gpu->mdevice.drm_fd, pipe,
+ IGT_PIPE_CRC_SOURCE_AUTO);
+ igt_pipe_crc_collect_crc(pipe_crc, &blank_crc);
+
+ prime_fd = prime_handle_to_fd_for_mmap(gpu->mdevice.drm_fd,
+ gpu->fb.gem_handle);
+ igt_skip_on(prime_fd == -1 && errno == EINVAL);
+
+ igt_fork(renderer_no, 1)
+ {
+ run_renderer(&gpu->rdevice, prime_fd, gpu->cid,
+ gpu->fb.size, gpu->fb.width,
+ gpu->fb.height, draw_flags);
+ }
+ igt_waitchildren();
+
+ igt_plane_set_fb(gpu->primary, &gpu->fb);
+ igt_display_commit(display);
+ igt_pipe_crc_collect_crc(pipe_crc, &tri_crc);
+ blank_crc_str = igt_crc_to_string(&blank_crc);
+ tri_crc_str = igt_crc_to_string(&tri_crc);
+
+ igt_debug("Blank crc = '%s', tri = '%s\n'", blank_crc_str,
+ tri_crc_str);
+ crc_equal = igt_check_crc_equal(&blank_crc, &tri_crc);
+ igt_assert_f(
+ !crc_equal,
+ "Blank and rendered triangle CRCs should be different.\n");
+ if (draw_flags == (vmw_triangle_draw_flags_sync |
+ vmw_triangle_draw_flags_readback)) {
+ memcpy(&gpu->reference_tri_crc, &tri_crc,
+ sizeof(gpu->reference_tri_crc));
+ } else if (gpu->reference_tri_crc.has_valid_frame) {
+ igt_assert_crc_equal(&gpu->reference_tri_crc, &tri_crc);
+ }
+
+ igt_debug_wait_for_keypress("paint");
+
+ close(prime_fd);
+ igt_pipe_crc_free(pipe_crc);
+ cleanup_crtc(gpu);
+ free(blank_crc_str);
+ free(tri_crc_str);
+ /* once is enough */
+ return;
+ }
+
+ igt_skip("no valid crtc/connector combinations found\n");
+}
+
+static void draw_dumb_buffer(gpu_process_t *gpu)
+{
+ igt_display_t *display = &gpu->display;
+ igt_output_t *output;
+ enum pipe pipe;
+ igt_pipe_crc_t *pipe_crc;
+ igt_crc_t blank_crc, red_crc, blue_crc, tri_crc, red2_crc;
+ char *blank_crc_str, *red_crc_str, *red2_crc_str, *blue_crc_str,
+ *tri_crc_str;
+ bool crc_equal;
+ cairo_t *cr;
+ struct vmw_default_objects objects = { 0 };
+ int32_t cid = vmw_ioctl_context_create(gpu->mdevice.drm_fd);
+
+ for_each_pipe_with_valid_output(display, pipe, output)
+ {
+ gpu->output = output;
+ gpu->pipe = pipe;
+
+ prepare_crtc_surface(gpu);
+ pipe_crc = igt_pipe_crc_new(gpu->mdevice.drm_fd, pipe,
+ IGT_PIPE_CRC_SOURCE_AUTO);
+ igt_pipe_crc_collect_crc(pipe_crc, &blank_crc);
+
+ cr = igt_get_cairo_ctx(gpu->mdevice.drm_fd, &gpu->fb);
+ igt_paint_color(cr, 0, 0, gpu->fb.width, gpu->fb.height, 1.0, 0,
+ 0);
+ igt_put_cairo_ctx(cr);
+ igt_plane_set_fb(gpu->primary, &gpu->fb);
+ igt_display_commit(display);
+ igt_pipe_crc_collect_crc(pipe_crc, &red_crc);
+
+ cr = igt_get_cairo_ctx(gpu->mdevice.drm_fd, &gpu->fb);
+ igt_paint_color(cr, 0, 0, gpu->fb.width, gpu->fb.height, 0, 0,
+ 1.0);
+ igt_put_cairo_ctx(cr);
+ igt_plane_set_fb(gpu->primary, &gpu->fb);
+ igt_display_commit(display);
+ igt_pipe_crc_collect_crc(pipe_crc, &blue_crc);
+
+ {
+ const SVGA3dSize size = { gpu->fb.width, gpu->fb.height,
+ 1 };
+ vmw_create_default_objects(&gpu->mdevice, cid, &objects,
+ &size);
+ replace_with_surface(&gpu->mdevice, cid,
+ gpu->fb_surface, &objects, &size);
+ vmw_triangle_draw(&gpu->mdevice, cid, &objects, 0);
+ }
+ igt_plane_set_fb(gpu->primary, &gpu->fb);
+ igt_display_commit(display);
+ igt_pipe_crc_collect_crc(pipe_crc, &tri_crc);
+ igt_debug_wait_for_keypress("paint");
+
+ cr = igt_get_cairo_ctx(gpu->mdevice.drm_fd, &gpu->fb);
+ igt_paint_color(cr, 0, 0, gpu->fb.width, gpu->fb.height, 1.0, 0,
+ 0);
+ igt_put_cairo_ctx(cr);
+ igt_plane_set_fb(gpu->primary, &gpu->fb);
+ igt_display_commit(display);
+ igt_pipe_crc_collect_crc(pipe_crc, &red2_crc);
+
+ blank_crc_str = igt_crc_to_string(&blank_crc);
+ red_crc_str = igt_crc_to_string(&red_crc);
+ red2_crc_str = igt_crc_to_string(&red2_crc);
+ blue_crc_str = igt_crc_to_string(&blue_crc);
+ tri_crc_str = igt_crc_to_string(&tri_crc);
+
+ igt_debug(
+ "Blank crc = '%s', red = '%s', red2 = '%s', blue = '%s', tri = '%s'\n",
+ blank_crc_str, red_crc_str, red2_crc_str, blue_crc_str,
+ tri_crc_str);
+ crc_equal = igt_check_crc_equal(&blank_crc, &red_crc);
+ igt_assert_f(!crc_equal,
+ "Blank and red CRCs should be different.\n");
+ crc_equal = igt_check_crc_equal(&red_crc, &blue_crc);
+ igt_assert_f(!crc_equal,
+ "Red and blue CRCs should be different.\n");
+ crc_equal = igt_check_crc_equal(&red_crc, &tri_crc);
+ igt_assert_f(!crc_equal,
+ "Red and tri CRCs should be different.\n");
+ crc_equal = igt_check_crc_equal(&blue_crc, &tri_crc);
+ igt_assert_f(!crc_equal,
+ "Blue and tri CRCs should be different.\n");
+
+ crc_equal = igt_check_crc_equal(&red_crc, &red2_crc);
+ igt_assert_f(crc_equal, "Red CRCs should be the same.\n");
+
+ vmw_destroy_default_objects(&gpu->mdevice, &objects);
+ vmw_ioctl_context_destroy(gpu->mdevice.drm_fd, cid);
+ igt_pipe_crc_free(pipe_crc);
+ cleanup_crtc(gpu);
+ free(blank_crc_str);
+ free(red_crc_str);
+ free(blue_crc_str);
+ /* once is enough */
+ return;
+ }
+}
+
+static const uint32_t pattern[] = {
+ 0xff000000, 0x00ff0000, 0x0000ff00, 0x000000ff, 0x000000ff, 0x0000ff00,
+ 0x00ff0000, 0xff000000, 0x00ffff00, 0xff0000ff, 0x00ff00ff, 0xff00ff00,
+ 0xff0000ff, 0x00ff00ff, 0x00ffff00, 0xff00ff00
+};
+
+static void test_vgem(gpu_process_t *gpu, int vgem_fd)
+{
+ int dma_buf_fd;
+ uint32_t *ptr;
+ struct dumb_buffer {
+ uint32_t handle;
+ uint32_t stride;
+ uint64_t size;
+ } vgem_buffer;
+ uint32_t vmw_buffer_handle;
+
+ vgem_buffer.handle = kmstest_dumb_create(
+ vgem_fd, 64, 64, 32, &vgem_buffer.stride, &vgem_buffer.size);
+ ptr = kmstest_dumb_map_buffer(vgem_fd, vgem_buffer.handle,
+ vgem_buffer.size, PROT_WRITE);
+ igt_assert(ptr != MAP_FAILED);
+ igt_assert(ptr != NULL);
+ igt_assert(vgem_buffer.size > sizeof(pattern));
+ memcpy(ptr, pattern, sizeof(pattern));
+ munmap(ptr, vgem_buffer.size);
+
+ dma_buf_fd = prime_handle_to_fd_for_mmap(vgem_fd, vgem_buffer.handle);
+
+ /* Skip if DRM_RDWR is not supported */
+ igt_skip_on(errno == EINVAL);
+
+ /* Check correctness of map using write protection (PROT_WRITE) */
+ ptr = mmap(NULL, vgem_buffer.size, PROT_READ, MAP_SHARED, dma_buf_fd,
+ 0);
+ igt_assert(ptr != MAP_FAILED);
+
+ /* Check pattern correctness */
+ igt_assert(memcmp(ptr, pattern, sizeof(pattern)) == 0);
+
+ munmap(ptr, vgem_buffer.size);
+ close(dma_buf_fd);
+
+ dma_buf_fd = prime_handle_to_fd(vgem_fd, vgem_buffer.handle);
+ vmw_buffer_handle = prime_fd_to_handle(gpu->mdevice.drm_fd, dma_buf_fd);
+ igt_assert(vmw_buffer_handle >= 0);
+ ptr = kmstest_dumb_map_buffer(gpu->mdevice.drm_fd, vmw_buffer_handle,
+ vgem_buffer.size, PROT_READ);
+ igt_assert(ptr != MAP_FAILED);
+ igt_assert(ptr != NULL);
+ igt_assert(memcmp(ptr, pattern, sizeof(pattern)) == 0);
+ munmap(ptr, vgem_buffer.size);
+ close(dma_buf_fd);
+
+ kmstest_dumb_destroy(vgem_fd, vgem_buffer.handle);
+ gem_close(gpu->mdevice.drm_fd, vmw_buffer_handle);
+}
+
+igt_main
+{
+ gpu_process_t gpu = { 0 };
+ int second_fd_vgem = -1;
+
+ igt_fixture
+ {
+ vmw_svga_device_init(&gpu.mdevice, vmw_svga_device_node_master);
+ vmw_svga_device_init(&gpu.rdevice, vmw_svga_device_node_render);
+ igt_require(gpu.mdevice.drm_fd != -1);
+ igt_require(gpu.rdevice.drm_fd != -1);
+
+ gpu.cid = vmw_ioctl_context_create(gpu.rdevice.drm_fd);
+ igt_require(gpu.cid != SVGA3D_INVALID_ID);
+
+ kmstest_set_vt_graphics_mode();
+
+ igt_require_pipe_crc(gpu.mdevice.drm_fd);
+
+ igt_display_require(&gpu.display, gpu.mdevice.drm_fd);
+ }
+
+ igt_describe("Tests prime rendering triangle with gem mmap.");
+ igt_subtest("tri-map-gem")
+ {
+ draw_triangle_map_gem(&gpu.mdevice, &gpu.rdevice, gpu.cid);
+ }
+
+ igt_describe("Tests prime rendering triangle with dmabuf mmap.");
+ igt_subtest("tri-map-dmabuf")
+ {
+ draw_triangle_map_dmabuf(&gpu.mdevice, &gpu.rdevice, gpu.cid);
+ }
+
+ igt_describe("Tests dumb buffer and fb synchronizations.");
+ igt_subtest("draw-dumb-buffer")
+ {
+ draw_dumb_buffer(&gpu);
+ }
+
+ igt_describe(
+ "Tests synchronous/readback prime rendering triangle while buffer bound to fb");
+ igt_subtest("buffer-surface-fb-sharing-sync-readback")
+ {
+ draw_triangle_3d(&gpu,
+ vmw_triangle_draw_flags_sync |
+ vmw_triangle_draw_flags_readback);
+ }
+
+ igt_describe(
+ "Tests synchronous prime rendering triangle while buffer bound to fb");
+ igt_subtest("buffer-surface-fb-sharing-sync")
+ {
+ draw_triangle_3d(&gpu, vmw_triangle_draw_flags_sync);
+ }
+
+ igt_describe("Tests prime rendering triangle while buffer bound to fb");
+ igt_subtest("buffer-surface-fb-sharing")
+ {
+ draw_triangle_3d(&gpu, vmw_triangle_draw_flags_none);
+ }
+
+ igt_describe("VGEM subtests");
+ igt_subtest_group
+ {
+ igt_fixture
+ {
+ second_fd_vgem =
+ __drm_open_driver_another(1, DRIVER_VGEM);
+ igt_require(second_fd_vgem >= 0);
+ }
+
+ igt_describe(
+ "Make a dumb color buffer, export to another device and"
+ " compare the CRCs with a buffer native to that device");
+ igt_subtest("basic-vgem")
+ {
+ test_vgem(&gpu, second_fd_vgem);
+ }
+
+ igt_fixture
+ {
+ drm_close_driver(second_fd_vgem);
+ }
+ }
+
+ igt_fixture
+ {
+ vmw_ioctl_context_destroy(gpu.rdevice.drm_fd, gpu.cid);
+ igt_display_fini(&gpu.display);
+ vmw_svga_device_fini(&gpu.rdevice);
+ vmw_svga_device_fini(&gpu.mdevice);
+ }
+}
--
2.40.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH i-g-t v3 3/4] tests/vmwgfx: Add a prime test
2024-06-28 19:02 ` [PATCH i-g-t v3 3/4] tests/vmwgfx: Add a prime test Zack Rusin
@ 2024-07-26 19:07 ` Kamil Konieczny
0 siblings, 0 replies; 12+ messages in thread
From: Kamil Konieczny @ 2024-07-26 19:07 UTC (permalink / raw)
To: igt-dev; +Cc: Zack Rusin, ian.forbes, martin.krastev, maaz.mombasawala
Hi Zack,
On 2024-06-28 at 15:02:42 -0400, Zack Rusin wrote:
> Add a test that check for various dma-buf/prime related issues that might
> show up on vmwgfx.
>
> Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
> ---
> tests/vmwgfx/meson.build | 7 +-
> tests/vmwgfx/vmw_prime.c | 599 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 603 insertions(+), 3 deletions(-)
> create mode 100644 tests/vmwgfx/vmw_prime.c
>
> diff --git a/tests/vmwgfx/meson.build b/tests/vmwgfx/meson.build
> index 073905f0a..28163d0f1 100644
> --- a/tests/vmwgfx/meson.build
> +++ b/tests/vmwgfx/meson.build
> @@ -1,10 +1,11 @@
>
> vmwgfx_progs = [
> - 'vmw_tri',
> 'vmw_execution_buffer',
> - 'vmw_surface_copy',
> 'vmw_mob_stress',
> - 'vmw_ref_count'
> + 'vmw_prime',
> + 'vmw_ref_count',
> + 'vmw_surface_copy',
> + 'vmw_tri',
> ]
> vmwgfx_deps = test_deps
>
> diff --git a/tests/vmwgfx/vmw_prime.c b/tests/vmwgfx/vmw_prime.c
> new file mode 100644
> index 000000000..891628b9b
> --- /dev/null
> +++ b/tests/vmwgfx/vmw_prime.c
> @@ -0,0 +1,599 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024 Broadcom. All Rights Reserved. The term
> + * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
> + */
As this is new test this licence is ok.
> +
> +#include "igt_kms.h"
> +#include "igt_vmwgfx.h"
> +
> +IGT_TEST_DESCRIPTION(
> + "Check whether basic DRM prime and dma-buf work correctly.");
Please write it in one line, also use script checkpatch.pl from
Linux kernel to spot some problems, see also CONTRIBUTE.md for
soem useful options. Btw some warnigs as CamelCase could be
ignored but that tool could spot few problems.
With that addressed
Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Btw could someone from your team do a review?
Regards,
Kamil
> +
> +static void replace_with_prime_rt(struct vmw_svga_device *device,
> + int32 context_id,
> + uint32 prime_fd,
> + uint32 buffer_handle,
> + struct vmw_default_objects *objects,
> + const SVGA3dSize *rt_size)
> +{
> + struct vmw_execbuf *cmd_buf;
> + SVGA3dRenderTargetViewDesc rtv_desc = { 0 };
> + SVGA3dCmdDXDefineRenderTargetView rt_view_define_cmd = { 0 };
> + SVGA3dCmdDXDestroyRenderTargetView rt_view_cmd = {
> + .renderTargetViewId = objects->color_rt_id
> + };
> +
> + vmw_ioctl_surface_unref(device->drm_fd, objects->color_rt);
> + objects->color_rt = vmw_ioctl_surface_ref(device->drm_fd, prime_fd, DRM_VMW_HANDLE_PRIME);
> +
> + cmd_buf = vmw_execbuf_create(device->drm_fd, context_id);
> +
> + rtv_desc.tex.arraySize = 1;
> + rtv_desc.tex.firstArraySlice = 0;
> + rtv_desc.tex.mipSlice = 0;
> + vmw_bitvector_find_next_bit(device->rt_view_bv,
> + &rt_view_define_cmd.renderTargetViewId);
> + rt_view_define_cmd.sid = objects->color_rt->base.handle;
> + rt_view_define_cmd.format = SVGA3D_B8G8R8X8_UNORM;
> + rt_view_define_cmd.resourceDimension = SVGA3D_RESOURCE_TEXTURE2D;
> + rt_view_define_cmd.desc = rtv_desc;
> + vmw_execbuf_append(cmd_buf, SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW,
> + &rt_view_cmd, sizeof(rt_view_cmd), NULL, 0);
> + vmw_execbuf_append(cmd_buf, SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW,
> + &rt_view_define_cmd, sizeof(rt_view_define_cmd),
> + NULL, 0);
> + vmw_execbuf_submit(cmd_buf, NULL);
> + vmw_execbuf_destroy(cmd_buf);
> +
> + vmw_bitvector_free_bit(device->rt_view_bv, objects->color_rt_id);
> + objects->color_rt_id = rt_view_define_cmd.renderTargetViewId;
> +}
> +
> +static void replace_with_surface(struct vmw_svga_device *device,
> + int32 context_id, struct vmw_surface *surf,
> + struct vmw_default_objects *objects,
> + const SVGA3dSize *rt_size)
> +{
> + struct vmw_execbuf *cmd_buf;
> + SVGA3dRenderTargetViewDesc rtv_desc = { 0 };
> + SVGA3dCmdDXDefineRenderTargetView rt_view_define_cmd = { 0 };
> + SVGA3dCmdDXDestroyRenderTargetView rt_view_cmd = {
> + .renderTargetViewId = objects->color_rt_id
> + };
> +
> + vmw_ioctl_surface_unref(device->drm_fd, objects->color_rt);
> + objects->color_rt = vmw_ioctl_surface_ref(device->drm_fd, surf->base.handle, DRM_VMW_HANDLE_LEGACY);
> +
> + cmd_buf = vmw_execbuf_create(device->drm_fd, context_id);
> +
> + rtv_desc.tex.arraySize = 1;
> + rtv_desc.tex.firstArraySlice = 0;
> + rtv_desc.tex.mipSlice = 0;
> + vmw_bitvector_find_next_bit(device->rt_view_bv,
> + &rt_view_define_cmd.renderTargetViewId);
> + rt_view_define_cmd.sid = objects->color_rt->base.handle;
> + rt_view_define_cmd.format = SVGA3D_B8G8R8X8_UNORM;
> + rt_view_define_cmd.resourceDimension = SVGA3D_RESOURCE_TEXTURE2D;
> + rt_view_define_cmd.desc = rtv_desc;
> + vmw_execbuf_append(cmd_buf, SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW,
> + &rt_view_cmd, sizeof(rt_view_cmd), NULL, 0);
> + vmw_execbuf_append(cmd_buf, SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW,
> + &rt_view_define_cmd, sizeof(rt_view_define_cmd),
> + NULL, 0);
> + vmw_execbuf_submit(cmd_buf, NULL);
> + vmw_execbuf_destroy(cmd_buf);
> +
> + vmw_bitvector_free_bit(device->rt_view_bv, objects->color_rt_id);
> + objects->color_rt_id = rt_view_define_cmd.renderTargetViewId;
> +}
> +
> +static void draw_triangle_map_gem(struct vmw_svga_device *mdevice,
> + struct vmw_svga_device *device, int32 cid)
> +{
> + struct vmw_default_objects objects;
> + void *ptr;
> + bool save_status;
> + int fd, imported_handle, gem_handle;
> + uint64_t gem_size;
> +
> + gem_handle = kmstest_dumb_create(mdevice->drm_fd,
> + vmw_default_rect_size.width,
> + vmw_default_rect_size.height, 32, NULL,
> + &gem_size);
> + fd = prime_handle_to_fd(mdevice->drm_fd, gem_handle);
> + imported_handle = prime_fd_to_handle(device->drm_fd, fd);
> +
> + vmw_create_default_objects(device, cid, &objects,
> + &vmw_default_rect_size);
> + replace_with_prime_rt(device, cid, fd, imported_handle, &objects,
> + &vmw_default_rect_size);
> + vmw_triangle_draw(device, cid, &objects,
> + vmw_triangle_draw_flags_sync |
> + vmw_triangle_draw_flags_readback);
> +
> + ptr = kmstest_dumb_map_buffer(mdevice->drm_fd, gem_handle, gem_size,
> + PROT_READ);
> +
> + save_status = vmw_save_data_as_png(objects.color_rt, ptr,
> + "vmw_prime_tri1.png");
> + igt_assert(save_status);
> +
> + munmap(ptr, gem_size);
> +
> + vmw_destroy_default_objects(device, &objects);
> + kmstest_dumb_destroy(mdevice->drm_fd, gem_handle);
> +}
> +
> +static void draw_triangle_map_dmabuf(struct vmw_svga_device *mdevice,
> + struct vmw_svga_device *device, int32 cid)
> +{
> + struct vmw_default_objects objects;
> + void *ptr;
> + bool save_status;
> + int fd, imported_handle, gem_handle;
> + uint64_t gem_size;
> +
> + gem_handle = kmstest_dumb_create(mdevice->drm_fd,
> + vmw_default_rect_size.width,
> + vmw_default_rect_size.height, 32, NULL,
> + &gem_size);
> + fd = prime_handle_to_fd_for_mmap(mdevice->drm_fd, gem_handle);
> + kmstest_dumb_destroy(mdevice->drm_fd, gem_handle);
> + imported_handle = prime_fd_to_handle(device->drm_fd, fd);
> +
> + vmw_create_default_objects(device, cid, &objects,
> + &vmw_default_rect_size);
> + replace_with_prime_rt(device, cid, fd, imported_handle, &objects,
> + &vmw_default_rect_size);
> + vmw_triangle_draw(device, cid, &objects,
> + vmw_triangle_draw_flags_sync |
> + vmw_triangle_draw_flags_readback);
> +
> + ptr = mmap(NULL, gem_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
> +
> + save_status = vmw_save_data_as_png(objects.color_rt, ptr,
> + "vmw_prime_tri2.png");
> + igt_assert(save_status);
> +
> + munmap(ptr, gem_size);
> + close(fd);
> +
> + vmw_destroy_default_objects(device, &objects);
> +}
> +
> +typedef struct {
> + struct vmw_svga_device mdevice;
> + struct vmw_svga_device rdevice;
> + int32 cid;
> + igt_display_t display;
> + struct igt_fb fb;
> + struct vmw_surface *fb_surface;
> + igt_output_t *output;
> + igt_plane_t *primary;
> + enum pipe pipe;
> + igt_crc_t reference_tri_crc;
> +} gpu_process_t;
> +
> +static void cleanup_crtc(gpu_process_t *gpu)
> +{
> + igt_display_t *display = &gpu->display;
> + igt_output_t *output = gpu->output;
> +
> + igt_plane_set_fb(gpu->primary, NULL);
> +
> + igt_output_set_pipe(output, PIPE_ANY);
> + igt_display_commit(display);
> +
> + igt_remove_fb(gpu->mdevice.drm_fd, &gpu->fb);
> + if (gpu->fb_surface) {
> + vmw_ioctl_surface_unref(gpu->mdevice.drm_fd, gpu->fb_surface);
> + gpu->fb_surface = NULL;
> + }
> +}
> +
> +static void prepare_crtc(gpu_process_t *gpu)
> +{
> + igt_display_t *display = &gpu->display;
> + igt_output_t *output = gpu->output;
> + drmModeModeInfo *mode;
> + int ret;
> +
> + /* select the pipe we want to use */
> + igt_output_set_pipe(output, gpu->pipe);
> +
> + mode = igt_output_get_mode(output);
> +
> + /* create a white fb and flip to it */
> + igt_create_color_fb(gpu->mdevice.drm_fd, mode->hdisplay, mode->vdisplay,
> + DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_LINEAR, 1.0,
> + 1.0, 1.0, &gpu->fb);
> +
> + gpu->primary =
> + igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
> +
> + igt_plane_set_fb(gpu->primary, &gpu->fb);
> + ret = igt_display_commit(display);
> + igt_assert(ret == 0);
> +}
> +
> +static void prepare_crtc_surface(gpu_process_t *gpu)
> +{
> + igt_display_t *display = &gpu->display;
> + igt_output_t *output = gpu->output;
> + drmModeModeInfo *mode;
> + int ret;
> + int prime_fd;
> +
> + /* select the pipe we want to use */
> + igt_output_set_pipe(output, gpu->pipe);
> +
> + mode = igt_output_get_mode(output);
> +
> + /* create a white fb and flip to it */
> + igt_create_color_fb(gpu->mdevice.drm_fd, mode->hdisplay, mode->vdisplay,
> + DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_LINEAR, 1.0,
> + 1.0, 1.0, &gpu->fb);
> + do_or_die(drmModeRmFB(gpu->mdevice.drm_fd, gpu->fb.fb_id));
> +
> + prime_fd = prime_handle_to_fd(gpu->mdevice.drm_fd, gpu->fb.gem_handle);
> + gpu->fb_surface = vmw_ioctl_surface_ref(
> + gpu->mdevice.drm_fd, prime_fd, DRM_VMW_HANDLE_PRIME);
> + close(prime_fd);
> +
> + do_or_die(__kms_addfb(gpu->fb.fd, gpu->fb_surface->base.handle,
> + gpu->fb.width, gpu->fb.height, gpu->fb.drm_format,
> + gpu->fb.modifier, gpu->fb.strides,
> + gpu->fb.offsets, gpu->fb.num_planes, 0,
> + &gpu->fb.fb_id));
> +
> + gpu->primary =
> + igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
> +
> + igt_plane_set_fb(gpu->primary, &gpu->fb);
> + ret = igt_display_commit(display);
> + igt_assert(ret == 0);
> +}
> +
> +static void run_renderer(struct vmw_svga_device *device, int prime_fd, int cid,
> + int fb_size, int width, int height,
> + uint32_t draw_flags)
> +{
> + struct vmw_default_objects objects;
> + int imported_handle;
> + SVGA3dSize rt_size = { 0 };
> +
> + rt_size.width = width;
> + rt_size.height = height;
> + rt_size.depth = 1;
> +
> + imported_handle = prime_fd_to_handle(device->drm_fd, prime_fd);
> +
> + vmw_create_default_objects(device, cid, &objects, &rt_size);
> + replace_with_prime_rt(device, cid, prime_fd, imported_handle, &objects,
> + &rt_size);
> + vmw_triangle_draw(device, cid, &objects, draw_flags);
> +
> + vmw_destroy_default_objects(device, &objects);
> +}
> +
> +static void draw_triangle_3d(gpu_process_t *gpu, uint32_t draw_flags)
> +{
> + igt_display_t *display = &gpu->display;
> + igt_output_t *output;
> + enum pipe pipe;
> + igt_pipe_crc_t *pipe_crc;
> + igt_crc_t blank_crc, tri_crc;
> + char *blank_crc_str, *tri_crc_str;
> + bool crc_equal;
> +
> + for_each_pipe_with_valid_output(display, pipe, output)
> + {
> + int prime_fd;
> +
> + gpu->output = output;
> + gpu->pipe = pipe;
> +
> + prepare_crtc(gpu);
> + pipe_crc = igt_pipe_crc_new(gpu->mdevice.drm_fd, pipe,
> + IGT_PIPE_CRC_SOURCE_AUTO);
> + igt_pipe_crc_collect_crc(pipe_crc, &blank_crc);
> +
> + prime_fd = prime_handle_to_fd_for_mmap(gpu->mdevice.drm_fd,
> + gpu->fb.gem_handle);
> + igt_skip_on(prime_fd == -1 && errno == EINVAL);
> +
> + igt_fork(renderer_no, 1)
> + {
> + run_renderer(&gpu->rdevice, prime_fd, gpu->cid,
> + gpu->fb.size, gpu->fb.width,
> + gpu->fb.height, draw_flags);
> + }
> + igt_waitchildren();
> +
> + igt_plane_set_fb(gpu->primary, &gpu->fb);
> + igt_display_commit(display);
> + igt_pipe_crc_collect_crc(pipe_crc, &tri_crc);
> + blank_crc_str = igt_crc_to_string(&blank_crc);
> + tri_crc_str = igt_crc_to_string(&tri_crc);
> +
> + igt_debug("Blank crc = '%s', tri = '%s\n'", blank_crc_str,
> + tri_crc_str);
> + crc_equal = igt_check_crc_equal(&blank_crc, &tri_crc);
> + igt_assert_f(
> + !crc_equal,
> + "Blank and rendered triangle CRCs should be different.\n");
> + if (draw_flags == (vmw_triangle_draw_flags_sync |
> + vmw_triangle_draw_flags_readback)) {
> + memcpy(&gpu->reference_tri_crc, &tri_crc,
> + sizeof(gpu->reference_tri_crc));
> + } else if (gpu->reference_tri_crc.has_valid_frame) {
> + igt_assert_crc_equal(&gpu->reference_tri_crc, &tri_crc);
> + }
> +
> + igt_debug_wait_for_keypress("paint");
> +
> + close(prime_fd);
> + igt_pipe_crc_free(pipe_crc);
> + cleanup_crtc(gpu);
> + free(blank_crc_str);
> + free(tri_crc_str);
> + /* once is enough */
> + return;
> + }
> +
> + igt_skip("no valid crtc/connector combinations found\n");
> +}
> +
> +static void draw_dumb_buffer(gpu_process_t *gpu)
> +{
> + igt_display_t *display = &gpu->display;
> + igt_output_t *output;
> + enum pipe pipe;
> + igt_pipe_crc_t *pipe_crc;
> + igt_crc_t blank_crc, red_crc, blue_crc, tri_crc, red2_crc;
> + char *blank_crc_str, *red_crc_str, *red2_crc_str, *blue_crc_str,
> + *tri_crc_str;
> + bool crc_equal;
> + cairo_t *cr;
> + struct vmw_default_objects objects = { 0 };
> + int32_t cid = vmw_ioctl_context_create(gpu->mdevice.drm_fd);
> +
> + for_each_pipe_with_valid_output(display, pipe, output)
> + {
> + gpu->output = output;
> + gpu->pipe = pipe;
> +
> + prepare_crtc_surface(gpu);
> + pipe_crc = igt_pipe_crc_new(gpu->mdevice.drm_fd, pipe,
> + IGT_PIPE_CRC_SOURCE_AUTO);
> + igt_pipe_crc_collect_crc(pipe_crc, &blank_crc);
> +
> + cr = igt_get_cairo_ctx(gpu->mdevice.drm_fd, &gpu->fb);
> + igt_paint_color(cr, 0, 0, gpu->fb.width, gpu->fb.height, 1.0, 0,
> + 0);
> + igt_put_cairo_ctx(cr);
> + igt_plane_set_fb(gpu->primary, &gpu->fb);
> + igt_display_commit(display);
> + igt_pipe_crc_collect_crc(pipe_crc, &red_crc);
> +
> + cr = igt_get_cairo_ctx(gpu->mdevice.drm_fd, &gpu->fb);
> + igt_paint_color(cr, 0, 0, gpu->fb.width, gpu->fb.height, 0, 0,
> + 1.0);
> + igt_put_cairo_ctx(cr);
> + igt_plane_set_fb(gpu->primary, &gpu->fb);
> + igt_display_commit(display);
> + igt_pipe_crc_collect_crc(pipe_crc, &blue_crc);
> +
> + {
> + const SVGA3dSize size = { gpu->fb.width, gpu->fb.height,
> + 1 };
> + vmw_create_default_objects(&gpu->mdevice, cid, &objects,
> + &size);
> + replace_with_surface(&gpu->mdevice, cid,
> + gpu->fb_surface, &objects, &size);
> + vmw_triangle_draw(&gpu->mdevice, cid, &objects, 0);
> + }
> + igt_plane_set_fb(gpu->primary, &gpu->fb);
> + igt_display_commit(display);
> + igt_pipe_crc_collect_crc(pipe_crc, &tri_crc);
> + igt_debug_wait_for_keypress("paint");
> +
> + cr = igt_get_cairo_ctx(gpu->mdevice.drm_fd, &gpu->fb);
> + igt_paint_color(cr, 0, 0, gpu->fb.width, gpu->fb.height, 1.0, 0,
> + 0);
> + igt_put_cairo_ctx(cr);
> + igt_plane_set_fb(gpu->primary, &gpu->fb);
> + igt_display_commit(display);
> + igt_pipe_crc_collect_crc(pipe_crc, &red2_crc);
> +
> + blank_crc_str = igt_crc_to_string(&blank_crc);
> + red_crc_str = igt_crc_to_string(&red_crc);
> + red2_crc_str = igt_crc_to_string(&red2_crc);
> + blue_crc_str = igt_crc_to_string(&blue_crc);
> + tri_crc_str = igt_crc_to_string(&tri_crc);
> +
> + igt_debug(
> + "Blank crc = '%s', red = '%s', red2 = '%s', blue = '%s', tri = '%s'\n",
> + blank_crc_str, red_crc_str, red2_crc_str, blue_crc_str,
> + tri_crc_str);
> + crc_equal = igt_check_crc_equal(&blank_crc, &red_crc);
> + igt_assert_f(!crc_equal,
> + "Blank and red CRCs should be different.\n");
> + crc_equal = igt_check_crc_equal(&red_crc, &blue_crc);
> + igt_assert_f(!crc_equal,
> + "Red and blue CRCs should be different.\n");
> + crc_equal = igt_check_crc_equal(&red_crc, &tri_crc);
> + igt_assert_f(!crc_equal,
> + "Red and tri CRCs should be different.\n");
> + crc_equal = igt_check_crc_equal(&blue_crc, &tri_crc);
> + igt_assert_f(!crc_equal,
> + "Blue and tri CRCs should be different.\n");
> +
> + crc_equal = igt_check_crc_equal(&red_crc, &red2_crc);
> + igt_assert_f(crc_equal, "Red CRCs should be the same.\n");
> +
> + vmw_destroy_default_objects(&gpu->mdevice, &objects);
> + vmw_ioctl_context_destroy(gpu->mdevice.drm_fd, cid);
> + igt_pipe_crc_free(pipe_crc);
> + cleanup_crtc(gpu);
> + free(blank_crc_str);
> + free(red_crc_str);
> + free(blue_crc_str);
> + /* once is enough */
> + return;
> + }
> +}
> +
> +static const uint32_t pattern[] = {
> + 0xff000000, 0x00ff0000, 0x0000ff00, 0x000000ff, 0x000000ff, 0x0000ff00,
> + 0x00ff0000, 0xff000000, 0x00ffff00, 0xff0000ff, 0x00ff00ff, 0xff00ff00,
> + 0xff0000ff, 0x00ff00ff, 0x00ffff00, 0xff00ff00
> +};
> +
> +static void test_vgem(gpu_process_t *gpu, int vgem_fd)
> +{
> + int dma_buf_fd;
> + uint32_t *ptr;
> + struct dumb_buffer {
> + uint32_t handle;
> + uint32_t stride;
> + uint64_t size;
> + } vgem_buffer;
> + uint32_t vmw_buffer_handle;
> +
> + vgem_buffer.handle = kmstest_dumb_create(
> + vgem_fd, 64, 64, 32, &vgem_buffer.stride, &vgem_buffer.size);
> + ptr = kmstest_dumb_map_buffer(vgem_fd, vgem_buffer.handle,
> + vgem_buffer.size, PROT_WRITE);
> + igt_assert(ptr != MAP_FAILED);
> + igt_assert(ptr != NULL);
> + igt_assert(vgem_buffer.size > sizeof(pattern));
> + memcpy(ptr, pattern, sizeof(pattern));
> + munmap(ptr, vgem_buffer.size);
> +
> + dma_buf_fd = prime_handle_to_fd_for_mmap(vgem_fd, vgem_buffer.handle);
> +
> + /* Skip if DRM_RDWR is not supported */
> + igt_skip_on(errno == EINVAL);
> +
> + /* Check correctness of map using write protection (PROT_WRITE) */
> + ptr = mmap(NULL, vgem_buffer.size, PROT_READ, MAP_SHARED, dma_buf_fd,
> + 0);
> + igt_assert(ptr != MAP_FAILED);
> +
> + /* Check pattern correctness */
> + igt_assert(memcmp(ptr, pattern, sizeof(pattern)) == 0);
> +
> + munmap(ptr, vgem_buffer.size);
> + close(dma_buf_fd);
> +
> + dma_buf_fd = prime_handle_to_fd(vgem_fd, vgem_buffer.handle);
> + vmw_buffer_handle = prime_fd_to_handle(gpu->mdevice.drm_fd, dma_buf_fd);
> + igt_assert(vmw_buffer_handle >= 0);
> + ptr = kmstest_dumb_map_buffer(gpu->mdevice.drm_fd, vmw_buffer_handle,
> + vgem_buffer.size, PROT_READ);
> + igt_assert(ptr != MAP_FAILED);
> + igt_assert(ptr != NULL);
> + igt_assert(memcmp(ptr, pattern, sizeof(pattern)) == 0);
> + munmap(ptr, vgem_buffer.size);
> + close(dma_buf_fd);
> +
> + kmstest_dumb_destroy(vgem_fd, vgem_buffer.handle);
> + gem_close(gpu->mdevice.drm_fd, vmw_buffer_handle);
> +}
> +
> +igt_main
> +{
> + gpu_process_t gpu = { 0 };
> + int second_fd_vgem = -1;
> +
> + igt_fixture
> + {
> + vmw_svga_device_init(&gpu.mdevice, vmw_svga_device_node_master);
> + vmw_svga_device_init(&gpu.rdevice, vmw_svga_device_node_render);
> + igt_require(gpu.mdevice.drm_fd != -1);
> + igt_require(gpu.rdevice.drm_fd != -1);
> +
> + gpu.cid = vmw_ioctl_context_create(gpu.rdevice.drm_fd);
> + igt_require(gpu.cid != SVGA3D_INVALID_ID);
> +
> + kmstest_set_vt_graphics_mode();
> +
> + igt_require_pipe_crc(gpu.mdevice.drm_fd);
> +
> + igt_display_require(&gpu.display, gpu.mdevice.drm_fd);
> + }
> +
> + igt_describe("Tests prime rendering triangle with gem mmap.");
> + igt_subtest("tri-map-gem")
> + {
> + draw_triangle_map_gem(&gpu.mdevice, &gpu.rdevice, gpu.cid);
> + }
> +
> + igt_describe("Tests prime rendering triangle with dmabuf mmap.");
> + igt_subtest("tri-map-dmabuf")
> + {
> + draw_triangle_map_dmabuf(&gpu.mdevice, &gpu.rdevice, gpu.cid);
> + }
> +
> + igt_describe("Tests dumb buffer and fb synchronizations.");
> + igt_subtest("draw-dumb-buffer")
> + {
> + draw_dumb_buffer(&gpu);
> + }
> +
> + igt_describe(
> + "Tests synchronous/readback prime rendering triangle while buffer bound to fb");
> + igt_subtest("buffer-surface-fb-sharing-sync-readback")
> + {
> + draw_triangle_3d(&gpu,
> + vmw_triangle_draw_flags_sync |
> + vmw_triangle_draw_flags_readback);
> + }
> +
> + igt_describe(
> + "Tests synchronous prime rendering triangle while buffer bound to fb");
> + igt_subtest("buffer-surface-fb-sharing-sync")
> + {
> + draw_triangle_3d(&gpu, vmw_triangle_draw_flags_sync);
> + }
> +
> + igt_describe("Tests prime rendering triangle while buffer bound to fb");
> + igt_subtest("buffer-surface-fb-sharing")
> + {
> + draw_triangle_3d(&gpu, vmw_triangle_draw_flags_none);
> + }
> +
> + igt_describe("VGEM subtests");
> + igt_subtest_group
> + {
> + igt_fixture
> + {
> + second_fd_vgem =
> + __drm_open_driver_another(1, DRIVER_VGEM);
> + igt_require(second_fd_vgem >= 0);
> + }
> +
> + igt_describe(
> + "Make a dumb color buffer, export to another device and"
> + " compare the CRCs with a buffer native to that device");
> + igt_subtest("basic-vgem")
> + {
> + test_vgem(&gpu, second_fd_vgem);
> + }
> +
> + igt_fixture
> + {
> + drm_close_driver(second_fd_vgem);
> + }
> + }
> +
> + igt_fixture
> + {
> + vmw_ioctl_context_destroy(gpu.rdevice.drm_fd, gpu.cid);
> + igt_display_fini(&gpu.display);
> + vmw_svga_device_fini(&gpu.rdevice);
> + vmw_svga_device_fini(&gpu.mdevice);
> + }
> +}
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH i-g-t v3 4/4] tests/vmwgfx: Fix and extend the reference counting test
2024-06-28 19:02 [PATCH i-g-t v3 0/4] Add vmwgfx prime tests Zack Rusin
` (2 preceding siblings ...)
2024-06-28 19:02 ` [PATCH i-g-t v3 3/4] tests/vmwgfx: Add a prime test Zack Rusin
@ 2024-06-28 19:02 ` Zack Rusin
2024-07-26 19:16 ` Kamil Konieczny
2024-06-28 19:31 ` ✓ CI.xeBAT: success for Add vmwgfx prime tests (rev3) Patchwork
` (2 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Zack Rusin @ 2024-06-28 19:02 UTC (permalink / raw)
To: igt-dev
Cc: ian.forbes, martin.krastev, maaz.mombasawala, kamil.konieczny,
Zack Rusin
Fix a few issues related to buffer managment in the reference counting
test. Extend it to include various prime related reference counting
issues.
Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
---
lib/igt_vmwgfx.c | 45 +++-----
lib/igt_vmwgfx.h | 30 +----
tests/vmwgfx/vmw_ref_count.c | 207 +++++++++++++++++++++++++++++------
3 files changed, 193 insertions(+), 89 deletions(-)
diff --git a/lib/igt_vmwgfx.c b/lib/igt_vmwgfx.c
index d2f699575..b62d7a326 100644
--- a/lib/igt_vmwgfx.c
+++ b/lib/igt_vmwgfx.c
@@ -1,28 +1,8 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
-/**********************************************************
- * Copyright 2021-2023 VMware, Inc.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- **********************************************************/
+/*
+ * Copyright (c) 2021-2024 Broadcom. All Rights Reserved. The term
+ * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
+ */
#include "igt_vmwgfx.h"
@@ -154,6 +134,7 @@ bool vmw_save_data_as_png(struct vmw_surface *surface, void *data,
/* Can separate this into another function as it grows */
switch (surface->params.base.format) {
case SVGA3D_R8G8B8A8_UNORM:
+ case SVGA3D_B8G8R8X8_UNORM:
format = CAIRO_FORMAT_ARGB32;
break;
default:
@@ -345,11 +326,15 @@ void vmw_ioctl_mob_close_handle(int fd, struct vmw_mob *mob)
free(mob);
}
-struct vmw_surface vmw_ioctl_surface_ref(int fd, int32 sid, uint32 handle_type)
+struct vmw_surface *vmw_ioctl_surface_ref(int fd, int32 sid, uint32 handle_type)
{
int ret;
- union drm_vmw_gb_surface_reference_ext_arg arg;
- struct vmw_surface surface;
+ union drm_vmw_gb_surface_reference_ext_arg arg = {0};
+ struct vmw_surface *surface;
+
+ surface = calloc(1, sizeof(struct vmw_surface));
+ if (!surface)
+ return NULL;
arg.req.handle_type = handle_type;
arg.req.sid = sid;
@@ -359,8 +344,8 @@ struct vmw_surface vmw_ioctl_surface_ref(int fd, int32 sid, uint32 handle_type)
if (ret != 0)
fprintf(stderr, "%s Failed\n", __func__);
- surface.base = arg.rep.crep;
- surface.params = arg.rep.creq;
+ surface->base = arg.rep.crep;
+ surface->params = arg.rep.creq;
return surface;
}
@@ -471,7 +456,7 @@ struct vmw_surface *vmw_ioctl_create_surface_full(
arg.req.base.autogen_filter = autogen_filter;
arg.req.base.drm_surface_flags |= surface_flags;
arg.req.base.buffer_handle = buffer_handle;
- if (buffer_handle != SVGA3D_INVALID_ID) {
+ if (buffer_handle == SVGA3D_INVALID_ID) {
arg.req.base.drm_surface_flags |=
drm_vmw_surface_flag_create_buffer;
}
diff --git a/lib/igt_vmwgfx.h b/lib/igt_vmwgfx.h
index 961aac389..e80e9848f 100644
--- a/lib/igt_vmwgfx.h
+++ b/lib/igt_vmwgfx.h
@@ -1,28 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/**********************************************************
- * Copyright 2021-2023 VMware, Inc.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- **********************************************************/
+/*
+ * Copyright (c) 2021-2024 Broadcom. All Rights Reserved. The term
+ * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
+ */
#ifndef IGT_VMWGFX_H
#define IGT_VMWGFX_H
@@ -186,7 +166,7 @@ struct vmw_surface *vmw_ioctl_buffer_create(int fd, SVGA3dSurfaceAllFlags flags,
uint32_t size, struct vmw_mob *mob);
void vmw_ioctl_surface_unref(int fd, struct vmw_surface *buffer);
-struct vmw_surface vmw_ioctl_surface_ref(int fd, int32 sid, uint32 handle_type);
+struct vmw_surface *vmw_ioctl_surface_ref(int fd, int32 sid, uint32 handle_type);
struct vmw_surface *vmw_ioctl_create_surface_full(
int fd, SVGA3dSurfaceAllFlags flags, SVGA3dSurfaceFormat format,
diff --git a/tests/vmwgfx/vmw_ref_count.c b/tests/vmwgfx/vmw_ref_count.c
index c765f2e70..8b4108471 100644
--- a/tests/vmwgfx/vmw_ref_count.c
+++ b/tests/vmwgfx/vmw_ref_count.c
@@ -1,33 +1,14 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
-/**********************************************************
- * Copyright 2021-2023 VMware, Inc.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- **********************************************************/
+/*
+ * Copyright (c) 2021-2024 Broadcom. All Rights Reserved. The term
+ * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
+ */
#include "igt_vmwgfx.h"
IGT_TEST_DESCRIPTION("Perform tests related to vmwgfx's ref_count codepaths.");
+#define NUM_SURFACES 10
static uint32 data[10] = { 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 };
static void write_to_mob(int fd, struct vmw_mob *mob)
@@ -35,6 +16,7 @@ static void write_to_mob(int fd, struct vmw_mob *mob)
void *write_data;
write_data = vmw_ioctl_mob_map(fd, mob);
+ igt_assert(write_data);
memcpy(write_data, data, sizeof(data));
vmw_ioctl_mob_unmap(mob);
}
@@ -73,7 +55,7 @@ create_and_write_shareable_surface(int32 fd, SVGA3dSize surface_size)
fd, SVGA3D_SURFACE_HINT_RENDERTARGET, SVGA3D_BUFFER, 0,
SVGA3D_MS_PATTERN_NONE, SVGA3D_MS_QUALITY_NONE,
SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, SVGA3D_INVALID_ID,
- drm_vmw_surface_flag_shareable);
+ drm_vmw_surface_flag_shareable | drm_vmw_surface_flag_create_buffer);
mob.handle = surface->base.buffer_handle;
mob.map_handle = surface->base.buffer_map_handle;
@@ -86,17 +68,22 @@ create_and_write_shareable_surface(int32 fd, SVGA3dSize surface_size)
static bool ref_surface_and_check_contents(int32 fd, uint32 surface_handle)
{
- struct vmw_surface surface;
+ struct vmw_surface *surface;
struct vmw_mob mob = { 0 };
+ bool data_valid;
surface = vmw_ioctl_surface_ref(fd, surface_handle,
DRM_VMW_HANDLE_LEGACY);
- mob.handle = surface.base.handle;
- mob.size = surface.base.buffer_size;
- mob.map_handle = surface.base.buffer_map_handle;
+ mob.handle = surface->base.handle;
+ mob.size = surface->base.buffer_size;
+ mob.map_handle = surface->base.buffer_map_handle;
+
+ data_valid = verify_mob_data(fd, &mob);
+
+ vmw_ioctl_surface_unref(fd, surface);
- return verify_mob_data(fd, &mob);
+ return data_valid;
}
igt_main
@@ -293,7 +280,7 @@ igt_main
igt_subtest("surface_alloc_ref_unref")
{
struct vmw_surface *surface;
- struct vmw_surface ref_surface;
+ struct vmw_surface *ref_surface;
struct vmw_mob readback_mob = { 0 };
surface = create_and_write_shareable_surface(fd1, surface_size);
@@ -303,11 +290,163 @@ igt_main
vmw_ioctl_surface_unref(fd1, surface);
- readback_mob.handle = ref_surface.base.handle;
- readback_mob.size = ref_surface.base.buffer_size;
- readback_mob.map_handle = ref_surface.base.buffer_map_handle;
+ readback_mob.handle = ref_surface->base.handle;
+ readback_mob.size = ref_surface->base.buffer_size;
+ readback_mob.map_handle = ref_surface->base.buffer_map_handle;
igt_assert(verify_mob_data(fd1, &readback_mob));
+
+ vmw_ioctl_surface_unref(fd1, ref_surface);
+ }
+
+ igt_describe("Test refing a surface from the buffer handle.");
+ igt_subtest("surface_buffer_ref")
+ {
+ struct vmw_surface *surfaces[NUM_SURFACES] = {0};
+ struct vmw_surface *refs[NUM_SURFACES] = {0};
+ struct vmw_surface *buf_refs[NUM_SURFACES] = {0};
+ int i;
+ SVGA3dSize surf_size;
+
+ for (i = 0; i < NUM_SURFACES; ++i) {
+ surf_size.width = 32 + i * 16;
+ surf_size.height = 32 + i * 16;
+ surf_size.depth = 1;
+
+ surfaces[i] = vmw_create_surface_simple(
+ fd1,
+ SVGA3D_SURFACE_HINT_TEXTURE |
+ SVGA3D_SURFACE_HINT_RENDERTARGET |
+ SVGA3D_SURFACE_BIND_RENDER_TARGET,
+ SVGA3D_R8G8B8A8_UNORM, surf_size, SVGA3D_INVALID_ID);
+ igt_assert(surfaces[i]);
+ }
+
+ for (i = 0; i < NUM_SURFACES; ++i) {
+ int prime_fd = prime_handle_to_fd_for_mmap(
+ fd1, surfaces[i]->base.handle);
+
+ refs[i] = vmw_ioctl_surface_ref(fd1, prime_fd,
+ DRM_VMW_HANDLE_PRIME);
+ igt_assert_eq(surfaces[i]->base.handle,
+ refs[i]->base.handle);
+ igt_assert_eq(surfaces[i]->base.backup_size,
+ refs[i]->base.backup_size);
+ igt_assert_eq(surfaces[i]->base.buffer_size,
+ refs[i]->base.buffer_size);
+ igt_assert_eq(surfaces[i]->base.buffer_map_handle,
+ refs[i]->base.buffer_map_handle);
+ igt_assert_eq(surfaces[i]->params.base.format,
+ refs[i]->params.base.format);
+ }
+
+ for (i = 0; i < NUM_SURFACES; ++i) {
+ int prime_fd = prime_handle_to_fd_for_mmap(
+ fd1, surfaces[i]->base.buffer_handle);
+
+ buf_refs[i] = vmw_ioctl_surface_ref(
+ fd1, prime_fd, DRM_VMW_HANDLE_PRIME);
+ igt_assert_eq(surfaces[i]->base.handle,
+ buf_refs[i]->base.handle);
+ igt_assert_eq(surfaces[i]->base.backup_size,
+ buf_refs[i]->base.backup_size);
+ igt_assert_eq(surfaces[i]->base.buffer_size,
+ buf_refs[i]->base.buffer_size);
+ igt_assert_eq(surfaces[i]->base.buffer_map_handle,
+ buf_refs[i]->base.buffer_map_handle);
+ igt_assert_eq(surfaces[i]->params.base.format,
+ buf_refs[i]->params.base.format);
+ }
+
+ for (i = 0; i < NUM_SURFACES; ++i) {
+ vmw_ioctl_surface_unref(fd1, buf_refs[i]);
+ vmw_ioctl_surface_unref(fd1, refs[i]);
+ vmw_ioctl_surface_unref(fd1, surfaces[i]);
+ }
+ }
+
+ igt_describe("Test refcounts on prime surfaces.");
+ igt_subtest("surface_prime_refs")
+ {
+ struct vmw_surface *surfaces[NUM_SURFACES] = {0};
+ int prime_fds[NUM_SURFACES] = {0};
+ struct vmw_surface *refs[NUM_SURFACES] = {0};
+ int i;
+ SVGA3dSize surf_size;
+
+ for (i = 0; i < NUM_SURFACES; ++i) {
+ surf_size.width = 32 + i * 16;
+ surf_size.height = 32 + i * 16;
+ surf_size.depth = 1;
+
+ surfaces[i] = vmw_create_surface_simple(
+ fd1,
+ SVGA3D_SURFACE_HINT_TEXTURE |
+ SVGA3D_SURFACE_HINT_RENDERTARGET |
+ SVGA3D_SURFACE_BIND_RENDER_TARGET,
+ SVGA3D_R8G8B8A8_UNORM, surf_size, SVGA3D_INVALID_ID);
+ igt_assert(surfaces[i]);
+ }
+
+ for (i = 0; i < NUM_SURFACES; ++i) {
+ prime_fds[i] = prime_handle_to_fd(
+ fd1, surfaces[i]->base.handle);
+ igt_assert_neq(prime_fds[i], 0);
+ igt_assert_neq(prime_fds[i], -1);
+ vmw_ioctl_surface_unref(fd1, surfaces[i]);
+ }
+
+ for (i = 0; i < NUM_SURFACES; ++i) {
+ refs[i] = vmw_ioctl_surface_ref(fd1, prime_fds[i],
+ DRM_VMW_HANDLE_PRIME);
+ close(prime_fds[i]);
+ igt_assert_neq(refs[i]->base.handle, 0);
+ igt_assert_neq(refs[i]->base.backup_size, 0);
+ igt_assert_neq(refs[i]->base.buffer_size, 0);
+
+ }
+ }
+
+ igt_describe("Test refcounts on prime surfaces with buffer handles.");
+ igt_subtest("surface_buffer_prime_refs")
+ {
+ struct vmw_surface *surfaces[NUM_SURFACES] = {0};
+ int prime_fds[NUM_SURFACES] = {0};
+ struct vmw_surface *refs[NUM_SURFACES] = {0};
+ int i;
+ SVGA3dSize surf_size;
+
+ for (i = 0; i < NUM_SURFACES; ++i) {
+ surf_size.width = 32 + i * 16;
+ surf_size.height = 32 + i * 16;
+ surf_size.depth = 1;
+
+ surfaces[i] = vmw_create_surface_simple(
+ fd1,
+ SVGA3D_SURFACE_HINT_TEXTURE |
+ SVGA3D_SURFACE_HINT_RENDERTARGET |
+ SVGA3D_SURFACE_BIND_RENDER_TARGET,
+ SVGA3D_R8G8B8A8_UNORM, surf_size, SVGA3D_INVALID_ID);
+ igt_assert(surfaces[i]);
+ }
+
+ for (i = 0; i < NUM_SURFACES; ++i) {
+ prime_fds[i] = prime_handle_to_fd(
+ fd1, surfaces[i]->base.buffer_handle);
+ igt_assert_neq(prime_fds[i], 0);
+ igt_assert_neq(prime_fds[i], -1);
+ vmw_ioctl_surface_unref(fd1, surfaces[i]);
+ }
+
+ for (i = 0; i < NUM_SURFACES; ++i) {
+ refs[i] = vmw_ioctl_surface_ref(fd1, prime_fds[i],
+ DRM_VMW_HANDLE_PRIME);
+ close(prime_fds[i]);
+ igt_assert_neq(refs[i]->base.handle, 0);
+ igt_assert_neq(refs[i]->base.backup_size, 0);
+ igt_assert_neq(refs[i]->base.buffer_size, 0);
+
+ }
}
igt_fixture
--
2.40.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH i-g-t v3 4/4] tests/vmwgfx: Fix and extend the reference counting test
2024-06-28 19:02 ` [PATCH i-g-t v3 4/4] tests/vmwgfx: Fix and extend the reference counting test Zack Rusin
@ 2024-07-26 19:16 ` Kamil Konieczny
2024-07-29 3:35 ` Zack Rusin
0 siblings, 1 reply; 12+ messages in thread
From: Kamil Konieczny @ 2024-07-26 19:16 UTC (permalink / raw)
To: igt-dev
Cc: Zack Rusin, Petri Latvala, ian.forbes, martin.krastev,
maaz.mombasawala
Hi Zack,
On 2024-06-28 at 15:02:43 -0400, Zack Rusin wrote:
> Fix a few issues related to buffer managment in the reference counting
> test. Extend it to include various prime related reference counting
> issues.
>
> Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
Sorry for late response. Could you split fixes from improvements?
See also other notes below.
> ---
> lib/igt_vmwgfx.c | 45 +++-----
> lib/igt_vmwgfx.h | 30 +----
> tests/vmwgfx/vmw_ref_count.c | 207 +++++++++++++++++++++++++++++------
> 3 files changed, 193 insertions(+), 89 deletions(-)
>
> diff --git a/lib/igt_vmwgfx.c b/lib/igt_vmwgfx.c
> index d2f699575..b62d7a326 100644
> --- a/lib/igt_vmwgfx.c
> +++ b/lib/igt_vmwgfx.c
> @@ -1,28 +1,8 @@
> // SPDX-License-Identifier: GPL-2.0 OR MIT
> -/**********************************************************
> - * Copyright 2021-2023 VMware, Inc.
Please do not remove old copyrigths.
> - *
> - * Permission is hereby granted, free of charge, to any person
> - * obtaining a copy of this software and associated documentation
> - * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use, copy,
> - * modify, merge, publish, distribute, sublicense, and/or sell copies
> - * of the Software, and to permit persons to whom the Software is
> - * furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be
> - * included in all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> - * SOFTWARE.
> - *
> - **********************************************************/
I just checked and it looks like written licence text is MIT,
while that '// SPDX ' at begin is GPL-2.0 OR MIT so maybe it
is ok to remove text in favor of SPDX.
> +/*
> + * Copyright (c) 2021-2024 Broadcom. All Rights Reserved. The term
--------------------^^^^^^^^^
This should be 2024 only.
Adding Petri to Cc.
> + * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
> + */
>
As for other changes below, please use checkpatch.pl and resend.
> #include "igt_vmwgfx.h"
>
> @@ -154,6 +134,7 @@ bool vmw_save_data_as_png(struct vmw_surface *surface, void *data,
> /* Can separate this into another function as it grows */
> switch (surface->params.base.format) {
> case SVGA3D_R8G8B8A8_UNORM:
> + case SVGA3D_B8G8R8X8_UNORM:
> format = CAIRO_FORMAT_ARGB32;
> break;
> default:
> @@ -345,11 +326,15 @@ void vmw_ioctl_mob_close_handle(int fd, struct vmw_mob *mob)
> free(mob);
> }
>
> -struct vmw_surface vmw_ioctl_surface_ref(int fd, int32 sid, uint32 handle_type)
> +struct vmw_surface *vmw_ioctl_surface_ref(int fd, int32 sid, uint32 handle_type)
> {
> int ret;
> - union drm_vmw_gb_surface_reference_ext_arg arg;
> - struct vmw_surface surface;
> + union drm_vmw_gb_surface_reference_ext_arg arg = {0};
> + struct vmw_surface *surface;
> +
> + surface = calloc(1, sizeof(struct vmw_surface));
> + if (!surface)
> + return NULL;
>
> arg.req.handle_type = handle_type;
> arg.req.sid = sid;
> @@ -359,8 +344,8 @@ struct vmw_surface vmw_ioctl_surface_ref(int fd, int32 sid, uint32 handle_type)
> if (ret != 0)
> fprintf(stderr, "%s Failed\n", __func__);
>
> - surface.base = arg.rep.crep;
> - surface.params = arg.rep.creq;
> + surface->base = arg.rep.crep;
> + surface->params = arg.rep.creq;
> return surface;
> }
>
> @@ -471,7 +456,7 @@ struct vmw_surface *vmw_ioctl_create_surface_full(
> arg.req.base.autogen_filter = autogen_filter;
> arg.req.base.drm_surface_flags |= surface_flags;
> arg.req.base.buffer_handle = buffer_handle;
> - if (buffer_handle != SVGA3D_INVALID_ID) {
> + if (buffer_handle == SVGA3D_INVALID_ID) {
> arg.req.base.drm_surface_flags |=
> drm_vmw_surface_flag_create_buffer;
> }
> diff --git a/lib/igt_vmwgfx.h b/lib/igt_vmwgfx.h
> index 961aac389..e80e9848f 100644
> --- a/lib/igt_vmwgfx.h
> +++ b/lib/igt_vmwgfx.h
> @@ -1,28 +1,8 @@
> /* SPDX-License-Identifier: GPL-2.0 OR MIT */
> -/**********************************************************
> - * Copyright 2021-2023 VMware, Inc.
Same here, do not remove old ones.
> - *
> - * Permission is hereby granted, free of charge, to any person
> - * obtaining a copy of this software and associated documentation
> - * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use, copy,
> - * modify, merge, publish, distribute, sublicense, and/or sell copies
> - * of the Software, and to permit persons to whom the Software is
> - * furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be
> - * included in all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> - * SOFTWARE.
> - *
> - **********************************************************/
> +/*
> + * Copyright (c) 2021-2024 Broadcom. All Rights Reserved. The term
Same here, only 2024.
> + * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
> + */
>
> #ifndef IGT_VMWGFX_H
> #define IGT_VMWGFX_H
> @@ -186,7 +166,7 @@ struct vmw_surface *vmw_ioctl_buffer_create(int fd, SVGA3dSurfaceAllFlags flags,
> uint32_t size, struct vmw_mob *mob);
> void vmw_ioctl_surface_unref(int fd, struct vmw_surface *buffer);
>
> -struct vmw_surface vmw_ioctl_surface_ref(int fd, int32 sid, uint32 handle_type);
> +struct vmw_surface *vmw_ioctl_surface_ref(int fd, int32 sid, uint32 handle_type);
>
> struct vmw_surface *vmw_ioctl_create_surface_full(
> int fd, SVGA3dSurfaceAllFlags flags, SVGA3dSurfaceFormat format,
> diff --git a/tests/vmwgfx/vmw_ref_count.c b/tests/vmwgfx/vmw_ref_count.c
> index c765f2e70..8b4108471 100644
> --- a/tests/vmwgfx/vmw_ref_count.c
> +++ b/tests/vmwgfx/vmw_ref_count.c
> @@ -1,33 +1,14 @@
> // SPDX-License-Identifier: GPL-2.0 OR MIT
> -/**********************************************************
> - * Copyright 2021-2023 VMware, Inc.
Same here, do not remove old ones.
> - *
> - * Permission is hereby granted, free of charge, to any person
> - * obtaining a copy of this software and associated documentation
> - * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use, copy,
> - * modify, merge, publish, distribute, sublicense, and/or sell copies
> - * of the Software, and to permit persons to whom the Software is
> - * furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be
> - * included in all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> - * SOFTWARE.
> - *
> - **********************************************************/
> +/*
> + * Copyright (c) 2021-2024 Broadcom. All Rights Reserved. The term
Same here, only 2024.
> + * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
> + */
It could help if someone from your team could review changes,
I could give you an ack after resend with corrections.
Regards,
Kamil
>
> #include "igt_vmwgfx.h"
>
> IGT_TEST_DESCRIPTION("Perform tests related to vmwgfx's ref_count codepaths.");
>
> +#define NUM_SURFACES 10
> static uint32 data[10] = { 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 };
>
> static void write_to_mob(int fd, struct vmw_mob *mob)
> @@ -35,6 +16,7 @@ static void write_to_mob(int fd, struct vmw_mob *mob)
> void *write_data;
>
> write_data = vmw_ioctl_mob_map(fd, mob);
> + igt_assert(write_data);
> memcpy(write_data, data, sizeof(data));
> vmw_ioctl_mob_unmap(mob);
> }
> @@ -73,7 +55,7 @@ create_and_write_shareable_surface(int32 fd, SVGA3dSize surface_size)
> fd, SVGA3D_SURFACE_HINT_RENDERTARGET, SVGA3D_BUFFER, 0,
> SVGA3D_MS_PATTERN_NONE, SVGA3D_MS_QUALITY_NONE,
> SVGA3D_TEX_FILTER_NONE, 1, 1, surface_size, SVGA3D_INVALID_ID,
> - drm_vmw_surface_flag_shareable);
> + drm_vmw_surface_flag_shareable | drm_vmw_surface_flag_create_buffer);
>
> mob.handle = surface->base.buffer_handle;
> mob.map_handle = surface->base.buffer_map_handle;
> @@ -86,17 +68,22 @@ create_and_write_shareable_surface(int32 fd, SVGA3dSize surface_size)
>
> static bool ref_surface_and_check_contents(int32 fd, uint32 surface_handle)
> {
> - struct vmw_surface surface;
> + struct vmw_surface *surface;
> struct vmw_mob mob = { 0 };
> + bool data_valid;
>
> surface = vmw_ioctl_surface_ref(fd, surface_handle,
> DRM_VMW_HANDLE_LEGACY);
>
> - mob.handle = surface.base.handle;
> - mob.size = surface.base.buffer_size;
> - mob.map_handle = surface.base.buffer_map_handle;
> + mob.handle = surface->base.handle;
> + mob.size = surface->base.buffer_size;
> + mob.map_handle = surface->base.buffer_map_handle;
> +
> + data_valid = verify_mob_data(fd, &mob);
> +
> + vmw_ioctl_surface_unref(fd, surface);
>
> - return verify_mob_data(fd, &mob);
> + return data_valid;
> }
>
> igt_main
> @@ -293,7 +280,7 @@ igt_main
> igt_subtest("surface_alloc_ref_unref")
> {
> struct vmw_surface *surface;
> - struct vmw_surface ref_surface;
> + struct vmw_surface *ref_surface;
> struct vmw_mob readback_mob = { 0 };
>
> surface = create_and_write_shareable_surface(fd1, surface_size);
> @@ -303,11 +290,163 @@ igt_main
>
> vmw_ioctl_surface_unref(fd1, surface);
>
> - readback_mob.handle = ref_surface.base.handle;
> - readback_mob.size = ref_surface.base.buffer_size;
> - readback_mob.map_handle = ref_surface.base.buffer_map_handle;
> + readback_mob.handle = ref_surface->base.handle;
> + readback_mob.size = ref_surface->base.buffer_size;
> + readback_mob.map_handle = ref_surface->base.buffer_map_handle;
>
> igt_assert(verify_mob_data(fd1, &readback_mob));
> +
> + vmw_ioctl_surface_unref(fd1, ref_surface);
> + }
> +
> + igt_describe("Test refing a surface from the buffer handle.");
> + igt_subtest("surface_buffer_ref")
> + {
> + struct vmw_surface *surfaces[NUM_SURFACES] = {0};
> + struct vmw_surface *refs[NUM_SURFACES] = {0};
> + struct vmw_surface *buf_refs[NUM_SURFACES] = {0};
> + int i;
> + SVGA3dSize surf_size;
> +
> + for (i = 0; i < NUM_SURFACES; ++i) {
> + surf_size.width = 32 + i * 16;
> + surf_size.height = 32 + i * 16;
> + surf_size.depth = 1;
> +
> + surfaces[i] = vmw_create_surface_simple(
> + fd1,
> + SVGA3D_SURFACE_HINT_TEXTURE |
> + SVGA3D_SURFACE_HINT_RENDERTARGET |
> + SVGA3D_SURFACE_BIND_RENDER_TARGET,
> + SVGA3D_R8G8B8A8_UNORM, surf_size, SVGA3D_INVALID_ID);
> + igt_assert(surfaces[i]);
> + }
> +
> + for (i = 0; i < NUM_SURFACES; ++i) {
> + int prime_fd = prime_handle_to_fd_for_mmap(
> + fd1, surfaces[i]->base.handle);
> +
> + refs[i] = vmw_ioctl_surface_ref(fd1, prime_fd,
> + DRM_VMW_HANDLE_PRIME);
> + igt_assert_eq(surfaces[i]->base.handle,
> + refs[i]->base.handle);
> + igt_assert_eq(surfaces[i]->base.backup_size,
> + refs[i]->base.backup_size);
> + igt_assert_eq(surfaces[i]->base.buffer_size,
> + refs[i]->base.buffer_size);
> + igt_assert_eq(surfaces[i]->base.buffer_map_handle,
> + refs[i]->base.buffer_map_handle);
> + igt_assert_eq(surfaces[i]->params.base.format,
> + refs[i]->params.base.format);
> + }
> +
> + for (i = 0; i < NUM_SURFACES; ++i) {
> + int prime_fd = prime_handle_to_fd_for_mmap(
> + fd1, surfaces[i]->base.buffer_handle);
> +
> + buf_refs[i] = vmw_ioctl_surface_ref(
> + fd1, prime_fd, DRM_VMW_HANDLE_PRIME);
> + igt_assert_eq(surfaces[i]->base.handle,
> + buf_refs[i]->base.handle);
> + igt_assert_eq(surfaces[i]->base.backup_size,
> + buf_refs[i]->base.backup_size);
> + igt_assert_eq(surfaces[i]->base.buffer_size,
> + buf_refs[i]->base.buffer_size);
> + igt_assert_eq(surfaces[i]->base.buffer_map_handle,
> + buf_refs[i]->base.buffer_map_handle);
> + igt_assert_eq(surfaces[i]->params.base.format,
> + buf_refs[i]->params.base.format);
> + }
> +
> + for (i = 0; i < NUM_SURFACES; ++i) {
> + vmw_ioctl_surface_unref(fd1, buf_refs[i]);
> + vmw_ioctl_surface_unref(fd1, refs[i]);
> + vmw_ioctl_surface_unref(fd1, surfaces[i]);
> + }
> + }
> +
> + igt_describe("Test refcounts on prime surfaces.");
> + igt_subtest("surface_prime_refs")
> + {
> + struct vmw_surface *surfaces[NUM_SURFACES] = {0};
> + int prime_fds[NUM_SURFACES] = {0};
> + struct vmw_surface *refs[NUM_SURFACES] = {0};
> + int i;
> + SVGA3dSize surf_size;
> +
> + for (i = 0; i < NUM_SURFACES; ++i) {
> + surf_size.width = 32 + i * 16;
> + surf_size.height = 32 + i * 16;
> + surf_size.depth = 1;
> +
> + surfaces[i] = vmw_create_surface_simple(
> + fd1,
> + SVGA3D_SURFACE_HINT_TEXTURE |
> + SVGA3D_SURFACE_HINT_RENDERTARGET |
> + SVGA3D_SURFACE_BIND_RENDER_TARGET,
> + SVGA3D_R8G8B8A8_UNORM, surf_size, SVGA3D_INVALID_ID);
> + igt_assert(surfaces[i]);
> + }
> +
> + for (i = 0; i < NUM_SURFACES; ++i) {
> + prime_fds[i] = prime_handle_to_fd(
> + fd1, surfaces[i]->base.handle);
> + igt_assert_neq(prime_fds[i], 0);
> + igt_assert_neq(prime_fds[i], -1);
> + vmw_ioctl_surface_unref(fd1, surfaces[i]);
> + }
> +
> + for (i = 0; i < NUM_SURFACES; ++i) {
> + refs[i] = vmw_ioctl_surface_ref(fd1, prime_fds[i],
> + DRM_VMW_HANDLE_PRIME);
> + close(prime_fds[i]);
> + igt_assert_neq(refs[i]->base.handle, 0);
> + igt_assert_neq(refs[i]->base.backup_size, 0);
> + igt_assert_neq(refs[i]->base.buffer_size, 0);
> +
> + }
> + }
> +
> + igt_describe("Test refcounts on prime surfaces with buffer handles.");
> + igt_subtest("surface_buffer_prime_refs")
> + {
> + struct vmw_surface *surfaces[NUM_SURFACES] = {0};
> + int prime_fds[NUM_SURFACES] = {0};
> + struct vmw_surface *refs[NUM_SURFACES] = {0};
> + int i;
> + SVGA3dSize surf_size;
> +
> + for (i = 0; i < NUM_SURFACES; ++i) {
> + surf_size.width = 32 + i * 16;
> + surf_size.height = 32 + i * 16;
> + surf_size.depth = 1;
> +
> + surfaces[i] = vmw_create_surface_simple(
> + fd1,
> + SVGA3D_SURFACE_HINT_TEXTURE |
> + SVGA3D_SURFACE_HINT_RENDERTARGET |
> + SVGA3D_SURFACE_BIND_RENDER_TARGET,
> + SVGA3D_R8G8B8A8_UNORM, surf_size, SVGA3D_INVALID_ID);
> + igt_assert(surfaces[i]);
> + }
> +
> + for (i = 0; i < NUM_SURFACES; ++i) {
> + prime_fds[i] = prime_handle_to_fd(
> + fd1, surfaces[i]->base.buffer_handle);
> + igt_assert_neq(prime_fds[i], 0);
> + igt_assert_neq(prime_fds[i], -1);
> + vmw_ioctl_surface_unref(fd1, surfaces[i]);
> + }
> +
> + for (i = 0; i < NUM_SURFACES; ++i) {
> + refs[i] = vmw_ioctl_surface_ref(fd1, prime_fds[i],
> + DRM_VMW_HANDLE_PRIME);
> + close(prime_fds[i]);
> + igt_assert_neq(refs[i]->base.handle, 0);
> + igt_assert_neq(refs[i]->base.backup_size, 0);
> + igt_assert_neq(refs[i]->base.buffer_size, 0);
> +
> + }
> }
>
> igt_fixture
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH i-g-t v3 4/4] tests/vmwgfx: Fix and extend the reference counting test
2024-07-26 19:16 ` Kamil Konieczny
@ 2024-07-29 3:35 ` Zack Rusin
0 siblings, 0 replies; 12+ messages in thread
From: Zack Rusin @ 2024-07-29 3:35 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev, Zack Rusin, Petri Latvala, ian.forbes,
martin.krastev, maaz.mombasawala
On Fri, Jul 26, 2024 at 3:16 PM Kamil Konieczny
<kamil.konieczny@linux.intel.com> wrote:
>
> Hi Zack,
> On 2024-06-28 at 15:02:43 -0400, Zack Rusin wrote:
> > Fix a few issues related to buffer managment in the reference counting
> > test. Extend it to include various prime related reference counting
> > issues.
> >
> > Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
>
> Sorry for late response. Could you split fixes from improvements?
It's really not worth it. The test is only valuable with all the
changes. If it makes it better I can remove it altogether in one
change and re-add it in its current form in the other but that seems
silly.
> > ---
> > lib/igt_vmwgfx.c | 45 +++-----
> > lib/igt_vmwgfx.h | 30 +----
> > tests/vmwgfx/vmw_ref_count.c | 207 +++++++++++++++++++++++++++++------
> > 3 files changed, 193 insertions(+), 89 deletions(-)
> >
> > diff --git a/lib/igt_vmwgfx.c b/lib/igt_vmwgfx.c
> > index d2f699575..b62d7a326 100644
> > --- a/lib/igt_vmwgfx.c
> > +++ b/lib/igt_vmwgfx.c
> > @@ -1,28 +1,8 @@
> > // SPDX-License-Identifier: GPL-2.0 OR MIT
> > -/**********************************************************
> > - * Copyright 2021-2023 VMware, Inc.
>
> Please do not remove old copyrigths.
I'm sorry but I can not do that. Broadcom acquired VMware, this is how
those copyrights have to look. You'd have to go through Broadcom's
legal team to contest this.
I'll respin the series with checkpatch.pl fixes.
z
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ CI.xeBAT: success for Add vmwgfx prime tests (rev3)
2024-06-28 19:02 [PATCH i-g-t v3 0/4] Add vmwgfx prime tests Zack Rusin
` (3 preceding siblings ...)
2024-06-28 19:02 ` [PATCH i-g-t v3 4/4] tests/vmwgfx: Fix and extend the reference counting test Zack Rusin
@ 2024-06-28 19:31 ` Patchwork
2024-06-28 19:40 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-06-28 20:39 ` ✓ CI.xeFULL: success " Patchwork
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2024-06-28 19:31 UTC (permalink / raw)
To: Zack Rusin; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 1771 bytes --]
== Series Details ==
Series: Add vmwgfx prime tests (rev3)
URL : https://patchwork.freedesktop.org/series/133402/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7907_BAT -> XEIGTPW_11332_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (5 -> 5)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in XEIGTPW_11332_BAT that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- {bat-lnl-1}: [FAIL][1] ([Intel XE#886]) -> [PASS][2] +1 other test pass
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
Build changes
-------------
* IGT: IGT_7907 -> IGTPW_11332
* Linux: xe-1538-42f35e623e6590cf8ec493373e4664ae4e32123c -> xe-1542-886eeb6d89b58f914ee5045fcac54b59a73d8299
IGTPW_11332: 11332
IGT_7907: 676b8e660cadae8ffb29a45b12ad5b53ef228b6a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-1538-42f35e623e6590cf8ec493373e4664ae4e32123c: 42f35e623e6590cf8ec493373e4664ae4e32123c
xe-1542-886eeb6d89b58f914ee5045fcac54b59a73d8299: 886eeb6d89b58f914ee5045fcac54b59a73d8299
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/index.html
[-- Attachment #2: Type: text/html, Size: 2358 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread* ✗ Fi.CI.BAT: failure for Add vmwgfx prime tests (rev3)
2024-06-28 19:02 [PATCH i-g-t v3 0/4] Add vmwgfx prime tests Zack Rusin
` (4 preceding siblings ...)
2024-06-28 19:31 ` ✓ CI.xeBAT: success for Add vmwgfx prime tests (rev3) Patchwork
@ 2024-06-28 19:40 ` Patchwork
2024-06-28 20:39 ` ✓ CI.xeFULL: success " Patchwork
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2024-06-28 19:40 UTC (permalink / raw)
To: Zack Rusin; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 19201 bytes --]
== Series Details ==
Series: Add vmwgfx prime tests (rev3)
URL : https://patchwork.freedesktop.org/series/133402/
State : failure
== Summary ==
CI Bug Log - changes from IGT_7907 -> IGTPW_11332
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_11332 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_11332, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/index.html
Participating hosts (35 -> 38)
------------------------------
Additional (7): bat-adlp-9 bat-adlp-6 fi-elk-e7500 bat-dg2-14 bat-dg2-13 bat-dg2-11 bat-jsl-3
Missing (4): bat-kbl-2 bat-arlh-2 fi-cfl-8109u fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_11332:
### IGT changes ###
#### Possible regressions ####
* igt@kms_chamelium_edid@dp-edid-read:
- bat-dg2-13: NOTRUN -> [ABORT][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-13/igt@kms_chamelium_edid@dp-edid-read.html
Known issues
------------
Here are the changes found in IGTPW_11332 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-adlp-9: NOTRUN -> [SKIP][2] ([i915#9318])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@debugfs_test@basic-hwmon.html
- bat-adlp-6: NOTRUN -> [SKIP][3] ([i915#9318])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-6/igt@debugfs_test@basic-hwmon.html
- bat-jsl-3: NOTRUN -> [SKIP][4] ([i915#9318])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-jsl-3/igt@debugfs_test@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-3: NOTRUN -> [SKIP][5] ([i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-jsl-3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-jsl-3: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-jsl-3/igt@gem_lmem_swapping@basic.html
- bat-adlp-9: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-11: NOTRUN -> [FAIL][8] ([i915#10378])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html
* igt@gem_lmem_swapping@random-engines:
- bat-adlp-6: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-6/igt@gem_lmem_swapping@random-engines.html
* igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#4083])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@gem_mmap@basic.html
- bat-dg2-14: NOTRUN -> [SKIP][11] ([i915#4083])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-14: NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg2-14: NOTRUN -> [SKIP][13] ([i915#4077]) +2 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@gem_tiled_fence_blits@basic.html
- bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#4077]) +2 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-adlp-6: NOTRUN -> [SKIP][15] ([i915#3282])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-6/igt@gem_tiled_pread_basic.html
- bat-adlp-9: NOTRUN -> [SKIP][16] ([i915#3282])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@gem_tiled_pread_basic.html
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#4079]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-adlp-9: NOTRUN -> [SKIP][18] ([i915#6621])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@i915_pm_rps@basic-api.html
- bat-dg2-14: NOTRUN -> [SKIP][19] ([i915#6621])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@i915_pm_rps@basic-api.html
- bat-adlp-6: NOTRUN -> [SKIP][20] ([i915#6621])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-6/igt@i915_pm_rps@basic-api.html
- bat-dg2-11: NOTRUN -> [SKIP][21] ([i915#6621])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][22] ([i915#4212]) +7 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][23] ([i915#5190])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-dg2-14: NOTRUN -> [SKIP][24] ([i915#5190])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg2-14: NOTRUN -> [SKIP][25] ([i915#4212]) +7 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][26] ([i915#4215] / [i915#5190])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-dg2-14: NOTRUN -> [SKIP][27] ([i915#4215] / [i915#5190])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-adlp-9: NOTRUN -> [SKIP][28] ([i915#4103]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- bat-dg2-11: NOTRUN -> [SKIP][29] ([i915#4103] / [i915#4213]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-14: NOTRUN -> [SKIP][30] ([i915#4103] / [i915#4213]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-3: NOTRUN -> [SKIP][31] ([i915#4103]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-jsl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-adlp-6: NOTRUN -> [SKIP][32] ([i915#4103]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- bat-arls-1: [PASS][33] -> [DMESG-WARN][34] ([i915#1982])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7907/bat-arls-1/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-arls-1/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
* igt@kms_dsc@dsc-basic:
- bat-dg2-11: NOTRUN -> [SKIP][35] ([i915#3555] / [i915#3840])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@kms_dsc@dsc-basic.html
- bat-dg2-14: NOTRUN -> [SKIP][36] ([i915#3555] / [i915#3840])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@kms_dsc@dsc-basic.html
- bat-adlp-6: NOTRUN -> [SKIP][37] ([i915#3555] / [i915#3840])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-6/igt@kms_dsc@dsc-basic.html
- bat-jsl-3: NOTRUN -> [SKIP][38] ([i915#3555] / [i915#9886])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-jsl-3/igt@kms_dsc@dsc-basic.html
- bat-adlp-9: NOTRUN -> [SKIP][39] ([i915#3555] / [i915#3840])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-14: NOTRUN -> [SKIP][40]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@kms_force_connector_basic@force-load-detect.html
- bat-jsl-3: NOTRUN -> [SKIP][41]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-jsl-3/igt@kms_force_connector_basic@force-load-detect.html
- bat-adlp-6: NOTRUN -> [SKIP][42]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-6/igt@kms_force_connector_basic@force-load-detect.html
- bat-adlp-9: NOTRUN -> [SKIP][43]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg2-11: NOTRUN -> [SKIP][44]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-11: NOTRUN -> [SKIP][45] ([i915#5274])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-dg2-14: NOTRUN -> [SKIP][46] ([i915#5274])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pm_backlight@basic-brightness:
- bat-dg2-11: NOTRUN -> [SKIP][47] ([i915#5354])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@kms_pm_backlight@basic-brightness.html
- bat-dg2-14: NOTRUN -> [SKIP][48] ([i915#5354])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@kms_pm_backlight@basic-brightness.html
- bat-adlp-9: NOTRUN -> [SKIP][49] ([i915#9812])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- fi-elk-e7500: NOTRUN -> [SKIP][50] +24 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/fi-elk-e7500/igt@kms_pm_rpm@basic-pci-d3-state.html
* igt@kms_psr@psr-sprite-plane-onoff:
- bat-adlp-9: NOTRUN -> [SKIP][51] ([i915#1072] / [i915#9673] / [i915#9732]) +3 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@kms_psr@psr-sprite-plane-onoff.html
- bat-dg2-11: NOTRUN -> [SKIP][52] ([i915#1072] / [i915#9732]) +3 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@kms_psr@psr-sprite-plane-onoff.html
- bat-dg2-14: NOTRUN -> [SKIP][53] ([i915#1072] / [i915#9732]) +3 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@kms_psr@psr-sprite-plane-onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adlp-9: NOTRUN -> [SKIP][54] ([i915#3555])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-14: NOTRUN -> [SKIP][55] ([i915#3555])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@kms_setmode@basic-clone-single-crtc.html
- bat-adlp-6: NOTRUN -> [SKIP][56] ([i915#3555])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-6/igt@kms_setmode@basic-clone-single-crtc.html
- bat-jsl-3: NOTRUN -> [SKIP][57] ([i915#3555])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-jsl-3/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-11: NOTRUN -> [SKIP][58] ([i915#3555])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-11: NOTRUN -> [SKIP][59] ([i915#3708])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@prime_vgem@basic-fence-flip.html
- bat-dg2-14: NOTRUN -> [SKIP][60] ([i915#3708])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-11: NOTRUN -> [SKIP][61] ([i915#3708] / [i915#4077]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@prime_vgem@basic-fence-mmap.html
- bat-dg2-14: NOTRUN -> [SKIP][62] ([i915#3708] / [i915#4077]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-adlp-9: NOTRUN -> [SKIP][63] ([i915#3291] / [i915#3708]) +2 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-9/igt@prime_vgem@basic-fence-read.html
- bat-adlp-6: NOTRUN -> [SKIP][64] ([i915#3291] / [i915#3708]) +2 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-adlp-6/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- bat-dg2-11: NOTRUN -> [SKIP][65] ([i915#3291] / [i915#3708]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-11/igt@prime_vgem@basic-read.html
- bat-dg2-14: NOTRUN -> [SKIP][66] ([i915#3291] / [i915#3708]) +2 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/bat-dg2-14/igt@prime_vgem@basic-read.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries:
- fi-kbl-7567u: [DMESG-WARN][67] -> [PASS][68] +5 other tests pass
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7907/fi-kbl-7567u/igt@debugfs_test@read_all_entries.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/fi-kbl-7567u/igt@debugfs_test@read_all_entries.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: [DMESG-WARN][69] ([i915#10062] / [i915#180] / [i915#1982] / [i915#9925]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7907/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@sanitycheck:
- fi-kbl-7567u: [DMESG-WARN][71] ([i915#11328]) -> [PASS][72] +74 other tests pass
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7907/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/fi-kbl-7567u/igt@i915_selftest@live@sanitycheck.html
* igt@kms_busy@basic@flip:
- fi-kbl-7567u: [DMESG-WARN][73] ([i915#180]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7907/fi-kbl-7567u/igt@kms_busy@basic@flip.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/fi-kbl-7567u/igt@kms_busy@basic@flip.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- fi-kbl-7567u: [DMESG-WARN][75] ([i915#10062] / [i915#180] / [i915#9925]) -> [PASS][76] +39 other tests pass
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7907/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html
[i915#10062]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10062
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#11328]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11328
[i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
[i915#9925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9925
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7907 -> IGTPW_11332
CI-20190529: 20190529
CI_DRM_15013: 0318a12ff6fb8c321458aa2b373e9322896ee951 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_11332: 11332
IGT_7907: 676b8e660cadae8ffb29a45b12ad5b53ef228b6a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11332/index.html
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^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ CI.xeFULL: success for Add vmwgfx prime tests (rev3)
2024-06-28 19:02 [PATCH i-g-t v3 0/4] Add vmwgfx prime tests Zack Rusin
` (5 preceding siblings ...)
2024-06-28 19:40 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2024-06-28 20:39 ` Patchwork
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2024-06-28 20:39 UTC (permalink / raw)
To: Zack Rusin; +Cc: igt-dev
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== Series Details ==
Series: Add vmwgfx prime tests (rev3)
URL : https://patchwork.freedesktop.org/series/133402/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7907_full -> XEIGTPW_11332_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (3 -> 3)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in XEIGTPW_11332_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p}:
- {shard-lnl}: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-lnl-3/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- {shard-lnl}: [SKIP][2] ([Intel XE#373]) -> [INCOMPLETE][3]
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-lnl-6/igt@kms_chamelium_hpd@vga-hpd-fast.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-lnl-1/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_plane_alpha_blend@coverage-7efc@pipe-c-edp-1:
- {shard-lnl}: [PASS][4] -> [INCOMPLETE][5] +3 other tests incomplete
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-lnl-1/igt@kms_plane_alpha_blend@coverage-7efc@pipe-c-edp-1.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-lnl-4/igt@kms_plane_alpha_blend@coverage-7efc@pipe-c-edp-1.html
Known issues
------------
Here are the changes found in XEIGTPW_11332_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][6] ([Intel XE#1201] / [Intel XE#316]) +1 other test skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-463/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-dg2-set2: NOTRUN -> [SKIP][7] ([Intel XE#1124] / [Intel XE#1201]) +3 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-464/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][8] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +13 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-434/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-dp-4.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#1201] / [Intel XE#787]) +48 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-435/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-dp-4.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#1201] / [Intel XE#314])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-466/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_chamelium_color@ctm-blue-to-red:
- shard-dg2-set2: NOTRUN -> [SKIP][11] ([Intel XE#1201] / [Intel XE#306])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-435/igt@kms_chamelium_color@ctm-blue-to-red.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-dg2-set2: NOTRUN -> [SKIP][12] ([Intel XE#1201] / [Intel XE#373]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-466/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2-set2: NOTRUN -> [SKIP][13] ([Intel XE#1201] / [Intel XE#307])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-464/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg2-set2: NOTRUN -> [SKIP][14] ([Intel XE#1201] / [Intel XE#308])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-434/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-dg2-set2: [PASS][15] -> [INCOMPLETE][16] ([Intel XE#1195]) +4 other tests incomplete
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-434/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-466/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#1201] / [Intel XE#455]) +6 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-436/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][18] ([Intel XE#1201] / [Intel XE#651]) +10 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
- shard-dg2-set2: [PASS][19] -> [DMESG-WARN][20] ([Intel XE#1214]) +1 other test dmesg-warn
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
- shard-dg2-set2: NOTRUN -> [SKIP][21] ([Intel XE#1201] / [Intel XE#653]) +9 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6:
- shard-dg2-set2: [PASS][22] -> [FAIL][23] ([Intel XE#361])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-433/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-463/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation:
- shard-dg2-set2: NOTRUN -> [SKIP][24] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#498]) +1 other test skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-464/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#1201] / [Intel XE#498]) +2 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-464/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6.html
* igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#1201] / [Intel XE#1489]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-436/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@fbc-psr2-sprite-plane-move:
- shard-dg2-set2: NOTRUN -> [SKIP][27] ([Intel XE#1201] / [Intel XE#929]) +5 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-463/igt@kms_psr@fbc-psr2-sprite-plane-move.html
* igt@sriov_basic@bind-unbind-vf:
- shard-dg2-set2: NOTRUN -> [SKIP][28] ([Intel XE#1091] / [Intel XE#1201])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-464/igt@sriov_basic@bind-unbind-vf.html
* igt@xe_compute@ccs-mode-basic:
- shard-dg2-set2: NOTRUN -> [FAIL][29] ([Intel XE#1050])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-433/igt@xe_compute@ccs-mode-basic.html
* igt@xe_copy_basic@mem-set-linear-0x369:
- shard-dg2-set2: NOTRUN -> [SKIP][30] ([Intel XE#1126] / [Intel XE#1201])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0x369.html
* igt@xe_evict@evict-beng-large-multi-vm-cm:
- shard-dg2-set2: [PASS][31] -> [FAIL][32] ([Intel XE#1600])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-463/igt@xe_evict@evict-beng-large-multi-vm-cm.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-435/igt@xe_evict@evict-beng-large-multi-vm-cm.html
* igt@xe_evict@evict-threads-large:
- shard-dg2-set2: [PASS][33] -> [TIMEOUT][34] ([Intel XE#1473] / [Intel XE#392]) +1 other test timeout
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-464/igt@xe_evict@evict-threads-large.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-434/igt@xe_evict@evict-threads-large.html
* igt@xe_exec_fault_mode@once-basic-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][35] ([Intel XE#1201] / [Intel XE#288]) +6 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-463/igt@xe_exec_fault_mode@once-basic-imm.html
* igt@xe_gt_freq@freq_fixed_exec:
- shard-dg2-set2: NOTRUN -> [FAIL][36] ([Intel XE#1414])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-436/igt@xe_gt_freq@freq_fixed_exec.html
* igt@xe_pm@s3-basic-exec:
- shard-dg2-set2: [PASS][37] -> [DMESG-WARN][38] ([Intel XE#1214] / [Intel XE#1551] / [Intel XE#569])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-436/igt@xe_pm@s3-basic-exec.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-436/igt@xe_pm@s3-basic-exec.html
* igt@xe_query@multigpu-query-topology-l3-bank-mask:
- shard-dg2-set2: NOTRUN -> [SKIP][39] ([Intel XE#1201] / [Intel XE#944])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-433/igt@xe_query@multigpu-query-topology-l3-bank-mask.html
#### Possible fixes ####
* igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs:
- {shard-lnl}: [FAIL][40] ([Intel XE#1701]) -> [PASS][41] +1 other test pass
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-lnl-1/igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-lnl-6/igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs.html
* igt@kms_flip@flip-vs-suspend@a-hdmi-a6:
- shard-dg2-set2: [DMESG-WARN][42] ([Intel XE#1214] / [Intel XE#1551]) -> [PASS][43] +3 other tests pass
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-463/igt@kms_flip@flip-vs-suspend@a-hdmi-a6.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-434/igt@kms_flip@flip-vs-suspend@a-hdmi-a6.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: [SKIP][44] ([Intel XE#1201] / [Intel XE#455]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-466/igt@kms_hdr@invalid-hdr.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
* igt@kms_psr@psr2-suspend:
- {shard-lnl}: [DMESG-WARN][46] ([Intel XE#2052]) -> [PASS][47] +1 other test pass
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-lnl-7/igt@kms_psr@psr2-suspend.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-lnl-4/igt@kms_psr@psr2-suspend.html
* igt@kms_sequence@get-forked-busy:
- shard-dg2-set2: [INCOMPLETE][48] ([Intel XE#1195]) -> [PASS][49] +3 other tests pass
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-466/igt@kms_sequence@get-forked-busy.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-464/igt@kms_sequence@get-forked-busy.html
* igt@xe_evict@evict-beng-cm-threads-large:
- shard-dg2-set2: [INCOMPLETE][50] ([Intel XE#1195] / [Intel XE#1473]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-436/igt@xe_evict@evict-beng-cm-threads-large.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-464/igt@xe_evict@evict-beng-cm-threads-large.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-dg2-set2: [TIMEOUT][52] ([Intel XE#1473] / [Intel XE#402]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-466/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_evict@evict-cm-threads-large:
- shard-dg2-set2: [INCOMPLETE][54] ([Intel XE#1195] / [Intel XE#1473] / [Intel XE#392]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-466/igt@xe_evict@evict-cm-threads-large.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-435/igt@xe_evict@evict-cm-threads-large.html
* igt@xe_evict@evict-large-multi-vm-cm:
- shard-dg2-set2: [FAIL][56] ([Intel XE#1600]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-436/igt@xe_evict@evict-large-multi-vm-cm.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-436/igt@xe_evict@evict-large-multi-vm-cm.html
* igt@xe_exec_reset@close-fd:
- {shard-lnl}: [DMESG-WARN][58] ([Intel XE#1638]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-lnl-1/igt@xe_exec_reset@close-fd.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-lnl-3/igt@xe_exec_reset@close-fd.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-dg2-set2: [TIMEOUT][60] ([Intel XE#2105]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-433/igt@xe_exec_reset@parallel-gt-reset.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-463/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_gt_freq@freq_range_idle:
- {shard-lnl}: [SKIP][62] ([Intel XE#1462]) -> [PASS][63] +1 other test pass
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-lnl-8/igt@xe_gt_freq@freq_range_idle.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-lnl-6/igt@xe_gt_freq@freq_range_idle.html
* igt@xe_live_ktest@xe_dma_buf:
- shard-dg2-set2: [SKIP][64] ([Intel XE#1192] / [Intel XE#1201]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-466/igt@xe_live_ktest@xe_dma_buf.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-435/igt@xe_live_ktest@xe_dma_buf.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-dg2-set2: [DMESG-WARN][66] ([Intel XE#1162] / [Intel XE#1214] / [Intel XE#1941]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-436/igt@xe_pm@s3-vm-bind-unbind-all.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-435/igt@xe_pm@s3-vm-bind-unbind-all.html
* igt@xe_pm@s4-exec-after:
- {shard-lnl}: [ABORT][68] ([Intel XE#1358] / [Intel XE#1607]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-lnl-2/igt@xe_pm@s4-exec-after.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-lnl-4/igt@xe_pm@s4-exec-after.html
#### Warnings ####
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b:
- shard-dg2-set2: [FAIL][70] ([Intel XE#616]) -> [DMESG-FAIL][71] ([Intel XE#1551]) +1 other test dmesg-fail
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-466/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-466/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html
* igt@xe_evict@evict-beng-mixed-many-threads-large:
- shard-dg2-set2: [TIMEOUT][72] ([Intel XE#1041] / [Intel XE#1473] / [Intel XE#392]) -> [INCOMPLETE][73] ([Intel XE#1195] / [Intel XE#1473])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7907/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-large.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/shard-dg2-463/igt@xe_evict@evict-beng-mixed-many-threads-large.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1041]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1041
[Intel XE#1050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1050
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1131
[Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
[Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
[Intel XE#1162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1162
[Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
[Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
[Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
[Intel XE#1214]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1214
[Intel XE#1330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1330
[Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1413
[Intel XE#1414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1414
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1430
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1437
[Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
[Intel XE#1450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1450
[Intel XE#1462]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1462
[Intel XE#1465]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1465
[Intel XE#1466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1466
[Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
[Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1504
[Intel XE#1551]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1551
[Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
[Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
[Intel XE#1638]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1638
[Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659
[Intel XE#1701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1701
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#1760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1760
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#1941]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1941
[Intel XE#2052]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2052
[Intel XE#2097]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2097
[Intel XE#2105]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2105
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/294
[Intel XE#305]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/305
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
[Intel XE#361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/361
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/374
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#379]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/379
[Intel XE#392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/392
[Intel XE#402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/402
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498
[Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
[Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
[Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
[Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
[Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#660]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/660
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_7907 -> IGTPW_11332
* Linux: xe-1538-42f35e623e6590cf8ec493373e4664ae4e32123c -> xe-1542-886eeb6d89b58f914ee5045fcac54b59a73d8299
IGTPW_11332: 11332
IGT_7907: 676b8e660cadae8ffb29a45b12ad5b53ef228b6a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-1538-42f35e623e6590cf8ec493373e4664ae4e32123c: 42f35e623e6590cf8ec493373e4664ae4e32123c
xe-1542-886eeb6d89b58f914ee5045fcac54b59a73d8299: 886eeb6d89b58f914ee5045fcac54b59a73d8299
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11332/index.html
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