* [PATCH i-g-t v3 0/1] tests/intel/xe_exec_capture: Add xe_exec_capture test
@ 2024-10-15 15:31 Zhanjun Dong
2024-10-15 15:31 ` [PATCH i-g-t v3 1/1] " Zhanjun Dong
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Zhanjun Dong @ 2024-10-15 15:31 UTC (permalink / raw)
To: igt-dev; +Cc: Zhanjun Dong, Peter Senna Tschudin, Kamil Konieczny, Alan Previn
Test with GuC reset, check if devcoredump register dump is within the
range.
Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
Cc: Peter Senna Tschudin <peter.senna@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Changes from prior revs:
v3:- Remove call to bash and awk
Add regular express parse
Detect devcoredump through card index
Add devcoredump removal check
v2:- Fix CI.build error
Add multiple GPU card support
Zhanjun Dong (1):
tests/intel/xe_exec_capture: Add xe_exec_capture test
tests/intel/xe_exec_capture.c | 308 ++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
2 files changed, 309 insertions(+)
create mode 100644 tests/intel/xe_exec_capture.c
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH i-g-t v3 1/1] tests/intel/xe_exec_capture: Add xe_exec_capture test
2024-10-15 15:31 [PATCH i-g-t v3 0/1] tests/intel/xe_exec_capture: Add xe_exec_capture test Zhanjun Dong
@ 2024-10-15 15:31 ` Zhanjun Dong
2024-10-16 5:29 ` Peter Senna Tschudin
2024-10-16 14:12 ` Kamil Konieczny
2024-10-15 20:29 ` ✓ CI.xeBAT: success for " Patchwork
` (2 subsequent siblings)
3 siblings, 2 replies; 9+ messages in thread
From: Zhanjun Dong @ 2024-10-15 15:31 UTC (permalink / raw)
To: igt-dev; +Cc: Zhanjun Dong
Test with GuC reset, check if devcoredump register dump is within the
range.
Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
---
tests/intel/xe_exec_capture.c | 308 ++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
2 files changed, 309 insertions(+)
create mode 100644 tests/intel/xe_exec_capture.c
diff --git a/tests/intel/xe_exec_capture.c b/tests/intel/xe_exec_capture.c
new file mode 100644
index 000000000..89b544c93
--- /dev/null
+++ b/tests/intel/xe_exec_capture.c
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+/**
+ * TEST: Basic tests for GuC based register capture
+ * Category: Core
+ * Mega feature: General Core features
+ * Sub-category: CMD submission
+ * Functionality: Debug
+ * Test category: functionality test
+ */
+
+#include <ctype.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <regex.h>
+
+#include "igt.h"
+#include "igt_device.h"
+#include "lib/igt_syncobj.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include "xe/xe_spin.h"
+
+#define MAX_N_EXECQUEUES 16
+#define MAX_INSTANCE 9
+#define GT_RESET (0x1 << 0)
+#define CLOSE_FD (0x1 << 1)
+#define CLOSE_EXEC_QUEUES (0x1 << 2)
+#define VIRTUAL (0x1 << 3)
+#define PARALLEL (0x1 << 4)
+#define CAT_ERROR (0x1 << 5)
+
+#define BASE_ADDRESS 0x1a0000
+/* Batch buffer element count, in number of dwords(uint32_t) */
+#define BATCH_DW_COUNT 16
+
+#define MAX_PATH_NAME_LEN 512
+#define MAX_LINES 512
+#define MAX_LINE_LEN 1024
+
+#define DUMP_PATH "/sys/class/drm/card%d/device/devcoredump/data"
+#define START_TAG "**** Job ****"
+#define REGEX_KEY_VALUE_PAIR "^[ \t]*([^:]+):[ \t]*([^ \t]+)[ \t]*$"
+#define REGEX_KEY_INDEX 1
+#define REGEX_VALUE_INDEX 2
+#define REGEX_KEY_VALUE_MATCH_COUNT 3
+
+int card_id;
+regex_t regex;
+char lines[MAX_LINES][MAX_LINE_LEN];
+
+static bool access_devcoredump(bool load_file)
+{
+ FILE *fd;
+ char path[MAX_PATH_NAME_LEN];
+
+ sprintf(path, DUMP_PATH, card_id);
+ fd = fopen(path, "r");
+ if (!fd) {
+ igt_debug("Devcoredump not exist.\n");
+ return false;
+ }
+ igt_debug("Devcoredump found: %s\n", path);
+
+ /* Clear memory before load file */
+ if (load_file) {
+ int i = 0;
+ bool found = false;
+
+ memset(lines, 0, sizeof(lines));
+ while (!feof(fd)) {
+ fgets(lines[i], MAX_LINE_LEN, fd);
+
+ /* Only save lines after start tag */
+ if (!found)
+ found = strstr(lines[0], START_TAG);
+ else
+ if (++i >= MAX_LINES)
+ break;
+ }
+ }
+
+ fclose(fd);
+ return true;
+}
+
+static void rm_devcoredump(void)
+{
+ char path[MAX_PATH_NAME_LEN];
+ int fd;
+
+ igt_debug("Clearing devcoredump.\n");
+
+ sprintf(path, DUMP_PATH, card_id);
+ fd = open(path, O_WRONLY);
+ if (fd != -1) {
+ write(fd, "0", 1);
+ close(fd);
+ }
+}
+
+static char *get_coredump_item(const char *tag)
+{
+ int i;
+ regmatch_t match[REGEX_KEY_VALUE_MATCH_COUNT];
+
+ for (i = 0; i < MAX_LINES && lines[i][0]; i++) {
+ char *line = lines[i];
+
+ /* Skip lines without tag */
+ if (!strstr(line, tag))
+ continue;
+
+ if (regexec(®ex, line, REGEX_KEY_VALUE_MATCH_COUNT, match, 0) == 0) {
+ char *key, *value;
+
+ key = &line[match[REGEX_KEY_INDEX].rm_so];
+ line[match[REGEX_KEY_INDEX].rm_eo] = '\0';
+ value = &line[match[REGEX_VALUE_INDEX].rm_so];
+ line[match[REGEX_VALUE_INDEX].rm_eo] = '\0';
+
+ if (strcmp(tag, key) == 0)
+ return value;
+ /* if key != tag, continue */
+ }
+ }
+
+ return NULL;
+}
+
+static void check_capture_output(const char *tag, uint64_t addr_lo, uint64_t addr_hi)
+{
+ uint64_t result;
+ char *output;
+
+ igt_assert(output = get_coredump_item(tag));
+ result = strtol(output, NULL, 16);
+ igt_debug("Compare %s: %s vs [0x%lX-0x%lX]\n", tag, output, addr_lo, addr_hi);
+ igt_assert((addr_lo <= result) && (result <= addr_hi));
+}
+
+static void check_capture_output_str(const char *tag, const char *target)
+{
+ char *output;
+
+ igt_assert(output = get_coredump_item(tag));
+ igt_debug("Compare %s: '%s' vs '%s'\n", tag, output, target);
+ igt_assert(!strcmp(output, target));
+}
+
+static void check_capture_out(uint64_t base_addr, uint64_t length)
+{
+ /* assert devcoredump created */
+ assert(access_devcoredump(true));
+
+ check_capture_output_str("Capture_source", "GuC");
+ check_capture_output("ACTHD", base_addr, base_addr + length);
+ check_capture_output("RING_BBADDR", base_addr, base_addr + length);
+
+ /* clear devcoredump */
+ rm_devcoredump();
+ sleep(1);
+ /* Assert devcoredump removed */
+ assert(!access_devcoredump(false));
+}
+
+/**
+ * SUBTEST: close-fd
+ * Description: Test close fd, check if devcoredump register dump is within the
+ */
+static void
+test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
+ int n_exec_queues, int n_execs, unsigned int flags)
+{
+ uint32_t vm;
+ const uint64_t addr = BASE_ADDRESS;
+ struct drm_xe_sync sync[2] = {
+ { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
+ };
+ struct drm_xe_exec exec = {
+ .num_batch_buffer = 1,
+ .num_syncs = 2,
+ .syncs = to_user_pointer(sync),
+ };
+ uint32_t exec_queues[MAX_N_EXECQUEUES];
+ uint32_t syncobjs[MAX_N_EXECQUEUES];
+ size_t bo_size;
+ uint32_t bo = 0;
+ struct {
+ struct xe_spin spin;
+ uint32_t batch[BATCH_DW_COUNT];
+ uint64_t pad;
+ uint32_t data;
+ } *data;
+ struct xe_spin_opts spin_opts = { .preempt = false };
+ int i, b;
+
+ igt_assert(n_exec_queues <= MAX_N_EXECQUEUES);
+
+ if (flags & CLOSE_FD)
+ fd = drm_open_driver(DRIVER_XE);
+
+ vm = xe_vm_create(fd, 0, 0);
+ bo_size = sizeof(*data) * n_execs;
+ bo_size = xe_bb_size(fd, bo_size);
+
+ bo = xe_bo_create(fd, vm, bo_size,
+ vram_if_possible(fd, eci->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+ data = xe_bo_map(fd, bo, bo_size);
+
+ for (i = 0; i < n_exec_queues; i++) {
+ exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0);
+ syncobjs[i] = syncobj_create(fd, 0);
+ };
+
+ sync[0].handle = syncobj_create(fd, 0);
+ xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1);
+
+ for (i = 0; i < n_execs; i++) {
+ uint64_t base_addr = addr;
+ uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
+ uint64_t batch_addr = base_addr + batch_offset;
+ uint64_t spin_offset = (char *)&data[i].spin - (char *)data;
+ uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
+ uint64_t sdi_addr = base_addr + sdi_offset;
+ uint64_t exec_addr;
+ int e = i % n_exec_queues;
+
+ if (!i) {
+ spin_opts.addr = base_addr + spin_offset;
+ xe_spin_init(&data[i].spin, &spin_opts);
+ exec_addr = spin_opts.addr;
+ } else {
+ b = 0;
+ data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+ data[i].batch[b++] = sdi_addr;
+ data[i].batch[b++] = sdi_addr >> 32;
+ data[i].batch[b++] = 0xc0ffee;
+ data[i].batch[b++] = MI_BATCH_BUFFER_END;
+ igt_assert(b <= ARRAY_SIZE(data[i].batch));
+
+ exec_addr = batch_addr;
+ }
+
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].handle = syncobjs[e];
+
+ exec.exec_queue_id = exec_queues[e];
+ exec.address = exec_addr;
+ if (e != i)
+ syncobj_reset(fd, &syncobjs[e], 1);
+ xe_exec(fd, &exec);
+ }
+
+ for (i = 0; i < n_exec_queues && n_execs; i++)
+ igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0,
+ NULL));
+ igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+ xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
+ igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+ syncobj_destroy(fd, sync[0].handle);
+ for (i = 0; i < n_exec_queues; i++) {
+ syncobj_destroy(fd, syncobjs[i]);
+ xe_exec_queue_destroy(fd, exec_queues[i]);
+ }
+
+ munmap(data, bo_size);
+ gem_close(fd, bo);
+ xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ card_id = igt_device_get_card_index(fd);
+
+ regcomp(®ex, REGEX_KEY_VALUE_PAIR, REG_EXTENDED | REG_NEWLINE);
+ }
+
+ igt_subtest("close-fd")
+ xe_for_each_engine(fd, hwe) {
+ igt_debug("Running on engine class: %x instance: %x\n", hwe->engine_class,
+ hwe->engine_instance);
+
+ test_legacy_mode(fd, hwe, 1, 1, 0);
+ check_capture_out(BASE_ADDRESS, sizeof(uint32_t) * BATCH_DW_COUNT);
+ }
+
+ igt_fixture {
+ drm_close_driver(fd);
+ regfree(®ex);
+ }
+}
diff --git a/tests/meson.build b/tests/meson.build
index 2d8cb87d5..b724a7c6d 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -284,6 +284,7 @@ intel_xe_progs = [
'xe_exec_atomic',
'xe_exec_balancer',
'xe_exec_basic',
+ 'xe_exec_capture',
'xe_exec_compute_mode',
'xe_exec_fault_mode',
'xe_exec_mix_modes',
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ CI.xeBAT: success for tests/intel/xe_exec_capture: Add xe_exec_capture test
2024-10-15 15:31 [PATCH i-g-t v3 0/1] tests/intel/xe_exec_capture: Add xe_exec_capture test Zhanjun Dong
2024-10-15 15:31 ` [PATCH i-g-t v3 1/1] " Zhanjun Dong
@ 2024-10-15 20:29 ` Patchwork
2024-10-15 20:41 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-10-16 7:48 ` ✗ CI.xeFULL: " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2024-10-15 20:29 UTC (permalink / raw)
To: Zhanjun Dong; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 5487 bytes --]
== Series Details ==
Series: tests/intel/xe_exec_capture: Add xe_exec_capture test
URL : https://patchwork.freedesktop.org/series/140007/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_8074_BAT -> XEIGTPW_11914_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in XEIGTPW_11914_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@xe_evict@evict-beng-mixed-threads-small-multi-vm:
- bat-adlp-vf: NOTRUN -> [SKIP][1] ([Intel XE#261] / [Intel XE#688]) +15 other tests skip
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-vf/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html
* igt@xe_evict@evict-beng-small:
- bat-adlp-7: NOTRUN -> [SKIP][2] ([Intel XE#261] / [Intel XE#688]) +15 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-7/igt@xe_evict@evict-beng-small.html
* igt@xe_exec_fault_mode@twice-rebind:
- bat-adlp-vf: NOTRUN -> [SKIP][3] ([Intel XE#288]) +32 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-vf/igt@xe_exec_fault_mode@twice-rebind.html
* igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch:
- bat-adlp-7: NOTRUN -> [SKIP][4] ([Intel XE#288]) +32 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-7/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html
* igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
- bat-adlp-vf: NOTRUN -> [SKIP][5] ([Intel XE#2229]) +2 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-vf/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
- bat-adlp-7: NOTRUN -> [SKIP][6] ([Intel XE#2229])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-7/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
* igt@xe_mmap@vram:
- bat-adlp-vf: NOTRUN -> [SKIP][7] ([Intel XE#1008])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-vf/igt@xe_mmap@vram.html
* igt@xe_pat@pat-index-xe2:
- bat-adlp-vf: NOTRUN -> [SKIP][8] ([Intel XE#977])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-vf/igt@xe_pat@pat-index-xe2.html
* igt@xe_pat@pat-index-xehpc:
- bat-adlp-vf: NOTRUN -> [SKIP][9] ([Intel XE#2838] / [Intel XE#979])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-vf/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pat@pat-index-xelpg:
- bat-adlp-vf: NOTRUN -> [SKIP][10] ([Intel XE#979])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-vf/igt@xe_pat@pat-index-xelpg.html
* igt@xe_pm_residency@gt-c6-on-idle:
- bat-adlp-vf: NOTRUN -> [SKIP][11] ([Intel XE#2468])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-vf/igt@xe_pm_residency@gt-c6-on-idle.html
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-lnl-1: [FAIL][12] ([Intel XE#886]) -> [PASS][13] +1 other test pass
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@xe_intel_bb@render@render-linear-256:
- bat-adlp-vf: [ABORT][14] -> [PASS][15] +1 other test pass
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/bat-adlp-vf/igt@xe_intel_bb@render@render-linear-256.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-vf/igt@xe_intel_bb@render@render-linear-256.html
* igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit:
- bat-adlp-7: [INCOMPLETE][16] ([Intel XE#2874]) -> [PASS][17] +1 other test pass
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/bat-adlp-7/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/bat-adlp-7/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html
[Intel XE#1008]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1008
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2468]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2468
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
[Intel XE#2874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2874
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
[Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
Build changes
-------------
* IGT: IGT_8074 -> IGTPW_11914
IGTPW_11914: 11914
IGT_8074: a886e0ad97832dc2ba9b85d35bca22e667c15105 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2070-01c7b2c084e5c84313f382734c10945b9aa49823: 01c7b2c084e5c84313f382734c10945b9aa49823
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/index.html
[-- Attachment #2: Type: text/html, Size: 6706 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for tests/intel/xe_exec_capture: Add xe_exec_capture test
2024-10-15 15:31 [PATCH i-g-t v3 0/1] tests/intel/xe_exec_capture: Add xe_exec_capture test Zhanjun Dong
2024-10-15 15:31 ` [PATCH i-g-t v3 1/1] " Zhanjun Dong
2024-10-15 20:29 ` ✓ CI.xeBAT: success for " Patchwork
@ 2024-10-15 20:41 ` Patchwork
2024-10-16 7:48 ` ✗ CI.xeFULL: " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2024-10-15 20:41 UTC (permalink / raw)
To: Zhanjun Dong; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 3005 bytes --]
== Series Details ==
Series: tests/intel/xe_exec_capture: Add xe_exec_capture test
URL : https://patchwork.freedesktop.org/series/140007/
State : failure
== Summary ==
CI Bug Log - changes from IGT_8074 -> IGTPW_11914
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_11914 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_11914, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11914/index.html
Participating hosts (42 -> 41)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_11914:
### IGT changes ###
#### Possible regressions ####
* igt@kms_chamelium_edid@dp-edid-read:
- bat-dg2-13: NOTRUN -> [ABORT][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11914/bat-dg2-13/igt@kms_chamelium_edid@dp-edid-read.html
Known issues
------------
Here are the changes found in IGTPW_11914 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][2] -> [SKIP][3] ([i915#9197]) +2 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8074/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11914/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
#### Possible fixes ####
* igt@i915_selftest@live:
- bat-arlh-2: [DMESG-FAIL][4] ([i915#10341]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8074/bat-arlh-2/igt@i915_selftest@live.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11914/bat-arlh-2/igt@i915_selftest@live.html
* igt@i915_selftest@live@hangcheck:
- bat-arlh-2: [DMESG-FAIL][6] -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8074/bat-arlh-2/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11914/bat-arlh-2/igt@i915_selftest@live@hangcheck.html
[i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_8074 -> IGTPW_11914
CI-20190529: 20190529
CI_DRM_15538: 01c7b2c084e5c84313f382734c10945b9aa49823 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_11914: 11914
IGT_8074: a886e0ad97832dc2ba9b85d35bca22e667c15105 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11914/index.html
[-- Attachment #2: Type: text/html, Size: 3698 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH i-g-t v3 1/1] tests/intel/xe_exec_capture: Add xe_exec_capture test
2024-10-15 15:31 ` [PATCH i-g-t v3 1/1] " Zhanjun Dong
@ 2024-10-16 5:29 ` Peter Senna Tschudin
2024-10-16 19:08 ` Dong, Zhanjun
2024-10-16 14:12 ` Kamil Konieczny
1 sibling, 1 reply; 9+ messages in thread
From: Peter Senna Tschudin @ 2024-10-16 5:29 UTC (permalink / raw)
To: Zhanjun Dong, igt-dev
Dear Zhanjun Dong,
Thank you for the patch! Please see my comments bellow.
On 15.10.2024 17:31, Zhanjun Dong wrote:
> Test with GuC reset, check if devcoredump register dump is within the
> range.
>
> Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
> ---
> tests/intel/xe_exec_capture.c | 308 ++++++++++++++++++++++++++++++++++
> tests/meson.build | 1 +
> 2 files changed, 309 insertions(+)
> create mode 100644 tests/intel/xe_exec_capture.c
>
> diff --git a/tests/intel/xe_exec_capture.c b/tests/intel/xe_exec_capture.c
> new file mode 100644
> index 000000000..89b544c93
> --- /dev/null
> +++ b/tests/intel/xe_exec_capture.c
> @@ -0,0 +1,308 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +/**
> + * TEST: Basic tests for GuC based register capture
> + * Category: Core
> + * Mega feature: General Core features
> + * Sub-category: CMD submission
> + * Functionality: Debug
> + * Test category: functionality test
> + */
> +
> +#include <ctype.h>
> +#include <fcntl.h>
> +#include <stdio.h>
> +#include <regex.h>
> +
> +#include "igt.h"
> +#include "igt_device.h"
> +#include "lib/igt_syncobj.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include "xe/xe_spin.h"
> +
> +#define MAX_N_EXECQUEUES 16
> +#define MAX_INSTANCE 9
> +#define GT_RESET (0x1 << 0)
> +#define CLOSE_FD (0x1 << 1)
> +#define CLOSE_EXEC_QUEUES (0x1 << 2)
> +#define VIRTUAL (0x1 << 3)
> +#define PARALLEL (0x1 << 4)
> +#define CAT_ERROR (0x1 << 5)
> +
> +#define BASE_ADDRESS 0x1a0000
> +/* Batch buffer element count, in number of dwords(uint32_t) */
> +#define BATCH_DW_COUNT 16
> +
> +#define MAX_PATH_NAME_LEN 512
> +#define MAX_LINES 512
> +#define MAX_LINE_LEN 1024
> +
> +#define DUMP_PATH "/sys/class/drm/card%d/device/devcoredump/data"
> +#define START_TAG "**** Job ****"
> +#define REGEX_KEY_VALUE_PAIR "^[ \t]*([^:]+):[ \t]*([^ \t]+)[ \t]*$"
> +#define REGEX_KEY_INDEX 1
> +#define REGEX_VALUE_INDEX 2
> +#define REGEX_KEY_VALUE_MATCH_COUNT 3
> +
> +int card_id;
If I am not mistaken, there are cases in which we have more than one card, and that we want to test more than one card. So I guess the logic does not work if card_id is global. I prefer not using global variables.
> +regex_t regex;
> +char lines[MAX_LINES][MAX_LINE_LEN];
Can you rewrite and not use global variables? regex could live on igt_main().
> +
> +static bool access_devcoredump(bool load_file)
> +{
> + FILE *fd;
> + char path[MAX_PATH_NAME_LEN];
> +
> + sprintf(path, DUMP_PATH, card_id);
> + fd = fopen(path, "r");
> + if (!fd) {
> + igt_debug("Devcoredump not exist.\n");
> + return false;
> + }
> + igt_debug("Devcoredump found: %s\n", path);
> +
> + /* Clear memory before load file */
> + if (load_file) {
> + int i = 0;
> + bool found = false;
> +
> + memset(lines, 0, sizeof(lines));
> + while (!feof(fd)) {
> + fgets(lines[i], MAX_LINE_LEN, fd);
> +
> + /* Only save lines after start tag */
> + if (!found)
> + found = strstr(lines[0], START_TAG);
i instead of 0? found = strstr(lines[i], START_TAG); ?
> + else
> + if (++i >= MAX_LINES)
> + break;
> + }
> + }
> +
> + fclose(fd);
> + return true;
> +}
> +
> +static void rm_devcoredump(void)
> +{
> + char path[MAX_PATH_NAME_LEN];
> + int fd;
> +
> + igt_debug("Clearing devcoredump.\n");
> +
> + sprintf(path, DUMP_PATH, card_id);
> + fd = open(path, O_WRONLY);
> + if (fd != -1) {
> + write(fd, "0", 1);
> + close(fd);
> + }
> +}
> +
> +static char *get_coredump_item(const char *tag)
> +{
> + int i;
> + regmatch_t match[REGEX_KEY_VALUE_MATCH_COUNT];
> +
> + for (i = 0; i < MAX_LINES && lines[i][0]; i++) {
> + char *line = lines[i];
> +
> + /* Skip lines without tag */
> + if (!strstr(line, tag))
> + continue;
> +
> + if (regexec(®ex, line, REGEX_KEY_VALUE_MATCH_COUNT, match, 0) == 0) {
> + char *key, *value;
> +
> + key = &line[match[REGEX_KEY_INDEX].rm_so];
> + line[match[REGEX_KEY_INDEX].rm_eo] = '\0';
> + value = &line[match[REGEX_VALUE_INDEX].rm_so];
> + line[match[REGEX_VALUE_INDEX].rm_eo] = '\0';
> +
> + if (strcmp(tag, key) == 0)
> + return value;
> + /* if key != tag, continue */
Can remove or expand the comment?
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static void check_capture_output(const char *tag, uint64_t addr_lo, uint64_t addr_hi)
> +{
> + uint64_t result;
> + char *output;
> +
> + igt_assert(output = get_coredump_item(tag));
> + result = strtol(output, NULL, 16);
strtoull() ?
> + igt_debug("Compare %s: %s vs [0x%lX-0x%lX]\n", tag, output, addr_lo, addr_hi);
0x%llX ?
> + igt_assert((addr_lo <= result) && (result <= addr_hi));
> +}
> +
> +static void check_capture_output_str(const char *tag, const char *target)
> +{
> + char *output;
> +
> + igt_assert(output = get_coredump_item(tag));
> + igt_debug("Compare %s: '%s' vs '%s'\n", tag, output, target);
> + igt_assert(!strcmp(output, target));
> +}
> +
> +static void check_capture_out(uint64_t base_addr, uint64_t length)
> +{
> + /* assert devcoredump created */
> + assert(access_devcoredump(true));
> +
> + check_capture_output_str("Capture_source", "GuC");
> + check_capture_output("ACTHD", base_addr, base_addr + length);
> + check_capture_output("RING_BBADDR", base_addr, base_addr + length);
> +
> + /* clear devcoredump */
> + rm_devcoredump();
> + sleep(1);
> + /* Assert devcoredump removed */
> + assert(!access_devcoredump(false));
> +}
> +
> +/**
> + * SUBTEST: close-fd
> + * Description: Test close fd, check if devcoredump register dump is within the
> + */
> +static void
> +test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
> + int n_exec_queues, int n_execs, unsigned int flags)
> +{
> + uint32_t vm;
> + const uint64_t addr = BASE_ADDRESS;
> + struct drm_xe_sync sync[2] = {
> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> + };
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 2,
> + .syncs = to_user_pointer(sync),
> + };
> + uint32_t exec_queues[MAX_N_EXECQUEUES];
> + uint32_t syncobjs[MAX_N_EXECQUEUES];
> + size_t bo_size;
> + uint32_t bo = 0;
> + struct {
> + struct xe_spin spin;
> + uint32_t batch[BATCH_DW_COUNT];
> + uint64_t pad;
> + uint32_t data;
> + } *data;
> + struct xe_spin_opts spin_opts = { .preempt = false };
> + int i, b;
> +
> + igt_assert(n_exec_queues <= MAX_N_EXECQUEUES);
> +
> + if (flags & CLOSE_FD)
> + fd = drm_open_driver(DRIVER_XE);
> +
> + vm = xe_vm_create(fd, 0, 0);
> + bo_size = sizeof(*data) * n_execs;
> + bo_size = xe_bb_size(fd, bo_size);
> +
> + bo = xe_bo_create(fd, vm, bo_size,
> + vram_if_possible(fd, eci->gt_id),
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + data = xe_bo_map(fd, bo, bo_size);
> +
> + for (i = 0; i < n_exec_queues; i++) {
> + exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0);
> + syncobjs[i] = syncobj_create(fd, 0);
> + };
> +
> + sync[0].handle = syncobj_create(fd, 0);
> + xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1);
> +
> + for (i = 0; i < n_execs; i++) {
> + uint64_t base_addr = addr;
> + uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
> + uint64_t batch_addr = base_addr + batch_offset;
> + uint64_t spin_offset = (char *)&data[i].spin - (char *)data;
> + uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
> + uint64_t sdi_addr = base_addr + sdi_offset;
> + uint64_t exec_addr;
> + int e = i % n_exec_queues;
> +
> + if (!i) {
> + spin_opts.addr = base_addr + spin_offset;
> + xe_spin_init(&data[i].spin, &spin_opts);
> + exec_addr = spin_opts.addr;
> + } else {
> + b = 0;
> + data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> + data[i].batch[b++] = sdi_addr;
> + data[i].batch[b++] = sdi_addr >> 32;
> + data[i].batch[b++] = 0xc0ffee;
> + data[i].batch[b++] = MI_BATCH_BUFFER_END;
> + igt_assert(b <= ARRAY_SIZE(data[i].batch));
> +
> + exec_addr = batch_addr;
> + }
> +
> + sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> + sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + sync[1].handle = syncobjs[e];
> +
> + exec.exec_queue_id = exec_queues[e];
> + exec.address = exec_addr;
> + if (e != i)
> + syncobj_reset(fd, &syncobjs[e], 1);
> + xe_exec(fd, &exec);
> + }
> +
> + for (i = 0; i < n_exec_queues && n_execs; i++)
> + igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0,
> + NULL));
> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + syncobj_destroy(fd, sync[0].handle);
> + for (i = 0; i < n_exec_queues; i++) {
> + syncobj_destroy(fd, syncobjs[i]);
> + xe_exec_queue_destroy(fd, exec_queues[i]);
> + }
> +
> + munmap(data, bo_size);
> + gem_close(fd, bo);
> + xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + card_id = igt_device_get_card_index(fd);
> +
> + regcomp(®ex, REGEX_KEY_VALUE_PAIR, REG_EXTENDED | REG_NEWLINE);
> + }
> +
> + igt_subtest("close-fd")
> + xe_for_each_engine(fd, hwe) {
> + igt_debug("Running on engine class: %x instance: %x\n", hwe->engine_class,
> + hwe->engine_instance);
> +
> + test_legacy_mode(fd, hwe, 1, 1, 0);
> + check_capture_out(BASE_ADDRESS, sizeof(uint32_t) * BATCH_DW_COUNT);
> + }
> +
> + igt_fixture {
> + drm_close_driver(fd);
> + regfree(®ex);
> + }
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index 2d8cb87d5..b724a7c6d 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -284,6 +284,7 @@ intel_xe_progs = [
> 'xe_exec_atomic',
> 'xe_exec_balancer',
> 'xe_exec_basic',
> + 'xe_exec_capture',
> 'xe_exec_compute_mode',
> 'xe_exec_fault_mode',
> 'xe_exec_mix_modes',
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ CI.xeFULL: failure for tests/intel/xe_exec_capture: Add xe_exec_capture test
2024-10-15 15:31 [PATCH i-g-t v3 0/1] tests/intel/xe_exec_capture: Add xe_exec_capture test Zhanjun Dong
` (2 preceding siblings ...)
2024-10-15 20:41 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2024-10-16 7:48 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2024-10-16 7:48 UTC (permalink / raw)
To: Zhanjun Dong; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 64753 bytes --]
== Series Details ==
Series: tests/intel/xe_exec_capture: Add xe_exec_capture test
URL : https://patchwork.freedesktop.org/series/140007/
State : failure
== Summary ==
CI Bug Log - changes from XEIGT_8074_full -> XEIGTPW_11914_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with XEIGTPW_11914_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in XEIGTPW_11914_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in XEIGTPW_11914_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
- shard-dg2-set2: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
* igt@xe_exec_capture@close-fd (NEW):
- {shard-bmg}: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-8/igt@xe_exec_capture@close-fd.html
- shard-dg2-set2: NOTRUN -> [FAIL][4] +1 other test fail
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@xe_exec_capture@close-fd.html
- shard-lnl: NOTRUN -> [FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-8/igt@xe_exec_capture@close-fd.html
* igt@xe_module_load@many-reload:
- shard-lnl: [PASS][6] -> [ABORT][7]
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-1/igt@xe_module_load@many-reload.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-3/igt@xe_module_load@many-reload.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- {shard-bmg}: [SKIP][8] ([Intel XE#2252]) -> [SKIP][9]
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-8/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-8/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- {shard-bmg}: [SKIP][10] ([Intel XE#2320]) -> [SKIP][11]
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-4/igt@kms_cursor_crc@cursor-offscreen-max-size.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-8/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_vblank@wait-idle-hang:
- {shard-bmg}: [PASS][12] -> [SKIP][13] +5 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-5/igt@kms_vblank@wait-idle-hang.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-8/igt@kms_vblank@wait-idle-hang.html
* igt@xe_pm@s2idle-exec-after:
- {shard-bmg}: [PASS][14] -> [INCOMPLETE][15]
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-5/igt@xe_pm@s2idle-exec-after.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-8/igt@xe_pm@s2idle-exec-after.html
New tests
---------
New tests have been introduced between XEIGT_8074_full and XEIGTPW_11914_full:
### New IGT tests (1) ###
* igt@xe_exec_capture@close-fd:
- Statuses : 3 fail(s)
- Exec time: [5.78, 6.52] s
Known issues
------------
Here are the changes found in XEIGTPW_11914_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@info:
- shard-dg2-set2: [PASS][16] -> [SKIP][17] ([Intel XE#2134])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-466/igt@fbdev@info.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@fbdev@info.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear:
- shard-lnl: NOTRUN -> [FAIL][18] ([Intel XE#911]) +3 other tests fail
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
- shard-lnl: [PASS][19] -> [FAIL][20] ([Intel XE#1701]) +1 other test fail
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-3/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-2/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-lnl: NOTRUN -> [SKIP][21] ([Intel XE#1407])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-4/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][22] ([Intel XE#316])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-dg2-set2: NOTRUN -> [SKIP][23] ([Intel XE#610])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-434/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-lnl: NOTRUN -> [SKIP][24] ([Intel XE#1124]) +4 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-8/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#1124]) +10 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-435/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#367]) +6 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-464/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
- shard-lnl: NOTRUN -> [SKIP][27] ([Intel XE#2191])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-3/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
* igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
- shard-dg2-set2: NOTRUN -> [SKIP][28] ([Intel XE#2191])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-436/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-4-displays-1920x1080p:
- shard-lnl: NOTRUN -> [SKIP][29] ([Intel XE#1512])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-7/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][30] ([Intel XE#455] / [Intel XE#787]) +35 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][31] ([Intel XE#787]) +132 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-435/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][32] ([Intel XE#2907]) +2 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][33] ([Intel XE#2887]) +5 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
- shard-dg2-set2: [PASS][34] -> [INCOMPLETE][35] ([Intel XE#1195])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][36] ([Intel XE#314]) +3 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-436/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][37] ([Intel XE#1152]) +3 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-lnl: NOTRUN -> [SKIP][38] ([Intel XE#373]) +2 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-3/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][39] ([Intel XE#373]) +11 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2-set2: NOTRUN -> [FAIL][40] ([Intel XE#1178] / [Intel XE#1204])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_content_protection@lic-type-0.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-lnl: NOTRUN -> [SKIP][41] ([Intel XE#2321])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-6/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-dg2-set2: NOTRUN -> [SKIP][42] ([Intel XE#308])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-434/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_crc@cursor-sliding-64x21:
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#1424])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-5/igt@kms_cursor_crc@cursor-sliding-64x21.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-lnl: NOTRUN -> [SKIP][44] ([Intel XE#309])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-8/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][45] ([Intel XE#1195])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-464/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-dg2-set2: NOTRUN -> [SKIP][46] ([Intel XE#323])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dsc@dsc-with-bpc:
- shard-lnl: NOTRUN -> [SKIP][47] ([Intel XE#599]) +1 other test skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-7/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2-set2: NOTRUN -> [SKIP][48] ([Intel XE#455]) +15 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-434/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_feature_discovery@psr1:
- shard-dg2-set2: NOTRUN -> [SKIP][49] ([Intel XE#1135])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-434/igt@kms_feature_discovery@psr1.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4:
- shard-dg2-set2: [PASS][50] -> [FAIL][51] ([Intel XE#301])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a6-dp4:
- shard-dg2-set2: NOTRUN -> [FAIL][52] ([Intel XE#301]) +5 other tests fail
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-432/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a6-dp4.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a6-dp4:
- shard-dg2-set2: NOTRUN -> [FAIL][53] ([Intel XE#1204]) +1 other test fail
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-432/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a6-dp4.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#1421]) +3 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-5/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@dpms-vs-vblank-race:
- shard-dg2-set2: NOTRUN -> [SKIP][55] ([Intel XE#2423] / [i915#2575]) +2 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_flip@dpms-vs-vblank-race.html
* igt@kms_flip@flip-vs-absolute-wf_vblank:
- shard-lnl: [PASS][56] -> [FAIL][57] ([Intel XE#886]) +10 other tests fail
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-7/igt@kms_flip@flip-vs-absolute-wf_vblank.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-7/igt@kms_flip@flip-vs-absolute-wf_vblank.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-lnl: NOTRUN -> [SKIP][58] ([Intel XE#1401] / [Intel XE#1745])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#1401])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][60] ([Intel XE#651]) +5 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-4/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-dg2-set2: [PASS][61] -> [SKIP][62] ([Intel XE#2890])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary:
- shard-dg2-set2: NOTRUN -> [SKIP][63] ([Intel XE#651]) +25 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
- shard-lnl: NOTRUN -> [SKIP][64] ([Intel XE#1469])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][65] ([Intel XE#2890]) +3 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-dg2-set2: NOTRUN -> [SKIP][66] ([Intel XE#1158])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][67] ([Intel XE#653]) +42 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][68] ([Intel XE#656]) +16 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][69] ([Intel XE#605])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@kms_getfb@getfb-reject-ccs.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-dg2-set2: NOTRUN -> [SKIP][70] ([Intel XE#346])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_plane@plane-position-covered:
- shard-lnl: [PASS][71] -> [DMESG-FAIL][72] ([Intel XE#324]) +2 other tests dmesg-fail
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-1/igt@kms_plane@plane-position-covered.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-7/igt@kms_plane@plane-position-covered.html
* igt@kms_plane@plane-position-hole@pipe-b-plane-1:
- shard-lnl: [PASS][73] -> [DMESG-WARN][74] ([Intel XE#324]) +1 other test dmesg-warn
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-5/igt@kms_plane@plane-position-hole@pipe-b-plane-1.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-6/igt@kms_plane@plane-position-hole@pipe-b-plane-1.html
* igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
- shard-dg2-set2: NOTRUN -> [FAIL][75] ([Intel XE#616]) +3 other tests fail
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d:
- shard-dg2-set2: NOTRUN -> [SKIP][76] ([Intel XE#2763] / [Intel XE#455]) +3 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a:
- shard-dg2-set2: NOTRUN -> [SKIP][77] ([Intel XE#2763]) +5 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a:
- shard-lnl: NOTRUN -> [SKIP][78] ([Intel XE#2763]) +3 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-dg2-set2: NOTRUN -> [SKIP][79] ([Intel XE#870])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_rpm@universal-planes:
- shard-lnl: [PASS][80] -> [INCOMPLETE][81] ([Intel XE#1620] / [Intel XE#2864])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-3/igt@kms_pm_rpm@universal-planes.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-1/igt@kms_pm_rpm@universal-planes.html
* igt@kms_pm_rpm@universal-planes@plane-32:
- shard-lnl: [PASS][82] -> [DMESG-FAIL][83] ([Intel XE#1620])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-3/igt@kms_pm_rpm@universal-planes@plane-32.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-1/igt@kms_pm_rpm@universal-planes@plane-32.html
* igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
- shard-dg2-set2: NOTRUN -> [SKIP][84] ([Intel XE#1489]) +12 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#1122])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-436/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-psr2-primary-render:
- shard-lnl: [PASS][86] -> [FAIL][87] ([Intel XE#1649]) +1 other test fail
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-3/igt@kms_psr@fbc-psr2-primary-render.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-5/igt@kms_psr@fbc-psr2-primary-render.html
* igt@kms_psr@psr-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][88] ([Intel XE#2850] / [Intel XE#929]) +19 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_psr@psr-dpms.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2-set2: NOTRUN -> [SKIP][89] ([Intel XE#327]) +1 other test skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-464/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-lnl: NOTRUN -> [SKIP][90] ([Intel XE#1437]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-5/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-lnl: NOTRUN -> [SKIP][91] ([Intel XE#1435])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2-set2: NOTRUN -> [SKIP][92] ([Intel XE#330])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_tv_load_detect@load-detect.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
- shard-lnl: [PASS][93] -> [FAIL][94] ([Intel XE#899]) +1 other test fail
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-8/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-1/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
* igt@kms_vblank@wait-idle-hang:
- shard-dg2-set2: [PASS][95] -> [SKIP][96] ([Intel XE#2423] / [i915#2575]) +3 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-463/igt@kms_vblank@wait-idle-hang.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_vblank@wait-idle-hang.html
* igt@kms_vrr@flip-basic:
- shard-lnl: [PASS][97] -> [FAIL][98] ([Intel XE#2443]) +3 other tests fail
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-4/igt@kms_vrr@flip-basic.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-6/igt@kms_vrr@flip-basic.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#756]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-434/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@xe_copy_basic@mem-copy-linear-0xfd:
- shard-dg2-set2: NOTRUN -> [SKIP][100] ([Intel XE#1123])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@xe_copy_basic@mem-copy-linear-0xfd.html
* igt@xe_copy_basic@mem-set-linear-0xfd:
- shard-dg2-set2: NOTRUN -> [SKIP][101] ([Intel XE#1126])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@xe_copy_basic@mem-set-linear-0xfd.html
* igt@xe_create@create-big-vram:
- shard-lnl: NOTRUN -> [SKIP][102] ([Intel XE#1062])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-4/igt@xe_create@create-big-vram.html
* igt@xe_eudebug@basic-close:
- shard-dg2-set2: NOTRUN -> [SKIP][103] ([Intel XE#2905]) +11 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-436/igt@xe_eudebug@basic-close.html
* igt@xe_evict@evict-beng-large-multi-vm-cm:
- shard-dg2-set2: [PASS][104] -> [FAIL][105] ([Intel XE#1600])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-435/igt@xe_evict@evict-beng-large-multi-vm-cm.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@xe_evict@evict-beng-large-multi-vm-cm.html
* igt@xe_evict@evict-beng-threads-large:
- shard-dg2-set2: [PASS][106] -> [FAIL][107] ([Intel XE#1000])
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-463/igt@xe_evict@evict-beng-threads-large.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@xe_evict@evict-beng-threads-large.html
* igt@xe_evict@evict-threads-small-multi-vm:
- shard-lnl: NOTRUN -> [SKIP][108] ([Intel XE#688]) +4 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-5/igt@xe_evict@evict-threads-small-multi-vm.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
- shard-lnl: NOTRUN -> [SKIP][109] ([Intel XE#1392]) +1 other test skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@twice-userptr-rebind-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][110] ([Intel XE#288]) +27 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html
* igt@xe_exec_sip_eudebug@breakpoint-waitsip:
- shard-lnl: NOTRUN -> [SKIP][111] ([Intel XE#2905]) +4 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-8/igt@xe_exec_sip_eudebug@breakpoint-waitsip.html
* igt@xe_exec_threads@threads-bal-mixed-fd-userptr-invalidate:
- shard-dg2-set2: [PASS][112] -> [SKIP][113] ([Intel XE#1130]) +7 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-435/igt@xe_exec_threads@threads-bal-mixed-fd-userptr-invalidate.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@xe_exec_threads@threads-bal-mixed-fd-userptr-invalidate.html
* igt@xe_gt_freq@freq_suspend:
- shard-lnl: NOTRUN -> [SKIP][114] ([Intel XE#584])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-3/igt@xe_gt_freq@freq_suspend.html
* igt@xe_live_ktest@xe_bo:
- shard-dg2-set2: NOTRUN -> [TIMEOUT][115] ([Intel XE#2961]) +1 other test timeout
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-464/igt@xe_live_ktest@xe_bo.html
* igt@xe_noexec_ping_pong:
- shard-lnl: NOTRUN -> [SKIP][116] ([Intel XE#379])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-5/igt@xe_noexec_ping_pong.html
* igt@xe_oa@non-privileged-access-vaddr:
- shard-dg2-set2: NOTRUN -> [SKIP][117] ([Intel XE#2541]) +5 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-464/igt@xe_oa@non-privileged-access-vaddr.html
* igt@xe_pm@d3cold-basic-exec:
- shard-dg2-set2: NOTRUN -> [SKIP][118] ([Intel XE#2284] / [Intel XE#366])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-432/igt@xe_pm@d3cold-basic-exec.html
* igt@xe_pm@d3cold-multiple-execs:
- shard-lnl: NOTRUN -> [SKIP][119] ([Intel XE#2284] / [Intel XE#366])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-2/igt@xe_pm@d3cold-multiple-execs.html
* igt@xe_pm@d3hot-mmap-vram:
- shard-lnl: NOTRUN -> [SKIP][120] ([Intel XE#1948])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-4/igt@xe_pm@d3hot-mmap-vram.html
* igt@xe_pm@s2idle-multiple-execs:
- shard-dg2-set2: [PASS][121] -> [ABORT][122] ([Intel XE#1358])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-466/igt@xe_pm@s2idle-multiple-execs.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-432/igt@xe_pm@s2idle-multiple-execs.html
* igt@xe_pm@s4-basic-exec:
- shard-dg2-set2: [PASS][123] -> [ABORT][124] ([Intel XE#1358] / [Intel XE#1794]) +1 other test abort
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-466/igt@xe_pm@s4-basic-exec.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-432/igt@xe_pm@s4-basic-exec.html
* igt@xe_pm@s4-vm-bind-unbind-all:
- shard-lnl: [PASS][125] -> [ABORT][126] ([Intel XE#1794])
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-3/igt@xe_pm@s4-vm-bind-unbind-all.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html
* igt@xe_query@multigpu-query-config:
- shard-lnl: NOTRUN -> [SKIP][127] ([Intel XE#944])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-7/igt@xe_query@multigpu-query-config.html
* igt@xe_query@multigpu-query-uc-fw-version-guc:
- shard-dg2-set2: NOTRUN -> [SKIP][128] ([Intel XE#944]) +2 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@xe_query@multigpu-query-uc-fw-version-guc.html
#### Possible fixes ####
* igt@core_hotunplug@hotunplug-rescan:
- shard-dg2-set2: [INCOMPLETE][129] ([Intel XE#1195]) -> [PASS][130] +3 other tests pass
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-434/igt@core_hotunplug@hotunplug-rescan.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-435/igt@core_hotunplug@hotunplug-rescan.html
* igt@kms_3d:
- {shard-bmg}: [SKIP][131] ([Intel XE#540]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-5/igt@kms_3d.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-2/igt@kms_3d.html
* igt@kms_addfb_basic@addfb25-bad-modifier:
- {shard-bmg}: [SKIP][133] ([Intel XE#2461]) -> [PASS][134] +1 other test pass
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-5/igt@kms_addfb_basic@addfb25-bad-modifier.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-1/igt@kms_addfb_basic@addfb25-bad-modifier.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1:
- shard-lnl: [FAIL][135] ([Intel XE#1426]) -> [PASS][136] +1 other test pass
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-3/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- {shard-bmg}: [INCOMPLETE][137] -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-4/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-5/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_cursor_edge_walk@128x128-top-edge:
- shard-lnl: [FAIL][139] ([Intel XE#2577]) -> [PASS][140] +1 other test pass
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-3/igt@kms_cursor_edge_walk@128x128-top-edge.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-8/igt@kms_cursor_edge_walk@128x128-top-edge.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- {shard-bmg}: [SKIP][141] -> [PASS][142] +7 other tests pass
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-4/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-2/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-lnl: [TIMEOUT][143] -> [PASS][144] +1 other test pass
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-8/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@torture-bo:
- shard-dg2-set2: [DMESG-WARN][145] ([Intel XE#1620]) -> [PASS][146] +1 other test pass
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-434/igt@kms_cursor_legacy@torture-bo.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-435/igt@kms_cursor_legacy@torture-bo.html
* igt@kms_cursor_legacy@torture-move@pipe-d:
- shard-dg2-set2: [DMESG-WARN][147] -> [PASS][148] +1 other test pass
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-435/igt@kms_cursor_legacy@torture-move@pipe-d.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@kms_cursor_legacy@torture-move@pipe-d.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3:
- {shard-bmg}: [FAIL][149] ([Intel XE#301]) -> [PASS][150] +1 other test pass
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
* igt@kms_flip@flip-vs-suspend:
- shard-dg2-set2: [INCOMPLETE][151] ([Intel XE#1195] / [Intel XE#2049] / [Intel XE#2597]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-464/igt@kms_flip@flip-vs-suspend.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-464/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend@c-dp4:
- shard-dg2-set2: [INCOMPLETE][153] ([Intel XE#1195] / [Intel XE#2049]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-464/igt@kms_flip@flip-vs-suspend@c-dp4.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-464/igt@kms_flip@flip-vs-suspend@c-dp4.html
* igt@kms_flip@nonexisting-fb:
- {shard-bmg}: [SKIP][155] ([Intel XE#3108]) -> [PASS][156] +7 other tests pass
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-5/igt@kms_flip@nonexisting-fb.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-5/igt@kms_flip@nonexisting-fb.html
* igt@kms_flip@nonexisting-fb-interruptible:
- shard-dg2-set2: [SKIP][157] ([Intel XE#2423] / [i915#2575]) -> [PASS][158] +7 other tests pass
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_flip@nonexisting-fb-interruptible.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-432/igt@kms_flip@nonexisting-fb-interruptible.html
* igt@kms_flip@wf_vblank-ts-check@b-edp1:
- shard-lnl: [FAIL][159] ([Intel XE#886]) -> [PASS][160] +5 other tests pass
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-2/igt@kms_flip@wf_vblank-ts-check@b-edp1.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-4/igt@kms_flip@wf_vblank-ts-check@b-edp1.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: [SKIP][161] ([Intel XE#455]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-436/igt@kms_hdr@invalid-hdr.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- {shard-bmg}: [SKIP][163] ([Intel XE#2231]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-8/igt@kms_joiner@invalid-modeset-force-big-joiner.html
- shard-dg2-set2: [SKIP][165] ([Intel XE#2890]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_plane@plane-position-hole-dpms@pipe-b-plane-4:
- shard-lnl: [DMESG-WARN][167] ([Intel XE#324]) -> [PASS][168] +2 other tests pass
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-4/igt@kms_plane@plane-position-hole-dpms@pipe-b-plane-4.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-5/igt@kms_plane@plane-position-hole-dpms@pipe-b-plane-4.html
* igt@kms_plane@plane-position-hole@pipe-a-plane-4:
- shard-lnl: [DMESG-FAIL][169] ([Intel XE#324]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-5/igt@kms_plane@plane-position-hole@pipe-a-plane-4.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-6/igt@kms_plane@plane-position-hole@pipe-a-plane-4.html
* igt@kms_plane_alpha_blend@coverage-7efc:
- {shard-bmg}: [SKIP][171] ([Intel XE#829]) -> [PASS][172] +1 other test pass
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-5/igt@kms_plane_alpha_blend@coverage-7efc.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-1/igt@kms_plane_alpha_blend@coverage-7efc.html
* igt@kms_plane_cursor@primary:
- {shard-bmg}: [FAIL][173] -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-5/igt@kms_plane_cursor@primary.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-4/igt@kms_plane_cursor@primary.html
* igt@kms_plane_cursor@viewport:
- shard-dg2-set2: [FAIL][175] ([Intel XE#616]) -> [PASS][176] +1 other test pass
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-463/igt@kms_plane_cursor@viewport.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_plane_cursor@viewport.html
* igt@kms_pm_dc@dc5-psr:
- shard-lnl: [FAIL][177] ([Intel XE#718]) -> [PASS][178]
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-5/igt@kms_pm_dc@dc5-psr.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-7/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_rpm@universal-planes-dpms:
- {shard-bmg}: [SKIP][179] ([Intel XE#2446]) -> [PASS][180]
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-4/igt@kms_pm_rpm@universal-planes-dpms.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-1/igt@kms_pm_rpm@universal-planes-dpms.html
- shard-dg2-set2: [SKIP][181] ([Intel XE#2446]) -> [PASS][182]
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_pm_rpm@universal-planes-dpms.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-464/igt@kms_pm_rpm@universal-planes-dpms.html
* igt@kms_psr@fbc-psr2-basic@edp-1:
- shard-lnl: [FAIL][183] ([Intel XE#1649]) -> [PASS][184] +1 other test pass
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-8/igt@kms_psr@fbc-psr2-basic@edp-1.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-8/igt@kms_psr@fbc-psr2-basic@edp-1.html
* igt@kms_psr@fbc-psr2-cursor-blt@edp-1:
- shard-lnl: [FAIL][185] ([Intel XE#2948]) -> [PASS][186] +5 other tests pass
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-8/igt@kms_psr@fbc-psr2-cursor-blt@edp-1.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-7/igt@kms_psr@fbc-psr2-cursor-blt@edp-1.html
* igt@xe_dma_buf_sync@export-dma-buf-many-write-sync:
- shard-lnl: [DMESG-WARN][187] -> [PASS][188]
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-6/igt@xe_dma_buf_sync@export-dma-buf-many-write-sync.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-6/igt@xe_dma_buf_sync@export-dma-buf-many-write-sync.html
* igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue:
- shard-lnl: [FAIL][189] ([Intel XE#2667]) -> [PASS][190]
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-6/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-3/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-dg2-set2: [TIMEOUT][191] ([Intel XE#1473] / [Intel XE#402]) -> [PASS][192]
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-433/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_evict@evict-beng-threads-large:
- {shard-bmg}: [TIMEOUT][193] ([Intel XE#1473]) -> [PASS][194]
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-5/igt@xe_evict@evict-beng-threads-large.html
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-4/igt@xe_evict@evict-beng-threads-large.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-dg2-set2: [TIMEOUT][195] ([Intel XE#1473]) -> [PASS][196]
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-466/igt@xe_evict@evict-mixed-many-threads-small.html
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate-race:
- shard-lnl: [FAIL][197] ([Intel XE#2754]) -> [PASS][198]
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-4/igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate-race.html
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-3/igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@once-bindexecqueue-rebind-imm:
- {shard-bmg}: [SKIP][199] ([Intel XE#1130]) -> [PASS][200] +12 other tests pass
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-4/igt@xe_exec_fault_mode@once-bindexecqueue-rebind-imm.html
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-2/igt@xe_exec_fault_mode@once-bindexecqueue-rebind-imm.html
* igt@xe_module_load@reload-no-display:
- {shard-bmg}: [FAIL][201] ([Intel XE#2136]) -> [PASS][202]
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-bmg-5/igt@xe_module_load@reload-no-display.html
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-bmg-1/igt@xe_module_load@reload-no-display.html
* igt@xe_pm@s4-d3hot-basic-exec:
- shard-lnl: [ABORT][203] ([Intel XE#1358] / [Intel XE#1607]) -> [PASS][204] +1 other test pass
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-2/igt@xe_pm@s4-d3hot-basic-exec.html
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-4/igt@xe_pm@s4-d3hot-basic-exec.html
* igt@xe_vm@munmap-style-unbind-front:
- shard-dg2-set2: [SKIP][205] ([Intel XE#1130]) -> [PASS][206] +7 other tests pass
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@xe_vm@munmap-style-unbind-front.html
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@xe_vm@munmap-style-unbind-front.html
#### Warnings ####
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-dg2-set2: [SKIP][207] ([Intel XE#316]) -> [SKIP][208] ([Intel XE#2351] / [Intel XE#2890])
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-464/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs:
- shard-dg2-set2: [SKIP][209] ([Intel XE#2890]) -> [SKIP][210] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
- shard-dg2-set2: [SKIP][211] ([Intel XE#2423] / [i915#2575]) -> [SKIP][212] ([Intel XE#373])
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-436/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-dg2-set2: [SKIP][213] ([Intel XE#373]) -> [SKIP][214] ([Intel XE#2423] / [i915#2575])
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_content_protection@lic-type-1:
- shard-dg2-set2: [SKIP][215] ([Intel XE#2423] / [i915#2575]) -> [SKIP][216] ([Intel XE#455])
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_content_protection@lic-type-1.html
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-433/igt@kms_content_protection@lic-type-1.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- shard-dg2-set2: [SKIP][217] ([Intel XE#455]) -> [SKIP][218] ([Intel XE#2423] / [i915#2575])
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-435/igt@kms_cursor_crc@cursor-offscreen-max-size.html
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-dg2-set2: [SKIP][219] ([Intel XE#455]) -> [SKIP][220] ([Intel XE#2890])
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-434/igt@kms_dsc@dsc-with-output-formats.html
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-pgflip-blt:
- shard-dg2-set2: [SKIP][221] ([Intel XE#2351] / [Intel XE#2890]) -> [SKIP][222] ([Intel XE#651])
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-pgflip-blt.html
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-render:
- shard-dg2-set2: [SKIP][223] ([Intel XE#2890]) -> [SKIP][224] ([Intel XE#651]) +1 other test skip
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-render.html
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render:
- shard-dg2-set2: [SKIP][225] ([Intel XE#2890]) -> [SKIP][226] ([Intel XE#653]) +1 other test skip
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render.html
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render.html
* igt@kms_pm_dc@deep-pkgc:
- shard-lnl: [DMESG-FAIL][227] ([Intel XE#1620]) -> [FAIL][228] ([Intel XE#2029])
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-lnl-8/igt@kms_pm_dc@deep-pkgc.html
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-lnl-8/igt@kms_pm_dc@deep-pkgc.html
* igt@kms_psr@fbc-psr2-basic:
- shard-dg2-set2: [SKIP][229] ([Intel XE#2890]) -> [SKIP][230] ([Intel XE#2850] / [Intel XE#929]) +1 other test skip
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_psr@fbc-psr2-basic.html
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-435/igt@kms_psr@fbc-psr2-basic.html
* igt@kms_psr@fbc-psr2-no-drrs:
- shard-dg2-set2: [SKIP][231] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][232] ([Intel XE#2890])
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-435/igt@kms_psr@fbc-psr2-no-drrs.html
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_psr@fbc-psr2-no-drrs.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-dg2-set2: [SKIP][233] ([Intel XE#2423] / [i915#2575]) -> [SKIP][234] ([Intel XE#327])
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-434/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2-set2: [SKIP][235] ([Intel XE#362]) -> [FAIL][236] ([Intel XE#1729])
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: [SKIP][237] ([Intel XE#362]) -> [SKIP][238] ([Intel XE#1500])
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_eudebug_online@interrupt-other:
- shard-dg2-set2: [SKIP][239] ([Intel XE#2905]) -> [SKIP][240] ([Intel XE#1130])
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-433/igt@xe_eudebug_online@interrupt-other.html
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@xe_eudebug_online@interrupt-other.html
* igt@xe_eudebug_online@set-breakpoint:
- shard-dg2-set2: [SKIP][241] ([Intel XE#1130]) -> [SKIP][242] ([Intel XE#2905])
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@xe_eudebug_online@set-breakpoint.html
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-435/igt@xe_eudebug_online@set-breakpoint.html
* igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate:
- shard-dg2-set2: [SKIP][243] ([Intel XE#288]) -> [SKIP][244] ([Intel XE#1130]) +2 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-463/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate.html
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate.html
* igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm:
- shard-dg2-set2: [SKIP][245] ([Intel XE#1130]) -> [SKIP][246] ([Intel XE#288]) +2 other tests skip
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm.html
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-464/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm.html
* igt@xe_huc_copy@huc_copy:
- shard-dg2-set2: [SKIP][247] ([Intel XE#1130]) -> [SKIP][248] ([Intel XE#255])
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-432/igt@xe_huc_copy@huc_copy.html
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-432/igt@xe_huc_copy@huc_copy.html
* igt@xe_oa@non-sampling-read-error:
- shard-dg2-set2: [SKIP][249] ([Intel XE#2541]) -> [SKIP][250] ([Intel XE#1130])
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-435/igt@xe_oa@non-sampling-read-error.html
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@xe_oa@non-sampling-read-error.html
* igt@xe_pm@s3-d3cold-basic-exec:
- shard-dg2-set2: [SKIP][251] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][252] ([Intel XE#1130])
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8074/shard-dg2-436/igt@xe_pm@s3-d3cold-basic-exec.html
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/shard-dg2-466/igt@xe_pm@s3-d3cold-basic-exec.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1000]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1000
[Intel XE#1062]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1062
[Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
[Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
[Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
[Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
[Intel XE#1152]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1152
[Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
[Intel XE#1204]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1204
[Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1437
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
[Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
[Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
[Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
[Intel XE#1620]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1620
[Intel XE#1649]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1649
[Intel XE#1701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1701
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#1948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1948
[Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2105]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2105
[Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
[Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2231
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2329
[Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
[Intel XE#2443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2443
[Intel XE#2446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2446
[Intel XE#2461]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2461
[Intel XE#2472]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2472
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255
[Intel XE#2577]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2577
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2667]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2667
[Intel XE#2754]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2754
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2791]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2791
[Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2864]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2864
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2890
[Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2948
[Intel XE#2961]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2961
[Intel XE#3007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3007
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3108]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3108
[Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
[Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
[Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#379]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/379
[Intel XE#402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/402
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/540
[Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
[Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
[Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#827]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/827
[Intel XE#829]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/829
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
[Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
Build changes
-------------
* IGT: IGT_8074 -> IGTPW_11914
IGTPW_11914: 11914
IGT_8074: a886e0ad97832dc2ba9b85d35bca22e667c15105 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2070-01c7b2c084e5c84313f382734c10945b9aa49823: 01c7b2c084e5c84313f382734c10945b9aa49823
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11914/index.html
[-- Attachment #2: Type: text/html, Size: 73693 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH i-g-t v3 1/1] tests/intel/xe_exec_capture: Add xe_exec_capture test
2024-10-15 15:31 ` [PATCH i-g-t v3 1/1] " Zhanjun Dong
2024-10-16 5:29 ` Peter Senna Tschudin
@ 2024-10-16 14:12 ` Kamil Konieczny
2024-10-16 21:20 ` Dong, Zhanjun
1 sibling, 1 reply; 9+ messages in thread
From: Kamil Konieczny @ 2024-10-16 14:12 UTC (permalink / raw)
To: igt-dev; +Cc: Zhanjun Dong
Hi Zhanjun,
On 2024-10-15 at 08:31:01 -0700, Zhanjun Dong wrote:
> Test with GuC reset, check if devcoredump register dump is within the
> range.
>
> Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
> ---
> tests/intel/xe_exec_capture.c | 308 ++++++++++++++++++++++++++++++++++
> tests/meson.build | 1 +
> 2 files changed, 309 insertions(+)
> create mode 100644 tests/intel/xe_exec_capture.c
>
> diff --git a/tests/intel/xe_exec_capture.c b/tests/intel/xe_exec_capture.c
> new file mode 100644
> index 000000000..89b544c93
> --- /dev/null
> +++ b/tests/intel/xe_exec_capture.c
> @@ -0,0 +1,308 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +/**
> + * TEST: Basic tests for GuC based register capture
> + * Category: Core
> + * Mega feature: General Core features
> + * Sub-category: CMD submission
> + * Functionality: Debug
> + * Test category: functionality test
> + */
> +
> +#include <ctype.h>
> +#include <fcntl.h>
> +#include <stdio.h>
> +#include <regex.h>
> +
> +#include "igt.h"
> +#include "igt_device.h"
> +#include "lib/igt_syncobj.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include "xe/xe_spin.h"
> +
> +#define MAX_N_EXECQUEUES 16
> +#define MAX_INSTANCE 9
> +#define GT_RESET (0x1 << 0)
> +#define CLOSE_FD (0x1 << 1)
> +#define CLOSE_EXEC_QUEUES (0x1 << 2)
> +#define VIRTUAL (0x1 << 3)
> +#define PARALLEL (0x1 << 4)
> +#define CAT_ERROR (0x1 << 5)
> +
> +#define BASE_ADDRESS 0x1a0000
> +/* Batch buffer element count, in number of dwords(uint32_t) */
> +#define BATCH_DW_COUNT 16
> +
> +#define MAX_PATH_NAME_LEN 512
> +#define MAX_LINES 512
> +#define MAX_LINE_LEN 1024
> +
> +#define DUMP_PATH "/sys/class/drm/card%d/device/devcoredump/data"
> +#define START_TAG "**** Job ****"
> +#define REGEX_KEY_VALUE_PAIR "^[ \t]*([^:]+):[ \t]*([^ \t]+)[ \t]*$"
> +#define REGEX_KEY_INDEX 1
> +#define REGEX_VALUE_INDEX 2
> +#define REGEX_KEY_VALUE_MATCH_COUNT 3
> +
> +int card_id;
> +regex_t regex;
> +char lines[MAX_LINES][MAX_LINE_LEN];
Why only MAX_LINE here? Could you dynamically allocate mem (and eventually
reallocate it) to fit all devcore?
> +
> +static bool access_devcoredump(bool load_file)
> +{
> + FILE *fd;
> + char path[MAX_PATH_NAME_LEN];
> +
> + sprintf(path, DUMP_PATH, card_id);
> + fd = fopen(path, "r");
You have this pattern also below, please write a function and use it.
> + if (!fd) {
> + igt_debug("Devcoredump not exist.\n");
Or there was some error, you could print errno here.
Btw why FILE* ? Could you use just normal open()?
> + return false;
> + }
> + igt_debug("Devcoredump found: %s\n", path);
> +
> + /* Clear memory before load file */
> + if (load_file) {
> + int i = 0;
> + bool found = false;
> +
> + memset(lines, 0, sizeof(lines));
> + while (!feof(fd)) {
> + fgets(lines[i], MAX_LINE_LEN, fd);
> +
> + /* Only save lines after start tag */
> + if (!found)
> + found = strstr(lines[0], START_TAG);
> + else
> + if (++i >= MAX_LINES)
> + break;
> + }
> + }
> +
> + fclose(fd);
> + return true;
> +}
> +
> +static void rm_devcoredump(void)
imho this could be bool
> +{
> + char path[MAX_PATH_NAME_LEN];
> + int fd;
> +
> + igt_debug("Clearing devcoredump.\n");
> +
> + sprintf(path, DUMP_PATH, card_id);
> + fd = open(path, O_WRONLY);
> + if (fd != -1) {
> + write(fd, "0", 1);
> + close(fd);
> + }
> +}
> +
> +static char *get_coredump_item(const char *tag)
> +{
> + int i;
> + regmatch_t match[REGEX_KEY_VALUE_MATCH_COUNT];
> +
> + for (i = 0; i < MAX_LINES && lines[i][0]; i++) {
> + char *line = lines[i];
> +
> + /* Skip lines without tag */
> + if (!strstr(line, tag))
> + continue;
> +
> + if (regexec(®ex, line, REGEX_KEY_VALUE_MATCH_COUNT, match, 0) == 0) {
> + char *key, *value;
> +
> + key = &line[match[REGEX_KEY_INDEX].rm_so];
> + line[match[REGEX_KEY_INDEX].rm_eo] = '\0';
> + value = &line[match[REGEX_VALUE_INDEX].rm_so];
> + line[match[REGEX_VALUE_INDEX].rm_eo] = '\0';
> +
> + if (strcmp(tag, key) == 0)
> + return value;
> + /* if key != tag, continue */
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static void check_capture_output(const char *tag, uint64_t addr_lo, uint64_t addr_hi)
> +{
> + uint64_t result;
> + char *output;
> +
> + igt_assert(output = get_coredump_item(tag));
imho better igt_assert_f and print which tag is missing.
> + result = strtol(output, NULL, 16);
> + igt_debug("Compare %s: %s vs [0x%lX-0x%lX]\n", tag, output, addr_lo, addr_hi);
> + igt_assert((addr_lo <= result) && (result <= addr_hi));
Same here, you could print actual values if assert failed.
> +}
> +
> +static void check_capture_output_str(const char *tag, const char *target)
> +{
> + char *output;
> +
> + igt_assert(output = get_coredump_item(tag));
Same here.
> + igt_debug("Compare %s: '%s' vs '%s'\n", tag, output, target);
> + igt_assert(!strcmp(output, target));
Same here.
> +}
> +
> +static void check_capture_out(uint64_t base_addr, uint64_t length)
> +{
> + /* assert devcoredump created */
> + assert(access_devcoredump(true));
Should be igt_assert_f
> +
> + check_capture_output_str("Capture_source", "GuC");
> + check_capture_output("ACTHD", base_addr, base_addr + length);
> + check_capture_output("RING_BBADDR", base_addr, base_addr + length);
> +
> + /* clear devcoredump */
> + rm_devcoredump();
> + sleep(1);
> + /* Assert devcoredump removed */
> + assert(!access_devcoredump(false));
Should be igt_assert_f
> +}
> +
> +/**
> + * SUBTEST: close-fd
> + * Description: Test close fd, check if devcoredump register dump is within the
> + */
> +static void
> +test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
> + int n_exec_queues, int n_execs, unsigned int flags)
> +{
> + uint32_t vm;
> + const uint64_t addr = BASE_ADDRESS;
> + struct drm_xe_sync sync[2] = {
> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> + };
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 2,
> + .syncs = to_user_pointer(sync),
> + };
> + uint32_t exec_queues[MAX_N_EXECQUEUES];
> + uint32_t syncobjs[MAX_N_EXECQUEUES];
> + size_t bo_size;
> + uint32_t bo = 0;
> + struct {
> + struct xe_spin spin;
> + uint32_t batch[BATCH_DW_COUNT];
> + uint64_t pad;
> + uint32_t data;
> + } *data;
> + struct xe_spin_opts spin_opts = { .preempt = false };
> + int i, b;
> +
> + igt_assert(n_exec_queues <= MAX_N_EXECQUEUES);
> +
> + if (flags & CLOSE_FD)
> + fd = drm_open_driver(DRIVER_XE);
Better drm_reopen_driver()
> +
> + vm = xe_vm_create(fd, 0, 0);
> + bo_size = sizeof(*data) * n_execs;
> + bo_size = xe_bb_size(fd, bo_size);
> +
> + bo = xe_bo_create(fd, vm, bo_size,
> + vram_if_possible(fd, eci->gt_id),
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + data = xe_bo_map(fd, bo, bo_size);
> +
> + for (i = 0; i < n_exec_queues; i++) {
> + exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0);
> + syncobjs[i] = syncobj_create(fd, 0);
> + };
> +
> + sync[0].handle = syncobj_create(fd, 0);
> + xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1);
> +
> + for (i = 0; i < n_execs; i++) {
> + uint64_t base_addr = addr;
> + uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
> + uint64_t batch_addr = base_addr + batch_offset;
> + uint64_t spin_offset = (char *)&data[i].spin - (char *)data;
> + uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
> + uint64_t sdi_addr = base_addr + sdi_offset;
> + uint64_t exec_addr;
> + int e = i % n_exec_queues;
> +
> + if (!i) {
> + spin_opts.addr = base_addr + spin_offset;
> + xe_spin_init(&data[i].spin, &spin_opts);
> + exec_addr = spin_opts.addr;
> + } else {
> + b = 0;
> + data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> + data[i].batch[b++] = sdi_addr;
> + data[i].batch[b++] = sdi_addr >> 32;
> + data[i].batch[b++] = 0xc0ffee;
> + data[i].batch[b++] = MI_BATCH_BUFFER_END;
> + igt_assert(b <= ARRAY_SIZE(data[i].batch));
> +
> + exec_addr = batch_addr;
> + }
> +
> + sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> + sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + sync[1].handle = syncobjs[e];
> +
> + exec.exec_queue_id = exec_queues[e];
> + exec.address = exec_addr;
> + if (e != i)
> + syncobj_reset(fd, &syncobjs[e], 1);
> + xe_exec(fd, &exec);
> + }
> +
> + for (i = 0; i < n_exec_queues && n_execs; i++)
> + igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0,
> + NULL));
> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + syncobj_destroy(fd, sync[0].handle);
> + for (i = 0; i < n_exec_queues; i++) {
> + syncobj_destroy(fd, syncobjs[i]);
> + xe_exec_queue_destroy(fd, exec_queues[i]);
> + }
> +
> + munmap(data, bo_size);
> + gem_close(fd, bo);
> + xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + card_id = igt_device_get_card_index(fd);
> +
imho here clear old devcoredump
Regards,
Kamil
> + regcomp(®ex, REGEX_KEY_VALUE_PAIR, REG_EXTENDED | REG_NEWLINE);
> + }
> +
> + igt_subtest("close-fd")
> + xe_for_each_engine(fd, hwe) {
> + igt_debug("Running on engine class: %x instance: %x\n", hwe->engine_class,
> + hwe->engine_instance);
> +
> + test_legacy_mode(fd, hwe, 1, 1, 0);
> + check_capture_out(BASE_ADDRESS, sizeof(uint32_t) * BATCH_DW_COUNT);
> + }
> +
> + igt_fixture {
> + drm_close_driver(fd);
> + regfree(®ex);
> + }
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index 2d8cb87d5..b724a7c6d 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -284,6 +284,7 @@ intel_xe_progs = [
> 'xe_exec_atomic',
> 'xe_exec_balancer',
> 'xe_exec_basic',
> + 'xe_exec_capture',
> 'xe_exec_compute_mode',
> 'xe_exec_fault_mode',
> 'xe_exec_mix_modes',
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH i-g-t v3 1/1] tests/intel/xe_exec_capture: Add xe_exec_capture test
2024-10-16 5:29 ` Peter Senna Tschudin
@ 2024-10-16 19:08 ` Dong, Zhanjun
0 siblings, 0 replies; 9+ messages in thread
From: Dong, Zhanjun @ 2024-10-16 19:08 UTC (permalink / raw)
To: Peter Senna Tschudin, igt-dev
Thanks for review, please see my comments below.
Regards,
Zhanjun Dong
On 2024-10-16 1:29 a.m., Peter Senna Tschudin wrote:
> Dear Zhanjun Dong,
>
> Thank you for the patch! Please see my comments bellow.
>
> On 15.10.2024 17:31, Zhanjun Dong wrote:
>> Test with GuC reset, check if devcoredump register dump is within the
>> range.
>>
>> Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
>> ---
>> tests/intel/xe_exec_capture.c | 308 ++++++++++++++++++++++++++++++++++
>> tests/meson.build | 1 +
>> 2 files changed, 309 insertions(+)
>> create mode 100644 tests/intel/xe_exec_capture.c
>>
>> diff --git a/tests/intel/xe_exec_capture.c b/tests/intel/xe_exec_capture.c
>> new file mode 100644
>> index 000000000..89b544c93
>> --- /dev/null
>> +++ b/tests/intel/xe_exec_capture.c
>> @@ -0,0 +1,308 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2024 Intel Corporation
>> + */
>> +
>> +/**
>> + * TEST: Basic tests for GuC based register capture
>> + * Category: Core
>> + * Mega feature: General Core features
>> + * Sub-category: CMD submission
>> + * Functionality: Debug
>> + * Test category: functionality test
>> + */
>> +
>> +#include <ctype.h>
>> +#include <fcntl.h>
>> +#include <stdio.h>
>> +#include <regex.h>
>> +
>> +#include "igt.h"
>> +#include "igt_device.h"
>> +#include "lib/igt_syncobj.h"
>> +#include "lib/intel_reg.h"
>> +#include "xe_drm.h"
>> +#include "xe/xe_ioctl.h"
>> +#include "xe/xe_query.h"
>> +#include "xe/xe_spin.h"
>> +
>> +#define MAX_N_EXECQUEUES 16
>> +#define MAX_INSTANCE 9
>> +#define GT_RESET (0x1 << 0)
>> +#define CLOSE_FD (0x1 << 1)
>> +#define CLOSE_EXEC_QUEUES (0x1 << 2)
>> +#define VIRTUAL (0x1 << 3)
>> +#define PARALLEL (0x1 << 4)
>> +#define CAT_ERROR (0x1 << 5)
>> +
>> +#define BASE_ADDRESS 0x1a0000
>> +/* Batch buffer element count, in number of dwords(uint32_t) */
>> +#define BATCH_DW_COUNT 16
>> +
>> +#define MAX_PATH_NAME_LEN 512
>> +#define MAX_LINES 512
>> +#define MAX_LINE_LEN 1024
>> +
>> +#define DUMP_PATH "/sys/class/drm/card%d/device/devcoredump/data"
>> +#define START_TAG "**** Job ****"
>> +#define REGEX_KEY_VALUE_PAIR "^[ \t]*([^:]+):[ \t]*([^ \t]+)[ \t]*$"
>> +#define REGEX_KEY_INDEX 1
>> +#define REGEX_VALUE_INDEX 2
>> +#define REGEX_KEY_VALUE_MATCH_COUNT 3
>> +
>> +int card_id;
>
> If I am not mistaken, there are cases in which we have more than one card, and that we want to test more than one card. So I guess the logic does not work if card_id is global. I prefer not using global variables.
Good point, for more than 1 card condition, the card_id is expected to
be changed when testing on next card, this patch only set it at
beginning, need an solution to support multiple cards
>
>> +regex_t regex;
>> +char lines[MAX_LINES][MAX_LINE_LEN];
>
> Can you rewrite and not use global variables? regex could live on igt_main().
Ok, not a problem.
>
>> +
>> +static bool access_devcoredump(bool load_file)
>> +{
>> + FILE *fd;
>> + char path[MAX_PATH_NAME_LEN];
>> +
>> + sprintf(path, DUMP_PATH, card_id);
>> + fd = fopen(path, "r");
>> + if (!fd) {
>> + igt_debug("Devcoredump not exist.\n");
>> + return false;
>> + }
>> + igt_debug("Devcoredump found: %s\n", path);
>> +
>> + /* Clear memory before load file */
>> + if (load_file) {
>> + int i = 0;
>> + bool found = false;
>> +
>> + memset(lines, 0, sizeof(lines));
>> + while (!feof(fd)) {
>> + fgets(lines[i], MAX_LINE_LEN, fd);
>> +
>> + /* Only save lines after start tag */
>> + if (!found)
>> + found = strstr(lines[0], START_TAG);
> i instead of 0? found = strstr(lines[i], START_TAG); ?
It is designed to use lines[0] as buffer to load single line and search
for START_TAG, only save lines after start tag.
From other review comments, load all contents is also not a bad ideal,
so this part might be changed
>
>> + else
>> + if (++i >= MAX_LINES)
>> + break;
>> + }
>> + }
>> +
>> + fclose(fd);
>> + return true;
>> +}
>> +
>> +static void rm_devcoredump(void)
>> +{
>> + char path[MAX_PATH_NAME_LEN];
>> + int fd;
>> +
>> + igt_debug("Clearing devcoredump.\n");
>> +
>> + sprintf(path, DUMP_PATH, card_id);
>> + fd = open(path, O_WRONLY);
>> + if (fd != -1) {
>> + write(fd, "0", 1);
>> + close(fd);
>> + }
>> +}
>> +
>> +static char *get_coredump_item(const char *tag)
>> +{
>> + int i;
>> + regmatch_t match[REGEX_KEY_VALUE_MATCH_COUNT];
>> +
>> + for (i = 0; i < MAX_LINES && lines[i][0]; i++) {
>> + char *line = lines[i];
>> +
>> + /* Skip lines without tag */
>> + if (!strstr(line, tag))
>> + continue;
>> +
>> + if (regexec(®ex, line, REGEX_KEY_VALUE_MATCH_COUNT, match, 0) == 0) {
>> + char *key, *value;
>> +
>> + key = &line[match[REGEX_KEY_INDEX].rm_so];
>> + line[match[REGEX_KEY_INDEX].rm_eo] = '\0';
>> + value = &line[match[REGEX_VALUE_INDEX].rm_so];
>> + line[match[REGEX_VALUE_INDEX].rm_eo] = '\0';
>> +
>> + if (strcmp(tag, key) == 0)
>> + return value;
>> + /* if key != tag, continue */
> Can remove or expand the comment?
>
Will changed to
/* if key != tag, keep searching and loop to next line */
>> + }
>> + }
>> +
>> + return NULL;
>> +}
>> +
>> +static void check_capture_output(const char *tag, uint64_t addr_lo, uint64_t addr_hi)
>> +{
>> + uint64_t result;
>> + char *output;
>> +
>> + igt_assert(output = get_coredump_item(tag));
>> + result = strtol(output, NULL, 16);
> strtoull() ?
yes, u64 need this
>
>> + igt_debug("Compare %s: %s vs [0x%lX-0x%lX]\n", tag, output, addr_lo, addr_hi);
> 0x%llX ?
yes
>
>> + igt_assert((addr_lo <= result) && (result <= addr_hi));
>> +}
>> +
>> +static void check_capture_output_str(const char *tag, const char *target)
>> +{
>> + char *output;
>> +
>> + igt_assert(output = get_coredump_item(tag));
>> + igt_debug("Compare %s: '%s' vs '%s'\n", tag, output, target);
>> + igt_assert(!strcmp(output, target));
>> +}
>> +
>> +static void check_capture_out(uint64_t base_addr, uint64_t length)
>> +{
>> + /* assert devcoredump created */
>> + assert(access_devcoredump(true));
>> +
>> + check_capture_output_str("Capture_source", "GuC");
>> + check_capture_output("ACTHD", base_addr, base_addr + length);
>> + check_capture_output("RING_BBADDR", base_addr, base_addr + length);
>> +
>> + /* clear devcoredump */
>> + rm_devcoredump();
>> + sleep(1);
>> + /* Assert devcoredump removed */
>> + assert(!access_devcoredump(false));
>> +}
>> +
>> +/**
>> + * SUBTEST: close-fd
>> + * Description: Test close fd, check if devcoredump register dump is within the
>> + */
>> +static void
>> +test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
>> + int n_exec_queues, int n_execs, unsigned int flags)
>> +{
>> + uint32_t vm;
>> + const uint64_t addr = BASE_ADDRESS;
>> + struct drm_xe_sync sync[2] = {
>> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
>> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
>> + };
>> + struct drm_xe_exec exec = {
>> + .num_batch_buffer = 1,
>> + .num_syncs = 2,
>> + .syncs = to_user_pointer(sync),
>> + };
>> + uint32_t exec_queues[MAX_N_EXECQUEUES];
>> + uint32_t syncobjs[MAX_N_EXECQUEUES];
>> + size_t bo_size;
>> + uint32_t bo = 0;
>> + struct {
>> + struct xe_spin spin;
>> + uint32_t batch[BATCH_DW_COUNT];
>> + uint64_t pad;
>> + uint32_t data;
>> + } *data;
>> + struct xe_spin_opts spin_opts = { .preempt = false };
>> + int i, b;
>> +
>> + igt_assert(n_exec_queues <= MAX_N_EXECQUEUES);
>> +
>> + if (flags & CLOSE_FD)
>> + fd = drm_open_driver(DRIVER_XE);
>> +
>> + vm = xe_vm_create(fd, 0, 0);
>> + bo_size = sizeof(*data) * n_execs;
>> + bo_size = xe_bb_size(fd, bo_size);
>> +
>> + bo = xe_bo_create(fd, vm, bo_size,
>> + vram_if_possible(fd, eci->gt_id),
>> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>> + data = xe_bo_map(fd, bo, bo_size);
>> +
>> + for (i = 0; i < n_exec_queues; i++) {
>> + exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0);
>> + syncobjs[i] = syncobj_create(fd, 0);
>> + };
>> +
>> + sync[0].handle = syncobj_create(fd, 0);
>> + xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1);
>> +
>> + for (i = 0; i < n_execs; i++) {
>> + uint64_t base_addr = addr;
>> + uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
>> + uint64_t batch_addr = base_addr + batch_offset;
>> + uint64_t spin_offset = (char *)&data[i].spin - (char *)data;
>> + uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
>> + uint64_t sdi_addr = base_addr + sdi_offset;
>> + uint64_t exec_addr;
>> + int e = i % n_exec_queues;
>> +
>> + if (!i) {
>> + spin_opts.addr = base_addr + spin_offset;
>> + xe_spin_init(&data[i].spin, &spin_opts);
>> + exec_addr = spin_opts.addr;
>> + } else {
>> + b = 0;
>> + data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
>> + data[i].batch[b++] = sdi_addr;
>> + data[i].batch[b++] = sdi_addr >> 32;
>> + data[i].batch[b++] = 0xc0ffee;
>> + data[i].batch[b++] = MI_BATCH_BUFFER_END;
>> + igt_assert(b <= ARRAY_SIZE(data[i].batch));
>> +
>> + exec_addr = batch_addr;
>> + }
>> +
>> + sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>> + sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>> + sync[1].handle = syncobjs[e];
>> +
>> + exec.exec_queue_id = exec_queues[e];
>> + exec.address = exec_addr;
>> + if (e != i)
>> + syncobj_reset(fd, &syncobjs[e], 1);
>> + xe_exec(fd, &exec);
>> + }
>> +
>> + for (i = 0; i < n_exec_queues && n_execs; i++)
>> + igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0,
>> + NULL));
>> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
>> +
>> + sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>> + xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
>> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
>> +
>> + syncobj_destroy(fd, sync[0].handle);
>> + for (i = 0; i < n_exec_queues; i++) {
>> + syncobj_destroy(fd, syncobjs[i]);
>> + xe_exec_queue_destroy(fd, exec_queues[i]);
>> + }
>> +
>> + munmap(data, bo_size);
>> + gem_close(fd, bo);
>> + xe_vm_destroy(fd, vm);
>> +}
>> +
>> +igt_main
>> +{
>> + struct drm_xe_engine_class_instance *hwe;
>> + int fd;
>> +
>> + igt_fixture {
>> + fd = drm_open_driver(DRIVER_XE);
>> + card_id = igt_device_get_card_index(fd);
>> +
>> + regcomp(®ex, REGEX_KEY_VALUE_PAIR, REG_EXTENDED | REG_NEWLINE);
>> + }
>> +
>> + igt_subtest("close-fd")
>> + xe_for_each_engine(fd, hwe) {
>> + igt_debug("Running on engine class: %x instance: %x\n", hwe->engine_class,
>> + hwe->engine_instance);
>> +
>> + test_legacy_mode(fd, hwe, 1, 1, 0);
>> + check_capture_out(BASE_ADDRESS, sizeof(uint32_t) * BATCH_DW_COUNT);
>> + }
>> +
>> + igt_fixture {
>> + drm_close_driver(fd);
>> + regfree(®ex);
>> + }
>> +}
>> diff --git a/tests/meson.build b/tests/meson.build
>> index 2d8cb87d5..b724a7c6d 100644
>> --- a/tests/meson.build
>> +++ b/tests/meson.build
>> @@ -284,6 +284,7 @@ intel_xe_progs = [
>> 'xe_exec_atomic',
>> 'xe_exec_balancer',
>> 'xe_exec_basic',
>> + 'xe_exec_capture',
>> 'xe_exec_compute_mode',
>> 'xe_exec_fault_mode',
>> 'xe_exec_mix_modes',
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH i-g-t v3 1/1] tests/intel/xe_exec_capture: Add xe_exec_capture test
2024-10-16 14:12 ` Kamil Konieczny
@ 2024-10-16 21:20 ` Dong, Zhanjun
0 siblings, 0 replies; 9+ messages in thread
From: Dong, Zhanjun @ 2024-10-16 21:20 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev
Thanks for review, please see my comments below.
Regards,
Zhanjun Dong
On 2024-10-16 10:12 a.m., Kamil Konieczny wrote:
> Hi Zhanjun,
> On 2024-10-15 at 08:31:01 -0700, Zhanjun Dong wrote:
>> Test with GuC reset, check if devcoredump register dump is within the
>> range.
>>
>> Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
>> ---
>> tests/intel/xe_exec_capture.c | 308 ++++++++++++++++++++++++++++++++++
>> tests/meson.build | 1 +
>> 2 files changed, 309 insertions(+)
>> create mode 100644 tests/intel/xe_exec_capture.c
>>
>> diff --git a/tests/intel/xe_exec_capture.c b/tests/intel/xe_exec_capture.c
>> new file mode 100644
>> index 000000000..89b544c93
>> --- /dev/null
>> +++ b/tests/intel/xe_exec_capture.c
>> @@ -0,0 +1,308 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2024 Intel Corporation
>> + */
>> +
>> +/**
>> + * TEST: Basic tests for GuC based register capture
>> + * Category: Core
>> + * Mega feature: General Core features
>> + * Sub-category: CMD submission
>> + * Functionality: Debug
>> + * Test category: functionality test
>> + */
>> +
>> +#include <ctype.h>
>> +#include <fcntl.h>
>> +#include <stdio.h>
>> +#include <regex.h>
>> +
>> +#include "igt.h"
>> +#include "igt_device.h"
>> +#include "lib/igt_syncobj.h"
>> +#include "lib/intel_reg.h"
>> +#include "xe_drm.h"
>> +#include "xe/xe_ioctl.h"
>> +#include "xe/xe_query.h"
>> +#include "xe/xe_spin.h"
>> +
>> +#define MAX_N_EXECQUEUES 16
>> +#define MAX_INSTANCE 9
>> +#define GT_RESET (0x1 << 0)
>> +#define CLOSE_FD (0x1 << 1)
>> +#define CLOSE_EXEC_QUEUES (0x1 << 2)
>> +#define VIRTUAL (0x1 << 3)
>> +#define PARALLEL (0x1 << 4)
>> +#define CAT_ERROR (0x1 << 5)
>> +
>> +#define BASE_ADDRESS 0x1a0000
>> +/* Batch buffer element count, in number of dwords(uint32_t) */
>> +#define BATCH_DW_COUNT 16
>> +
>> +#define MAX_PATH_NAME_LEN 512
>> +#define MAX_LINES 512
>> +#define MAX_LINE_LEN 1024
>> +
>> +#define DUMP_PATH "/sys/class/drm/card%d/device/devcoredump/data"
>> +#define START_TAG "**** Job ****"
>> +#define REGEX_KEY_VALUE_PAIR "^[ \t]*([^:]+):[ \t]*([^ \t]+)[ \t]*$"
>> +#define REGEX_KEY_INDEX 1
>> +#define REGEX_VALUE_INDEX 2
>> +#define REGEX_KEY_VALUE_MATCH_COUNT 3
>> +
>> +int card_id;
>> +regex_t regex;
>> +char lines[MAX_LINES][MAX_LINE_LEN];
>
> Why only MAX_LINE here? Could you dynamically allocate mem (and eventually
> reallocate it) to fit all devcore?
The thought is only keep up to MAX_LINES here, focus on parts(after
START_TAG) for this test only.
Might be better to load all content, in future if we want to parse more
lines, there is no need to change the data loading part.
One more benefit I can think is for debugging purpose, if load all
contents in buffer, the line index+1 is equal to the line number when we
open the file in editor, make our life easier.
Will change it to load all in next rev.
>
>> +
>> +static bool access_devcoredump(bool load_file)
>> +{
>> + FILE *fd;
>> + char path[MAX_PATH_NAME_LEN];
>> +
>> + sprintf(path, DUMP_PATH, card_id);
>> + fd = fopen(path, "r");
>
> You have this pattern also below, please write a function and use it.
Will do, to support multiple cards, it would be a function like:
char *get_devcoredump_path
>
>> + if (!fd) {
>> + igt_debug("Devcoredump not exist.\n");
>
> Or there was some error, you could print errno here.
Sure, will add print errno
> Btw why FILE* ? Could you use just normal open()?
The devcoredump data is text content file, open with FILE* is more easy
to deal with text lines.
>
>> + return false;
>> + }
>> + igt_debug("Devcoredump found: %s\n", path);
>> +
>> + /* Clear memory before load file */
>> + if (load_file) {
>> + int i = 0;
>> + bool found = false;
>> +
>> + memset(lines, 0, sizeof(lines));
>> + while (!feof(fd)) {
>> + fgets(lines[i], MAX_LINE_LEN, fd);
>> +
>> + /* Only save lines after start tag */
>> + if (!found)
>> + found = strstr(lines[0], START_TAG);
>> + else
>> + if (++i >= MAX_LINES)
>> + break;
>> + }
>> + }
>> +
>> + fclose(fd);
>> + return true;
>> +}
>> +
>> +static void rm_devcoredump(void)
>
> imho this could be bool
Sounds good. When caller try to remove not existing devcoredump, it
could return false.
>
>> +{
>> + char path[MAX_PATH_NAME_LEN];
>> + int fd;
>> +
>> + igt_debug("Clearing devcoredump.\n");
>> +
>> + sprintf(path, DUMP_PATH, card_id);
>> + fd = open(path, O_WRONLY);
>> + if (fd != -1) {
>> + write(fd, "0", 1);
>> + close(fd);
>> + }
>> +}
>> +
>> +static char *get_coredump_item(const char *tag)
>> +{
>> + int i;
>> + regmatch_t match[REGEX_KEY_VALUE_MATCH_COUNT];
>> +
>> + for (i = 0; i < MAX_LINES && lines[i][0]; i++) {
>> + char *line = lines[i];
>> +
>> + /* Skip lines without tag */
>> + if (!strstr(line, tag))
>> + continue;
>> +
>> + if (regexec(®ex, line, REGEX_KEY_VALUE_MATCH_COUNT, match, 0) == 0) {
>> + char *key, *value;
>> +
>> + key = &line[match[REGEX_KEY_INDEX].rm_so];
>> + line[match[REGEX_KEY_INDEX].rm_eo] = '\0';
>> + value = &line[match[REGEX_VALUE_INDEX].rm_so];
>> + line[match[REGEX_VALUE_INDEX].rm_eo] = '\0';
>> +
>> + if (strcmp(tag, key) == 0)
>> + return value;
>> + /* if key != tag, continue */
>> + }
>> + }
>> +
>> + return NULL;
>> +}
>> +
>> +static void check_capture_output(const char *tag, uint64_t addr_lo, uint64_t addr_hi)
>> +{
>> + uint64_t result;
>> + char *output;
>> +
>> + igt_assert(output = get_coredump_item(tag));
>
> imho better igt_assert_f and print which tag is missing.
Good point, will do.
>
>> + result = strtol(output, NULL, 16);
>> + igt_debug("Compare %s: %s vs [0x%lX-0x%lX]\n", tag, output, addr_lo, addr_hi);
>> + igt_assert((addr_lo <= result) && (result <= addr_hi));
>
> Same here, you could print actual values if assert failed.
Good point, will do.
>
>> +}
>> +
>> +static void check_capture_output_str(const char *tag, const char *target)
>> +{
>> + char *output;
>> +
>> + igt_assert(output = get_coredump_item(tag));
>
> Same here.
>
>> + igt_debug("Compare %s: '%s' vs '%s'\n", tag, output, target);
>> + igt_assert(!strcmp(output, target));
>
> Same here.
>
>> +}
>> +
>> +static void check_capture_out(uint64_t base_addr, uint64_t length)
>> +{
>> + /* assert devcoredump created */
>> + assert(access_devcoredump(true));
>
> Should be igt_assert_f
Thanks, that's my typo
>
>> +
>> + check_capture_output_str("Capture_source", "GuC");
>> + check_capture_output("ACTHD", base_addr, base_addr + length);
>> + check_capture_output("RING_BBADDR", base_addr, base_addr + length);
>> +
>> + /* clear devcoredump */
>> + rm_devcoredump();
>> + sleep(1);
>> + /* Assert devcoredump removed */
>> + assert(!access_devcoredump(false));
>
> Should be igt_assert_f
same typo
>
>> +}
>> +
>> +/**
>> + * SUBTEST: close-fd
>> + * Description: Test close fd, check if devcoredump register dump is within the
>> + */
>> +static void
>> +test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
>> + int n_exec_queues, int n_execs, unsigned int flags)
>> +{
>> + uint32_t vm;
>> + const uint64_t addr = BASE_ADDRESS;
>> + struct drm_xe_sync sync[2] = {
>> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
>> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
>> + };
>> + struct drm_xe_exec exec = {
>> + .num_batch_buffer = 1,
>> + .num_syncs = 2,
>> + .syncs = to_user_pointer(sync),
>> + };
>> + uint32_t exec_queues[MAX_N_EXECQUEUES];
>> + uint32_t syncobjs[MAX_N_EXECQUEUES];
>> + size_t bo_size;
>> + uint32_t bo = 0;
>> + struct {
>> + struct xe_spin spin;
>> + uint32_t batch[BATCH_DW_COUNT];
>> + uint64_t pad;
>> + uint32_t data;
>> + } *data;
>> + struct xe_spin_opts spin_opts = { .preempt = false };
>> + int i, b;
>> +
>> + igt_assert(n_exec_queues <= MAX_N_EXECQUEUES);
>> +
>> + if (flags & CLOSE_FD)
>> + fd = drm_open_driver(DRIVER_XE);
>
> Better drm_reopen_driver()
Sounds good, while next rev will deal with multiple cards, this part
might be changed.
>
>> +
>> + vm = xe_vm_create(fd, 0, 0);
>> + bo_size = sizeof(*data) * n_execs;
>> + bo_size = xe_bb_size(fd, bo_size);
>> +
>> + bo = xe_bo_create(fd, vm, bo_size,
>> + vram_if_possible(fd, eci->gt_id),
>> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>> + data = xe_bo_map(fd, bo, bo_size);
>> +
>> + for (i = 0; i < n_exec_queues; i++) {
>> + exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0);
>> + syncobjs[i] = syncobj_create(fd, 0);
>> + };
>> +
>> + sync[0].handle = syncobj_create(fd, 0);
>> + xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1);
>> +
>> + for (i = 0; i < n_execs; i++) {
>> + uint64_t base_addr = addr;
>> + uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
>> + uint64_t batch_addr = base_addr + batch_offset;
>> + uint64_t spin_offset = (char *)&data[i].spin - (char *)data;
>> + uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
>> + uint64_t sdi_addr = base_addr + sdi_offset;
>> + uint64_t exec_addr;
>> + int e = i % n_exec_queues;
>> +
>> + if (!i) {
>> + spin_opts.addr = base_addr + spin_offset;
>> + xe_spin_init(&data[i].spin, &spin_opts);
>> + exec_addr = spin_opts.addr;
>> + } else {
>> + b = 0;
>> + data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
>> + data[i].batch[b++] = sdi_addr;
>> + data[i].batch[b++] = sdi_addr >> 32;
>> + data[i].batch[b++] = 0xc0ffee;
>> + data[i].batch[b++] = MI_BATCH_BUFFER_END;
>> + igt_assert(b <= ARRAY_SIZE(data[i].batch));
>> +
>> + exec_addr = batch_addr;
>> + }
>> +
>> + sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>> + sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>> + sync[1].handle = syncobjs[e];
>> +
>> + exec.exec_queue_id = exec_queues[e];
>> + exec.address = exec_addr;
>> + if (e != i)
>> + syncobj_reset(fd, &syncobjs[e], 1);
>> + xe_exec(fd, &exec);
>> + }
>> +
>> + for (i = 0; i < n_exec_queues && n_execs; i++)
>> + igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0,
>> + NULL));
>> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
>> +
>> + sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>> + xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
>> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
>> +
>> + syncobj_destroy(fd, sync[0].handle);
>> + for (i = 0; i < n_exec_queues; i++) {
>> + syncobj_destroy(fd, syncobjs[i]);
>> + xe_exec_queue_destroy(fd, exec_queues[i]);
>> + }
>> +
>> + munmap(data, bo_size);
>> + gem_close(fd, bo);
>> + xe_vm_destroy(fd, vm);
>> +}
>> +
>> +igt_main
>> +{
>> + struct drm_xe_engine_class_instance *hwe;
>> + int fd;
>> +
>> + igt_fixture {
>> + fd = drm_open_driver(DRIVER_XE);
>> + card_id = igt_device_get_card_index(fd);
>> +
>
> imho here clear old devcoredump
Yes, should clear old one if exist.
>
> Regards,
> Kamil
>
>> + regcomp(®ex, REGEX_KEY_VALUE_PAIR, REG_EXTENDED | REG_NEWLINE);
>> + }
>> +
>> + igt_subtest("close-fd")
>> + xe_for_each_engine(fd, hwe) {
>> + igt_debug("Running on engine class: %x instance: %x\n", hwe->engine_class,
>> + hwe->engine_instance);
>> +
>> + test_legacy_mode(fd, hwe, 1, 1, 0);
>> + check_capture_out(BASE_ADDRESS, sizeof(uint32_t) * BATCH_DW_COUNT);
>> + }
>> +
>> + igt_fixture {
>> + drm_close_driver(fd);
>> + regfree(®ex);
>> + }
>> +}
>> diff --git a/tests/meson.build b/tests/meson.build
>> index 2d8cb87d5..b724a7c6d 100644
>> --- a/tests/meson.build
>> +++ b/tests/meson.build
>> @@ -284,6 +284,7 @@ intel_xe_progs = [
>> 'xe_exec_atomic',
>> 'xe_exec_balancer',
>> 'xe_exec_basic',
>> + 'xe_exec_capture',
>> 'xe_exec_compute_mode',
>> 'xe_exec_fault_mode',
>> 'xe_exec_mix_modes',
>> --
>> 2.34.1
>>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-10-16 21:20 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-15 15:31 [PATCH i-g-t v3 0/1] tests/intel/xe_exec_capture: Add xe_exec_capture test Zhanjun Dong
2024-10-15 15:31 ` [PATCH i-g-t v3 1/1] " Zhanjun Dong
2024-10-16 5:29 ` Peter Senna Tschudin
2024-10-16 19:08 ` Dong, Zhanjun
2024-10-16 14:12 ` Kamil Konieczny
2024-10-16 21:20 ` Dong, Zhanjun
2024-10-15 20:29 ` ✓ CI.xeBAT: success for " Patchwork
2024-10-15 20:41 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-10-16 7:48 ` ✗ CI.xeFULL: " Patchwork
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