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From: Ashutosh Dixit <ashutosh.dixit@intel.com>
To: igt-dev@lists.freedesktop.org
Subject: [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update
Date: Tue, 29 Oct 2024 19:53:26 -0700	[thread overview]
Message-ID: <20241030025327.1487897-2-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20241030025327.1487897-1-ashutosh.dixit@intel.com>

Align with kernel commit c8507a25cebd ("drm/xe/oa/uapi: Define and parse OA
sync properties") which adds OA syncs uapi.

v2: Fix #ifdef identifier change (Kamil)

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 include/drm-uapi/xe_drm.h | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index f0a450db95..56163eb913 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -134,7 +134,7 @@ extern "C" {
  * redefine the interface more easily than an ever growing struct of
  * increasing complexity, and for large parts of that interface to be
  * entirely optional. The downside is more pointer chasing; chasing across
- * the boundary with pointers encapsulated inside u64.
+ * the __user boundary with pointers encapsulated inside u64.
  *
  * Example chaining:
  *
@@ -512,7 +512,9 @@ struct drm_xe_query_gt_list {
  *    containing the following in mask:
  *    ``DSS_COMPUTE    ff ff ff ff 00 00 00 00``
  *    means 32 DSS are available for compute.
- *  - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks
+ *  - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks.  This type
+ *    may be omitted if the driver is unable to query the mask from the
+ *    hardware.
  *  - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
  *    available per Dual Sub Slices (DSS). For example a query response
  *    containing the following in mask:
@@ -1483,6 +1485,7 @@ struct drm_xe_oa_unit {
 	/** @capabilities: OA capabilities bit-mask */
 	__u64 capabilities;
 #define DRM_XE_OA_CAPS_BASE		(1 << 0)
+#define DRM_XE_OA_CAPS_SYNCS		(1 << 1)
 
 	/** @oa_timestamp_freq: OA timestamp freq */
 	__u64 oa_timestamp_freq;
@@ -1632,6 +1635,22 @@ enum drm_xe_oa_property_id {
 	 * to be disabled for the stream exec queue.
 	 */
 	DRM_XE_OA_PROPERTY_NO_PREEMPT,
+
+	/**
+	 * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array
+	 * specified in @DRM_XE_OA_PROPERTY_SYNCS
+	 */
+	DRM_XE_OA_PROPERTY_NUM_SYNCS,
+
+	/**
+	 * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array
+	 * with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA
+	 * configuration will wait till input fences signal. Output fences
+	 * will signal after the new OA configuration takes effect. For
+	 * @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar
+	 * to the VM bind case.
+	 */
+	DRM_XE_OA_PROPERTY_SYNCS,
 };
 
 /**
-- 
2.41.0


  reply	other threads:[~2024-10-30  2:53 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-30  2:53 [PATCH i-g-t v5 0/2] tests/intel/oa: Tests for OA syncs Ashutosh Dixit
2024-10-30  2:53 ` Ashutosh Dixit [this message]
2024-10-30  2:53 ` [PATCH i-g-t 2/2] tests/intel/xe_oa: " Ashutosh Dixit
2024-10-30 12:54   ` Kamil Konieczny
2024-10-31  2:11     ` Dixit, Ashutosh
2024-10-30  4:07 ` ✗ Fi.CI.BAT: failure for tests/intel/oa: Tests for OA syncs (rev5) Patchwork
2024-10-30  4:07 ` ✓ CI.xeBAT: success " Patchwork
2024-10-30  8:06 ` ✗ CI.xeFULL: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2024-10-25 18:52 [PATCH i-g-t 0/2] tests/intel/oa: Tests for OA syncs Ashutosh Dixit
2024-10-25 18:52 ` [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update Ashutosh Dixit
2024-10-25 19:36   ` Umesh Nerlige Ramappa
2024-10-28 15:16   ` Kamil Konieczny
2024-10-29 19:38     ` Dixit, Ashutosh

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