[PATCH i-g-t 1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started

[PATCH i-g-t 1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started

[Lucas De Marchi]

If cork was not started, do not try to end it. Similar fix to commit
598c268686f4 ("tests/intel/xe_drm_fdinfo: Do not destroy NULL xe_cork").

Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: Pravalika Gurram <pravalika.gurram@intel.com>
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3869
Fixes: 2feb1d6718a1 ("lib/xe/xe_spin: move the spinner related functions to lib")
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index e83c55c64..6549629b4 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -533,7 +533,9 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
 	xe_for_each_engine_class(class)
-		xe_cork_sync_end(fd, ctx[class]);
+		if (ctx[class])
+			xe_cork_sync_end(fd, ctx[class]);
+
 	read_engine_cycles(fd, pceu2);
 
 	xe_for_each_engine_class(class) {
-- 
2.47.0

[PATCH i-g-t 2/8] lib/xe/xe_gt: Fix header guards and boilerplate

[Lucas De Marchi]

Add proper header guard and remove author from comment: authorship is
maintained in git, not as comment.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 lib/xe/xe_gt.c | 3 ---
 lib/xe/xe_gt.h | 8 +++++---
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/lib/xe/xe_gt.c b/lib/xe/xe_gt.c
index 1f4b42ed9..53554beb0 100644
--- a/lib/xe/xe_gt.c
+++ b/lib/xe/xe_gt.c
@@ -1,9 +1,6 @@
 /* SPDX-License-Identifier: MIT */
 /*
  * Copyright © 2023 Intel Corporation
- *
- * Authors:
- *    Janga Rahul Kumar <janga.rahul.kumar@intel.com>
  */
 
 #include <fcntl.h>
diff --git a/lib/xe/xe_gt.h b/lib/xe/xe_gt.h
index a4bb85679..756b5f38e 100644
--- a/lib/xe/xe_gt.h
+++ b/lib/xe/xe_gt.h
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: MIT */
 /*
  * Copyright © 2023 Intel Corporation
- *
- * Authors:
- *    Janga Rahul Kumar <janga.rahul.kumar@intel.com>
  */
 
+#ifndef XE_GT_H
+#define XE_GT_H
+
 #include "lib/igt_gt.h"
 
 bool has_xe_gt_reset(int fd);
@@ -14,3 +14,5 @@ igt_hang_t xe_hang_ring(int fd, uint64_t ahnd, uint32_t ctx, int ring,
 				unsigned int flags);
 void xe_post_hang_ring(int fd, igt_hang_t arg);
 int xe_gt_stats_get_count(int fd, int gt, const char *stat);
+
+#endif
-- 
2.47.0

[PATCH i-g-t 3/8] lib/xe: Move functions from xe_util to xe_gt

[Lucas De Marchi]

Some functions are clearly gt-related, so move them to xe_gt.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 lib/xe/xe_gt.c                 | 67 ++++++++++++++++++++++++++++++++++
 lib/xe/xe_gt.h                 |  8 ++++
 lib/xe/xe_util.c               | 67 ----------------------------------
 lib/xe/xe_util.h               |  7 ----
 tests/intel/xe_drm_fdinfo.c    |  2 +
 tests/intel/xe_exec_balancer.c |  1 +
 tests/intel/xe_exec_reset.c    |  1 +
 tests/intel/xe_exec_threads.c  |  1 +
 tests/intel/xe_gt_freq.c       |  1 +
 tests/intel/xe_pm_residency.c  |  2 +
 10 files changed, 83 insertions(+), 74 deletions(-)

diff --git a/lib/xe/xe_gt.c b/lib/xe/xe_gt.c
index 53554beb0..e1f353b41 100644
--- a/lib/xe/xe_gt.c
+++ b/lib/xe/xe_gt.c
@@ -174,3 +174,70 @@ int xe_gt_stats_get_count(int fd, int gt, const char *stat)
 
 	return count;
 }
+
+/**
+ * xe_is_gt_in_c6:
+ * @fd: pointer to xe drm fd
+ * @gt: gt number
+ *
+ * Check if GT is in C6 state
+ */
+bool xe_is_gt_in_c6(int fd, int gt)
+{
+	char gt_c_state[16];
+	int gt_fd;
+
+	gt_fd = xe_sysfs_gt_open(fd, gt);
+	igt_assert(gt_fd >= 0);
+	igt_assert(igt_sysfs_scanf(gt_fd, "gtidle/idle_status", "%s", gt_c_state) == 1);
+	close(gt_fd);
+
+	return strcmp(gt_c_state, "gt-c6") == 0;
+}
+
+/**
+ * xe_gt_fill_engines_by_class:
+ * @fd: pointer to xe drm fd
+ * @gt: gt number
+ * @class: engine class to use to filter engines
+ * @eci: output argument to copy engines to
+ *
+ * Fill out @drm_xe_engine_class_instance with all the engines in @gt that have
+ * a certain @class.
+ *
+ * Return: number of engines that match the gt and clas
+ */
+int xe_gt_fill_engines_by_class(int fd, int gt, int class,
+				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE])
+{
+	struct drm_xe_engine_class_instance *hwe;
+	int n = 0;
+
+	xe_for_each_engine(fd, hwe)
+		if (hwe->engine_class == class && hwe->gt_id == gt)
+			eci[n++] = *hwe;
+
+	return n;
+}
+
+/**
+ * xe_gt_count_engines_by_class:
+ * @fd: pointer to xe drm fd
+ * @gt: gt number
+ * @class: engine class to use to filter engines
+ *
+ * Count number of engines in @gt that have a certain @class.
+ *
+ * Return: number of engines that match the gt and clas
+ */
+int xe_gt_count_engines_by_class(int fd, int gt, int class)
+{
+	struct drm_xe_engine_class_instance *hwe;
+	int n = 0;
+
+	xe_for_each_engine(fd, hwe)
+		if (hwe->engine_class == class && hwe->gt_id == gt)
+			n++;
+
+	return n;
+}
diff --git a/lib/xe/xe_gt.h b/lib/xe/xe_gt.h
index 756b5f38e..47569cec3 100644
--- a/lib/xe/xe_gt.h
+++ b/lib/xe/xe_gt.h
@@ -8,6 +8,8 @@
 
 #include "lib/igt_gt.h"
 
+#include "xe_query.h"
+
 bool has_xe_gt_reset(int fd);
 void xe_force_gt_reset_all(int fd);
 igt_hang_t xe_hang_ring(int fd, uint64_t ahnd, uint32_t ctx, int ring,
@@ -15,4 +17,10 @@ igt_hang_t xe_hang_ring(int fd, uint64_t ahnd, uint32_t ctx, int ring,
 void xe_post_hang_ring(int fd, igt_hang_t arg);
 int xe_gt_stats_get_count(int fd, int gt, const char *stat);
 
+bool xe_is_gt_in_c6(int fd, int gt);
+
+int xe_gt_fill_engines_by_class(int fd, int gt, int class,
+				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE]);
+int xe_gt_count_engines_by_class(int fd, int gt, int class);
+
 #endif
diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index 9482819c2..f0b6bbb2d 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -235,70 +235,3 @@ void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine,
 
 	free(bind_ops);
 }
-
-/**
- * xe_is_gt_in_c6:
- * @fd: pointer to xe drm fd
- * @gt: gt number
- *
- * Check if GT is in C6 state
- */
-bool xe_is_gt_in_c6(int fd, int gt)
-{
-	char gt_c_state[16];
-	int gt_fd;
-
-	gt_fd = xe_sysfs_gt_open(fd, gt);
-	igt_assert(gt_fd >= 0);
-	igt_assert(igt_sysfs_scanf(gt_fd, "gtidle/idle_status", "%s", gt_c_state) == 1);
-	close(gt_fd);
-
-	return strcmp(gt_c_state, "gt-c6") == 0;
-}
-
-/**
- * xe_gt_fill_engines_by_class:
- * @fd: pointer to xe drm fd
- * @gt: gt number
- * @class: engine class to use to filter engines
- * @eci: output argument to copy engines to
- *
- * Fill out @drm_xe_engine_class_instance with all the engines in @gt that have
- * a certain @class.
- *
- * Return: number of engines that match the gt and clas
- */
-int xe_gt_fill_engines_by_class(int fd, int gt, int class,
-				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE])
-{
-	struct drm_xe_engine_class_instance *hwe;
-	int n = 0;
-
-	xe_for_each_engine(fd, hwe)
-		if (hwe->engine_class == class && hwe->gt_id == gt)
-			eci[n++] = *hwe;
-
-	return n;
-}
-
-/**
- * xe_gt_count_engines_by_class:
- * @fd: pointer to xe drm fd
- * @gt: gt number
- * @class: engine class to use to filter engines
- *
- * Count number of engines in @gt that have a certain @class.
- *
- * Return: number of engines that match the gt and clas
- */
-int xe_gt_count_engines_by_class(int fd, int gt, int class)
-{
-	struct drm_xe_engine_class_instance *hwe;
-	int n = 0;
-
-	xe_for_each_engine(fd, hwe)
-		if (hwe->engine_class == class && hwe->gt_id == gt)
-			n++;
-
-	return n;
-}
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
index b9fbfc5cd..c544d912f 100644
--- a/lib/xe/xe_util.h
+++ b/lib/xe/xe_util.h
@@ -47,11 +47,4 @@ void xe_bind_unbind_async(int fd, uint32_t vm, uint32_t bind_engine,
 			  struct igt_list_head *obj_list,
 			  uint32_t sync_in, uint32_t sync_out);
 
-bool xe_is_gt_in_c6(int fd, int gt);
-
-int xe_gt_fill_engines_by_class(int fd, int gt, int class,
-				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE]);
-int xe_gt_count_engines_by_class(int fd, int gt, int class);
-
-
 #endif /* XE_UTIL_H */
diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 6549629b4..f4264aadb 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -8,7 +8,9 @@
 #include "igt_device.h"
 #include "igt_drm_fdinfo.h"
 #include "lib/igt_syncobj.h"
+
 #include "xe_drm.h"
+#include "xe/xe_gt.h"
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "xe/xe_spin.h"
diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c
index 1e552e9ef..f2df5cbec 100644
--- a/tests/intel/xe_exec_balancer.c
+++ b/tests/intel/xe_exec_balancer.c
@@ -19,6 +19,7 @@
 #include "lib/intel_reg.h"
 #include "xe_drm.h"
 
+#include "xe/xe_gt.h"
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "xe/xe_spin.h"
diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
index a3eaf8bbf..47c7666df 100644
--- a/tests/intel/xe_exec_reset.c
+++ b/tests/intel/xe_exec_reset.c
@@ -21,6 +21,7 @@
 
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
+#include "xe/xe_gt.h"
 #include "xe/xe_spin.h"
 #include "xe/xe_util.h"
 #include <string.h>
diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c
index 661117bed..c8fc17366 100644
--- a/tests/intel/xe_exec_threads.c
+++ b/tests/intel/xe_exec_threads.c
@@ -21,6 +21,7 @@
 
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
+#include "xe/xe_gt.h"
 #include "xe/xe_spin.h"
 #include "xe/xe_util.h"
 #include <string.h>
diff --git a/tests/intel/xe_gt_freq.c b/tests/intel/xe_gt_freq.c
index de4d111ea..5d806cf15 100644
--- a/tests/intel/xe_gt_freq.c
+++ b/tests/intel/xe_gt_freq.c
@@ -17,6 +17,7 @@
 #include "igt_sysfs.h"
 
 #include "xe_drm.h"
+#include "xe/xe_gt.h"
 #include "xe/xe_ioctl.h"
 #include "xe/xe_spin.h"
 #include "xe/xe_query.h"
diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
index d4b26b231..18e5cb6c3 100644
--- a/tests/intel/xe_pm_residency.c
+++ b/tests/intel/xe_pm_residency.c
@@ -21,7 +21,9 @@
 #include "igt_sysfs.h"
 
 #include "lib/igt_syncobj.h"
+
 #include "xe/xe_ioctl.h"
+#include "xe/xe_gt.h"
 #include "xe/xe_query.h"
 #include "xe/xe_util.h"
 
-- 
2.47.0

[PATCH i-g-t 4/8] lib/xe: Rename xe_is_gt_in_c6()

[Lucas De Marchi]

Use xe_gt_ as namespace.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 lib/xe/xe_gt.c                |  4 ++--
 lib/xe/xe_gt.h                |  2 +-
 tests/intel/xe_gt_freq.c      | 12 ++++++------
 tests/intel/xe_pm_residency.c |  8 ++++----
 4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/lib/xe/xe_gt.c b/lib/xe/xe_gt.c
index e1f353b41..6f1475be0 100644
--- a/lib/xe/xe_gt.c
+++ b/lib/xe/xe_gt.c
@@ -176,13 +176,13 @@ int xe_gt_stats_get_count(int fd, int gt, const char *stat)
 }
 
 /**
- * xe_is_gt_in_c6:
+ * xe_gt_is_in_c6:
  * @fd: pointer to xe drm fd
  * @gt: gt number
  *
  * Check if GT is in C6 state
  */
-bool xe_is_gt_in_c6(int fd, int gt)
+bool xe_gt_is_in_c6(int fd, int gt)
 {
 	char gt_c_state[16];
 	int gt_fd;
diff --git a/lib/xe/xe_gt.h b/lib/xe/xe_gt.h
index 47569cec3..511b31149 100644
--- a/lib/xe/xe_gt.h
+++ b/lib/xe/xe_gt.h
@@ -17,7 +17,7 @@ igt_hang_t xe_hang_ring(int fd, uint64_t ahnd, uint32_t ctx, int ring,
 void xe_post_hang_ring(int fd, igt_hang_t arg);
 int xe_gt_stats_get_count(int fd, int gt, const char *stat);
 
-bool xe_is_gt_in_c6(int fd, int gt);
+bool xe_gt_is_in_c6(int fd, int gt);
 
 int xe_gt_fill_engines_by_class(int fd, int gt, int class,
 				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE]);
diff --git a/tests/intel/xe_gt_freq.c b/tests/intel/xe_gt_freq.c
index 5d806cf15..2ece2e6f4 100644
--- a/tests/intel/xe_gt_freq.c
+++ b/tests/intel/xe_gt_freq.c
@@ -200,7 +200,7 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle)
 
 	if (gt_idle) {
 		/* Wait for GT to go in C6 as previous get_freq wakes up GT*/
-		igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10),
+		igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt_id), 1000, 10),
 			     "GT %d should be in C6\n", gt_id);
 		igt_assert(get_freq(fd, gt_id, "act") == 0);
 	} else {
@@ -215,7 +215,7 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle)
 	igt_assert_lte_u32((rpmid - FREQ_UNIT_MHZ), cur_freq);
 
 	if (gt_idle) {
-		igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10),
+		igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt_id), 1000, 10),
 			     "GT %d should be in C6\n", gt_id);
 		igt_assert(get_freq(fd, gt_id, "act") == 0);
 	} else {
@@ -234,7 +234,7 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle)
 	igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rp0);
 
 	if (gt_idle) {
-		igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10),
+		igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt_id), 1000, 10),
 			     "GT %d should be in C6\n", gt_id);
 		igt_assert(get_freq(fd, gt_id, "act") == 0);
 	}
@@ -265,7 +265,7 @@ static void test_freq_range(int fd, int gt_id, bool gt_idle)
 	igt_assert(rpn <= cur && cur <= rpmid + FREQ_UNIT_MHZ);
 
 	if (gt_idle) {
-		igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10),
+		igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt_id), 1000, 10),
 			     "GT %d should be in C6\n", gt_id);
 		igt_assert(get_freq(fd, gt_id, "act") == 0);
 	} else {
@@ -466,7 +466,7 @@ igt_main
 
 	igt_subtest("freq_fixed_idle") {
 		xe_for_each_gt(fd, gt) {
-			igt_require_f(igt_wait(xe_is_gt_in_c6(fd, gt), 1000, 10),
+			igt_require_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 10),
 				      "GT %d should be in C6\n", gt);
 			test_freq_fixed(fd, gt, true);
 		}
@@ -484,7 +484,7 @@ igt_main
 
 	igt_subtest("freq_range_idle") {
 		xe_for_each_gt(fd, gt) {
-			igt_require_f(igt_wait(xe_is_gt_in_c6(fd, gt), 1000, 10),
+			igt_require_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 10),
 				      "GT %d should be in C6\n", gt);
 			test_freq_range(fd, gt, true);
 		}
diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
index 18e5cb6c3..0b48a1c79 100644
--- a/tests/intel/xe_pm_residency.c
+++ b/tests/intel/xe_pm_residency.c
@@ -210,7 +210,7 @@ static void test_idle_residency(int fd, int gt, enum test_type flag)
 {
 	unsigned long elapsed_ms, residency_start, residency_end;
 
-	igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt), 1000, 1), "GT %d not in C6\n", gt);
+	igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 1), "GT %d not in C6\n", gt);
 
 	if (flag == TEST_S2IDLE) {
 		/*
@@ -300,7 +300,7 @@ static void toggle_gt_c6(int fd, int n)
 		igt_assert_lte(0, fw_handle);
 		/* check if all gts are in C0 after forcewake is acquired */
 		xe_for_each_gt(fd, gt)
-			igt_assert_f(!xe_is_gt_in_c6(fd, gt),
+			igt_assert_f(!xe_gt_is_in_c6(fd, gt),
 				     "Forcewake acquired, GT %d should be in C0\n", gt);
 
 		if (n == NUM_REPS)
@@ -309,7 +309,7 @@ static void toggle_gt_c6(int fd, int n)
 		close(fw_handle);
 		/* check if all gts are in C6 after forcewake is released */
 		xe_for_each_gt(fd, gt)
-			igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt), 1000, 1),
+			igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 1),
 				     "Forcewake released, GT %d should be in C6\n", gt);
 
 		if (n == NUM_REPS)
@@ -406,7 +406,7 @@ igt_main
 	igt_subtest_with_dynamic("gt-c6-on-idle") {
 		xe_for_each_gt(fd, gt)
 			igt_dynamic_f("gt%u", gt)
-				igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt), 1000, 1),
+				igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 1),
 					     "GT %d not in C6\n", gt);
 	}
 
-- 
2.47.0

[PATCH i-g-t 5/8] lib/xe: Split nsec to ticks abstraction

[Lucas De Marchi]

There are 2 things happening here: one is converting time in nanoseconds
to ticks by using the refclock, and another asserting a spin duration is
not so close to the maximum duration since there needs to be room for
context switch.

Move the time conversion to xe_util.c and adjust it to maintain
namespace and have better names.  Places that do the time conversion to
pass to xe_spin then use the xe_spin_nsec_to_ticks() wrapper to
calculate the ticks.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 benchmarks/gem_wsim.c           |  8 +++---
 lib/xe/xe_spin.c                | 47 +++++++++------------------------
 lib/xe/xe_spin.h                |  9 +++----
 lib/xe/xe_util.c                | 40 ++++++++++++++++++++++++++++
 lib/xe/xe_util.h                |  2 ++
 tests/intel/xe_exec_mix_modes.c |  3 ++-
 tests/intel/xe_spin_batch.c     |  2 +-
 7 files changed, 66 insertions(+), 45 deletions(-)

diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index c4fd00a6a..454b6f017 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -1797,8 +1797,8 @@ xe_alloc_step_batch(struct workload *wrk, struct w_step *w)
 	xe_vm_bind_sync(fd, vm->id, w->bb_handle, 0, w->xe.exec.address, w->bb_size);
 	xe_spin_init_opts(&w->xe.data->spin, .addr = w->xe.exec.address,
 				   .preempt = (w->preempt_us > 0),
-				   .ctx_ticks = duration_to_ctx_ticks(fd, eq->hwe_list[0].gt_id,
-								1000LL * get_duration(wrk, w)));
+				   .ctx_ticks = xe_spin_nsec_to_ticks(fd, eq->hwe_list[0].gt_id,
+								      1000LL * get_duration(wrk, w)));
 	w->xe.exec.exec_queue_id = eq->id;
 	w->xe.exec.num_batch_buffer = 1;
 	/* always at least one out fence */
@@ -2655,8 +2655,8 @@ static void do_xe_exec(struct workload *wrk, struct w_step *w)
 		xe_spin_init_opts(&w->xe.data->spin,
 				  .addr = w->xe.exec.address,
 				  .preempt = (w->preempt_us > 0),
-				  .ctx_ticks = duration_to_ctx_ticks(fd, eq->hwe_list[0].gt_id,
-								1000LL * get_duration(wrk, w)));
+				  .ctx_ticks = xe_spin_nsec_to_ticks(fd, eq->hwe_list[0].gt_id,
+								     1000LL * get_duration(wrk, w)));
 	xe_exec(fd, &w->xe.exec);
 }
 
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 2bde55856..333f8d7d8 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -13,43 +13,12 @@
 #include "igt_core.h"
 #include "igt_syncobj.h"
 #include "intel_reg.h"
+
 #include "xe_ioctl.h"
 #include "xe_spin.h"
+#include "xe_util.h"
 
-static uint32_t read_timestamp_frequency(int fd, int gt_id)
-{
-	struct xe_device *dev = xe_device_get(fd);
-
-	igt_assert(dev && dev->gt_list && dev->gt_list->num_gt);
-	igt_assert(gt_id >= 0 && gt_id <= dev->gt_list->num_gt);
-
-	return dev->gt_list->gt_list[gt_id].reference_clock;
-}
-
-static uint64_t div64_u64_round_up(const uint64_t x, const uint64_t y)
-{
-	igt_assert(y > 0);
-	igt_assert_lte_u64(x, UINT64_MAX - (y - 1));
-
-	return (x + y - 1) / y;
-}
-
-/**
- * duration_to_ctx_ticks:
- * @fd: opened device
- * @gt_id: tile id
- * @duration_ns: duration in nanoseconds to be converted to context timestamp ticks
- * @return: duration converted to context timestamp ticks.
- */
-uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t duration_ns)
-{
-	uint32_t f = read_timestamp_frequency(fd, gt_id);
-	uint64_t ctx_ticks = div64_u64_round_up(duration_ns * f, NSEC_PER_SEC);
-
-	igt_assert_lt_u64(ctx_ticks, XE_SPIN_MAX_CTX_TICKS);
-
-	return ctx_ticks;
-}
+#define XE_SPIN_MAX_CTX_TICKS (UINT32_MAX - 1000)
 
 #define MI_SRM_CS_MMIO				(1 << 19)
 #define MI_LRI_CS_MMIO				(1 << 19)
@@ -60,6 +29,16 @@ uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t duration_ns)
 
 enum { START_TS, NOW_TS };
 
+
+uint32_t xe_spin_nsec_to_ticks(int fd, int gt_id, uint64_t nsec)
+{
+	uint32_t ticks = xe_nsec_to_ticks(fd, gt_id, nsec);
+
+	igt_assert_lt_u64(ticks, XE_SPIN_MAX_CTX_TICKS);
+
+	return ticks;
+}
+
 /**
  * xe_spin_init:
  * @spin: pointer to mapped bo in which spinner code will be written
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index 593065bc0..01f45eaeb 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -15,10 +15,8 @@
 #include "xe_query.h"
 #include "lib/igt_dummyload.h"
 
-#define XE_SPIN_MAX_CTX_TICKS (UINT32_MAX - 1000)
-
-/** struct xe_spin_opts
- *
+/**
+ * struct xe_spin_opts
  * @addr: offset of spinner within vm
  * @preempt: allow spinner to be preempted or not
  * @ctx_ticks: number of ticks after which spinner is stopped, applied if > 0
@@ -68,7 +66,6 @@ struct xe_cork {
 };
 
 igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
-uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
 void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
 struct xe_cork *
 xe_cork_create(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
@@ -82,6 +79,8 @@ void xe_cork_destroy(int fd, struct xe_cork *ctx);
 #define xe_spin_init_opts(fd, ...) \
 	xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
 
+uint32_t xe_spin_nsec_to_ticks(int fd, int gt_id, uint64_t nsec);
+
 bool xe_spin_started(struct xe_spin *spin);
 void xe_spin_sync_wait(int fd, struct igt_spin *spin);
 void xe_spin_wait_started(struct xe_spin *spin);
diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index f0b6bbb2d..06b378ce0 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -4,9 +4,11 @@
  */
 
 #include "igt.h"
+#include "igt_core.h"
 #include "igt_syncobj.h"
 #include "igt_sysfs.h"
 #include "intel_pat.h"
+
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "xe/xe_util.h"
@@ -235,3 +237,41 @@ void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine,
 
 	free(bind_ops);
 }
+
+static uint32_t reference_clock(int fd, int gt_id)
+{
+	struct xe_device *dev = xe_device_get(fd);
+	uint32_t refclock;
+
+	igt_assert(dev && dev->gt_list && dev->gt_list->num_gt);
+	igt_assert(gt_id >= 0 && gt_id <= dev->gt_list->num_gt);
+
+	refclock = dev->gt_list->gt_list[gt_id].reference_clock;
+
+	igt_assert_lt(0, refclock);
+
+	return refclock;
+}
+
+static uint64_t div64_u64_round_up(const uint64_t x, const uint64_t y)
+{
+	igt_assert(y > 0);
+	igt_assert_lte_u64(x, UINT64_MAX - (y - 1));
+
+	return (x + y - 1) / y;
+}
+
+/**
+ * xe_nsec_to_ticks: convert time in nanoseconds to timestamp ticks
+ * @fd: opened device
+ * @gt_id: tile id
+ * @nsec: time in nanoseconds
+ *
+ * Return: Time converted to context timestamp ticks.
+ */
+uint32_t xe_nsec_to_ticks(int fd, int gt_id, uint64_t nsec)
+{
+	uint32_t refclock = reference_clock(fd, gt_id);
+
+	return div64_u64_round_up(nsec * refclock, NSEC_PER_SEC);
+}
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
index c544d912f..06ebd3c2a 100644
--- a/lib/xe/xe_util.h
+++ b/lib/xe/xe_util.h
@@ -47,4 +47,6 @@ void xe_bind_unbind_async(int fd, uint32_t vm, uint32_t bind_engine,
 			  struct igt_list_head *obj_list,
 			  uint32_t sync_in, uint32_t sync_out);
 
+uint32_t xe_nsec_to_ticks(int fd, int gt_id, uint64_t ns);
+
 #endif /* XE_UTIL_H */
diff --git a/tests/intel/xe_exec_mix_modes.c b/tests/intel/xe_exec_mix_modes.c
index eeae9d122..0bcd49cc0 100644
--- a/tests/intel/xe_exec_mix_modes.c
+++ b/tests/intel/xe_exec_mix_modes.c
@@ -22,6 +22,7 @@
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "xe/xe_spin.h"
+#include "xe/xe_util.h"
 #include <string.h>
 
 #define FLAG_EXEC_MODE_LR	(0x1 << 0)
@@ -132,7 +133,7 @@ run_job(int fd, struct drm_xe_engine_class_instance *hwe,
 
 	if (job_type == SPINNER_INTERRUPTED) {
 		spin_opts.addr = addr + (char *)&data[SPIN_DATA].spin - (char *)data;
-		spin_opts.ctx_ticks = duration_to_ctx_ticks(fd, 0, duration_ns);
+		spin_opts.ctx_ticks = xe_spin_nsec_to_ticks(fd, 0, duration_ns);
 		xe_spin_init(&data[SPIN_DATA].spin, &spin_opts);
 		if (engine_execution_mode == EXEC_MODE_LR)
 			sync[0].addr = addr + (char *)&data[SPIN_DATA].exec_sync - (char *)data;
diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index 0ad2490a0..5d9afaf3d 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -277,7 +277,7 @@ static void xe_spin_fixed_duration(int fd, int gt, int class, int flags)
 	xe_vm_bind_sync(fd, vm, bo, 0, spin_addr, bo_size);
 	xe_spin_init_opts(spin, .addr = spin_addr,
 				.preempt = true,
-				.ctx_ticks = duration_to_ctx_ticks(fd, 0, duration_ns));
+				.ctx_ticks = xe_spin_nsec_to_ticks(fd, 0, duration_ns));
 	exec.address = spin_addr;
 	exec.exec_queue_id = exec_queue;
 
-- 
2.47.0

[PATCH i-g-t 6/8] lib/xe/xe_spin: Move declarations around

[Lucas De Marchi]

xe_spin.h has 3 abstractions:

1) the integration with igt_dummyload
2) xe_spin, the bo to be exec'ed somewhere
3) xe_cork, that resembles more the igt_spin, abstracting the fd, vm,
   bind, etc

Group them so it's easier to understand each one.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 lib/xe/xe_spin.c |  2 +-
 lib/xe/xe_spin.h | 54 +++++++++++++++++++++++++++---------------------
 2 files changed, 32 insertions(+), 24 deletions(-)

diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 333f8d7d8..bb6318cef 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -232,7 +232,7 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt)
 	return spin;
 }
 
-void xe_spin_sync_wait(int fd, struct igt_spin *spin)
+static void xe_spin_sync_wait(int fd, struct igt_spin *spin)
 {
 	igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0, NULL));
 }
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index 01f45eaeb..7c95996c3 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -15,6 +15,15 @@
 #include "xe_query.h"
 #include "lib/igt_dummyload.h"
 
+/* Wrapper to integrate with igt_dummyload, aka igt_spin */
+igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
+void xe_spin_free(int fd, struct igt_spin *spin);
+
+/*
+ * xe_spin: abstract a bo mapped in the GPU that when exec'ed will spin the
+ * engine in which it's exec'ed
+ */
+
 /**
  * struct xe_spin_opts
  * @addr: offset of spinner within vm
@@ -30,11 +39,6 @@ struct xe_spin_opts {
 	bool write_timestamp;
 };
 
-struct xe_cork_opts {
-	uint64_t ahnd;
-	bool debug;
-};
-
 /* Mapped GPU object */
 struct xe_spin {
 	uint32_t batch[128];
@@ -46,6 +50,24 @@ struct xe_spin {
 	uint32_t timestamp;
 };
 
+uint32_t xe_spin_nsec_to_ticks(int fd, int gt_id, uint64_t nsec);
+void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
+#define xe_spin_init_opts(fd, ...) \
+	xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
+bool xe_spin_started(struct xe_spin *spin);
+void xe_spin_wait_started(struct xe_spin *spin);
+void xe_spin_end(struct xe_spin *spin);
+
+/*
+ * xe_cork: higher level API that simplifies exec'ing an xe_spin by taking care
+ * of vm creation, exec call, etc.
+ */
+
+struct xe_cork_opts {
+	uint64_t ahnd;
+	bool debug;
+};
+
 struct xe_cork {
 	struct xe_spin *spin;
 	int fd;
@@ -65,27 +87,13 @@ struct xe_cork {
 	uint16_t num_placements;
 };
 
-igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
-void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
-struct xe_cork *
-xe_cork_create(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
-	      uint16_t width, uint16_t num_placements, struct xe_cork_opts *opts);
-void xe_cork_destroy(int fd, struct xe_cork *ctx);
-
+struct xe_cork *xe_cork_create(int fd, struct drm_xe_engine_class_instance *hwe,
+			       uint32_t vm, uint16_t width, uint16_t num_placements,
+			       struct xe_cork_opts *opts);
 #define xe_cork_create_opts(fd, hwe, vm, width, num_placements, ...) \
 	xe_cork_create(fd, hwe, vm, width, num_placements, \
 			&((struct xe_cork_opts){__VA_ARGS__}))
-
-#define xe_spin_init_opts(fd, ...) \
-	xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
-
-uint32_t xe_spin_nsec_to_ticks(int fd, int gt_id, uint64_t nsec);
-
-bool xe_spin_started(struct xe_spin *spin);
-void xe_spin_sync_wait(int fd, struct igt_spin *spin);
-void xe_spin_wait_started(struct xe_spin *spin);
-void xe_spin_end(struct xe_spin *spin);
-void xe_spin_free(int fd, struct igt_spin *spin);
+void xe_cork_destroy(int fd, struct xe_cork *ctx);
 void xe_cork_sync_start(int fd, struct xe_cork *ctx);
 void xe_cork_sync_end(int fd, struct xe_cork *ctx);
 
-- 
2.47.0

[PATCH i-g-t 7/8] treewide: s/ctx/cork/ when referring to xe_cork

[Lucas De Marchi]

Commit 2feb1d6718a1 ("lib/xe/xe_spin: move the spinner related functions
to lib") extracted the spin_ctx abstraction from xe_drm_fdinfo to be
re-used in other places as part of the xe_cork. Complement it by also
renaming the variable s/ctx/cork/ when referring to struct xe_cork.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 lib/xe/xe_spin.c            | 158 ++++++++++++++++++------------------
 tests/intel/xe_drm_fdinfo.c |  74 ++++++++---------
 tests/intel/xe_spin_batch.c |  14 ++--
 tests/intel/xe_vm.c         |  12 +--
 4 files changed, 129 insertions(+), 129 deletions(-)

diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index bb6318cef..0de0b1f2e 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -291,148 +291,148 @@ xe_cork_create(int fd, struct drm_xe_engine_class_instance *hwe,
 		uint32_t vm, uint16_t width, uint16_t num_placements,
 		struct xe_cork_opts *opts)
 {
-	struct xe_cork *ctx = calloc(1, sizeof(*ctx));
+	struct xe_cork *cork = calloc(1, sizeof(*cork));
 
-	igt_assert(ctx);
+	igt_assert(cork);
 	igt_assert(width && num_placements &&
 		   (width == 1 || num_placements == 1));
 	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
 
-	ctx->class = hwe->engine_class;
-	ctx->width = width;
-	ctx->num_placements = num_placements;
-	ctx->vm = vm;
-	ctx->cork_opts = *opts;
-
-	ctx->exec.num_batch_buffer = width;
-	ctx->exec.num_syncs = 2;
-	ctx->exec.syncs = to_user_pointer(ctx->sync);
-
-	ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
-	ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
-	ctx->sync[0].handle = syncobj_create(fd, 0);
-
-	ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
-	ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
-	ctx->sync[1].handle = syncobj_create(fd, 0);
-
-	ctx->bo_size = sizeof(struct xe_spin);
-	ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
-	ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
-			       vram_if_possible(fd, hwe->gt_id),
-			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
-	if (ctx->cork_opts.ahnd) {
+	cork->class = hwe->engine_class;
+	cork->width = width;
+	cork->num_placements = num_placements;
+	cork->vm = vm;
+	cork->cork_opts = *opts;
+
+	cork->exec.num_batch_buffer = width;
+	cork->exec.num_syncs = 2;
+	cork->exec.syncs = to_user_pointer(cork->sync);
+
+	cork->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+	cork->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
+	cork->sync[0].handle = syncobj_create(fd, 0);
+
+	cork->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+	cork->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
+	cork->sync[1].handle = syncobj_create(fd, 0);
+
+	cork->bo_size = sizeof(struct xe_spin);
+	cork->bo_size = xe_bb_size(fd, cork->bo_size);
+	cork->bo = xe_bo_create(fd, cork->vm, cork->bo_size,
+				vram_if_possible(fd, hwe->gt_id),
+				DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+	if (cork->cork_opts.ahnd) {
 		for (unsigned int i = 0; i < width; i++)
-			ctx->addr[i] = intel_allocator_alloc_with_strategy(ctx->cork_opts.ahnd,
-					ctx->bo, ctx->bo_size, 0,
+			cork->addr[i] = intel_allocator_alloc_with_strategy(cork->cork_opts.ahnd,
+					cork->bo, cork->bo_size, 0,
 					ALLOC_STRATEGY_LOW_TO_HIGH);
 	} else {
 		for (unsigned int i = 0; i < width; i++)
-			ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
+			cork->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
 	}
 
-	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
+	cork->spin = xe_bo_map(fd, cork->bo, cork->bo_size);
 
-	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
-					     hwe, 0, &ctx->exec_queue), 0);
+	igt_assert_eq(__xe_exec_queue_create(fd, cork->vm, width, num_placements,
+					     hwe, 0, &cork->exec_queue), 0);
 
-	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
-			 ctx->sync, 1);
+	xe_vm_bind_async(fd, cork->vm, 0, cork->bo, 0, cork->addr[0], cork->bo_size,
+			 cork->sync, 1);
 
-	return ctx;
+	return cork;
 }
 
 /**
  * xe_cork_sync_start:
  *
  * @fd: xe device fd
- * @ctx: pointer to xe_cork structure
+ * @cork: pointer to xe_cork structure
  *
  * run the spinner using xe_spin_init submit batch using xe_exec
  * and wait for fence using syncobj_wait
  */
-void xe_cork_sync_start(int fd, struct xe_cork *ctx)
+void xe_cork_sync_start(int fd, struct xe_cork *cork)
 {
-	igt_assert(ctx);
+	igt_assert(cork);
 
-	ctx->spin_opts.addr = ctx->addr[0];
-	ctx->spin_opts.write_timestamp = true;
-	ctx->spin_opts.preempt = true;
-	xe_spin_init(ctx->spin, &ctx->spin_opts);
+	cork->spin_opts.addr = cork->addr[0];
+	cork->spin_opts.write_timestamp = true;
+	cork->spin_opts.preempt = true;
+	xe_spin_init(cork->spin, &cork->spin_opts);
 
 	/* reuse sync[0] as in-fence for exec */
-	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+	cork->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
 
-	ctx->exec.exec_queue_id = ctx->exec_queue;
+	cork->exec.exec_queue_id = cork->exec_queue;
 
-	if (ctx->width > 1)
-		ctx->exec.address = to_user_pointer(ctx->addr);
+	if (cork->width > 1)
+		cork->exec.address = to_user_pointer(cork->addr);
 	else
-		ctx->exec.address = ctx->addr[0];
+		cork->exec.address = cork->addr[0];
 
-	xe_exec(fd, &ctx->exec);
+	xe_exec(fd, &cork->exec);
 
-	xe_spin_wait_started(ctx->spin);
-	igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
+	xe_spin_wait_started(cork->spin);
+	igt_assert(!syncobj_wait(fd, &cork->sync[1].handle, 1, 1, 0, NULL));
 
-	if (ctx->cork_opts.debug)
-		igt_info("%d: spinner started\n", ctx->class);
+	if (cork->cork_opts.debug)
+		igt_info("%d: spinner started\n", cork->class);
 }
 
 /*
  * xe_cork_sync_end
  *
  * @fd: xe device fd
- * @ctx: pointer to xe_cork structure
+ * @cork: pointer to xe_cork structure
  *
  * Wrapper to end spinner created by xe_cork_create. It will
  * unbind the vm which was binded to the exec_queue and bo.
  */
-void xe_cork_sync_end(int fd, struct xe_cork *ctx)
+void xe_cork_sync_end(int fd, struct xe_cork *cork)
 {
-	igt_assert(ctx);
+	igt_assert(cork);
 
-	if (ctx->ended)
-		igt_warn("Don't attempt call end twice %d\n", ctx->ended);
+	if (cork->ended)
+		igt_warn("Don't attempt call end twice %d\n", cork->ended);
 
-	xe_spin_end(ctx->spin);
+	xe_spin_end(cork->spin);
 
-	igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
+	igt_assert(syncobj_wait(fd, &cork->sync[1].handle, 1, INT64_MAX, 0, NULL));
 
-	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
-	syncobj_reset(fd, &ctx->sync[0].handle, 1);
+	cork->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+	syncobj_reset(fd, &cork->sync[0].handle, 1);
 
-	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
-	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
+	xe_vm_unbind_async(fd, cork->vm, 0, 0, cork->addr[0], cork->bo_size, cork->sync, 1);
+	igt_assert(syncobj_wait(fd, &cork->sync[0].handle, 1, INT64_MAX, 0, NULL));
 
-	ctx->ended = true;
+	cork->ended = true;
 
-	if (ctx->cork_opts.debug)
-		igt_info("%d: spinner ended (timestamp=%u)\n", ctx->class,
-			ctx->spin->timestamp);
+	if (cork->cork_opts.debug)
+		igt_info("%d: spinner ended (timestamp=%u)\n", cork->class,
+			cork->spin->timestamp);
 }
 
 /*
  * xe_cork_destroy
  *
  * @fd: xe device fd
- * @ctx: pointer to xe_cork structure
+ * @cork: pointer to xe_cork structure
  *
- * It will destroy vm, exec_queue and free the ctx.
+ * It will destroy vm, exec_queue and free the cork.
  */
-void xe_cork_destroy(int fd, struct xe_cork *ctx)
+void xe_cork_destroy(int fd, struct xe_cork *cork)
 {
-	igt_assert(ctx);
+	igt_assert(cork);
 
-	syncobj_destroy(fd, ctx->sync[0].handle);
-	syncobj_destroy(fd, ctx->sync[1].handle);
-	xe_exec_queue_destroy(fd, ctx->exec_queue);
+	syncobj_destroy(fd, cork->sync[0].handle);
+	syncobj_destroy(fd, cork->sync[1].handle);
+	xe_exec_queue_destroy(fd, cork->exec_queue);
 
-	if (ctx->cork_opts.ahnd)
-		intel_allocator_free(ctx->cork_opts.ahnd, ctx->bo);
+	if (cork->cork_opts.ahnd)
+		intel_allocator_free(cork->cork_opts.ahnd, cork->bo);
 
-	munmap(ctx->spin, ctx->bo_size);
-	gem_close(fd, ctx->bo);
+	munmap(cork->spin, cork->bo_size);
+	gem_close(fd, cork->bo);
 
-	free(ctx);
+	free(cork);
 }
diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index f4264aadb..1089e5119 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -410,7 +410,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 {
 	struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
-	struct xe_cork *ctx = NULL;
+	struct xe_cork *cork = NULL;
 	enum expected_load expected_load;
 	uint32_t vm;
 	int new_fd;
@@ -420,8 +420,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 
 	vm = xe_vm_create(fd, 0, 0);
 	if (flags & TEST_BUSY) {
-		ctx = xe_cork_create_opts(fd, hwe, vm, 1, 1);
-		xe_cork_sync_start(fd, ctx);
+		cork = xe_cork_create_opts(fd, hwe, vm, 1, 1);
+		xe_cork_sync_start(fd, cork);
 	}
 
 	read_engine_cycles(fd, pceu1[0]);
@@ -430,7 +430,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 
 	usleep(batch_duration_usec);
 	if (flags & TEST_TRAILING_IDLE)
-		xe_cork_sync_end(fd, ctx);
+		xe_cork_sync_end(fd, cork);
 
 	read_engine_cycles(fd, pceu2[0]);
 	if (flags & TEST_ISOLATION)
@@ -449,8 +449,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 		close(new_fd);
 	}
 
-	if (flags & TEST_BUSY)
-		xe_cork_destroy(fd, ctx);
+	if (cork)
+		xe_cork_destroy(fd, cork);
 
 	xe_vm_destroy(fd, vm);
 }
@@ -460,19 +460,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
-	struct xe_cork *ctx = NULL;
+	struct xe_cork *cork;
 	uint32_t vm;
 
 	vm = xe_vm_create(fd, 0, 0);
-	ctx = xe_cork_create_opts(fd, hwe, vm, 1, 1);
-	xe_cork_sync_start(fd, ctx);
+	cork = xe_cork_create_opts(fd, hwe, vm, 1, 1);
+	xe_cork_sync_start(fd, cork);
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
 
 	/* destroy queue before sampling again */
-	xe_cork_sync_end(fd, ctx);
-	xe_cork_destroy(fd, ctx);
+	xe_cork_sync_end(fd, cork);
+	xe_cork_destroy(fd, cork);
 
 	read_engine_cycles(fd, pceu2);
 
@@ -486,17 +486,17 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
-	struct xe_cork *ctx = NULL;
+	struct xe_cork *cork;
 	uint32_t vm;
 	int class;
 
 	vm = xe_vm_create(fd, 0, 0);
-	ctx = xe_cork_create_opts(fd, hwe, vm, 1, 1);
-	xe_cork_sync_start(fd, ctx);
+	cork = xe_cork_create_opts(fd, hwe, vm, 1, 1);
+	xe_cork_sync_start(fd, cork);
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
-	xe_cork_sync_end(fd, ctx);
+	xe_cork_sync_end(fd, cork);
 	read_engine_cycles(fd, pceu2);
 
 	xe_for_each_engine_class(class) {
@@ -506,7 +506,7 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
 		check_results(pceu1, pceu2, class, 1, expected_load);
 	}
 
-	xe_cork_destroy(fd, ctx);
+	xe_cork_destroy(fd, cork);
 	xe_vm_destroy(fd, vm);
 }
 
@@ -515,7 +515,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
-	struct xe_cork *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
+	struct xe_cork *cork[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
 	struct drm_xe_engine_class_instance *_hwe;
 	uint32_t vm;
 	int class;
@@ -526,17 +526,17 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 	xe_for_each_engine(fd, _hwe) {
 		int _class = _hwe->engine_class;
 
-		if (_class == hwe->engine_class || ctx[_class])
+		if (_class == hwe->engine_class || cork[_class])
 			continue;
-		ctx[_class] = xe_cork_create_opts(fd, _hwe, vm, 1, 1);
-		xe_cork_sync_start(fd, ctx[_class]);
+		cork[_class] = xe_cork_create_opts(fd, _hwe, vm, 1, 1);
+		xe_cork_sync_start(fd, cork[_class]);
 	}
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
 	xe_for_each_engine_class(class)
-		if (ctx[class])
-			xe_cork_sync_end(fd, ctx[class]);
+		if (cork[class])
+			xe_cork_sync_end(fd, cork[class]);
 
 	read_engine_cycles(fd, pceu2);
 
@@ -544,11 +544,11 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 		enum expected_load expected_load = hwe->engine_class == class ?
 			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
 
-		if (!ctx[class])
+		if (!cork[class])
 			continue;
 
 		check_results(pceu1, pceu2, class, 1, expected_load);
-		xe_cork_destroy(fd, ctx[class]);
+		xe_cork_destroy(fd, cork[class]);
 	}
 
 	xe_vm_destroy(fd, vm);
@@ -559,7 +559,7 @@ utilization_all_full_load(int fd)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
-	struct xe_cork *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
+	struct xe_cork *cork[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
 	struct drm_xe_engine_class_instance *hwe;
 	uint32_t vm;
 	int class;
@@ -569,24 +569,24 @@ utilization_all_full_load(int fd)
 	/* spin on one hwe per class */
 	xe_for_each_engine(fd, hwe) {
 		class = hwe->engine_class;
-		if (ctx[class])
+		if (cork[class])
 			continue;
-		ctx[class] = xe_cork_create_opts(fd, hwe, vm, 1, 1);
-		xe_cork_sync_start(fd, ctx[class]);
+		cork[class] = xe_cork_create_opts(fd, hwe, vm, 1, 1);
+		xe_cork_sync_start(fd, cork[class]);
 	}
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
 	xe_for_each_engine_class(class)
-		xe_cork_sync_end(fd, ctx[class]);
+		xe_cork_sync_end(fd, cork[class]);
 	read_engine_cycles(fd, pceu2);
 
 	xe_for_each_engine_class(class) {
-		if (!ctx[class])
+		if (!cork[class])
 			continue;
 
 		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
-		xe_cork_destroy(fd, ctx[class]);
+		xe_cork_destroy(fd, cork[class]);
 	}
 
 	xe_vm_destroy(fd, vm);
@@ -613,7 +613,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
 	struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
-	struct xe_cork *ctx = NULL;
+	struct xe_cork *cork = NULL;
 	enum expected_load expected_load;
 	int fd_spill, num_placements;
 	uint32_t vm;
@@ -639,8 +639,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
 
 	vm = xe_vm_create(fd, 0, 0);
 	if (flags & TEST_BUSY) {
-		ctx = xe_cork_create_opts(fd, eci, vm, width, num_placements);
-		xe_cork_sync_start(fd, ctx);
+		cork = xe_cork_create_opts(fd, eci, vm, width, num_placements);
+		xe_cork_sync_start(fd, cork);
 	}
 
 	read_engine_cycles(fd, pceu[0]);
@@ -649,7 +649,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
 
 	usleep(batch_duration_usec);
 	if (flags & TEST_TRAILING_IDLE)
-		xe_cork_sync_end(fd, ctx);
+		xe_cork_sync_end(fd, cork);
 
 	read_engine_cycles(fd, pceu[1]);
 	if (flags & TEST_ISOLATION)
@@ -669,8 +669,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
 		close(fd_spill);
 	}
 
-	if (flags & TEST_BUSY)
-		xe_cork_destroy(fd, ctx);
+	if (cork)
+		xe_cork_destroy(fd, cork);
 
 	xe_vm_destroy(fd, vm);
 }
diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index 5d9afaf3d..e4000f50e 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -384,25 +384,25 @@ static void exec_store(int fd, struct drm_xe_engine_class_instance *eci,
 
 static void run_spinner(int fd, struct drm_xe_engine_class_instance *eci)
 {
-	struct xe_cork *ctx = NULL;
+	struct xe_cork *cork;
 	uint32_t vm;
 	uint32_t ts_1, ts_2;
 	uint64_t ahnd;
 
 	vm = xe_vm_create(fd, 0, 0);
 	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
-	ctx = xe_cork_create_opts(fd, eci, vm, 1, 1, .ahnd = ahnd);
-	xe_cork_sync_start(fd, ctx);
+	cork = xe_cork_create_opts(fd, eci, vm, 1, 1, .ahnd = ahnd);
+	xe_cork_sync_start(fd, cork);
 
 	/* Collect and check timestamps before stopping the spinner */
 	usleep(50000);
-	ts_1 = READ_ONCE(ctx->spin->timestamp);
+	ts_1 = READ_ONCE(cork->spin->timestamp);
 	usleep(50000);
-	ts_2 = READ_ONCE(ctx->spin->timestamp);
+	ts_2 = READ_ONCE(cork->spin->timestamp);
 	igt_assert_neq_u32(ts_1, ts_2);
 
-	xe_cork_sync_end(fd, ctx);
-	xe_cork_destroy(fd, ctx);
+	xe_cork_sync_end(fd, cork);
+	xe_cork_destroy(fd, cork);
 
 	xe_vm_destroy(fd, vm);
 	put_ahnd(ahnd);
diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
index b10269191..9e524578a 100644
--- a/tests/intel/xe_vm.c
+++ b/tests/intel/xe_vm.c
@@ -945,21 +945,21 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
 
 	sync[0].handle = syncobj_create(fd, 0);
 	if (flags & BIND_ARRAY_ENOBUFS_FLAG) {
-		struct xe_cork *ctx = NULL;
+		struct xe_cork *cork;
 		uint32_t vm_cork;
 
 		vm_cork = xe_vm_create(fd, 0, 0);
-		ctx = xe_cork_create_opts(fd, eci, vm_cork, 1, 1);
-		xe_cork_sync_start(fd, ctx);
+		cork = xe_cork_create_opts(fd, eci, vm_cork, 1, 1);
+		xe_cork_sync_start(fd, cork);
 
-		sync[1].handle = ctx->sync[1].handle;
+		sync[1].handle = cork->sync[1].handle;
 		sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
 
 		xe_vm_bind_array_err(fd, vm, bind_exec_queue, bind_ops,
 				     n_execs, sync, 2, ENOBUFS);
 		/* destroy queue before sampling again */
-		xe_cork_sync_end(fd, ctx);
-		xe_cork_destroy(fd, ctx);
+		xe_cork_sync_end(fd, cork);
+		xe_cork_destroy(fd, cork);
 		xe_vm_destroy(fd, vm_cork);
 
 		n_execs = n_execs / 4;
-- 
2.47.0

[PATCH i-g-t 8/8] tests/intel/xe_drm_fdinfo: Stop asserting on usage percentage

[Lucas De Marchi]

It's unreliable to assert on the usage percentage considering 2 data
points as it still depends on the CPU scheduling not preempting tasks in
the wrong moment. On a normal use case of a top-like application, the
value not accounted for would simply show up in the next sample without
much issue. For a test assertion, it's better to check that the value
reported via fdinfo is reasonably close to the one saved by the GPU in
the spin. It's still allowed some error because there are a few GPU
ticks of difference due to the **GPU** scheduling the contexts.

Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 49 +++++++++++++++++++++++--------------
 1 file changed, 31 insertions(+), 18 deletions(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 1089e5119..120436fbe 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -3,6 +3,8 @@
  * Copyright © 2023 Intel Corporation
  */
 
+#include <math.h>
+
 #include "igt.h"
 #include "igt_core.h"
 #include "igt_device.h"
@@ -371,7 +373,8 @@ static void basic_engine_utilization(int xe)
 
 static void
 check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
-	      int class, int width, enum expected_load expected_load)
+	      int class, int width, uint32_t spin_stamp,
+	      enum expected_load expected_load)
 {
 	double percent;
 	u64 den, num;
@@ -383,12 +386,9 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
 
 	num = s2[class].cycles - s1[class].cycles;
 	den = s2[class].total_cycles - s1[class].total_cycles;
-	percent = (num * 100.0) / (den + 1);
-
-	/* for parallel submission scale the busyness with width */
-	percent /= width;
 
-	igt_debug("%s: percent: %f\n", engine_map[class], percent);
+	percent = (num * 100.0) / (den + 1) / width;
+	igt_debug("%s: percent: %.2f%%\n", engine_map[class], percent);
 
 	switch (expected_load) {
 	case EXPECTED_LOAD_IDLE:
@@ -396,11 +396,12 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
 		break;
 	case EXPECTED_LOAD_FULL:
 		/*
-		 * We are still relying on CPU sleep time and there could be
-		 * some imprecision when calculating the load. Use a 5% margin.
+		 * percentage error between value saved by gpu in xe_spin and what
+		 * is reported via fdinfo
 		 */
-		igt_assert_lt_double(95.0, percent);
-		igt_assert_lt_double(percent, 105.0);
+		percent = fabs((num - spin_stamp) * 100.0) / (spin_stamp + 1);
+		igt_debug("%s: error: %.2f%%\n", engine_map[class], percent);
+		igt_assert_lt_double(percent, 5.0);
 		break;
 	}
 }
@@ -438,14 +439,17 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 
 	expected_load = flags & TEST_BUSY ?
 	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
-	check_results(pceu1[0], pceu2[0], hwe->engine_class, 1, expected_load);
+
+	check_results(pceu1[0], pceu2[0], hwe->engine_class, 1,
+		      cork ? cork->spin->timestamp : 0, expected_load);
 
 	if (flags & TEST_ISOLATION) {
 		/*
 		 * Load from one client shouldn't spill on another,
 		 * so check for idle
 		 */
-		check_results(pceu1[1], pceu2[1], hwe->engine_class, 1, EXPECTED_LOAD_IDLE);
+		check_results(pceu1[1], pceu2[1], hwe->engine_class, 1, 0,
+			      EXPECTED_LOAD_IDLE);
 		close(new_fd);
 	}
 
@@ -461,6 +465,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct xe_cork *cork;
+	uint32_t timestamp;
 	uint32_t vm;
 
 	vm = xe_vm_create(fd, 0, 0);
@@ -472,13 +477,15 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
 
 	/* destroy queue before sampling again */
 	xe_cork_sync_end(fd, cork);
+	timestamp = cork->spin->timestamp;
 	xe_cork_destroy(fd, cork);
 
 	read_engine_cycles(fd, pceu2);
 
 	xe_vm_destroy(fd, vm);
 
-	check_results(pceu1, pceu2, hwe->engine_class, 1, EXPECTED_LOAD_FULL);
+	check_results(pceu1, pceu2, hwe->engine_class, 1, timestamp,
+		      EXPECTED_LOAD_FULL);
 }
 
 static void
@@ -503,7 +510,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
 		enum expected_load expected_load = hwe->engine_class != class ?
 			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
 
-		check_results(pceu1, pceu2, class, 1, expected_load);
+		check_results(pceu1, pceu2, class, 1, cork->spin->timestamp,
+			      expected_load);
 	}
 
 	xe_cork_destroy(fd, cork);
@@ -547,7 +555,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 		if (!cork[class])
 			continue;
 
-		check_results(pceu1, pceu2, class, 1, expected_load);
+		check_results(pceu1, pceu2, class, 1, cork[class]->spin->timestamp,
+			      expected_load);
 		xe_cork_destroy(fd, cork[class]);
 	}
 
@@ -585,7 +594,9 @@ utilization_all_full_load(int fd)
 		if (!cork[class])
 			continue;
 
-		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
+		check_results(pceu1, pceu2, class, 1,
+			      cork[class]->spin->timestamp,
+			      EXPECTED_LOAD_FULL);
 		xe_cork_destroy(fd, cork[class]);
 	}
 
@@ -657,14 +668,16 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
 
 	expected_load = flags & TEST_BUSY ?
 	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
-	check_results(pceu[0], pceu[1], class, width, expected_load);
+
+	check_results(pceu[0], pceu[1], class, width,
+		      cork ? cork->spin->timestamp : 0, expected_load);
 
 	if (flags & TEST_ISOLATION) {
 		/*
 		 * Load from one client shouldn't spill on another,
 		 * so check for idle
 		 */
-		check_results(pceu_spill[0], pceu_spill[1], class, width,
+		check_results(pceu_spill[0], pceu_spill[1], class, width, 0,
 			      EXPECTED_LOAD_IDLE);
 		close(fd_spill);
 	}
-- 
2.47.0

✓ i915.CI.BAT: success for series starting with [i-g-t,1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started (rev2)
URL   : https://patchwork.freedesktop.org/series/143108/
State : success

== Summary ==

CI Bug Log - changes from IGT_8174 -> IGTPW_12393
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/index.html

Participating hosts (40 -> 37)
------------------------------

  Missing    (3): bat-atsm-1 fi-snb-2520m fi-bsw-nick 

Known issues
------------

  Here are the changes found in IGTPW_12393 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@runner@aborted:
    - fi-kbl-x1275:       NOTRUN -> [FAIL][1] ([i915#13462])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-kbl-x1275/igt@runner@aborted.html
    - bat-adlp-11:        NOTRUN -> [FAIL][2] ([i915#13462])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-adlp-11/igt@runner@aborted.html
    - fi-hsw-4770:        NOTRUN -> [FAIL][3] ([i915#13462])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-hsw-4770/igt@runner@aborted.html
    - fi-cfl-8109u:       NOTRUN -> [FAIL][4] ([i915#13462])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-cfl-8109u/igt@runner@aborted.html
    - fi-kbl-8809g:       NOTRUN -> [FAIL][5] ([i915#13462])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-kbl-8809g/igt@runner@aborted.html
    - fi-ivb-3770:        NOTRUN -> [FAIL][6] ([i915#13462])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-ivb-3770/igt@runner@aborted.html
    - bat-mtlp-8:         NOTRUN -> [FAIL][7] ([i915#13462])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-mtlp-8/igt@runner@aborted.html
    - bat-dg1-6:          NOTRUN -> [FAIL][8] ([i915#13462])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-dg1-6/igt@runner@aborted.html
    - fi-elk-e7500:       NOTRUN -> [FAIL][9] ([i915#13462])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-elk-e7500/igt@runner@aborted.html
    - bat-dg2-8:          NOTRUN -> [FAIL][10] ([i915#13462])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-dg2-8/igt@runner@aborted.html
    - fi-kbl-guc:         NOTRUN -> [FAIL][11] ([i915#13462])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-kbl-guc/igt@runner@aborted.html
    - bat-adls-6:         NOTRUN -> [FAIL][12] ([i915#13462])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-adls-6/igt@runner@aborted.html
    - fi-ilk-650:         NOTRUN -> [FAIL][13] ([i915#13462])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-ilk-650/igt@runner@aborted.html
    - bat-jsl-1:          NOTRUN -> [FAIL][14] ([i915#13462])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-jsl-1/igt@runner@aborted.html
    - fi-tgl-1115g4:      NOTRUN -> [FAIL][15] ([i915#13462])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-tgl-1115g4/igt@runner@aborted.html
    - fi-blb-e6850:       NOTRUN -> [FAIL][16] ([i915#13462])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-blb-e6850/igt@runner@aborted.html
    - bat-mtlp-6:         NOTRUN -> [FAIL][17] ([i915#13462])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-mtlp-6/igt@runner@aborted.html
    - bat-arlh-3:         NOTRUN -> [FAIL][18] ([i915#13462])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-arlh-3/igt@runner@aborted.html
    - fi-pnv-d510:        NOTRUN -> [FAIL][19] ([i915#13462])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-pnv-d510/igt@runner@aborted.html
    - bat-dg1-7:          NOTRUN -> [FAIL][20] ([i915#13462])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-dg1-7/igt@runner@aborted.html
    - bat-adlp-9:         NOTRUN -> [FAIL][21] ([i915#13462])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-adlp-9/igt@runner@aborted.html
    - bat-twl-2:          NOTRUN -> [FAIL][22] ([i915#13462])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-twl-2/igt@runner@aborted.html
    - bat-dg2-11:         NOTRUN -> [FAIL][23] ([i915#13462])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-dg2-11/igt@runner@aborted.html
    - bat-rpls-4:         NOTRUN -> [FAIL][24] ([i915#13462])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-rpls-4/igt@runner@aborted.html
    - fi-kbl-7567u:       NOTRUN -> [FAIL][25] ([i915#13462])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-kbl-7567u/igt@runner@aborted.html
    - fi-cfl-8700k:       NOTRUN -> [FAIL][26] ([i915#13462])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-cfl-8700k/igt@runner@aborted.html
    - bat-dg2-14:         NOTRUN -> [FAIL][27] ([i915#13462])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-dg2-14/igt@runner@aborted.html
    - bat-kbl-2:          NOTRUN -> [FAIL][28] ([i915#13462])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-kbl-2/igt@runner@aborted.html
    - bat-arls-5:         NOTRUN -> [FAIL][29] ([i915#13462])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-arls-5/igt@runner@aborted.html
    - bat-rplp-1:         NOTRUN -> [FAIL][30] ([i915#13462])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-rplp-1/igt@runner@aborted.html
    - bat-arlh-2:         NOTRUN -> [FAIL][31] ([i915#13462])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-arlh-2/igt@runner@aborted.html
    - fi-rkl-11600:       NOTRUN -> [FAIL][32] ([i915#13462])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-rkl-11600/igt@runner@aborted.html
    - fi-cfl-guc:         NOTRUN -> [FAIL][33] ([i915#13462])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/fi-cfl-guc/igt@runner@aborted.html
    - bat-dg2-13:         NOTRUN -> [FAIL][34] ([i915#13462])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-dg2-13/igt@runner@aborted.html
    - bat-jsl-3:          NOTRUN -> [FAIL][35] ([i915#13462])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/bat-jsl-3/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#13462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13462


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8174 -> IGTPW_12393
  * Linux: CI_DRM_15892 -> CI_DRM_15908

  CI-20190529: 20190529
  CI_DRM_15892: 08bd590935a5258ffd79355c59adffd72fb2c642 @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_15908: f06efdfad9d0e9f5cb74404ac98e1a5b3b246567 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_12393: 5ff4f2c7478a332586c48137da1a34f34ba5337d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8174: d2004b0623dbccd08502525849b4eef881aa199e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/index.html

✓ Xe.CI.BAT: success for series starting with [i-g-t,1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4704 bytes --]

== Series Details ==

Series: series starting with [i-g-t,1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started (rev2)
URL   : https://patchwork.freedesktop.org/series/143108/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8174_BAT -> XEIGTPW_12393_BAT
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with XEIGTPW_12393_BAT need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_12393_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 8)
------------------------------

  Missing    (1): bat-adlp-7 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_12393_BAT:

### IGT changes ###

#### Warnings ####

  * igt@xe_gt_freq@freq_fixed_idle:
    - bat-pvc-2:          [SKIP][1] ([Intel XE#1021]) -> [SKIP][2] +1 other test skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/bat-pvc-2/igt@xe_gt_freq@freq_fixed_idle.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/bat-pvc-2/igt@xe_gt_freq@freq_fixed_idle.html

  
Known issues
------------

  Here are the changes found in XEIGTPW_12393_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_live_ktest@xe_bo:
    - bat-pvc-2:          [PASS][3] -> [SKIP][4] ([Intel XE#1192]) +2 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/bat-pvc-2/igt@xe_live_ktest@xe_bo.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/bat-pvc-2/igt@xe_live_ktest@xe_bo.html

  * igt@xe_live_ktest@xe_dma_buf:
    - bat-bmg-2:          [PASS][5] -> [SKIP][6] ([Intel XE#1192]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/bat-bmg-2/igt@xe_live_ktest@xe_dma_buf.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/bat-bmg-2/igt@xe_live_ktest@xe_dma_buf.html

  * igt@xe_live_ktest@xe_migrate:
    - bat-bmg-1:          [PASS][7] -> [SKIP][8] ([Intel XE#1192]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/bat-bmg-1/igt@xe_live_ktest@xe_migrate.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/bat-bmg-1/igt@xe_live_ktest@xe_migrate.html
    - bat-dg2-oem2:       [PASS][9] -> [SKIP][10] ([Intel XE#1192]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/bat-dg2-oem2/igt@xe_live_ktest@xe_migrate.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/bat-dg2-oem2/igt@xe_live_ktest@xe_migrate.html
    - bat-atsm-2:         [PASS][11] -> [SKIP][12] ([Intel XE#1192]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/bat-atsm-2/igt@xe_live_ktest@xe_migrate.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/bat-atsm-2/igt@xe_live_ktest@xe_migrate.html
    - bat-adlp-vf:        [PASS][13] -> [SKIP][14] ([Intel XE#1192]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/bat-adlp-vf/igt@xe_live_ktest@xe_migrate.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/bat-adlp-vf/igt@xe_live_ktest@xe_migrate.html

  
#### Warnings ####

  * igt@xe_live_ktest@xe_bo:
    - bat-adlp-vf:        [SKIP][15] ([Intel XE#2229] / [Intel XE#455]) -> [SKIP][16] ([Intel XE#1192])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/bat-adlp-vf/igt@xe_live_ktest@xe_bo.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/bat-adlp-vf/igt@xe_live_ktest@xe_bo.html

  
  [Intel XE#1021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1021
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455


Build changes
-------------

  * IGT: IGT_8174 -> IGTPW_12393
  * Linux: xe-2424-08bd590935a5258ffd79355c59adffd72fb2c642 -> xe-2440-f06efdfad9d0e9f5cb74404ac98e1a5b3b246567

  IGTPW_12393: 5ff4f2c7478a332586c48137da1a34f34ba5337d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8174: d2004b0623dbccd08502525849b4eef881aa199e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-2424-08bd590935a5258ffd79355c59adffd72fb2c642: 08bd590935a5258ffd79355c59adffd72fb2c642
  xe-2440-f06efdfad9d0e9f5cb74404ac98e1a5b3b246567: f06efdfad9d0e9f5cb74404ac98e1a5b3b246567

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/index.html

[-- Attachment #2: Type: text/html, Size: 5827 bytes --]

RE: [PATCH i-g-t 1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started

[Cavitt, Jonathan]

-----Original Message-----
From: De Marchi, Lucas <lucas.demarchi@intel.com> 
Sent: Friday, January 3, 2025 11:16 PM
To: igt-dev@lists.freedesktop.org
Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; Cavitt, Jonathan <jonathan.cavitt@intel.com>; Gurram, Pravalika <pravalika.gurram@intel.com>
Subject: [PATCH i-g-t 1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started
> 
> If cork was not started, do not try to end it. Similar fix to commit
> 598c268686f4 ("tests/intel/xe_drm_fdinfo: Do not destroy NULL xe_cork").
> 
> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Cc: Pravalika Gurram <pravalika.gurram@intel.com>
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3869
> Fixes: 2feb1d6718a1 ("lib/xe/xe_spin: move the spinner related functions to lib")
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  tests/intel/xe_drm_fdinfo.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index e83c55c64..6549629b4 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -533,7 +533,9 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>  	read_engine_cycles(fd, pceu1);
>  	usleep(batch_duration_usec);
>  	xe_for_each_engine_class(class)
> -		xe_cork_sync_end(fd, ctx[class]);
> +		if (ctx[class])
> +			xe_cork_sync_end(fd, ctx[class]);
> +

This also needs to be applied to utilization_all_full_load.
Also: https://patchwork.freedesktop.org/series/143066/
-Jonathan Cavitt

>  	read_engine_cycles(fd, pceu2);
>  
>  	xe_for_each_engine_class(class) {
> -- 
> 2.47.0
> 
> 

✓ i915.CI.Full: success for series starting with [i-g-t,1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started (rev2)
URL   : https://patchwork.freedesktop.org/series/143108/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_15908_full -> IGTPW_12393_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/index.html

Participating hosts (12 -> 10)
------------------------------

  Missing    (2): pig-kbl-iris shard-glk-0 

Known issues
------------

  Here are the changes found in IGTPW_12393_full that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_module_load@load:
    - shard-glk:          ([PASS][1], [PASS][2], [DMESG-WARN][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#118]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk5/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk6/igt@i915_module_load@load.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk5/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk2/igt@i915_module_load@load.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk1/igt@i915_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk3/igt@i915_module_load@load.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk4/igt@i915_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk1/igt@i915_module_load@load.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk3/igt@i915_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk5/igt@i915_module_load@load.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk3/igt@i915_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk2/igt@i915_module_load@load.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk1/igt@i915_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk2/igt@i915_module_load@load.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk1/igt@i915_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk7/igt@i915_module_load@load.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk8/igt@i915_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk7/igt@i915_module_load@load.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk6/igt@i915_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk9/igt@i915_module_load@load.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk7/igt@i915_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk9/igt@i915_module_load@load.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk6/igt@i915_module_load@load.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk7/igt@i915_module_load@load.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15908/shard-glk9/igt@i915_module_load@load.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk4/igt@i915_module_load@load.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk7/igt@i915_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk2/igt@i915_module_load@load.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk7/igt@i915_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk4/igt@i915_module_load@load.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk6/igt@i915_module_load@load.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk1/igt@i915_module_load@load.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk7/igt@i915_module_load@load.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk6/igt@i915_module_load@load.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk2/igt@i915_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk6/igt@i915_module_load@load.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk3/igt@i915_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk1/igt@i915_module_load@load.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk9/igt@i915_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk8/igt@i915_module_load@load.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk5/igt@i915_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk8/igt@i915_module_load@load.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk9/igt@i915_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk3/igt@i915_module_load@load.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk5/igt@i915_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk3/igt@i915_module_load@load.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk8/igt@i915_module_load@load.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk1/igt@i915_module_load@load.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk5/igt@i915_module_load@load.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/shard-glk9/igt@i915_module_load@load.html

  
  [i915#118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/118


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8174 -> IGTPW_12393
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_15908: f06efdfad9d0e9f5cb74404ac98e1a5b3b246567 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_12393: 5ff4f2c7478a332586c48137da1a34f34ba5337d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8174: d2004b0623dbccd08502525849b4eef881aa199e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12393/index.html

Re: [PATCH i-g-t 1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started

[Lucas De Marchi]

On Mon, Jan 06, 2025 at 03:08:54PM +0000, Cavitt, Jonathan wrote:
>-----Original Message-----
>From: De Marchi, Lucas <lucas.demarchi@intel.com>
>Sent: Friday, January 3, 2025 11:16 PM
>To: igt-dev@lists.freedesktop.org
>Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; Cavitt, Jonathan <jonathan.cavitt@intel.com>; Gurram, Pravalika <pravalika.gurram@intel.com>
>Subject: [PATCH i-g-t 1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started
>>
>> If cork was not started, do not try to end it. Similar fix to commit
>> 598c268686f4 ("tests/intel/xe_drm_fdinfo: Do not destroy NULL xe_cork").
>>
>> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
>> Cc: Pravalika Gurram <pravalika.gurram@intel.com>
>> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3869
>> Fixes: 2feb1d6718a1 ("lib/xe/xe_spin: move the spinner related functions to lib")
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  tests/intel/xe_drm_fdinfo.c | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
>> index e83c55c64..6549629b4 100644
>> --- a/tests/intel/xe_drm_fdinfo.c
>> +++ b/tests/intel/xe_drm_fdinfo.c
>> @@ -533,7 +533,9 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>>  	read_engine_cycles(fd, pceu1);
>>  	usleep(batch_duration_usec);
>>  	xe_for_each_engine_class(class)
>> -		xe_cork_sync_end(fd, ctx[class]);
>> +		if (ctx[class])
>> +			xe_cork_sync_end(fd, ctx[class]);
>> +
>
>This also needs to be applied to utilization_all_full_load.
>Also: https://patchwork.freedesktop.org/series/143066/

Awesome. Reviewed and applied your more complete version.

thanks
Lucas De Marchi

>-Jonathan Cavitt
>
>>  	read_engine_cycles(fd, pceu2);
>>
>>  	xe_for_each_engine_class(class) {
>> --
>> 2.47.0
>>
>>

RE: [PATCH i-g-t 2/8] lib/xe/xe_gt: Fix header guards and boilerplate

[Cavitt, Jonathan]

-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De Marchi
Sent: Friday, January 3, 2025 11:16 PM
To: igt-dev@lists.freedesktop.org
Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
Subject: [PATCH i-g-t 2/8] lib/xe/xe_gt: Fix header guards and boilerplate
> 
> Add proper header guard and remove author from comment: authorship is
> maintained in git, not as comment.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

LGTM.
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
-Jonathan Cavitt

> ---
>  lib/xe/xe_gt.c | 3 ---
>  lib/xe/xe_gt.h | 8 +++++---
>  2 files changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/lib/xe/xe_gt.c b/lib/xe/xe_gt.c
> index 1f4b42ed9..53554beb0 100644
> --- a/lib/xe/xe_gt.c
> +++ b/lib/xe/xe_gt.c
> @@ -1,9 +1,6 @@
>  /* SPDX-License-Identifier: MIT */
>  /*
>   * Copyright (c) 2023 Intel Corporation
> - *
> - * Authors:
> - *    Janga Rahul Kumar <janga.rahul.kumar@intel.com>
>   */
>  
>  #include <fcntl.h>
> diff --git a/lib/xe/xe_gt.h b/lib/xe/xe_gt.h
> index a4bb85679..756b5f38e 100644
> --- a/lib/xe/xe_gt.h
> +++ b/lib/xe/xe_gt.h
> @@ -1,11 +1,11 @@
>  /* SPDX-License-Identifier: MIT */
>  /*
>   * Copyright (c) 2023 Intel Corporation
> - *
> - * Authors:
> - *    Janga Rahul Kumar <janga.rahul.kumar@intel.com>
>   */
>  
> +#ifndef XE_GT_H
> +#define XE_GT_H
> +
>  #include "lib/igt_gt.h"
>  
>  bool has_xe_gt_reset(int fd);
> @@ -14,3 +14,5 @@ igt_hang_t xe_hang_ring(int fd, uint64_t ahnd, uint32_t ctx, int ring,
>  				unsigned int flags);
>  void xe_post_hang_ring(int fd, igt_hang_t arg);
>  int xe_gt_stats_get_count(int fd, int gt, const char *stat);
> +
> +#endif
> -- 
> 2.47.0
> 
> 

RE: [PATCH i-g-t 3/8] lib/xe: Move functions from xe_util to xe_gt

[Cavitt, Jonathan]

-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De Marchi
Sent: Friday, January 3, 2025 11:16 PM
To: igt-dev@lists.freedesktop.org
Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
Subject: [PATCH i-g-t 3/8] lib/xe: Move functions from xe_util to xe_gt
> 
> Some functions are clearly gt-related, so move them to xe_gt.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

LGTM, though at some point in the future, we should probably take a closer look at
the test files that have been impacted by this change and check if xe_util.h is still a
required includes for them.
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
-Jonathan Cavitt

> ---
>  lib/xe/xe_gt.c                 | 67 ++++++++++++++++++++++++++++++++++
>  lib/xe/xe_gt.h                 |  8 ++++
>  lib/xe/xe_util.c               | 67 ----------------------------------
>  lib/xe/xe_util.h               |  7 ----
>  tests/intel/xe_drm_fdinfo.c    |  2 +
>  tests/intel/xe_exec_balancer.c |  1 +
>  tests/intel/xe_exec_reset.c    |  1 +
>  tests/intel/xe_exec_threads.c  |  1 +
>  tests/intel/xe_gt_freq.c       |  1 +
>  tests/intel/xe_pm_residency.c  |  2 +
>  10 files changed, 83 insertions(+), 74 deletions(-)
> 
> diff --git a/lib/xe/xe_gt.c b/lib/xe/xe_gt.c
> index 53554beb0..e1f353b41 100644
> --- a/lib/xe/xe_gt.c
> +++ b/lib/xe/xe_gt.c
> @@ -174,3 +174,70 @@ int xe_gt_stats_get_count(int fd, int gt, const char *stat)
>  
>  	return count;
>  }
> +
> +/**
> + * xe_is_gt_in_c6:
> + * @fd: pointer to xe drm fd
> + * @gt: gt number
> + *
> + * Check if GT is in C6 state
> + */
> +bool xe_is_gt_in_c6(int fd, int gt)
> +{
> +	char gt_c_state[16];
> +	int gt_fd;
> +
> +	gt_fd = xe_sysfs_gt_open(fd, gt);
> +	igt_assert(gt_fd >= 0);
> +	igt_assert(igt_sysfs_scanf(gt_fd, "gtidle/idle_status", "%s", gt_c_state) == 1);
> +	close(gt_fd);
> +
> +	return strcmp(gt_c_state, "gt-c6") == 0;
> +}
> +
> +/**
> + * xe_gt_fill_engines_by_class:
> + * @fd: pointer to xe drm fd
> + * @gt: gt number
> + * @class: engine class to use to filter engines
> + * @eci: output argument to copy engines to
> + *
> + * Fill out @drm_xe_engine_class_instance with all the engines in @gt that have
> + * a certain @class.
> + *
> + * Return: number of engines that match the gt and clas
> + */
> +int xe_gt_fill_engines_by_class(int fd, int gt, int class,
> +				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE])
> +{
> +	struct drm_xe_engine_class_instance *hwe;
> +	int n = 0;
> +
> +	xe_for_each_engine(fd, hwe)
> +		if (hwe->engine_class == class && hwe->gt_id == gt)
> +			eci[n++] = *hwe;
> +
> +	return n;
> +}
> +
> +/**
> + * xe_gt_count_engines_by_class:
> + * @fd: pointer to xe drm fd
> + * @gt: gt number
> + * @class: engine class to use to filter engines
> + *
> + * Count number of engines in @gt that have a certain @class.
> + *
> + * Return: number of engines that match the gt and clas
> + */
> +int xe_gt_count_engines_by_class(int fd, int gt, int class)
> +{
> +	struct drm_xe_engine_class_instance *hwe;
> +	int n = 0;
> +
> +	xe_for_each_engine(fd, hwe)
> +		if (hwe->engine_class == class && hwe->gt_id == gt)
> +			n++;
> +
> +	return n;
> +}
> diff --git a/lib/xe/xe_gt.h b/lib/xe/xe_gt.h
> index 756b5f38e..47569cec3 100644
> --- a/lib/xe/xe_gt.h
> +++ b/lib/xe/xe_gt.h
> @@ -8,6 +8,8 @@
>  
>  #include "lib/igt_gt.h"
>  
> +#include "xe_query.h"
> +
>  bool has_xe_gt_reset(int fd);
>  void xe_force_gt_reset_all(int fd);
>  igt_hang_t xe_hang_ring(int fd, uint64_t ahnd, uint32_t ctx, int ring,
> @@ -15,4 +17,10 @@ igt_hang_t xe_hang_ring(int fd, uint64_t ahnd, uint32_t ctx, int ring,
>  void xe_post_hang_ring(int fd, igt_hang_t arg);
>  int xe_gt_stats_get_count(int fd, int gt, const char *stat);
>  
> +bool xe_is_gt_in_c6(int fd, int gt);
> +
> +int xe_gt_fill_engines_by_class(int fd, int gt, int class,
> +				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE]);
> +int xe_gt_count_engines_by_class(int fd, int gt, int class);
> +
>  #endif
> diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
> index 9482819c2..f0b6bbb2d 100644
> --- a/lib/xe/xe_util.c
> +++ b/lib/xe/xe_util.c
> @@ -235,70 +235,3 @@ void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine,
>  
>  	free(bind_ops);
>  }
> -
> -/**
> - * xe_is_gt_in_c6:
> - * @fd: pointer to xe drm fd
> - * @gt: gt number
> - *
> - * Check if GT is in C6 state
> - */
> -bool xe_is_gt_in_c6(int fd, int gt)
> -{
> -	char gt_c_state[16];
> -	int gt_fd;
> -
> -	gt_fd = xe_sysfs_gt_open(fd, gt);
> -	igt_assert(gt_fd >= 0);
> -	igt_assert(igt_sysfs_scanf(gt_fd, "gtidle/idle_status", "%s", gt_c_state) == 1);
> -	close(gt_fd);
> -
> -	return strcmp(gt_c_state, "gt-c6") == 0;
> -}
> -
> -/**
> - * xe_gt_fill_engines_by_class:
> - * @fd: pointer to xe drm fd
> - * @gt: gt number
> - * @class: engine class to use to filter engines
> - * @eci: output argument to copy engines to
> - *
> - * Fill out @drm_xe_engine_class_instance with all the engines in @gt that have
> - * a certain @class.
> - *
> - * Return: number of engines that match the gt and clas
> - */
> -int xe_gt_fill_engines_by_class(int fd, int gt, int class,
> -				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE])
> -{
> -	struct drm_xe_engine_class_instance *hwe;
> -	int n = 0;
> -
> -	xe_for_each_engine(fd, hwe)
> -		if (hwe->engine_class == class && hwe->gt_id == gt)
> -			eci[n++] = *hwe;
> -
> -	return n;
> -}
> -
> -/**
> - * xe_gt_count_engines_by_class:
> - * @fd: pointer to xe drm fd
> - * @gt: gt number
> - * @class: engine class to use to filter engines
> - *
> - * Count number of engines in @gt that have a certain @class.
> - *
> - * Return: number of engines that match the gt and clas
> - */
> -int xe_gt_count_engines_by_class(int fd, int gt, int class)
> -{
> -	struct drm_xe_engine_class_instance *hwe;
> -	int n = 0;
> -
> -	xe_for_each_engine(fd, hwe)
> -		if (hwe->engine_class == class && hwe->gt_id == gt)
> -			n++;
> -
> -	return n;
> -}
> diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
> index b9fbfc5cd..c544d912f 100644
> --- a/lib/xe/xe_util.h
> +++ b/lib/xe/xe_util.h
> @@ -47,11 +47,4 @@ void xe_bind_unbind_async(int fd, uint32_t vm, uint32_t bind_engine,
>  			  struct igt_list_head *obj_list,
>  			  uint32_t sync_in, uint32_t sync_out);
>  
> -bool xe_is_gt_in_c6(int fd, int gt);
> -
> -int xe_gt_fill_engines_by_class(int fd, int gt, int class,
> -				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE]);
> -int xe_gt_count_engines_by_class(int fd, int gt, int class);
> -
> -
>  #endif /* XE_UTIL_H */
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 6549629b4..f4264aadb 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -8,7 +8,9 @@
>  #include "igt_device.h"
>  #include "igt_drm_fdinfo.h"
>  #include "lib/igt_syncobj.h"
> +
>  #include "xe_drm.h"
> +#include "xe/xe_gt.h"
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_spin.h"
> diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c
> index 1e552e9ef..f2df5cbec 100644
> --- a/tests/intel/xe_exec_balancer.c
> +++ b/tests/intel/xe_exec_balancer.c
> @@ -19,6 +19,7 @@
>  #include "lib/intel_reg.h"
>  #include "xe_drm.h"
>  
> +#include "xe/xe_gt.h"
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_spin.h"
> diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
> index a3eaf8bbf..47c7666df 100644
> --- a/tests/intel/xe_exec_reset.c
> +++ b/tests/intel/xe_exec_reset.c
> @@ -21,6 +21,7 @@
>  
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
> +#include "xe/xe_gt.h"
>  #include "xe/xe_spin.h"
>  #include "xe/xe_util.h"
>  #include <string.h>
> diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c
> index 661117bed..c8fc17366 100644
> --- a/tests/intel/xe_exec_threads.c
> +++ b/tests/intel/xe_exec_threads.c
> @@ -21,6 +21,7 @@
>  
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
> +#include "xe/xe_gt.h"
>  #include "xe/xe_spin.h"
>  #include "xe/xe_util.h"
>  #include <string.h>
> diff --git a/tests/intel/xe_gt_freq.c b/tests/intel/xe_gt_freq.c
> index de4d111ea..5d806cf15 100644
> --- a/tests/intel/xe_gt_freq.c
> +++ b/tests/intel/xe_gt_freq.c
> @@ -17,6 +17,7 @@
>  #include "igt_sysfs.h"
>  
>  #include "xe_drm.h"
> +#include "xe/xe_gt.h"
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_spin.h"
>  #include "xe/xe_query.h"
> diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
> index d4b26b231..18e5cb6c3 100644
> --- a/tests/intel/xe_pm_residency.c
> +++ b/tests/intel/xe_pm_residency.c
> @@ -21,7 +21,9 @@
>  #include "igt_sysfs.h"
>  
>  #include "lib/igt_syncobj.h"
> +
>  #include "xe/xe_ioctl.h"
> +#include "xe/xe_gt.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_util.h"
>  
> -- 
> 2.47.0
> 
> 

RE: [PATCH i-g-t 4/8] lib/xe: Rename xe_is_gt_in_c6()

[Cavitt, Jonathan]

-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De Marchi
Sent: Friday, January 3, 2025 11:16 PM
To: igt-dev@lists.freedesktop.org
Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
Subject: [PATCH i-g-t 4/8] lib/xe: Rename xe_is_gt_in_c6()
> 
> Use xe_gt_ as namespace.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

LGTM.
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
-Jonathan Cavitt

> ---
>  lib/xe/xe_gt.c                |  4 ++--
>  lib/xe/xe_gt.h                |  2 +-
>  tests/intel/xe_gt_freq.c      | 12 ++++++------
>  tests/intel/xe_pm_residency.c |  8 ++++----
>  4 files changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/lib/xe/xe_gt.c b/lib/xe/xe_gt.c
> index e1f353b41..6f1475be0 100644
> --- a/lib/xe/xe_gt.c
> +++ b/lib/xe/xe_gt.c
> @@ -176,13 +176,13 @@ int xe_gt_stats_get_count(int fd, int gt, const char *stat)
>  }
>  
>  /**
> - * xe_is_gt_in_c6:
> + * xe_gt_is_in_c6:
>   * @fd: pointer to xe drm fd
>   * @gt: gt number
>   *
>   * Check if GT is in C6 state
>   */
> -bool xe_is_gt_in_c6(int fd, int gt)
> +bool xe_gt_is_in_c6(int fd, int gt)
>  {
>  	char gt_c_state[16];
>  	int gt_fd;
> diff --git a/lib/xe/xe_gt.h b/lib/xe/xe_gt.h
> index 47569cec3..511b31149 100644
> --- a/lib/xe/xe_gt.h
> +++ b/lib/xe/xe_gt.h
> @@ -17,7 +17,7 @@ igt_hang_t xe_hang_ring(int fd, uint64_t ahnd, uint32_t ctx, int ring,
>  void xe_post_hang_ring(int fd, igt_hang_t arg);
>  int xe_gt_stats_get_count(int fd, int gt, const char *stat);
>  
> -bool xe_is_gt_in_c6(int fd, int gt);
> +bool xe_gt_is_in_c6(int fd, int gt);
>  
>  int xe_gt_fill_engines_by_class(int fd, int gt, int class,
>  				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE]);
> diff --git a/tests/intel/xe_gt_freq.c b/tests/intel/xe_gt_freq.c
> index 5d806cf15..2ece2e6f4 100644
> --- a/tests/intel/xe_gt_freq.c
> +++ b/tests/intel/xe_gt_freq.c
> @@ -200,7 +200,7 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle)
>  
>  	if (gt_idle) {
>  		/* Wait for GT to go in C6 as previous get_freq wakes up GT*/
> -		igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10),
> +		igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt_id), 1000, 10),
>  			     "GT %d should be in C6\n", gt_id);
>  		igt_assert(get_freq(fd, gt_id, "act") == 0);
>  	} else {
> @@ -215,7 +215,7 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle)
>  	igt_assert_lte_u32((rpmid - FREQ_UNIT_MHZ), cur_freq);
>  
>  	if (gt_idle) {
> -		igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10),
> +		igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt_id), 1000, 10),
>  			     "GT %d should be in C6\n", gt_id);
>  		igt_assert(get_freq(fd, gt_id, "act") == 0);
>  	} else {
> @@ -234,7 +234,7 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle)
>  	igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rp0);
>  
>  	if (gt_idle) {
> -		igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10),
> +		igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt_id), 1000, 10),
>  			     "GT %d should be in C6\n", gt_id);
>  		igt_assert(get_freq(fd, gt_id, "act") == 0);
>  	}
> @@ -265,7 +265,7 @@ static void test_freq_range(int fd, int gt_id, bool gt_idle)
>  	igt_assert(rpn <= cur && cur <= rpmid + FREQ_UNIT_MHZ);
>  
>  	if (gt_idle) {
> -		igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10),
> +		igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt_id), 1000, 10),
>  			     "GT %d should be in C6\n", gt_id);
>  		igt_assert(get_freq(fd, gt_id, "act") == 0);
>  	} else {
> @@ -466,7 +466,7 @@ igt_main
>  
>  	igt_subtest("freq_fixed_idle") {
>  		xe_for_each_gt(fd, gt) {
> -			igt_require_f(igt_wait(xe_is_gt_in_c6(fd, gt), 1000, 10),
> +			igt_require_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 10),
>  				      "GT %d should be in C6\n", gt);
>  			test_freq_fixed(fd, gt, true);
>  		}
> @@ -484,7 +484,7 @@ igt_main
>  
>  	igt_subtest("freq_range_idle") {
>  		xe_for_each_gt(fd, gt) {
> -			igt_require_f(igt_wait(xe_is_gt_in_c6(fd, gt), 1000, 10),
> +			igt_require_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 10),
>  				      "GT %d should be in C6\n", gt);
>  			test_freq_range(fd, gt, true);
>  		}
> diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
> index 18e5cb6c3..0b48a1c79 100644
> --- a/tests/intel/xe_pm_residency.c
> +++ b/tests/intel/xe_pm_residency.c
> @@ -210,7 +210,7 @@ static void test_idle_residency(int fd, int gt, enum test_type flag)
>  {
>  	unsigned long elapsed_ms, residency_start, residency_end;
>  
> -	igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt), 1000, 1), "GT %d not in C6\n", gt);
> +	igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 1), "GT %d not in C6\n", gt);
>  
>  	if (flag == TEST_S2IDLE) {
>  		/*
> @@ -300,7 +300,7 @@ static void toggle_gt_c6(int fd, int n)
>  		igt_assert_lte(0, fw_handle);
>  		/* check if all gts are in C0 after forcewake is acquired */
>  		xe_for_each_gt(fd, gt)
> -			igt_assert_f(!xe_is_gt_in_c6(fd, gt),
> +			igt_assert_f(!xe_gt_is_in_c6(fd, gt),
>  				     "Forcewake acquired, GT %d should be in C0\n", gt);
>  
>  		if (n == NUM_REPS)
> @@ -309,7 +309,7 @@ static void toggle_gt_c6(int fd, int n)
>  		close(fw_handle);
>  		/* check if all gts are in C6 after forcewake is released */
>  		xe_for_each_gt(fd, gt)
> -			igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt), 1000, 1),
> +			igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 1),
>  				     "Forcewake released, GT %d should be in C6\n", gt);
>  
>  		if (n == NUM_REPS)
> @@ -406,7 +406,7 @@ igt_main
>  	igt_subtest_with_dynamic("gt-c6-on-idle") {
>  		xe_for_each_gt(fd, gt)
>  			igt_dynamic_f("gt%u", gt)
> -				igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt), 1000, 1),
> +				igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 1),
>  					     "GT %d not in C6\n", gt);
>  	}
>  
> -- 
> 2.47.0
> 
> 

RE: [PATCH i-g-t 5/8] lib/xe: Split nsec to ticks abstraction

[Cavitt, Jonathan]

-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De Marchi
Sent: Friday, January 3, 2025 11:16 PM
To: igt-dev@lists.freedesktop.org
Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
Subject: [PATCH i-g-t 5/8] lib/xe: Split nsec to ticks abstraction
> 
> There are 2 things happening here: one is converting time in nanoseconds
> to ticks by using the refclock, and another asserting a spin duration is
> not so close to the maximum duration since there needs to be room for
> context switch.
> 
> Move the time conversion to xe_util.c and adjust it to maintain
> namespace and have better names.  Places that do the time conversion to
> pass to xe_spin then use the xe_spin_nsec_to_ticks() wrapper to
> calculate the ticks.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

I only have a single minor nit below, but otherwise:
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>

> ---
>  benchmarks/gem_wsim.c           |  8 +++---
>  lib/xe/xe_spin.c                | 47 +++++++++------------------------
>  lib/xe/xe_spin.h                |  9 +++----
>  lib/xe/xe_util.c                | 40 ++++++++++++++++++++++++++++
>  lib/xe/xe_util.h                |  2 ++
>  tests/intel/xe_exec_mix_modes.c |  3 ++-
>  tests/intel/xe_spin_batch.c     |  2 +-
>  7 files changed, 66 insertions(+), 45 deletions(-)
> 
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index c4fd00a6a..454b6f017 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -1797,8 +1797,8 @@ xe_alloc_step_batch(struct workload *wrk, struct w_step *w)
>  	xe_vm_bind_sync(fd, vm->id, w->bb_handle, 0, w->xe.exec.address, w->bb_size);
>  	xe_spin_init_opts(&w->xe.data->spin, .addr = w->xe.exec.address,
>  				   .preempt = (w->preempt_us > 0),
> -				   .ctx_ticks = duration_to_ctx_ticks(fd, eq->hwe_list[0].gt_id,
> -								1000LL * get_duration(wrk, w)));
> +				   .ctx_ticks = xe_spin_nsec_to_ticks(fd, eq->hwe_list[0].gt_id,
> +								      1000LL * get_duration(wrk, w)));
>  	w->xe.exec.exec_queue_id = eq->id;
>  	w->xe.exec.num_batch_buffer = 1;
>  	/* always at least one out fence */
> @@ -2655,8 +2655,8 @@ static void do_xe_exec(struct workload *wrk, struct w_step *w)
>  		xe_spin_init_opts(&w->xe.data->spin,
>  				  .addr = w->xe.exec.address,
>  				  .preempt = (w->preempt_us > 0),
> -				  .ctx_ticks = duration_to_ctx_ticks(fd, eq->hwe_list[0].gt_id,
> -								1000LL * get_duration(wrk, w)));
> +				  .ctx_ticks = xe_spin_nsec_to_ticks(fd, eq->hwe_list[0].gt_id,
> +								     1000LL * get_duration(wrk, w)));
>  	xe_exec(fd, &w->xe.exec);
>  }
>  
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 2bde55856..333f8d7d8 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -13,43 +13,12 @@
>  #include "igt_core.h"
>  #include "igt_syncobj.h"
>  #include "intel_reg.h"
> +
>  #include "xe_ioctl.h"
>  #include "xe_spin.h"
> +#include "xe_util.h"
>  
> -static uint32_t read_timestamp_frequency(int fd, int gt_id)
> -{
> -	struct xe_device *dev = xe_device_get(fd);
> -
> -	igt_assert(dev && dev->gt_list && dev->gt_list->num_gt);
> -	igt_assert(gt_id >= 0 && gt_id <= dev->gt_list->num_gt);
> -
> -	return dev->gt_list->gt_list[gt_id].reference_clock;
> -}
> -
> -static uint64_t div64_u64_round_up(const uint64_t x, const uint64_t y)
> -{
> -	igt_assert(y > 0);
> -	igt_assert_lte_u64(x, UINT64_MAX - (y - 1));
> -
> -	return (x + y - 1) / y;
> -}
> -
> -/**
> - * duration_to_ctx_ticks:
> - * @fd: opened device
> - * @gt_id: tile id
> - * @duration_ns: duration in nanoseconds to be converted to context timestamp ticks
> - * @return: duration converted to context timestamp ticks.
> - */
> -uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t duration_ns)
> -{
> -	uint32_t f = read_timestamp_frequency(fd, gt_id);
> -	uint64_t ctx_ticks = div64_u64_round_up(duration_ns * f, NSEC_PER_SEC);
> -
> -	igt_assert_lt_u64(ctx_ticks, XE_SPIN_MAX_CTX_TICKS);
> -
> -	return ctx_ticks;
> -}
> +#define XE_SPIN_MAX_CTX_TICKS (UINT32_MAX - 1000)
>  
>  #define MI_SRM_CS_MMIO				(1 << 19)
>  #define MI_LRI_CS_MMIO				(1 << 19)
> @@ -60,6 +29,16 @@ uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t duration_ns)
>  
>  enum { START_TS, NOW_TS };
>  
> +
> +uint32_t xe_spin_nsec_to_ticks(int fd, int gt_id, uint64_t nsec)
> +{
> +	uint32_t ticks = xe_nsec_to_ticks(fd, gt_id, nsec);
> +
> +	igt_assert_lt_u64(ticks, XE_SPIN_MAX_CTX_TICKS);
> +
> +	return ticks;
> +}
> +
>  /**
>   * xe_spin_init:
>   * @spin: pointer to mapped bo in which spinner code will be written
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index 593065bc0..01f45eaeb 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -15,10 +15,8 @@
>  #include "xe_query.h"
>  #include "lib/igt_dummyload.h"
>  
> -#define XE_SPIN_MAX_CTX_TICKS (UINT32_MAX - 1000)
> -
> -/** struct xe_spin_opts
> - *
> +/**
> + * struct xe_spin_opts

Nit:
This change (correcting the comment style for the xe_spin_opts declaration)
might be better suited for the next patch in this series, as we're already cleaning
up the other abstractions in the xe_spin.h file at that time.  But either way
works for me.
-Jonathan Cavitt

>   * @addr: offset of spinner within vm
>   * @preempt: allow spinner to be preempted or not
>   * @ctx_ticks: number of ticks after which spinner is stopped, applied if > 0
> @@ -68,7 +66,6 @@ struct xe_cork {
>  };
>  
>  igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
> -uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
>  void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
>  struct xe_cork *
>  xe_cork_create(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> @@ -82,6 +79,8 @@ void xe_cork_destroy(int fd, struct xe_cork *ctx);
>  #define xe_spin_init_opts(fd, ...) \
>  	xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
>  
> +uint32_t xe_spin_nsec_to_ticks(int fd, int gt_id, uint64_t nsec);
> +
>  bool xe_spin_started(struct xe_spin *spin);
>  void xe_spin_sync_wait(int fd, struct igt_spin *spin);
>  void xe_spin_wait_started(struct xe_spin *spin);
> diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
> index f0b6bbb2d..06b378ce0 100644
> --- a/lib/xe/xe_util.c
> +++ b/lib/xe/xe_util.c
> @@ -4,9 +4,11 @@
>   */
>  
>  #include "igt.h"
> +#include "igt_core.h"
>  #include "igt_syncobj.h"
>  #include "igt_sysfs.h"
>  #include "intel_pat.h"
> +
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_util.h"
> @@ -235,3 +237,41 @@ void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine,
>  
>  	free(bind_ops);
>  }
> +
> +static uint32_t reference_clock(int fd, int gt_id)
> +{
> +	struct xe_device *dev = xe_device_get(fd);
> +	uint32_t refclock;
> +
> +	igt_assert(dev && dev->gt_list && dev->gt_list->num_gt);
> +	igt_assert(gt_id >= 0 && gt_id <= dev->gt_list->num_gt);
> +
> +	refclock = dev->gt_list->gt_list[gt_id].reference_clock;
> +
> +	igt_assert_lt(0, refclock);
> +
> +	return refclock;
> +}
> +
> +static uint64_t div64_u64_round_up(const uint64_t x, const uint64_t y)
> +{
> +	igt_assert(y > 0);
> +	igt_assert_lte_u64(x, UINT64_MAX - (y - 1));
> +
> +	return (x + y - 1) / y;
> +}
> +
> +/**
> + * xe_nsec_to_ticks: convert time in nanoseconds to timestamp ticks
> + * @fd: opened device
> + * @gt_id: tile id
> + * @nsec: time in nanoseconds
> + *
> + * Return: Time converted to context timestamp ticks.
> + */
> +uint32_t xe_nsec_to_ticks(int fd, int gt_id, uint64_t nsec)
> +{
> +	uint32_t refclock = reference_clock(fd, gt_id);
> +
> +	return div64_u64_round_up(nsec * refclock, NSEC_PER_SEC);
> +}
> diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
> index c544d912f..06ebd3c2a 100644
> --- a/lib/xe/xe_util.h
> +++ b/lib/xe/xe_util.h
> @@ -47,4 +47,6 @@ void xe_bind_unbind_async(int fd, uint32_t vm, uint32_t bind_engine,
>  			  struct igt_list_head *obj_list,
>  			  uint32_t sync_in, uint32_t sync_out);
>  
> +uint32_t xe_nsec_to_ticks(int fd, int gt_id, uint64_t ns);
> +
>  #endif /* XE_UTIL_H */
> diff --git a/tests/intel/xe_exec_mix_modes.c b/tests/intel/xe_exec_mix_modes.c
> index eeae9d122..0bcd49cc0 100644
> --- a/tests/intel/xe_exec_mix_modes.c
> +++ b/tests/intel/xe_exec_mix_modes.c
> @@ -22,6 +22,7 @@
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_spin.h"
> +#include "xe/xe_util.h"
>  #include <string.h>
>  
>  #define FLAG_EXEC_MODE_LR	(0x1 << 0)
> @@ -132,7 +133,7 @@ run_job(int fd, struct drm_xe_engine_class_instance *hwe,
>  
>  	if (job_type == SPINNER_INTERRUPTED) {
>  		spin_opts.addr = addr + (char *)&data[SPIN_DATA].spin - (char *)data;
> -		spin_opts.ctx_ticks = duration_to_ctx_ticks(fd, 0, duration_ns);
> +		spin_opts.ctx_ticks = xe_spin_nsec_to_ticks(fd, 0, duration_ns);
>  		xe_spin_init(&data[SPIN_DATA].spin, &spin_opts);
>  		if (engine_execution_mode == EXEC_MODE_LR)
>  			sync[0].addr = addr + (char *)&data[SPIN_DATA].exec_sync - (char *)data;
> diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
> index 0ad2490a0..5d9afaf3d 100644
> --- a/tests/intel/xe_spin_batch.c
> +++ b/tests/intel/xe_spin_batch.c
> @@ -277,7 +277,7 @@ static void xe_spin_fixed_duration(int fd, int gt, int class, int flags)
>  	xe_vm_bind_sync(fd, vm, bo, 0, spin_addr, bo_size);
>  	xe_spin_init_opts(spin, .addr = spin_addr,
>  				.preempt = true,
> -				.ctx_ticks = duration_to_ctx_ticks(fd, 0, duration_ns));
> +				.ctx_ticks = xe_spin_nsec_to_ticks(fd, 0, duration_ns));
>  	exec.address = spin_addr;
>  	exec.exec_queue_id = exec_queue;
>  
> -- 
> 2.47.0
> 
> 

RE: [PATCH i-g-t 6/8] lib/xe/xe_spin: Move declarations around

[Cavitt, Jonathan]

-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De Marchi
Sent: Friday, January 3, 2025 11:16 PM
To: igt-dev@lists.freedesktop.org
Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
Subject: [PATCH i-g-t 6/8] lib/xe/xe_spin: Move declarations around
> 
> xe_spin.h has 3 abstractions:
> 
> 1) the integration with igt_dummyload
> 2) xe_spin, the bo to be exec'ed somewhere
> 3) xe_cork, that resembles more the igt_spin, abstracting the fd, vm,
>    bind, etc
> 
> Group them so it's easier to understand each one.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Okay, I think I get it.  We're bundling the various functions declared in xe_spin.h
by their purpose/interaction with the various structures, yeah?  That makes sense
to me.
And even if my understanding of the purpose of this patch is wrong, I don't see
any harm in applying it, so:
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
-Jonathan Cavitt

> ---
>  lib/xe/xe_spin.c |  2 +-
>  lib/xe/xe_spin.h | 54 +++++++++++++++++++++++++++---------------------
>  2 files changed, 32 insertions(+), 24 deletions(-)
> 
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 333f8d7d8..bb6318cef 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -232,7 +232,7 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt)
>  	return spin;
>  }
>  
> -void xe_spin_sync_wait(int fd, struct igt_spin *spin)
> +static void xe_spin_sync_wait(int fd, struct igt_spin *spin)
>  {
>  	igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0, NULL));
>  }
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index 01f45eaeb..7c95996c3 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -15,6 +15,15 @@
>  #include "xe_query.h"
>  #include "lib/igt_dummyload.h"
>  
> +/* Wrapper to integrate with igt_dummyload, aka igt_spin */
> +igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
> +void xe_spin_free(int fd, struct igt_spin *spin);
> +
> +/*
> + * xe_spin: abstract a bo mapped in the GPU that when exec'ed will spin the
> + * engine in which it's exec'ed
> + */
> +
>  /**
>   * struct xe_spin_opts
>   * @addr: offset of spinner within vm
> @@ -30,11 +39,6 @@ struct xe_spin_opts {
>  	bool write_timestamp;
>  };
>  
> -struct xe_cork_opts {
> -	uint64_t ahnd;
> -	bool debug;
> -};
> -
>  /* Mapped GPU object */
>  struct xe_spin {
>  	uint32_t batch[128];
> @@ -46,6 +50,24 @@ struct xe_spin {
>  	uint32_t timestamp;
>  };
>  
> +uint32_t xe_spin_nsec_to_ticks(int fd, int gt_id, uint64_t nsec);
> +void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
> +#define xe_spin_init_opts(fd, ...) \
> +	xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
> +bool xe_spin_started(struct xe_spin *spin);
> +void xe_spin_wait_started(struct xe_spin *spin);
> +void xe_spin_end(struct xe_spin *spin);
> +
> +/*
> + * xe_cork: higher level API that simplifies exec'ing an xe_spin by taking care
> + * of vm creation, exec call, etc.
> + */
> +
> +struct xe_cork_opts {
> +	uint64_t ahnd;
> +	bool debug;
> +};
> +
>  struct xe_cork {
>  	struct xe_spin *spin;
>  	int fd;
> @@ -65,27 +87,13 @@ struct xe_cork {
>  	uint16_t num_placements;
>  };
>  
> -igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
> -void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
> -struct xe_cork *
> -xe_cork_create(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> -	      uint16_t width, uint16_t num_placements, struct xe_cork_opts *opts);
> -void xe_cork_destroy(int fd, struct xe_cork *ctx);
> -
> +struct xe_cork *xe_cork_create(int fd, struct drm_xe_engine_class_instance *hwe,
> +			       uint32_t vm, uint16_t width, uint16_t num_placements,
> +			       struct xe_cork_opts *opts);
>  #define xe_cork_create_opts(fd, hwe, vm, width, num_placements, ...) \
>  	xe_cork_create(fd, hwe, vm, width, num_placements, \
>  			&((struct xe_cork_opts){__VA_ARGS__}))
> -
> -#define xe_spin_init_opts(fd, ...) \
> -	xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
> -
> -uint32_t xe_spin_nsec_to_ticks(int fd, int gt_id, uint64_t nsec);
> -
> -bool xe_spin_started(struct xe_spin *spin);
> -void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> -void xe_spin_wait_started(struct xe_spin *spin);
> -void xe_spin_end(struct xe_spin *spin);
> -void xe_spin_free(int fd, struct igt_spin *spin);
> +void xe_cork_destroy(int fd, struct xe_cork *ctx);
>  void xe_cork_sync_start(int fd, struct xe_cork *ctx);
>  void xe_cork_sync_end(int fd, struct xe_cork *ctx);
>  
> -- 
> 2.47.0
> 
> 

RE: [PATCH i-g-t 7/8] treewide: s/ctx/cork/ when referring to xe_cork

[Cavitt, Jonathan]

-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De Marchi
Sent: Friday, January 3, 2025 11:16 PM
To: igt-dev@lists.freedesktop.org
Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
Subject: [PATCH i-g-t 7/8] treewide: s/ctx/cork/ when referring to xe_cork
> 
> Commit 2feb1d6718a1 ("lib/xe/xe_spin: move the spinner related functions
> to lib") extracted the spin_ctx abstraction from xe_drm_fdinfo to be
> re-used in other places as part of the xe_cork. Complement it by also
> renaming the variable s/ctx/cork/ when referring to struct xe_cork.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

LGTM.

Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>

By the way, this RB also applies to the inevitable rebase that this will
require after commit c982ba23a3 ("tests/intel/xe_drm_fdinfo: Do not end NULL xe_cork")
landed.

-Jonathan Cavitt

> ---
>  lib/xe/xe_spin.c            | 158 ++++++++++++++++++------------------
>  tests/intel/xe_drm_fdinfo.c |  74 ++++++++---------
>  tests/intel/xe_spin_batch.c |  14 ++--
>  tests/intel/xe_vm.c         |  12 +--
>  4 files changed, 129 insertions(+), 129 deletions(-)
> 
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index bb6318cef..0de0b1f2e 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -291,148 +291,148 @@ xe_cork_create(int fd, struct drm_xe_engine_class_instance *hwe,
>  		uint32_t vm, uint16_t width, uint16_t num_placements,
>  		struct xe_cork_opts *opts)
>  {
> -	struct xe_cork *ctx = calloc(1, sizeof(*ctx));
> +	struct xe_cork *cork = calloc(1, sizeof(*cork));
>  
> -	igt_assert(ctx);
> +	igt_assert(cork);
>  	igt_assert(width && num_placements &&
>  		   (width == 1 || num_placements == 1));
>  	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
>  
> -	ctx->class = hwe->engine_class;
> -	ctx->width = width;
> -	ctx->num_placements = num_placements;
> -	ctx->vm = vm;
> -	ctx->cork_opts = *opts;
> -
> -	ctx->exec.num_batch_buffer = width;
> -	ctx->exec.num_syncs = 2;
> -	ctx->exec.syncs = to_user_pointer(ctx->sync);
> -
> -	ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> -	ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> -	ctx->sync[0].handle = syncobj_create(fd, 0);
> -
> -	ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> -	ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> -	ctx->sync[1].handle = syncobj_create(fd, 0);
> -
> -	ctx->bo_size = sizeof(struct xe_spin);
> -	ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> -	ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> -			       vram_if_possible(fd, hwe->gt_id),
> -			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> -	if (ctx->cork_opts.ahnd) {
> +	cork->class = hwe->engine_class;
> +	cork->width = width;
> +	cork->num_placements = num_placements;
> +	cork->vm = vm;
> +	cork->cork_opts = *opts;
> +
> +	cork->exec.num_batch_buffer = width;
> +	cork->exec.num_syncs = 2;
> +	cork->exec.syncs = to_user_pointer(cork->sync);
> +
> +	cork->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> +	cork->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> +	cork->sync[0].handle = syncobj_create(fd, 0);
> +
> +	cork->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> +	cork->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> +	cork->sync[1].handle = syncobj_create(fd, 0);
> +
> +	cork->bo_size = sizeof(struct xe_spin);
> +	cork->bo_size = xe_bb_size(fd, cork->bo_size);
> +	cork->bo = xe_bo_create(fd, cork->vm, cork->bo_size,
> +				vram_if_possible(fd, hwe->gt_id),
> +				DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +	if (cork->cork_opts.ahnd) {
>  		for (unsigned int i = 0; i < width; i++)
> -			ctx->addr[i] = intel_allocator_alloc_with_strategy(ctx->cork_opts.ahnd,
> -					ctx->bo, ctx->bo_size, 0,
> +			cork->addr[i] = intel_allocator_alloc_with_strategy(cork->cork_opts.ahnd,
> +					cork->bo, cork->bo_size, 0,
>  					ALLOC_STRATEGY_LOW_TO_HIGH);
>  	} else {
>  		for (unsigned int i = 0; i < width; i++)
> -			ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> +			cork->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
>  	}
>  
> -	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> +	cork->spin = xe_bo_map(fd, cork->bo, cork->bo_size);
>  
> -	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> -					     hwe, 0, &ctx->exec_queue), 0);
> +	igt_assert_eq(__xe_exec_queue_create(fd, cork->vm, width, num_placements,
> +					     hwe, 0, &cork->exec_queue), 0);
>  
> -	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> -			 ctx->sync, 1);
> +	xe_vm_bind_async(fd, cork->vm, 0, cork->bo, 0, cork->addr[0], cork->bo_size,
> +			 cork->sync, 1);
>  
> -	return ctx;
> +	return cork;
>  }
>  
>  /**
>   * xe_cork_sync_start:
>   *
>   * @fd: xe device fd
> - * @ctx: pointer to xe_cork structure
> + * @cork: pointer to xe_cork structure
>   *
>   * run the spinner using xe_spin_init submit batch using xe_exec
>   * and wait for fence using syncobj_wait
>   */
> -void xe_cork_sync_start(int fd, struct xe_cork *ctx)
> +void xe_cork_sync_start(int fd, struct xe_cork *cork)
>  {
> -	igt_assert(ctx);
> +	igt_assert(cork);
>  
> -	ctx->spin_opts.addr = ctx->addr[0];
> -	ctx->spin_opts.write_timestamp = true;
> -	ctx->spin_opts.preempt = true;
> -	xe_spin_init(ctx->spin, &ctx->spin_opts);
> +	cork->spin_opts.addr = cork->addr[0];
> +	cork->spin_opts.write_timestamp = true;
> +	cork->spin_opts.preempt = true;
> +	xe_spin_init(cork->spin, &cork->spin_opts);
>  
>  	/* reuse sync[0] as in-fence for exec */
> -	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> +	cork->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>  
> -	ctx->exec.exec_queue_id = ctx->exec_queue;
> +	cork->exec.exec_queue_id = cork->exec_queue;
>  
> -	if (ctx->width > 1)
> -		ctx->exec.address = to_user_pointer(ctx->addr);
> +	if (cork->width > 1)
> +		cork->exec.address = to_user_pointer(cork->addr);
>  	else
> -		ctx->exec.address = ctx->addr[0];
> +		cork->exec.address = cork->addr[0];
>  
> -	xe_exec(fd, &ctx->exec);
> +	xe_exec(fd, &cork->exec);
>  
> -	xe_spin_wait_started(ctx->spin);
> -	igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> +	xe_spin_wait_started(cork->spin);
> +	igt_assert(!syncobj_wait(fd, &cork->sync[1].handle, 1, 1, 0, NULL));
>  
> -	if (ctx->cork_opts.debug)
> -		igt_info("%d: spinner started\n", ctx->class);
> +	if (cork->cork_opts.debug)
> +		igt_info("%d: spinner started\n", cork->class);
>  }
>  
>  /*
>   * xe_cork_sync_end
>   *
>   * @fd: xe device fd
> - * @ctx: pointer to xe_cork structure
> + * @cork: pointer to xe_cork structure
>   *
>   * Wrapper to end spinner created by xe_cork_create. It will
>   * unbind the vm which was binded to the exec_queue and bo.
>   */
> -void xe_cork_sync_end(int fd, struct xe_cork *ctx)
> +void xe_cork_sync_end(int fd, struct xe_cork *cork)
>  {
> -	igt_assert(ctx);
> +	igt_assert(cork);
>  
> -	if (ctx->ended)
> -		igt_warn("Don't attempt call end twice %d\n", ctx->ended);
> +	if (cork->ended)
> +		igt_warn("Don't attempt call end twice %d\n", cork->ended);
>  
> -	xe_spin_end(ctx->spin);
> +	xe_spin_end(cork->spin);
>  
> -	igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> +	igt_assert(syncobj_wait(fd, &cork->sync[1].handle, 1, INT64_MAX, 0, NULL));
>  
> -	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> -	syncobj_reset(fd, &ctx->sync[0].handle, 1);
> +	cork->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> +	syncobj_reset(fd, &cork->sync[0].handle, 1);
>  
> -	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> -	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> +	xe_vm_unbind_async(fd, cork->vm, 0, 0, cork->addr[0], cork->bo_size, cork->sync, 1);
> +	igt_assert(syncobj_wait(fd, &cork->sync[0].handle, 1, INT64_MAX, 0, NULL));
>  
> -	ctx->ended = true;
> +	cork->ended = true;
>  
> -	if (ctx->cork_opts.debug)
> -		igt_info("%d: spinner ended (timestamp=%u)\n", ctx->class,
> -			ctx->spin->timestamp);
> +	if (cork->cork_opts.debug)
> +		igt_info("%d: spinner ended (timestamp=%u)\n", cork->class,
> +			cork->spin->timestamp);
>  }
>  
>  /*
>   * xe_cork_destroy
>   *
>   * @fd: xe device fd
> - * @ctx: pointer to xe_cork structure
> + * @cork: pointer to xe_cork structure
>   *
> - * It will destroy vm, exec_queue and free the ctx.
> + * It will destroy vm, exec_queue and free the cork.
>   */
> -void xe_cork_destroy(int fd, struct xe_cork *ctx)
> +void xe_cork_destroy(int fd, struct xe_cork *cork)
>  {
> -	igt_assert(ctx);
> +	igt_assert(cork);
>  
> -	syncobj_destroy(fd, ctx->sync[0].handle);
> -	syncobj_destroy(fd, ctx->sync[1].handle);
> -	xe_exec_queue_destroy(fd, ctx->exec_queue);
> +	syncobj_destroy(fd, cork->sync[0].handle);
> +	syncobj_destroy(fd, cork->sync[1].handle);
> +	xe_exec_queue_destroy(fd, cork->exec_queue);
>  
> -	if (ctx->cork_opts.ahnd)
> -		intel_allocator_free(ctx->cork_opts.ahnd, ctx->bo);
> +	if (cork->cork_opts.ahnd)
> +		intel_allocator_free(cork->cork_opts.ahnd, cork->bo);
>  
> -	munmap(ctx->spin, ctx->bo_size);
> -	gem_close(fd, ctx->bo);
> +	munmap(cork->spin, cork->bo_size);
> +	gem_close(fd, cork->bo);
>  
> -	free(ctx);
> +	free(cork);
>  }
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index f4264aadb..1089e5119 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -410,7 +410,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  {
>  	struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> -	struct xe_cork *ctx = NULL;
> +	struct xe_cork *cork = NULL;
>  	enum expected_load expected_load;
>  	uint32_t vm;
>  	int new_fd;
> @@ -420,8 +420,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  
>  	vm = xe_vm_create(fd, 0, 0);
>  	if (flags & TEST_BUSY) {
> -		ctx = xe_cork_create_opts(fd, hwe, vm, 1, 1);
> -		xe_cork_sync_start(fd, ctx);
> +		cork = xe_cork_create_opts(fd, hwe, vm, 1, 1);
> +		xe_cork_sync_start(fd, cork);
>  	}
>  
>  	read_engine_cycles(fd, pceu1[0]);
> @@ -430,7 +430,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  
>  	usleep(batch_duration_usec);
>  	if (flags & TEST_TRAILING_IDLE)
> -		xe_cork_sync_end(fd, ctx);
> +		xe_cork_sync_end(fd, cork);
>  
>  	read_engine_cycles(fd, pceu2[0]);
>  	if (flags & TEST_ISOLATION)
> @@ -449,8 +449,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  		close(new_fd);
>  	}
>  
> -	if (flags & TEST_BUSY)
> -		xe_cork_destroy(fd, ctx);
> +	if (cork)
> +		xe_cork_destroy(fd, cork);
>  
>  	xe_vm_destroy(fd, vm);
>  }
> @@ -460,19 +460,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>  {
>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> -	struct xe_cork *ctx = NULL;
> +	struct xe_cork *cork;
>  	uint32_t vm;
>  
>  	vm = xe_vm_create(fd, 0, 0);
> -	ctx = xe_cork_create_opts(fd, hwe, vm, 1, 1);
> -	xe_cork_sync_start(fd, ctx);
> +	cork = xe_cork_create_opts(fd, hwe, vm, 1, 1);
> +	xe_cork_sync_start(fd, cork);
>  
>  	read_engine_cycles(fd, pceu1);
>  	usleep(batch_duration_usec);
>  
>  	/* destroy queue before sampling again */
> -	xe_cork_sync_end(fd, ctx);
> -	xe_cork_destroy(fd, ctx);
> +	xe_cork_sync_end(fd, cork);
> +	xe_cork_destroy(fd, cork);
>  
>  	read_engine_cycles(fd, pceu2);
>  
> @@ -486,17 +486,17 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>  {
>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> -	struct xe_cork *ctx = NULL;
> +	struct xe_cork *cork;
>  	uint32_t vm;
>  	int class;
>  
>  	vm = xe_vm_create(fd, 0, 0);
> -	ctx = xe_cork_create_opts(fd, hwe, vm, 1, 1);
> -	xe_cork_sync_start(fd, ctx);
> +	cork = xe_cork_create_opts(fd, hwe, vm, 1, 1);
> +	xe_cork_sync_start(fd, cork);
>  
>  	read_engine_cycles(fd, pceu1);
>  	usleep(batch_duration_usec);
> -	xe_cork_sync_end(fd, ctx);
> +	xe_cork_sync_end(fd, cork);
>  	read_engine_cycles(fd, pceu2);
>  
>  	xe_for_each_engine_class(class) {
> @@ -506,7 +506,7 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>  		check_results(pceu1, pceu2, class, 1, expected_load);
>  	}
>  
> -	xe_cork_destroy(fd, ctx);
> +	xe_cork_destroy(fd, cork);
>  	xe_vm_destroy(fd, vm);
>  }
>  
> @@ -515,7 +515,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>  {
>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> -	struct xe_cork *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> +	struct xe_cork *cork[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>  	struct drm_xe_engine_class_instance *_hwe;
>  	uint32_t vm;
>  	int class;
> @@ -526,17 +526,17 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>  	xe_for_each_engine(fd, _hwe) {
>  		int _class = _hwe->engine_class;
>  
> -		if (_class == hwe->engine_class || ctx[_class])
> +		if (_class == hwe->engine_class || cork[_class])
>  			continue;
> -		ctx[_class] = xe_cork_create_opts(fd, _hwe, vm, 1, 1);
> -		xe_cork_sync_start(fd, ctx[_class]);
> +		cork[_class] = xe_cork_create_opts(fd, _hwe, vm, 1, 1);
> +		xe_cork_sync_start(fd, cork[_class]);
>  	}
>  
>  	read_engine_cycles(fd, pceu1);
>  	usleep(batch_duration_usec);
>  	xe_for_each_engine_class(class)
> -		if (ctx[class])
> -			xe_cork_sync_end(fd, ctx[class]);
> +		if (cork[class])
> +			xe_cork_sync_end(fd, cork[class]);
>  
>  	read_engine_cycles(fd, pceu2);
>  
> @@ -544,11 +544,11 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>  		enum expected_load expected_load = hwe->engine_class == class ?
>  			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
>  
> -		if (!ctx[class])
> +		if (!cork[class])
>  			continue;
>  
>  		check_results(pceu1, pceu2, class, 1, expected_load);
> -		xe_cork_destroy(fd, ctx[class]);
> +		xe_cork_destroy(fd, cork[class]);
>  	}
>  
>  	xe_vm_destroy(fd, vm);
> @@ -559,7 +559,7 @@ utilization_all_full_load(int fd)
>  {
>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> -	struct xe_cork *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> +	struct xe_cork *cork[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>  	struct drm_xe_engine_class_instance *hwe;
>  	uint32_t vm;
>  	int class;
> @@ -569,24 +569,24 @@ utilization_all_full_load(int fd)
>  	/* spin on one hwe per class */
>  	xe_for_each_engine(fd, hwe) {
>  		class = hwe->engine_class;
> -		if (ctx[class])
> +		if (cork[class])
>  			continue;
> -		ctx[class] = xe_cork_create_opts(fd, hwe, vm, 1, 1);
> -		xe_cork_sync_start(fd, ctx[class]);
> +		cork[class] = xe_cork_create_opts(fd, hwe, vm, 1, 1);
> +		xe_cork_sync_start(fd, cork[class]);
>  	}
>  
>  	read_engine_cycles(fd, pceu1);
>  	usleep(batch_duration_usec);
>  	xe_for_each_engine_class(class)
> -		xe_cork_sync_end(fd, ctx[class]);
> +		xe_cork_sync_end(fd, cork[class]);
>  	read_engine_cycles(fd, pceu2);
>  
>  	xe_for_each_engine_class(class) {
> -		if (!ctx[class])
> +		if (!cork[class])
>  			continue;
>  
>  		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
> -		xe_cork_destroy(fd, ctx[class]);
> +		xe_cork_destroy(fd, cork[class]);
>  	}
>  
>  	xe_vm_destroy(fd, vm);
> @@ -613,7 +613,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>  	struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
> -	struct xe_cork *ctx = NULL;
> +	struct xe_cork *cork = NULL;
>  	enum expected_load expected_load;
>  	int fd_spill, num_placements;
>  	uint32_t vm;
> @@ -639,8 +639,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>  
>  	vm = xe_vm_create(fd, 0, 0);
>  	if (flags & TEST_BUSY) {
> -		ctx = xe_cork_create_opts(fd, eci, vm, width, num_placements);
> -		xe_cork_sync_start(fd, ctx);
> +		cork = xe_cork_create_opts(fd, eci, vm, width, num_placements);
> +		xe_cork_sync_start(fd, cork);
>  	}
>  
>  	read_engine_cycles(fd, pceu[0]);
> @@ -649,7 +649,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>  
>  	usleep(batch_duration_usec);
>  	if (flags & TEST_TRAILING_IDLE)
> -		xe_cork_sync_end(fd, ctx);
> +		xe_cork_sync_end(fd, cork);
>  
>  	read_engine_cycles(fd, pceu[1]);
>  	if (flags & TEST_ISOLATION)
> @@ -669,8 +669,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>  		close(fd_spill);
>  	}
>  
> -	if (flags & TEST_BUSY)
> -		xe_cork_destroy(fd, ctx);
> +	if (cork)
> +		xe_cork_destroy(fd, cork);
>  
>  	xe_vm_destroy(fd, vm);
>  }
> diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
> index 5d9afaf3d..e4000f50e 100644
> --- a/tests/intel/xe_spin_batch.c
> +++ b/tests/intel/xe_spin_batch.c
> @@ -384,25 +384,25 @@ static void exec_store(int fd, struct drm_xe_engine_class_instance *eci,
>  
>  static void run_spinner(int fd, struct drm_xe_engine_class_instance *eci)
>  {
> -	struct xe_cork *ctx = NULL;
> +	struct xe_cork *cork;
>  	uint32_t vm;
>  	uint32_t ts_1, ts_2;
>  	uint64_t ahnd;
>  
>  	vm = xe_vm_create(fd, 0, 0);
>  	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> -	ctx = xe_cork_create_opts(fd, eci, vm, 1, 1, .ahnd = ahnd);
> -	xe_cork_sync_start(fd, ctx);
> +	cork = xe_cork_create_opts(fd, eci, vm, 1, 1, .ahnd = ahnd);
> +	xe_cork_sync_start(fd, cork);
>  
>  	/* Collect and check timestamps before stopping the spinner */
>  	usleep(50000);
> -	ts_1 = READ_ONCE(ctx->spin->timestamp);
> +	ts_1 = READ_ONCE(cork->spin->timestamp);
>  	usleep(50000);
> -	ts_2 = READ_ONCE(ctx->spin->timestamp);
> +	ts_2 = READ_ONCE(cork->spin->timestamp);
>  	igt_assert_neq_u32(ts_1, ts_2);
>  
> -	xe_cork_sync_end(fd, ctx);
> -	xe_cork_destroy(fd, ctx);
> +	xe_cork_sync_end(fd, cork);
> +	xe_cork_destroy(fd, cork);
>  
>  	xe_vm_destroy(fd, vm);
>  	put_ahnd(ahnd);
> diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
> index b10269191..9e524578a 100644
> --- a/tests/intel/xe_vm.c
> +++ b/tests/intel/xe_vm.c
> @@ -945,21 +945,21 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
>  
>  	sync[0].handle = syncobj_create(fd, 0);
>  	if (flags & BIND_ARRAY_ENOBUFS_FLAG) {
> -		struct xe_cork *ctx = NULL;
> +		struct xe_cork *cork;
>  		uint32_t vm_cork;
>  
>  		vm_cork = xe_vm_create(fd, 0, 0);
> -		ctx = xe_cork_create_opts(fd, eci, vm_cork, 1, 1);
> -		xe_cork_sync_start(fd, ctx);
> +		cork = xe_cork_create_opts(fd, eci, vm_cork, 1, 1);
> +		xe_cork_sync_start(fd, cork);
>  
> -		sync[1].handle = ctx->sync[1].handle;
> +		sync[1].handle = cork->sync[1].handle;
>  		sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>  
>  		xe_vm_bind_array_err(fd, vm, bind_exec_queue, bind_ops,
>  				     n_execs, sync, 2, ENOBUFS);
>  		/* destroy queue before sampling again */
> -		xe_cork_sync_end(fd, ctx);
> -		xe_cork_destroy(fd, ctx);
> +		xe_cork_sync_end(fd, cork);
> +		xe_cork_destroy(fd, cork);
>  		xe_vm_destroy(fd, vm_cork);
>  
>  		n_execs = n_execs / 4;
> -- 
> 2.47.0
> 
> 

RE: [PATCH i-g-t 8/8] tests/intel/xe_drm_fdinfo: Stop asserting on usage percentage

[Cavitt, Jonathan]

-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De Marchi
Sent: Friday, January 3, 2025 11:16 PM
To: igt-dev@lists.freedesktop.org
Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; Nerlige Ramappa, Umesh <umesh.nerlige.ramappa@intel.com>
Subject: [PATCH i-g-t 8/8] tests/intel/xe_drm_fdinfo: Stop asserting on usage percentage
> 
> It's unreliable to assert on the usage percentage considering 2 data
> points as it still depends on the CPU scheduling not preempting tasks in
> the wrong moment. On a normal use case of a top-like application, the
> value not accounted for would simply show up in the next sample without
> much issue. For a test assertion, it's better to check that the value
> reported via fdinfo is reasonably close to the one saved by the GPU in
> the spin. It's still allowed some error because there are a few GPU
> ticks of difference due to the **GPU** scheduling the contexts.
> 
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

There's a few nits/questions below, but I trust that everything is in
order, so nothing below is particularly blocking.  If I did manage to
catch something that needs fixing, then of course that should be
fixed, but otherwise:
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>

> ---
>  tests/intel/xe_drm_fdinfo.c | 49 +++++++++++++++++++++++--------------
>  1 file changed, 31 insertions(+), 18 deletions(-)
> 
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 1089e5119..120436fbe 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -3,6 +3,8 @@
>   * Copyright (c) 2023 Intel Corporation
>   */
>  
> +#include <math.h>
> +
>  #include "igt.h"
>  #include "igt_core.h"
>  #include "igt_device.h"
> @@ -371,7 +373,8 @@ static void basic_engine_utilization(int xe)
>  
>  static void
>  check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> -	      int class, int width, enum expected_load expected_load)
> +	      int class, int width, uint32_t spin_stamp,
> +	      enum expected_load expected_load)
>  {
>  	double percent;
>  	u64 den, num;
> @@ -383,12 +386,9 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>  
>  	num = s2[class].cycles - s1[class].cycles;
>  	den = s2[class].total_cycles - s1[class].total_cycles;
> -	percent = (num * 100.0) / (den + 1);
> -
> -	/* for parallel submission scale the busyness with width */
> -	percent /= width;
>  
> -	igt_debug("%s: percent: %f\n", engine_map[class], percent);
> +	percent = (num * 100.0) / (den + 1) / width;

Nit:
There's probably an argument to be made that we didn't need to modify
the calculation here because the end result is still the same and it loses
a (presumably) helpful comment, but I won't block on it.

Also, is this percentage correct given the test modifications?
Maybe we should be dividing by spin_stamp + 1 instead, since that's what
we're using to calculate the percentage later?

> +	igt_debug("%s: percent: %.2f%%\n", engine_map[class], percent);
>  
>  	switch (expected_load) {
>  	case EXPECTED_LOAD_IDLE:
> @@ -396,11 +396,12 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>  		break;
>  	case EXPECTED_LOAD_FULL:
>  		/*
> -		 * We are still relying on CPU sleep time and there could be
> -		 * some imprecision when calculating the load. Use a 5% margin.
> +		 * percentage error between value saved by gpu in xe_spin and what
> +		 * is reported via fdinfo

Nit:
s/percentage/Percentage

>  		 */
> -		igt_assert_lt_double(95.0, percent);
> -		igt_assert_lt_double(percent, 105.0);
> +		percent = fabs((num - spin_stamp) * 100.0) / (spin_stamp + 1);

Nit:
Shouldn't we also be dividing by width here?  I'm just asking because that's
what we were doing before, and it looks like spin_stamp is being used here
as a stand-in for the "den" variable in the earlier percent calculation.

> +		igt_debug("%s: error: %.2f%%\n", engine_map[class], percent);
> +		igt_assert_lt_double(percent, 5.0);
>  		break;
>  	}
>  }
> @@ -438,14 +439,17 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  
>  	expected_load = flags & TEST_BUSY ?
>  	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
> -	check_results(pceu1[0], pceu2[0], hwe->engine_class, 1, expected_load);
> +
> +	check_results(pceu1[0], pceu2[0], hwe->engine_class, 1,
> +		      cork ? cork->spin->timestamp : 0, expected_load);
>  
>  	if (flags & TEST_ISOLATION) {
>  		/*
>  		 * Load from one client shouldn't spill on another,
>  		 * so check for idle
>  		 */
> -		check_results(pceu1[1], pceu2[1], hwe->engine_class, 1, EXPECTED_LOAD_IDLE);
> +		check_results(pceu1[1], pceu2[1], hwe->engine_class, 1, 0,
> +			      EXPECTED_LOAD_IDLE);
>  		close(new_fd);
>  	}
>  
> @@ -461,6 +465,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct xe_cork *cork;
> +	uint32_t timestamp;
>  	uint32_t vm;
>  
>  	vm = xe_vm_create(fd, 0, 0);
> @@ -472,13 +477,15 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>  
>  	/* destroy queue before sampling again */
>  	xe_cork_sync_end(fd, cork);
> +	timestamp = cork->spin->timestamp;
>  	xe_cork_destroy(fd, cork);
>  
>  	read_engine_cycles(fd, pceu2);
>  
>  	xe_vm_destroy(fd, vm);
>  
> -	check_results(pceu1, pceu2, hwe->engine_class, 1, EXPECTED_LOAD_FULL);
> +	check_results(pceu1, pceu2, hwe->engine_class, 1, timestamp,
> +		      EXPECTED_LOAD_FULL);
>  }
>  
>  static void
> @@ -503,7 +510,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>  		enum expected_load expected_load = hwe->engine_class != class ?
>  			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
>  
> -		check_results(pceu1, pceu2, class, 1, expected_load);
> +		check_results(pceu1, pceu2, class, 1, cork->spin->timestamp,
> +			      expected_load);
>  	}
>  
>  	xe_cork_destroy(fd, cork);
> @@ -547,7 +555,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>  		if (!cork[class])
>  			continue;
>  
> -		check_results(pceu1, pceu2, class, 1, expected_load);
> +		check_results(pceu1, pceu2, class, 1, cork[class]->spin->timestamp,
> +			      expected_load);
>  		xe_cork_destroy(fd, cork[class]);
>  	}
>  
> @@ -585,7 +594,9 @@ utilization_all_full_load(int fd)
>  		if (!cork[class])
>  			continue;
>  
> -		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
> +		check_results(pceu1, pceu2, class, 1,
> +			      cork[class]->spin->timestamp,
> +			      EXPECTED_LOAD_FULL);
>  		xe_cork_destroy(fd, cork[class]);
>  	}
>  
> @@ -657,14 +668,16 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>  
>  	expected_load = flags & TEST_BUSY ?
>  	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
> -	check_results(pceu[0], pceu[1], class, width, expected_load);
> +
> +	check_results(pceu[0], pceu[1], class, width,
> +		      cork ? cork->spin->timestamp : 0, expected_load);
>  
>  	if (flags & TEST_ISOLATION) {
>  		/*
>  		 * Load from one client shouldn't spill on another,
>  		 * so check for idle
>  		 */
> -		check_results(pceu_spill[0], pceu_spill[1], class, width,
> +		check_results(pceu_spill[0], pceu_spill[1], class, width, 0,
>  			      EXPECTED_LOAD_IDLE);
>  		close(fd_spill);
>  	}
> -- 
> 2.47.0
> 
> 

✗ Xe.CI.Full: failure for series starting with [i-g-t,1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 106046 bytes --]

== Series Details ==

Series: series starting with [i-g-t,1/8] tests/intel/xe_drm_fdinfo: Do not end cork not started (rev2)
URL   : https://patchwork.freedesktop.org/series/143108/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8174_full -> XEIGTPW_12393_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_12393_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_12393_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_12393_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@flip-vs-suspend@c-dp2:
    - shard-bmg:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-7/igt@kms_flip@flip-vs-suspend@c-dp2.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-5/igt@kms_flip@flip-vs-suspend@c-dp2.html

  * igt@xe_drm_fdinfo@parallel-utilization-single-full-load-isolation:
    - shard-bmg:          [PASS][3] -> [FAIL][4] +1 other test fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@xe_drm_fdinfo@parallel-utilization-single-full-load-isolation.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@xe_drm_fdinfo@parallel-utilization-single-full-load-isolation.html
    - shard-dg2-set2:     [PASS][5] -> [FAIL][6] +1 other test fail
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@xe_drm_fdinfo@parallel-utilization-single-full-load-isolation.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-434/igt@xe_drm_fdinfo@parallel-utilization-single-full-load-isolation.html

  
#### Warnings ####

  * igt@xe_drm_fdinfo@utilization-others-full-load:
    - shard-dg2-set2:     [FAIL][7] ([Intel XE#3869]) -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-436/igt@xe_drm_fdinfo@utilization-others-full-load.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@xe_drm_fdinfo@utilization-others-full-load.html

  
Known issues
------------

  Here are the changes found in XEIGTPW_12393_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_getstats:
    - shard-dg2-set2:     [PASS][9] -> [SKIP][10] ([Intel XE#2423]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@core_getstats.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@core_getstats.html

  * igt@core_hotunplug@hotunplug-rescan:
    - shard-dg2-set2:     [PASS][11] -> [SKIP][12] ([Intel XE#1885]) +3 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@core_hotunplug@hotunplug-rescan.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@core_hotunplug@hotunplug-rescan.html

  * igt@core_setmaster@master-drop-set-root:
    - shard-dg2-set2:     NOTRUN -> [FAIL][13] ([Intel XE#3249])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@core_setmaster@master-drop-set-root.html

  * igt@fbdev@read:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#2134])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@fbdev@read.html

  * igt@fbdev@write:
    - shard-dg2-set2:     [PASS][15] -> [SKIP][16] ([Intel XE#2134]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@fbdev@write.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@fbdev@write.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#3157])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic:
    - shard-lnl:          [PASS][18] -> [FAIL][19] ([Intel XE#3719]) +3 other tests fail
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html

  * igt@kms_atomic@plane-invalid-params-fence:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#2423] / [i915#2575]) +17 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_atomic@plane-invalid-params-fence.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#3279])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#316])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#3658])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#1407]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#1428])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#1124]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#1124]) +8 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#1124]) +4 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2314] / [Intel XE#2894])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#367])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#367])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#2887]) +7 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-hdmi-a-3:
    - shard-bmg:          [PASS][33] -> [INCOMPLETE][34] ([Intel XE#3862])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-hdmi-a-3.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#3432]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][36] ([Intel XE#455] / [Intel XE#787]) +18 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#787]) +58 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2887]) +9 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-dg2-set2:     NOTRUN -> [SKIP][39] ([Intel XE#373]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#306])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-4/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2252]) +5 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#373]) +5 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-4/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#307])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@mei-interface:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#3007]) +4 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@uevent:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#3278]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#2321]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2321])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-5/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#1424]) +3 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@kms_cursor_crc@cursor-random-128x42.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#455]) +8 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2320]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-5/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-dg2-set2:     [PASS][51] -> [INCOMPLETE][52] ([Intel XE#3226])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#309]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][54] -> [DMESG-WARN][55] ([Intel XE#877]) +1 other test dmesg-warn
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2286])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [FAIL][57] ([Intel XE#2141]) +2 other tests fail
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#3383])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#2244])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-dp2-hdmi-a3:
    - shard-bmg:          [PASS][60] -> [FAIL][61] ([Intel XE#2882] / [Intel XE#3288]) +1 other test fail
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-dp2-hdmi-a3.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3:
    - shard-bmg:          [PASS][62] -> [FAIL][63] ([Intel XE#3288] / [Intel XE#3321]) +1 other test fail
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3:
    - shard-bmg:          [PASS][64] -> [FAIL][65] ([Intel XE#3321])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#1421]) +3 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-bmg:          [PASS][67] -> [SKIP][68] ([Intel XE#3007]) +11 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-8/igt@kms_flip@2x-plain-flip-fb-recreate.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@busy-flip:
    - shard-dg2-set2:     [PASS][69] -> [SKIP][70] ([Intel XE#2423] / [i915#2575]) +225 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_flip@busy-flip.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_flip@busy-flip.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][71] ([Intel XE#301]) +3 other tests fail
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6:
    - shard-dg2-set2:     [PASS][72] -> [FAIL][73] ([Intel XE#301])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][74] ([Intel XE#2597]) +1 other test incomplete
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend@a-dp2:
    - shard-bmg:          [PASS][75] -> [FAIL][76] ([Intel XE#3879])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-7/igt@kms_flip@flip-vs-suspend@a-dp2.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-5/igt@kms_flip@flip-vs-suspend@a-dp2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-dg2-set2:     [PASS][77] -> [SKIP][78] ([Intel XE#2136]) +75 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#2136] / [Intel XE#2351]) +7 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#2293]) +1 other test skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#1401] / [Intel XE#1745])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#1401])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#1397] / [Intel XE#1745]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#1397]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling:
    - shard-bmg:          [PASS][85] -> [SKIP][86] ([Intel XE#2136] / [Intel XE#2231])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#2311]) +11 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#651]) +7 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][90] ([Intel XE#651]) +3 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          NOTRUN -> [FAIL][91] ([Intel XE#2333]) +8 other tests fail
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [PASS][92] -> [SKIP][93] ([Intel XE#2136] / [Intel XE#2351]) +24 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#2352])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][95] ([Intel XE#656]) +20 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#2313]) +23 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#2136] / [Intel XE#2231]) +3 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#1469])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     NOTRUN -> [SKIP][99] ([Intel XE#653]) +6 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_hdr@static-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#1503])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@kms_hdr@static-toggle.html

  * igt@kms_histogram@global-basic:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#3898]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_histogram@global-basic.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][102] ([Intel XE#346])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#2927])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][104] ([Intel XE#2927])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
    - shard-dg2-set2:     [PASS][105] -> [FAIL][106] ([Intel XE#616]) +1 other test fail
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#2763]) +3 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d:
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#2763]) +14 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
    - shard-dg2-set2:     NOTRUN -> [SKIP][109] ([Intel XE#2763] / [Intel XE#455]) +3 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b:
    - shard-dg2-set2:     NOTRUN -> [SKIP][110] ([Intel XE#2763]) +5 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [PASS][111] -> [FAIL][112] ([Intel XE#718])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-3/igt@kms_pm_dc@dc5-psr.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][113] ([Intel XE#908])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#2499])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-dg2-set2:     [PASS][115] -> [SKIP][116] ([Intel XE#2446]) +8 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_pm_rpm@modeset-non-lpsp.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@universal-planes-dpms:
    - shard-bmg:          [PASS][117] -> [SKIP][118] ([Intel XE#2446])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-8/igt@kms_pm_rpm@universal-planes-dpms.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_pm_rpm@universal-planes-dpms.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][119] ([Intel XE#2893])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][120] ([Intel XE#1489])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][121] ([Intel XE#1489]) +4 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][122] ([Intel XE#2136]) +21 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_psr@pr-cursor-render:
    - shard-lnl:          NOTRUN -> [SKIP][123] ([Intel XE#1406])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@kms_psr@pr-cursor-render.html

  * igt@kms_psr@psr-primary-page-flip:
    - shard-bmg:          NOTRUN -> [SKIP][124] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_psr@psr-primary-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][125] ([Intel XE#2850] / [Intel XE#929])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_psr@psr-primary-render.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-lnl:          NOTRUN -> [SKIP][126] ([Intel XE#3414] / [Intel XE#3904])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-4/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-bmg:          NOTRUN -> [SKIP][127] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-bmg:          NOTRUN -> [SKIP][128] ([Intel XE#2413])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][129] ([Intel XE#1435])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-lnl:          NOTRUN -> [SKIP][130] ([Intel XE#362])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][131] -> [FAIL][132] ([Intel XE#2159]) +1 other test fail
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-3/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@kms_vrr@flipline:
    - shard-bmg:          NOTRUN -> [SKIP][133] ([Intel XE#1499])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_vrr@flipline.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-lnl:          NOTRUN -> [SKIP][134] ([Intel XE#1499])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-8/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-dg2-set2:     NOTRUN -> [SKIP][135] ([Intel XE#1091] / [Intel XE#2849])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@xe_ccs@suspend-resume:
    - shard-bmg:          [PASS][136] -> [INCOMPLETE][137] ([Intel XE#3918]) +1 other test incomplete
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-7/igt@xe_ccs@suspend-resume.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-5/igt@xe_ccs@suspend-resume.html

  * igt@xe_drm_fdinfo@utilization-single-full-load-isolation:
    - shard-bmg:          [PASS][138] -> [SKIP][139] ([Intel XE#1130]) +25 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-8/igt@xe_drm_fdinfo@utilization-single-full-load-isolation.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@xe_drm_fdinfo@utilization-single-full-load-isolation.html

  * igt@xe_eudebug@basic-vm-access-parameters-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][140] ([Intel XE#3889])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@xe_eudebug@basic-vm-access-parameters-userptr.html

  * igt@xe_eudebug@basic-vm-bind-discovery:
    - shard-dg2-set2:     NOTRUN -> [SKIP][141] ([Intel XE#2905])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@xe_eudebug@basic-vm-bind-discovery.html

  * igt@xe_eudebug_online@single-step:
    - shard-lnl:          NOTRUN -> [SKIP][142] ([Intel XE#2905]) +2 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@xe_eudebug_online@single-step.html

  * igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-vram:
    - shard-bmg:          NOTRUN -> [SKIP][143] ([Intel XE#2905]) +5 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-vram.html

  * igt@xe_evict@evict-cm-threads-small-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][144] ([Intel XE#688]) +7 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-5/igt@xe_evict@evict-cm-threads-small-multi-vm.html

  * igt@xe_evict@evict-large-multi-vm-cm:
    - shard-bmg:          NOTRUN -> [FAIL][145] ([Intel XE#2364])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@xe_evict@evict-large-multi-vm-cm.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-reopen:
    - shard-dg2-set2:     [PASS][146] -> [SKIP][147] ([Intel XE#1130]) +417 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-436/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-reopen.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-reopen.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][148] ([Intel XE#1392]) +1 other test skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][149] ([Intel XE#2322]) +3 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_basic@no-exec-null-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][150] ([Intel XE#1130]) +7 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@xe_exec_basic@no-exec-null-defer-bind.html

  * igt@xe_exec_fault_mode@many-invalid-userptr-fault:
    - shard-dg2-set2:     NOTRUN -> [SKIP][151] ([Intel XE#288])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@xe_exec_fault_mode@many-invalid-userptr-fault.html

  * igt@xe_live_ktest@xe_bo:
    - shard-lnl:          NOTRUN -> [SKIP][152] ([Intel XE#1192])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@xe_live_ktest@xe_bo.html

  * igt@xe_live_ktest@xe_dma_buf:
    - shard-bmg:          NOTRUN -> [SKIP][153] ([Intel XE#1192])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@xe_live_ktest@xe_dma_buf.html

  * igt@xe_live_ktest@xe_migrate:
    - shard-dg2-set2:     [PASS][154] -> [SKIP][155] ([Intel XE#1192]) +2 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@xe_live_ktest@xe_migrate.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_live_ktest@xe_migrate.html

  * igt@xe_live_ktest@xe_mocs:
    - shard-bmg:          [PASS][156] -> [SKIP][157] ([Intel XE#1192]) +2 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-7/igt@xe_live_ktest@xe_mocs.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@xe_live_ktest@xe_mocs.html

  * igt@xe_module_load@force-load:
    - shard-lnl:          NOTRUN -> [SKIP][158] ([Intel XE#378])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@xe_module_load@force-load.html

  * igt@xe_module_load@reload-no-display:
    - shard-dg2-set2:     [PASS][159] -> [FAIL][160] ([Intel XE#3546])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@xe_module_load@reload-no-display.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_module_load@reload-no-display.html

  * igt@xe_oa@closed-fd-and-unmapped-access:
    - shard-dg2-set2:     NOTRUN -> [SKIP][161] ([Intel XE#2541] / [Intel XE#3573]) +2 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-434/igt@xe_oa@closed-fd-and-unmapped-access.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-lnl:          NOTRUN -> [SKIP][162] ([Intel XE#1420] / [Intel XE#2838])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-bmg:          NOTRUN -> [SKIP][163] ([Intel XE#2284])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@xe_pm@d3cold-mmap-system.html

  * igt@xe_pm@s3-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][164] ([Intel XE#584])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-8/igt@xe_pm@s3-basic-exec.html

  * igt@xe_pm@s4-d3cold-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][165] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@xe_pm@s4-d3cold-basic-exec.html

  * igt@xe_query@multigpu-query-engines:
    - shard-bmg:          NOTRUN -> [SKIP][166] ([Intel XE#944])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@xe_query@multigpu-query-engines.html

  * igt@xe_query@multigpu-query-invalid-extension:
    - shard-lnl:          NOTRUN -> [SKIP][167] ([Intel XE#944])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@xe_query@multigpu-query-invalid-extension.html

  * igt@xe_query@multigpu-query-topology:
    - shard-dg2-set2:     NOTRUN -> [SKIP][168] ([Intel XE#944])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@xe_query@multigpu-query-topology.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-lnl:          NOTRUN -> [SKIP][169] ([Intel XE#3342])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@xe_sriov_flr@flr-vf1-clear.html

  * igt@xe_vm@invalid-extensions:
    - shard-dg2-set2:     NOTRUN -> [SKIP][170] ([Intel XE#1130]) +36 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_vm@invalid-extensions.html

  
#### Possible fixes ####

  * igt@kms_flip@2x-flip-vs-expired-vblank@ad-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][171] ([Intel XE#3321]) -> [PASS][172] +1 other test pass
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank@ad-dp2-hdmi-a3.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ad-dp2-hdmi-a3.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a6:
    - shard-dg2-set2:     [FAIL][173] ([Intel XE#301]) -> [PASS][174]
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a6.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a6.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-dg2-set2:     [INCOMPLETE][175] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_flip@flip-vs-suspend-interruptible.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp4:
    - shard-dg2-set2:     [INCOMPLETE][177] ([Intel XE#2597]) -> [PASS][178]
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_flip@flip-vs-suspend-interruptible@c-dp4.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_flip@flip-vs-suspend-interruptible@c-dp4.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2:
    - shard-bmg:          [FAIL][179] ([Intel XE#2882]) -> [PASS][180] +1 other test pass
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2.html

  * igt@kms_hdr@bpc-switch:
    - shard-dg2-set2:     [INCOMPLETE][181] -> [PASS][182]
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_hdr@bpc-switch.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-436/igt@kms_hdr@bpc-switch.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [FAIL][183] ([Intel XE#361]) -> [PASS][184]
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-434/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [FAIL][185] ([Intel XE#718]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-5/igt@kms_pm_dc@dc5-dpms.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-8/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_sequence@get-forked-busy:
    - shard-bmg:          [INCOMPLETE][187] ([Intel XE#3313]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-7/igt@kms_sequence@get-forked-busy.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_sequence@get-forked-busy.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
    - shard-lnl:          [FAIL][189] ([Intel XE#899]) -> [PASS][190]
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-5/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][191], [PASS][192], [PASS][193], [PASS][194], [PASS][195], [PASS][196], [PASS][197], [PASS][198], [PASS][199], [PASS][200], [PASS][201], [PASS][202], [PASS][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207], [PASS][208], [PASS][209], [PASS][210], [PASS][211], [PASS][212], [SKIP][213], [PASS][214], [PASS][215], [PASS][216]) ([Intel XE#378]) -> ([PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232], [PASS][233], [PASS][234], [PASS][235], [PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [PASS][241])
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-1/igt@xe_module_load@load.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-7/igt@xe_module_load@load.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-1/igt@xe_module_load@load.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-5/igt@xe_module_load@load.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-8/igt@xe_module_load@load.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-2/igt@xe_module_load@load.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-7/igt@xe_module_load@load.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-8/igt@xe_module_load@load.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-8/igt@xe_module_load@load.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-3/igt@xe_module_load@load.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-3/igt@xe_module_load@load.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-3/igt@xe_module_load@load.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-2/igt@xe_module_load@load.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-2/igt@xe_module_load@load.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-4/igt@xe_module_load@load.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-6/igt@xe_module_load@load.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-1/igt@xe_module_load@load.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-4/igt@xe_module_load@load.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-4/igt@xe_module_load@load.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-7/igt@xe_module_load@load.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-5/igt@xe_module_load@load.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-5/igt@xe_module_load@load.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-1/igt@xe_module_load@load.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-6/igt@xe_module_load@load.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-6/igt@xe_module_load@load.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-1/igt@xe_module_load@load.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-8/igt@xe_module_load@load.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-4/igt@xe_module_load@load.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-8/igt@xe_module_load@load.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-4/igt@xe_module_load@load.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@xe_module_load@load.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@xe_module_load@load.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@xe_module_load@load.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-5/igt@xe_module_load@load.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@xe_module_load@load.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@xe_module_load@load.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@xe_module_load@load.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-1/igt@xe_module_load@load.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-8/igt@xe_module_load@load.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-5/igt@xe_module_load@load.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@xe_module_load@load.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@xe_module_load@load.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@xe_module_load@load.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-5/igt@xe_module_load@load.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@xe_module_load@load.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-4/igt@xe_module_load@load.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-4/igt@xe_module_load@load.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@xe_module_load@load.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@xe_module_load@load.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-6/igt@xe_module_load@load.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@xe_module_load@load.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-lnl:          [ABORT][242] ([Intel XE#1607] / [Intel XE#1794]) -> [PASS][243]
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-3/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_pm_residency@gt-c6-freeze:
    - shard-bmg:          [INCOMPLETE][244] ([Intel XE#3088]) -> [PASS][245]
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-8/igt@xe_pm_residency@gt-c6-freeze.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@xe_pm_residency@gt-c6-freeze.html

  * igt@xe_pm_residency@gt-c6-freeze@gt1:
    - shard-bmg:          [INCOMPLETE][246] -> [PASS][247] +1 other test pass
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-8/igt@xe_pm_residency@gt-c6-freeze@gt1.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@xe_pm_residency@gt-c6-freeze@gt1.html

  
#### Warnings ####

  * igt@kms_async_flips@crc:
    - shard-bmg:          [INCOMPLETE][248] ([Intel XE#3781]) -> [INCOMPLETE][249] ([Intel XE#3781] / [Intel XE#3946]) +1 other test incomplete
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@kms_async_flips@crc.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@kms_async_flips@crc.html

  * igt@kms_async_flips@crc-atomic:
    - shard-dg2-set2:     [INCOMPLETE][250] ([Intel XE#3781]) -> [INCOMPLETE][251] ([Intel XE#3781] / [Intel XE#3946]) +1 other test incomplete
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_async_flips@crc-atomic.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-434/igt@kms_async_flips@crc-atomic.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-dg2-set2:     [SKIP][252] ([Intel XE#873]) -> [SKIP][253] ([Intel XE#2423] / [i915#2575])
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_async_flips@invalid-async-flip.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][254] ([Intel XE#316]) -> [SKIP][255] ([Intel XE#2136] / [Intel XE#2351]) +2 other tests skip
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_big_fb@linear-16bpp-rotate-90.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-bmg:          [SKIP][256] ([Intel XE#2327]) -> [SKIP][257] ([Intel XE#2136] / [Intel XE#2231]) +1 other test skip
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-5/igt@kms_big_fb@linear-64bpp-rotate-270.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][258] ([Intel XE#316]) -> [SKIP][259] ([Intel XE#2136]) +7 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-dg2-set2:     [SKIP][260] ([Intel XE#619]) -> [SKIP][261] ([Intel XE#2136] / [Intel XE#2351])
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_big_fb@y-tiled-addfb.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-dg2-set2:     [SKIP][262] ([Intel XE#1124]) -> [SKIP][263] ([Intel XE#2136] / [Intel XE#2351]) +11 other tests skip
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     [SKIP][264] ([Intel XE#607]) -> [SKIP][265] ([Intel XE#2136])
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-bmg:          [SKIP][266] ([Intel XE#1124]) -> [SKIP][267] ([Intel XE#2136] / [Intel XE#2231])
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg2-set2:     [SKIP][268] ([Intel XE#1124]) -> [SKIP][269] ([Intel XE#2136]) +18 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p:
    - shard-dg2-set2:     [SKIP][270] ([Intel XE#367]) -> [SKIP][271] ([Intel XE#2423] / [i915#2575]) +10 other tests skip
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-436/igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
    - shard-dg2-set2:     [SKIP][272] ([Intel XE#2191]) -> [SKIP][273] ([Intel XE#2423] / [i915#2575]) +2 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-dg2-set2:     [SKIP][274] ([Intel XE#2907]) -> [SKIP][275] ([Intel XE#2136]) +4 other tests skip
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs:
    - shard-dg2-set2:     [SKIP][276] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][277] ([Intel XE#2136] / [Intel XE#2351]) +5 other tests skip
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-436/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg2-set2:     [SKIP][278] ([Intel XE#3442]) -> [SKIP][279] ([Intel XE#2136])
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs:
    - shard-bmg:          [SKIP][280] ([Intel XE#2887]) -> [SKIP][281] ([Intel XE#2136] / [Intel XE#2231]) +1 other test skip
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-7/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
    - shard-dg2-set2:     [SKIP][282] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][283] ([Intel XE#2136]) +24 other tests skip
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-dg2-set2:     [SKIP][284] ([Intel XE#314]) -> [SKIP][285] ([Intel XE#2136] / [Intel XE#2351])
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_cdclk@mode-transition-all-outputs.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-bmg:          [SKIP][286] ([Intel XE#2325]) -> [SKIP][287] ([Intel XE#3007])
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-4/igt@kms_chamelium_color@ctm-negative.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_color@gamma:
    - shard-dg2-set2:     [SKIP][288] ([Intel XE#306]) -> [SKIP][289] ([Intel XE#2423] / [i915#2575]) +3 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_chamelium_color@gamma.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_frames@hdmi-cmp-planes-random:
    - shard-bmg:          [SKIP][290] ([Intel XE#2252]) -> [SKIP][291] ([Intel XE#3007])
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-7/igt@kms_chamelium_frames@hdmi-cmp-planes-random.html
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_chamelium_frames@hdmi-cmp-planes-random.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-dg2-set2:     [SKIP][292] ([Intel XE#373]) -> [SKIP][293] ([Intel XE#2423] / [i915#2575]) +28 other tests skip
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-set2:     [FAIL][294] ([Intel XE#1178]) -> [SKIP][295] ([Intel XE#2423] / [i915#2575]) +3 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_content_protection@atomic-dpms.html
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2-set2:     [SKIP][296] ([Intel XE#307]) -> [SKIP][297] ([Intel XE#2423] / [i915#2575]) +3 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_content_protection@dp-mst-lic-type-0.html
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-bmg:          [SKIP][298] ([Intel XE#2320]) -> [SKIP][299] ([Intel XE#3007]) +1 other test skip
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-8/igt@kms_cursor_crc@cursor-sliding-256x85.html
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-dg2-set2:     [SKIP][300] ([Intel XE#308]) -> [SKIP][301] ([Intel XE#2423] / [i915#2575]) +2 other tests skip
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_cursor_crc@cursor-sliding-512x170.html
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg2-set2:     [SKIP][302] ([Intel XE#323]) -> [SKIP][303] ([Intel XE#2423] / [i915#2575]) +3 other tests skip
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-bmg:          [SKIP][304] ([Intel XE#2286]) -> [SKIP][305] ([Intel XE#3007])
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-dg2-set2:     [SKIP][306] ([Intel XE#455]) -> [SKIP][307] ([Intel XE#2136] / [Intel XE#2351]) +6 other tests skip
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_dsc@dsc-with-bpc-formats.html
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-bmg:          [SKIP][308] ([Intel XE#2244]) -> [SKIP][309] ([Intel XE#2136] / [Intel XE#2231])
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@kms_dsc@dsc-with-formats.html
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2-set2:     [SKIP][310] ([Intel XE#455]) -> [SKIP][311] ([Intel XE#2136]) +9 other tests skip
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2-set2:     [SKIP][312] ([Intel XE#701]) -> [SKIP][313] ([Intel XE#2423] / [i915#2575])
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_feature_discovery@chamelium.html
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2-set2:     [SKIP][314] ([Intel XE#703]) -> [SKIP][315] ([Intel XE#2423] / [i915#2575])
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_feature_discovery@display-3x.html
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
    - shard-bmg:          [SKIP][316] ([Intel XE#2293] / [Intel XE#2380]) -> [SKIP][317] ([Intel XE#2136] / [Intel XE#2231])
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-suspend:
    - shard-dg2-set2:     [SKIP][318] ([Intel XE#651]) -> [SKIP][319] ([Intel XE#2136] / [Intel XE#2351]) +26 other tests skip
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-suspend.html
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
    - shard-bmg:          [DMESG-FAIL][320] ([Intel XE#877]) -> [FAIL][321] ([Intel XE#2333])
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [FAIL][322] ([Intel XE#2333]) -> [SKIP][323] ([Intel XE#2136] / [Intel XE#2231]) +4 other tests skip
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte:
    - shard-dg2-set2:     [SKIP][324] ([Intel XE#651]) -> [SKIP][325] ([Intel XE#2136]) +49 other tests skip
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte.html
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear:
    - shard-bmg:          [SKIP][326] ([Intel XE#2311]) -> [SKIP][327] ([Intel XE#2136] / [Intel XE#2231]) +3 other tests skip
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear.html
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-dg2-set2:     [SKIP][328] ([Intel XE#658]) -> [SKIP][329] ([Intel XE#2136] / [Intel XE#2351]) +1 other test skip
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-slowdraw:
    - shard-dg2-set2:     [SKIP][330] ([Intel XE#653]) -> [SKIP][331] ([Intel XE#2136] / [Intel XE#2351]) +20 other tests skip
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-dg2-set2:     [SKIP][332] ([Intel XE#1158]) -> [SKIP][333] ([Intel XE#2136])
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][334] ([Intel XE#2313]) -> [SKIP][335] ([Intel XE#2136] / [Intel XE#2231]) +2 other tests skip
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-dg2-set2:     [SKIP][336] ([Intel XE#653]) -> [SKIP][337] ([Intel XE#2136]) +60 other tests skip
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-slowdraw.html
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-dg2-set2:     [SKIP][338] ([Intel XE#605]) -> [SKIP][339] ([Intel XE#2423] / [i915#2575])
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_getfb@getfb-reject-ccs.html
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3:
    - shard-bmg:          [FAIL][340] -> [INCOMPLETE][341] ([Intel XE#3966]) +1 other test incomplete
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-5/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3.html
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-dg2-set2:     [SKIP][342] ([Intel XE#346]) -> [SKIP][343] ([Intel XE#2136])
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-436/igt@kms_joiner@basic-big-joiner.html
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-dg2-set2:     [SKIP][344] ([Intel XE#2927]) -> [SKIP][345] ([Intel XE#2136])
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_joiner@basic-ultra-joiner.html
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-dg2-set2:     [SKIP][346] ([Intel XE#2925]) -> [SKIP][347] ([Intel XE#2136])
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-bmg:          [SKIP][348] ([Intel XE#2486]) -> [SKIP][349] ([Intel XE#3007])
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@kms_panel_fitting@legacy.html
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_cursor@primary:
    - shard-dg2-set2:     [FAIL][350] ([Intel XE#616]) -> [SKIP][351] ([Intel XE#2423] / [i915#2575])
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_plane_cursor@primary.html
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_plane_cursor@primary.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
    - shard-dg2-set2:     [SKIP][352] ([Intel XE#2763] / [Intel XE#455]) -> [SKIP][353] ([Intel XE#2423] / [i915#2575]) +1 other test skip
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
   [353]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-dg2-set2:     [SKIP][354] ([Intel XE#2938]) -> [SKIP][355] ([Intel XE#2136])
   [354]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-436/igt@kms_pm_backlight@brightness-with-dpms.html
   [355]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade:
    - shard-dg2-set2:     [SKIP][356] ([Intel XE#870]) -> [SKIP][357] ([Intel XE#2136]) +1 other test skip
   [356]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_pm_backlight@fade.html
   [357]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg2-set2:     [SKIP][358] ([Intel XE#1122]) -> [SKIP][359] ([Intel XE#2136] / [Intel XE#2351])
   [358]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [359]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2-set2:     [SKIP][360] ([Intel XE#3309]) -> [SKIP][361] ([Intel XE#2136])
   [360]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_pm_dc@dc5-retention-flops.html
   [361]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-dg2-set2:     [SKIP][362] ([Intel XE#1129]) -> [SKIP][363] ([Intel XE#2136] / [Intel XE#2351])
   [362]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_pm_dc@dc6-psr.html
   [363]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-bmg:          [SKIP][364] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836]) -> [SKIP][365] ([Intel XE#2446])
   [364]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-7/igt@kms_pm_rpm@modeset-lpsp.html
   [365]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     [SKIP][366] ([Intel XE#1489]) -> [SKIP][367] ([Intel XE#2136]) +22 other tests skip
   [366]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-436/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html
   [367]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-bmg:          [SKIP][368] ([Intel XE#1489]) -> [SKIP][369] ([Intel XE#2136] / [Intel XE#2231])
   [368]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-8/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
   [369]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-dg2-set2:     [SKIP][370] ([Intel XE#1122]) -> [SKIP][371] ([Intel XE#2136]) +1 other test skip
   [370]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_psr2_su@page_flip-nv12.html
   [371]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-dg2-set2:     [SKIP][372] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][373] ([Intel XE#2136]) +26 other tests skip
   [372]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_psr@fbc-psr2-sprite-plane-move.html
   [373]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@fbc-psr2-suspend:
    - shard-bmg:          [SKIP][374] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][375] ([Intel XE#2136] / [Intel XE#2231]) +2 other tests skip
   [374]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@kms_psr@fbc-psr2-suspend.html
   [375]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_psr@fbc-psr2-suspend.html

  * igt@kms_psr@psr-dpms:
    - shard-dg2-set2:     [SKIP][376] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][377] ([Intel XE#2136] / [Intel XE#2351]) +11 other tests skip
   [376]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_psr@psr-dpms.html
   [377]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_psr@psr-dpms.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-dg2-set2:     [SKIP][378] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][379] ([Intel XE#2351])
   [378]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_psr@psr-sprite-plane-onoff.html
   [379]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2-set2:     [SKIP][380] ([Intel XE#3414]) -> [SKIP][381] ([Intel XE#2423] / [i915#2575]) +6 other tests skip
   [380]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_rotation_crc@bad-tiling.html
   [381]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-bmg:          [SKIP][382] ([Intel XE#3414] / [Intel XE#3904]) -> [SKIP][383] ([Intel XE#3007])
   [382]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@kms_rotation_crc@primary-rotation-90.html
   [383]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2-set2:     [SKIP][384] ([Intel XE#1127]) -> [SKIP][385] ([Intel XE#2423] / [i915#2575]) +1 other test skip
   [384]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
   [385]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_setmode@basic@pipe-a-edp-1:
    - shard-lnl:          [FAIL][386] -> [FAIL][387] ([Intel XE#2883])
   [386]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-lnl-5/igt@kms_setmode@basic@pipe-a-edp-1.html
   [387]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-lnl-2/igt@kms_setmode@basic@pipe-a-edp-1.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2-set2:     [SKIP][388] ([Intel XE#362]) -> [FAIL][389] ([Intel XE#1729])
   [388]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern.html
   [389]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-434/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][390] ([Intel XE#1500]) -> [SKIP][391] ([Intel XE#2423] / [i915#2575])
   [390]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [391]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-dg2-set2:     [SKIP][392] ([Intel XE#330]) -> [SKIP][393] ([Intel XE#2423] / [i915#2575])
   [392]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@kms_tv_load_detect@load-detect.html
   [393]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@flip-dpms:
    - shard-dg2-set2:     [SKIP][394] ([Intel XE#455]) -> [SKIP][395] ([Intel XE#2423] / [i915#2575]) +22 other tests skip
   [394]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_vrr@flip-dpms.html
   [395]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_vrr@flip-dpms.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-dg2-set2:     [SKIP][396] ([Intel XE#756]) -> [SKIP][397] ([Intel XE#2423] / [i915#2575]) +1 other test skip
   [396]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@kms_writeback@writeback-invalid-parameters.html
   [397]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@xe_copy_basic@mem-copy-linear-0xfffe:
    - shard-dg2-set2:     [SKIP][398] ([Intel XE#1123]) -> [SKIP][399] ([Intel XE#1130])
   [398]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@xe_copy_basic@mem-copy-linear-0xfffe.html
   [399]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@xe_copy_basic@mem-copy-linear-0xfffe.html

  * igt@xe_copy_basic@mem-set-linear-0x3fff:
    - shard-dg2-set2:     [SKIP][400] ([Intel XE#1126]) -> [SKIP][401] ([Intel XE#1130]) +1 other test skip
   [400]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@xe_copy_basic@mem-set-linear-0x3fff.html
   [401]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0x3fff.html

  * igt@xe_eudebug@basic-vm-access-parameters-userptr:
    - shard-dg2-set2:     [SKIP][402] ([Intel XE#3889]) -> [SKIP][403] ([Intel XE#1130]) +1 other test skip
   [402]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-436/igt@xe_eudebug@basic-vm-access-parameters-userptr.html
   [403]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_eudebug@basic-vm-access-parameters-userptr.html

  * igt@xe_eudebug_online@breakpoint-not-in-debug-mode:
    - shard-bmg:          [SKIP][404] ([Intel XE#2905]) -> [SKIP][405] ([Intel XE#1130])
   [404]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-8/igt@xe_eudebug_online@breakpoint-not-in-debug-mode.html
   [405]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@xe_eudebug_online@breakpoint-not-in-debug-mode.html

  * igt@xe_evict@evict-beng-large-multi-vm-cm:
    - shard-dg2-set2:     [FAIL][406] ([Intel XE#1600]) -> [SKIP][407] ([Intel XE#1130])
   [406]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@xe_evict@evict-beng-large-multi-vm-cm.html
   [407]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_evict@evict-beng-large-multi-vm-cm.html

  * igt@xe_evict@evict-beng-mixed-many-threads-large:
    - shard-dg2-set2:     [TIMEOUT][408] ([Intel XE#1473]) -> [SKIP][409] ([Intel XE#1130])
   [408]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-large.html
   [409]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_evict@evict-beng-mixed-many-threads-large.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-dg2-set2:     [TIMEOUT][410] ([Intel XE#1473] / [Intel XE#402]) -> [INCOMPLETE][411] ([Intel XE#1473] / [Intel XE#402])
   [410]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [411]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-beng-threads-large:
    - shard-bmg:          [TIMEOUT][412] ([Intel XE#1473]) -> [FAIL][413] ([Intel XE#1000])
   [412]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-3/igt@xe_evict@evict-beng-threads-large.html
   [413]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@xe_evict@evict-beng-threads-large.html

  * igt@xe_evict@evict-mixed-many-threads-large:
    - shard-bmg:          [TIMEOUT][414] ([Intel XE#1473]) -> [INCOMPLETE][415] ([Intel XE#1473]) +1 other test incomplete
   [414]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-4/igt@xe_evict@evict-mixed-many-threads-large.html
   [415]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-large.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [TIMEOUT][416] ([Intel XE#1473] / [Intel XE#2472]) -> [INCOMPLETE][417] ([Intel XE#1473]) +2 other tests incomplete
   [416]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html
   [417]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html
    - shard-dg2-set2:     [TIMEOUT][418] ([Intel XE#1473]) -> [INCOMPLETE][419] ([Intel XE#1473]) +1 other test incomplete
   [418]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@xe_evict@evict-mixed-many-threads-small.html
   [419]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-434/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr:
    - shard-bmg:          [SKIP][420] ([Intel XE#2322]) -> [SKIP][421] ([Intel XE#1130]) +1 other test skip
   [420]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-bmg-8/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr.html
   [421]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-bmg-7/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr.html

  * igt@xe_exec_fault_mode@twice-invalid-fault:
    - shard-dg2-set2:     [SKIP][422] ([Intel XE#288]) -> [SKIP][423] ([Intel XE#1130]) +65 other tests skip
   [422]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@xe_exec_fault_mode@twice-invalid-fault.html
   [423]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_exec_fault_mode@twice-invalid-fault.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
    - shard-dg2-set2:     [SKIP][424] ([Intel XE#2360]) -> [SKIP][425] ([Intel XE#1130]) +2 other tests skip
   [424]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html
   [425]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html

  * igt@xe_exec_sip_eudebug@breakpoint-writesip:
    - shard-dg2-set2:     [SKIP][426] ([Intel XE#2905]) -> [SKIP][427] ([Intel XE#1130]) +31 other tests skip
   [426]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@xe_exec_sip_eudebug@breakpoint-writesip.html
   [427]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_exec_sip_eudebug@breakpoint-writesip.html

  * igt@xe_huc_copy@huc_copy:
    - shard-dg2-set2:     [SKIP][428] ([Intel XE#255]) -> [SKIP][429] ([Intel XE#1130])
   [428]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@xe_huc_copy@huc_copy.html
   [429]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_huc_copy@huc_copy.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-dg2-set2:     [SKIP][430] ([Intel XE#455]) -> [SKIP][431] ([Intel XE#1192])
   [430]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@xe_live_ktest@xe_eudebug.html
   [431]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_live_ktest@xe_mocs:
    - shard-dg2-set2:     [FAIL][432] ([Intel XE#1999]) -> [SKIP][433] ([Intel XE#1192])
   [432]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@xe_live_ktest@xe_mocs.html
   [433]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-434/igt@xe_live_ktest@xe_mocs.html

  * igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
    - shard-dg2-set2:     [SKIP][434] ([Intel XE#2541] / [Intel XE#3573]) -> [SKIP][435] ([Intel XE#1130]) +20 other tests skip
   [434]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html
   [435]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-435/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-dg2-set2:     [SKIP][436] ([Intel XE#979]) -> [SKIP][437] ([Intel XE#1130])
   [436]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-435/igt@xe_pat@pat-index-xelpg.html
   [437]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_peer2peer@read:
    - shard-dg2-set2:     [FAIL][438] ([Intel XE#1173]) -> [SKIP][439] ([Intel XE#1061])
   [438]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@xe_peer2peer@read.html
   [439]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_peer2peer@read.html

  * igt@xe_pm@d3cold-mocs:
    - shard-dg2-set2:     [SKIP][440] ([Intel XE#2284]) -> [SKIP][441] ([Intel XE#1130])
   [440]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@xe_pm@d3cold-mocs.html
   [441]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-dg2-set2:     [SKIP][442] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][443] ([Intel XE#1130]) +2 other tests skip
   [442]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-436/igt@xe_pm@s2idle-d3cold-basic-exec.html
   [443]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-dg2-set2:     [SKIP][444] ([Intel XE#944]) -> [SKIP][445] ([Intel XE#1130]) +5 other tests skip
   [444]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-434/igt@xe_query@multigpu-query-oa-units.html
   [445]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_query@multigpu-query-oa-units.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-dg2-set2:     [SKIP][446] ([Intel XE#3342]) -> [SKIP][447] ([Intel XE#1130])
   [446]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@xe_sriov_flr@flr-each-isolation.html
   [447]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_sriov_flr@flr-each-isolation.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-dg2-set2:     [ABORT][448] ([Intel XE#3075] / [Intel XE#3084]) -> [SKIP][449] ([Intel XE#1130])
   [448]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8174/shard-dg2-466/igt@xe_wedged@wedged-mode-toggle.html
   [449]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/shard-dg2-466/igt@xe_wedged@wedged-mode-toggle.html

  
  [Intel XE#1000]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1000
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
  [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
  [Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
  [Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1885]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1885
  [Intel XE#1999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1999
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
  [Intel XE#2141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2141
  [Intel XE#2159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2159
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2231
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2364
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
  [Intel XE#2446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2446
  [Intel XE#2472]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2472
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#3007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3007
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#3075]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3075
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#3084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3084
  [Intel XE#3088]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3088
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3157]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3157
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3249
  [Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
  [Intel XE#3279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3279
  [Intel XE#3288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3288
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3313
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3383
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#3546]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3546
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/361
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3719]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3719
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3781]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3781
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3869]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3869
  [Intel XE#3879]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3879
  [Intel XE#3889]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3889
  [Intel XE#3898]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3898
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#3918]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3918
  [Intel XE#3946]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3946
  [Intel XE#3966]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3966
  [Intel XE#402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/402
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575


Build changes
-------------

  * IGT: IGT_8174 -> IGTPW_12393
  * Linux: xe-2424-08bd590935a5258ffd79355c59adffd72fb2c642 -> xe-2440-f06efdfad9d0e9f5cb74404ac98e1a5b3b246567

  IGTPW_12393: 5ff4f2c7478a332586c48137da1a34f34ba5337d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8174: d2004b0623dbccd08502525849b4eef881aa199e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-2424-08bd590935a5258ffd79355c59adffd72fb2c642: 08bd590935a5258ffd79355c59adffd72fb2c642
  xe-2440-f06efdfad9d0e9f5cb74404ac98e1a5b3b246567: f06efdfad9d0e9f5cb74404ac98e1a5b3b246567

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12393/index.html

[-- Attachment #2: Type: text/html, Size: 131975 bytes --]

Re: [PATCH i-g-t 3/8] lib/xe: Move functions from xe_util to xe_gt

[Lucas De Marchi]

On Mon, Jan 06, 2025 at 10:58:15PM +0000, Cavitt, Jonathan wrote:
>-----Original Message-----
>From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De Marchi
>Sent: Friday, January 3, 2025 11:16 PM
>To: igt-dev@lists.freedesktop.org
>Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
>Subject: [PATCH i-g-t 3/8] lib/xe: Move functions from xe_util to xe_gt
>>
>> Some functions are clearly gt-related, so move them to xe_gt.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>LGTM, though at some point in the future, we should probably take a closer look at
>the test files that have been impacted by this change and check if xe_util.h is still a
>required includes for them.

good idea. I went ahead and did that. I will include it in v2. Since we
only include xe_util.h from *.c, that's easy:

$ git grep -l  xe_util.h | xargs sed -i '/xe_util\.h/d'
$ meson compile --ninja-args "-k 2000" -C build  2>/dev/null | grep -e "^FAILED:.*\.c\.o"
FAILED: tests/xe_copy_basic.p/intel_xe_copy_basic.c.o       
FAILED: lib/libigt-xe_xe_util_c.a.p/xe_xe_util.c.o          
FAILED: lib/libigt-intel_allocator_c.a.p/intel_allocator.c.o
FAILED: tests/xe_peer2peer.p/intel_xe_peer2peer.c.o         
FAILED: tests/xe_exercise_blt.p/intel_xe_exercise_blt.c.o   
FAILED: tests/xe_exec_store.p/intel_xe_exec_store.c.o       
FAILED: tests/xe_ccs.p/intel_xe_ccs.c.o                     
FAILED: tests/xe_pat.p/intel_xe_pat.c.o                     
FAILED: lib/libigt-intel_blt_c.a.p/intel_blt.c.o            

Then remove the changes for the ones that failed, and make sure we have
.o for the ones that succeeded (i.e. they are not guarded by build
flags).


>Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>

thanks
Lucas De Marchi

>-Jonathan Cavitt
>
>> ---
>>  lib/xe/xe_gt.c                 | 67 ++++++++++++++++++++++++++++++++++
>>  lib/xe/xe_gt.h                 |  8 ++++
>>  lib/xe/xe_util.c               | 67 ----------------------------------
>>  lib/xe/xe_util.h               |  7 ----
>>  tests/intel/xe_drm_fdinfo.c    |  2 +
>>  tests/intel/xe_exec_balancer.c |  1 +
>>  tests/intel/xe_exec_reset.c    |  1 +
>>  tests/intel/xe_exec_threads.c  |  1 +
>>  tests/intel/xe_gt_freq.c       |  1 +
>>  tests/intel/xe_pm_residency.c  |  2 +
>>  10 files changed, 83 insertions(+), 74 deletions(-)
>>
>> diff --git a/lib/xe/xe_gt.c b/lib/xe/xe_gt.c
>> index 53554beb0..e1f353b41 100644
>> --- a/lib/xe/xe_gt.c
>> +++ b/lib/xe/xe_gt.c
>> @@ -174,3 +174,70 @@ int xe_gt_stats_get_count(int fd, int gt, const char *stat)
>>
>>  	return count;
>>  }
>> +
>> +/**
>> + * xe_is_gt_in_c6:
>> + * @fd: pointer to xe drm fd
>> + * @gt: gt number
>> + *
>> + * Check if GT is in C6 state
>> + */
>> +bool xe_is_gt_in_c6(int fd, int gt)
>> +{
>> +	char gt_c_state[16];
>> +	int gt_fd;
>> +
>> +	gt_fd = xe_sysfs_gt_open(fd, gt);
>> +	igt_assert(gt_fd >= 0);
>> +	igt_assert(igt_sysfs_scanf(gt_fd, "gtidle/idle_status", "%s", gt_c_state) == 1);
>> +	close(gt_fd);
>> +
>> +	return strcmp(gt_c_state, "gt-c6") == 0;
>> +}
>> +
>> +/**
>> + * xe_gt_fill_engines_by_class:
>> + * @fd: pointer to xe drm fd
>> + * @gt: gt number
>> + * @class: engine class to use to filter engines
>> + * @eci: output argument to copy engines to
>> + *
>> + * Fill out @drm_xe_engine_class_instance with all the engines in @gt that have
>> + * a certain @class.
>> + *
>> + * Return: number of engines that match the gt and clas
>> + */
>> +int xe_gt_fill_engines_by_class(int fd, int gt, int class,
>> +				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE])
>> +{
>> +	struct drm_xe_engine_class_instance *hwe;
>> +	int n = 0;
>> +
>> +	xe_for_each_engine(fd, hwe)
>> +		if (hwe->engine_class == class && hwe->gt_id == gt)
>> +			eci[n++] = *hwe;
>> +
>> +	return n;
>> +}
>> +
>> +/**
>> + * xe_gt_count_engines_by_class:
>> + * @fd: pointer to xe drm fd
>> + * @gt: gt number
>> + * @class: engine class to use to filter engines
>> + *
>> + * Count number of engines in @gt that have a certain @class.
>> + *
>> + * Return: number of engines that match the gt and clas
>> + */
>> +int xe_gt_count_engines_by_class(int fd, int gt, int class)
>> +{
>> +	struct drm_xe_engine_class_instance *hwe;
>> +	int n = 0;
>> +
>> +	xe_for_each_engine(fd, hwe)
>> +		if (hwe->engine_class == class && hwe->gt_id == gt)
>> +			n++;
>> +
>> +	return n;
>> +}
>> diff --git a/lib/xe/xe_gt.h b/lib/xe/xe_gt.h
>> index 756b5f38e..47569cec3 100644
>> --- a/lib/xe/xe_gt.h
>> +++ b/lib/xe/xe_gt.h
>> @@ -8,6 +8,8 @@
>>
>>  #include "lib/igt_gt.h"
>>
>> +#include "xe_query.h"
>> +
>>  bool has_xe_gt_reset(int fd);
>>  void xe_force_gt_reset_all(int fd);
>>  igt_hang_t xe_hang_ring(int fd, uint64_t ahnd, uint32_t ctx, int ring,
>> @@ -15,4 +17,10 @@ igt_hang_t xe_hang_ring(int fd, uint64_t ahnd, uint32_t ctx, int ring,
>>  void xe_post_hang_ring(int fd, igt_hang_t arg);
>>  int xe_gt_stats_get_count(int fd, int gt, const char *stat);
>>
>> +bool xe_is_gt_in_c6(int fd, int gt);
>> +
>> +int xe_gt_fill_engines_by_class(int fd, int gt, int class,
>> +				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE]);
>> +int xe_gt_count_engines_by_class(int fd, int gt, int class);
>> +
>>  #endif
>> diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
>> index 9482819c2..f0b6bbb2d 100644
>> --- a/lib/xe/xe_util.c
>> +++ b/lib/xe/xe_util.c
>> @@ -235,70 +235,3 @@ void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine,
>>
>>  	free(bind_ops);
>>  }
>> -
>> -/**
>> - * xe_is_gt_in_c6:
>> - * @fd: pointer to xe drm fd
>> - * @gt: gt number
>> - *
>> - * Check if GT is in C6 state
>> - */
>> -bool xe_is_gt_in_c6(int fd, int gt)
>> -{
>> -	char gt_c_state[16];
>> -	int gt_fd;
>> -
>> -	gt_fd = xe_sysfs_gt_open(fd, gt);
>> -	igt_assert(gt_fd >= 0);
>> -	igt_assert(igt_sysfs_scanf(gt_fd, "gtidle/idle_status", "%s", gt_c_state) == 1);
>> -	close(gt_fd);
>> -
>> -	return strcmp(gt_c_state, "gt-c6") == 0;
>> -}
>> -
>> -/**
>> - * xe_gt_fill_engines_by_class:
>> - * @fd: pointer to xe drm fd
>> - * @gt: gt number
>> - * @class: engine class to use to filter engines
>> - * @eci: output argument to copy engines to
>> - *
>> - * Fill out @drm_xe_engine_class_instance with all the engines in @gt that have
>> - * a certain @class.
>> - *
>> - * Return: number of engines that match the gt and clas
>> - */
>> -int xe_gt_fill_engines_by_class(int fd, int gt, int class,
>> -				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE])
>> -{
>> -	struct drm_xe_engine_class_instance *hwe;
>> -	int n = 0;
>> -
>> -	xe_for_each_engine(fd, hwe)
>> -		if (hwe->engine_class == class && hwe->gt_id == gt)
>> -			eci[n++] = *hwe;
>> -
>> -	return n;
>> -}
>> -
>> -/**
>> - * xe_gt_count_engines_by_class:
>> - * @fd: pointer to xe drm fd
>> - * @gt: gt number
>> - * @class: engine class to use to filter engines
>> - *
>> - * Count number of engines in @gt that have a certain @class.
>> - *
>> - * Return: number of engines that match the gt and clas
>> - */
>> -int xe_gt_count_engines_by_class(int fd, int gt, int class)
>> -{
>> -	struct drm_xe_engine_class_instance *hwe;
>> -	int n = 0;
>> -
>> -	xe_for_each_engine(fd, hwe)
>> -		if (hwe->engine_class == class && hwe->gt_id == gt)
>> -			n++;
>> -
>> -	return n;
>> -}
>> diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
>> index b9fbfc5cd..c544d912f 100644
>> --- a/lib/xe/xe_util.h
>> +++ b/lib/xe/xe_util.h
>> @@ -47,11 +47,4 @@ void xe_bind_unbind_async(int fd, uint32_t vm, uint32_t bind_engine,
>>  			  struct igt_list_head *obj_list,
>>  			  uint32_t sync_in, uint32_t sync_out);
>>
>> -bool xe_is_gt_in_c6(int fd, int gt);
>> -
>> -int xe_gt_fill_engines_by_class(int fd, int gt, int class,
>> -				struct drm_xe_engine_class_instance eci[static XE_MAX_ENGINE_INSTANCE]);
>> -int xe_gt_count_engines_by_class(int fd, int gt, int class);
>> -
>> -
>>  #endif /* XE_UTIL_H */
>> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
>> index 6549629b4..f4264aadb 100644
>> --- a/tests/intel/xe_drm_fdinfo.c
>> +++ b/tests/intel/xe_drm_fdinfo.c
>> @@ -8,7 +8,9 @@
>>  #include "igt_device.h"
>>  #include "igt_drm_fdinfo.h"
>>  #include "lib/igt_syncobj.h"
>> +
>>  #include "xe_drm.h"
>> +#include "xe/xe_gt.h"
>>  #include "xe/xe_ioctl.h"
>>  #include "xe/xe_query.h"
>>  #include "xe/xe_spin.h"
>> diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c
>> index 1e552e9ef..f2df5cbec 100644
>> --- a/tests/intel/xe_exec_balancer.c
>> +++ b/tests/intel/xe_exec_balancer.c
>> @@ -19,6 +19,7 @@
>>  #include "lib/intel_reg.h"
>>  #include "xe_drm.h"
>>
>> +#include "xe/xe_gt.h"
>>  #include "xe/xe_ioctl.h"
>>  #include "xe/xe_query.h"
>>  #include "xe/xe_spin.h"
>> diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
>> index a3eaf8bbf..47c7666df 100644
>> --- a/tests/intel/xe_exec_reset.c
>> +++ b/tests/intel/xe_exec_reset.c
>> @@ -21,6 +21,7 @@
>>
>>  #include "xe/xe_ioctl.h"
>>  #include "xe/xe_query.h"
>> +#include "xe/xe_gt.h"
>>  #include "xe/xe_spin.h"
>>  #include "xe/xe_util.h"
>>  #include <string.h>
>> diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c
>> index 661117bed..c8fc17366 100644
>> --- a/tests/intel/xe_exec_threads.c
>> +++ b/tests/intel/xe_exec_threads.c
>> @@ -21,6 +21,7 @@
>>
>>  #include "xe/xe_ioctl.h"
>>  #include "xe/xe_query.h"
>> +#include "xe/xe_gt.h"
>>  #include "xe/xe_spin.h"
>>  #include "xe/xe_util.h"
>>  #include <string.h>
>> diff --git a/tests/intel/xe_gt_freq.c b/tests/intel/xe_gt_freq.c
>> index de4d111ea..5d806cf15 100644
>> --- a/tests/intel/xe_gt_freq.c
>> +++ b/tests/intel/xe_gt_freq.c
>> @@ -17,6 +17,7 @@
>>  #include "igt_sysfs.h"
>>
>>  #include "xe_drm.h"
>> +#include "xe/xe_gt.h"
>>  #include "xe/xe_ioctl.h"
>>  #include "xe/xe_spin.h"
>>  #include "xe/xe_query.h"
>> diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
>> index d4b26b231..18e5cb6c3 100644
>> --- a/tests/intel/xe_pm_residency.c
>> +++ b/tests/intel/xe_pm_residency.c
>> @@ -21,7 +21,9 @@
>>  #include "igt_sysfs.h"
>>
>>  #include "lib/igt_syncobj.h"
>> +
>>  #include "xe/xe_ioctl.h"
>> +#include "xe/xe_gt.h"
>>  #include "xe/xe_query.h"
>>  #include "xe/xe_util.h"
>>
>> --
>> 2.47.0
>>
>>

Re: [PATCH i-g-t 6/8] lib/xe/xe_spin: Move declarations around

[Lucas De Marchi]

On Mon, Jan 06, 2025 at 10:58:26PM +0000, Cavitt, Jonathan wrote:
>-----Original Message-----
>From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De Marchi
>Sent: Friday, January 3, 2025 11:16 PM
>To: igt-dev@lists.freedesktop.org
>Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
>Subject: [PATCH i-g-t 6/8] lib/xe/xe_spin: Move declarations around
>>
>> xe_spin.h has 3 abstractions:
>>
>> 1) the integration with igt_dummyload
>> 2) xe_spin, the bo to be exec'ed somewhere
>> 3) xe_cork, that resembles more the igt_spin, abstracting the fd, vm,
>>    bind, etc
>>
>> Group them so it's easier to understand each one.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>Okay, I think I get it.  We're bundling the various functions declared in xe_spin.h
>by their purpose/interaction with the various structures, yeah?  That makes sense
>to me.

yes. We could also use separate headers for each of them, but they are
so related and in a small number that I felt it's ok to leave in the
same header.


>And even if my understanding of the purpose of this patch is wrong, I don't see
>any harm in applying it, so:
>Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>

thanks
Lucas De Marchi

Re: [PATCH i-g-t 8/8] tests/intel/xe_drm_fdinfo: Stop asserting on usage percentage

[Lucas De Marchi]

On Mon, Jan 06, 2025 at 10:58:34PM +0000, Cavitt, Jonathan wrote:
>-----Original Message-----
>From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De Marchi
>Sent: Friday, January 3, 2025 11:16 PM
>To: igt-dev@lists.freedesktop.org
>Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; Nerlige Ramappa, Umesh <umesh.nerlige.ramappa@intel.com>
>Subject: [PATCH i-g-t 8/8] tests/intel/xe_drm_fdinfo: Stop asserting on usage percentage
>>
>> It's unreliable to assert on the usage percentage considering 2 data
>> points as it still depends on the CPU scheduling not preempting tasks in
>> the wrong moment. On a normal use case of a top-like application, the
>> value not accounted for would simply show up in the next sample without
>> much issue. For a test assertion, it's better to check that the value
>> reported via fdinfo is reasonably close to the one saved by the GPU in
>> the spin. It's still allowed some error because there are a few GPU
>> ticks of difference due to the **GPU** scheduling the contexts.
>>
>> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>There's a few nits/questions below, but I trust that everything is in
>order, so nothing below is particularly blocking.  If I did manage to
>catch something that needs fixing, then of course that should be
>fixed, but otherwise:
>Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>
>> ---
>>  tests/intel/xe_drm_fdinfo.c | 49 +++++++++++++++++++++++--------------
>>  1 file changed, 31 insertions(+), 18 deletions(-)
>>
>> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
>> index 1089e5119..120436fbe 100644
>> --- a/tests/intel/xe_drm_fdinfo.c
>> +++ b/tests/intel/xe_drm_fdinfo.c
>> @@ -3,6 +3,8 @@
>>   * Copyright (c) 2023 Intel Corporation
>>   */
>>
>> +#include <math.h>
>> +
>>  #include "igt.h"
>>  #include "igt_core.h"
>>  #include "igt_device.h"
>> @@ -371,7 +373,8 @@ static void basic_engine_utilization(int xe)
>>
>>  static void
>>  check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>> -	      int class, int width, enum expected_load expected_load)
>> +	      int class, int width, uint32_t spin_stamp,
>> +	      enum expected_load expected_load)
>>  {
>>  	double percent;
>>  	u64 den, num;
>> @@ -383,12 +386,9 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>>
>>  	num = s2[class].cycles - s1[class].cycles;
>>  	den = s2[class].total_cycles - s1[class].total_cycles;
>> -	percent = (num * 100.0) / (den + 1);
>> -
>> -	/* for parallel submission scale the busyness with width */
>> -	percent /= width;
>>
>> -	igt_debug("%s: percent: %f\n", engine_map[class], percent);
>> +	percent = (num * 100.0) / (den + 1) / width;
>
>Nit:
>There's probably an argument to be made that we didn't need to modify
>the calculation here because the end result is still the same and it loses
>a (presumably) helpful comment, but I won't block on it.

ok, adding that back

>
>Also, is this percentage correct given the test modifications?
>Maybe we should be dividing by spin_stamp + 1 instead, since that's what
>we're using to calculate the percentage later?

nah.. there are 2 percentages here. This one I decided to leave as a
debug print... it's still useful to check we are ~100% utilization. I
just don't want the test to assert that anymore as it's noisy when there
are things disrupting the test execution.

>
>> +	igt_debug("%s: percent: %.2f%%\n", engine_map[class], percent);
>>
>>  	switch (expected_load) {
>>  	case EXPECTED_LOAD_IDLE:
>> @@ -396,11 +396,12 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>>  		break;
>>  	case EXPECTED_LOAD_FULL:
>>  		/*
>> -		 * We are still relying on CPU sleep time and there could be
>> -		 * some imprecision when calculating the load. Use a 5% margin.
>> +		 * percentage error between value saved by gpu in xe_spin and what
>> +		 * is reported via fdinfo
>
>Nit:
>s/percentage/Percentage
>
>>  		 */
>> -		igt_assert_lt_double(95.0, percent);
>> -		igt_assert_lt_double(percent, 105.0);
>> +		percent = fabs((num - spin_stamp) * 100.0) / (spin_stamp + 1);
>
>Nit:
>Shouldn't we also be dividing by width here?  I'm just asking because that's

actually spin_stamp should be multiplied by width, which should also
fix the errors reported by CI - I happened to test it only on machines
that had 1 CCS so didn't reproduce any issue on virtual/parallel. My
bad.  I'm adding a fix and sending as v2.

thanks
Lucas De Marchi

>what we were doing before, and it looks like spin_stamp is being used here
>as a stand-in for the "den" variable in the earlier percent calculation.
>
>> +		igt_debug("%s: error: %.2f%%\n", engine_map[class], percent);
>> +		igt_assert_lt_double(percent, 5.0);
>>  		break;
>>  	}
>>  }
>> @@ -438,14 +439,17 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>>
>>  	expected_load = flags & TEST_BUSY ?
>>  	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
>> -	check_results(pceu1[0], pceu2[0], hwe->engine_class, 1, expected_load);
>> +
>> +	check_results(pceu1[0], pceu2[0], hwe->engine_class, 1,
>> +		      cork ? cork->spin->timestamp : 0, expected_load);
>>
>>  	if (flags & TEST_ISOLATION) {
>>  		/*
>>  		 * Load from one client shouldn't spill on another,
>>  		 * so check for idle
>>  		 */
>> -		check_results(pceu1[1], pceu2[1], hwe->engine_class, 1, EXPECTED_LOAD_IDLE);
>> +		check_results(pceu1[1], pceu2[1], hwe->engine_class, 1, 0,
>> +			      EXPECTED_LOAD_IDLE);
>>  		close(new_fd);
>>  	}
>>
>> @@ -461,6 +465,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>  	struct xe_cork *cork;
>> +	uint32_t timestamp;
>>  	uint32_t vm;
>>
>>  	vm = xe_vm_create(fd, 0, 0);
>> @@ -472,13 +477,15 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>>
>>  	/* destroy queue before sampling again */
>>  	xe_cork_sync_end(fd, cork);
>> +	timestamp = cork->spin->timestamp;
>>  	xe_cork_destroy(fd, cork);
>>
>>  	read_engine_cycles(fd, pceu2);
>>
>>  	xe_vm_destroy(fd, vm);
>>
>> -	check_results(pceu1, pceu2, hwe->engine_class, 1, EXPECTED_LOAD_FULL);
>> +	check_results(pceu1, pceu2, hwe->engine_class, 1, timestamp,
>> +		      EXPECTED_LOAD_FULL);
>>  }
>>
>>  static void
>> @@ -503,7 +510,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>>  		enum expected_load expected_load = hwe->engine_class != class ?
>>  			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
>>
>> -		check_results(pceu1, pceu2, class, 1, expected_load);
>> +		check_results(pceu1, pceu2, class, 1, cork->spin->timestamp,
>> +			      expected_load);
>>  	}
>>
>>  	xe_cork_destroy(fd, cork);
>> @@ -547,7 +555,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>>  		if (!cork[class])
>>  			continue;
>>
>> -		check_results(pceu1, pceu2, class, 1, expected_load);
>> +		check_results(pceu1, pceu2, class, 1, cork[class]->spin->timestamp,
>> +			      expected_load);
>>  		xe_cork_destroy(fd, cork[class]);
>>  	}
>>
>> @@ -585,7 +594,9 @@ utilization_all_full_load(int fd)
>>  		if (!cork[class])
>>  			continue;
>>
>> -		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
>> +		check_results(pceu1, pceu2, class, 1,
>> +			      cork[class]->spin->timestamp,
>> +			      EXPECTED_LOAD_FULL);
>>  		xe_cork_destroy(fd, cork[class]);
>>  	}
>>
>> @@ -657,14 +668,16 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>>
>>  	expected_load = flags & TEST_BUSY ?
>>  	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
>> -	check_results(pceu[0], pceu[1], class, width, expected_load);
>> +
>> +	check_results(pceu[0], pceu[1], class, width,
>> +		      cork ? cork->spin->timestamp : 0, expected_load);
>>
>>  	if (flags & TEST_ISOLATION) {
>>  		/*
>>  		 * Load from one client shouldn't spill on another,
>>  		 * so check for idle
>>  		 */
>> -		check_results(pceu_spill[0], pceu_spill[1], class, width,
>> +		check_results(pceu_spill[0], pceu_spill[1], class, width, 0,
>>  			      EXPECTED_LOAD_IDLE);
>>  		close(fd_spill);
>>  	}
>> --
>> 2.47.0
>>
>>