Re: [PATCH] lib/pciids: Sync pci id changes for DG2/MTL/BMG/PTL

[Matt Roper <matthew.d.roper@intel.com>]

On Thu, Feb 06, 2025 at 09:06:32AM -0800, Matt Atwood wrote:
> On Wed, Feb 05, 2025 at 03:30:55PM -0800, Matt Roper wrote:
> > On Tue, Feb 04, 2025 at 09:53:02AM -0800, Matt Atwood wrote:
> > > There have been several changes to pciids upstream that need to be
> > > sync'd into igt.
> > > 
> > > Sync with the following kernel commits:
> > > f9a15b968dce ("drm/intel/pciids: Refactor DG2 PCI IDs into segment
> > > ranges")
> > > e35ecd95ecf2 ("drm/i915/display: Add MTL subplatforms definition")
> > > fa8ffaae1b15 ("drm/xe/bmg: Add new PCI IDs")
> > > 16016ade13f6 ("drm/xe/ptl: Update the PTL pci id table")
> > 
> > The updates below look correct (they match the kernel header), but the
> > commit message here is confusing.  IGT updates to this file generally
> > specify which actual kernel commit you're synchronizing against; none of
> > the four listed above match the content you've copied here because there
> > are additional changes not present in those.
> Because there are now several out of sync next branches, saying as
> of this commit idea was not working. Hence this approach.

You should generally be syncing with drm-next after things land there.
So which drm-next commit are you syncing with for this commit?


Matt

> 
> MattA
> > 
> > 
> > Matt
> > 
> > > 
> > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > ---
> > >  lib/pciids.h | 62 +++++++++++++++++++++++++++++++++++++++-------------
> > >  1 file changed, 47 insertions(+), 15 deletions(-)
> > > 
> > > diff --git a/lib/pciids.h b/lib/pciids.h
> > > index 23f349f65..4736ea525 100644
> > > --- a/lib/pciids.h
> > > +++ b/lib/pciids.h
> > > @@ -717,37 +717,66 @@
> > >  	MACRO__(0xA7AB, ## __VA_ARGS__)
> > >  
> > >  /* DG2 */
> > > -#define INTEL_DG2_G10_IDS(MACRO__, ...) \
> > > -	MACRO__(0x5690, ## __VA_ARGS__), \
> > > -	MACRO__(0x5691, ## __VA_ARGS__), \
> > > -	MACRO__(0x5692, ## __VA_ARGS__), \
> > > +#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \
> > >  	MACRO__(0x56A0, ## __VA_ARGS__), \
> > >  	MACRO__(0x56A1, ## __VA_ARGS__), \
> > > -	MACRO__(0x56A2, ## __VA_ARGS__), \
> > > +	MACRO__(0x56A2, ## __VA_ARGS__)
> > > +
> > > +#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \
> > >  	MACRO__(0x56BE, ## __VA_ARGS__), \
> > >  	MACRO__(0x56BF, ## __VA_ARGS__)
> > >  
> > > -#define INTEL_DG2_G11_IDS(MACRO__, ...) \
> > > -	MACRO__(0x5693, ## __VA_ARGS__), \
> > > -	MACRO__(0x5694, ## __VA_ARGS__), \
> > > -	MACRO__(0x5695, ## __VA_ARGS__), \
> > > +#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \
> > > +	MACRO__(0x5690, ## __VA_ARGS__), \
> > > +	MACRO__(0x5691, ## __VA_ARGS__), \
> > > +	MACRO__(0x5692, ## __VA_ARGS__)
> > > +
> > > +#define INTEL_DG2_G10_IDS(MACRO__, ...) \
> > > +	INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
> > > +	INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \
> > > +	INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__)
> > > +
> > > +#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \
> > >  	MACRO__(0x56A5, ## __VA_ARGS__), \
> > >  	MACRO__(0x56A6, ## __VA_ARGS__), \
> > >  	MACRO__(0x56B0, ## __VA_ARGS__), \
> > > -	MACRO__(0x56B1, ## __VA_ARGS__), \
> > > +	MACRO__(0x56B1, ## __VA_ARGS__)
> > > +
> > > +#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \
> > >  	MACRO__(0x56BA, ## __VA_ARGS__), \
> > >  	MACRO__(0x56BB, ## __VA_ARGS__), \
> > >  	MACRO__(0x56BC, ## __VA_ARGS__), \
> > >  	MACRO__(0x56BD, ## __VA_ARGS__)
> > >  
> > > -#define INTEL_DG2_G12_IDS(MACRO__, ...) \
> > > -	MACRO__(0x5696, ## __VA_ARGS__), \
> > > -	MACRO__(0x5697, ## __VA_ARGS__), \
> > > +#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \
> > > +	MACRO__(0x5693, ## __VA_ARGS__), \
> > > +	MACRO__(0x5694, ## __VA_ARGS__), \
> > > +	MACRO__(0x5695, ## __VA_ARGS__)
> > > +
> > > +#define INTEL_DG2_G11_IDS(MACRO__, ...) \
> > > +	INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
> > > +	INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \
> > > +	INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__)
> > > +
> > > +#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \
> > >  	MACRO__(0x56A3, ## __VA_ARGS__), \
> > >  	MACRO__(0x56A4, ## __VA_ARGS__), \
> > >  	MACRO__(0x56B2, ## __VA_ARGS__), \
> > >  	MACRO__(0x56B3, ## __VA_ARGS__)
> > >  
> > > +#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \
> > > +	MACRO__(0x5696, ## __VA_ARGS__), \
> > > +	MACRO__(0x5697, ## __VA_ARGS__)
> > > +
> > > +#define INTEL_DG2_G12_IDS(MACRO__, ...) \
> > > +	INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \
> > > +	INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__)
> > > +
> > > +#define INTEL_DG2_D_IDS(MACRO__, ...) \
> > > +	INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
> > > +	INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
> > > +	INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__)
> > > +
> > >  #define INTEL_DG2_IDS(MACRO__, ...) \
> > >  	INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
> > >  	INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
> > > @@ -782,9 +811,12 @@
> > >  	INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__)
> > >  
> > >  /* MTL */
> > > -#define INTEL_MTL_IDS(MACRO__, ...) \
> > > +#define INTEL_MTL_U_IDS(MACRO__, ...) \
> > >  	MACRO__(0x7D40, ## __VA_ARGS__), \
> > > -	MACRO__(0x7D45, ## __VA_ARGS__), \
> > > +	MACRO__(0x7D45, ## __VA_ARGS__)
> > > +
> > > +#define INTEL_MTL_IDS(MACRO__, ...) \
> > > +	INTEL_MTL_U_IDS(MACRO__, ## __VA_ARGS__), \
> > >  	MACRO__(0x7D55, ## __VA_ARGS__), \
> > >  	MACRO__(0x7D60, ## __VA_ARGS__), \
> > >  	MACRO__(0x7DD5, ## __VA_ARGS__)
> > > -- 
> > > 2.45.0
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation