From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Matt Atwood <matthew.s.atwood@intel.com>
Cc: <igt-dev@lists.freedesktop.org>
Subject: Re: [PATCH] lib/pciids: Sync pci id changes for DG2/MTL/BMG/PTL
Date: Tue, 4 Feb 2025 13:16:20 -0500 [thread overview]
Message-ID: <Z6JZdGTnucfiqC6P@intel.com> (raw)
In-Reply-To: <20250204175302.18147-1-matthew.s.atwood@intel.com>
On Tue, Feb 04, 2025 at 09:53:02AM -0800, Matt Atwood wrote:
> There have been several changes to pciids upstream that need to be
> sync'd into igt.
>
> Sync with the following kernel commits:
> f9a15b968dce ("drm/intel/pciids: Refactor DG2 PCI IDs into segment
> ranges")
> e35ecd95ecf2 ("drm/i915/display: Add MTL subplatforms definition")
> fa8ffaae1b15 ("drm/xe/bmg: Add new PCI IDs")
> 16016ade13f6 ("drm/xe/ptl: Update the PTL pci id table")
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> lib/pciids.h | 62 +++++++++++++++++++++++++++++++++++++++-------------
> 1 file changed, 47 insertions(+), 15 deletions(-)
>
> diff --git a/lib/pciids.h b/lib/pciids.h
> index 23f349f65..4736ea525 100644
> --- a/lib/pciids.h
> +++ b/lib/pciids.h
> @@ -717,37 +717,66 @@
> MACRO__(0xA7AB, ## __VA_ARGS__)
>
> /* DG2 */
> -#define INTEL_DG2_G10_IDS(MACRO__, ...) \
> - MACRO__(0x5690, ## __VA_ARGS__), \
> - MACRO__(0x5691, ## __VA_ARGS__), \
> - MACRO__(0x5692, ## __VA_ARGS__), \
> +#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \
> MACRO__(0x56A0, ## __VA_ARGS__), \
> MACRO__(0x56A1, ## __VA_ARGS__), \
> - MACRO__(0x56A2, ## __VA_ARGS__), \
> + MACRO__(0x56A2, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \
> MACRO__(0x56BE, ## __VA_ARGS__), \
> MACRO__(0x56BF, ## __VA_ARGS__)
>
> -#define INTEL_DG2_G11_IDS(MACRO__, ...) \
> - MACRO__(0x5693, ## __VA_ARGS__), \
> - MACRO__(0x5694, ## __VA_ARGS__), \
> - MACRO__(0x5695, ## __VA_ARGS__), \
> +#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \
> + MACRO__(0x5690, ## __VA_ARGS__), \
> + MACRO__(0x5691, ## __VA_ARGS__), \
> + MACRO__(0x5692, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G10_IDS(MACRO__, ...) \
> + INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \
> MACRO__(0x56A5, ## __VA_ARGS__), \
> MACRO__(0x56A6, ## __VA_ARGS__), \
> MACRO__(0x56B0, ## __VA_ARGS__), \
> - MACRO__(0x56B1, ## __VA_ARGS__), \
> + MACRO__(0x56B1, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \
> MACRO__(0x56BA, ## __VA_ARGS__), \
> MACRO__(0x56BB, ## __VA_ARGS__), \
> MACRO__(0x56BC, ## __VA_ARGS__), \
> MACRO__(0x56BD, ## __VA_ARGS__)
>
> -#define INTEL_DG2_G12_IDS(MACRO__, ...) \
> - MACRO__(0x5696, ## __VA_ARGS__), \
> - MACRO__(0x5697, ## __VA_ARGS__), \
> +#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \
> + MACRO__(0x5693, ## __VA_ARGS__), \
> + MACRO__(0x5694, ## __VA_ARGS__), \
> + MACRO__(0x5695, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G11_IDS(MACRO__, ...) \
> + INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \
> MACRO__(0x56A3, ## __VA_ARGS__), \
> MACRO__(0x56A4, ## __VA_ARGS__), \
> MACRO__(0x56B2, ## __VA_ARGS__), \
> MACRO__(0x56B3, ## __VA_ARGS__)
>
> +#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \
> + MACRO__(0x5696, ## __VA_ARGS__), \
> + MACRO__(0x5697, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G12_IDS(MACRO__, ...) \
> + INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_D_IDS(MACRO__, ...) \
> + INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__)
> +
> #define INTEL_DG2_IDS(MACRO__, ...) \
> INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
> INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
> @@ -782,9 +811,12 @@
> INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__)
>
> /* MTL */
> -#define INTEL_MTL_IDS(MACRO__, ...) \
> +#define INTEL_MTL_U_IDS(MACRO__, ...) \
> MACRO__(0x7D40, ## __VA_ARGS__), \
> - MACRO__(0x7D45, ## __VA_ARGS__), \
> + MACRO__(0x7D45, ## __VA_ARGS__)
> +
> +#define INTEL_MTL_IDS(MACRO__, ...) \
> + INTEL_MTL_U_IDS(MACRO__, ## __VA_ARGS__), \
> MACRO__(0x7D55, ## __VA_ARGS__), \
> MACRO__(0x7D60, ## __VA_ARGS__), \
> MACRO__(0x7DD5, ## __VA_ARGS__)
> --
> 2.45.0
>
next prev parent reply other threads:[~2025-02-04 18:16 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-04 17:53 [PATCH] lib/pciids: Sync pci id changes for DG2/MTL/BMG/PTL Matt Atwood
2025-02-04 18:16 ` Rodrigo Vivi [this message]
2025-02-05 1:14 ` ✓ Xe.CI.BAT: success for " Patchwork
2025-02-05 1:15 ` ✓ i915.CI.BAT: " Patchwork
2025-02-05 7:05 ` ✗ Xe.CI.Full: failure " Patchwork
2025-02-05 9:13 ` ✗ i915.CI.Full: " Patchwork
2025-02-05 23:30 ` [PATCH] " Matt Roper
2025-02-06 17:06 ` Matt Atwood
2025-02-06 18:01 ` Matt Roper
2025-02-06 19:26 ` Matt Atwood
2025-02-06 19:35 ` Rodrigo Vivi
2025-02-06 19:44 ` Matt Roper
2025-02-07 21:04 ` Lucas De Marchi
2025-02-10 17:44 ` Rodrigo Vivi
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