[PATCH i-g-t 0/6] Multi-tile support for xe_sriov_flr and related MMIO improvements

[PATCH i-g-t 0/6] Multi-tile support for xe_sriov_flr and related MMIO improvements

[Marcin Bernatowicz]

This series builds on Piotr Piórkowski’s v2 of the tile-aware VF FLR
test (see [1]) and reworks xe_sriov_flr test.

Main updates:
 - Move shared helper logic to lib/xe_query (tile helpers)
 - Refactor xe_sriov_flr test to use per-tile subchecks
 - Use proper MMIO initialization helpers (xe_mmio)
 - Keep verify_flr() template intact while isolating per-tile data
 - Simplify MMIO initialization/cleanup
 - Mark failed prerequisites to ensure CI detects them

Thanks to Piotr for the groundwork and earlier revisions.

[1] https://patchwork.freedesktop.org/series/156216/ 

v2: 
 - Drop misleading GT-oriented helpers (Lukasz)
 - Add missing colon in xe_tiles_count function doc (Lukasz)
 - Use xe_mmio_tile_read32; update patch 4/6 title; fix extra space (Piotr)
 - Switch num_vfs to unsigned int in struct g_mmio (Piotr)

Marcin Bernatowicz (3):
  tests/intel/xe_sriov_flr: Make subchecks Tile aware
  tests/intel/xe_sriov_flr: Use global MMIO context initialized in
    verify_flr
  tests/intel/xe_sriov_flr: Do not ignore failed prerequisites

Piotr Piórkowski (3):
  lib/xe_mmio: Introduce tile-level XE MMIO access helpers
  lib/xe_mmio: Add init flag and helper to check initialization
  lib/xe/xe_query: Add tile helpers and iteration macro

 lib/xe/xe_mmio.c               |  92 +++++----
 lib/xe/xe_mmio.h               |  15 +-
 lib/xe/xe_query.c              |  45 ++++
 lib/xe/xe_query.h              |   6 +
 lib/xe/xe_sriov_provisioning.c |   6 +-
 lib/xe/xe_sriov_provisioning.h |   2 +-
 tests/intel/xe_sriov_flr.c     | 365 ++++++++++++++++++---------------
 7 files changed, 312 insertions(+), 219 deletions(-)

-- 
2.43.0

[PATCH i-g-t 1/6] lib/xe_mmio: Introduce tile-level XE MMIO access helpers

[Marcin Bernatowicz]

From: Piotr Piórkowski <piotr.piorkowski@intel.com>

Add new helpers for tile-based MMIO access:
 - xe_mmio_tile_read32()
 - xe_mmio_tile_read64()
 - xe_mmio_tile_write32()
 - xe_mmio_tile_write64()

These functions provide explicit MMIO read/write operations within
a given tile by applying TILE_MMIO_SIZE offsetting logic.
GGTT is also a per-tile resource, so let's adjust the GGTT access
helpers to use tile IDs instead of GT.

v2:
 - find the real tile based on gt instead of assuming root tile
v3:
 - drop misleading GT-oriented helpers (Lukasz)

Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Jan Sokolowski <jan.sokolowski@intel.com>
---
 lib/xe/xe_mmio.c               | 78 ++++++++++++++++------------------
 lib/xe/xe_mmio.h               | 13 +++---
 lib/xe/xe_sriov_provisioning.c |  6 +--
 lib/xe/xe_sriov_provisioning.h |  2 +-
 tests/intel/xe_sriov_flr.c     | 12 +++---
 5 files changed, 52 insertions(+), 59 deletions(-)

diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
index 834816133..b52e90dba 100644
--- a/lib/xe/xe_mmio.c
+++ b/lib/xe/xe_mmio.c
@@ -107,94 +107,88 @@ void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val)
 	return iowrite64(mmio->intel_mmio.igt_mmio, offset, val);
 }
 
-/**
- * xe_mmio_gt_read32:
+/** xe_mmio_tile_read32:
  * @mmio: xe mmio structure for IO operations
- * @gt: gt id
- * @offset: mmio register offset in tile to which @gt belongs
+ * @tile: tile id
+ * @offset: mmio register offset in the tile
  *
- * 32-bit read of the register at @offset in tile to which @gt belongs.
+ * 32-bit read of the register at @offset in the specified @tile
  *
- * Returns:
- * The value read from the register.
+ * Returns: The value read from the register.
  */
-uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset)
+uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
 {
-	return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
+	return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * tile));
 }
 
-/**
- * xe_mmio_gt_read64:
+/** xe_mmio_tile_read64:
  * @mmio: xe mmio structure for IO operations
- * @gt: gt id
- * @offset: mmio register offset in tile to which @gt belongs
+ * @tile: tile id
+ * @offset: mmio register offset in the @tile
  *
- * 64-bit read of the register at @offset in tile to which @gt belongs.
+ * 64-bit read of the register at @offset in the specified @tile
  *
- * Returns:
- * The value read from the register.
+ * Returns: The value read from the register.
  */
-uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset)
+uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
 {
-	return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
+	return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * tile));
 }
 
 /**
- * xe_mmio_gt_write32:
+ * xe_mmio_tile_write32:
  * @mmio: xe mmio structure for IO operations
- * @gt: gt id
- * @offset: mmio register offset
+ * @tile: tile id
+ * @offset: mmio register offset in the @tile
  * @val: value to write
  *
- * 32-bit write to the register at @offset in tile to which @gt belongs.
+ * 32-bit write to the register at @offset in the specified @tile
  */
-void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val)
+void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint32_t val)
 {
-	return xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
-			       val);
+	xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * tile), val);
 }
 
 /**
- * xe_mmio_gt_write64:
+ * xe_mmio_tile_write64:
  * @mmio: xe mmio structure for IO operations
- * @gt: gt id
- * @offset: mmio register offset
+ * @tile: tile id
+ * @offset: mmio register offset in the @tile
  * @val: value to write
  *
- * 64-bit write to the register at @offset in tile to which @gt belongs.
+ * 64-bit write to the register at @offset in the specified @tile
  */
-void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val)
+void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint64_t val)
 {
-	return xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
-			       val);
+	xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * tile), val);
 }
 
 /**
  * xe_mmio_ggtt_read:
  * @mmio: xe mmio structure for IO operations
- * @gt: gt id
- * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
+ * @tile: tile id
+ * @offset: PTE offset from the beginning of GGTT in @tile
  *
- * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
+ * Read of GGTT PTE at GGTT @offset in the @tile.
  *
  * Returns:
  * The value read from the register.
  */
-xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t offset)
+xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
 {
-	return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
+	return xe_mmio_tile_read64(mmio, tile, offset + GGTT_OFFSET_IN_TILE);
 }
 
 /**
  * xe_mmio_ggtt_write:
  * @mmio: xe mmio structure for IO operations
- * @gt: gt id
- * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
+ * @tile: tile id
+ * @offset: PTE offset from the beginning of GGTT in @tile
  * @pte: PTE value to write
  *
- * Write PTE value at GGTT @offset in tile to which @gt belongs.
+ * Write PTE value at GGTT @offset in the @tile.
  */
-void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset, xe_ggtt_pte_t pte)
+void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, xe_ggtt_pte_t pte)
 {
-	return xe_mmio_gt_write64(mmio, gt, offset + GGTT_OFFSET_IN_TILE, pte);
+	return xe_mmio_tile_write64(mmio, tile, offset + GGTT_OFFSET_IN_TILE, pte);
 }
diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
index f144d4b53..35cafa448 100644
--- a/lib/xe/xe_mmio.h
+++ b/lib/xe/xe_mmio.h
@@ -29,13 +29,12 @@ uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t offset);
 void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, uint32_t val);
 void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val);
 
-uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset);
-uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset);
+uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset);
+uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset);
+void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint32_t val);
+void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint64_t val);
 
-void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val);
-void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val);
-
-xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
-void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
+xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
+void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
 
 #endif	/* XE_MMIO_H */
diff --git a/lib/xe/xe_sriov_provisioning.c b/lib/xe/xe_sriov_provisioning.c
index ff9d1f7d2..2ca73d2ef 100644
--- a/lib/xe/xe_sriov_provisioning.c
+++ b/lib/xe/xe_sriov_provisioning.c
@@ -90,7 +90,7 @@ static int append_range(struct xe_sriov_provisioned_range **ranges,
 /**
  * xe_sriov_find_ggtt_provisioned_pte_offsets - Find GGTT provisioned PTE offsets
  * @pf_fd: File descriptor for the Physical Function
- * @gt: GT identifier
+ * @tile: Tile id
  * @mmio: Pointer to the MMIO structure
  * @ranges: Pointer to the array of provisioned ranges
  * @nr_ranges: Pointer to the number of provisioned ranges
@@ -106,7 +106,7 @@ static int append_range(struct xe_sriov_provisioned_range **ranges,
  *
  * Returns 0 on success, or a negative error code on failure.
  */
-int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio *mmio,
+int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile, struct xe_mmio *mmio,
 					       struct xe_sriov_provisioned_range **ranges,
 					       unsigned int *nr_ranges)
 {
@@ -122,7 +122,7 @@ int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio
 
 	for (uint32_t offset = START_PTE_OFFSET; offset < MAX_PTE_OFFSET;
 	     offset += sizeof(xe_ggtt_pte_t)) {
-		pte = xe_mmio_ggtt_read(mmio, gt, offset);
+		pte = xe_mmio_ggtt_read(mmio, tile, offset);
 		vf_id = (pte & vfid_mask) >> GGTT_PTE_VFID_SHIFT;
 
 		if (vf_id != current_vf_id) {
diff --git a/lib/xe/xe_sriov_provisioning.h b/lib/xe/xe_sriov_provisioning.h
index e1a9d0a63..1e1dca866 100644
--- a/lib/xe/xe_sriov_provisioning.h
+++ b/lib/xe/xe_sriov_provisioning.h
@@ -92,7 +92,7 @@ struct xe_sriov_provisioned_range {
 
 const char *xe_sriov_shared_res_to_string(enum xe_sriov_shared_res res);
 bool xe_sriov_is_shared_res_provisionable(int pf, enum xe_sriov_shared_res res, unsigned int gt);
-int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio *mmio,
+int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile, struct xe_mmio *mmio,
 					       struct xe_sriov_provisioned_range **ranges,
 					       unsigned int *nr_ranges);
 const char *xe_sriov_shared_res_attr_name(enum xe_sriov_shared_res res,
diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
index aabbd8c05..077ed15af 100644
--- a/tests/intel/xe_sriov_flr.c
+++ b/tests/intel/xe_sriov_flr.c
@@ -493,20 +493,20 @@ struct ggtt_data {
 
 static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
 {
-	return xe_mmio_ggtt_read(mmio, gt, pte_offset);
+	return xe_mmio_ggtt_read(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset);
 }
 
 static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
 {
-	xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
+	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
 }
 
 static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
 {
-	xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
+	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
 
 	/* force flush by read some MMIO register */
-	xe_mmio_gt_read32(mmio, gt, GEN12_VF_CAP_REG);
+	xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, gt), GEN12_VF_CAP_REG);
 }
 
 static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
@@ -548,8 +548,8 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
 	gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
 	igt_assert(gdata->pte_offsets);
 
-	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, gt, gdata->mmio,
-							 &ranges, &nr_ranges);
+	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, xe_gt_get_tile_id(pf_fd, gt),
+							 gdata->mmio, &ranges, &nr_ranges);
 	if (ret) {
 		set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
 				gt, ret);
-- 
2.43.0

Re: [PATCH i-g-t 1/6] lib/xe_mmio: Introduce tile-level XE MMIO access helpers

[Laguna, Lukasz]

On 11/6/2025 16:28, Marcin Bernatowicz wrote:
> From: Piotr Piórkowski <piotr.piorkowski@intel.com>
>
> Add new helpers for tile-based MMIO access:
>   - xe_mmio_tile_read32()
>   - xe_mmio_tile_read64()
>   - xe_mmio_tile_write32()
>   - xe_mmio_tile_write64()
>
> These functions provide explicit MMIO read/write operations within
> a given tile by applying TILE_MMIO_SIZE offsetting logic.
> GGTT is also a per-tile resource, so let's adjust the GGTT access
> helpers to use tile IDs instead of GT.
>
> v2:
>   - find the real tile based on gt instead of assuming root tile
> v3:
>   - drop misleading GT-oriented helpers (Lukasz)
>
> Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>

Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com>

> Cc: Jan Sokolowski <jan.sokolowski@intel.com>
> ---
>   lib/xe/xe_mmio.c               | 78 ++++++++++++++++------------------
>   lib/xe/xe_mmio.h               | 13 +++---
>   lib/xe/xe_sriov_provisioning.c |  6 +--
>   lib/xe/xe_sriov_provisioning.h |  2 +-
>   tests/intel/xe_sriov_flr.c     | 12 +++---
>   5 files changed, 52 insertions(+), 59 deletions(-)
>
> diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
> index 834816133..b52e90dba 100644
> --- a/lib/xe/xe_mmio.c
> +++ b/lib/xe/xe_mmio.c
> @@ -107,94 +107,88 @@ void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val)
>   	return iowrite64(mmio->intel_mmio.igt_mmio, offset, val);
>   }
>   
> -/**
> - * xe_mmio_gt_read32:
> +/** xe_mmio_tile_read32:
>    * @mmio: xe mmio structure for IO operations
> - * @gt: gt id
> - * @offset: mmio register offset in tile to which @gt belongs
> + * @tile: tile id
> + * @offset: mmio register offset in the tile
>    *
> - * 32-bit read of the register at @offset in tile to which @gt belongs.
> + * 32-bit read of the register at @offset in the specified @tile
>    *
> - * Returns:
> - * The value read from the register.
> + * Returns: The value read from the register.
>    */
> -uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset)
> +uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
>   {
> -	return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
> +	return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * tile));
>   }
>   
> -/**
> - * xe_mmio_gt_read64:
> +/** xe_mmio_tile_read64:
>    * @mmio: xe mmio structure for IO operations
> - * @gt: gt id
> - * @offset: mmio register offset in tile to which @gt belongs
> + * @tile: tile id
> + * @offset: mmio register offset in the @tile
>    *
> - * 64-bit read of the register at @offset in tile to which @gt belongs.
> + * 64-bit read of the register at @offset in the specified @tile
>    *
> - * Returns:
> - * The value read from the register.
> + * Returns: The value read from the register.
>    */
> -uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset)
> +uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
>   {
> -	return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
> +	return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * tile));
>   }
>   
>   /**
> - * xe_mmio_gt_write32:
> + * xe_mmio_tile_write32:
>    * @mmio: xe mmio structure for IO operations
> - * @gt: gt id
> - * @offset: mmio register offset
> + * @tile: tile id
> + * @offset: mmio register offset in the @tile
>    * @val: value to write
>    *
> - * 32-bit write to the register at @offset in tile to which @gt belongs.
> + * 32-bit write to the register at @offset in the specified @tile
>    */
> -void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val)
> +void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint32_t val)
>   {
> -	return xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
> -			       val);
> +	xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * tile), val);
>   }
>   
>   /**
> - * xe_mmio_gt_write64:
> + * xe_mmio_tile_write64:
>    * @mmio: xe mmio structure for IO operations
> - * @gt: gt id
> - * @offset: mmio register offset
> + * @tile: tile id
> + * @offset: mmio register offset in the @tile
>    * @val: value to write
>    *
> - * 64-bit write to the register at @offset in tile to which @gt belongs.
> + * 64-bit write to the register at @offset in the specified @tile
>    */
> -void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val)
> +void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint64_t val)
>   {
> -	return xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
> -			       val);
> +	xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * tile), val);
>   }
>   
>   /**
>    * xe_mmio_ggtt_read:
>    * @mmio: xe mmio structure for IO operations
> - * @gt: gt id
> - * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
> + * @tile: tile id
> + * @offset: PTE offset from the beginning of GGTT in @tile
>    *
> - * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
> + * Read of GGTT PTE at GGTT @offset in the @tile.
>    *
>    * Returns:
>    * The value read from the register.
>    */
> -xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t offset)
> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
>   {
> -	return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
> +	return xe_mmio_tile_read64(mmio, tile, offset + GGTT_OFFSET_IN_TILE);
>   }
>   
>   /**
>    * xe_mmio_ggtt_write:
>    * @mmio: xe mmio structure for IO operations
> - * @gt: gt id
> - * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
> + * @tile: tile id
> + * @offset: PTE offset from the beginning of GGTT in @tile
>    * @pte: PTE value to write
>    *
> - * Write PTE value at GGTT @offset in tile to which @gt belongs.
> + * Write PTE value at GGTT @offset in the @tile.
>    */
> -void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset, xe_ggtt_pte_t pte)
> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, xe_ggtt_pte_t pte)
>   {
> -	return xe_mmio_gt_write64(mmio, gt, offset + GGTT_OFFSET_IN_TILE, pte);
> +	return xe_mmio_tile_write64(mmio, tile, offset + GGTT_OFFSET_IN_TILE, pte);
>   }
> diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
> index f144d4b53..35cafa448 100644
> --- a/lib/xe/xe_mmio.h
> +++ b/lib/xe/xe_mmio.h
> @@ -29,13 +29,12 @@ uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t offset);
>   void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, uint32_t val);
>   void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val);
>   
> -uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset);
> -uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset);
> +uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset);
> +uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset);
> +void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint32_t val);
> +void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint64_t val);
>   
> -void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val);
> -void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val);
> -
> -xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
> -void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
>   
>   #endif	/* XE_MMIO_H */
> diff --git a/lib/xe/xe_sriov_provisioning.c b/lib/xe/xe_sriov_provisioning.c
> index ff9d1f7d2..2ca73d2ef 100644
> --- a/lib/xe/xe_sriov_provisioning.c
> +++ b/lib/xe/xe_sriov_provisioning.c
> @@ -90,7 +90,7 @@ static int append_range(struct xe_sriov_provisioned_range **ranges,
>   /**
>    * xe_sriov_find_ggtt_provisioned_pte_offsets - Find GGTT provisioned PTE offsets
>    * @pf_fd: File descriptor for the Physical Function
> - * @gt: GT identifier
> + * @tile: Tile id
>    * @mmio: Pointer to the MMIO structure
>    * @ranges: Pointer to the array of provisioned ranges
>    * @nr_ranges: Pointer to the number of provisioned ranges
> @@ -106,7 +106,7 @@ static int append_range(struct xe_sriov_provisioned_range **ranges,
>    *
>    * Returns 0 on success, or a negative error code on failure.
>    */
> -int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio *mmio,
> +int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile, struct xe_mmio *mmio,
>   					       struct xe_sriov_provisioned_range **ranges,
>   					       unsigned int *nr_ranges)
>   {
> @@ -122,7 +122,7 @@ int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio
>   
>   	for (uint32_t offset = START_PTE_OFFSET; offset < MAX_PTE_OFFSET;
>   	     offset += sizeof(xe_ggtt_pte_t)) {
> -		pte = xe_mmio_ggtt_read(mmio, gt, offset);
> +		pte = xe_mmio_ggtt_read(mmio, tile, offset);
>   		vf_id = (pte & vfid_mask) >> GGTT_PTE_VFID_SHIFT;
>   
>   		if (vf_id != current_vf_id) {
> diff --git a/lib/xe/xe_sriov_provisioning.h b/lib/xe/xe_sriov_provisioning.h
> index e1a9d0a63..1e1dca866 100644
> --- a/lib/xe/xe_sriov_provisioning.h
> +++ b/lib/xe/xe_sriov_provisioning.h
> @@ -92,7 +92,7 @@ struct xe_sriov_provisioned_range {
>   
>   const char *xe_sriov_shared_res_to_string(enum xe_sriov_shared_res res);
>   bool xe_sriov_is_shared_res_provisionable(int pf, enum xe_sriov_shared_res res, unsigned int gt);
> -int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio *mmio,
> +int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile, struct xe_mmio *mmio,
>   					       struct xe_sriov_provisioned_range **ranges,
>   					       unsigned int *nr_ranges);
>   const char *xe_sriov_shared_res_attr_name(enum xe_sriov_shared_res res,
> diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
> index aabbd8c05..077ed15af 100644
> --- a/tests/intel/xe_sriov_flr.c
> +++ b/tests/intel/xe_sriov_flr.c
> @@ -493,20 +493,20 @@ struct ggtt_data {
>   
>   static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
>   {
> -	return xe_mmio_ggtt_read(mmio, gt, pte_offset);
> +	return xe_mmio_ggtt_read(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset);
>   }
>   
>   static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
>   {
> -	xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
> +	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
>   }
>   
>   static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
>   {
> -	xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
> +	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
>   
>   	/* force flush by read some MMIO register */
> -	xe_mmio_gt_read32(mmio, gt, GEN12_VF_CAP_REG);
> +	xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, gt), GEN12_VF_CAP_REG);
>   }
>   
>   static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> @@ -548,8 +548,8 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
>   	gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
>   	igt_assert(gdata->pte_offsets);
>   
> -	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, gt, gdata->mmio,
> -							 &ranges, &nr_ranges);
> +	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, xe_gt_get_tile_id(pf_fd, gt),
> +							 gdata->mmio, &ranges, &nr_ranges);
>   	if (ret) {
>   		set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
>   				gt, ret);

[PATCH i-g-t 2/6] lib/xe_mmio: Add init flag and helper to check initialization

[Marcin Bernatowicz]

From: Piotr Piórkowski <piotr.piorkowski@intel.com>

Track MMIO initialization state via a new `init` flag and expose it
through xe_mmio_is_initialized().

Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Reviewed-by: Jan Sokolowski <jan.sokolowski@intel.com>
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
---
 lib/xe/xe_mmio.c | 14 ++++++++++++++
 lib/xe/xe_mmio.h |  2 ++
 2 files changed, 16 insertions(+)

diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
index b52e90dba..94e516417 100644
--- a/lib/xe/xe_mmio.c
+++ b/lib/xe/xe_mmio.c
@@ -25,6 +25,7 @@ void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio)
 
 	intel_register_access_init(&mmio->intel_mmio, pci_dev, false);
 	mmio->fd = pf_fd;
+	mmio->init = true;
 }
 
 /**
@@ -39,6 +40,18 @@ void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio)
 	xe_mmio_vf_access_init(pf_fd, 0, mmio);
 }
 
+/**
+ * xe_mmio_is_initialized:
+ * @mmio: xe mmio structure for IO operations
+ *
+ * Returns:
+ * Non-zero if the xe mmio structure is initialized.
+ */
+bool xe_mmio_is_initialized(const struct xe_mmio *mmio)
+{
+	return mmio->init;
+}
+
 /**
  * xe_mmio_access_fini:
  * @mmio: xe mmio structure for IO operations
@@ -49,6 +62,7 @@ void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio)
 void xe_mmio_access_fini(struct xe_mmio *mmio)
 {
 	intel_register_access_fini(&mmio->intel_mmio);
+	mmio->init = false;
 }
 
 /**
diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
index 35cafa448..030c50a2e 100644
--- a/lib/xe/xe_mmio.h
+++ b/lib/xe/xe_mmio.h
@@ -16,11 +16,13 @@ typedef uint64_t xe_ggtt_pte_t;
 
 struct xe_mmio {
 	int fd;
+	bool init;
 	struct intel_mmio_data intel_mmio;
 };
 
 void xe_mmio_vf_access_init(int pf_fd, int vf_id, struct xe_mmio *mmio);
 void xe_mmio_access_init(int pf_fd, struct xe_mmio *mmio);
+bool xe_mmio_is_initialized(const struct xe_mmio *mmio);
 void xe_mmio_access_fini(struct xe_mmio *mmio);
 
 uint32_t xe_mmio_read32(struct xe_mmio *mmio, uint32_t offset);
-- 
2.43.0

[PATCH i-g-t 3/6] lib/xe/xe_query: Add tile helpers and iteration macro

[Marcin Bernatowicz]

From: Piotr Piórkowski <piotr.piorkowski@intel.com>

Add helpers for tile-level access:
 - xe_tiles_count(): return number of tiles
 - xe_tile_get_main_gt_id(): get MAIN GT ID for a tile
 - xe_for_each_tile(): iterate over tiles via tile_mask

v2: Add missing colon in function doc (Lukasz)

Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
---
 lib/xe/xe_query.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
 lib/xe/xe_query.h |  6 ++++++
 2 files changed, 51 insertions(+)

diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index a89e0b980..8e3e05fd3 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -515,6 +515,22 @@ unsigned int xe_dev_max_gt(int fd)
 	return igt_fls(xe_dev->gt_mask) - 1;
 }
 
+/**
+ * xe_tiles_count:
+ * @fd: xe device fd
+ *
+ * Return number of tiles for xe device fd.
+ */
+uint8_t xe_tiles_count(int fd)
+{
+	struct xe_device *xe_dev;
+
+	xe_dev = find_in_cache(fd);
+	igt_assert(xe_dev);
+
+	return igt_hweight(xe_dev->tile_mask);
+}
+
 /**
  * all_memory_regions:
  * @fd: xe device fd
@@ -995,6 +1011,35 @@ uint16_t xe_gt_get_tile_id(int fd, int gt)
 	return xe_dev->gt_list->gt_list[gt].tile_id;
 }
 
+/**
+ * xe_tile_get_main_gt_id:
+ * @fd: xe device fd
+ * @tile: tile id
+ *
+ * Returns main GT ID for given @tile.
+ */
+uint16_t xe_tile_get_main_gt_id(int fd, uint8_t tile)
+{
+	struct xe_device *xe_dev;
+	int gt_id = -1;
+
+	xe_dev = find_in_cache(fd);
+	igt_assert(xe_dev);
+
+	for (int i = 0; i < xe_dev->gt_list->num_gt; i++) {
+		const struct drm_xe_gt *gt_data = &xe_dev->gt_list->gt_list[i];
+
+		if (gt_data->tile_id == tile && gt_data->type == DRM_XE_QUERY_GT_TYPE_MAIN) {
+			gt_id = gt_data->gt_id;
+			break;
+		}
+	}
+
+	igt_assert_f(gt_id >= 0, "No main GT found for tile %d\n", tile);
+
+	return gt_id;
+}
+
 /**
  * xe_hwconfig_lookup_value:
  * @fd: xe device fd
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 715b64e2f..bcdfb54b0 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -86,6 +86,10 @@ struct xe_device {
 	for (uint64_t igt_unique(__mask) = xe_device_get(__fd)->gt_mask; \
 	     __gt = ffsll(igt_unique(__mask)) - 1, igt_unique(__mask) != 0; \
 	     igt_unique(__mask) &= ~(1ull << __gt))
+#define xe_for_each_tile(__fd, __tile) \
+	for (uint64_t igt_unique(__mask) = xe_device_get(__fd)->tile_mask; \
+	     __tile = ffsll(igt_unique(__mask)) - 1, igt_unique(__mask) != 0; \
+	     igt_unique(__mask) &= ~(1ull << __tile))
 #define xe_for_each_mem_region(__fd, __memreg, __r) \
 	for (uint64_t igt_unique(__i) = 0; igt_unique(__i) < igt_fls(__memreg); igt_unique(__i)++) \
 		for_if(__r = (__memreg & (1ull << igt_unique(__i))))
@@ -101,6 +105,7 @@ struct xe_device {
 
 unsigned int xe_number_gt(int fd);
 unsigned int xe_dev_max_gt(int fd);
+uint8_t xe_tiles_count(int fd);
 uint64_t all_memory_regions(int fd);
 uint64_t system_memory(int fd);
 const struct drm_xe_gt *drm_xe_get_gt(struct xe_device *xe_dev, int gt_id);
@@ -135,6 +140,7 @@ uint16_t xe_gt_type(int fd, int gt);
 bool xe_is_media_gt(int fd, int gt);
 bool xe_is_main_gt(int fd, int gt);
 uint16_t xe_gt_get_tile_id(int fd, int gt);
+uint16_t xe_tile_get_main_gt_id(int fd, uint8_t tile);
 uint32_t *xe_hwconfig_lookup_value(int fd, enum intel_hwconfig attribute, uint32_t *len);
 int xe_query_pxp_status(int fd);
 int xe_wait_for_pxp_init(int fd);
-- 
2.43.0

[PATCH i-g-t 4/6] tests/intel/xe_sriov_flr: Make subchecks Tile aware

[Marcin Bernatowicz]

Follow up on Piotr's adjustments for tile-aware FLR tests.

Replace GT ID with Tile ID in struct subcheck_data and adapt the code
to use new MMIO tile helpers. Each tile now has its own set of subchecks
initialized in clear_tests, with separate data structures per tile.

Keeping the Tile ID in subcheck_data allows verify_flr() to remain
unchanged and avoids an xe_for_each_tile "explosion".

v2:
 - Use xe_mmio_tile_read32; update title; fix extra space (Piotr)

Link: https://patchwork.freedesktop.org/series/156216/
Suggested-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
---
 tests/intel/xe_sriov_flr.c | 276 ++++++++++++++++++-------------------
 1 file changed, 135 insertions(+), 141 deletions(-)

diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
index 077ed15af..ee0baa0fa 100644
--- a/tests/intel/xe_sriov_flr.c
+++ b/tests/intel/xe_sriov_flr.c
@@ -66,8 +66,7 @@ const char *SKIP_REASON = "SKIP";
  * @pf_fd: File descriptor for the Physical Function.
  * @num_vfs: Number of Virtual Functions (VFs) enabled and under test. This count is
  *           used to iterate over and manage the VFs during the testing process.
- * @gt: GT under test. This identifier is used to specify a particular GT
- *      for operations when GT-specific testing is required.
+ * @tile: Tile under test.
  * @stop_reason: Pointer to a string that indicates why a subcheck should skip or fail.
  *               This field is crucial for controlling the flow of subcheck execution.
  *               If set, it should prevent further execution of the current subcheck,
@@ -79,12 +78,12 @@ const char *SKIP_REASON = "SKIP";
  * Example usage:
  * A typical use of this structure involves initializing it with the necessary test setup
  * parameters, checking the `stop_reason` field before proceeding with each subcheck operation,
- * and using `pf_fd`, `num_vfs`, and `gt` as needed based on the specific subcheck requirements.
+ * and using `pf_fd`, `num_vfs`, and `tile` as needed based on the specific subcheck requirements.
  */
 struct subcheck_data {
 	int pf_fd;
 	int num_vfs;
-	int gt;
+	uint8_t tile;
 	char *stop_reason;
 };
 
@@ -207,16 +206,19 @@ static void subchecks_report_results(struct subcheck *checks, int num_checks)
 	for (int i = 0; i < num_checks; ++i) {
 		if (checks[i].data->stop_reason) {
 			if (is_subcheck_skipped(&checks[i])) {
-				igt_info("%s: %s", checks[i].name,
+				igt_info("%s: Tile%u: %s", checks[i].name,
+					 checks[i].data->tile,
 					 checks[i].data->stop_reason);
 				skips++;
 			} else {
-				igt_critical("%s: %s", checks[i].name,
+				igt_critical("%s: Tile%u: %s", checks[i].name,
+					     checks[i].data->tile,
 					     checks[i].data->stop_reason);
 				fails++;
 			}
 		} else {
-			igt_info("%s: SUCCESS\n", checks[i].name);
+			igt_info("%s: Tile%u: SUCCESS\n", checks[i].name,
+				 checks[i].data->tile);
 		}
 	}
 
@@ -470,8 +472,8 @@ static int execute_parallel_flr_twice(int pf_fd, int num_vfs,
 #define GGTT_PTE_ADDR_SHIFT			12
 
 struct ggtt_ops {
-	void (*set_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
-	xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
+	void (*set_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
+	xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
 };
 
 struct ggtt_provisioned_offset_range {
@@ -491,68 +493,66 @@ struct ggtt_data {
 	struct ggtt_ops ggtt;
 };
 
-static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
+static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset)
 {
-	return xe_mmio_ggtt_read(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset);
+	return xe_mmio_ggtt_read(mmio, tile, pte_offset);
 }
 
-static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
+static void intel_set_pte(struct xe_mmio *mmio, uint8_t tile,
+			  uint32_t pte_offset, xe_ggtt_pte_t pte)
 {
-	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
+	xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
 }
 
-static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
+static void intel_mtl_set_pte(struct xe_mmio *mmio, uint8_t tile,
+			      uint32_t pte_offset, xe_ggtt_pte_t pte)
 {
-	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
+	xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
 
 	/* force flush by read some MMIO register */
-	xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, gt), GEN12_VF_CAP_REG);
+	xe_mmio_tile_read32(mmio, tile, GEN12_VF_CAP_REG);
 }
 
-static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
-			uint8_t gpa, xe_ggtt_pte_t *out)
+static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
+			uint32_t pte_offset, uint8_t gpa, xe_ggtt_pte_t *out)
 {
 	xe_ggtt_pte_t pte;
 
-	pte = ggtt->get_pte(mmio, gt, pte_offset);
+	pte = ggtt->get_pte(mmio, tile, pte_offset);
 	pte &= ~GGTT_PTE_TEST_FIELD_MASK;
 	pte |= ((xe_ggtt_pte_t)gpa << GGTT_PTE_ADDR_SHIFT) & GGTT_PTE_TEST_FIELD_MASK;
-	ggtt->set_pte(mmio, gt, pte_offset, pte);
-	*out = ggtt->get_pte(mmio, gt, pte_offset);
+	ggtt->set_pte(mmio, tile, pte_offset, pte);
+	*out = ggtt->get_pte(mmio, tile, pte_offset);
 
 	return *out == pte;
 }
 
-static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
-			  uint8_t expected_gpa, xe_ggtt_pte_t *out)
+static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
+			  uint32_t pte_offset, uint8_t expected_gpa, xe_ggtt_pte_t *out)
 {
 	uint8_t val;
 
-	*out = ggtt->get_pte(mmio, gt, pte_offset);
+	*out = ggtt->get_pte(mmio, tile, pte_offset);
 	val = (uint8_t)((*out & GGTT_PTE_TEST_FIELD_MASK) >> GGTT_PTE_ADDR_SHIFT);
 
 	return val == expected_gpa;
 }
 
-static bool is_intel_mmio_initialized(const struct intel_mmio_data *mmio)
-{
-	return mmio->dev;
-}
-
 static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
 {
 	int ret, pf_fd = gdata->base.pf_fd, num_vfs = gdata->base.num_vfs;
 	struct xe_sriov_provisioned_range *ranges;
-	unsigned int nr_ranges, gt = gdata->base.gt;
+	uint8_t tile = gdata->base.tile;
+	unsigned int nr_ranges;
 
 	gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
 	igt_assert(gdata->pte_offsets);
 
-	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, xe_gt_get_tile_id(pf_fd, gt),
-							 gdata->mmio, &ranges, &nr_ranges);
+	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, tile, gdata->mmio,
+							 &ranges, &nr_ranges);
 	if (ret) {
-		set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
-				gt, ret);
+		set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges (%d)\n",
+				ret);
 		return -1;
 	}
 
@@ -597,12 +597,6 @@ static void ggtt_subcheck_init(struct subcheck_data *data)
 {
 	struct ggtt_data *gdata = (struct ggtt_data *)data;
 
-	if (!xe_is_main_gt(data->pf_fd, data->gt)) {
-		set_skip_reason(data, "GGTT provisioning not exposed on GT%d (non-MAIN)\n",
-				data->gt);
-		return;
-	}
-
 	gdata->ggtt.get_pte = intel_get_pte;
 	if (IS_METEORLAKE(intel_get_drm_devid(data->pf_fd)))
 		gdata->ggtt.set_pte = intel_mtl_set_pte;
@@ -610,7 +604,7 @@ static void ggtt_subcheck_init(struct subcheck_data *data)
 		gdata->ggtt.set_pte = intel_set_pte;
 
 	if (gdata->mmio) {
-		if (!is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
+		if (!xe_mmio_is_initialized(&gdata->mmio[0]))
 			xe_mmio_vf_access_init(data->pf_fd, 0 /*PF*/, gdata->mmio);
 
 		populate_ggtt_pte_offsets(gdata);
@@ -628,12 +622,13 @@ static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
 	if (data->stop_reason)
 		return;
 
-	igt_debug("Prepare gpa on VF%u offset range [%#x-%#x]\n", vf_id,
+	igt_debug("Tile%u: Prepare gpa on VF%u offset range [%#x-%#x]\n",
+		  gdata->base.tile, vf_id,
 		  gdata->pte_offsets[vf_id].start,
 		  gdata->pte_offsets[vf_id].end);
 
 	for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
-		if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
+		if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, data->tile, pte_offset,
 				 (uint8_t)vf_id, &pte)) {
 			set_skip_reason(data,
 					"Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x\n",
@@ -654,7 +649,7 @@ static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
 		return;
 
 	for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
-		if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
+		if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, data->tile, pte_offset,
 				   expected, &pte)) {
 			set_fail_reason(data,
 					"GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
@@ -669,8 +664,6 @@ static void ggtt_subcheck_cleanup(struct subcheck_data *data)
 	struct ggtt_data *gdata = (struct ggtt_data *)data;
 
 	free(gdata->pte_offsets);
-	if (gdata->mmio && is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
-		xe_mmio_access_fini(gdata->mmio);
 }
 
 struct lmem_data {
@@ -739,37 +732,33 @@ static int populate_vf_lmem_sizes(struct subcheck_data *data)
 {
 	struct lmem_data *ldata = (struct lmem_data *)data;
 	struct xe_sriov_provisioned_range *ranges;
-	unsigned int nr_ranges, gt;
+	unsigned int nr_ranges, main_gt;
 	int ret;
 
+	main_gt = xe_tile_get_main_gt_id(data->pf_fd, data->tile);
 	ldata->vf_lmem_size = calloc(data->num_vfs + 1, sizeof(size_t));
 	igt_assert(ldata->vf_lmem_size);
 
-	xe_for_each_gt(data->pf_fd, gt) {
-		if (!xe_is_main_gt(data->pf_fd, gt))
-			continue;
-
-		ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd,
-								  XE_SRIOV_SHARED_RES_LMEM,
-								  gt, &ranges, &nr_ranges);
-		if (ret) {
-			set_skip_reason(data, "Failed read %s on gt%u (%d)\n",
-					xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
-					gt, ret);
-			return -1;
-		}
-
-		for (unsigned int i = 0; i < nr_ranges; ++i) {
-			const unsigned int vf_id = ranges[i].vf_id;
+	ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd,
+							  XE_SRIOV_SHARED_RES_LMEM,
+							  main_gt, &ranges, &nr_ranges);
+	if (ret) {
+		set_skip_reason(data, "Failed read %s on main GT (%d)\n",
+				xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
+				ret);
+		return -1;
+	}
 
-			igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
-			/* Sum the allocation for vf_id (inclusive range) */
-			ldata->vf_lmem_size[vf_id] += ranges[i].end - ranges[i].start + 1;
-		}
+	for (unsigned int i = 0; i < nr_ranges; ++i) {
+		const unsigned int vf_id = ranges[i].vf_id;
 
-		free(ranges);
+		igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
+		/* Sum the allocation for vf_id (inclusive range) */
+		ldata->vf_lmem_size[vf_id] += ranges[i].end - ranges[i].start + 1;
 	}
 
+	free(ranges);
+
 	for (int vf_id = 1; vf_id <= data->num_vfs; ++vf_id)
 		if (!ldata->vf_lmem_size[vf_id]) {
 			set_skip_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
@@ -839,7 +828,7 @@ static void lmem_subcheck_cleanup(struct subcheck_data *data)
 
 struct regs_data {
 	struct subcheck_data base;
-	struct intel_mmio_data *mmio;
+	struct xe_mmio *mmio;
 	uint32_t reg_addr;
 	int reg_count;
 };
@@ -857,31 +846,21 @@ static void regs_subcheck_init(struct subcheck_data *data)
 static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
 {
 	struct regs_data *rdata = (struct regs_data *)data;
+	uint8_t tile = data->tile;
 	uint32_t reg;
 	int i;
 
 	if (data->stop_reason)
 		return;
 
-	if (!is_intel_mmio_initialized(&rdata->mmio[vf_id])) {
-		struct pci_device *pci_dev = __igt_device_get_pci_device(data->pf_fd, vf_id);
-
-		if (!pci_dev) {
-			set_skip_reason(data, "No PCI device found for VF%u\n", vf_id);
-			return;
-		}
-
-		if (intel_register_access_init(&rdata->mmio[vf_id], pci_dev, false)) {
-			set_skip_reason(data, "Failed to get access to VF%u MMIO\n", vf_id);
-			return;
-		}
-	}
+	if (!xe_mmio_is_initialized(&rdata->mmio[vf_id]))
+		xe_mmio_vf_access_init(data->pf_fd, vf_id, &rdata->mmio[vf_id]);
 
 	for (i = 0; i < rdata->reg_count; i++) {
 		reg = rdata->reg_addr + i * 4;
 
-		intel_register_write(&rdata->mmio[vf_id], reg, vf_id);
-		if (intel_register_read(&rdata->mmio[vf_id], reg) != vf_id) {
+		xe_mmio_tile_write32(&rdata->mmio[vf_id], tile, reg, vf_id);
+		if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != vf_id) {
 			set_skip_reason(data, "Registers write/read check failed on VF%u\n", vf_id);
 			return;
 		}
@@ -901,7 +880,7 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
 	for (i = 0; i < rdata->reg_count; i++) {
 		reg = rdata->reg_addr + i * 4;
 
-		if (intel_register_read(&rdata->mmio[vf_id], reg) != expected) {
+		if (xe_mmio_tile_read32(&rdata->mmio[vf_id], data->tile, reg) != expected) {
 			set_fail_reason(data,
 					"Registers check after VF%u FLR failed on VF%u\n",
 					flr_vf_id, vf_id);
@@ -910,50 +889,42 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
 	}
 }
 
-static void regs_subcheck_cleanup(struct subcheck_data *data)
-{
-	struct regs_data *rdata = (struct regs_data *)data;
-	int i;
+static void regs_subcheck_cleanup(struct subcheck_data *data) { }
 
-	if (rdata->mmio)
-		for (i = 1; i <= data->num_vfs; ++i)
-			if (is_intel_mmio_initialized(&rdata->mmio[i]))
-				intel_register_access_fini(&rdata->mmio[i]);
+static void cleanup_mmio(struct xe_mmio *mmio, int num_vfs)
+{
+	for (int i = 0; i <= num_vfs; ++i)
+		if (xe_mmio_is_initialized(&mmio[i]))
+			xe_mmio_access_fini(&mmio[i]);
 }
 
 static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
 {
-	struct xe_mmio xemmio = { };
-	const unsigned int num_gts = xe_number_gt(pf_fd);
-	struct ggtt_data gdata[num_gts];
-	struct lmem_data ldata = {
-		.base = { .pf_fd = pf_fd, .num_vfs = num_vfs }
-	};
-	struct intel_mmio_data mmio[num_vfs + 1];
-	struct regs_data scratch_data = {
-		.base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
-		.mmio = mmio,
-		.reg_addr = SCRATCH_REG,
-		.reg_count = SCRATCH_REG_COUNT
-	};
-	struct regs_data media_scratch_data = {
-		.base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
-		.mmio = mmio,
-		.reg_addr = MED_SCRATCH_REG,
-		.reg_count = MED_SCRATCH_REG_COUNT
-	};
-	const unsigned int num_checks = num_gts + 3;
+	struct xe_mmio mmio[num_vfs + 1];
+	const uint8_t num_tiles = xe_tiles_count(pf_fd);
+	struct subcheck_data base;
+	struct ggtt_data gdata[num_tiles];
+	struct lmem_data ldata[num_tiles];
+	struct regs_data scratch_data[num_tiles];
+	struct regs_data media_scratch_data[num_tiles];
+	const unsigned int subcheck_count = 4;
+	const unsigned int num_checks =	subcheck_count * num_tiles;
 	struct subcheck checks[num_checks];
-	int i = 0, gt_id;
+	unsigned int i = 0, t;
 
 	memset(mmio, 0, sizeof(mmio));
 
-	xe_for_each_gt(pf_fd, gt_id) {
+	xe_for_each_tile(pf_fd, t) {
+		igt_assert_lt(i, num_tiles);
+		base = (struct subcheck_data){ .pf_fd = pf_fd,
+					       .num_vfs = num_vfs,
+					       .tile = t };
+
 		gdata[i] = (struct ggtt_data){
-			.base = { .pf_fd = pf_fd, .num_vfs = num_vfs, .gt = gt_id },
-			.mmio = &xemmio
+			.base = base,
+			.mmio = mmio,
 		};
-		checks[i] = (struct subcheck){
+		checks[i * subcheck_count + 0] = (struct subcheck){
 			.data = (struct subcheck_data *)&gdata[i],
 			.name = "clear-ggtt",
 			.init = ggtt_subcheck_init,
@@ -961,33 +932,56 @@ static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
 			.verify_vf = ggtt_subcheck_verify_vf,
 			.cleanup = ggtt_subcheck_cleanup
 		};
+
+		ldata[i] = (struct lmem_data){
+			.base = base,
+		};
+		checks[i * subcheck_count + 1] = (struct subcheck){
+			.data = (struct subcheck_data *)&ldata[i],
+			.name = "clear-lmem",
+			.init = lmem_subcheck_init,
+			.prepare_vf = lmem_subcheck_prepare_vf,
+			.verify_vf = lmem_subcheck_verify_vf,
+			.cleanup = lmem_subcheck_cleanup
+		};
+
+		scratch_data[i] = (struct regs_data){
+			.base = base,
+			.mmio = mmio,
+			.reg_addr = SCRATCH_REG,
+			.reg_count = SCRATCH_REG_COUNT,
+		};
+		checks[i * subcheck_count + 2] = (struct subcheck){
+			.data = (struct subcheck_data *)&scratch_data[i],
+			.name = "clear-scratch-regs",
+			.init = regs_subcheck_init,
+			.prepare_vf = regs_subcheck_prepare_vf,
+			.verify_vf = regs_subcheck_verify_vf,
+			.cleanup = regs_subcheck_cleanup
+		};
+
+		media_scratch_data[i] = (struct regs_data){
+			.base = base,
+			.mmio = mmio,
+			.reg_addr = MED_SCRATCH_REG,
+			.reg_count = MED_SCRATCH_REG_COUNT,
+		};
+		checks[i * subcheck_count + 3] = (struct subcheck){
+			.data = (struct subcheck_data *)&media_scratch_data[i],
+			.name = "clear-media-scratch-regs",
+			.init = regs_subcheck_init,
+			.prepare_vf = regs_subcheck_prepare_vf,
+			.verify_vf = regs_subcheck_verify_vf,
+			.cleanup = regs_subcheck_cleanup
+		};
 		i++;
 	}
-	checks[i++] = (struct subcheck) {
-		.data = (struct subcheck_data *)&ldata,
-		.name = "clear-lmem",
-		.init = lmem_subcheck_init,
-		.prepare_vf = lmem_subcheck_prepare_vf,
-		.verify_vf = lmem_subcheck_verify_vf,
-		.cleanup = lmem_subcheck_cleanup };
-	checks[i++] = (struct subcheck) {
-		.data = (struct subcheck_data *)&scratch_data,
-		.name = "clear-scratch-regs",
-		.init = regs_subcheck_init,
-		.prepare_vf = regs_subcheck_prepare_vf,
-		.verify_vf = regs_subcheck_verify_vf,
-		.cleanup = regs_subcheck_cleanup };
-	checks[i++] = (struct subcheck) {
-		.data = (struct subcheck_data *)&media_scratch_data,
-		.name = "clear-media-scratch-regs",
-		.init = regs_subcheck_init,
-		.prepare_vf = regs_subcheck_prepare_vf,
-		.verify_vf = regs_subcheck_verify_vf,
-		.cleanup = regs_subcheck_cleanup
-	};
-	igt_assert_eq(i, num_checks);
+	igt_assert_eq(i, num_tiles);
+	igt_assert_eq(i * subcheck_count, num_checks);
 
 	verify_flr(pf_fd, num_vfs, checks, num_checks, exec_strategy);
+
+	cleanup_mmio(mmio, num_vfs);
 }
 
 igt_main
-- 
2.43.0

Re: [PATCH i-g-t 4/6] tests/intel/xe_sriov_flr: Make subchecks Tile aware

[Piotr Piórkowski]

Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> wrote on czw [2025-lis-06 16:28:08 +0100]:
> Follow up on Piotr's adjustments for tile-aware FLR tests.
> 
> Replace GT ID with Tile ID in struct subcheck_data and adapt the code
> to use new MMIO tile helpers. Each tile now has its own set of subchecks
> initialized in clear_tests, with separate data structures per tile.
> 
> Keeping the Tile ID in subcheck_data allows verify_flr() to remain
> unchanged and avoids an xe_for_each_tile "explosion".
> 
> v2:
>  - Use xe_mmio_tile_read32; update title; fix extra space (Piotr)
> 
> Link: https://patchwork.freedesktop.org/series/156216/
> Suggested-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
> ---
>  tests/intel/xe_sriov_flr.c | 276 ++++++++++++++++++-------------------
>  1 file changed, 135 insertions(+), 141 deletions(-)
> 
> diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
> index 077ed15af..ee0baa0fa 100644
> --- a/tests/intel/xe_sriov_flr.c
> +++ b/tests/intel/xe_sriov_flr.c
> @@ -66,8 +66,7 @@ const char *SKIP_REASON = "SKIP";
>   * @pf_fd: File descriptor for the Physical Function.
>   * @num_vfs: Number of Virtual Functions (VFs) enabled and under test. This count is
>   *           used to iterate over and manage the VFs during the testing process.
> - * @gt: GT under test. This identifier is used to specify a particular GT
> - *      for operations when GT-specific testing is required.
> + * @tile: Tile under test.
>   * @stop_reason: Pointer to a string that indicates why a subcheck should skip or fail.
>   *               This field is crucial for controlling the flow of subcheck execution.
>   *               If set, it should prevent further execution of the current subcheck,
> @@ -79,12 +78,12 @@ const char *SKIP_REASON = "SKIP";
>   * Example usage:
>   * A typical use of this structure involves initializing it with the necessary test setup
>   * parameters, checking the `stop_reason` field before proceeding with each subcheck operation,
> - * and using `pf_fd`, `num_vfs`, and `gt` as needed based on the specific subcheck requirements.
> + * and using `pf_fd`, `num_vfs`, and `tile` as needed based on the specific subcheck requirements.
>   */
>  struct subcheck_data {
>  	int pf_fd;
>  	int num_vfs;
> -	int gt;
> +	uint8_t tile;
>  	char *stop_reason;
>  };
>  
> @@ -207,16 +206,19 @@ static void subchecks_report_results(struct subcheck *checks, int num_checks)
>  	for (int i = 0; i < num_checks; ++i) {
>  		if (checks[i].data->stop_reason) {
>  			if (is_subcheck_skipped(&checks[i])) {
> -				igt_info("%s: %s", checks[i].name,
> +				igt_info("%s: Tile%u: %s", checks[i].name,
> +					 checks[i].data->tile,
>  					 checks[i].data->stop_reason);
>  				skips++;
>  			} else {
> -				igt_critical("%s: %s", checks[i].name,
> +				igt_critical("%s: Tile%u: %s", checks[i].name,
> +					     checks[i].data->tile,
>  					     checks[i].data->stop_reason);
>  				fails++;

I looked through other igt logs: igt_info and igt_critical everywhere else has
an end-of-line character. I think it's needed here too.


>  			}
>  		} else {
> -			igt_info("%s: SUCCESS\n", checks[i].name);
> +			igt_info("%s: Tile%u: SUCCESS\n", checks[i].name,
> +				 checks[i].data->tile);
>  		}
>  	}
>  
> @@ -470,8 +472,8 @@ static int execute_parallel_flr_twice(int pf_fd, int num_vfs,
>  #define GGTT_PTE_ADDR_SHIFT			12
>  
>  struct ggtt_ops {
> -	void (*set_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
> -	xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
> +	void (*set_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
> +	xe_ggtt_pte_t (*get_pte)(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
>  };
>  
>  struct ggtt_provisioned_offset_range {
> @@ -491,68 +493,66 @@ struct ggtt_data {
>  	struct ggtt_ops ggtt;
>  };
>  
> -static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
> +static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset)
>  {
> -	return xe_mmio_ggtt_read(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset);
> +	return xe_mmio_ggtt_read(mmio, tile, pte_offset);
>  }
>  
> -static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
> +static void intel_set_pte(struct xe_mmio *mmio, uint8_t tile,
> +			  uint32_t pte_offset, xe_ggtt_pte_t pte)
>  {
> -	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
> +	xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
>  }
>  
> -static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
> +static void intel_mtl_set_pte(struct xe_mmio *mmio, uint8_t tile,
> +			      uint32_t pte_offset, xe_ggtt_pte_t pte)
>  {
> -	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
> +	xe_mmio_ggtt_write(mmio, tile, pte_offset, pte);
>  
>  	/* force flush by read some MMIO register */
> -	xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, gt), GEN12_VF_CAP_REG);
> +	xe_mmio_tile_read32(mmio, tile, GEN12_VF_CAP_REG);
>  }
>  
> -static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> -			uint8_t gpa, xe_ggtt_pte_t *out)
> +static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
> +			uint32_t pte_offset, uint8_t gpa, xe_ggtt_pte_t *out)
>  {
>  	xe_ggtt_pte_t pte;
>  
> -	pte = ggtt->get_pte(mmio, gt, pte_offset);
> +	pte = ggtt->get_pte(mmio, tile, pte_offset);
>  	pte &= ~GGTT_PTE_TEST_FIELD_MASK;
>  	pte |= ((xe_ggtt_pte_t)gpa << GGTT_PTE_ADDR_SHIFT) & GGTT_PTE_TEST_FIELD_MASK;
> -	ggtt->set_pte(mmio, gt, pte_offset, pte);
> -	*out = ggtt->get_pte(mmio, gt, pte_offset);
> +	ggtt->set_pte(mmio, tile, pte_offset, pte);
> +	*out = ggtt->get_pte(mmio, tile, pte_offset);
>  
>  	return *out == pte;
>  }
>  
> -static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> -			  uint8_t expected_gpa, xe_ggtt_pte_t *out)
> +static bool check_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, uint8_t tile,
> +			  uint32_t pte_offset, uint8_t expected_gpa, xe_ggtt_pte_t *out)
>  {
>  	uint8_t val;
>  
> -	*out = ggtt->get_pte(mmio, gt, pte_offset);
> +	*out = ggtt->get_pte(mmio, tile, pte_offset);
>  	val = (uint8_t)((*out & GGTT_PTE_TEST_FIELD_MASK) >> GGTT_PTE_ADDR_SHIFT);
>  
>  	return val == expected_gpa;
>  }
>  
> -static bool is_intel_mmio_initialized(const struct intel_mmio_data *mmio)
> -{
> -	return mmio->dev;
> -}
> -
>  static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
>  {
>  	int ret, pf_fd = gdata->base.pf_fd, num_vfs = gdata->base.num_vfs;
>  	struct xe_sriov_provisioned_range *ranges;
> -	unsigned int nr_ranges, gt = gdata->base.gt;
> +	uint8_t tile = gdata->base.tile;
> +	unsigned int nr_ranges;
>  
>  	gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
>  	igt_assert(gdata->pte_offsets);
>  
> -	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, xe_gt_get_tile_id(pf_fd, gt),
> -							 gdata->mmio, &ranges, &nr_ranges);
> +	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, tile, gdata->mmio,
> +							 &ranges, &nr_ranges);
>  	if (ret) {
> -		set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
> -				gt, ret);
> +		set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges (%d)\n",
> +				ret);
>  		return -1;
>  	}
>  
> @@ -597,12 +597,6 @@ static void ggtt_subcheck_init(struct subcheck_data *data)
>  {
>  	struct ggtt_data *gdata = (struct ggtt_data *)data;
>  
> -	if (!xe_is_main_gt(data->pf_fd, data->gt)) {
> -		set_skip_reason(data, "GGTT provisioning not exposed on GT%d (non-MAIN)\n",
> -				data->gt);
> -		return;
> -	}
> -
>  	gdata->ggtt.get_pte = intel_get_pte;
>  	if (IS_METEORLAKE(intel_get_drm_devid(data->pf_fd)))
>  		gdata->ggtt.set_pte = intel_mtl_set_pte;
> @@ -610,7 +604,7 @@ static void ggtt_subcheck_init(struct subcheck_data *data)
>  		gdata->ggtt.set_pte = intel_set_pte;
>  
>  	if (gdata->mmio) {
> -		if (!is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
> +		if (!xe_mmio_is_initialized(&gdata->mmio[0]))
>  			xe_mmio_vf_access_init(data->pf_fd, 0 /*PF*/, gdata->mmio);
>  
>  		populate_ggtt_pte_offsets(gdata);
> @@ -628,12 +622,13 @@ static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
>  	if (data->stop_reason)
>  		return;
>  
> -	igt_debug("Prepare gpa on VF%u offset range [%#x-%#x]\n", vf_id,
> +	igt_debug("Tile%u: Prepare gpa on VF%u offset range [%#x-%#x]\n",
> +		  gdata->base.tile, vf_id,
>  		  gdata->pte_offsets[vf_id].start,
>  		  gdata->pte_offsets[vf_id].end);
>  
>  	for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
> -		if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
> +		if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, data->tile, pte_offset,
>  				 (uint8_t)vf_id, &pte)) {
>  			set_skip_reason(data,
>  					"Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x\n",
> @@ -654,7 +649,7 @@ static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
>  		return;
>  
>  	for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
> -		if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, data->gt, pte_offset,
> +		if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, data->tile, pte_offset,
>  				   expected, &pte)) {
>  			set_fail_reason(data,
>  					"GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
> @@ -669,8 +664,6 @@ static void ggtt_subcheck_cleanup(struct subcheck_data *data)
>  	struct ggtt_data *gdata = (struct ggtt_data *)data;
>  
>  	free(gdata->pte_offsets);
> -	if (gdata->mmio && is_intel_mmio_initialized(&gdata->mmio->intel_mmio))
> -		xe_mmio_access_fini(gdata->mmio);
>  }
>  
>  struct lmem_data {
> @@ -739,37 +732,33 @@ static int populate_vf_lmem_sizes(struct subcheck_data *data)
>  {
>  	struct lmem_data *ldata = (struct lmem_data *)data;
>  	struct xe_sriov_provisioned_range *ranges;
> -	unsigned int nr_ranges, gt;
> +	unsigned int nr_ranges, main_gt;
>  	int ret;
>  
> +	main_gt = xe_tile_get_main_gt_id(data->pf_fd, data->tile);
>  	ldata->vf_lmem_size = calloc(data->num_vfs + 1, sizeof(size_t));
>  	igt_assert(ldata->vf_lmem_size);
>  
> -	xe_for_each_gt(data->pf_fd, gt) {
> -		if (!xe_is_main_gt(data->pf_fd, gt))
> -			continue;
> -
> -		ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd,
> -								  XE_SRIOV_SHARED_RES_LMEM,
> -								  gt, &ranges, &nr_ranges);
> -		if (ret) {
> -			set_skip_reason(data, "Failed read %s on gt%u (%d)\n",
> -					xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
> -					gt, ret);
> -			return -1;
> -		}
> -
> -		for (unsigned int i = 0; i < nr_ranges; ++i) {
> -			const unsigned int vf_id = ranges[i].vf_id;
> +	ret = xe_sriov_pf_debugfs_read_provisioned_ranges(data->pf_fd,
> +							  XE_SRIOV_SHARED_RES_LMEM,
> +							  main_gt, &ranges, &nr_ranges);
> +	if (ret) {
> +		set_skip_reason(data, "Failed read %s on main GT (%d)\n",
> +				xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
> +				ret);
> +		return -1;
> +	}
>  
> -			igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
> -			/* Sum the allocation for vf_id (inclusive range) */
> -			ldata->vf_lmem_size[vf_id] += ranges[i].end - ranges[i].start + 1;
> -		}
> +	for (unsigned int i = 0; i < nr_ranges; ++i) {
> +		const unsigned int vf_id = ranges[i].vf_id;
>  
> -		free(ranges);
> +		igt_assert(vf_id >= 1 && vf_id <= data->num_vfs);
> +		/* Sum the allocation for vf_id (inclusive range) */
> +		ldata->vf_lmem_size[vf_id] += ranges[i].end - ranges[i].start + 1;
>  	}
>  
> +	free(ranges);
> +
>  	for (int vf_id = 1; vf_id <= data->num_vfs; ++vf_id)
>  		if (!ldata->vf_lmem_size[vf_id]) {
>  			set_skip_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
> @@ -839,7 +828,7 @@ static void lmem_subcheck_cleanup(struct subcheck_data *data)
>  
>  struct regs_data {
>  	struct subcheck_data base;
> -	struct intel_mmio_data *mmio;
> +	struct xe_mmio *mmio;
>  	uint32_t reg_addr;
>  	int reg_count;
>  };
> @@ -857,31 +846,21 @@ static void regs_subcheck_init(struct subcheck_data *data)
>  static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
>  {
>  	struct regs_data *rdata = (struct regs_data *)data;
> +	uint8_t tile = data->tile;
>  	uint32_t reg;
>  	int i;
>  
>  	if (data->stop_reason)
>  		return;
>  
> -	if (!is_intel_mmio_initialized(&rdata->mmio[vf_id])) {
> -		struct pci_device *pci_dev = __igt_device_get_pci_device(data->pf_fd, vf_id);
> -
> -		if (!pci_dev) {
> -			set_skip_reason(data, "No PCI device found for VF%u\n", vf_id);
> -			return;
> -		}
> -
> -		if (intel_register_access_init(&rdata->mmio[vf_id], pci_dev, false)) {
> -			set_skip_reason(data, "Failed to get access to VF%u MMIO\n", vf_id);
> -			return;
> -		}
> -	}
> +	if (!xe_mmio_is_initialized(&rdata->mmio[vf_id]))
> +		xe_mmio_vf_access_init(data->pf_fd, vf_id, &rdata->mmio[vf_id]);
>  
>  	for (i = 0; i < rdata->reg_count; i++) {
>  		reg = rdata->reg_addr + i * 4;
>  
> -		intel_register_write(&rdata->mmio[vf_id], reg, vf_id);
> -		if (intel_register_read(&rdata->mmio[vf_id], reg) != vf_id) {
> +		xe_mmio_tile_write32(&rdata->mmio[vf_id], tile, reg, vf_id);
> +		if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != vf_id) {
>  			set_skip_reason(data, "Registers write/read check failed on VF%u\n", vf_id);
>  			return;
>  		}
> @@ -901,7 +880,7 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
>  	for (i = 0; i < rdata->reg_count; i++) {
>  		reg = rdata->reg_addr + i * 4;
>  
> -		if (intel_register_read(&rdata->mmio[vf_id], reg) != expected) {
> +		if (xe_mmio_tile_read32(&rdata->mmio[vf_id], data->tile, reg) != expected) {
>  			set_fail_reason(data,
>  					"Registers check after VF%u FLR failed on VF%u\n",
>  					flr_vf_id, vf_id);
> @@ -910,50 +889,42 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
>  	}
>  }
>  
> -static void regs_subcheck_cleanup(struct subcheck_data *data)
> -{
> -	struct regs_data *rdata = (struct regs_data *)data;
> -	int i;
> +static void regs_subcheck_cleanup(struct subcheck_data *data) { }
>  
> -	if (rdata->mmio)
> -		for (i = 1; i <= data->num_vfs; ++i)
> -			if (is_intel_mmio_initialized(&rdata->mmio[i]))
> -				intel_register_access_fini(&rdata->mmio[i]);
> +static void cleanup_mmio(struct xe_mmio *mmio, int num_vfs)
> +{
> +	for (int i = 0; i <= num_vfs; ++i)
> +		if (xe_mmio_is_initialized(&mmio[i]))
> +			xe_mmio_access_fini(&mmio[i]);
>  }
>  
>  static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
>  {
> -	struct xe_mmio xemmio = { };
> -	const unsigned int num_gts = xe_number_gt(pf_fd);
> -	struct ggtt_data gdata[num_gts];
> -	struct lmem_data ldata = {
> -		.base = { .pf_fd = pf_fd, .num_vfs = num_vfs }
> -	};
> -	struct intel_mmio_data mmio[num_vfs + 1];
> -	struct regs_data scratch_data = {
> -		.base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
> -		.mmio = mmio,
> -		.reg_addr = SCRATCH_REG,
> -		.reg_count = SCRATCH_REG_COUNT
> -	};
> -	struct regs_data media_scratch_data = {
> -		.base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
> -		.mmio = mmio,
> -		.reg_addr = MED_SCRATCH_REG,
> -		.reg_count = MED_SCRATCH_REG_COUNT
> -	};
> -	const unsigned int num_checks = num_gts + 3;
> +	struct xe_mmio mmio[num_vfs + 1];
> +	const uint8_t num_tiles = xe_tiles_count(pf_fd);
> +	struct subcheck_data base;
> +	struct ggtt_data gdata[num_tiles];
> +	struct lmem_data ldata[num_tiles];
> +	struct regs_data scratch_data[num_tiles];
> +	struct regs_data media_scratch_data[num_tiles];
> +	const unsigned int subcheck_count = 4;
> +	const unsigned int num_checks =	subcheck_count * num_tiles;
>  	struct subcheck checks[num_checks];
> -	int i = 0, gt_id;
> +	unsigned int i = 0, t;
>  
>  	memset(mmio, 0, sizeof(mmio));
>  
> -	xe_for_each_gt(pf_fd, gt_id) {
> +	xe_for_each_tile(pf_fd, t) {
> +		igt_assert_lt(i, num_tiles);
> +		base = (struct subcheck_data){ .pf_fd = pf_fd,
> +					       .num_vfs = num_vfs,
> +					       .tile = t };
> +
>  		gdata[i] = (struct ggtt_data){
> -			.base = { .pf_fd = pf_fd, .num_vfs = num_vfs, .gt = gt_id },
> -			.mmio = &xemmio
> +			.base = base,
> +			.mmio = mmio,
>  		};
> -		checks[i] = (struct subcheck){
> +		checks[i * subcheck_count + 0] = (struct subcheck){
>  			.data = (struct subcheck_data *)&gdata[i],
>  			.name = "clear-ggtt",
>  			.init = ggtt_subcheck_init,
> @@ -961,33 +932,56 @@ static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
>  			.verify_vf = ggtt_subcheck_verify_vf,
>  			.cleanup = ggtt_subcheck_cleanup
>  		};
> +
> +		ldata[i] = (struct lmem_data){
> +			.base = base,
> +		};
> +		checks[i * subcheck_count + 1] = (struct subcheck){
> +			.data = (struct subcheck_data *)&ldata[i],
> +			.name = "clear-lmem",
> +			.init = lmem_subcheck_init,
> +			.prepare_vf = lmem_subcheck_prepare_vf,
> +			.verify_vf = lmem_subcheck_verify_vf,
> +			.cleanup = lmem_subcheck_cleanup
> +		};
> +
> +		scratch_data[i] = (struct regs_data){
> +			.base = base,
> +			.mmio = mmio,
> +			.reg_addr = SCRATCH_REG,
> +			.reg_count = SCRATCH_REG_COUNT,
> +		};
> +		checks[i * subcheck_count + 2] = (struct subcheck){
> +			.data = (struct subcheck_data *)&scratch_data[i],
> +			.name = "clear-scratch-regs",
> +			.init = regs_subcheck_init,
> +			.prepare_vf = regs_subcheck_prepare_vf,
> +			.verify_vf = regs_subcheck_verify_vf,
> +			.cleanup = regs_subcheck_cleanup
> +		};
> +
> +		media_scratch_data[i] = (struct regs_data){
> +			.base = base,
> +			.mmio = mmio,
> +			.reg_addr = MED_SCRATCH_REG,
> +			.reg_count = MED_SCRATCH_REG_COUNT,
> +		};
> +		checks[i * subcheck_count + 3] = (struct subcheck){
> +			.data = (struct subcheck_data *)&media_scratch_data[i],
> +			.name = "clear-media-scratch-regs",
> +			.init = regs_subcheck_init,
> +			.prepare_vf = regs_subcheck_prepare_vf,
> +			.verify_vf = regs_subcheck_verify_vf,
> +			.cleanup = regs_subcheck_cleanup
> +		};
>  		i++;
>  	}
> -	checks[i++] = (struct subcheck) {
> -		.data = (struct subcheck_data *)&ldata,
> -		.name = "clear-lmem",
> -		.init = lmem_subcheck_init,
> -		.prepare_vf = lmem_subcheck_prepare_vf,
> -		.verify_vf = lmem_subcheck_verify_vf,
> -		.cleanup = lmem_subcheck_cleanup };
> -	checks[i++] = (struct subcheck) {
> -		.data = (struct subcheck_data *)&scratch_data,
> -		.name = "clear-scratch-regs",
> -		.init = regs_subcheck_init,
> -		.prepare_vf = regs_subcheck_prepare_vf,
> -		.verify_vf = regs_subcheck_verify_vf,
> -		.cleanup = regs_subcheck_cleanup };
> -	checks[i++] = (struct subcheck) {
> -		.data = (struct subcheck_data *)&media_scratch_data,
> -		.name = "clear-media-scratch-regs",
> -		.init = regs_subcheck_init,
> -		.prepare_vf = regs_subcheck_prepare_vf,
> -		.verify_vf = regs_subcheck_verify_vf,
> -		.cleanup = regs_subcheck_cleanup
> -	};
> -	igt_assert_eq(i, num_checks);
> +	igt_assert_eq(i, num_tiles);
> +	igt_assert_eq(i * subcheck_count, num_checks);
>  
>  	verify_flr(pf_fd, num_vfs, checks, num_checks, exec_strategy);
> +
> +	cleanup_mmio(mmio, num_vfs);
>  }

One comment above. With a fix:
Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com>


>  
>  igt_main
> -- 
> 2.43.0
> 

-- 

[PATCH i-g-t 5/6] tests/intel/xe_sriov_flr: Use global MMIO context initialized in verify_flr

[Marcin Bernatowicz]

Move MMIO initialization to verify_flr() after VF enable and PCI reinit.
Replace per-subcheck MMIO pointers with a global context accessed via
xe_mmio_for_vf() to simplify resource management.

v2:
 - Switch num_vfs to unsigned int (Piotr)

Suggested-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
---
 tests/intel/xe_sriov_flr.c | 90 ++++++++++++++++++++++++--------------
 1 file changed, 57 insertions(+), 33 deletions(-)

diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
index ee0baa0fa..e69de46c4 100644
--- a/tests/intel/xe_sriov_flr.c
+++ b/tests/intel/xe_sriov_flr.c
@@ -55,6 +55,44 @@ IGT_TEST_DESCRIPTION("Xe tests for SR-IOV VF FLR (Functional Level Reset)");
 
 const char *SKIP_REASON = "SKIP";
 
+static struct g_mmio {
+	struct xe_mmio *mmio;
+	unsigned int num_vfs;
+} g_mmio;
+
+static inline struct xe_mmio *xe_mmio_for_vf(unsigned int vf)
+{
+	igt_assert_f(g_mmio.mmio, "MMIO not initialized\n");
+	igt_assert_f(vf <= g_mmio.num_vfs, "VF%u out of range (<= %u)\n", vf,
+		     g_mmio.num_vfs);
+	return &g_mmio.mmio[vf];
+}
+
+static void init_mmio(int pf_fd, unsigned int num_vfs)
+{
+	igt_assert_f(!g_mmio.mmio, "MMIO already initialized\n");
+	g_mmio.mmio = calloc(num_vfs + 1, sizeof(*g_mmio.mmio));
+	igt_assert(g_mmio.mmio);
+
+	for (unsigned int i = 0; i <= num_vfs; ++i)
+		xe_mmio_vf_access_init(pf_fd, i, &g_mmio.mmio[i]);
+
+	g_mmio.num_vfs = num_vfs;
+}
+
+static void cleanup_mmio(void)
+{
+	if (!g_mmio.mmio)
+		return;
+
+	for (size_t i = 0; i <= g_mmio.num_vfs; ++i)
+		if (xe_mmio_is_initialized(&g_mmio.mmio[i]))
+			xe_mmio_access_fini(&g_mmio.mmio[i]);
+	free(g_mmio.mmio);
+	g_mmio.mmio = NULL;
+	g_mmio.num_vfs = 0;
+}
+
 /**
  * struct subcheck_data - Base structure for subcheck data.
  *
@@ -285,6 +323,8 @@ static void verify_flr(int pf_fd, int num_vfs, struct subcheck *checks,
 	if (igt_warn_on(igt_pci_system_reinit()))
 		goto disable_vfs;
 
+	init_mmio(pf_fd, num_vfs);
+
 	for (i = 0; i < num_checks; ++i)
 		checks[i].init(checks[i].data);
 
@@ -303,6 +343,8 @@ cleanup:
 	for (i = 0; i < num_checks; ++i)
 		checks[i].cleanup(checks[i].data);
 
+	cleanup_mmio();
+
 disable_vfs:
 	igt_sriov_disable_vfs(pf_fd);
 
@@ -489,7 +531,6 @@ struct ggtt_provisioned_offset_range {
 struct ggtt_data {
 	struct subcheck_data base;
 	struct ggtt_provisioned_offset_range *pte_offsets;
-	struct xe_mmio *mmio;
 	struct ggtt_ops ggtt;
 };
 
@@ -544,11 +585,12 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
 	struct xe_sriov_provisioned_range *ranges;
 	uint8_t tile = gdata->base.tile;
 	unsigned int nr_ranges;
+	struct xe_mmio *mmio = xe_mmio_for_vf(0);
 
 	gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
 	igt_assert(gdata->pte_offsets);
 
-	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, tile, gdata->mmio,
+	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, tile, mmio,
 							 &ranges, &nr_ranges);
 	if (ret) {
 		set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges (%d)\n",
@@ -603,19 +645,15 @@ static void ggtt_subcheck_init(struct subcheck_data *data)
 	else
 		gdata->ggtt.set_pte = intel_set_pte;
 
-	if (gdata->mmio) {
-		if (!xe_mmio_is_initialized(&gdata->mmio[0]))
-			xe_mmio_vf_access_init(data->pf_fd, 0 /*PF*/, gdata->mmio);
-
-		populate_ggtt_pte_offsets(gdata);
-	} else {
-		set_skip_reason(data, "xe_mmio is NULL\n");
-	}
+	if (populate_ggtt_pte_offsets(gdata))
+		/* skip reason set in populate_ggtt_pte_offsets */
+		return;
 }
 
 static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
 {
 	struct ggtt_data *gdata = (struct ggtt_data *)data;
+	struct xe_mmio *mmio = xe_mmio_for_vf(0);
 	xe_ggtt_pte_t pte;
 	uint32_t pte_offset;
 
@@ -628,7 +666,7 @@ static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
 		  gdata->pte_offsets[vf_id].end);
 
 	for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
-		if (!set_pte_gpa(&gdata->ggtt, gdata->mmio, data->tile, pte_offset,
+		if (!set_pte_gpa(&gdata->ggtt, mmio, data->tile, pte_offset,
 				 (uint8_t)vf_id, &pte)) {
 			set_skip_reason(data,
 					"Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x\n",
@@ -642,6 +680,7 @@ static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
 {
 	struct ggtt_data *gdata = (struct ggtt_data *)data;
 	uint8_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
+	struct xe_mmio *mmio = xe_mmio_for_vf(0);
 	xe_ggtt_pte_t pte;
 	uint32_t pte_offset;
 
@@ -649,7 +688,7 @@ static void ggtt_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
 		return;
 
 	for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
-		if (!check_pte_gpa(&gdata->ggtt, gdata->mmio, data->tile, pte_offset,
+		if (!check_pte_gpa(&gdata->ggtt, mmio, data->tile, pte_offset,
 				   expected, &pte)) {
 			set_fail_reason(data,
 					"GGTT check after VF%u FLR failed on VF%u: Read PTE: %#" PRIx64 " at offset: %#x\n",
@@ -828,7 +867,6 @@ static void lmem_subcheck_cleanup(struct subcheck_data *data)
 
 struct regs_data {
 	struct subcheck_data base;
-	struct xe_mmio *mmio;
 	uint32_t reg_addr;
 	int reg_count;
 };
@@ -846,6 +884,7 @@ static void regs_subcheck_init(struct subcheck_data *data)
 static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
 {
 	struct regs_data *rdata = (struct regs_data *)data;
+	struct xe_mmio *mmio = xe_mmio_for_vf(vf_id);
 	uint8_t tile = data->tile;
 	uint32_t reg;
 	int i;
@@ -853,14 +892,11 @@ static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
 	if (data->stop_reason)
 		return;
 
-	if (!xe_mmio_is_initialized(&rdata->mmio[vf_id]))
-		xe_mmio_vf_access_init(data->pf_fd, vf_id, &rdata->mmio[vf_id]);
-
 	for (i = 0; i < rdata->reg_count; i++) {
 		reg = rdata->reg_addr + i * 4;
 
-		xe_mmio_tile_write32(&rdata->mmio[vf_id], tile, reg, vf_id);
-		if (xe_mmio_tile_read32(&rdata->mmio[vf_id], tile, reg) != vf_id) {
+		xe_mmio_tile_write32(mmio, tile, reg, vf_id);
+		if (xe_mmio_tile_read32(mmio, tile, reg) != vf_id) {
 			set_skip_reason(data, "Registers write/read check failed on VF%u\n", vf_id);
 			return;
 		}
@@ -871,6 +907,7 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
 {
 	struct regs_data *rdata = (struct regs_data *)data;
 	uint32_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
+	struct xe_mmio *mmio = xe_mmio_for_vf(vf_id);
 	uint32_t reg;
 	int i;
 
@@ -880,7 +917,7 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
 	for (i = 0; i < rdata->reg_count; i++) {
 		reg = rdata->reg_addr + i * 4;
 
-		if (xe_mmio_tile_read32(&rdata->mmio[vf_id], data->tile, reg) != expected) {
+		if (xe_mmio_tile_read32(mmio, data->tile, reg) != expected) {
 			set_fail_reason(data,
 					"Registers check after VF%u FLR failed on VF%u\n",
 					flr_vf_id, vf_id);
@@ -889,18 +926,12 @@ static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_da
 	}
 }
 
-static void regs_subcheck_cleanup(struct subcheck_data *data) { }
-
-static void cleanup_mmio(struct xe_mmio *mmio, int num_vfs)
+static void regs_subcheck_cleanup(struct subcheck_data *data)
 {
-	for (int i = 0; i <= num_vfs; ++i)
-		if (xe_mmio_is_initialized(&mmio[i]))
-			xe_mmio_access_fini(&mmio[i]);
 }
 
 static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
 {
-	struct xe_mmio mmio[num_vfs + 1];
 	const uint8_t num_tiles = xe_tiles_count(pf_fd);
 	struct subcheck_data base;
 	struct ggtt_data gdata[num_tiles];
@@ -912,8 +943,6 @@ static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
 	struct subcheck checks[num_checks];
 	unsigned int i = 0, t;
 
-	memset(mmio, 0, sizeof(mmio));
-
 	xe_for_each_tile(pf_fd, t) {
 		igt_assert_lt(i, num_tiles);
 		base = (struct subcheck_data){ .pf_fd = pf_fd,
@@ -922,7 +951,6 @@ static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
 
 		gdata[i] = (struct ggtt_data){
 			.base = base,
-			.mmio = mmio,
 		};
 		checks[i * subcheck_count + 0] = (struct subcheck){
 			.data = (struct subcheck_data *)&gdata[i],
@@ -947,7 +975,6 @@ static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
 
 		scratch_data[i] = (struct regs_data){
 			.base = base,
-			.mmio = mmio,
 			.reg_addr = SCRATCH_REG,
 			.reg_count = SCRATCH_REG_COUNT,
 		};
@@ -962,7 +989,6 @@ static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
 
 		media_scratch_data[i] = (struct regs_data){
 			.base = base,
-			.mmio = mmio,
 			.reg_addr = MED_SCRATCH_REG,
 			.reg_count = MED_SCRATCH_REG_COUNT,
 		};
@@ -980,8 +1006,6 @@ static void clear_tests(int pf_fd, int num_vfs, flr_exec_strategy exec_strategy)
 	igt_assert_eq(i * subcheck_count, num_checks);
 
 	verify_flr(pf_fd, num_vfs, checks, num_checks, exec_strategy);
-
-	cleanup_mmio(mmio, num_vfs);
 }
 
 igt_main
-- 
2.43.0

[PATCH i-g-t 6/6] tests/intel/xe_sriov_flr: Do not ignore failed prerequisites

[Marcin Bernatowicz]

Mark failed prerequisites with an abort reason and treat them as test
failures instead of skips. This ensures that such cases are caught by CI
rather than silently ignored.

Suggested-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
---
 tests/intel/xe_sriov_flr.c | 59 ++++++++++++++++++++++++--------------
 1 file changed, 37 insertions(+), 22 deletions(-)

diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
index e69de46c4..9868a5b7a 100644
--- a/tests/intel/xe_sriov_flr.c
+++ b/tests/intel/xe_sriov_flr.c
@@ -53,7 +53,9 @@
 
 IGT_TEST_DESCRIPTION("Xe tests for SR-IOV VF FLR (Functional Level Reset)");
 
-const char *SKIP_REASON = "SKIP";
+static const char STOP_REASON_ABORT[] = "ABORT";
+static const char STOP_REASON_FAIL[]  = "FAIL";
+static const char STOP_REASON_SKIP[]  = "SKIP";
 
 static struct g_mmio {
 	struct xe_mmio *mmio;
@@ -196,7 +198,7 @@ static void set_skip_reason(struct subcheck_data *data, const char *format, ...)
 	va_list args;
 
 	va_start(args, format);
-	set_stop_reason_v(data, SKIP_REASON, format, args);
+	set_stop_reason_v(data, STOP_REASON_SKIP, format, args);
 	va_end(args);
 }
 
@@ -206,7 +208,17 @@ static void set_fail_reason(struct subcheck_data *data, const char *format, ...)
 	va_list args;
 
 	va_start(args, format);
-	set_stop_reason_v(data, "FAIL", format, args);
+	set_stop_reason_v(data, STOP_REASON_FAIL, format, args);
+	va_end(args);
+}
+
+__attribute__((format(printf, 2, 3)))
+static void set_abort_reason(struct subcheck_data *data, const char *format, ...)
+{
+	va_list args;
+
+	va_start(args, format);
+	set_stop_reason_v(data, STOP_REASON_ABORT, format, args);
 	va_end(args);
 }
 
@@ -234,7 +246,7 @@ static bool no_subchecks_can_proceed(struct subcheck *checks, int num_checks)
 static bool is_subcheck_skipped(struct subcheck *subcheck)
 {
 	return subcheck->data && subcheck->data->stop_reason &&
-	       !strncmp(SKIP_REASON, subcheck->data->stop_reason, strlen(SKIP_REASON));
+	       !strncmp(STOP_REASON_SKIP, subcheck->data->stop_reason, strlen(STOP_REASON_SKIP));
 }
 
 static void subchecks_report_results(struct subcheck *checks, int num_checks)
@@ -593,8 +605,8 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
 	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, tile, mmio,
 							 &ranges, &nr_ranges);
 	if (ret) {
-		set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges (%d)\n",
-				ret);
+		set_abort_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges (%d)\n",
+				 ret);
 		return -1;
 	}
 
@@ -605,15 +617,17 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
 			continue;
 
 		if (vf_id < 1 || vf_id > num_vfs) {
-			set_skip_reason(&gdata->base, "Unexpected VF%u at range entry %u [%#" PRIx64 "-%#" PRIx64 "], num_vfs=%u\n",
-					vf_id, i, ranges[i].start, ranges[i].end, num_vfs);
+			set_abort_reason(&gdata->base,
+					 "Unexpected VF%u at range entry %u [%#" PRIx64
+					 "-%#" PRIx64 "], num_vfs=%u\n",
+					 vf_id, i, ranges[i].start, ranges[i].end, num_vfs);
 			free(ranges);
 			return -1;
 		}
 
 		if (gdata->pte_offsets[vf_id].end) {
-			set_skip_reason(&gdata->base, "Duplicate GGTT PTE offset range for VF%u\n",
-					vf_id);
+			set_abort_reason(&gdata->base, "Duplicate GGTT PTE offset range for VF%u\n",
+					 vf_id);
 			free(ranges);
 			return -1;
 		}
@@ -626,9 +640,9 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
 
 	for (int vf_id = 1; vf_id <= num_vfs; ++vf_id)
 		if (!gdata->pte_offsets[vf_id].end) {
-			set_skip_reason(&gdata->base,
-					"Failed to find VF%u provisioned GGTT PTE offset range\n",
-					vf_id);
+			set_abort_reason(&gdata->base,
+					 "Failed to find VF%u provisioned GGTT PTE offset range\n",
+					 vf_id);
 			return -1;
 		}
 
@@ -668,9 +682,9 @@ static void ggtt_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
 	for_each_pte_offset(pte_offset, &gdata->pte_offsets[vf_id]) {
 		if (!set_pte_gpa(&gdata->ggtt, mmio, data->tile, pte_offset,
 				 (uint8_t)vf_id, &pte)) {
-			set_skip_reason(data,
-					"Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x\n",
-					vf_id, pte, pte_offset);
+			set_abort_reason(data,
+					 "Prepare VF%u failed, unexpected gpa: Read PTE: %#" PRIx64 " at offset: %#x\n",
+					 vf_id, pte, pte_offset);
 			return;
 		}
 	}
@@ -782,9 +796,9 @@ static int populate_vf_lmem_sizes(struct subcheck_data *data)
 							  XE_SRIOV_SHARED_RES_LMEM,
 							  main_gt, &ranges, &nr_ranges);
 	if (ret) {
-		set_skip_reason(data, "Failed read %s on main GT (%d)\n",
-				xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
-				ret);
+		set_abort_reason(data, "Failed read %s on main GT (%d)\n",
+				 xe_sriov_debugfs_provisioned_attr_name(XE_SRIOV_SHARED_RES_LMEM),
+				 ret);
 		return -1;
 	}
 
@@ -800,7 +814,7 @@ static int populate_vf_lmem_sizes(struct subcheck_data *data)
 
 	for (int vf_id = 1; vf_id <= data->num_vfs; ++vf_id)
 		if (!ldata->vf_lmem_size[vf_id]) {
-			set_skip_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
+			set_abort_reason(data, "No LMEM provisioned for VF%u\n", vf_id);
 			return -1;
 		}
 
@@ -833,7 +847,7 @@ static void lmem_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
 
 	if (!lmem_mmap_write_munmap(data->pf_fd, vf_id,
 				    ldata->vf_lmem_size[vf_id], vf_id)) {
-		set_skip_reason(data, "LMEM write failed on VF%u\n", vf_id);
+		set_abort_reason(data, "LMEM write failed on VF%u\n", vf_id);
 	}
 }
 
@@ -897,7 +911,8 @@ static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
 
 		xe_mmio_tile_write32(mmio, tile, reg, vf_id);
 		if (xe_mmio_tile_read32(mmio, tile, reg) != vf_id) {
-			set_skip_reason(data, "Registers write/read check failed on VF%u\n", vf_id);
+			set_abort_reason(data, "Registers write/read check failed on VF%u\n",
+					 vf_id);
 			return;
 		}
 	}
-- 
2.43.0

✓ Xe.CI.BAT: success for Multi-tile support for xe_sriov_flr and related MMIO improvements (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2420 bytes --]

== Series Details ==

Series: Multi-tile support for xe_sriov_flr and related MMIO improvements (rev2)
URL   : https://patchwork.freedesktop.org/series/156839/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8613_BAT -> XEIGTPW_14017_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_14017_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-plain-flip@a-edp1:
    - bat-adlp-7:         [PASS][1] -> [DMESG-WARN][2] ([Intel XE#4543]) +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/bat-adlp-7/igt@kms_flip@basic-plain-flip@a-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/bat-adlp-7/igt@kms_flip@basic-plain-flip@a-edp1.html

  * igt@xe_waitfence@abstime:
    - bat-dg2-oem2:       [PASS][3] -> [TIMEOUT][4] ([Intel XE#6506])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/bat-dg2-oem2/igt@xe_waitfence@abstime.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/bat-dg2-oem2/igt@xe_waitfence@abstime.html

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [PASS][5] -> [FAIL][6] ([Intel XE#6519])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519


Build changes
-------------

  * IGT: IGT_8613 -> IGTPW_14017
  * Linux: xe-4058-6aa8d62a50c33f091548cc961a713223d488d6ad -> xe-4060-9deffe4baace482f9414f36f53f3385868533fd6

  IGTPW_14017: 14017
  IGT_8613: b542242f5b116e3b554b4068ef5dfa4451075b2b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4058-6aa8d62a50c33f091548cc961a713223d488d6ad: 6aa8d62a50c33f091548cc961a713223d488d6ad
  xe-4060-9deffe4baace482f9414f36f53f3385868533fd6: 9deffe4baace482f9414f36f53f3385868533fd6

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/index.html

[-- Attachment #2: Type: text/html, Size: 3055 bytes --]

✓ i915.CI.BAT: success for Multi-tile support for xe_sriov_flr and related MMIO improvements (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9541 bytes --]

== Series Details ==

Series: Multi-tile support for xe_sriov_flr and related MMIO improvements (rev2)
URL   : https://patchwork.freedesktop.org/series/156839/
State : success

== Summary ==

CI Bug Log - changes from IGT_8613 -> IGTPW_14017
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/index.html

Participating hosts (43 -> 42)
------------------------------

  Additional (1): bat-adlp-6 
  Missing    (2): bat-rplp-1 fi-snb-2520m 

Known issues
------------

  Here are the changes found in IGTPW_14017 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-mtlp-9:         NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - bat-adlp-6:         NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-adlp-6/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_mmap@basic:
    - bat-mtlp-9:         NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@gem_mmap@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-mtlp-9:         NOTRUN -> [SKIP][4] ([i915#4079]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-mtlp-9:         NOTRUN -> [SKIP][5] ([i915#4077]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-adlp-6:         NOTRUN -> [SKIP][6] ([i915#3282])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-adlp-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-adlp-6:         NOTRUN -> [SKIP][7] ([i915#6621])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-adlp-6/igt@i915_pm_rps@basic-api.html
    - bat-mtlp-9:         NOTRUN -> [SKIP][8] ([i915#11681] / [i915#6621])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [PASS][9] -> [DMESG-FAIL][10] ([i915#12061]) +1 other test dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8613/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-dg2-9/igt@i915_selftest@live@workarounds.html
    - bat-arls-6:         [PASS][11] -> [DMESG-FAIL][12] ([i915#12061]) +1 other test dmesg-fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8613/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-arls-6/igt@i915_selftest@live@workarounds.html

  * igt@intel_hwmon@hwmon-read:
    - bat-mtlp-9:         NOTRUN -> [SKIP][13] ([i915#7707]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@intel_hwmon@hwmon-read.html
    - bat-adlp-6:         NOTRUN -> [SKIP][14] ([i915#7707]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-adlp-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-mtlp-9:         NOTRUN -> [SKIP][15] ([i915#5190])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-mtlp-9:         NOTRUN -> [SKIP][16] ([i915#4212]) +8 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-mtlp-9:         NOTRUN -> [SKIP][17] ([i915#4213]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-adlp-6:         NOTRUN -> [SKIP][18] ([i915#4103]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-adlp-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-mtlp-9:         NOTRUN -> [SKIP][19] ([i915#3555] / [i915#3840] / [i915#9159])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-mtlp-9:         NOTRUN -> [SKIP][20]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@kms_force_connector_basic@force-load-detect.html
    - bat-adlp-6:         NOTRUN -> [SKIP][21]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-adlp-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - bat-mtlp-9:         NOTRUN -> [SKIP][22] ([i915#4077] / [i915#9688]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-adlp-6:         NOTRUN -> [SKIP][23] ([i915#3555])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-adlp-6/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-mtlp-9:         NOTRUN -> [SKIP][24] ([i915#3555] / [i915#8809])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-gtt:
    - bat-mtlp-9:         NOTRUN -> [SKIP][25] ([i915#3708] / [i915#4077]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@basic-read:
    - bat-mtlp-9:         NOTRUN -> [SKIP][26] ([i915#3708]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - bat-adlp-6:         NOTRUN -> [SKIP][27] ([i915#3291] / [i915#3708]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-adlp-6/igt@prime_vgem@basic-write.html
    - bat-mtlp-9:         NOTRUN -> [SKIP][28] ([i915#10216] / [i915#3708])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@i915_module_load@load:
    - bat-mtlp-9:         [ABORT][29] ([i915#13494]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8613/bat-mtlp-9/igt@i915_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-9/igt@i915_module_load@load.html

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [DMESG-FAIL][31] ([i915#12061]) -> [PASS][32] +1 other test pass
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8613/bat-mtlp-8/igt@i915_selftest@live.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/bat-mtlp-8/igt@i915_selftest@live.html

  
  [i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
  [i915#9159]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9159
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8613 -> IGTPW_14017
  * Linux: CI_DRM_17499 -> CI_DRM_17501

  CI-20190529: 20190529
  CI_DRM_17499: 6aa8d62a50c33f091548cc961a713223d488d6ad @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_17501: 9deffe4baace482f9414f36f53f3385868533fd6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_14017: 14017
  IGT_8613: b542242f5b116e3b554b4068ef5dfa4451075b2b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/index.html

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✗ i915.CI.Full: failure for Multi-tile support for xe_sriov_flr and related MMIO improvements (rev2)

[Patchwork]

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== Series Details ==

Series: Multi-tile support for xe_sriov_flr and related MMIO improvements (rev2)
URL   : https://patchwork.freedesktop.org/series/156839/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17501_full -> IGTPW_14017_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_14017_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_14017_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/index.html

Participating hosts (11 -> 10)
------------------------------

  Missing    (1): shard-dg2-set2 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_14017_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_flink_race@flink_close:
    - shard-dg1:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg1-15/igt@gem_flink_race@flink_close.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-19/igt@gem_flink_race@flink_close.html

  * igt@kms_async_flips@async-flip-hang:
    - shard-dg2:          [PASS][3] -> [INCOMPLETE][4] +1 other test incomplete
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-3/igt@kms_async_flips@async-flip-hang.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@kms_async_flips@async-flip-hang.html

  * igt@panthor/panthor_vm@vm_destroy_invalid:
    - shard-dg2:          NOTRUN -> [SKIP][5] +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@panthor/panthor_vm@vm_destroy_invalid.html

  
New tests
---------

  New tests have been introduced between CI_DRM_17501_full and IGTPW_14017_full:

### New IGT tests (3) ###

  * igt@kms_cursor_crc@cursor-onscreen-64x64@pipe-a-vga-1:
    - Statuses : 1 pass(s)
    - Exec time: [2.29] s

  * igt@kms_invalid_mode@bad-hsync-end@pipe-a-vga-1:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_invalid_mode@bad-hsync-end@pipe-b-vga-1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_14017_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-dg2:          NOTRUN -> [SKIP][6] ([i915#8411])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-tglu-1:       NOTRUN -> [SKIP][7] ([i915#11078])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@drm_buddy@drm_buddy@drm_test_buddy_fragmentation_performance:
    - shard-snb:          NOTRUN -> [DMESG-WARN][8] ([i915#15095]) +1 other test dmesg-warn
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-snb6/igt@drm_buddy@drm_buddy@drm_test_buddy_fragmentation_performance.html

  * igt@fbdev@unaligned-read:
    - shard-rkl:          [PASS][9] -> [SKIP][10] ([i915#14544] / [i915#2582])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-4/igt@fbdev@unaligned-read.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@fbdev@unaligned-read.html

  * igt@gem_bad_reloc@negative-reloc-lut:
    - shard-rkl:          NOTRUN -> [SKIP][11] ([i915#14544] / [i915#3281])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_bad_reloc@negative-reloc-lut.html

  * igt@gem_basic@multigpu-create-close:
    - shard-dg2:          NOTRUN -> [SKIP][12] ([i915#7697])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-5/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-tglu:         NOTRUN -> [SKIP][13] ([i915#9323])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-4/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@suspend-resume:
    - shard-tglu-1:       NOTRUN -> [SKIP][14] ([i915#9323])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@gem_ccs@suspend-resume.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          NOTRUN -> [SKIP][15] ([i915#7697])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_freq@sysfs@gt0:
    - shard-dg2:          NOTRUN -> [FAIL][16] ([i915#9561]) +1 other test fail
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@gem_ctx_freq@sysfs@gt0.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-tglu-1:       NOTRUN -> [SKIP][17] +29 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-tglu-1:       NOTRUN -> [SKIP][18] ([i915#280])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-tglu:         NOTRUN -> [SKIP][19] ([i915#280])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-8/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_eio@kms:
    - shard-tglu:         NOTRUN -> [DMESG-WARN][20] ([i915#13363])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-3/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@bonded-sync:
    - shard-dg2:          NOTRUN -> [SKIP][21] ([i915#4771]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@gem_exec_balancer@bonded-sync.html

  * igt@gem_exec_balancer@noheartbeat:
    - shard-dg2:          NOTRUN -> [SKIP][22] ([i915#8555])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@gem_exec_balancer@noheartbeat.html
    - shard-dg1:          NOTRUN -> [SKIP][23] ([i915#8555])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-16/igt@gem_exec_balancer@noheartbeat.html
    - shard-mtlp:         NOTRUN -> [SKIP][24] ([i915#8555])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-3/igt@gem_exec_balancer@noheartbeat.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-tglu-1:       NOTRUN -> [SKIP][25] ([i915#4525])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-tglu:         NOTRUN -> [SKIP][26] ([i915#4525])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-6/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-tglu-1:       NOTRUN -> [SKIP][27] ([i915#6334]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_fence@submit67:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#4812]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@gem_exec_fence@submit67.html

  * igt@gem_exec_fence@syncobj-backward-timeline-chain-engines:
    - shard-snb:          NOTRUN -> [SKIP][29] +107 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-snb7/igt@gem_exec_fence@syncobj-backward-timeline-chain-engines.html

  * igt@gem_exec_flush@basic-wb-rw-before-default:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#3539] / [i915#4852]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@gem_exec_flush@basic-wb-rw-before-default.html

  * igt@gem_exec_reloc@basic-gtt-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][31] ([i915#3281]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-cpu.html
    - shard-dg1:          NOTRUN -> [SKIP][32] ([i915#3281]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@gem_exec_reloc@basic-gtt-cpu.html
    - shard-mtlp:         NOTRUN -> [SKIP][33] ([i915#3281])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-3/igt@gem_exec_reloc@basic-gtt-cpu.html

  * igt@gem_exec_reloc@basic-wc-gtt-active:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#3281]) +10 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@gem_exec_reloc@basic-wc-gtt-active.html

  * igt@gem_exec_schedule@preempt-queue-chain:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#4537] / [i915#4812])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@gem_exec_schedule@preempt-queue-chain.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-glk:          NOTRUN -> [INCOMPLETE][36] ([i915#13196] / [i915#13356]) +1 other test incomplete
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk5/igt@gem_exec_suspend@basic-s3.html
    - shard-rkl:          [PASS][37] -> [INCOMPLETE][38] ([i915#13356]) +1 other test incomplete
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@gem_exec_suspend@basic-s3.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-3/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_fenced_exec_thrash@no-spare-fences:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#4860])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@gem_fenced_exec_thrash@no-spare-fences.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-tglu:         NOTRUN -> [SKIP][40] ([i915#4613] / [i915#7582])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-9/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-rkl:          NOTRUN -> [SKIP][41] ([i915#14544] / [i915#4613])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - shard-mtlp:         NOTRUN -> [SKIP][42] ([i915#4613])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-5/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-tglu:         NOTRUN -> [SKIP][43] ([i915#4613]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-3/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][44] ([i915#4613]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-glk:          NOTRUN -> [SKIP][45] ([i915#4613]) +5 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk9/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@verify:
    - shard-rkl:          NOTRUN -> [SKIP][46] ([i915#4613]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@gem_lmem_swapping@verify.html

  * igt@gem_media_vme:
    - shard-tglu:         NOTRUN -> [SKIP][47] ([i915#284])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-3/igt@gem_media_vme.html

  * igt@gem_mmap_gtt@zero-extend:
    - shard-dg2:          NOTRUN -> [SKIP][48] ([i915#4077]) +8 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@gem_mmap_gtt@zero-extend.html

  * igt@gem_mmap_wc@close:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#4083]) +3 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@gem_mmap_wc@close.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-tglu:         NOTRUN -> [WARN][50] ([i915#2658])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-7/igt@gem_pwrite@basic-exhaustion.html
    - shard-glk10:        NOTRUN -> [WARN][51] ([i915#14702] / [i915#2658])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk10/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pwrite_snooped:
    - shard-rkl:          NOTRUN -> [SKIP][52] ([i915#3282]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@gem_pwrite_snooped.html

  * igt@gem_pxp@display-protected-crc:
    - shard-rkl:          [PASS][53] -> [TIMEOUT][54] ([i915#12917] / [i915#12964]) +2 other tests timeout
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@gem_pxp@display-protected-crc.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@gem_pxp@display-protected-crc.html

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#4270]) +4 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@gem_pxp@reject-modify-context-protection-off-1.html
    - shard-rkl:          [PASS][56] -> [SKIP][57] ([i915#4270])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-1.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@gem_pxp@reject-modify-context-protection-off-1.html

  * igt@gem_readwrite@write-bad-handle:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#3282]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@gem_readwrite@write-bad-handle.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][59] ([i915#8428])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-7/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#5190] / [i915#8428]) +5 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][61] ([i915#4079]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html

  * igt@gem_softpin@evict-snoop:
    - shard-rkl:          NOTRUN -> [SKIP][62] +6 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@gem_softpin@evict-snoop.html
    - shard-dg1:          NOTRUN -> [SKIP][63] ([i915#4885])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-17/igt@gem_softpin@evict-snoop.html
    - shard-mtlp:         NOTRUN -> [SKIP][64] ([i915#4885])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-7/igt@gem_softpin@evict-snoop.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([i915#4885]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_tiled_wb:
    - shard-dg1:          NOTRUN -> [SKIP][66] ([i915#4077])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-17/igt@gem_tiled_wb.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][67] ([i915#3297]) +1 other test skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-tglu:         NOTRUN -> [SKIP][68] ([i915#3297] / [i915#3323])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-2/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-glk:          NOTRUN -> [SKIP][69] ([i915#3323])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk9/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][70] ([i915#3297]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_userptr_blits@unsync-unmap:
    - shard-dg1:          NOTRUN -> [SKIP][71] ([i915#3297])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-18/igt@gem_userptr_blits@unsync-unmap.html
    - shard-tglu:         NOTRUN -> [SKIP][72] ([i915#3297])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-3/igt@gem_userptr_blits@unsync-unmap.html
    - shard-mtlp:         NOTRUN -> [SKIP][73] ([i915#3297])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-5/igt@gem_userptr_blits@unsync-unmap.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-rkl:          [PASS][74] -> [ABORT][75] ([i915#15152])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@gem_workarounds@suspend-resume-fd.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-4/igt@gem_workarounds@suspend-resume-fd.html
    - shard-glk:          [PASS][76] -> [INCOMPLETE][77] ([i915#13356] / [i915#14586])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-glk1/igt@gem_workarounds@suspend-resume-fd.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk9/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen7_exec_parse@basic-allocation:
    - shard-mtlp:         NOTRUN -> [SKIP][78] +2 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-6/igt@gen7_exec_parse@basic-allocation.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-dg2:          NOTRUN -> [SKIP][79] ([i915#2856]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@gen9_exec_parse@allowed-single.html
    - shard-rkl:          NOTRUN -> [SKIP][80] ([i915#14544] / [i915#2527])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gen9_exec_parse@allowed-single.html
    - shard-tglu-1:       NOTRUN -> [SKIP][81] ([i915#2527] / [i915#2856]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@gen9_exec_parse@allowed-single.html
    - shard-dg1:          NOTRUN -> [SKIP][82] ([i915#2527])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@gen9_exec_parse@allowed-single.html
    - shard-mtlp:         NOTRUN -> [SKIP][83] ([i915#2856])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-8/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@basic-rejected-ctx-param:
    - shard-tglu:         NOTRUN -> [SKIP][84] ([i915#2527] / [i915#2856]) +3 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-6/igt@gen9_exec_parse@basic-rejected-ctx-param.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-rkl:          NOTRUN -> [SKIP][85] ([i915#2527])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@gen9_exec_parse@secure-batches.html

  * igt@i915_drm_fdinfo@all-busy-idle-check-all:
    - shard-dg2:          NOTRUN -> [SKIP][86] ([i915#14123]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@i915_drm_fdinfo@all-busy-idle-check-all.html

  * igt@i915_drm_fdinfo@busy-check-all@vecs0:
    - shard-dg2:          NOTRUN -> [SKIP][87] ([i915#11527]) +7 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@i915_drm_fdinfo@busy-check-all@vecs0.html

  * igt@i915_drm_fdinfo@busy@vecs1:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([i915#14073]) +7 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@i915_drm_fdinfo@busy@vecs1.html

  * igt@i915_drm_fdinfo@virtual-busy-idle-all:
    - shard-dg2:          NOTRUN -> [SKIP][89] ([i915#14118])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@i915_drm_fdinfo@virtual-busy-idle-all.html

  * igt@i915_module_load@reload-no-display:
    - shard-dg2:          NOTRUN -> [DMESG-WARN][90] ([i915#13029] / [i915#14545])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@i915_module_load@reload-no-display.html

  * igt@i915_module_load@resize-bar:
    - shard-dg2:          NOTRUN -> [DMESG-WARN][91] ([i915#14545])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-rkl:          NOTRUN -> [SKIP][92] ([i915#14544] / [i915#8399])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@i915_pm_freq_api@freq-reset-multiple.html
    - shard-tglu:         NOTRUN -> [SKIP][93] ([i915#8399]) +1 other test skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-6/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-dg2:          NOTRUN -> [FAIL][94] ([i915#12964]) +1 other test fail
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_pm_rps@thresholds-idle:
    - shard-dg2:          NOTRUN -> [SKIP][95] ([i915#11681])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@i915_pm_rps@thresholds-idle.html

  * igt@i915_selftest@live@workarounds:
    - shard-dg2:          [PASS][96] -> [DMESG-FAIL][97] ([i915#12061]) +1 other test dmesg-fail
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-11/igt@i915_selftest@live@workarounds.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@i915_selftest@live@workarounds.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-dg1:          [PASS][98] -> [DMESG-WARN][99] ([i915#4391] / [i915#4423])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg1-12/igt@i915_suspend@basic-s3-without-i915.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-16/igt@i915_suspend@basic-s3-without-i915.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-glk:          NOTRUN -> [INCOMPLETE][100] ([i915#4817])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk1/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][101] ([i915#4212]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-tglu-1:       NOTRUN -> [SKIP][102] ([i915#12454] / [i915#12712])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-rkl:          [PASS][103] -> [INCOMPLETE][104] ([i915#12761] / [i915#12964])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_async_flips@async-flip-suspend-resume.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_async_flips@async-flip-suspend-resume.html
    - shard-glk:          NOTRUN -> [INCOMPLETE][105] ([i915#12761]) +1 other test incomplete
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk9/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][106] ([i915#12761] / [i915#12964])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-2.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-mtlp:         NOTRUN -> [SKIP][107] ([i915#1769] / [i915#3555])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-glk:          NOTRUN -> [SKIP][108] ([i915#1769])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
    - shard-dg2:          NOTRUN -> [SKIP][109] ([i915#1769] / [i915#3555])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
    - shard-tglu-1:       NOTRUN -> [SKIP][110] ([i915#1769] / [i915#3555])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3:
    - shard-dg2:          [PASS][111] -> [FAIL][112] ([i915#5956]) +1 other test fail
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-6/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#4538] / [i915#5286]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-15/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][114] ([i915#5286]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-mtlp:         [PASS][115] -> [FAIL][116] ([i915#12469] / [i915#5138])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-mtlp-4/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-3/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][117] ([i915#5286]) +4 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-tglu-1:       NOTRUN -> [SKIP][118] ([i915#5286]) +2 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-0:
    - shard-dg2:          NOTRUN -> [SKIP][119] ([i915#4538] / [i915#5190]) +12 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#3638])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
    - shard-dg1:          NOTRUN -> [SKIP][121] ([i915#3638]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-12/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2:          NOTRUN -> [SKIP][122] ([i915#5190]) +2 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][123] +43 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
    - shard-dg1:          NOTRUN -> [SKIP][124] ([i915#4538])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-19/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][125] ([i915#12313])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-5/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
    - shard-glk:          NOTRUN -> [SKIP][126] +350 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk1/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([i915#10307] / [i915#6095]) +180 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-dp-3.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][128] ([i915#12313]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][129] ([i915#14098] / [i915#6095]) +49 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][130] ([i915#6095]) +14 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-3/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#12805])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([i915#12805])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-8/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][133] ([i915#6095]) +48 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][134] ([i915#6095]) +11 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][135] ([i915#12313])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][136] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][137] ([i915#6095]) +14 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][138] ([i915#6095]) +152 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-13/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][139] ([i915#6095]) +54 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-8/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][140] ([i915#13781]) +4 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#13783]) +4 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-3/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html

  * igt@kms_chamelium_color@degamma:
    - shard-dg2:          NOTRUN -> [SKIP][142] +13 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-5/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-tglu-1:       NOTRUN -> [SKIP][143] ([i915#11151] / [i915#7828]) +2 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-tglu:         NOTRUN -> [SKIP][144] ([i915#11151] / [i915#7828]) +4 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-3/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@dp-hpd-fast:
    - shard-rkl:          NOTRUN -> [SKIP][145] ([i915#11151] / [i915#7828]) +2 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_chamelium_hpd@dp-hpd-fast.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#11151] / [i915#7828]) +7 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@kms_chamelium_hpd@dp-hpd-storm.html
    - shard-rkl:          NOTRUN -> [SKIP][147] ([i915#11151] / [i915#14544] / [i915#7828])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd-storm.html
    - shard-dg1:          NOTRUN -> [SKIP][148] ([i915#11151] / [i915#7828]) +1 other test skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@kms_chamelium_hpd@dp-hpd-storm.html
    - shard-mtlp:         NOTRUN -> [SKIP][149] ([i915#11151] / [i915#7828]) +1 other test skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-8/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_color@ctm-max:
    - shard-rkl:          [PASS][150] -> [SKIP][151] ([i915#12655] / [i915#14544])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_color@ctm-max.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_color@ctm-max.html

  * igt@kms_color@deep-color:
    - shard-dg2:          NOTRUN -> [SKIP][152] ([i915#12655] / [i915#3555])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@kms_color@deep-color.html
    - shard-rkl:          NOTRUN -> [SKIP][153] ([i915#12655] / [i915#3555])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_color@deep-color.html
    - shard-dg1:          NOTRUN -> [SKIP][154] ([i915#12655] / [i915#3555])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@kms_color@deep-color.html
    - shard-tglu:         NOTRUN -> [SKIP][155] ([i915#3555] / [i915#9979])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-3/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [FAIL][156] ([i915#7173]) +1 other test fail
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@kms_content_protection@atomic-dpms@pipe-a-dp-3.html

  * igt@kms_content_protection@content-type-change:
    - shard-dg2:          NOTRUN -> [SKIP][157] ([i915#9424])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@legacy:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#7118] / [i915#9424])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-4/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@cursor-onscreen-256x256:
    - shard-rkl:          [PASS][159] -> [SKIP][160] ([i915#14544]) +54 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_cursor_crc@cursor-onscreen-256x256.html
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-256x256.html

  * igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][161] -> [FAIL][162] ([i915#13566]) +1 other test fail
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-tglu-9/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-10/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#13049]) +1 other test skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-rkl:          NOTRUN -> [SKIP][164] ([i915#13049])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-rkl:          [PASS][165] -> [FAIL][166] ([i915#13566])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-3/igt@kms_cursor_crc@cursor-sliding-256x85.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][167] ([i915#13566])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-dg2:          NOTRUN -> [SKIP][168] ([i915#3555]) +4 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@kms_cursor_crc@cursor-sliding-32x10.html
    - shard-tglu-1:       NOTRUN -> [SKIP][169] ([i915#3555]) +1 other test skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-32x10.html
    - shard-dg1:          NOTRUN -> [SKIP][170] ([i915#3555]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-19/igt@kms_cursor_crc@cursor-sliding-32x10.html
    - shard-mtlp:         NOTRUN -> [SKIP][171] ([i915#3555] / [i915#8814])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-5/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-32x32:
    - shard-tglu:         NOTRUN -> [SKIP][172] ([i915#3555]) +4 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-5/igt@kms_cursor_crc@cursor-sliding-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-tglu-1:       NOTRUN -> [SKIP][173] ([i915#13049]) +1 other test skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - shard-rkl:          [PASS][174] -> [SKIP][175] ([i915#11190] / [i915#14544]) +2 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][176] ([i915#13046] / [i915#5354]) +3 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
    - shard-mtlp:         NOTRUN -> [SKIP][177] ([i915#9809])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-7/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-tglu-1:       NOTRUN -> [SKIP][178] ([i915#9067])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][179] ([i915#4103] / [i915#4213]) +2 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-tglu:         NOTRUN -> [SKIP][180] ([i915#9723])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-3/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-tglu-1:       NOTRUN -> [SKIP][181] ([i915#1769] / [i915#3555] / [i915#3804])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][182] ([i915#3804])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dp_aux_dev:
    - shard-dg2:          [PASS][183] -> [SKIP][184] ([i915#1257])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-11/igt@kms_dp_aux_dev.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@kms_dp_aux_dev.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-tglu:         NOTRUN -> [SKIP][185] ([i915#13749])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-10/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-tglu:         NOTRUN -> [SKIP][186] ([i915#13748]) +1 other test skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-4/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-rkl:          NOTRUN -> [SKIP][187] ([i915#3840])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-dg2:          NOTRUN -> [SKIP][188] ([i915#3555] / [i915#3840])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          NOTRUN -> [SKIP][189] ([i915#3555] / [i915#3840])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-dg2:          [PASS][190] -> [FAIL][191] ([i915#4767])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-4/igt@kms_fbcon_fbt@fbc-suspend.html
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-dg2:          NOTRUN -> [SKIP][192] ([i915#9337])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@kms_feature_discovery@dp-mst.html
    - shard-rkl:          NOTRUN -> [SKIP][193] ([i915#14544] / [i915#9337])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_feature_discovery@dp-mst.html
    - shard-dg1:          NOTRUN -> [SKIP][194] ([i915#9337])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-18/igt@kms_feature_discovery@dp-mst.html
    - shard-tglu:         NOTRUN -> [SKIP][195] ([i915#9337])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-6/igt@kms_feature_discovery@dp-mst.html
    - shard-mtlp:         NOTRUN -> [SKIP][196] ([i915#9337])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-6/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-tglu-1:       NOTRUN -> [SKIP][197] ([i915#658])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_feature_discovery@psr1.html

  * igt@kms_fence_pin_leak:
    - shard-dg2:          NOTRUN -> [SKIP][198] ([i915#4881])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@kms_fence_pin_leak.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-rkl:          NOTRUN -> [SKIP][199] ([i915#9934]) +2 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-mtlp:         NOTRUN -> [SKIP][200] ([i915#3637] / [i915#9934])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-5/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-dg1:          NOTRUN -> [SKIP][201] ([i915#9934]) +1 other test skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-16/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-glk:          NOTRUN -> [INCOMPLETE][202] ([i915#12745] / [i915#4839])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk6/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
    - shard-snb:          [PASS][203] -> [TIMEOUT][204] ([i915#14033] / [i915#14350])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-snb7/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-snb4/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][205] ([i915#4839])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk6/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1:
    - shard-snb:          [PASS][206] -> [TIMEOUT][207] ([i915#14033])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-snb7/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1.html
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-snb4/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][208] ([i915#9934]) +8 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@2x-nonexisting-fb-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][209] ([i915#3637] / [i915#9934]) +4 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-6/igt@kms_flip@2x-nonexisting-fb-interruptible.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][210] ([i915#14544] / [i915#9934]) +1 other test skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][211] ([i915#12964]) +5 other tests dmesg-warn
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-dpms-on-nop-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][212] ([i915#14544] / [i915#3637])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-rkl:          [PASS][213] -> [SKIP][214] ([i915#14544] / [i915#3637]) +9 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][215] ([i915#8381])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling:
    - shard-rkl:          [PASS][216] -> [SKIP][217] ([i915#14544] / [i915#3555]) +3 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][218] ([i915#2672] / [i915#3555] / [i915#5190]) +3 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][219] ([i915#2672]) +5 other tests skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][220] ([i915#2672] / [i915#3555]) +1 other test skip
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
    - shard-dg1:          [PASS][221] -> [DMESG-WARN][222] ([i915#4423]) +2 other tests dmesg-warn
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg1-14/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][223] ([i915#2587] / [i915#2672]) +1 other test skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][224] ([i915#2672] / [i915#3555])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][225] ([i915#2587] / [i915#2672])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][226] ([i915#2672]) +3 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-rkl:          [PASS][227] -> [SKIP][228] ([i915#14544] / [i915#1849] / [i915#5354]) +8 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
    - shard-dg2:          NOTRUN -> [SKIP][229] ([i915#5354]) +29 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
    - shard-dg1:          NOTRUN -> [SKIP][230] +11 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][231] ([i915#8708]) +17 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][232] ([i915#1825]) +8 other tests skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-snb:          [PASS][233] -> [SKIP][234] +2 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
    - shard-dg2:          [PASS][235] -> [FAIL][236] ([i915#6880])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][237] ([i915#15102]) +1 other test skip
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][238] ([i915#15102])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][239] ([i915#8708]) +6 other tests skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][240] ([i915#1825]) +19 other tests skip
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
    - shard-mtlp:         NOTRUN -> [SKIP][241] ([i915#8708]) +1 other test skip
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][242] ([i915#15102]) +2 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
    - shard-dg1:          NOTRUN -> [SKIP][243] ([i915#15104])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
    - shard-mtlp:         NOTRUN -> [SKIP][244] ([i915#15104])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-4/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-render:
    - shard-tglu:         NOTRUN -> [SKIP][245] ([i915#15102]) +17 other tests skip
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-gtt:
    - shard-tglu-1:       NOTRUN -> [SKIP][246] ([i915#15102]) +12 other tests skip
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][247] ([i915#15104]) +1 other test skip
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][248] ([i915#10433] / [i915#15102] / [i915#3458])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][249] ([i915#14544] / [i915#1849] / [i915#5354]) +12 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite:
    - shard-glk10:        NOTRUN -> [SKIP][250] +134 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk10/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
    - shard-dg2:          NOTRUN -> [SKIP][251] ([i915#15102] / [i915#3458]) +18 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][252] ([i915#15102] / [i915#3023]) +8 other tests skip
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-suspend.html
    - shard-dg1:          NOTRUN -> [SKIP][253] ([i915#15102] / [i915#3458]) +1 other test skip
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_hdr@static-swap:
    - shard-dg2:          [PASS][254] -> [SKIP][255] ([i915#3555] / [i915#8228])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-11/igt@kms_hdr@static-swap.html
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-5/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][256] ([i915#3555] / [i915#8228])
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@kms_hdr@static-toggle.html

  * igt@kms_invalid_mode@zero-clock:
    - shard-rkl:          [PASS][257] -> [SKIP][258] ([i915#14544] / [i915#3555] / [i915#8826]) +1 other test skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_invalid_mode@zero-clock.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_invalid_mode@zero-clock.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][259] ([i915#10656] / [i915#14544])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_joiner@basic-big-joiner.html
    - shard-dg1:          NOTRUN -> [SKIP][260] ([i915#10656])
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-17/igt@kms_joiner@basic-big-joiner.html
    - shard-tglu:         NOTRUN -> [SKIP][261] ([i915#10656]) +1 other test skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-5/igt@kms_joiner@basic-big-joiner.html
    - shard-mtlp:         NOTRUN -> [SKIP][262] ([i915#10656])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-4/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][263] ([i915#12388])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][264] ([i915#13688])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][265] ([i915#12339])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg1:          NOTRUN -> [SKIP][266] ([i915#12388])
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-16/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][267] ([i915#10656]) +1 other test skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
    - shard-tglu-1:       NOTRUN -> [SKIP][268] ([i915#12394])
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][269] ([i915#13522] / [i915#14544])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
    - shard-tglu-1:       NOTRUN -> [SKIP][270] ([i915#13522])
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-tglu:         NOTRUN -> [SKIP][271] ([i915#6301])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-7/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          NOTRUN -> [SKIP][272] ([i915#6301])
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-4tiled:
    - shard-rkl:          NOTRUN -> [SKIP][273] ([i915#14712])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2:          NOTRUN -> [SKIP][274] ([i915#13705])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-5/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
    - shard-mtlp:         NOTRUN -> [SKIP][275] ([i915#13705])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-7/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane@planar-pixel-format-settings:
    - shard-rkl:          [PASS][276] -> [SKIP][277] ([i915#14544] / [i915#9581])
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_plane@planar-pixel-format-settings.html
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_plane@planar-pixel-format-settings.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][278] ([i915#13026]) +1 other test incomplete
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk10/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane@plane-position-hole-dpms:
    - shard-rkl:          [PASS][279] -> [SKIP][280] ([i915#14544] / [i915#8825])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_plane@plane-position-hole-dpms.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_plane@plane-position-hole-dpms.html

  * igt@kms_plane_lowres@tiling-4:
    - shard-mtlp:         NOTRUN -> [SKIP][281] ([i915#10226] / [i915#11614] / [i915#3555] / [i915#8821])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-7/igt@kms_plane_lowres@tiling-4.html

  * igt@kms_plane_lowres@tiling-4@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][282] ([i915#11614] / [i915#3582]) +3 other tests skip
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-7/igt@kms_plane_lowres@tiling-4@pipe-c-edp-1.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-dg2:          NOTRUN -> [SKIP][283] ([i915#3555] / [i915#8821])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][284] ([i915#13958])
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-tglu:         NOTRUN -> [SKIP][285] ([i915#13958])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-7/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_scaling@invalid-num-scalers:
    - shard-rkl:          [PASS][286] -> [SKIP][287] ([i915#14544] / [i915#3555] / [i915#6953] / [i915#8152])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-2/igt@kms_plane_scaling@invalid-num-scalers.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_plane_scaling@invalid-num-scalers.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-d:
    - shard-dg1:          NOTRUN -> [SKIP][288] ([i915#12247]) +4 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-15/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-d.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers:
    - shard-rkl:          [PASS][289] -> [SKIP][290] ([i915#14544] / [i915#8152])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][291] ([i915#12247]) +9 other tests skip
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-10/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-c.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20:
    - shard-rkl:          [PASS][292] -> [SKIP][293] ([i915#12247] / [i915#14544] / [i915#8152]) +4 other tests skip
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20@pipe-a:
    - shard-rkl:          [PASS][294] -> [SKIP][295] ([i915#12247] / [i915#14544]) +2 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20@pipe-a.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20@pipe-a.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-tglu-1:       NOTRUN -> [SKIP][296] ([i915#9812])
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-dg2:          NOTRUN -> [SKIP][297] ([i915#9685]) +1 other test skip
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][298] ([i915#3828])
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-7/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][299] ([i915#14544] / [i915#15073]) +1 other test skip
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@fences:
    - shard-dg1:          NOTRUN -> [SKIP][300] ([i915#4077] / [i915#4423])
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-16/igt@kms_pm_rpm@fences.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          [PASS][301] -> [SKIP][302] ([i915#15073]) +1 other test skip
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-rkl:          [PASS][303] -> [SKIP][304] ([i915#15073]) +1 other test skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-tglu-1:       NOTRUN -> [SKIP][305] ([i915#15073])
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@pm-caching:
    - shard-rkl:          [PASS][306] -> [DMESG-WARN][307] ([i915#12964]) +35 other tests dmesg-warn
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_pm_rpm@pm-caching.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_pm_rpm@pm-caching.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-dg2:          NOTRUN -> [SKIP][308] ([i915#6524] / [i915#6805])
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@kms_prime@basic-modeset-hybrid.html
    - shard-tglu-1:       NOTRUN -> [SKIP][309] ([i915#6524])
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_properties@plane-properties-atomic:
    - shard-rkl:          [PASS][310] -> [SKIP][311] ([i915#11521] / [i915#14544])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_properties@plane-properties-atomic.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_properties@plane-properties-atomic.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
    - shard-tglu:         NOTRUN -> [SKIP][312] ([i915#11520]) +5 other tests skip
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-8/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-glk:          NOTRUN -> [SKIP][313] ([i915#11520]) +9 other tests skip
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk1/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-dg1:          NOTRUN -> [SKIP][314] ([i915#11520]) +2 other tests skip
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-18/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          NOTRUN -> [SKIP][315] ([i915#11520]) +2 other tests skip
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
    - shard-tglu-1:       NOTRUN -> [SKIP][316] ([i915#11520]) +2 other tests skip
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][317] ([i915#11520] / [i915#14544]) +1 other test skip
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf:
    - shard-mtlp:         NOTRUN -> [SKIP][318] ([i915#12316])
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-4/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf.html
    - shard-snb:          NOTRUN -> [SKIP][319] ([i915#11520]) +1 other test skip
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-snb7/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-glk10:        NOTRUN -> [SKIP][320] ([i915#11520]) +3 other tests skip
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk10/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
    - shard-dg2:          NOTRUN -> [SKIP][321] ([i915#11520]) +7 other tests skip
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg2:          NOTRUN -> [SKIP][322] ([i915#9683]) +1 other test skip
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html
    - shard-rkl:          NOTRUN -> [SKIP][323] ([i915#9683])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
    - shard-dg1:          NOTRUN -> [SKIP][324] ([i915#9683])
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-18/igt@kms_psr2_su@frontbuffer-xrgb8888.html
    - shard-tglu:         NOTRUN -> [SKIP][325] ([i915#9683])
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-3/igt@kms_psr2_su@frontbuffer-xrgb8888.html
    - shard-mtlp:         NOTRUN -> [SKIP][326] ([i915#4348])
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-psr-cursor-blt@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][327] ([i915#9688]) +4 other tests skip
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-2/igt@kms_psr@fbc-psr-cursor-blt@edp-1.html

  * igt@kms_psr@fbc-psr-cursor-plane-move:
    - shard-dg2:          NOTRUN -> [SKIP][328] ([i915#1072] / [i915#9732]) +22 other tests skip
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@kms_psr@fbc-psr-cursor-plane-move.html

  * igt@kms_psr@fbc-psr-primary-page-flip:
    - shard-dg1:          NOTRUN -> [SKIP][329] ([i915#1072] / [i915#9732]) +6 other tests skip
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-19/igt@kms_psr@fbc-psr-primary-page-flip.html

  * igt@kms_psr@pr-sprite-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][330] ([i915#9732]) +14 other tests skip
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-5/igt@kms_psr@pr-sprite-mmap-cpu.html
    - shard-rkl:          NOTRUN -> [SKIP][331] ([i915#1072] / [i915#14544] / [i915#9732])
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_psr@pr-sprite-mmap-cpu.html

  * igt@kms_psr@psr2-sprite-mmap-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][332] ([i915#1072] / [i915#9732]) +7 other tests skip
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_psr@psr2-sprite-mmap-cpu.html

  * igt@kms_psr@psr2-sprite-mmap-gtt:
    - shard-tglu-1:       NOTRUN -> [SKIP][333] ([i915#9732]) +8 other tests skip
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_psr@psr2-sprite-mmap-gtt.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][334] ([i915#5289])
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-rkl:          NOTRUN -> [SKIP][335] ([i915#14544]) +16 other tests skip
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-dg2:          NOTRUN -> [SKIP][336] ([i915#12755]) +2 other tests skip
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_rotation_crc@sprite-rotation-90.html
    - shard-mtlp:         NOTRUN -> [SKIP][337] ([i915#12755])
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-8/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-rkl:          NOTRUN -> [SKIP][338] ([i915#3555]) +2 other tests skip
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-tglu:         NOTRUN -> [ABORT][339] ([i915#13179]) +1 other test abort
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-8/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_sharpness_filter@filter-formats:
    - shard-tglu-1:       NOTRUN -> [SKIP][340] ([i915#15232])
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_sharpness_filter@filter-formats.html

  * igt@kms_sharpness_filter@filter-modifiers:
    - shard-dg2:          NOTRUN -> [SKIP][341] ([i915#15232]) +2 other tests skip
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_sharpness_filter@filter-modifiers.html

  * igt@kms_sharpness_filter@filter-strength:
    - shard-tglu:         NOTRUN -> [SKIP][342] ([i915#15232])
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-3/igt@kms_sharpness_filter@filter-strength.html
    - shard-mtlp:         NOTRUN -> [SKIP][343] ([i915#15232])
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-5/igt@kms_sharpness_filter@filter-strength.html
    - shard-rkl:          NOTRUN -> [SKIP][344] ([i915#15232])
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_sharpness_filter@filter-strength.html

  * igt@kms_sharpness_filter@invalid-plane-with-filter:
    - shard-dg1:          NOTRUN -> [SKIP][345] ([i915#15232]) +1 other test skip
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-17/igt@kms_sharpness_filter@invalid-plane-with-filter.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-tglu:         NOTRUN -> [SKIP][346] ([i915#8623])
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-mtlp:         [PASS][347] -> [FAIL][348] ([i915#9196]) +1 other test fail
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-6/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@kms_vrr@flipline:
    - shard-rkl:          NOTRUN -> [SKIP][349] ([i915#15243] / [i915#3555])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_vrr@flipline.html

  * igt@kms_vrr@max-min:
    - shard-rkl:          NOTRUN -> [SKIP][350] ([i915#9906])
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_vrr@max-min.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-tglu-1:       NOTRUN -> [SKIP][351] ([i915#9906])
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-tglu:         NOTRUN -> [SKIP][352] ([i915#9906])
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-8/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@kms_writeback@writeback-check-output:
    - shard-glk:          NOTRUN -> [SKIP][353] ([i915#2437])
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-glk6/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-dg2:          NOTRUN -> [SKIP][354] ([i915#2437] / [i915#9412])
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-dg2:          NOTRUN -> [SKIP][355] ([i915#2437])
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-3/igt@kms_writeback@writeback-fb-id.html
    - shard-rkl:          NOTRUN -> [SKIP][356] ([i915#2437])
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_writeback@writeback-fb-id.html
    - shard-dg1:          NOTRUN -> [SKIP][357] ([i915#2437])
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-17/igt@kms_writeback@writeback-fb-id.html
    - shard-mtlp:         NOTRUN -> [SKIP][358] ([i915#2437])
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-7/igt@kms_writeback@writeback-fb-id.html

  * igt@panthor/panthor_gem@bo_create_round_size:
    - shard-tglu-1:       NOTRUN -> [SKIP][359] ([i915#2575]) +1 other test skip
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@panthor/panthor_gem@bo_create_round_size.html

  * igt@panthor/panthor_vm@vm_unbind_invalid_address:
    - shard-tglu:         NOTRUN -> [SKIP][360] ([i915#2575])
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-8/igt@panthor/panthor_vm@vm_unbind_invalid_address.html

  * igt@perf@global-sseu-config-invalid:
    - shard-dg2:          NOTRUN -> [SKIP][361] ([i915#7387])
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@perf@global-sseu-config-invalid.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-tglu:         NOTRUN -> [SKIP][362] ([i915#8516])
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-4/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_vgem@basic-read:
    - shard-dg2:          NOTRUN -> [SKIP][363] ([i915#3291] / [i915#3708])
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-1/igt@prime_vgem@basic-read.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-dg2:          NOTRUN -> [SKIP][364] ([i915#9917]) +2 other tests skip
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each:
    - shard-rkl:          NOTRUN -> [SKIP][365] ([i915#14544] / [i915#9917])
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@sriov_basic@enable-vfs-bind-unbind-each.html
    - shard-dg1:          NOTRUN -> [SKIP][366] ([i915#9917]) +1 other test skip
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@sriov_basic@enable-vfs-bind-unbind-each.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-tglu:         NOTRUN -> [FAIL][367] ([i915#12910])
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-7/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-2:
    - shard-tglu-1:       NOTRUN -> [FAIL][368] ([i915#12910]) +18 other tests fail
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-1/igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-2.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-random:
    - shard-mtlp:         NOTRUN -> [FAIL][369] ([i915#12910]) +8 other tests fail
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-8/igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-random.html

  
#### Possible fixes ####

  * igt@gem_ccs@suspend-resume:
    - shard-dg2:          [INCOMPLETE][370] ([i915#13356]) -> [PASS][371]
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-3/igt@gem_ccs@suspend-resume.html
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@gem_ccs@suspend-resume.html

  * igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          [INCOMPLETE][372] ([i915#12392] / [i915#13356]) -> [PASS][373]
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-3/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-8/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [DMESG-WARN][374] ([i915#5493]) -> [PASS][375] +1 other test pass
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_pxp@fail-invalid-protected-context:
    - shard-rkl:          [TIMEOUT][376] ([i915#12964]) -> [PASS][377]
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@gem_pxp@fail-invalid-protected-context.html
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@gem_pxp@fail-invalid-protected-context.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-rkl:          [TIMEOUT][378] ([i915#12917] / [i915#12964]) -> [PASS][379] +1 other test pass
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@gem_pxp@reject-modify-context-protection-off-3.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@gem_userptr_blits@stress-purge:
    - shard-rkl:          [DMESG-WARN][380] ([i915#12964]) -> [PASS][381] +25 other tests pass
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-2/igt@gem_userptr_blits@stress-purge.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@gem_userptr_blits@stress-purge.html

  * igt@i915_module_load@reload-no-display:
    - shard-dg1:          [DMESG-WARN][382] ([i915#13029] / [i915#14545]) -> [PASS][383]
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg1-12/igt@i915_module_load@reload-no-display.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-16/igt@i915_module_load@reload-no-display.html

  * igt@i915_pm_rpm@reg-read-ioctl:
    - shard-rkl:          [SKIP][384] ([i915#13328]) -> [PASS][385]
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-3/igt@i915_pm_rpm@reg-read-ioctl.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-4/igt@i915_pm_rpm@reg-read-ioctl.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [INCOMPLETE][386] ([i915#13729] / [i915#13821]) -> [PASS][387]
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-snb4/igt@i915_pm_rps@reset.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-snb5/igt@i915_pm_rps@reset.html

  * igt@i915_selftest@live@workarounds:
    - shard-mtlp:         [DMESG-FAIL][388] ([i915#12061]) -> [PASS][389] +1 other test pass
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-mtlp-4/igt@i915_selftest@live@workarounds.html
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-8/igt@i915_selftest@live@workarounds.html

  * igt@i915_selftest@mock:
    - shard-dg2:          [DMESG-WARN][390] ([i915#14545]) -> [PASS][391]
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-11/igt@i915_selftest@mock.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-5/igt@i915_selftest@mock.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - shard-rkl:          [DMESG-WARN][392] ([i915#12917] / [i915#12964]) -> [PASS][393]
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@i915_suspend@basic-s2idle-without-i915.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-mtlp:         [FAIL][394] ([i915#5138]) -> [PASS][395]
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
    - shard-rkl:          [SKIP][396] ([i915#14544]) -> [PASS][397] +37 other tests pass
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html

  * igt@kms_color@gamma:
    - shard-rkl:          [SKIP][398] ([i915#12655] / [i915#14544]) -> [PASS][399] +1 other test pass
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_color@gamma.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_color@gamma.html

  * igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-2:
    - shard-rkl:          [FAIL][400] ([i915#13566]) -> [PASS][401] +2 other tests pass
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-2.html
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-b-hdmi-a-1:
    - shard-rkl:          [ABORT][402] ([i915#15132]) -> [PASS][403] +1 other test pass
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-4/igt@kms_cursor_crc@cursor-suspend@pipe-b-hdmi-a-1.html
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_cursor_crc@cursor-suspend@pipe-b-hdmi-a-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-rkl:          [FAIL][404] ([i915#2346]) -> [PASS][405]
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-plain-flip-ts-check:
    - shard-snb:          [FAIL][406] ([i915#10826] / [i915#11832]) -> [PASS][407] +1 other test pass
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-snb5/igt@kms_flip@2x-plain-flip-ts-check.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-snb7/igt@kms_flip@2x-plain-flip-ts-check.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - shard-rkl:          [SKIP][408] ([i915#14544] / [i915#3637]) -> [PASS][409] +5 other tests pass
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-dg1:          [DMESG-WARN][410] ([i915#4423]) -> [PASS][411] +2 other tests pass
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg1-16/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-17/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-rkl:          [SKIP][412] ([i915#14544] / [i915#3555]) -> [PASS][413]
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-pwrite:
    - shard-dg2:          [FAIL][414] -> [PASS][415]
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-pwrite.html
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
    - shard-dg2:          [FAIL][416] ([i915#6880]) -> [PASS][417]
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][418] ([i915#14544] / [i915#1849] / [i915#5354]) -> [PASS][419] +7 other tests pass
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-snb:          [SKIP][420] -> [PASS][421]
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_invalid_mode@clock-too-high:
    - shard-rkl:          [SKIP][422] ([i915#14544] / [i915#3555] / [i915#8826]) -> [PASS][423]
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_invalid_mode@clock-too-high.html
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_invalid_mode@clock-too-high.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-dg2:          [SKIP][424] ([i915#12388]) -> [PASS][425]
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-3/igt@kms_joiner@basic-force-big-joiner.html
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
    - shard-rkl:          [SKIP][426] ([i915#11190] / [i915#14544]) -> [PASS][427]
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html

  * igt@kms_plane@plane-panning-top-left:
    - shard-rkl:          [SKIP][428] ([i915#14544] / [i915#8825]) -> [PASS][429] +1 other test pass
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_plane@plane-panning-top-left.html
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_plane@plane-panning-top-left.html

  * igt@kms_plane_alpha_blend@constant-alpha-max:
    - shard-rkl:          [SKIP][430] ([i915#14544] / [i915#7294]) -> [PASS][431] +1 other test pass
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_plane_alpha_blend@constant-alpha-max.html
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_plane_alpha_blend@constant-alpha-max.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-pixel-format:
    - shard-rkl:          [SKIP][432] ([i915#14544] / [i915#8152]) -> [PASS][433]
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-20x20-with-pixel-format.html
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_plane_scaling@plane-upscale-20x20-with-pixel-format.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling:
    - shard-rkl:          [SKIP][434] ([i915#12247] / [i915#14544] / [i915#8152]) -> [PASS][435] +2 other tests pass
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling.html
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-a:
    - shard-rkl:          [SKIP][436] ([i915#12247] / [i915#14544]) -> [PASS][437] +1 other test pass
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-a.html
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-a.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg2:          [SKIP][438] ([i915#15073]) -> [PASS][439]
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-1/igt@kms_pm_rpm@dpms-lpsp.html
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [SKIP][440] ([i915#15073]) -> [PASS][441] +1 other test pass
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp.html
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-dg2:          [ABORT][442] ([i915#15058] / [i915#15132]) -> [PASS][443]
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-10/igt@kms_vblank@ts-continuation-dpms-suspend.html
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@perf_pmu@most-busy-idle-check-all:
    - shard-mtlp:         [FAIL][444] ([i915#11943]) -> [PASS][445] +1 other test pass
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-mtlp-8/igt@perf_pmu@most-busy-idle-check-all.html
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-mtlp-8/igt@perf_pmu@most-busy-idle-check-all.html

  
#### Warnings ####

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-rkl:          [SKIP][446] ([i915#14544] / [i915#8411]) -> [SKIP][447] ([i915#8411])
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@api_intel_bb@object-reloc-purge-cache.html
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-rkl:          [SKIP][448] ([i915#11078]) -> [SKIP][449] ([i915#11078] / [i915#14544])
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-4/igt@device_reset@unbind-cold-reset-rebind.html
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-rkl:          [SKIP][450] ([i915#9323]) -> [SKIP][451] ([i915#14544] / [i915#9323])
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-3/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          [SKIP][452] ([i915#13008] / [i915#14544]) -> [SKIP][453] ([i915#13008])
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@gem_ccs@large-ctrl-surf-copy.html
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-rkl:          [SKIP][454] ([i915#7697]) -> [SKIP][455] ([i915#14544] / [i915#7697])
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@gem_close_race@multigpu-basic-process.html
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-rkl:          [SKIP][456] ([i915#6335]) -> [SKIP][457] ([i915#14544] / [i915#6335])
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-2/igt@gem_create@create-ext-cpu-access-big.html
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-rkl:          [SKIP][458] ([i915#280]) -> [SKIP][459] ([i915#14544] / [i915#280])
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@gem_ctx_sseu@invalid-args.html
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_exec_balancer@parallel:
    - shard-rkl:          [SKIP][460] ([i915#4525]) -> [SKIP][461] ([i915#14544] / [i915#4525]) +1 other test skip
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-4/igt@gem_exec_balancer@parallel.html
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_reloc@basic-softpin:
    - shard-rkl:          [SKIP][462] ([i915#3281]) -> [SKIP][463] ([i915#14544] / [i915#3281]) +2 other tests skip
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@gem_exec_reloc@basic-softpin.html
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_exec_reloc@basic-softpin.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - shard-rkl:          [SKIP][464] ([i915#14544] / [i915#3281]) -> [SKIP][465] ([i915#3281]) +8 other tests skip
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@gem_exec_reloc@basic-write-read-noreloc.html
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-4/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_lmem_swapping@random:
    - shard-rkl:          [SKIP][466] ([i915#4613]) -> [SKIP][467] ([i915#14544] / [i915#4613]) +1 other test skip
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@gem_lmem_swapping@random.html
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-rkl:          [SKIP][468] ([i915#14544] / [i915#4613]) -> [SKIP][469] ([i915#4613]) +2 other tests skip
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@gem_lmem_swapping@random-engines.html
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-rkl:          [SKIP][470] ([i915#13717]) -> [TIMEOUT][471] ([i915#12917] / [i915#12964])
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@gem_pxp@hw-rejects-pxp-context.html
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_readwrite@beyond-eob:
    - shard-rkl:          [SKIP][472] ([i915#3282]) -> [SKIP][473] ([i915#14544] / [i915#3282]) +5 other tests skip
   [472]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@gem_readwrite@beyond-eob.html
   [473]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_readwrite@beyond-eob.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-rkl:          [SKIP][474] ([i915#3297]) -> [SKIP][475] ([i915#14544] / [i915#3297]) +1 other test skip
   [474]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-3/igt@gem_userptr_blits@create-destroy-unsync.html
   [475]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-rkl:          [SKIP][476] ([i915#14544] / [i915#3297]) -> [SKIP][477] ([i915#3297]) +1 other test skip
   [476]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@gem_userptr_blits@unsync-overlap.html
   [477]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-rkl:          [SKIP][478] ([i915#2527]) -> [SKIP][479] ([i915#14544] / [i915#2527]) +1 other test skip
   [478]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@gen9_exec_parse@bb-oversize.html
   [479]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-rkl:          [SKIP][480] ([i915#14544] / [i915#2527]) -> [SKIP][481] ([i915#2527]) +3 other tests skip
   [480]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html
   [481]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-rkl:          [SKIP][482] ([i915#14544] / [i915#6590]) -> [SKIP][483] ([i915#6590]) +1 other test skip
   [482]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@i915_pm_freq_mult@media-freq@gt0.html
   [483]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@intel_hwmon@hwmon-read:
    - shard-rkl:          [SKIP][484] ([i915#7707]) -> [SKIP][485] ([i915#14544] / [i915#7707])
   [484]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@intel_hwmon@hwmon-read.html
   [485]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-rkl:          [SKIP][486] ([i915#12454] / [i915#12712]) -> [SKIP][487] ([i915#12454] / [i915#12712] / [i915#14544])
   [486]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-3/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
   [487]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-rkl:          [SKIP][488] ([i915#1769] / [i915#3555]) -> [SKIP][489] ([i915#14544])
   [488]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [489]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-rkl:          [SKIP][490] ([i915#14544]) -> [SKIP][491] ([i915#5286]) +1 other test skip
   [490]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
   [491]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-rkl:          [SKIP][492] ([i915#5286]) -> [SKIP][493] ([i915#14544]) +5 other tests skip
   [492]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [493]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-rkl:          [SKIP][494] ([i915#3638]) -> [SKIP][495] ([i915#14544]) +1 other test skip
   [494]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-4/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
   [495]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
    - shard-rkl:          [SKIP][496] ([i915#14544]) -> [SKIP][497] ([i915#3638]) +2 other tests skip
   [496]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
   [497]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-4/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][498] ([i915#14544]) -> [SKIP][499] ([i915#12313]) +2 other tests skip
   [498]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
   [499]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-3/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][500] ([i915#14098] / [i915#6095]) -> [SKIP][501] ([i915#6095]) +2 other tests skip
   [500]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-b-hdmi-a-2.html
   [501]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][502] ([i915#12313]) -> [SKIP][503] ([i915#14544])
   [502]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
   [503]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-rkl:          [SKIP][504] ([i915#14098] / [i915#6095]) -> [SKIP][505] ([i915#14544]) +13 other tests skip
   [504]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
   [505]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs:
    - shard-rkl:          [SKIP][506] ([i915#14544]) -> [SKIP][507] ([i915#14098] / [i915#6095]) +10 other tests skip
   [506]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs.html
   [507]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-4/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-rkl:          [SKIP][508] ([i915#14544] / [i915#3742]) -> [SKIP][509] ([i915#3742])
   [508]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_cdclk@mode-transition-all-outputs.html
   [509]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@plane-scaling:
    - shard-rkl:          [SKIP][510] ([i915#3742]) -> [SKIP][511] ([i915#14544] / [i915#3742])
   [510]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_cdclk@plane-scaling.html
   [511]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-rkl:          [SKIP][512] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][513] ([i915#11151] / [i915#7828]) +8 other tests skip
   [512]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_chamelium_frames@hdmi-frame-dump.html
   [513]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
    - shard-rkl:          [SKIP][514] ([i915#11151] / [i915#7828]) -> [SKIP][515] ([i915#11151] / [i915#14544] / [i915#7828]) +9 other tests skip
   [514]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
   [515]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          [SKIP][516] ([i915#14544]) -> [SKIP][517] ([i915#7118] / [i915#9424])
   [516]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_content_protection@atomic.html
   [517]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          [SKIP][518] ([i915#7118] / [i915#9424]) -> [FAIL][519] ([i915#7173])
   [518]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-1/igt@kms_content_protection@atomic-dpms.html
   [519]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@kms_content_protection@atomic-dpms.html
    - shard-rkl:          [SKIP][520] ([i915#7118] / [i915#9424]) -> [SKIP][521] ([i915#14544])
   [520]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_content_protection@atomic-dpms.html
   [521]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-rkl:          [SKIP][522] ([i915#14544]) -> [SKIP][523] ([i915#3116])
   [522]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_content_protection@dp-mst-lic-type-0.html
   [523]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-rkl:          [SKIP][524] ([i915#3116]) -> [SKIP][525] ([i915#14544]) +1 other test skip
   [524]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_content_protection@dp-mst-lic-type-1.html
   [525]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          [SKIP][526] ([i915#14544]) -> [SKIP][527] ([i915#9424])
   [526]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_content_protection@mei-interface.html
   [527]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-dg2:          [SKIP][528] ([i915#7118]) -> [FAIL][529] ([i915#7173])
   [528]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-4/igt@kms_content_protection@srm.html
   [529]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-11/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@uevent:
    - shard-dg2:          [FAIL][530] ([i915#1339] / [i915#7173]) -> [SKIP][531] ([i915#7118] / [i915#9424])
   [530]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-11/igt@kms_content_protection@uevent.html
   [531]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21:
    - shard-rkl:          [FAIL][532] ([i915#13566]) -> [SKIP][533] ([i915#14544])
   [532]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-64x21.html
   [533]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-64x21.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-rkl:          [SKIP][534] ([i915#3555]) -> [SKIP][535] ([i915#14544]) +2 other tests skip
   [534]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_cursor_crc@cursor-random-32x32.html
   [535]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-rkl:          [SKIP][536] ([i915#13049]) -> [SKIP][537] ([i915#14544])
   [536]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-512x512.html
   [537]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-rkl:          [SKIP][538] -> [SKIP][539] ([i915#14544]) +12 other tests skip
   [538]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-2/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [539]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
    - shard-rkl:          [SKIP][540] ([i915#14544]) -> [SKIP][541] +10 other tests skip
   [540]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
   [541]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-rkl:          [SKIP][542] ([i915#13749]) -> [SKIP][543] ([i915#14544])
   [542]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_dp_link_training@non-uhbr-mst.html
   [543]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          [SKIP][544] ([i915#14544]) -> [SKIP][545] ([i915#13707])
   [544]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [545]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-rkl:          [SKIP][546] ([i915#14544]) -> [SKIP][547] ([i915#3840] / [i915#9053])
   [546]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
   [547]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@psr1:
    - shard-rkl:          [SKIP][548] ([i915#658]) -> [SKIP][549] ([i915#14544] / [i915#658])
   [548]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_feature_discovery@psr1.html
   [549]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-rkl:          [SKIP][550] ([i915#14544] / [i915#9934]) -> [SKIP][551] ([i915#9934]) +4 other tests skip
   [550]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_flip@2x-flip-vs-dpms.html
   [551]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-plain-flip:
    - shard-rkl:          [SKIP][552] ([i915#9934]) -> [SKIP][553] ([i915#14544] / [i915#9934]) +6 other tests skip
   [552]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_flip@2x-plain-flip.html
   [553]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-rkl:          [SKIP][554] ([i915#14544] / [i915#3555]) -> [SKIP][555] ([i915#2672] / [i915#3555]) +5 other tests skip
   [554]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [555]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-rkl:          [SKIP][556] ([i915#2672] / [i915#3555]) -> [SKIP][557] ([i915#14544] / [i915#3555]) +3 other tests skip
   [556]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
   [557]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-rkl:          [DMESG-WARN][558] ([i915#12964]) -> [SKIP][559] ([i915#14544])
   [558]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc.html
   [559]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][560] ([i915#14544]) -> [SKIP][561] ([i915#15102]) +2 other tests skip
   [560]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-cpu.html
   [561]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-render:
    - shard-rkl:          [SKIP][562] ([i915#15102]) -> [SKIP][563] ([i915#14544]) +4 other tests skip
   [562]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-render.html
   [563]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-dg1:          [SKIP][564] ([i915#15102] / [i915#3458]) -> [SKIP][565] ([i915#15102] / [i915#3458] / [i915#4423])
   [564]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html
   [565]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][566] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][567] ([i915#1825]) +25 other tests skip
   [566]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
   [567]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
    - shard-dg2:          [SKIP][568] ([i915#15102] / [i915#3458]) -> [SKIP][569] ([i915#10433] / [i915#15102] / [i915#3458]) +3 other tests skip
   [568]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
   [569]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-dg1:          [SKIP][570] ([i915#15102] / [i915#3458] / [i915#4423]) -> [SKIP][571] ([i915#15102] / [i915#3458])
   [570]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
   [571]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
    - shard-rkl:          [SKIP][572] ([i915#15102] / [i915#3023]) -> [SKIP][573] ([i915#14544] / [i915#1849] / [i915#5354]) +13 other tests skip
   [572]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
   [573]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2:          [SKIP][574] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][575] ([i915#15102] / [i915#3458]) +1 other test skip
   [574]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
   [575]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-rkl:          [SKIP][576] ([i915#1825]) -> [SKIP][577] ([i915#14544] / [i915#1849] / [i915#5354]) +25 other tests skip
   [576]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
   [577]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt:
    - shard-rkl:          [SKIP][578] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][579] ([i915#15102] / [i915#3023]) +10 other tests skip
   [578]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html
   [579]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-rkl:          [SKIP][580] ([i915#14544]) -> [SKIP][581] ([i915#3555] / [i915#8228])
   [580]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_hdr@static-toggle-dpms.html
   [581]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-rkl:          [SKIP][582] ([i915#12394]) -> [SKIP][583] ([i915#12394] / [i915#14544])
   [582]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_joiner@basic-force-ultra-joiner.html
   [583]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-dg1:          [SKIP][584] ([i915#10656]) -> [SKIP][585] ([i915#10656] / [i915#4423])
   [584]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg1-12/igt@kms_joiner@invalid-modeset-big-joiner.html
   [585]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-dg1:          [SKIP][586] ([i915#13522] / [i915#4423]) -> [SKIP][587] ([i915#13522])
   [586]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg1-16/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
   [587]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg1-14/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][588] ([i915#4816]) -> [SKIP][589] ([i915#1839] / [i915#4816])
   [588]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [589]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-rkl:          [SKIP][590] ([i915#14544]) -> [SKIP][591] ([i915#13958]) +1 other test skip
   [590]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-none.html
   [591]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a:
    - shard-rkl:          [SKIP][592] ([i915#12247]) -> [SKIP][593] ([i915#12247] / [i915#14544])
   [592]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a.html
   [593]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b:
    - shard-rkl:          [SKIP][594] ([i915#12247]) -> [SKIP][595] ([i915#12247] / [i915#14544] / [i915#8152]) +1 other test skip
   [594]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b.html
   [595]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-rkl:          [SKIP][596] ([i915#12343]) -> [SKIP][597] ([i915#12343] / [i915#14544])
   [596]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-3/igt@kms_pm_backlight@brightness-with-dpms.html
   [597]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-rkl:          [SKIP][598] ([i915#14544] / [i915#5354]) -> [SKIP][599] ([i915#5354])
   [598]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_pm_backlight@fade-with-dpms.html
   [599]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          [FAIL][600] ([i915#9295]) -> [SKIP][601] ([i915#3361])
   [600]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_pm_dc@dc6-dpms.html
   [601]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html
    - shard-tglu:         [SKIP][602] ([i915#15128]) -> [FAIL][603] ([i915#9295])
   [602]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-tglu-6/igt@kms_pm_dc@dc6-dpms.html
   [603]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-3/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-rkl:          [SKIP][604] ([i915#14544] / [i915#4281]) -> [SKIP][605] ([i915#4281])
   [604]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_pm_dc@dc9-dpms.html
   [605]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_pm_dc@dc9-dpms.html
    - shard-tglu:         [SKIP][606] ([i915#4281]) -> [SKIP][607] ([i915#15128])
   [606]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-tglu-4/igt@kms_pm_dc@dc9-dpms.html
   [607]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-tglu-6/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          [SKIP][608] ([i915#3828]) -> [SKIP][609] ([i915#9340])
   [608]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-7/igt@kms_pm_lpsp@kms-lpsp.html
   [609]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [SKIP][610] ([i915#14544] / [i915#15073]) -> [SKIP][611] ([i915#15073])
   [610]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_pm_rpm@dpms-lpsp.html
   [611]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg2:          [FAIL][612] -> [SKIP][613] ([i915#15073])
   [612]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-dg2-11/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [613]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-dg2-6/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-rkl:          [SKIP][614] ([i915#14544]) -> [ABORT][615] ([i915#15132])
   [614]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_pm_rpm@system-suspend-modeset.html
   [615]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-4/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-rkl:          [SKIP][616] ([i915#14544] / [i915#6524]) -> [SKIP][617] ([i915#6524])
   [616]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_prime@basic-crc-hybrid.html
   [617]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          [SKIP][618] ([i915#6524]) -> [SKIP][619] ([i915#14544] / [i915#6524])
   [618]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_prime@basic-modeset-hybrid.html
   [619]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][620] ([i915#11520] / [i915#14544]) -> [SKIP][621] ([i915#11520]) +4 other tests skip
   [620]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
   [621]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-rkl:          [SKIP][622] ([i915#11520]) -> [SKIP][623] ([i915#11520] / [i915#14544]) +5 other tests skip
   [622]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html
   [623]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-psr2-primary-blt:
    - shard-rkl:          [SKIP][624] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][625] ([i915#1072] / [i915#9732]) +13 other tests skip
   [624]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_psr@fbc-psr2-primary-blt.html
   [625]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@kms_psr@fbc-psr2-primary-blt.html

  * igt@kms_psr@psr-cursor-plane-move:
    - shard-rkl:          [SKIP][626] ([i915#1072] / [i915#9732]) -> [SKIP][627] ([i915#1072] / [i915#14544] / [i915#9732]) +19 other tests skip
   [626]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-3/igt@kms_psr@psr-cursor-plane-move.html
   [627]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_psr@psr-cursor-plane-move.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-rkl:          [SKIP][628] ([i915#5289]) -> [SKIP][629] ([i915#14544])
   [628]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
   [629]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-rkl:          [SKIP][630] ([i915#14544]) -> [SKIP][631] ([i915#3555])
   [630]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_scaling_modes@scaling-mode-full.html
   [631]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_setmode@basic:
    - shard-rkl:          [DMESG-WARN][632] ([i915#12964]) -> [SKIP][633] ([i915#14544] / [i915#3555])
   [632]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-2/igt@kms_setmode@basic.html
   [633]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_setmode@basic.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-rkl:          [SKIP][634] ([i915#14544] / [i915#3555]) -> [SKIP][635] ([i915#3555]) +1 other test skip
   [634]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_setmode@clone-exclusive-crtc.html
   [635]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-5/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-rkl:          [SKIP][636] ([i915#3555]) -> [SKIP][637] ([i915#14544] / [i915#3555])
   [636]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_setmode@invalid-clone-single-crtc.html
   [637]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_sharpness_filter@filter-rotations:
    - shard-rkl:          [SKIP][638] ([i915#15232]) -> [SKIP][639] ([i915#14544]) +1 other test skip
   [638]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_sharpness_filter@filter-rotations.html
   [639]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_sharpness_filter@filter-rotations.html

  * igt@kms_sharpness_filter@filter-scaler-upscale:
    - shard-rkl:          [SKIP][640] ([i915#14544]) -> [SKIP][641] ([i915#15232])
   [640]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_sharpness_filter@filter-scaler-upscale.html
   [641]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_sharpness_filter@filter-scaler-upscale.html

  * igt@kms_vrr@negative-basic:
    - shard-rkl:          [SKIP][642] ([i915#14544]) -> [SKIP][643] ([i915#3555] / [i915#9906])
   [642]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_vrr@negative-basic.html
   [643]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-rkl:          [SKIP][644] ([i915#14544]) -> [SKIP][645] ([i915#9906])
   [644]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@kms_vrr@seamless-rr-switch-drrs.html
   [645]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-8/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-rkl:          [SKIP][646] ([i915#2437] / [i915#9412]) -> [SKIP][647] ([i915#14544] / [i915#2437] / [i915#9412])
   [646]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-8/igt@kms_writeback@writeback-check-output-xrgb2101010.html
   [647]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-rkl:          [SKIP][648] ([i915#14544] / [i915#2436]) -> [SKIP][649] ([i915#2436])
   [648]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@perf@gen8-unprivileged-single-ctx-counters.html
   [649]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-7/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf@mi-rpc:
    - shard-rkl:          [SKIP][650] ([i915#2434]) -> [SKIP][651] ([i915#14544] / [i915#2434])
   [650]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@perf@mi-rpc.html
   [651]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@perf@mi-rpc.html

  * igt@perf_pmu@module-unload:
    - shard-rkl:          [DMESG-FAIL][652] ([i915#12964]) -> [FAIL][653] ([i915#14433])
   [652]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-6/igt@perf_pmu@module-unload.html
   [653]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-2/igt@perf_pmu@module-unload.html

  * igt@prime_vgem@basic-write:
    - shard-rkl:          [SKIP][654] ([i915#3291] / [i915#3708]) -> [SKIP][655] ([i915#14544] / [i915#3291] / [i915#3708])
   [654]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-5/igt@prime_vgem@basic-write.html
   [655]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@fence-read-hang:
    - shard-rkl:          [SKIP][656] ([i915#3708]) -> [SKIP][657] ([i915#14544] / [i915#3708])
   [656]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17501/shard-rkl-3/igt@prime_vgem@fence-read-hang.html
   [657]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/shard-rkl-6/igt@prime_vgem@fence-read-hang.html

  
  [i915#10226]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10226
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10826
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11190
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11521]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11521
  [i915#11527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11527
  [i915#11614]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11614
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#11832]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11832
  [i915#11943]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11943
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
  [i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
  [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
  [i915#12469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12469
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
  [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
  [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
  [i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13196
  [i915#13328]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13328
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13363]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13363
  [i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
  [i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
  [i915#13705]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13705
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
  [i915#13729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13729
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13783]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13783
  [i915#13821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13821
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14033]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14033
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
  [i915#14123]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14123
  [i915#14350]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14350
  [i915#14433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14433
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
  [i915#14586]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14586
  [i915#14702]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14702
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#15058]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15058
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15095
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15128]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15128
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#15152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15152
  [i915#15232]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15232
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3582
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4348
  [i915#4391]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4767
  [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7294]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7294
  [i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#8152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8152
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
  [i915#8825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8825
  [i915#8826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8826
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
  [i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9561
  [i915#9581]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9581
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
  [i915#9979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9979


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8613 -> IGTPW_14017
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_17501: 9deffe4baace482f9414f36f53f3385868533fd6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_14017: 14017
  IGT_8613: b542242f5b116e3b554b4068ef5dfa4451075b2b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14017/index.html

[-- Attachment #2: Type: text/html, Size: 214368 bytes --]

✗ Xe.CI.Full: failure for Multi-tile support for xe_sriov_flr and related MMIO improvements (rev2)

[Patchwork]

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== Series Details ==

Series: Multi-tile support for xe_sriov_flr and related MMIO improvements (rev2)
URL   : https://patchwork.freedesktop.org/series/156839/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8613_FULL -> XEIGTPW_14017_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_14017_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_14017_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 3)
------------------------------

  Missing    (1): shard-adlp 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_14017_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@panthor/panthor_group@group_submit:
    - shard-dg2-set2:     NOTRUN -> [SKIP][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-433/igt@panthor/panthor_group@group_submit.html

  
Known issues
------------

  Here are the changes found in XEIGTPW_14017_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-lnl:          NOTRUN -> [SKIP][2] ([Intel XE#1125])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-7/igt@intel_hwmon@hwmon-write.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#1407])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][4] ([Intel XE#316])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-432/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][5] ([Intel XE#1124]) +5 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-466/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-5/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#367])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-5/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#367]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-466/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2887]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#2887]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#787]) +55 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-463/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#3432])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#455] / [Intel XE#787]) +15 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [PASS][15] -> [INCOMPLETE][16] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][17] -> [INCOMPLETE][18] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][19] -> [INCOMPLETE][20] ([Intel XE#6168])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][21] -> [DMESG-WARN][22] ([Intel XE#1727] / [Intel XE#3113])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_cdclk@mode-transition:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2724])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-2/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#306])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-1/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#373]) +3 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-433/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#373])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-3/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2252]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-8/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html

  * igt@kms_content_protection@legacy:
    - shard-dg2-set2:     NOTRUN -> [FAIL][28] ([Intel XE#1178]) +1 other test fail
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-434/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@srm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][29] ([Intel XE#1178])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-4/igt@kms_content_protection@srm@pipe-a-dp-2.html

  * igt@kms_content_protection@uevent@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][30] ([Intel XE#1188])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-5/igt@kms_content_protection@uevent@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2321])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-4/igt@kms_cursor_crc@cursor-sliding-512x512.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#308])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-466/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#309])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-bmg:          [PASS][34] -> [SKIP][35] ([Intel XE#2291]) +4 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-8/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#1340])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#4494] / [i915#3804])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-432/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          [PASS][38] -> [SKIP][39] ([Intel XE#2373])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-2/igt@kms_feature_discovery@display-2x.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#1138])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-4/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-bmg:          [PASS][41] -> [SKIP][42] ([Intel XE#2316]) +2 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#1421]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-8/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][44] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-8/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@d-dp4:
    - shard-dg2-set2:     [PASS][45] -> [INCOMPLETE][46] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-dg2-436/igt@kms_flip@flip-vs-suspend@d-dp4.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-433/igt@kms_flip@flip-vs-suspend@d-dp4.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2293] / [Intel XE#2380])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2293])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#651]) +15 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#5390]) +5 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2312])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2311]) +5 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-stridechange:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#651])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-stridechange.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#6312]) +2 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#2313]) +7 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#653]) +15 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#656]) +5 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#3374] / [Intel XE#3544])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#455]) +11 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-436/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#2763]) +9 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [PASS][61] -> [FAIL][62] ([Intel XE#718])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-lnl-2/igt@kms_pm_dc@dc5-psr.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-3/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#1406] / [Intel XE#1489]) +5 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-463/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#1406] / [Intel XE#2893]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-5/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-8/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-pr-sprite-plane-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +3 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-463/igt@kms_psr@fbc-pr-sprite-plane-move.html

  * igt@kms_psr@fbc-psr-basic:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_psr@fbc-psr-basic.html

  * igt@kms_psr@pr-basic:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#1406])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-5/igt@kms_psr@pr-basic.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][70] ([Intel XE#3414]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-464/igt@kms_rotation_crc@bad-tiling.html
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#3414] / [Intel XE#3904])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-5/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_sharpness_filter@filter-strength:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#6503])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-1/igt@kms_sharpness_filter@filter-strength.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#330])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-2/igt@kms_tv_load_detect@load-detect.html

  * igt@panthor/panthor_group@group_submit:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#6530])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-3/igt@panthor/panthor_group@group_submit.html
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#6530])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@panthor/panthor_group@group_submit.html

  * igt@xe_compute@ccs-mode-basic:
    - shard-bmg:          NOTRUN -> [FAIL][76] ([Intel XE#5794])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-5/igt@xe_compute@ccs-mode-basic.html

  * igt@xe_compute_preempt@compute-preempt-many-all-ram:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#6360])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-434/igt@xe_compute_preempt@compute-preempt-many-all-ram.html

  * igt@xe_copy_basic@mem-page-copy-1:
    - shard-dg2-set2:     NOTRUN -> [SKIP][78] ([Intel XE#5300])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-466/igt@xe_copy_basic@mem-page-copy-1.html

  * igt@xe_copy_basic@mem-set-linear-0xfffe:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#1126])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0xfffe.html

  * igt@xe_eudebug@basic-vm-access:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#4837]) +2 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@xe_eudebug@basic-vm-access.html

  * igt@xe_eudebug_online@debugger-reopen:
    - shard-dg2-set2:     NOTRUN -> [SKIP][81] ([Intel XE#4837]) +5 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-464/igt@xe_eudebug_online@debugger-reopen.html

  * igt@xe_eudebug_online@interrupt-all-set-breakpoint-faultable:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#4837])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-7/igt@xe_eudebug_online@interrupt-all-set-breakpoint-faultable.html

  * igt@xe_evict@evict-large-external:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#688]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-3/igt@xe_evict@evict-large-external.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#2322]) +2 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-8/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html

  * igt@xe_exec_fault_mode@twice-invalid-fault:
    - shard-dg2-set2:     NOTRUN -> [SKIP][85] ([Intel XE#288]) +15 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-433/igt@xe_exec_fault_mode@twice-invalid-fault.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][86] ([Intel XE#2360])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-434/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html

  * igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][87] ([Intel XE#6299])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-433/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html

  * igt@xe_exec_system_allocator@process-many-stride-mmap-prefetch-shared:
    - shard-dg2-set2:     NOTRUN -> [SKIP][88] ([Intel XE#4915]) +172 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-432/igt@xe_exec_system_allocator@process-many-stride-mmap-prefetch-shared.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-free-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#4943]) +5 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-7/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-free-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#4943]) +4 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-prefetch:
    - shard-bmg:          [PASS][91] -> [INCOMPLETE][92] ([Intel XE#2594] / [Intel XE#6480])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-prefetch.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-prefetch.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - shard-dg2-set2:     NOTRUN -> [SKIP][93] ([Intel XE#2229])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-436/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  * igt@xe_oa@non-zero-reason-all:
    - shard-dg2-set2:     NOTRUN -> [SKIP][94] ([Intel XE#6377])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-434/igt@xe_oa@non-zero-reason-all.html

  * igt@xe_oa@syncs-userptr-wait-cfg:
    - shard-dg2-set2:     NOTRUN -> [SKIP][95] ([Intel XE#3573]) +5 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-433/igt@xe_oa@syncs-userptr-wait-cfg.html

  * igt@xe_peer2peer@write:
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#1061])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-3/igt@xe_peer2peer@write.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#2284])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-4/igt@xe_pm@s2idle-d3cold-basic-exec.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][98] ([Intel XE#2284] / [Intel XE#366])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-432/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0:
    - shard-lnl:          [PASS][99] -> [FAIL][100] ([Intel XE#6251])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html

  * igt@xe_pxp@pxp-termination-key-update-post-rpm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][101] ([Intel XE#4733]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-435/igt@xe_pxp@pxp-termination-key-update-post-rpm.html
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#4733]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-8/igt@xe_pxp@pxp-termination-key-update-post-rpm.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-dg2-set2:     NOTRUN -> [SKIP][103] ([Intel XE#944])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-433/igt@xe_query@multigpu-query-mem-usage.html

  * igt@xe_render_copy@render-stress-0-copies:
    - shard-dg2-set2:     NOTRUN -> [SKIP][104] ([Intel XE#4814])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-463/igt@xe_render_copy@render-stress-0-copies.html

  * igt@xe_sriov_vram@vf-access-after-resize-down:
    - shard-bmg:          [PASS][105] -> [FAIL][106] ([Intel XE#5937]) +1 other test fail
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-7/igt@xe_sriov_vram@vf-access-after-resize-down.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@xe_sriov_vram@vf-access-after-resize-down.html

  
#### Possible fixes ####

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [SKIP][107] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-2/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-bmg:          [SKIP][109] ([Intel XE#2291]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-6/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-8/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [FAIL][111] ([Intel XE#1475]) -> [PASS][112]
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][113] ([Intel XE#5299]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [SKIP][115] ([Intel XE#2316]) -> [PASS][116] +4 other tests pass
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-lnl:          [FAIL][117] ([Intel XE#301]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [FAIL][119] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][120] +1 other test pass
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [FAIL][121] ([Intel XE#718]) -> [PASS][122] +1 other test pass
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-lnl-5/igt@kms_pm_dc@dc6-psr.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-4/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-lnl:          [FAIL][123] ([Intel XE#2029]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-lnl-5/igt@kms_pm_dc@deep-pkgc.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-3/igt@kms_pm_dc@deep-pkgc.html

  * igt@xe_gt_freq@freq_suspend:
    - shard-bmg:          [DMESG-WARN][125] ([Intel XE#6481]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-6/igt@xe_gt_freq@freq_suspend.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-7/igt@xe_gt_freq@freq_suspend.html

  * igt@xe_pmu@gt-c6-idle:
    - shard-dg2-set2:     [FAIL][127] ([Intel XE#6366]) -> [PASS][128]
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-dg2-466/igt@xe_pmu@gt-c6-idle.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-dg2-436/igt@xe_pmu@gt-c6-idle.html

  
#### Warnings ####

  * igt@kms_content_protection@srm:
    - shard-bmg:          [SKIP][129] ([Intel XE#2341]) -> [FAIL][130] ([Intel XE#1178])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-6/igt@kms_content_protection@srm.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-4/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          [SKIP][131] ([Intel XE#2341]) -> [FAIL][132] ([Intel XE#1188])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-6/igt@kms_content_protection@uevent.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-5/igt@kms_content_protection@uevent.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][133] ([Intel XE#2312]) -> [SKIP][134] ([Intel XE#2311]) +10 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][135] ([Intel XE#2312]) -> [SKIP][136] ([Intel XE#5390]) +2 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][137] ([Intel XE#5390]) -> [SKIP][138] ([Intel XE#2312])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][139] ([Intel XE#2311]) -> [SKIP][140] ([Intel XE#2312]) +8 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][141] ([Intel XE#2313]) -> [SKIP][142] ([Intel XE#2312]) +9 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
    - shard-bmg:          [SKIP][143] ([Intel XE#2312]) -> [SKIP][144] ([Intel XE#2313]) +9 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          [SKIP][145] ([Intel XE#5021]) -> [SKIP][146] ([Intel XE#4596])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-8/igt@kms_plane_multiple@2x-tiling-yf.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][147] ([Intel XE#2426]) -> [FAIL][148] ([Intel XE#1729])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][149] ([Intel XE#5862]) -> [FAIL][150] ([Intel XE#2142]) +1 other test fail
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8613/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4494]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4494
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5794
  [Intel XE#5862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5862
  [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6299
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
  [Intel XE#6366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6366
  [Intel XE#6377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6377
  [Intel XE#6480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6480
  [Intel XE#6481]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6481
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#6530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6530
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804


Build changes
-------------

  * IGT: IGT_8613 -> IGTPW_14017
  * Linux: xe-4058-6aa8d62a50c33f091548cc961a713223d488d6ad -> xe-4060-9deffe4baace482f9414f36f53f3385868533fd6

  IGTPW_14017: 14017
  IGT_8613: b542242f5b116e3b554b4068ef5dfa4451075b2b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4058-6aa8d62a50c33f091548cc961a713223d488d6ad: 6aa8d62a50c33f091548cc961a713223d488d6ad
  xe-4060-9deffe4baace482f9414f36f53f3385868533fd6: 9deffe4baace482f9414f36f53f3385868533fd6

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14017/index.html

[-- Attachment #2: Type: text/html, Size: 50648 bytes --]

[PATCH i-g-t 0/6] Multi-tile support for xe_sriov_flr and related MMIO improvements

[Marcin Bernatowicz]

This series builds on Piotr Piórkowski’s v2 of the tile-aware VF FLR
test (see [1]) and reworks xe_sriov_flr test.

Main updates:
 - Move shared helper logic to lib/xe_query (tile helpers)
 - Refactor xe_sriov_flr test to use per-tile subchecks
 - Use proper MMIO initialization helpers (xe_mmio)
 - Keep verify_flr() template intact while isolating per-tile data
 - Simplify MMIO initialization/cleanup
 - Mark failed prerequisites to ensure CI detects them

Thanks to Piotr for the groundwork and earlier revisions.

[1] https://patchwork.freedesktop.org/series/156216/ 

Marcin Bernatowicz (3):
  tests/xe_sriov_flr: Make subchecks Tile aware
  tests/intel/xe_sriov_flr: Use global MMIO context initialized in
    verify_flr
  tests/intel/xe_sriov_flr: Do not ignore failed prerequisites

Piotr Piórkowski (3):
  lib/xe_mmio: Introduce tile-level XE MMIO access helpers
  lib/xe_mmio: Add init flag and helper to check initialization
  lib/xe/xe_query: Add tile helpers and iteration macro

 lib/xe/xe_mmio.c               | 108 ++++++++--
 lib/xe/xe_mmio.h               |  18 +-
 lib/xe/xe_query.c              |  45 ++++
 lib/xe/xe_query.h              |   6 +
 lib/xe/xe_sriov_provisioning.c |   6 +-
 lib/xe/xe_sriov_provisioning.h |   2 +-
 tests/intel/xe_sriov_flr.c     | 365 ++++++++++++++++++---------------
 7 files changed, 354 insertions(+), 196 deletions(-)

-- 
2.43.0

[PATCH i-g-t 1/6] lib/xe_mmio: Introduce tile-level XE MMIO access helpers

[Marcin Bernatowicz]

From: Piotr Piórkowski <piotr.piorkowski@intel.com>

Add new helpers for tile-based MMIO access:
 - xe_mmio_tile_read32()
 - xe_mmio_tile_read64()
 - xe_mmio_tile_write32()
 - xe_mmio_tile_write64()

These functions provide explicit MMIO read/write operations within
a given tile by applying TILE_MMIO_SIZE offsetting logic. Existing
GT-level MMIO helpers (xe_mmio_gt_*()) are refactored to use these
new tile-level accessors, simplifying code and improving consistency
across MMIO operations.
GGTT is also a per-tile resource, so let's adjust the GGTT access
helpers to use tile IDs instead of GT.

v2:
 - find the real tile based on gt instead of assuming root tile

Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Cc: Jan Sokolowski <jan.sokolowski@intel.com>
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
---
 lib/xe/xe_mmio.c               | 94 ++++++++++++++++++++++++++--------
 lib/xe/xe_mmio.h               | 20 +++++---
 lib/xe/xe_sriov_provisioning.c |  6 +--
 lib/xe/xe_sriov_provisioning.h |  2 +-
 tests/intel/xe_sriov_flr.c     | 12 ++---
 5 files changed, 96 insertions(+), 38 deletions(-)

diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
index 834816133..8bc446fb9 100644
--- a/lib/xe/xe_mmio.c
+++ b/lib/xe/xe_mmio.c
@@ -107,6 +107,62 @@ void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val)
 	return iowrite64(mmio->intel_mmio.igt_mmio, offset, val);
 }
 
+/** xe_mmio_tile_read32:
+ * @mmio: xe mmio structure for IO operations
+ * @tile: tile id
+ * @offset: mmio register offset in the tile
+ *
+ * 32-bit read of the register at @offset in the specified @tile
+ *
+ * Returns: The value read from the register.
+ */
+uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
+{
+	return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * tile));
+}
+
+/** xe_mmio_tile_read64:
+ * @mmio: xe mmio structure for IO operations
+ * @tile: tile id
+ * @offset: mmio register offset in the @tile
+ *
+ * 64-bit read of the register at @offset in the specified @tile
+ *
+ * Returns: The value read from the register.
+ */
+uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
+{
+	return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * tile));
+}
+
+/**
+ * xe_mmio_tile_write32:
+ * @mmio: xe mmio structure for IO operations
+ * @tile: tile id
+ * @offset: mmio register offset in the @tile
+ * @val: value to write
+ *
+ * 32-bit write to the register at @offset in the specified @tile
+ */
+void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint32_t val)
+{
+	xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * tile), val);
+}
+
+/**
+ * xe_mmio_tile_write64:
+ * @mmio: xe mmio structure for IO operations
+ * @tile: tile id
+ * @offset: mmio register offset in the @tile
+ * @val: value to write
+ *
+ * 64-bit write to the register at @offset in the specified @tile
+ */
+void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint64_t val)
+{
+	xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * tile), val);
+}
+
 /**
  * xe_mmio_gt_read32:
  * @mmio: xe mmio structure for IO operations
@@ -118,9 +174,9 @@ void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val)
  * Returns:
  * The value read from the register.
  */
-uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset)
+uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset)
 {
-	return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
+	return xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset);
 }
 
 /**
@@ -134,9 +190,9 @@ uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset)
  * Returns:
  * The value read from the register.
  */
-uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset)
+uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset)
 {
-	return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
+	return xe_mmio_tile_read64(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset);
 }
 
 /**
@@ -148,10 +204,9 @@ uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset)
  *
  * 32-bit write to the register at @offset in tile to which @gt belongs.
  */
-void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val)
+void xe_mmio_gt_write32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint32_t val)
 {
-	return xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
-			       val);
+	return xe_mmio_tile_write32(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset, val);
 }
 
 /**
@@ -163,38 +218,37 @@ void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t
  *
  * 64-bit write to the register at @offset in tile to which @gt belongs.
  */
-void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val)
+void xe_mmio_gt_write64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint64_t val)
 {
-	return xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
-			       val);
+	return xe_mmio_tile_write64(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset, val);
 }
 
 /**
  * xe_mmio_ggtt_read:
  * @mmio: xe mmio structure for IO operations
- * @gt: gt id
- * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
+ * @tile: tile id
+ * @offset: PTE offset from the beginning of GGTT in @tile
  *
- * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
+ * Read of GGTT PTE at GGTT @offset in the @tile.
  *
  * Returns:
  * The value read from the register.
  */
-xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t offset)
+xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
 {
-	return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
+	return xe_mmio_tile_read64(mmio, tile, offset + GGTT_OFFSET_IN_TILE);
 }
 
 /**
  * xe_mmio_ggtt_write:
  * @mmio: xe mmio structure for IO operations
- * @gt: gt id
- * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
+ * @tile: tile id
+ * @offset: PTE offset from the beginning of GGTT in @tile
  * @pte: PTE value to write
  *
- * Write PTE value at GGTT @offset in tile to which @gt belongs.
+ * Write PTE value at GGTT @offset in the @tile.
  */
-void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset, xe_ggtt_pte_t pte)
+void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, xe_ggtt_pte_t pte)
 {
-	return xe_mmio_gt_write64(mmio, gt, offset + GGTT_OFFSET_IN_TILE, pte);
+	return xe_mmio_tile_write64(mmio, tile, offset + GGTT_OFFSET_IN_TILE, pte);
 }
diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
index f144d4b53..f15017c96 100644
--- a/lib/xe/xe_mmio.h
+++ b/lib/xe/xe_mmio.h
@@ -29,13 +29,17 @@ uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t offset);
 void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, uint32_t val);
 void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val);
 
-uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset);
-uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset);
-
-void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val);
-void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val);
-
-xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
-void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
+uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset);
+uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset);
+void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint32_t val);
+void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint64_t val);
+
+uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset);
+uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset);
+void xe_mmio_gt_write32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint32_t val);
+void xe_mmio_gt_write64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint64_t val);
+
+xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
+void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
 
 #endif	/* XE_MMIO_H */
diff --git a/lib/xe/xe_sriov_provisioning.c b/lib/xe/xe_sriov_provisioning.c
index ff9d1f7d2..2ca73d2ef 100644
--- a/lib/xe/xe_sriov_provisioning.c
+++ b/lib/xe/xe_sriov_provisioning.c
@@ -90,7 +90,7 @@ static int append_range(struct xe_sriov_provisioned_range **ranges,
 /**
  * xe_sriov_find_ggtt_provisioned_pte_offsets - Find GGTT provisioned PTE offsets
  * @pf_fd: File descriptor for the Physical Function
- * @gt: GT identifier
+ * @tile: Tile id
  * @mmio: Pointer to the MMIO structure
  * @ranges: Pointer to the array of provisioned ranges
  * @nr_ranges: Pointer to the number of provisioned ranges
@@ -106,7 +106,7 @@ static int append_range(struct xe_sriov_provisioned_range **ranges,
  *
  * Returns 0 on success, or a negative error code on failure.
  */
-int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio *mmio,
+int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile, struct xe_mmio *mmio,
 					       struct xe_sriov_provisioned_range **ranges,
 					       unsigned int *nr_ranges)
 {
@@ -122,7 +122,7 @@ int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio
 
 	for (uint32_t offset = START_PTE_OFFSET; offset < MAX_PTE_OFFSET;
 	     offset += sizeof(xe_ggtt_pte_t)) {
-		pte = xe_mmio_ggtt_read(mmio, gt, offset);
+		pte = xe_mmio_ggtt_read(mmio, tile, offset);
 		vf_id = (pte & vfid_mask) >> GGTT_PTE_VFID_SHIFT;
 
 		if (vf_id != current_vf_id) {
diff --git a/lib/xe/xe_sriov_provisioning.h b/lib/xe/xe_sriov_provisioning.h
index e1a9d0a63..1e1dca866 100644
--- a/lib/xe/xe_sriov_provisioning.h
+++ b/lib/xe/xe_sriov_provisioning.h
@@ -92,7 +92,7 @@ struct xe_sriov_provisioned_range {
 
 const char *xe_sriov_shared_res_to_string(enum xe_sriov_shared_res res);
 bool xe_sriov_is_shared_res_provisionable(int pf, enum xe_sriov_shared_res res, unsigned int gt);
-int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio *mmio,
+int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile, struct xe_mmio *mmio,
 					       struct xe_sriov_provisioned_range **ranges,
 					       unsigned int *nr_ranges);
 const char *xe_sriov_shared_res_attr_name(enum xe_sriov_shared_res res,
diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
index aabbd8c05..077ed15af 100644
--- a/tests/intel/xe_sriov_flr.c
+++ b/tests/intel/xe_sriov_flr.c
@@ -493,20 +493,20 @@ struct ggtt_data {
 
 static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
 {
-	return xe_mmio_ggtt_read(mmio, gt, pte_offset);
+	return xe_mmio_ggtt_read(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset);
 }
 
 static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
 {
-	xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
+	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
 }
 
 static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
 {
-	xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
+	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
 
 	/* force flush by read some MMIO register */
-	xe_mmio_gt_read32(mmio, gt, GEN12_VF_CAP_REG);
+	xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, gt), GEN12_VF_CAP_REG);
 }
 
 static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
@@ -548,8 +548,8 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
 	gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
 	igt_assert(gdata->pte_offsets);
 
-	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, gt, gdata->mmio,
-							 &ranges, &nr_ranges);
+	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, xe_gt_get_tile_id(pf_fd, gt),
+							 gdata->mmio, &ranges, &nr_ranges);
 	if (ret) {
 		set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
 				gt, ret);
-- 
2.43.0

Re: [PATCH i-g-t 1/6] lib/xe_mmio: Introduce tile-level XE MMIO access helpers

[Laguna, Lukasz]

On 10/31/2025 13:56, Marcin Bernatowicz wrote:
> From: Piotr Piórkowski <piotr.piorkowski@intel.com>
>
> Add new helpers for tile-based MMIO access:
>   - xe_mmio_tile_read32()
>   - xe_mmio_tile_read64()
>   - xe_mmio_tile_write32()
>   - xe_mmio_tile_write64()
>
> These functions provide explicit MMIO read/write operations within
> a given tile by applying TILE_MMIO_SIZE offsetting logic. Existing
> GT-level MMIO helpers (xe_mmio_gt_*()) are refactored to use these
> new tile-level accessors, simplifying code and improving consistency
> across MMIO operations.
> GGTT is also a per-tile resource, so let's adjust the GGTT access
> helpers to use tile IDs instead of GT.
>
> v2:
>   - find the real tile based on gt instead of assuming root tile
>
> Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
> Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> Cc: Jan Sokolowski <jan.sokolowski@intel.com>
> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> ---
>   lib/xe/xe_mmio.c               | 94 ++++++++++++++++++++++++++--------
>   lib/xe/xe_mmio.h               | 20 +++++---
>   lib/xe/xe_sriov_provisioning.c |  6 +--
>   lib/xe/xe_sriov_provisioning.h |  2 +-
>   tests/intel/xe_sriov_flr.c     | 12 ++---
>   5 files changed, 96 insertions(+), 38 deletions(-)
>
> diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
> index 834816133..8bc446fb9 100644
> --- a/lib/xe/xe_mmio.c
> +++ b/lib/xe/xe_mmio.c
> @@ -107,6 +107,62 @@ void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val)
>   	return iowrite64(mmio->intel_mmio.igt_mmio, offset, val);
>   }
>   
> +/** xe_mmio_tile_read32:
> + * @mmio: xe mmio structure for IO operations
> + * @tile: tile id
> + * @offset: mmio register offset in the tile
> + *
> + * 32-bit read of the register at @offset in the specified @tile
> + *
> + * Returns: The value read from the register.
> + */
> +uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
> +{
> +	return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * tile));
> +}
> +
> +/** xe_mmio_tile_read64:
> + * @mmio: xe mmio structure for IO operations
> + * @tile: tile id
> + * @offset: mmio register offset in the @tile
> + *
> + * 64-bit read of the register at @offset in the specified @tile
> + *
> + * Returns: The value read from the register.
> + */
> +uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
> +{
> +	return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * tile));
> +}
> +
> +/**
> + * xe_mmio_tile_write32:
> + * @mmio: xe mmio structure for IO operations
> + * @tile: tile id
> + * @offset: mmio register offset in the @tile
> + * @val: value to write
> + *
> + * 32-bit write to the register at @offset in the specified @tile
> + */
> +void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint32_t val)
> +{
> +	xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * tile), val);
> +}
> +
> +/**
> + * xe_mmio_tile_write64:
> + * @mmio: xe mmio structure for IO operations
> + * @tile: tile id
> + * @offset: mmio register offset in the @tile
> + * @val: value to write
> + *
> + * 64-bit write to the register at @offset in the specified @tile
> + */
> +void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint64_t val)
> +{
> +	xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * tile), val);
> +}
> +
>   /**
>    * xe_mmio_gt_read32:
>    * @mmio: xe mmio structure for IO operations
> @@ -118,9 +174,9 @@ void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val)
>    * Returns:
>    * The value read from the register.
>    */
> -uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset)
> +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset)
>   {
> -	return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
> +	return xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset);
>   }

I don't see any benefit in having GT-oriented helpers. Especially 
they're not implemented for the GSI register range. Currently they 
duplicate what the tile helpers already do.
Additionally, the naming is misleading as it implies GT data access, 
which is not true. I'd recommend removing them.

>   
>   /**
> @@ -134,9 +190,9 @@ uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset)
>    * Returns:
>    * The value read from the register.
>    */
> -uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset)
> +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset)
>   {
> -	return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)));
> +	return xe_mmio_tile_read64(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset);
>   }
>   
>   /**
> @@ -148,10 +204,9 @@ uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset)
>    *
>    * 32-bit write to the register at @offset in tile to which @gt belongs.
>    */
> -void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val)
> +void xe_mmio_gt_write32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint32_t val)
>   {
> -	return xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
> -			       val);
> +	return xe_mmio_tile_write32(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset, val);
>   }
>   
>   /**
> @@ -163,38 +218,37 @@ void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t
>    *
>    * 64-bit write to the register at @offset in tile to which @gt belongs.
>    */
> -void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val)
> +void xe_mmio_gt_write64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint64_t val)
>   {
> -	return xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * xe_gt_get_tile_id(mmio->fd, gt)),
> -			       val);
> +	return xe_mmio_tile_write64(mmio, xe_gt_get_tile_id(mmio->fd, gt), offset, val);
>   }
>   
>   /**
>    * xe_mmio_ggtt_read:
>    * @mmio: xe mmio structure for IO operations
> - * @gt: gt id
> - * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
> + * @tile: tile id
> + * @offset: PTE offset from the beginning of GGTT in @tile
>    *
> - * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
> + * Read of GGTT PTE at GGTT @offset in the @tile.
>    *
>    * Returns:
>    * The value read from the register.
>    */
> -xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t offset)
> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, uint32_t offset)
>   {
> -	return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
> +	return xe_mmio_tile_read64(mmio, tile, offset + GGTT_OFFSET_IN_TILE);
>   }
>   
>   /**
>    * xe_mmio_ggtt_write:
>    * @mmio: xe mmio structure for IO operations
> - * @gt: gt id
> - * @offset: PTE offset from the beginning of GGTT, in tile to which @gt belongs
> + * @tile: tile id
> + * @offset: PTE offset from the beginning of GGTT in @tile
>    * @pte: PTE value to write
>    *
> - * Write PTE value at GGTT @offset in tile to which @gt belongs.
> + * Write PTE value at GGTT @offset in the @tile.
>    */
> -void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t offset, xe_ggtt_pte_t pte)
> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, xe_ggtt_pte_t pte)
>   {
> -	return xe_mmio_gt_write64(mmio, gt, offset + GGTT_OFFSET_IN_TILE, pte);
> +	return xe_mmio_tile_write64(mmio, tile, offset + GGTT_OFFSET_IN_TILE, pte);
>   }
> diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
> index f144d4b53..f15017c96 100644
> --- a/lib/xe/xe_mmio.h
> +++ b/lib/xe/xe_mmio.h
> @@ -29,13 +29,17 @@ uint64_t xe_mmio_read64(struct xe_mmio *mmio, uint32_t offset);
>   void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, uint32_t val);
>   void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, uint64_t val);
>   
> -uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t offset);
> -uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t offset);
> -
> -void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t offset, uint32_t val);
> -void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t offset, uint64_t val);
> -
> -xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, uint32_t pte_offset);
> -void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte);
> +uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset);
> +uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset);
> +void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint32_t val);
> +void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, uint32_t offset, uint64_t val);
> +
> +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset);
> +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset);
> +void xe_mmio_gt_write32(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint32_t val);
> +void xe_mmio_gt_write64(struct xe_mmio *mmio, uint8_t gt, uint32_t offset, uint64_t val);
> +
> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset);
> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t pte_offset, xe_ggtt_pte_t pte);
>   
>   #endif	/* XE_MMIO_H */
> diff --git a/lib/xe/xe_sriov_provisioning.c b/lib/xe/xe_sriov_provisioning.c
> index ff9d1f7d2..2ca73d2ef 100644
> --- a/lib/xe/xe_sriov_provisioning.c
> +++ b/lib/xe/xe_sriov_provisioning.c
> @@ -90,7 +90,7 @@ static int append_range(struct xe_sriov_provisioned_range **ranges,
>   /**
>    * xe_sriov_find_ggtt_provisioned_pte_offsets - Find GGTT provisioned PTE offsets
>    * @pf_fd: File descriptor for the Physical Function
> - * @gt: GT identifier
> + * @tile: Tile id
>    * @mmio: Pointer to the MMIO structure
>    * @ranges: Pointer to the array of provisioned ranges
>    * @nr_ranges: Pointer to the number of provisioned ranges
> @@ -106,7 +106,7 @@ static int append_range(struct xe_sriov_provisioned_range **ranges,
>    *
>    * Returns 0 on success, or a negative error code on failure.
>    */
> -int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio *mmio,
> +int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile, struct xe_mmio *mmio,
>   					       struct xe_sriov_provisioned_range **ranges,
>   					       unsigned int *nr_ranges)
>   {
> @@ -122,7 +122,7 @@ int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio
>   
>   	for (uint32_t offset = START_PTE_OFFSET; offset < MAX_PTE_OFFSET;
>   	     offset += sizeof(xe_ggtt_pte_t)) {
> -		pte = xe_mmio_ggtt_read(mmio, gt, offset);
> +		pte = xe_mmio_ggtt_read(mmio, tile, offset);
>   		vf_id = (pte & vfid_mask) >> GGTT_PTE_VFID_SHIFT;
>   
>   		if (vf_id != current_vf_id) {
> diff --git a/lib/xe/xe_sriov_provisioning.h b/lib/xe/xe_sriov_provisioning.h
> index e1a9d0a63..1e1dca866 100644
> --- a/lib/xe/xe_sriov_provisioning.h
> +++ b/lib/xe/xe_sriov_provisioning.h
> @@ -92,7 +92,7 @@ struct xe_sriov_provisioned_range {
>   
>   const char *xe_sriov_shared_res_to_string(enum xe_sriov_shared_res res);
>   bool xe_sriov_is_shared_res_provisionable(int pf, enum xe_sriov_shared_res res, unsigned int gt);
> -int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct xe_mmio *mmio,
> +int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t tile, struct xe_mmio *mmio,
>   					       struct xe_sriov_provisioned_range **ranges,
>   					       unsigned int *nr_ranges);
>   const char *xe_sriov_shared_res_attr_name(enum xe_sriov_shared_res res,
> diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
> index aabbd8c05..077ed15af 100644
> --- a/tests/intel/xe_sriov_flr.c
> +++ b/tests/intel/xe_sriov_flr.c
> @@ -493,20 +493,20 @@ struct ggtt_data {
>   
>   static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset)
>   {
> -	return xe_mmio_ggtt_read(mmio, gt, pte_offset);
> +	return xe_mmio_ggtt_read(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset);
>   }
>   
>   static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
>   {
> -	xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
> +	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
>   }
>   
>   static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, uint32_t pte_offset, xe_ggtt_pte_t pte)
>   {
> -	xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
> +	xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), pte_offset, pte);
>   
>   	/* force flush by read some MMIO register */
> -	xe_mmio_gt_read32(mmio, gt, GEN12_VF_CAP_REG);
> +	xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, gt), GEN12_VF_CAP_REG);
>   }
>   
>   static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio *mmio, int gt, uint32_t pte_offset,
> @@ -548,8 +548,8 @@ static int populate_ggtt_pte_offsets(struct ggtt_data *gdata)
>   	gdata->pte_offsets = calloc(num_vfs + 1, sizeof(*gdata->pte_offsets));
>   	igt_assert(gdata->pte_offsets);
>   
> -	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, gt, gdata->mmio,
> -							 &ranges, &nr_ranges);
> +	ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, xe_gt_get_tile_id(pf_fd, gt),
> +							 gdata->mmio, &ranges, &nr_ranges);
>   	if (ret) {
>   		set_skip_reason(&gdata->base, "Failed to scan GGTT PTE offset ranges on gt%u (%d)\n",
>   				gt, ret);

Re: [PATCH i-g-t 1/6] lib/xe_mmio: Introduce tile-level XE MMIO access helpers

[Bernatowicz, Marcin]

On 11/6/2025 12:12 PM, Laguna, Lukasz wrote:
> On 10/31/2025 13:56, Marcin Bernatowicz wrote:
>> From: Piotr Piórkowski <piotr.piorkowski@intel.com>
>>
>> Add new helpers for tile-based MMIO access:
>>   - xe_mmio_tile_read32()
>>   - xe_mmio_tile_read64()
>>   - xe_mmio_tile_write32()
>>   - xe_mmio_tile_write64()
>>
>> These functions provide explicit MMIO read/write operations within
>> a given tile by applying TILE_MMIO_SIZE offsetting logic. Existing
>> GT-level MMIO helpers (xe_mmio_gt_*()) are refactored to use these
>> new tile-level accessors, simplifying code and improving consistency
>> across MMIO operations.
>> GGTT is also a per-tile resource, so let's adjust the GGTT access
>> helpers to use tile IDs instead of GT.
>>
>> v2:
>>   - find the real tile based on gt instead of assuming root tile
>>
>> Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
>> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
>> Cc: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
>> Cc: Jan Sokolowski <jan.sokolowski@intel.com>
>> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
>> ---
>>   lib/xe/xe_mmio.c               | 94 ++++++++++++++++++++++++++--------
>>   lib/xe/xe_mmio.h               | 20 +++++---
>>   lib/xe/xe_sriov_provisioning.c |  6 +--
>>   lib/xe/xe_sriov_provisioning.h |  2 +-
>>   tests/intel/xe_sriov_flr.c     | 12 ++---
>>   5 files changed, 96 insertions(+), 38 deletions(-)
>>
>> diff --git a/lib/xe/xe_mmio.c b/lib/xe/xe_mmio.c
>> index 834816133..8bc446fb9 100644
>> --- a/lib/xe/xe_mmio.c
>> +++ b/lib/xe/xe_mmio.c
>> @@ -107,6 +107,62 @@ void xe_mmio_write64(struct xe_mmio *mmio, 
>> uint32_t offset, uint64_t val)
>>       return iowrite64(mmio->intel_mmio.igt_mmio, offset, val);
>>   }
>>   +/** xe_mmio_tile_read32:
>> + * @mmio: xe mmio structure for IO operations
>> + * @tile: tile id
>> + * @offset: mmio register offset in the tile
>> + *
>> + * 32-bit read of the register at @offset in the specified @tile
>> + *
>> + * Returns: The value read from the register.
>> + */
>> +uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, 
>> uint32_t offset)
>> +{
>> +    return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * tile));
>> +}
>> +
>> +/** xe_mmio_tile_read64:
>> + * @mmio: xe mmio structure for IO operations
>> + * @tile: tile id
>> + * @offset: mmio register offset in the @tile
>> + *
>> + * 64-bit read of the register at @offset in the specified @tile
>> + *
>> + * Returns: The value read from the register.
>> + */
>> +uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, 
>> uint32_t offset)
>> +{
>> +    return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * tile));
>> +}
>> +
>> +/**
>> + * xe_mmio_tile_write32:
>> + * @mmio: xe mmio structure for IO operations
>> + * @tile: tile id
>> + * @offset: mmio register offset in the @tile
>> + * @val: value to write
>> + *
>> + * 32-bit write to the register at @offset in the specified @tile
>> + */
>> +void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, 
>> uint32_t offset, uint32_t val)
>> +{
>> +    xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * tile), val);
>> +}
>> +
>> +/**
>> + * xe_mmio_tile_write64:
>> + * @mmio: xe mmio structure for IO operations
>> + * @tile: tile id
>> + * @offset: mmio register offset in the @tile
>> + * @val: value to write
>> + *
>> + * 64-bit write to the register at @offset in the specified @tile
>> + */
>> +void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, 
>> uint32_t offset, uint64_t val)
>> +{
>> +    xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * tile), val);
>> +}
>> +
>>   /**
>>    * xe_mmio_gt_read32:
>>    * @mmio: xe mmio structure for IO operations
>> @@ -118,9 +174,9 @@ void xe_mmio_write64(struct xe_mmio *mmio, 
>> uint32_t offset, uint64_t val)
>>    * Returns:
>>    * The value read from the register.
>>    */
>> -uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t 
>> offset)
>> +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, uint8_t gt, 
>> uint32_t offset)
>>   {
>> -    return xe_mmio_read32(mmio, offset + (TILE_MMIO_SIZE * 
>> xe_gt_get_tile_id(mmio->fd, gt)));
>> +    return xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, 
>> gt), offset);
>>   }
>
> I don't see any benefit in having GT-oriented helpers. Especially 
> they're not implemented for the GSI register range. Currently they 
> duplicate what the tile helpers already do.
> Additionally, the naming is misleading as it implies GT data access, 
> which is not true. I'd recommend removing them.
Ok, I'll drop these helpers.
>
>>     /**
>> @@ -134,9 +190,9 @@ uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, 
>> int gt, uint32_t offset)
>>    * Returns:
>>    * The value read from the register.
>>    */
>> -uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t 
>> offset)
>> +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, uint8_t gt, 
>> uint32_t offset)
>>   {
>> -    return xe_mmio_read64(mmio, offset + (TILE_MMIO_SIZE * 
>> xe_gt_get_tile_id(mmio->fd, gt)));
>> +    return xe_mmio_tile_read64(mmio, xe_gt_get_tile_id(mmio->fd, 
>> gt), offset);
>>   }
>>     /**
>> @@ -148,10 +204,9 @@ uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, 
>> int gt, uint32_t offset)
>>    *
>>    * 32-bit write to the register at @offset in tile to which @gt 
>> belongs.
>>    */
>> -void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t 
>> offset, uint32_t val)
>> +void xe_mmio_gt_write32(struct xe_mmio *mmio, uint8_t gt, uint32_t 
>> offset, uint32_t val)
>>   {
>> -    return xe_mmio_write32(mmio, offset + (TILE_MMIO_SIZE * 
>> xe_gt_get_tile_id(mmio->fd, gt)),
>> -                   val);
>> +    return xe_mmio_tile_write32(mmio, xe_gt_get_tile_id(mmio->fd, 
>> gt), offset, val);
>>   }
>>     /**
>> @@ -163,38 +218,37 @@ void xe_mmio_gt_write32(struct xe_mmio *mmio, 
>> int gt, uint32_t offset, uint32_t
>>    *
>>    * 64-bit write to the register at @offset in tile to which @gt 
>> belongs.
>>    */
>> -void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t 
>> offset, uint64_t val)
>> +void xe_mmio_gt_write64(struct xe_mmio *mmio, uint8_t gt, uint32_t 
>> offset, uint64_t val)
>>   {
>> -    return xe_mmio_write64(mmio, offset + (TILE_MMIO_SIZE * 
>> xe_gt_get_tile_id(mmio->fd, gt)),
>> -                   val);
>> +    return xe_mmio_tile_write64(mmio, xe_gt_get_tile_id(mmio->fd, 
>> gt), offset, val);
>>   }
>>     /**
>>    * xe_mmio_ggtt_read:
>>    * @mmio: xe mmio structure for IO operations
>> - * @gt: gt id
>> - * @offset: PTE offset from the beginning of GGTT, in tile to which 
>> @gt belongs
>> + * @tile: tile id
>> + * @offset: PTE offset from the beginning of GGTT in @tile
>>    *
>> - * Read of GGTT PTE at GGTT @offset in tile to which @gt belongs.
>> + * Read of GGTT PTE at GGTT @offset in the @tile.
>>    *
>>    * Returns:
>>    * The value read from the register.
>>    */
>> -xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, 
>> uint32_t offset)
>> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, 
>> uint32_t offset)
>>   {
>> -    return xe_mmio_gt_read64(mmio, gt, offset + GGTT_OFFSET_IN_TILE);
>> +    return xe_mmio_tile_read64(mmio, tile, offset + 
>> GGTT_OFFSET_IN_TILE);
>>   }
>>     /**
>>    * xe_mmio_ggtt_write:
>>    * @mmio: xe mmio structure for IO operations
>> - * @gt: gt id
>> - * @offset: PTE offset from the beginning of GGTT, in tile to which 
>> @gt belongs
>> + * @tile: tile id
>> + * @offset: PTE offset from the beginning of GGTT in @tile
>>    * @pte: PTE value to write
>>    *
>> - * Write PTE value at GGTT @offset in tile to which @gt belongs.
>> + * Write PTE value at GGTT @offset in the @tile.
>>    */
>> -void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t 
>> offset, xe_ggtt_pte_t pte)
>> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t 
>> offset, xe_ggtt_pte_t pte)
>>   {
>> -    return xe_mmio_gt_write64(mmio, gt, offset + 
>> GGTT_OFFSET_IN_TILE, pte);
>> +    return xe_mmio_tile_write64(mmio, tile, offset + 
>> GGTT_OFFSET_IN_TILE, pte);
>>   }
>> diff --git a/lib/xe/xe_mmio.h b/lib/xe/xe_mmio.h
>> index f144d4b53..f15017c96 100644
>> --- a/lib/xe/xe_mmio.h
>> +++ b/lib/xe/xe_mmio.h
>> @@ -29,13 +29,17 @@ uint64_t xe_mmio_read64(struct xe_mmio *mmio, 
>> uint32_t offset);
>>   void xe_mmio_write32(struct xe_mmio *mmio, uint32_t offset, 
>> uint32_t val);
>>   void xe_mmio_write64(struct xe_mmio *mmio, uint32_t offset, 
>> uint64_t val);
>>   -uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, int gt, uint32_t 
>> offset);
>> -uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, int gt, uint32_t 
>> offset);
>> -
>> -void xe_mmio_gt_write32(struct xe_mmio *mmio, int gt, uint32_t 
>> offset, uint32_t val);
>> -void xe_mmio_gt_write64(struct xe_mmio *mmio, int gt, uint32_t 
>> offset, uint64_t val);
>> -
>> -xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, int gt, 
>> uint32_t pte_offset);
>> -void xe_mmio_ggtt_write(struct xe_mmio *mmio, int gt, uint32_t 
>> pte_offset, xe_ggtt_pte_t pte);
>> +uint32_t xe_mmio_tile_read32(struct xe_mmio *mmio, uint8_t tile, 
>> uint32_t offset);
>> +uint64_t xe_mmio_tile_read64(struct xe_mmio *mmio, uint8_t tile, 
>> uint32_t offset);
>> +void xe_mmio_tile_write32(struct xe_mmio *mmio, uint8_t tile, 
>> uint32_t offset, uint32_t val);
>> +void xe_mmio_tile_write64(struct xe_mmio *mmio, uint8_t tile, 
>> uint32_t offset, uint64_t val);
>> +
>> +uint32_t xe_mmio_gt_read32(struct xe_mmio *mmio, uint8_t gt, 
>> uint32_t offset);
>> +uint64_t xe_mmio_gt_read64(struct xe_mmio *mmio, uint8_t gt, 
>> uint32_t offset);
>> +void xe_mmio_gt_write32(struct xe_mmio *mmio, uint8_t gt, uint32_t 
>> offset, uint32_t val);
>> +void xe_mmio_gt_write64(struct xe_mmio *mmio, uint8_t gt, uint32_t 
>> offset, uint64_t val);
>> +
>> +xe_ggtt_pte_t xe_mmio_ggtt_read(struct xe_mmio *mmio, uint8_t tile, 
>> uint32_t pte_offset);
>> +void xe_mmio_ggtt_write(struct xe_mmio *mmio, uint8_t tile, uint32_t 
>> pte_offset, xe_ggtt_pte_t pte);
>>     #endif    /* XE_MMIO_H */
>> diff --git a/lib/xe/xe_sriov_provisioning.c 
>> b/lib/xe/xe_sriov_provisioning.c
>> index ff9d1f7d2..2ca73d2ef 100644
>> --- a/lib/xe/xe_sriov_provisioning.c
>> +++ b/lib/xe/xe_sriov_provisioning.c
>> @@ -90,7 +90,7 @@ static int append_range(struct 
>> xe_sriov_provisioned_range **ranges,
>>   /**
>>    * xe_sriov_find_ggtt_provisioned_pte_offsets - Find GGTT 
>> provisioned PTE offsets
>>    * @pf_fd: File descriptor for the Physical Function
>> - * @gt: GT identifier
>> + * @tile: Tile id
>>    * @mmio: Pointer to the MMIO structure
>>    * @ranges: Pointer to the array of provisioned ranges
>>    * @nr_ranges: Pointer to the number of provisioned ranges
>> @@ -106,7 +106,7 @@ static int append_range(struct 
>> xe_sriov_provisioned_range **ranges,
>>    *
>>    * Returns 0 on success, or a negative error code on failure.
>>    */
>> -int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, 
>> struct xe_mmio *mmio,
>> +int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t 
>> tile, struct xe_mmio *mmio,
>>                              struct xe_sriov_provisioned_range **ranges,
>>                              unsigned int *nr_ranges)
>>   {
>> @@ -122,7 +122,7 @@ int 
>> xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, struct 
>> xe_mmio
>>         for (uint32_t offset = START_PTE_OFFSET; offset < 
>> MAX_PTE_OFFSET;
>>            offset += sizeof(xe_ggtt_pte_t)) {
>> -        pte = xe_mmio_ggtt_read(mmio, gt, offset);
>> +        pte = xe_mmio_ggtt_read(mmio, tile, offset);
>>           vf_id = (pte & vfid_mask) >> GGTT_PTE_VFID_SHIFT;
>>             if (vf_id != current_vf_id) {
>> diff --git a/lib/xe/xe_sriov_provisioning.h 
>> b/lib/xe/xe_sriov_provisioning.h
>> index e1a9d0a63..1e1dca866 100644
>> --- a/lib/xe/xe_sriov_provisioning.h
>> +++ b/lib/xe/xe_sriov_provisioning.h
>> @@ -92,7 +92,7 @@ struct xe_sriov_provisioned_range {
>>     const char *xe_sriov_shared_res_to_string(enum 
>> xe_sriov_shared_res res);
>>   bool xe_sriov_is_shared_res_provisionable(int pf, enum 
>> xe_sriov_shared_res res, unsigned int gt);
>> -int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, int gt, 
>> struct xe_mmio *mmio,
>> +int xe_sriov_find_ggtt_provisioned_pte_offsets(int pf_fd, uint8_t 
>> tile, struct xe_mmio *mmio,
>>                              struct xe_sriov_provisioned_range **ranges,
>>                              unsigned int *nr_ranges);
>>   const char *xe_sriov_shared_res_attr_name(enum xe_sriov_shared_res 
>> res,
>> diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
>> index aabbd8c05..077ed15af 100644
>> --- a/tests/intel/xe_sriov_flr.c
>> +++ b/tests/intel/xe_sriov_flr.c
>> @@ -493,20 +493,20 @@ struct ggtt_data {
>>     static xe_ggtt_pte_t intel_get_pte(struct xe_mmio *mmio, int gt, 
>> uint32_t pte_offset)
>>   {
>> -    return xe_mmio_ggtt_read(mmio, gt, pte_offset);
>> +    return xe_mmio_ggtt_read(mmio, xe_gt_get_tile_id(mmio->fd, gt), 
>> pte_offset);
>>   }
>>     static void intel_set_pte(struct xe_mmio *mmio, int gt, uint32_t 
>> pte_offset, xe_ggtt_pte_t pte)
>>   {
>> -    xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
>> +    xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), 
>> pte_offset, pte);
>>   }
>>     static void intel_mtl_set_pte(struct xe_mmio *mmio, int gt, 
>> uint32_t pte_offset, xe_ggtt_pte_t pte)
>>   {
>> -    xe_mmio_ggtt_write(mmio, gt, pte_offset, pte);
>> +    xe_mmio_ggtt_write(mmio, xe_gt_get_tile_id(mmio->fd, gt), 
>> pte_offset, pte);
>>         /* force flush by read some MMIO register */
>> -    xe_mmio_gt_read32(mmio, gt, GEN12_VF_CAP_REG);
>> +    xe_mmio_tile_read32(mmio, xe_gt_get_tile_id(mmio->fd, gt), 
>> GEN12_VF_CAP_REG);
>>   }
>>     static bool set_pte_gpa(struct ggtt_ops *ggtt, struct xe_mmio 
>> *mmio, int gt, uint32_t pte_offset,
>> @@ -548,8 +548,8 @@ static int populate_ggtt_pte_offsets(struct 
>> ggtt_data *gdata)
>>       gdata->pte_offsets = calloc(num_vfs + 1, 
>> sizeof(*gdata->pte_offsets));
>>       igt_assert(gdata->pte_offsets);
>>   -    ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, gt, 
>> gdata->mmio,
>> -                             &ranges, &nr_ranges);
>> +    ret = xe_sriov_find_ggtt_provisioned_pte_offsets(pf_fd, 
>> xe_gt_get_tile_id(pf_fd, gt),
>> +                             gdata->mmio, &ranges, &nr_ranges);
>>       if (ret) {
>>           set_skip_reason(&gdata->base, "Failed to scan GGTT PTE 
>> offset ranges on gt%u (%d)\n",
>>                   gt, ret);