[PATCH i-g-t 0/3] gem_wsim: fix batch premature completion

[PATCH i-g-t 0/3] gem_wsim: fix batch premature completion

[Marcin Bernatowicz]

Fixes observed verification failure under looped runs:

gem_wsim -w "1.RCS.5000.0.0,1.BCS.5000.0.0,1.CCS.5000.0.1,1.VCS.5000.0.0"
  -V -r 4000

CRITICAL: Failed assertion:
  w->duration.requested_ticks <= ~w->xe.data->spin.ticks_delta
CRITICAL: error: 96000 > 2

V1 attempted to fix the issue by initializing ticks_delta to ~0u in
xe_spin and resetting it from the host before each fixed-duration
submission in gem_wsim.

V2 fix (suggested by Zbigniew): write sentinel 0 to ticks_delta and use
MI_SEMAPHORE_WAIT to confirm it's in memory before entering the loop.
This is a self-contained GPU-side fix - no host-side reset per submission
needed. Also switches from inverted ticks_delta (STOREINV + ~ctx_ticks)
to direct elapsed (STORE + MAD_LT_IDD + ctx_ticks) for readability.

V1 -> V2:
- Replace host-side ticks_delta reset with GPU-side SDW+SEMAPHORE_WAIT
- Switch from inverted to direct elapsed ticks logic
- Remove ineffective pad loop between SRM and COND_BBE
- Add xe_sriov_scheduling.c fix for the same ticks_delta check

Marcin Bernatowicz (3):
  lib/xe/xe_spin: fix premature batch exit on BO resubmission
  benchmarks/gem_wsim: fix ticks_delta assertion for non-inverted logic
  tests/xe_sriov_scheduling: fix ticks_delta check for non-inverted
    logic

 benchmarks/gem_wsim.c             |  2 +-
 lib/xe/xe_spin.c                  | 31 +++++++++++++++++--------------
 tests/intel/xe_sriov_scheduling.c |  2 +-
 3 files changed, 19 insertions(+), 16 deletions(-)

-- 
2.43.0

[PATCH i-g-t 1/3] lib/xe/xe_spin: fix premature batch exit on BO resubmission

[Marcin Bernatowicz]

COND_BBE reads ticks_delta from memory. When the same BO is resubmitted,
COND_BBE can read the value left by the previous batch(elapsed >= ctx_ticks
at that batch's exit), satisfying the exit condition on the very first loop
iteration before any new elapsed time is stored.

Write sentinel 0 to ticks_delta at batch start and use
MI_SEMAPHORE_WAIT to poll until it is visible in memory before entering
the loop. This guarantees COND_BBE cannot read the stale value from the
previous batch.

Also switch from inverted ticks_delta logic (STOREINV + ~ctx_ticks) to
direct elapsed ticks (STORE + MAD_LT_IDD + ctx_ticks) for readability.
The pad loop between SRM and COND_BBE is removed as it does not help.

Suggested-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/xe/xe_spin.c | 31 +++++++++++++++++--------------
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 874310789..2863d2163 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -52,7 +52,6 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
 	uint64_t start_addr = opts->addr + offsetof(struct xe_spin, start);
 	uint64_t end_addr = opts->addr + offsetof(struct xe_spin, end);
 	uint64_t ticks_delta_addr = opts->addr + offsetof(struct xe_spin, ticks_delta);
-	uint64_t pad_addr = opts->addr + offsetof(struct xe_spin, pad);
 	uint64_t timestamp_addr = opts->addr + offsetof(struct xe_spin, timestamp);
 	int b = 0;
 	uint32_t devid;
@@ -77,6 +76,18 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
 	spin->batch[b++] = start_addr >> 32;
 	spin->batch[b++] = 0xc0ffee;
 
+	if (opts->ctx_ticks) {
+		/* Write sentinel and wait until it is visible in memory before loop. */
+		spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+		spin->batch[b++] = ticks_delta_addr;
+		spin->batch[b++] = ticks_delta_addr >> 32;
+		spin->batch[b++] = 0;
+		spin->batch[b++] = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_POLL | MI_SEMAPHORE_SAD_EQ_SDD;
+		spin->batch[b++] = 0;
+		spin->batch[b++] = ticks_delta_addr;
+		spin->batch[b++] = ticks_delta_addr >> 32;
+	}
+
 	loop_addr = opts->addr + b * sizeof(uint32_t);
 
 	if (opts->preempt)
@@ -101,12 +112,12 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
 		spin->batch[b++] = opts->use_queue_timestamp ? QUEUE_TIMESTAMP : CTX_TIMESTAMP;
 		spin->batch[b++] = CS_GPR(NOW_TS);
 
-		/* delta = now - start; inverted to match COND_BBE */
+		/* delta = now - start */
 		spin->batch[b++] = MI_MATH(4);
 		spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
 		spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
 		spin->batch[b++] = MI_MATH_SUB;
-		spin->batch[b++] = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
+		spin->batch[b++] = MI_MATH_STORE(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
 
 		/* Save delta for reading by COND_BBE */
 		spin->batch[b++] = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_CS_MMIO;
@@ -114,17 +125,9 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
 		spin->batch[b++] = ticks_delta_addr;
 		spin->batch[b++] = ticks_delta_addr >> 32;
 
-		/* Delay between SRM and COND_BBE to post the writes */
-		for (int n = 0; n < 8; n++) {
-			spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
-			spin->batch[b++] = pad_addr;
-			spin->batch[b++] = pad_addr >> 32;
-			spin->batch[b++] = 0xc0ffee;
-		}
-
-		/* Break if delta [time elapsed] > ns */
-		spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2;
-		spin->batch[b++] = ~(opts->ctx_ticks);
+		/* Break if delta [time elapsed] >= ns */
+		spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | MAD_LT_IDD | 2;
+		spin->batch[b++] = opts->ctx_ticks;
 		spin->batch[b++] = ticks_delta_addr;
 		spin->batch[b++] = ticks_delta_addr >> 32;
 	}
-- 
2.43.0

[PATCH i-g-t 2/3] benchmarks/gem_wsim: fix ticks_delta assertion for non-inverted logic

[Marcin Bernatowicz]

xe_spin now stores elapsed ticks directly in ticks_delta (not inverted).
Update the post-execution assertion accordingly.

Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 benchmarks/gem_wsim.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 8be44d0c8..462188708 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -2676,7 +2676,7 @@ static void xe_w_step_sync_and_verify(struct w_step *w)
 
 	if (!w->duration.unbound) {
 		igt_assert(w->duration.requested_ticks && w->xe.data->spin.ticks_delta);
-		igt_assert_lte(w->duration.requested_ticks, ~w->xe.data->spin.ticks_delta);
+		igt_assert_lte(w->duration.requested_ticks, w->xe.data->spin.ticks_delta);
 	}
 }
 
-- 
2.43.0

[PATCH i-g-t 3/3] tests/xe_sriov_scheduling: fix ticks_delta check for non-inverted logic

[Marcin Bernatowicz]

xe_spin now stores elapsed ticks directly in ticks_delta (not inverted).
Update subm_is_work_complete() accordingly.

Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_sriov_scheduling.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/intel/xe_sriov_scheduling.c b/tests/intel/xe_sriov_scheduling.c
index 47cc5d9b0..5d30b961d 100644
--- a/tests/intel/xe_sriov_scheduling.c
+++ b/tests/intel/xe_sriov_scheduling.c
@@ -189,7 +189,7 @@ static void subm_exec_slot(struct subm *s, unsigned int slot)
 
 static bool subm_is_work_complete(struct subm *s, unsigned int slot)
 {
-	return s->expected_ticks <= ~s->spin[slot]->ticks_delta;
+	return s->expected_ticks <= s->spin[slot]->ticks_delta;
 }
 
 static bool subm_is_exec_queue_banned(struct subm *s)
-- 
2.43.0

✓ Xe.CI.BAT: success for gem_wsim: fix batch premature completion (rev2)

[Patchwork]

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== Series Details ==

Series: gem_wsim: fix batch premature completion (rev2)
URL   : https://patchwork.freedesktop.org/series/171174/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_9035_BAT -> XEIGTPW_15618_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_9035 -> IGTPW_15618

  IGTPW_15618: 15618
  IGT_9035: 61674acebe1520ef02165573257f552366c2879c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5515-f9ef9f302ee01854066ec6da30550da6ea6cb03a: f9ef9f302ee01854066ec6da30550da6ea6cb03a

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15618/index.html

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✓ i915.CI.BAT: success for gem_wsim: fix batch premature completion (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4979 bytes --]

== Series Details ==

Series: gem_wsim: fix batch premature completion (rev2)
URL   : https://patchwork.freedesktop.org/series/171174/
State : success

== Summary ==

CI Bug Log - changes from IGT_9035 -> IGTPW_15618
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/index.html

Participating hosts (40 -> 39)
------------------------------

  Additional (1): bat-adls-6 
  Missing    (2): bat-dg2-13 fi-snb-2520m 

Known issues
------------

  Here are the changes found in IGTPW_15618 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-adls-6:         NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic@basic:
    - bat-adls-6:         NOTRUN -> [SKIP][2] ([i915#15656])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/bat-adls-6/igt@gem_tiled_pread_basic@basic.html

  * igt@i915_selftest@live@client:
    - fi-kbl-7567u:       [PASS][3] -> [DMESG-WARN][4] ([i915#13735]) +13 other tests dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9035/fi-kbl-7567u/igt@i915_selftest@live@client.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/fi-kbl-7567u/igt@i915_selftest@live@client.html

  * igt@intel_hwmon@hwmon-read:
    - bat-adls-6:         NOTRUN -> [SKIP][5] ([i915#7707]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/bat-adls-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-adls-6:         NOTRUN -> [SKIP][6] ([i915#4103]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/bat-adls-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-adls-6:         NOTRUN -> [SKIP][7] ([i915#16361])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/bat-adls-6/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-adls-6:         NOTRUN -> [SKIP][8]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/bat-adls-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-adls-6:         NOTRUN -> [SKIP][9] ([i915#5354])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/bat-adls-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - bat-adls-6:         NOTRUN -> [SKIP][10] ([i915#1072] / [i915#9732]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/bat-adls-6/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-adls-6:         NOTRUN -> [SKIP][11] ([i915#3555])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/bat-adls-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
    - bat-adls-6:         NOTRUN -> [SKIP][12] ([i915#3291]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/bat-adls-6/igt@prime_vgem@basic-fence-read.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@migrate:
    - fi-bsw-nick:        [DMESG-FAIL][13] -> [PASS][14] +1 other test pass
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9035/fi-bsw-nick/igt@i915_selftest@live@migrate.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/fi-bsw-nick/igt@i915_selftest@live@migrate.html

  
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#13735]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13735
  [i915#15656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15656
  [i915#16361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16361
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_9035 -> IGTPW_15618

  CI-20190529: 20190529
  CI_DRM_18932: f9ef9f302ee01854066ec6da30550da6ea6cb03a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_15618: 15618
  IGT_9035: 61674acebe1520ef02165573257f552366c2879c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15618/index.html

[-- Attachment #2: Type: text/html, Size: 5877 bytes --]

Re: [PATCH i-g-t 1/3] lib/xe/xe_spin: fix premature batch exit on BO resubmission

[Zbigniew Kempczyński]

On Fri, Jul 31, 2026 at 04:18:04PM +0200, Marcin Bernatowicz wrote:
> COND_BBE reads ticks_delta from memory. When the same BO is resubmitted,
> COND_BBE can read the value left by the previous batch(elapsed >= ctx_ticks
> at that batch's exit), satisfying the exit condition on the very first loop
> iteration before any new elapsed time is stored.
> 
> Write sentinel 0 to ticks_delta at batch start and use
> MI_SEMAPHORE_WAIT to poll until it is visible in memory before entering
> the loop. This guarantees COND_BBE cannot read the stale value from the
> previous batch.
> 
> Also switch from inverted ticks_delta logic (STOREINV + ~ctx_ticks) to
> direct elapsed ticks (STORE + MAD_LT_IDD + ctx_ticks) for readability.
> The pad loop between SRM and COND_BBE is removed as it does not help.
> 
> Suggested-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  lib/xe/xe_spin.c | 31 +++++++++++++++++--------------
>  1 file changed, 17 insertions(+), 14 deletions(-)
> 
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 874310789..2863d2163 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -52,7 +52,6 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
>  	uint64_t start_addr = opts->addr + offsetof(struct xe_spin, start);
>  	uint64_t end_addr = opts->addr + offsetof(struct xe_spin, end);
>  	uint64_t ticks_delta_addr = opts->addr + offsetof(struct xe_spin, ticks_delta);
> -	uint64_t pad_addr = opts->addr + offsetof(struct xe_spin, pad);
>  	uint64_t timestamp_addr = opts->addr + offsetof(struct xe_spin, timestamp);
>  	int b = 0;
>  	uint32_t devid;
> @@ -77,6 +76,18 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
>  	spin->batch[b++] = start_addr >> 32;
>  	spin->batch[b++] = 0xc0ffee;
>  
> +	if (opts->ctx_ticks) {
> +		/* Write sentinel and wait until it is visible in memory before loop. */
> +		spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> +		spin->batch[b++] = ticks_delta_addr;
> +		spin->batch[b++] = ticks_delta_addr >> 32;
> +		spin->batch[b++] = 0;
> +		spin->batch[b++] = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_POLL | MI_SEMAPHORE_SAD_EQ_SDD;
> +		spin->batch[b++] = 0;
> +		spin->batch[b++] = ticks_delta_addr;
> +		spin->batch[b++] = ticks_delta_addr >> 32;
> +	}
> +

Great, it is more reliable than resetting ticks_delta outside spinner code.

>  	loop_addr = opts->addr + b * sizeof(uint32_t);
>  
>  	if (opts->preempt)
> @@ -101,12 +112,12 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
>  		spin->batch[b++] = opts->use_queue_timestamp ? QUEUE_TIMESTAMP : CTX_TIMESTAMP;
>  		spin->batch[b++] = CS_GPR(NOW_TS);
>  
> -		/* delta = now - start; inverted to match COND_BBE */
> +		/* delta = now - start */
>  		spin->batch[b++] = MI_MATH(4);
>  		spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
>  		spin->batch[b++] = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
>  		spin->batch[b++] = MI_MATH_SUB;
> -		spin->batch[b++] = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
> +		spin->batch[b++] = MI_MATH_STORE(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
>  
>  		/* Save delta for reading by COND_BBE */
>  		spin->batch[b++] = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_CS_MMIO;
> @@ -114,17 +125,9 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
>  		spin->batch[b++] = ticks_delta_addr;
>  		spin->batch[b++] = ticks_delta_addr >> 32;
>  
> -		/* Delay between SRM and COND_BBE to post the writes */
> -		for (int n = 0; n < 8; n++) {
> -			spin->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> -			spin->batch[b++] = pad_addr;
> -			spin->batch[b++] = pad_addr >> 32;
> -			spin->batch[b++] = 0xc0ffee;
> -		}
> -
> -		/* Break if delta [time elapsed] > ns */
> -		spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2;
> -		spin->batch[b++] = ~(opts->ctx_ticks);
> +		/* Break if delta [time elapsed] >= ns */
> +		spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | MAD_LT_IDD | 2;
> +		spin->batch[b++] = opts->ctx_ticks;

And this is easier to read.

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

>  		spin->batch[b++] = ticks_delta_addr;
>  		spin->batch[b++] = ticks_delta_addr >> 32;
>  	}
> -- 
> 2.43.0
> 

Re: [PATCH i-g-t 2/3] benchmarks/gem_wsim: fix ticks_delta assertion for non-inverted logic

[Zbigniew Kempczyński]

On Fri, Jul 31, 2026 at 04:18:05PM +0200, Marcin Bernatowicz wrote:
> xe_spin now stores elapsed ticks directly in ticks_delta (not inverted).
> Update the post-execution assertion accordingly.
> 

LGTM:

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  benchmarks/gem_wsim.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index 8be44d0c8..462188708 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -2676,7 +2676,7 @@ static void xe_w_step_sync_and_verify(struct w_step *w)
>  
>  	if (!w->duration.unbound) {
>  		igt_assert(w->duration.requested_ticks && w->xe.data->spin.ticks_delta);
> -		igt_assert_lte(w->duration.requested_ticks, ~w->xe.data->spin.ticks_delta);
> +		igt_assert_lte(w->duration.requested_ticks, w->xe.data->spin.ticks_delta);
>  	}
>  }
>  
> -- 
> 2.43.0
> 

Re: [PATCH i-g-t 3/3] tests/xe_sriov_scheduling: fix ticks_delta check for non-inverted logic

[Zbigniew Kempczyński]

On Fri, Jul 31, 2026 at 04:18:06PM +0200, Marcin Bernatowicz wrote:
> xe_spin now stores elapsed ticks directly in ticks_delta (not inverted).
> Update subm_is_work_complete() accordingly.
>

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Lukasz Laguna <lukasz.laguna@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  tests/intel/xe_sriov_scheduling.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tests/intel/xe_sriov_scheduling.c b/tests/intel/xe_sriov_scheduling.c
> index 47cc5d9b0..5d30b961d 100644
> --- a/tests/intel/xe_sriov_scheduling.c
> +++ b/tests/intel/xe_sriov_scheduling.c
> @@ -189,7 +189,7 @@ static void subm_exec_slot(struct subm *s, unsigned int slot)
>  
>  static bool subm_is_work_complete(struct subm *s, unsigned int slot)
>  {
> -	return s->expected_ticks <= ~s->spin[slot]->ticks_delta;
> +	return s->expected_ticks <= s->spin[slot]->ticks_delta;
>  }
>  
>  static bool subm_is_exec_queue_banned(struct subm *s)
> -- 
> 2.43.0
>