From: nishit.sharma@intel.com
To: igt-dev@lists.freedesktop.org, kamil.konieczny@intel.com
Subject: [PATCH v2 5/9] tests/intel/xe_exec_reset: add gt-stress-reset-rapid-cycle subtest
Date: Tue, 18 Aug 2026 04:08:41 +0000 [thread overview]
Message-ID: <20260818040845.548727-6-nishit.sharma@intel.com> (raw)
In-Reply-To: <20260818040845.548727-1-nishit.sharma@intel.com>
From: Nishit Sharma <nishit.sharma@intel.com>
This extends concurrent reset and submission stress coverage to a
high-frequency reset scenario while keeping the existing stress harness
unchanged for other subtests.
Signed-off-by: Nishit Sharma <nishit.sharma@intel.com>
---
tests/intel/xe_exec_reset.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
index 2a822b29b..a9c3b593d 100644
--- a/tests/intel/xe_exec_reset.c
+++ b/tests/intel/xe_exec_reset.c
@@ -136,6 +136,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci,
#define RESET_SYNC_MODE (0x1 << 16)
#define MEM_PRESSURE_STRESS (0x1 << 17)
#define INVALIDATE_BO_STRESS (0x1 << 18)
+#define RAPID_RESET_STRESS (0x1 << 19)
/**
* SUBTEST: %s-cat-error
@@ -717,8 +718,10 @@ static void pressure_bo_destroy(int fd, uint32_t *bos, int count)
static void do_resets(struct gt_thread_data *t)
{
+ int interval_us = (t->flags & RAPID_RESET_STRESS) ? 1000 : 250000;
+
while (!*(t->exit)) {
- usleep(250000); /* 250 ms */
+ usleep(interval_us);
(*t->num_reset)++;
if (t->flags & RESET_SYNC_MODE)
xe_force_gt_reset_sync(t->fd, t->gt);
@@ -840,6 +843,10 @@ static void *gt_reset_thread(void *data)
* Description: Stress concurrent GT resets and job submissions while invalidating BO CPU mappings
* Test category: stress test
*
+ * SUBTEST: gt-stress-reset-rapid-cycle
+ * Description: Stress concurrent GT resets and job submissions with rapid-cycle resets
+ * Test category: stress test
+ *
*/
static void
gt_reset(int fd, int gt, int n_threads, int n_sec, unsigned int flags)
@@ -1061,6 +1068,7 @@ int igt_main()
{ "reset-concurrent-submit-sync", RESET_SYNC_MODE },
{ "reset-memory-pressure", MEM_PRESSURE_STRESS },
{ "reset-bo-invalidation", INVALIDATE_BO_STRESS },
+ { "reset-rapid-cycle", RAPID_RESET_STRESS },
{ NULL },
};
int gt;
--
2.43.0
next prev parent reply other threads:[~2026-08-18 4:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-18 4:08 [PATCH v2 0/9] extend GT reset stress coverage nishit.sharma
2026-08-18 4:08 ` [PATCH v2 1/9] tests/intel/xe_exec_reset: Add concurrent GT reset submit stress test nishit.sharma
2026-08-18 4:08 ` [PATCH v2 2/9] tests/intel/xe_exec_reset: add sync concurrent reset submit subtest nishit.sharma
2026-08-18 4:08 ` [PATCH v2 3/9] tests/intel/xe_exec_reset: add gt-stress-reset-memory-pressure subtest nishit.sharma
2026-08-18 4:08 ` [PATCH v2 4/9] tests/intel/xe_exec_reset: add gt-stress-reset-bo-invalidation subtest nishit.sharma
2026-08-18 4:08 ` nishit.sharma [this message]
2026-08-18 4:08 ` [PATCH v2 6/9] tests/intel/xe_exec_reset: add gt-stress-reset-destroy-vm-context subtest nishit.sharma
2026-08-18 4:08 ` [PATCH v2 7/9] tests/intel/xe_exec_reset: add gt-stress-reset-mixed-engine-usage subtest nishit.sharma
2026-08-18 4:08 ` [PATCH v2 8/9] tests/intel/xe_exec_reset: add gt-stress-reset-pm-transition subtest nishit.sharma
2026-08-18 4:08 ` [PATCH v2 9/9] tests/intel/xe_exec_reset: add gt-stress-reset-engine-hang subtest nishit.sharma
2026-08-18 4:50 ` ✓ Xe.CI.BAT: success for extend GT reset stress coverage (rev2) Patchwork
2026-08-18 5:04 ` ✓ i915.CI.BAT: " Patchwork
2026-08-18 5:56 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-08-18 16:04 ` ✗ i915.CI.Full: " Patchwork
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