[PATCH i-g-t 0/2] tests/intel/xe_prefetch_fault: Add L2 prefetch fault tests

[PATCH i-g-t 0/2] tests/intel/xe_prefetch_fault: Add L2 prefetch fault tests

[Varun Gupta]

Add coverage for L2 prefetch faults in the xe_prefetch_fault test.

The existing test framework is first refactored to support different
prefetch shader configurations. The second patch then adds coverage for
L2 prefetch faults in both regular and SVM modes.

Varun Gupta (2):
  tests/intel/xe_prefetch_fault: refactor test to accept shader function
    pointer
  tests/intel/xe_prefetch_fault: add L2 prefetch fault subtests

 tests/intel/xe_prefetch_fault.c | 120 +++++++++++++++++++++++++++++---
 1 file changed, 112 insertions(+), 8 deletions(-)

-- 
2.43.0

[PATCH i-g-t 1/2] tests/intel/xe_prefetch_fault: refactor test to accept shader function pointer

[Varun Gupta]

Parameterize test_prefetch_fault() to accept a shader getter function
pointer instead of hardcoding get_prefetch_shader(). This enables reuse
of the same test logic with different shader configurations (e.g., L2
prefetch fault shaders) without duplicating the test function.

No functional change for existing subtests.

Signed-off-by: Varun Gupta <varun.gupta@intel.com>
---
 tests/intel/xe_prefetch_fault.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/tests/intel/xe_prefetch_fault.c b/tests/intel/xe_prefetch_fault.c
index d3b5aff47..e86cd68d9 100644
--- a/tests/intel/xe_prefetch_fault.c
+++ b/tests/intel/xe_prefetch_fault.c
@@ -117,9 +117,11 @@ static struct intel_bb *xe_bb_create_on_offset(int fd, uint32_t exec_queue, uint
 	return ibb;
 }
 
+typedef struct gpgpu_shader *(*get_shader_fn)(int fd);
+
 static struct gpgpu_shader *get_prefetch_shader(int fd)
 {
-	static struct gpgpu_shader *shader;
+	struct gpgpu_shader *shader;
 
 	shader = gpgpu_shader_create(fd);
 	gpgpu_shader__prefetch_fault(shader, xe_canonical_va(fd, PREFETCH_ADDR));
@@ -130,14 +132,17 @@ static struct gpgpu_shader *get_prefetch_shader(int fd)
 
 /**
  * SUBTEST: prefetch-fault
- * Description: Validate prefetch fault and hit-under-miss behavior
+ * Description: Validate L1 prefetch fault and hit-under-miss behavior with
+ *		L1 cached, L2 cached cache policy (fault source: LSC)
  * Run type: FULL
  *
  * SUBTEST: prefetch-fault-svm
- * Description: Validate prefetch fault and hit-under-miss behavior in SVM mode
+ * Description: Validate L1 prefetch fault and hit-under-miss behavior in SVM
+ *		mode with L1 cached, L2 cached cache policy (fault source: LSC)
  * Run type: FULL
  */
-static void test_prefetch_fault(int fd, struct drm_xe_engine_class_instance *hwe, bool svm)
+static void test_prefetch_fault(int fd, struct drm_xe_engine_class_instance *hwe,
+				bool svm, get_shader_fn get_shader)
 {
 	uint64_t bb_offset = BB_OFFSET;
 	/*
@@ -191,7 +196,7 @@ static void test_prefetch_fault(int fd, struct drm_xe_engine_class_instance *hwe
 	ibb = xe_bb_create_on_offset(fd, exec_queue_id, vm, bb_offset, bb_size);
 	intel_bb_set_lr_mode(ibb, true);
 
-	shader = get_prefetch_shader(fd);
+	shader = get_shader(fd);
 	gpgpu_shader_exec(ibb, buf, w_dim.x, w_dim.y, shader, NULL, 0, 0);
 	gpgpu_shader_destroy(shader);
 	intel_bb_sync(ibb);
@@ -225,7 +230,7 @@ static void test_prefetch_fault(int fd, struct drm_xe_engine_class_instance *hwe
 	ibb = xe_bb_create_on_offset(fd, exec_queue_id, vm, bb_offset2, bb_size);
 	intel_bb_set_lr_mode(ibb, true);
 
-	shader = get_prefetch_shader(fd);
+	shader = get_shader(fd);
 	gpgpu_shader_exec(ibb, buf, w_dim.x, w_dim.y, shader, NULL, 0, 0);
 	gpgpu_shader_destroy(shader);
 	intel_bb_sync(ibb);
@@ -271,7 +276,8 @@ int igt_main()
 			    hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) {
 				igt_dynamic_f("%s%d", xe_engine_class_string(hwe->engine_class),
 					      hwe->engine_instance)
-					test_prefetch_fault(fd, hwe, false);
+					test_prefetch_fault(fd, hwe, false,
+							    get_prefetch_shader);
 			}
 		}
 	}
@@ -284,7 +290,8 @@ int igt_main()
 			    hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) {
 				igt_dynamic_f("%s%d", xe_engine_class_string(hwe->engine_class),
 					      hwe->engine_instance)
-					test_prefetch_fault(fd, hwe, true);
+					test_prefetch_fault(fd, hwe, true,
+							    get_prefetch_shader);
 			}
 		}
 	}
-- 
2.43.0

[PATCH i-g-t 2/2] tests/intel/xe_prefetch_fault: add L2 prefetch fault subtests

[Varun Gupta]

Add L2 prefetch fault testing. When L1 cache policy is
set to uncached (UC), the prefetch bypasses LSC and is sourced from L2
instead.

Add a new shader gpgpu_shader__l2_prefetch_fault() that uses message
descriptor 0x49C00 (L1UC_L2C_L3UC, cache control value 4) instead of
the existing 0x99C00 (L1C_L2C_L3C, cache control value 9). Only bits
[19:16] of the descriptor differ.

Add two new subtests:
  - l2-prefetch-fault: validates L2 prefetch fault with unmapped address
    followed by hit-under-miss with mapped page
  - l2-prefetch-fault-svm: same as above but in SVM mode with HMM-backed
    CPU page table resolution

Signed-off-by: Varun Gupta <varun.gupta@intel.com>
---
 tests/intel/xe_prefetch_fault.c | 97 +++++++++++++++++++++++++++++++++
 1 file changed, 97 insertions(+)

diff --git a/tests/intel/xe_prefetch_fault.c b/tests/intel/xe_prefetch_fault.c
index e86cd68d9..4843f56fd 100644
--- a/tests/intel/xe_prefetch_fault.c
+++ b/tests/intel/xe_prefetch_fault.c
@@ -81,6 +81,56 @@ L0:
 	)", lower_32_bits(addr), upper_32_bits(addr));
 }
 
+/**
+ * gpgpu_shader__l2_prefetch_fault:
+ * @shdr: shader to be modified
+ * @addr: ppgtt virtual address to raise L2 prefetch fault
+ *
+ * This shader can only be used when in efficient 64bit mode.
+ * For a given arbitrary ppgtt virtual address, it raises an L2 prefetch fault
+ * using load instruction with L1 uncached + L2 cached cache policy.
+ * With L1 uncached, the prefetch bypasses LSC and is sourced from L2.
+ */
+static void gpgpu_shader__l2_prefetch_fault(struct gpgpu_shader *shdr,
+					    uint64_t addr)
+{
+	igt_assert_f((addr & 0x7) == 0, "address must be aligned to QWord!\n");
+
+	emit_iga64_code(shdr, xe_l2_prefetch_fault_prefetch, R"(
+#define IGA64_FLAGS ""
+#if GFX_VER >= 4000
+#elif GFX_VER >= 3500
+L0:
+// Set base address with scalar register
+(W)	mov (1)		s0.0<1>:ud		ARG(0):ud
+(W)	mov (1)		s0.1<1>:ud		ARG(1):ud
+
+// A64 offset
+(W)	mov (8)		r30.0<1>:uq		0x0:uq
+
+// efficient 64bit Read with uncached L1, cached L2 and uncached L3
+// sendg ugm load - L2 prefetch (L1 bypass)
+// Message Descriptor
+//      DP_LOAD_STORE_STATELESS_DESC (HAS:2209865465)
+//      DP_CACHE_LOAD (HAS:2209865465) value 4 = L1UC_L2C_L3UC
+//      0x49C00 =>
+//      [45:44] Offset Scaling: 0 (disable)
+//      [43:22] Global Offset: 0
+//      [21] Overfetch: 0 (disable)
+//      [19:16] Cache: 4 (L1 uncached, L2 cached and L3 uncached)
+//      [15:14] Address Type and Size: 2 (Flat A64 Base, A64 Index)
+//      [13:11] Data Size: 3 (D64)
+//      [10:10] Transpose : 1 (enable)
+//      [9:7] Vector Size: 0 (Vector length 1)
+//      [5:0] Opcode: 0 (Load)
+// Prefetch operations are implemented using a NULL destination register.
+// L1 uncached forces the prefetch to bypass LSC, making L2 the fault source.
+(W)	sendg.ugm (1|M0)	null	r30:1	null:0	s0.0	0x49C00	{A@1,$5}
+
+#endif
+	)", lower_32_bits(addr), upper_32_bits(addr));
+}
+
 static struct intel_buf *
 create_buf(int fd, int width, int height, uint32_t color)
 {
@@ -130,6 +180,17 @@ static struct gpgpu_shader *get_prefetch_shader(int fd)
 	return shader;
 }
 
+static struct gpgpu_shader *get_l2_prefetch_shader(int fd)
+{
+	struct gpgpu_shader *shader;
+
+	shader = gpgpu_shader_create(fd);
+	gpgpu_shader__l2_prefetch_fault(shader, xe_canonical_va(fd, PREFETCH_ADDR));
+	gpgpu_shader__eot(shader);
+
+	return shader;
+}
+
 /**
  * SUBTEST: prefetch-fault
  * Description: Validate L1 prefetch fault and hit-under-miss behavior with
@@ -140,6 +201,16 @@ static struct gpgpu_shader *get_prefetch_shader(int fd)
  * Description: Validate L1 prefetch fault and hit-under-miss behavior in SVM
  *		mode with L1 cached, L2 cached cache policy (fault source: LSC)
  * Run type: FULL
+ *
+ * SUBTEST: l2-prefetch-fault
+ * Description: Validate L2 prefetch fault and hit-under-miss behavior with
+ *		L1 uncached, L2 cached cache policy (fault source: L2)
+ * Run type: FULL
+ *
+ * SUBTEST: l2-prefetch-fault-svm
+ * Description: Validate L2 prefetch fault and hit-under-miss behavior in SVM
+ *		mode with L1 uncached, L2 cached cache policy (fault source: L2)
+ * Run type: FULL
  */
 static void test_prefetch_fault(int fd, struct drm_xe_engine_class_instance *hwe,
 				bool svm, get_shader_fn get_shader)
@@ -296,6 +367,32 @@ int igt_main()
 		}
 	}
 
+	igt_subtest_with_dynamic("l2-prefetch-fault") {
+		xe_for_each_engine(fd, hwe) {
+			if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
+			    hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) {
+				igt_dynamic_f("%s%d", xe_engine_class_string(hwe->engine_class),
+					      hwe->engine_instance)
+					test_prefetch_fault(fd, hwe, false,
+							    get_l2_prefetch_shader);
+			}
+		}
+	}
+
+	igt_subtest_with_dynamic("l2-prefetch-fault-svm") {
+		if (!svm_supported)
+			igt_skip("SVM not supported on this device, skipping.\n");
+		xe_for_each_engine(fd, hwe) {
+			if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
+			    hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) {
+				igt_dynamic_f("%s%d", xe_engine_class_string(hwe->engine_class),
+					      hwe->engine_instance)
+					test_prefetch_fault(fd, hwe, true,
+							    get_l2_prefetch_shader);
+			}
+		}
+	}
+
 	igt_fixture() {
 		drm_close_driver(fd);
 	}
-- 
2.43.0

RE: [PATCH i-g-t 1/2] tests/intel/xe_prefetch_fault: refactor test to accept shader function pointer

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Gupta, Varun <varun.gupta@intel.com>
> Sent: 18 August 2026 10:57 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Dandamudi, Priyanka <priyanka.dandamudi@intel.com>
> Subject: [PATCH i-g-t 1/2] tests/intel/xe_prefetch_fault: refactor test to accept
> shader function pointer
> 
> Parameterize test_prefetch_fault() to accept a shader getter function pointer
> instead of hardcoding get_prefetch_shader(). This enables reuse of the same
> test logic with different shader configurations (e.g., L2 prefetch fault shaders)
> without duplicating the test function.
> 
> No functional change for existing subtests.
> 
> Signed-off-by: Varun Gupta <varun.gupta@intel.com>
> ---
>  tests/intel/xe_prefetch_fault.c | 23 +++++++++++++++--------
>  1 file changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/tests/intel/xe_prefetch_fault.c b/tests/intel/xe_prefetch_fault.c
> index d3b5aff47..e86cd68d9 100644
> --- a/tests/intel/xe_prefetch_fault.c
> +++ b/tests/intel/xe_prefetch_fault.c
> @@ -117,9 +117,11 @@ static struct intel_bb *xe_bb_create_on_offset(int fd,
> uint32_t exec_queue, uint
>  	return ibb;
>  }
> 
> +typedef struct gpgpu_shader *(*get_shader_fn)(int fd);
> +
>  static struct gpgpu_shader *get_prefetch_shader(int fd)  {
> -	static struct gpgpu_shader *shader;
> +	struct gpgpu_shader *shader;
> 
>  	shader = gpgpu_shader_create(fd);
>  	gpgpu_shader__prefetch_fault(shader, xe_canonical_va(fd,
> PREFETCH_ADDR)); @@ -130,14 +132,17 @@ static struct gpgpu_shader
> *get_prefetch_shader(int fd)
> 
>  /**
>   * SUBTEST: prefetch-fault
> - * Description: Validate prefetch fault and hit-under-miss behavior
> + * Description: Validate L1 prefetch fault and hit-under-miss behavior with
> + *		L1 cached, L2 cached cache policy (fault source: LSC)
>   * Run type: FULL
>   *
>   * SUBTEST: prefetch-fault-svm
> - * Description: Validate prefetch fault and hit-under-miss behavior in SVM
> mode
> + * Description: Validate L1 prefetch fault and hit-under-miss behavior in SVM
> + *		mode with L1 cached, L2 cached cache policy (fault source:
> LSC)
>   * Run type: FULL
>   */
> -static void test_prefetch_fault(int fd, struct drm_xe_engine_class_instance
> *hwe, bool svm)
> +static void test_prefetch_fault(int fd, struct drm_xe_engine_class_instance
> *hwe,
> +				bool svm, get_shader_fn get_shader)
>  {
>  	uint64_t bb_offset = BB_OFFSET;
>  	/*
> @@ -191,7 +196,7 @@ static void test_prefetch_fault(int fd, struct
> drm_xe_engine_class_instance *hwe
>  	ibb = xe_bb_create_on_offset(fd, exec_queue_id, vm, bb_offset,
> bb_size);
>  	intel_bb_set_lr_mode(ibb, true);
> 
> -	shader = get_prefetch_shader(fd);
> +	shader = get_shader(fd);
>  	gpgpu_shader_exec(ibb, buf, w_dim.x, w_dim.y, shader, NULL, 0, 0);
>  	gpgpu_shader_destroy(shader);
>  	intel_bb_sync(ibb);
> @@ -225,7 +230,7 @@ static void test_prefetch_fault(int fd, struct
> drm_xe_engine_class_instance *hwe
>  	ibb = xe_bb_create_on_offset(fd, exec_queue_id, vm, bb_offset2,
> bb_size);
>  	intel_bb_set_lr_mode(ibb, true);
> 
> -	shader = get_prefetch_shader(fd);
> +	shader = get_shader(fd);
>  	gpgpu_shader_exec(ibb, buf, w_dim.x, w_dim.y, shader, NULL, 0, 0);
>  	gpgpu_shader_destroy(shader);
>  	intel_bb_sync(ibb);
> @@ -271,7 +276,8 @@ int igt_main()
>  			    hwe->engine_class ==
> DRM_XE_ENGINE_CLASS_COMPUTE) {
>  				igt_dynamic_f("%s%d",
> xe_engine_class_string(hwe->engine_class),
>  					      hwe->engine_instance)
> -					test_prefetch_fault(fd, hwe, false);
> +					test_prefetch_fault(fd, hwe, false,
> +
> get_prefetch_shader);
>  			}
>  		}
>  	}
> @@ -284,7 +290,8 @@ int igt_main()
>  			    hwe->engine_class ==
> DRM_XE_ENGINE_CLASS_COMPUTE) {
>  				igt_dynamic_f("%s%d",
> xe_engine_class_string(hwe->engine_class),
>  					      hwe->engine_instance)
> -					test_prefetch_fault(fd, hwe, true);
> +					test_prefetch_fault(fd, hwe, true,
> +
> get_prefetch_shader);
>  			}
LGTM,
Reviewed-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>  		}
>  	}
> --
> 2.43.0

RE: [PATCH i-g-t 2/2] tests/intel/xe_prefetch_fault: add L2 prefetch fault subtests

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Gupta, Varun <varun.gupta@intel.com>
> Sent: 18 August 2026 10:57 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Dandamudi, Priyanka <priyanka.dandamudi@intel.com>
> Subject: [PATCH i-g-t 2/2] tests/intel/xe_prefetch_fault: add L2 prefetch fault
> subtests
> 
> Add L2 prefetch fault testing. When L1 cache policy is set to uncached (UC),
> the prefetch bypasses LSC and is sourced from L2 instead.
> 
> Add a new shader gpgpu_shader__l2_prefetch_fault() that uses message
> descriptor 0x49C00 (L1UC_L2C_L3UC, cache control value 4) instead of the
> existing 0x99C00 (L1C_L2C_L3C, cache control value 9). Only bits [19:16] of
> the descriptor differ.
> 
> Add two new subtests:
>   - l2-prefetch-fault: validates L2 prefetch fault with unmapped address
>     followed by hit-under-miss with mapped page
>   - l2-prefetch-fault-svm: same as above but in SVM mode with HMM-backed
>     CPU page table resolution
> 
> Signed-off-by: Varun Gupta <varun.gupta@intel.com>
> ---
>  tests/intel/xe_prefetch_fault.c | 97 +++++++++++++++++++++++++++++++++
>  1 file changed, 97 insertions(+)
> 
> diff --git a/tests/intel/xe_prefetch_fault.c b/tests/intel/xe_prefetch_fault.c
> index e86cd68d9..4843f56fd 100644
> --- a/tests/intel/xe_prefetch_fault.c
> +++ b/tests/intel/xe_prefetch_fault.c
> @@ -81,6 +81,56 @@ L0:
>  	)", lower_32_bits(addr), upper_32_bits(addr));  }
> 
> +/**
> + * gpgpu_shader__l2_prefetch_fault:
> + * @shdr: shader to be modified
> + * @addr: ppgtt virtual address to raise L2 prefetch fault
> + *
> + * This shader can only be used when in efficient 64bit mode.
> + * For a given arbitrary ppgtt virtual address, it raises an L2
> +prefetch fault
> + * using load instruction with L1 uncached + L2 cached cache policy.
> + * With L1 uncached, the prefetch bypasses LSC and is sourced from L2.
> + */
> +static void gpgpu_shader__l2_prefetch_fault(struct gpgpu_shader *shdr,
> +					    uint64_t addr)
> +{
> +	igt_assert_f((addr & 0x7) == 0, "address must be aligned to
> +QWord!\n");
> +
> +	emit_iga64_code(shdr, xe_l2_prefetch_fault_prefetch, R"( #define
> +IGA64_FLAGS ""
> +#if GFX_VER >= 4000
> +#elif GFX_VER >= 3500
> +L0:
> +// Set base address with scalar register
> +(W)	mov (1)		s0.0<1>:ud		ARG(0):ud
> +(W)	mov (1)		s0.1<1>:ud		ARG(1):ud
> +
> +// A64 offset
> +(W)	mov (8)		r30.0<1>:uq		0x0:uq
> +
> +// efficient 64bit Read with uncached L1, cached L2 and uncached L3 //
> +sendg ugm load - L2 prefetch (L1 bypass) // Message Descriptor
> +//      DP_LOAD_STORE_STATELESS_DESC (HAS:2209865465)
> +//      DP_CACHE_LOAD (HAS:2209865465) value 4 = L1UC_L2C_L3UC
> +//      0x49C00 =>
> +//      [45:44] Offset Scaling: 0 (disable)
> +//      [43:22] Global Offset: 0
> +//      [21] Overfetch: 0 (disable)
> +//      [19:16] Cache: 4 (L1 uncached, L2 cached and L3 uncached)
> +//      [15:14] Address Type and Size: 2 (Flat A64 Base, A64 Index)
> +//      [13:11] Data Size: 3 (D64)
> +//      [10:10] Transpose : 1 (enable)
> +//      [9:7] Vector Size: 0 (Vector length 1)
> +//      [5:0] Opcode: 0 (Load)
> +// Prefetch operations are implemented using a NULL destination register.
> +// L1 uncached forces the prefetch to bypass LSC, making L2 the fault source.
> +(W)	sendg.ugm (1|M0)	null	r30:1	null:0	s0.0	0x49C00
> 	{A@1,$5}
> +
> +#endif
> +	)", lower_32_bits(addr), upper_32_bits(addr)); }
> +
>  static struct intel_buf *
>  create_buf(int fd, int width, int height, uint32_t color)  { @@ -130,6 +180,17
> @@ static struct gpgpu_shader *get_prefetch_shader(int fd)
>  	return shader;
>  }
> 
> +static struct gpgpu_shader *get_l2_prefetch_shader(int fd) {
> +	struct gpgpu_shader *shader;
> +
> +	shader = gpgpu_shader_create(fd);
> +	gpgpu_shader__l2_prefetch_fault(shader, xe_canonical_va(fd,
> PREFETCH_ADDR));
> +	gpgpu_shader__eot(shader);
> +
> +	return shader;
> +}
> +
>  /**
>   * SUBTEST: prefetch-fault
>   * Description: Validate L1 prefetch fault and hit-under-miss behavior with
> @@ -140,6 +201,16 @@ static struct gpgpu_shader *get_prefetch_shader(int
> fd)
>   * Description: Validate L1 prefetch fault and hit-under-miss behavior in SVM
>   *		mode with L1 cached, L2 cached cache policy (fault source:
> LSC)
>   * Run type: FULL
> + *
> + * SUBTEST: l2-prefetch-fault
> + * Description: Validate L2 prefetch fault and hit-under-miss behavior with
> + *		L1 uncached, L2 cached cache policy (fault source: L2)
> + * Run type: FULL
> + *
> + * SUBTEST: l2-prefetch-fault-svm
> + * Description: Validate L2 prefetch fault and hit-under-miss behavior in SVM
> + *		mode with L1 uncached, L2 cached cache policy (fault source:
> L2)
> + * Run type: FULL
>   */
>  static void test_prefetch_fault(int fd, struct drm_xe_engine_class_instance
> *hwe,
>  				bool svm, get_shader_fn get_shader) @@ -
> 296,6 +367,32 @@ int igt_main()
>  		}
>  	}
> 
> +	igt_subtest_with_dynamic("l2-prefetch-fault") {
> +		xe_for_each_engine(fd, hwe) {
> +			if (hwe->engine_class ==
> DRM_XE_ENGINE_CLASS_RENDER ||
> +			    hwe->engine_class ==
> DRM_XE_ENGINE_CLASS_COMPUTE) {
> +				igt_dynamic_f("%s%d",
> xe_engine_class_string(hwe->engine_class),
> +					      hwe->engine_instance)
> +					test_prefetch_fault(fd, hwe, false,
> +
> get_l2_prefetch_shader);
> +			}
> +		}
> +	}
> +
> +	igt_subtest_with_dynamic("l2-prefetch-fault-svm") {
> +		if (!svm_supported)
> +			igt_skip("SVM not supported on this device,
> skipping.\n");
> +		xe_for_each_engine(fd, hwe) {
> +			if (hwe->engine_class ==
> DRM_XE_ENGINE_CLASS_RENDER ||
> +			    hwe->engine_class ==
> DRM_XE_ENGINE_CLASS_COMPUTE) {
> +				igt_dynamic_f("%s%d",
> xe_engine_class_string(hwe->engine_class),
> +					      hwe->engine_instance)
> +					test_prefetch_fault(fd, hwe, true,
> +
> get_l2_prefetch_shader);
> +			}
> +		}
> +	}
> +
LGTM,
Reviewed-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>  	igt_fixture() {
>  		drm_close_driver(fd);
>  	}
> --
> 2.43.0

RE: [PATCH i-g-t 1/2] tests/intel/xe_prefetch_fault: refactor test to accept shader function pointer

[Dandamudi, Priyanka]

> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of
> Dandamudi, Priyanka
> Sent: 18 August 2026 11:42 AM
> To: Gupta, Varun <varun.gupta@intel.com>; igt-dev@lists.freedesktop.org
> Subject: RE: [PATCH i-g-t 1/2] tests/intel/xe_prefetch_fault: refactor test to
> accept shader function pointer
> 
> 
> 
> > -----Original Message-----
> > From: Gupta, Varun <varun.gupta@intel.com>
> > Sent: 18 August 2026 10:57 AM
> > To: igt-dev@lists.freedesktop.org
> > Cc: Dandamudi, Priyanka <priyanka.dandamudi@intel.com>
> > Subject: [PATCH i-g-t 1/2] tests/intel/xe_prefetch_fault: refactor
> > test to accept shader function pointer
> >
> > Parameterize test_prefetch_fault() to accept a shader getter function
> > pointer instead of hardcoding get_prefetch_shader(). This enables
> > reuse of the same test logic with different shader configurations
> > (e.g., L2 prefetch fault shaders) without duplicating the test function.
> >
> > No functional change for existing subtests.
> >
> > Signed-off-by: Varun Gupta <varun.gupta@intel.com>
> > ---
> >  tests/intel/xe_prefetch_fault.c | 23 +++++++++++++++--------
> >  1 file changed, 15 insertions(+), 8 deletions(-)
> >
> > diff --git a/tests/intel/xe_prefetch_fault.c
> > b/tests/intel/xe_prefetch_fault.c index d3b5aff47..e86cd68d9 100644
> > --- a/tests/intel/xe_prefetch_fault.c
> > +++ b/tests/intel/xe_prefetch_fault.c
> > @@ -117,9 +117,11 @@ static struct intel_bb
> > *xe_bb_create_on_offset(int fd, uint32_t exec_queue, uint
> >  	return ibb;
> >  }
> >
> > +typedef struct gpgpu_shader *(*get_shader_fn)(int fd);
> > +
> >  static struct gpgpu_shader *get_prefetch_shader(int fd)  {
> > -	static struct gpgpu_shader *shader;
> > +	struct gpgpu_shader *shader;
> >
> >  	shader = gpgpu_shader_create(fd);
> >  	gpgpu_shader__prefetch_fault(shader, xe_canonical_va(fd,
> > PREFETCH_ADDR)); @@ -130,14 +132,17 @@ static struct gpgpu_shader
> > *get_prefetch_shader(int fd)
> >
> >  /**
> >   * SUBTEST: prefetch-fault
> > - * Description: Validate prefetch fault and hit-under-miss behavior
> > + * Description: Validate L1 prefetch fault and hit-under-miss behavior with
> > + *		L1 cached, L2 cached cache policy (fault source: LSC)
> >   * Run type: FULL
> >   *
> >   * SUBTEST: prefetch-fault-svm
> > - * Description: Validate prefetch fault and hit-under-miss behavior
> > in SVM mode
> > + * Description: Validate L1 prefetch fault and hit-under-miss behavior in
> SVM
> > + *		mode with L1 cached, L2 cached cache policy (fault source:
> > LSC)
> >   * Run type: FULL
> >   */
> > -static void test_prefetch_fault(int fd, struct
> > drm_xe_engine_class_instance *hwe, bool svm)
> > +static void test_prefetch_fault(int fd, struct
> > +drm_xe_engine_class_instance
> > *hwe,
> > +				bool svm, get_shader_fn get_shader)
> >  {
> >  	uint64_t bb_offset = BB_OFFSET;
> >  	/*
> > @@ -191,7 +196,7 @@ static void test_prefetch_fault(int fd, struct
> > drm_xe_engine_class_instance *hwe
> >  	ibb = xe_bb_create_on_offset(fd, exec_queue_id, vm, bb_offset,
> > bb_size);
> >  	intel_bb_set_lr_mode(ibb, true);
> >
> > -	shader = get_prefetch_shader(fd);
> > +	shader = get_shader(fd);
> >  	gpgpu_shader_exec(ibb, buf, w_dim.x, w_dim.y, shader, NULL, 0, 0);
> >  	gpgpu_shader_destroy(shader);
> >  	intel_bb_sync(ibb);
> > @@ -225,7 +230,7 @@ static void test_prefetch_fault(int fd, struct
> > drm_xe_engine_class_instance *hwe
> >  	ibb = xe_bb_create_on_offset(fd, exec_queue_id, vm, bb_offset2,
> > bb_size);
> >  	intel_bb_set_lr_mode(ibb, true);
> >
> > -	shader = get_prefetch_shader(fd);
> > +	shader = get_shader(fd);
> >  	gpgpu_shader_exec(ibb, buf, w_dim.x, w_dim.y, shader, NULL, 0, 0);
> >  	gpgpu_shader_destroy(shader);
> >  	intel_bb_sync(ibb);
> > @@ -271,7 +276,8 @@ int igt_main()
> >  			    hwe->engine_class ==
> > DRM_XE_ENGINE_CLASS_COMPUTE) {
> >  				igt_dynamic_f("%s%d",
> > xe_engine_class_string(hwe->engine_class),
> >  					      hwe->engine_instance)
> > -					test_prefetch_fault(fd, hwe, false);
> > +					test_prefetch_fault(fd, hwe, false,
> > +
> > get_prefetch_shader);
> >  			}
> >  		}
> >  	}
> > @@ -284,7 +290,8 @@ int igt_main()
> >  			    hwe->engine_class ==
> > DRM_XE_ENGINE_CLASS_COMPUTE) {
> >  				igt_dynamic_f("%s%d",
> > xe_engine_class_string(hwe->engine_class),
> >  					      hwe->engine_instance)
> > -					test_prefetch_fault(fd, hwe, true);
> > +					test_prefetch_fault(fd, hwe, true,
> > +
> > get_prefetch_shader);
> >  			}
> LGTM,
> Reviewed-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> >  		}
Build failed, can you check once.
> >  	}
> > --
> > 2.43.0

Re: [PATCH i-g-t 2/2] tests/intel/xe_prefetch_fault: add L2 prefetch fault subtests

[Kamil Konieczny]

Hi Varun,
On 2026-08-18 at 10:57:16 +0530, Varun Gupta wrote:
> Add L2 prefetch fault testing. When L1 cache policy is
> set to uncached (UC), the prefetch bypasses LSC and is sourced from L2
> instead.
> 
> Add a new shader gpgpu_shader__l2_prefetch_fault() that uses message
> descriptor 0x49C00 (L1UC_L2C_L3UC, cache control value 4) instead of
> the existing 0x99C00 (L1C_L2C_L3C, cache control value 9). Only bits
> [19:16] of the descriptor differ.

When you add a new shader you also need to add it to compiled
source in tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c

Now linking on armhf fails with:

[1314/1800] Linking target tests/xe_prefetch_fault
FAILED: tests/xe_prefetch_fault 
/usr/bin/arm-linux-gnueabihf-gcc  -o tests/xe_prefetch_fault tests/xe_prefetch_fault.p/intel_xe_prefetch_fault.c.o -Wl,--as-needed -Wl,--no-undefined -Wl,--start-group lib/libigt.so.0 /usr/lib/arm-linux-gnueabihf/libcairo.so /usr/lib/arm-linux-gnueabihf/libglib-2.0.so /usr/lib/arm-linux-gnueabihf/libdrm.so /usr/lib/arm-linux-gnueabihf/libdw.so /usr/lib/arm-linux-gnueabihf/libelf.so /usr/lib/arm-linux-gnueabihf/libkmod.so /usr/lib/arm-linux-gnueabihf/libpci.so /usr/lib/arm-linux-gnueabihf/libudev.so -lm /usr/lib/arm-linux-gnueabihf/libpciaccess.so /usr/lib/arm-linux-gnueabihf/libpixman-1.so -pthread -lrt -lz /usr/lib/arm-linux-gnueabihf/libdrm_nouveau.so /usr/lib/arm-linux-gnueabihf/libdrm_amdgpu.so /usr/lib/arm-linux-gnueabihf/libunwind.so /usr/lib/arm-linux-gnueabihf/libgsl.so /usr/lib/arm-linux-gnueabihf/libgslcblas.so /usr/lib/arm-linux-gnueabihf/libasound.so -Wl,--end-group '-Wl,-rpath,$ORIGIN/../lib' -Wl,-rpath-link,/opt/builds/build/lib
/usr/lib/gcc-cross/arm-linux-gnueabihf/10/../../../../arm-linux-gnueabihf/bin/ld: tests/xe_prefetch_fault.p/intel_xe_prefetch_fault.c.o: in function `gpgpu_shader__l2_prefetch_fault':
/opt/builds/build/../tests/intel/xe_prefetch_fault.c:97: undefined reference to `iga64_code_xe_l2_prefetch_fault_prefetch'
collect2: error: ld returned 1 exit status
ninja: build stopped: subcommand failed.

+cc Andrzej Hajda



Regards,
Kamil

> 
> Add two new subtests:
>   - l2-prefetch-fault: validates L2 prefetch fault with unmapped address
>     followed by hit-under-miss with mapped page
>   - l2-prefetch-fault-svm: same as above but in SVM mode with HMM-backed
>     CPU page table resolution
> 
> Signed-off-by: Varun Gupta <varun.gupta@intel.com>
> ---
>  tests/intel/xe_prefetch_fault.c | 97 +++++++++++++++++++++++++++++++++
>  1 file changed, 97 insertions(+)
> 
> diff --git a/tests/intel/xe_prefetch_fault.c b/tests/intel/xe_prefetch_fault.c
> index e86cd68d9..4843f56fd 100644
> --- a/tests/intel/xe_prefetch_fault.c
> +++ b/tests/intel/xe_prefetch_fault.c
> @@ -81,6 +81,56 @@ L0:
>  	)", lower_32_bits(addr), upper_32_bits(addr));
>  }
>  
> +/**
> + * gpgpu_shader__l2_prefetch_fault:
> + * @shdr: shader to be modified
> + * @addr: ppgtt virtual address to raise L2 prefetch fault
> + *
> + * This shader can only be used when in efficient 64bit mode.
> + * For a given arbitrary ppgtt virtual address, it raises an L2 prefetch fault
> + * using load instruction with L1 uncached + L2 cached cache policy.
> + * With L1 uncached, the prefetch bypasses LSC and is sourced from L2.
> + */
> +static void gpgpu_shader__l2_prefetch_fault(struct gpgpu_shader *shdr,
> +					    uint64_t addr)
> +{
> +	igt_assert_f((addr & 0x7) == 0, "address must be aligned to QWord!\n");
> +
> +	emit_iga64_code(shdr, xe_l2_prefetch_fault_prefetch, R"(
> +#define IGA64_FLAGS ""
> +#if GFX_VER >= 4000
> +#elif GFX_VER >= 3500
> +L0:
> +// Set base address with scalar register
> +(W)	mov (1)		s0.0<1>:ud		ARG(0):ud
> +(W)	mov (1)		s0.1<1>:ud		ARG(1):ud
> +
> +// A64 offset
> +(W)	mov (8)		r30.0<1>:uq		0x0:uq
> +
> +// efficient 64bit Read with uncached L1, cached L2 and uncached L3
> +// sendg ugm load - L2 prefetch (L1 bypass)
> +// Message Descriptor
> +//      DP_LOAD_STORE_STATELESS_DESC (HAS:2209865465)
> +//      DP_CACHE_LOAD (HAS:2209865465) value 4 = L1UC_L2C_L3UC
> +//      0x49C00 =>
> +//      [45:44] Offset Scaling: 0 (disable)
> +//      [43:22] Global Offset: 0
> +//      [21] Overfetch: 0 (disable)
> +//      [19:16] Cache: 4 (L1 uncached, L2 cached and L3 uncached)
> +//      [15:14] Address Type and Size: 2 (Flat A64 Base, A64 Index)
> +//      [13:11] Data Size: 3 (D64)
> +//      [10:10] Transpose : 1 (enable)
> +//      [9:7] Vector Size: 0 (Vector length 1)
> +//      [5:0] Opcode: 0 (Load)
> +// Prefetch operations are implemented using a NULL destination register.
> +// L1 uncached forces the prefetch to bypass LSC, making L2 the fault source.
> +(W)	sendg.ugm (1|M0)	null	r30:1	null:0	s0.0	0x49C00	{A@1,$5}
> +
> +#endif
> +	)", lower_32_bits(addr), upper_32_bits(addr));
> +}
> +
>  static struct intel_buf *
>  create_buf(int fd, int width, int height, uint32_t color)
>  {
> @@ -130,6 +180,17 @@ static struct gpgpu_shader *get_prefetch_shader(int fd)
>  	return shader;
>  }
>  
> +static struct gpgpu_shader *get_l2_prefetch_shader(int fd)
> +{
> +	struct gpgpu_shader *shader;
> +
> +	shader = gpgpu_shader_create(fd);
> +	gpgpu_shader__l2_prefetch_fault(shader, xe_canonical_va(fd, PREFETCH_ADDR));
> +	gpgpu_shader__eot(shader);
> +
> +	return shader;
> +}
> +
>  /**
>   * SUBTEST: prefetch-fault
>   * Description: Validate L1 prefetch fault and hit-under-miss behavior with
> @@ -140,6 +201,16 @@ static struct gpgpu_shader *get_prefetch_shader(int fd)
>   * Description: Validate L1 prefetch fault and hit-under-miss behavior in SVM
>   *		mode with L1 cached, L2 cached cache policy (fault source: LSC)
>   * Run type: FULL
> + *
> + * SUBTEST: l2-prefetch-fault
> + * Description: Validate L2 prefetch fault and hit-under-miss behavior with
> + *		L1 uncached, L2 cached cache policy (fault source: L2)
> + * Run type: FULL
> + *
> + * SUBTEST: l2-prefetch-fault-svm
> + * Description: Validate L2 prefetch fault and hit-under-miss behavior in SVM
> + *		mode with L1 uncached, L2 cached cache policy (fault source: L2)
> + * Run type: FULL
>   */
>  static void test_prefetch_fault(int fd, struct drm_xe_engine_class_instance *hwe,
>  				bool svm, get_shader_fn get_shader)
> @@ -296,6 +367,32 @@ int igt_main()
>  		}
>  	}
>  
> +	igt_subtest_with_dynamic("l2-prefetch-fault") {
> +		xe_for_each_engine(fd, hwe) {
> +			if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
> +			    hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) {
> +				igt_dynamic_f("%s%d", xe_engine_class_string(hwe->engine_class),
> +					      hwe->engine_instance)
> +					test_prefetch_fault(fd, hwe, false,
> +							    get_l2_prefetch_shader);
> +			}
> +		}
> +	}
> +
> +	igt_subtest_with_dynamic("l2-prefetch-fault-svm") {
> +		if (!svm_supported)
> +			igt_skip("SVM not supported on this device, skipping.\n");
> +		xe_for_each_engine(fd, hwe) {
> +			if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
> +			    hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) {
> +				igt_dynamic_f("%s%d", xe_engine_class_string(hwe->engine_class),
> +					      hwe->engine_instance)
> +					test_prefetch_fault(fd, hwe, true,
> +							    get_l2_prefetch_shader);
> +			}
> +		}
> +	}
> +
>  	igt_fixture() {
>  		drm_close_driver(fd);
>  	}
> -- 
> 2.43.0
>