[PATCH i-g-t v2 0/7] Validate PM_PME signalling on display hotplug

[PATCH i-g-t v2 0/7] Validate PM_PME signalling on display hotplug

[Pranay Samala]

A display hotplug can be signalled as a PCI PME while the graphics device
is runtime suspended in D3hot. That lets the driver leave the
drm_kms_helper connector poll worker disabled across runtime suspend, so
the device stays parked instead of being resumed every ~10s just to probe
connectors.

The property worth validating is therefore not "does a hotplug still
work" - the polling fallback delivers that too, just slowly and at the
cost of the power saving. It is "does the hotplug work while polling
stays off". A test that only toggles HPD and waits for a uevent passes
either way, and would not notice the feature regressing into the
fallback.

So the new subtest runs two phases against the same suspended device:

  Phase 1: hold the device idle in D3hot for 25s and check from PCI
           config space that it never leaves D3hot. This is the power
           saving.
  Phase 2: toggle HPD from D3hot and check that a uevent arrives, that
           the connector status updated, and that
           power/wakeup_active_count incremented - i.e. that the resume
           was signalled by the device and not initiated by the host.

Patches 1-2 add the PCI Power Management capability register layout and
accessors for PME_Support, PME_En, PME_Status and the PowerState field.
PME_Status distinguishes a device that signalled but was never
acknowledged from one that never signalled at all, which makes a failure
report actionable instead of just "no uevent".

Patches 3-5 add the power/wakeup and power/wakeup_active_count
accessors, with patch 3 factoring out the path construction they share.
active_count is used rather than wakeup_count because the latter never
moves for a runtime resume.

Patch 6 adds igt_pm_kms_poll_save(), _set() and _restore(). The two
tests that already open code this are converted in a separate series
that depends on this one, since one of them also has a pre-existing
restore-without-save bug unrelated to PME.

Patch 7 adds the subtest.

v2:
- Rebase

Pranay Samala (7):
  lib/igt_pci: Add PCI Power Management capability register layout
  lib/igt_pm: Add PCI PME capability and D state accessors
  lib/igt_pm: Factor out power attribute path construction
  lib/igt_pm: Add power/wakeup accessors
  lib/igt_pm: Add power/wakeup_active_count accessor
  lib/igt_pm: Add drm_kms_helper.poll save/restore helpers
  tests/chamelium/kms_chamelium_hpd: Add HPD from runtime suspended
    D3hot

 lib/igt_pci.h                       |  12 +
 lib/igt_pm.c                        | 457 +++++++++++++++++++++++++++-
 lib/igt_pm.h                        |  12 +
 tests/chamelium/kms_chamelium_hpd.c | 344 +++++++++++++++++++++
 4 files changed, 816 insertions(+), 9 deletions(-)

-- 
2.53.0

[PATCH i-g-t v2 1/7] lib/igt_pci: Add PCI Power Management capability register layout

[Pranay Samala]

Add the register offsets and field masks of the PCI Power Management
capability. Two registers are needed.

PMC (PM Capabilities) holds the PME_Support field, which says what D states
the device can send a PME from.

PMCS (PM Control/Status) holds the PowerState field, the PME_En bit and the
PME_Status bit, which say what D state the device is in, whether it is
armed to send a PME, and whether it has one pending. PME_Status is
write-1-to-clear and stays set until someone acknowledges the PME, so it
distinguishes a device that never signalled from one whose signal was never
delivered.

Assisted-by: GitHub_Copilot:claude-opus-5
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
---
 lib/igt_pci.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/lib/igt_pci.h b/lib/igt_pci.h
index 509345b2d..ae612d611 100644
--- a/lib/igt_pci.h
+++ b/lib/igt_pci.h
@@ -26,6 +26,18 @@ enum pci_cap_id {
 #define PCI_SLOT_CAP_OFFSET 0x14
 #define  PCI_SLOT_PWR_CTRL_PRESENT (1 << 1)
 
+/*
+ * PCI Power Management capability registers, at the given offsets from the
+ * start of the PM capability as returned by find_pci_cap_offset().
+ */
+#define PCI_PM_PMC_OFFSET 0x2			/* PM Capabilities */
+#define  PCI_PM_PMC_PME_SUPPORT_SHIFT 11	/* PME_Support, bits [15:11] */
+#define  PCI_PM_PMC_PME_SUPPORT_MASK (0x1f << PCI_PM_PMC_PME_SUPPORT_SHIFT)
+#define PCI_PM_PMCS_OFFSET 0x4			/* PM Control/Status */
+#define  PCI_PM_PMCS_PSTATE_MASK 0x3		/* PowerState, bits [1:0] */
+#define  PCI_PM_PMCS_PME_EN (1 << 8)		/* PME_En */
+#define  PCI_PM_PMCS_PME_STATUS (1 << 15)	/* PME_Status, write 1 to clear */
+
 int find_pci_cap_offset(struct pci_device *dev, enum pci_cap_id cap_id);
 int igt_pci_device_unbind(const char *pci_slot);
 int igt_pci_driver_bind(const char *driver, const char *pci_slot);
-- 
2.53.0

RE: [PATCH i-g-t v2 1/7] lib/igt_pci: Add PCI Power Management capability register layout

[Joshi, Kunal1]

Hello Pranay,

> -----Original Message-----
> From: Samala, Pranay <pranay.samala@intel.com>
> Sent: Friday, October 9, 2026 10:56 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Joshi, Kunal1 <kunal1.joshi@intel.com>; Lattannavar, Sameer
> <sameer.lattannavar@intel.com>; Samala, Pranay
> <pranay.samala@intel.com>
> Subject: [PATCH i-g-t v2 1/7] lib/igt_pci: Add PCI Power Management
> capability register layout
> 
> Add the register offsets and field masks of the PCI Power Management
> capability. Two registers are needed.
> 
> PMC (PM Capabilities) holds the PME_Support field, which says what D states
> the device can send a PME from.
> 
> PMCS (PM Control/Status) holds the PowerState field, the PME_En bit and
> the PME_Status bit, which say what D state the device is in, whether it is
> armed to send a PME, and whether it has one pending. PME_Status is write-
> 1-to-clear and stays set until someone acknowledges the PME, so it
> distinguishes a device that never signalled from one whose signal was never
> delivered.
> 
> Assisted-by: GitHub_Copilot:claude-opus-5
> Signed-off-by: Pranay Samala <pranay.samala@intel.com>

Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>

[PATCH i-g-t v2 2/7] lib/igt_pm: Add PCI PME capability and D state accessors

[Pranay Samala]

Add four helpers that read the PCI Power Management capability.

igt_pm_pci_pme_supported() says whether the device can send a PME from a
given D state, by testing one bit of the PME_Support field.
The state matters. Intel graphics devices support PME in D3hot but not in
D3cold.

igt_pm_pci_pme_enabled() reads PME_En, which says whether the device is
armed to send a PME. Its kerneldoc notes that a driver may arm PME from
its own runtime suspend hook rather than leaving it to the PCI/PM core,
and that xe does so subject to device_may_wakeup(), i.e. subject to
power/wakeup.

igt_pm_pci_pme_status() reads PME_Status, which says whether the device has
a PME pending. Because the bit is write-1-to-clear and nothing but software
clears it, a test that expected a wakeup and did not get one can use this
to tell a device that never signalled from one whose signal was never
delivered.

igt_pm_pci_get_d_state() reads the PowerState field. Its kerneldoc points
out that PMCS can only ever report D0-D3hot, and that it cannot be used to
detect D3cold: config space here is reached through sysfs, where
pci_config_pm_runtime_get() resumes a device in D3cold before the read, so
such a device reports D0.

Assisted-by: GitHub_Copilot:claude-opus-5
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
---
 lib/igt_pm.c | 162 +++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_pm.h |   5 ++
 2 files changed, 167 insertions(+)

diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 1e3cc7757..b1f9868eb 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -1524,6 +1524,168 @@ bool igt_has_pci_pm_capability(struct pci_device *pci_dev)
 	return (offset > 0);
 }
 
+/*
+ * Read a 16 bit register of the PCI Power Management capability, at @reg_offset
+ * from the start of the capability. Returns false if the device has no PM
+ * capability, the config space read failed, or the device did not respond.
+ *
+ * Config space reads do not resume a device suspended into D3hot, so these are
+ * safe to use while the device is runtime suspended. They are not a way to
+ * observe D3cold though: the read goes through sysfs, where
+ * pci_config_pm_runtime_get() resumes a device in D3cold first, so such a
+ * device answers as D0 rather than dropping off the bus.
+ */
+static bool igt_pm_read_pci_pm_reg(struct pci_device *pci_dev, int reg_offset,
+				   uint16_t *val)
+{
+	int offset;
+
+	offset = find_pci_cap_offset(pci_dev, PCI_PM_CAP_ID);
+	if (offset <= 0)
+		return false;
+
+	if (pci_device_cfg_read_u16(pci_dev, val, offset + reg_offset))
+		return false;
+
+	/*
+	 * A device that has gone away reads back as all ones, which would
+	 * otherwise decode as a valid register value: PMCS 0xffff means
+	 * PowerState = D3hot with PME_En set. Reject it.
+	 */
+	return *val != 0xffff;
+}
+
+/**
+ * igt_pm_pci_pme_supported:
+ * @pci_dev: PCI device struct
+ * @state: D state to query PME support for
+ *
+ * Reads the PME_Support field (bits [15:11]) of the PCI Power Management
+ * Capabilities (PMC) register and reports whether the device is able to
+ * generate a Power Management Event from @state.
+ *
+ * Note that PME support is per D state: Intel graphics devices typically
+ * advertise PME support in D3hot but not in D3cold, so a state agnostic check
+ * is not sufficient to decide whether PME based signalling can be used.
+ *
+ * Returns: true if the device can generate a PME from @state, false otherwise.
+ */
+bool igt_pm_pci_pme_supported(struct pci_device *pci_dev,
+			      enum igt_acpi_d_state state)
+{
+	uint16_t pmc;
+	int bit;
+
+	switch (state) {
+	case IGT_ACPI_D0:
+		bit = 0;
+		break;
+	case IGT_ACPI_D1:
+		bit = 1;
+		break;
+	case IGT_ACPI_D2:
+		bit = 2;
+		break;
+	case IGT_ACPI_D3Hot:
+		bit = 3;
+		break;
+	case IGT_ACPI_D3Cold:
+		bit = 4;
+		break;
+	default:
+		igt_debug("Invalid D state %d for PME support query\n", state);
+		return false;
+	}
+
+	if (!igt_pm_read_pci_pm_reg(pci_dev, PCI_PM_PMC_OFFSET, &pmc))
+		return false;
+
+	igt_debug("PCI '%04x:%02x:%02x.%01x' PMC = 0x%04x, PME_Support = 0x%02x\n",
+		  pci_dev->domain, pci_dev->bus, pci_dev->dev, pci_dev->func, pmc,
+		  (pmc & PCI_PM_PMC_PME_SUPPORT_MASK) >> PCI_PM_PMC_PME_SUPPORT_SHIFT);
+
+	return !!(pmc & (1 << (PCI_PM_PMC_PME_SUPPORT_SHIFT + bit)));
+}
+
+/**
+ * igt_pm_pci_pme_enabled:
+ * @pci_dev: PCI device struct
+ *
+ * Reads PME_En (bit 8) of the PCI Power Management Control/Status (PMCS)
+ * register, i.e. whether the device is armed to generate PMEs.
+ *
+ * The PCI/PM core sets this on suspend if the device can generate a PME from the
+ * state it is suspending into, but a driver may also arm PME itself from its
+ * runtime suspend hook, in which case the driver's own conditions apply. xe does
+ * exactly that, and requires the device_may_wakeup() policy behind power/wakeup,
+ * so on xe this bit follows power/wakeup even for a runtime suspend. See
+ * igt_pm_set_wakeup_enabled().
+ *
+ * Returns: true if the device is armed to generate PMEs, false otherwise.
+ */
+bool igt_pm_pci_pme_enabled(struct pci_device *pci_dev)
+{
+	uint16_t pmcs;
+
+	if (!igt_pm_read_pci_pm_reg(pci_dev, PCI_PM_PMCS_OFFSET, &pmcs))
+		return false;
+
+	return !!(pmcs & PCI_PM_PMCS_PME_EN);
+}
+
+/**
+ * igt_pm_pci_pme_status:
+ * @pci_dev: PCI device struct
+ *
+ * Reads PME_Status (bit 15) of the PCI Power Management Control/Status (PMCS)
+ * register, i.e. whether the device has a PME pending.
+ *
+ * The bit is write-1-to-clear and the device does not clear it itself. It stays
+ * set from the moment the device signals a PME until software acknowledges it,
+ * which for a runtime resume is pci_pme_wakeup() on the way back to D0. So
+ * finding it still set on a device that is still suspended means the device did
+ * signal but the platform never delivered the PME, whereas finding it clear
+ * means the device never signalled at all.
+ *
+ * Returns: true if the device has a PME pending, false otherwise.
+ */
+bool igt_pm_pci_pme_status(struct pci_device *pci_dev)
+{
+	uint16_t pmcs;
+
+	if (!igt_pm_read_pci_pm_reg(pci_dev, PCI_PM_PMCS_OFFSET, &pmcs))
+		return false;
+
+	return !!(pmcs & PCI_PM_PMCS_PME_STATUS);
+}
+
+/**
+ * igt_pm_pci_get_d_state:
+ * @pci_dev: PCI device struct
+ *
+ * Reads the PowerState field (bits [1:0]) of the PCI Power Management
+ * Control/Status (PMCS) register.
+ *
+ * PMCS can only express D0-D3hot, and it is no help in detecting D3cold either:
+ * a device in D3cold is resumed by the config space read itself and so reports
+ * D0. A runtime suspended device that reports D3hot here is genuinely in D3hot.
+ *
+ * Returns: the D state the device reports, or IGT_ACPI_UNKNOWN_STATE if the
+ * device has no PM capability or the read failed.
+ */
+enum igt_acpi_d_state igt_pm_pci_get_d_state(struct pci_device *pci_dev)
+{
+	static const enum igt_acpi_d_state d_states[] = {
+		IGT_ACPI_D0, IGT_ACPI_D1, IGT_ACPI_D2, IGT_ACPI_D3Hot,
+	};
+	uint16_t pmcs;
+
+	if (!igt_pm_read_pci_pm_reg(pci_dev, PCI_PM_PMCS_OFFSET, &pmcs))
+		return IGT_ACPI_UNKNOWN_STATE;
+
+	return d_states[pmcs & PCI_PM_PMCS_PSTATE_MASK];
+}
+
 /**
  * igt_pm_dpms_toggle:
  * @output: igt output for which DPMS toggle has to be performed
diff --git a/lib/igt_pm.h b/lib/igt_pm.h
index 328875f9c..ccb000998 100644
--- a/lib/igt_pm.h
+++ b/lib/igt_pm.h
@@ -105,6 +105,11 @@ uint64_t igt_pm_get_runtime_active_time(struct pci_device *pci_dev);
 int igt_pm_get_runtime_usage(struct pci_device *pci_dev);
 void igt_pm_ignore_slpc_efficient_freq(int i915, int gtfd, bool val);
 bool igt_has_pci_pm_capability(struct pci_device *pci_dev);
+bool igt_pm_pci_pme_supported(struct pci_device *pci_dev,
+			      enum igt_acpi_d_state state);
+bool igt_pm_pci_pme_enabled(struct pci_device *pci_dev);
+bool igt_pm_pci_pme_status(struct pci_device *pci_dev);
+enum igt_acpi_d_state igt_pm_pci_get_d_state(struct pci_device *pci_dev);
 void igt_pm_dpms_toggle(igt_output_t *output);
 uint32_t igt_get_dc_counter(const char *dc_data);
 bool igt_support_dc6(int debugfs_fd);
-- 
2.53.0

RE: [PATCH i-g-t v2 2/7] lib/igt_pm: Add PCI PME capability and D state accessors

[Joshi, Kunal1]

Hello Pranay,

> -----Original Message-----
> From: Samala, Pranay <pranay.samala@intel.com>
> Sent: Friday, October 9, 2026 10:56 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Joshi, Kunal1 <kunal1.joshi@intel.com>; Lattannavar, Sameer
> <sameer.lattannavar@intel.com>; Samala, Pranay
> <pranay.samala@intel.com>
> Subject: [PATCH i-g-t v2 2/7] lib/igt_pm: Add PCI PME capability and D state
> accessors
> 
> Add four helpers that read the PCI Power Management capability.
> 
> igt_pm_pci_pme_supported() says whether the device can send a PME from
> a given D state, by testing one bit of the PME_Support field.
> The state matters. Intel graphics devices support PME in D3hot but not in
> D3cold.
> 
> igt_pm_pci_pme_enabled() reads PME_En, which says whether the device is
> armed to send a PME. Its kerneldoc notes that a driver may arm PME from its
> own runtime suspend hook rather than leaving it to the PCI/PM core, and
> that xe does so subject to device_may_wakeup(), i.e. subject to
> power/wakeup.
> 
> igt_pm_pci_pme_status() reads PME_Status, which says whether the device
> has a PME pending. Because the bit is write-1-to-clear and nothing but
> software clears it, a test that expected a wakeup and did not get one can use
> this to tell a device that never signalled from one whose signal was never
> delivered.
> 
> igt_pm_pci_get_d_state() reads the PowerState field. Its kerneldoc points out
> that PMCS can only ever report D0-D3hot, and that it cannot be used to
> detect D3cold: config space here is reached through sysfs, where
> pci_config_pm_runtime_get() resumes a device in D3cold before the read, so
> such a device reports D0.
> 
> Assisted-by: GitHub_Copilot:claude-opus-5
> Signed-off-by: Pranay Samala <pranay.samala@intel.com>
> ---
>  lib/igt_pm.c | 162
> +++++++++++++++++++++++++++++++++++++++++++++++++++
>  lib/igt_pm.h |   5 ++
>  2 files changed, 167 insertions(+)
> 
> diff --git a/lib/igt_pm.c b/lib/igt_pm.c index 1e3cc7757..b1f9868eb 100644
> --- a/lib/igt_pm.c
> +++ b/lib/igt_pm.c
> @@ -1524,6 +1524,168 @@ bool igt_has_pci_pm_capability(struct
> pci_device *pci_dev)
>  	return (offset > 0);
>  }
> 
> +/*
> + * Read a 16 bit register of the PCI Power Management capability, at
> +@reg_offset
> + * from the start of the capability. Returns false if the device has no
> +PM
> + * capability, the config space read failed, or the device did not respond.
> + *
> + * Config space reads do not resume a device suspended into D3hot, so
> +these are
> + * safe to use while the device is runtime suspended. They are not a
> +way to
> + * observe D3cold though: the read goes through sysfs, where
> + * pci_config_pm_runtime_get() resumes a device in D3cold first, so
> +such a
> + * device answers as D0 rather than dropping off the bus.
> + */
> +static bool igt_pm_read_pci_pm_reg(struct pci_device *pci_dev, int
> reg_offset,
> +				   uint16_t *val)

So this helper itself wakes up a D3cold device, i.e. get_d_state()
changes the state it is reporting. Any D3cold test using it later will
break silently.

Can we read /sys/bus/pci/devices/<bdf>/power_state first? It only prints
pdev->current_state, no runtime pm side effect. If it is D3cold, return
without touching config space. Then get_d_state() can report D3cold
also, and the test doesn't need the "D3cold reads as D0" logic.


> +{
> +	int offset;
> +
> +	offset = find_pci_cap_offset(pci_dev, PCI_PM_CAP_ID);
> +	if (offset <= 0)
> +		return false;
> +
> +	if (pci_device_cfg_read_u16(pci_dev, val, offset + reg_offset))
> +		return false;
> +
> +	/*
> +	 * A device that has gone away reads back as all ones, which would
> +	 * otherwise decode as a valid register value: PMCS 0xffff means
> +	 * PowerState = D3hot with PME_En set. Reject it.
> +	 */
> +	return *val != 0xffff;
> +}
> +
> +/**
> + * igt_pm_pci_pme_supported:
> + * @pci_dev: PCI device struct
> + * @state: D state to query PME support for
> + *
> + * Reads the PME_Support field (bits [15:11]) of the PCI Power
> +Management
> + * Capabilities (PMC) register and reports whether the device is able
> +to
> + * generate a Power Management Event from @state.
> + *
> + * Note that PME support is per D state: Intel graphics devices
> +typically
> + * advertise PME support in D3hot but not in D3cold, so a state
> +agnostic check
> + * is not sufficient to decide whether PME based signalling can be used.
> + *

Please verify this once, Also we can leave out intel specific comments in common library.

> + * Returns: true if the device can generate a PME from @state, false
> otherwise.
> + */
> +bool igt_pm_pci_pme_supported(struct pci_device *pci_dev,
> +			      enum igt_acpi_d_state state)
> +{
> +	uint16_t pmc;
> +	int bit;
> +
> +	switch (state) {
> +	case IGT_ACPI_D0:
> +		bit = 0;
> +		break;
> +	case IGT_ACPI_D1:
> +		bit = 1;
> +		break;
> +	case IGT_ACPI_D2:
> +		bit = 2;
> +		break;
> +	case IGT_ACPI_D3Hot:
> +		bit = 3;
> +		break;
> +	case IGT_ACPI_D3Cold:
> +		bit = 4;
> +		break;
> +	default:
> +		igt_debug("Invalid D state %d for PME support query\n",
> state);
> +		return false;
> +	}
> +
> +	if (!igt_pm_read_pci_pm_reg(pci_dev, PCI_PM_PMC_OFFSET, &pmc))
> +		return false;
> +
> +	igt_debug("PCI '%04x:%02x:%02x.%01x' PMC = 0x%04x,
> PME_Support = 0x%02x\n",
> +		  pci_dev->domain, pci_dev->bus, pci_dev->dev, pci_dev-
> >func, pmc,
> +		  (pmc & PCI_PM_PMC_PME_SUPPORT_MASK) >>
> +PCI_PM_PMC_PME_SUPPORT_SHIFT);
> +
> +	return !!(pmc & (1 << (PCI_PM_PMC_PME_SUPPORT_SHIFT + bit))); }
> +
> +/**
> + * igt_pm_pci_pme_enabled:
> + * @pci_dev: PCI device struct
> + *
> + * Reads PME_En (bit 8) of the PCI Power Management Control/Status
> +(PMCS)
> + * register, i.e. whether the device is armed to generate PMEs.
> + *
> + * The PCI/PM core sets this on suspend if the device can generate a
> +PME from the
> + * state it is suspending into, but a driver may also arm PME itself
> +from its
> + * runtime suspend hook, in which case the driver's own conditions
> +apply. xe does
> + * exactly that, and requires the device_may_wakeup() policy behind
> +power/wakeup,
> + * so on xe this bit follows power/wakeup even for a runtime suspend.
> +See
> + * igt_pm_set_wakeup_enabled().
> + *
> + * Returns: true if the device is armed to generate PMEs, false otherwise.
> + */

Lib doc should stay generic, please move xe details to the test.
Also verify this once.


> +bool igt_pm_pci_pme_enabled(struct pci_device *pci_dev) {
> +	uint16_t pmcs;
> +
> +	if (!igt_pm_read_pci_pm_reg(pci_dev, PCI_PM_PMCS_OFFSET,
> &pmcs))
> +		return false;
> +
> +	return !!(pmcs & PCI_PM_PMCS_PME_EN);
> +}

A read failure and a clear bit both return false here (same in
igt_pm_pci_pme_status). So the test prints "PME_Status is clear" even
when the read failed. Can we return -1 on failure, or at least
igt_debug() the failure?

Thanks and Regards
Kunal Joshi

> +
> +/**
> + * igt_pm_pci_pme_status:
> + * @pci_dev: PCI device struct
> + *
> + * Reads PME_Status (bit 15) of the PCI Power Management Control/Status
> +(PMCS)
> + * register, i.e. whether the device has a PME pending.
> + *
> + * The bit is write-1-to-clear and the device does not clear it itself.
> +It stays
> + * set from the moment the device signals a PME until software
> +acknowledges it,
> + * which for a runtime resume is pci_pme_wakeup() on the way back to
> +D0. So
> + * finding it still set on a device that is still suspended means the
> +device did
> + * signal but the platform never delivered the PME, whereas finding it
> +clear
> + * means the device never signalled at all.
> + *
> + * Returns: true if the device has a PME pending, false otherwise.
> + */
> +bool igt_pm_pci_pme_status(struct pci_device *pci_dev) {
> +	uint16_t pmcs;
> +
> +	if (!igt_pm_read_pci_pm_reg(pci_dev, PCI_PM_PMCS_OFFSET,
> &pmcs))
> +		return false;
> +
> +	return !!(pmcs & PCI_PM_PMCS_PME_STATUS); }
> +
> +/**
> + * igt_pm_pci_get_d_state:
> + * @pci_dev: PCI device struct
> + *
> + * Reads the PowerState field (bits [1:0]) of the PCI Power Management
> + * Control/Status (PMCS) register.
> + *
> + * PMCS can only express D0-D3hot, and it is no help in detecting D3cold
> either:
> + * a device in D3cold is resumed by the config space read itself and so
> +reports
> + * D0. A runtime suspended device that reports D3hot here is genuinely in
> D3hot.
> + *
> + * Returns: the D state the device reports, or IGT_ACPI_UNKNOWN_STATE
> +if the
> + * device has no PM capability or the read failed.
> + */
> +enum igt_acpi_d_state igt_pm_pci_get_d_state(struct pci_device
> +*pci_dev) {
> +	static const enum igt_acpi_d_state d_states[] = {
> +		IGT_ACPI_D0, IGT_ACPI_D1, IGT_ACPI_D2, IGT_ACPI_D3Hot,
> +	};
> +	uint16_t pmcs;
> +
> +	if (!igt_pm_read_pci_pm_reg(pci_dev, PCI_PM_PMCS_OFFSET,
> &pmcs))
> +		return IGT_ACPI_UNKNOWN_STATE;
> +
> +	return d_states[pmcs & PCI_PM_PMCS_PSTATE_MASK]; }
> +
>  /**
>   * igt_pm_dpms_toggle:
>   * @output: igt output for which DPMS toggle has to be performed diff --git
> a/lib/igt_pm.h b/lib/igt_pm.h index 328875f9c..ccb000998 100644
> --- a/lib/igt_pm.h
> +++ b/lib/igt_pm.h
> @@ -105,6 +105,11 @@ uint64_t igt_pm_get_runtime_active_time(struct
> pci_device *pci_dev);  int igt_pm_get_runtime_usage(struct pci_device
> *pci_dev);  void igt_pm_ignore_slpc_efficient_freq(int i915, int gtfd, bool
> val);  bool igt_has_pci_pm_capability(struct pci_device *pci_dev);
> +bool igt_pm_pci_pme_supported(struct pci_device *pci_dev,
> +			      enum igt_acpi_d_state state);
> +bool igt_pm_pci_pme_enabled(struct pci_device *pci_dev); bool
> +igt_pm_pci_pme_status(struct pci_device *pci_dev); enum
> +igt_acpi_d_state igt_pm_pci_get_d_state(struct pci_device *pci_dev);
>  void igt_pm_dpms_toggle(igt_output_t *output);  uint32_t
> igt_get_dc_counter(const char *dc_data);  bool igt_support_dc6(int
> debugfs_fd);
> --
> 2.53.0

[PATCH i-g-t v2 3/7] lib/igt_pm: Factor out power attribute path construction

[Pranay Samala]

igt_pm_get_power_attr_fd() and igt_pm_get_power_attr_fd_rdonly() build the
same sysfs path with the same snprintf(). The only difference is the open()
flags.

Move the shared part into __igt_pm_get_power_attr_fd(), which takes the
flags and returns -1 instead of asserting.

Nothing changes for existing callers. Both wrappers still assert, so they
behave exactly as before.

The point of the change is the -1. Not every power attribute exists on
every device, so later callers need to ask whether one is present and get
an answer back rather than failing the test. Without this they would each
have to repeat the snprintf().

Assisted-by: GitHub_Copilot:claude-opus-5
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
---
 lib/igt_pm.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index b1f9868eb..7ad56fbce 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -1033,15 +1033,26 @@ static void __igt_pm_pci_card_exit_handler(int sig)
 	igt_pm_restore_pci_card_runtime_pm();
 }
 
-static int igt_pm_get_power_attr_fd(struct pci_device *pci_dev, const char *attr)
+/*
+ * Open a power attribute of @pci_dev with @flags, returning -1 if it does not
+ * exist. Not all attributes are present on all devices, so callers that want to
+ * probe for one need an error rather than an assertion.
+ */
+static int __igt_pm_get_power_attr_fd(struct pci_device *pci_dev,
+				      const char *attr, int flags)
 {
 	char name[PATH_MAX];
-	int fd;
 
 	snprintf(name, PATH_MAX, "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/power/%s",
 		 pci_dev->domain, pci_dev->bus, pci_dev->dev, pci_dev->func, attr);
 
-	fd = open(name, O_RDWR);
+	return open(name, flags);
+}
+
+static int igt_pm_get_power_attr_fd(struct pci_device *pci_dev, const char *attr)
+{
+	int fd = __igt_pm_get_power_attr_fd(pci_dev, attr, O_RDWR);
+
 	igt_assert_f(fd >= 0, "Can't open %s\n", attr);
 
 	return fd;
@@ -1049,13 +1060,8 @@ static int igt_pm_get_power_attr_fd(struct pci_device *pci_dev, const char *attr
 
 static int igt_pm_get_power_attr_fd_rdonly(struct pci_device *pci_dev, const char *attr)
 {
-	char name[PATH_MAX];
-	int fd;
+	int fd = __igt_pm_get_power_attr_fd(pci_dev, attr, O_RDONLY);
 
-	snprintf(name, PATH_MAX, "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/power/%s",
-		 pci_dev->domain, pci_dev->bus, pci_dev->dev, pci_dev->func, attr);
-
-	fd = open(name, O_RDONLY);
 	igt_assert_f(fd >= 0, "Can't open %s\n", attr);
 
 	return fd;
-- 
2.53.0

RE: [PATCH i-g-t v2 3/7] lib/igt_pm: Factor out power attribute path construction

[Joshi, Kunal1]

> -----Original Message-----
> From: Samala, Pranay <pranay.samala@intel.com>
> Sent: Friday, October 9, 2026 10:56 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Joshi, Kunal1 <kunal1.joshi@intel.com>; Lattannavar, Sameer
> <sameer.lattannavar@intel.com>; Samala, Pranay
> <pranay.samala@intel.com>
> Subject: [PATCH i-g-t v2 3/7] lib/igt_pm: Factor out power attribute path
> construction
> 
> igt_pm_get_power_attr_fd() and igt_pm_get_power_attr_fd_rdonly() build
> the same sysfs path with the same snprintf(). The only difference is the
> open() flags.
> 
> Move the shared part into __igt_pm_get_power_attr_fd(), which takes the
> flags and returns -1 instead of asserting.
> 
> Nothing changes for existing callers. Both wrappers still assert, so they
> behave exactly as before.
> 
> The point of the change is the -1. Not every power attribute exists on every
> device, so later callers need to ask whether one is present and get an answer
> back rather than failing the test. Without this they would each have to repeat
> the snprintf().
> 
> Assisted-by: GitHub_Copilot:claude-opus-5
> Signed-off-by: Pranay Samala <pranay.samala@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>

[PATCH i-g-t v2 4/7] lib/igt_pm: Add power/wakeup accessors

[Pranay Samala]

Add PCI power/wakeup accessors for igt_pm:

igt_pm_has_wakeup_support()
igt_pm_set_wakeup_enabled()
igt_pm_restore_wakeup()

These helpers expose whether the device supports wakeup accounting and allow
tests to enable/restore the power/wakeup sysfs attribute. This is needed for
PME-based HPD tests, where both device wakeup support and the PM wakeup source
must be enabled.

Assisted-by: GitHub_Copilot:claude-opus-5
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
---
 lib/igt_pm.c | 133 +++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_pm.h |   3 ++
 2 files changed, 136 insertions(+)

diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 7ad56fbce..b8b66e120 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -1498,6 +1498,139 @@ int igt_pm_get_runtime_usage(struct pci_device *pci_dev)
 	return usage;
 }
 
+#define IGT_PM_WAKEUP_ENABLED_STR "enabled\n"
+#define IGT_PM_WAKEUP_DISABLED_STR "disabled\n"
+
+static struct {
+	struct pci_device *pci_dev;
+	bool orig_enabled;
+} __igt_pm_wakeup;
+
+static void __igt_pm_wakeup_exit_handler(int sig)
+{
+	igt_pm_restore_wakeup();
+}
+
+/**
+ * igt_pm_has_wakeup_support:
+ * @pci_dev: PCI device struct
+ *
+ * The power/wakeup* sysfs attributes only exist for devices the PM core
+ * considers wakeup capable, so their presence is the check for whether wakeup
+ * source accounting is available at all for @pci_dev.
+ *
+ * Returns: true if the device exposes power/wakeup, false otherwise.
+ */
+bool igt_pm_has_wakeup_support(struct pci_device *pci_dev)
+{
+	int fd = __igt_pm_get_power_attr_fd(pci_dev, "wakeup", O_RDONLY);
+
+	if (fd < 0)
+		return false;
+
+	close(fd);
+
+	return true;
+}
+
+/*
+ * Read power/wakeup, i.e. whether the device is permitted to wake the system.
+ * Returns false if wakeup is disabled or the device is not wakeup capable.
+ *
+ * This gates two separate things. It is the device_may_wakeup() policy, which
+ * the system suspend path requires before arming PME, and which a driver may
+ * also consult from its own runtime suspend hook - xe does, so on xe this
+ * decides whether PME is armed for a runtime suspend at all, see
+ * igt_pm_pci_pme_enabled().
+ *
+ * It also gates the device's wakeup source object: writing "disabled" makes the
+ * PM core drop dev->power.wakeup, after which wakeup events are not accounted
+ * at all and the power/wakeup_* counters read back as a bare newline. Tests
+ * that sample those counters therefore need wakeup enabled, whether or not they
+ * care about system wakeup.
+ */
+static bool igt_pm_get_wakeup_enabled(struct pci_device *pci_dev)
+{
+	char buf[64];
+	int fd;
+	bool enabled;
+
+	fd = __igt_pm_get_power_attr_fd(pci_dev, "wakeup", O_RDONLY);
+	if (fd < 0)
+		return false;
+
+	enabled = igt_pm_read_power_attr(fd, buf, sizeof(buf), false) &&
+		  !strcmp(buf, "enabled");
+
+	close(fd);
+
+	return enabled;
+}
+
+/**
+ * igt_pm_set_wakeup_enabled:
+ * @pci_dev: PCI device struct
+ * @enable: whether to allow the device to wake the system
+ *
+ * Writes power/wakeup. The original value is saved on the first call and
+ * restored by an exit handler, or explicitly via igt_pm_restore_wakeup().
+ *
+ * Callers must gate on igt_pm_has_wakeup_support() first.
+ */
+void igt_pm_set_wakeup_enabled(struct pci_device *pci_dev, bool enable)
+{
+	const char *val = enable ? IGT_PM_WAKEUP_ENABLED_STR :
+				   IGT_PM_WAKEUP_DISABLED_STR;
+	int len = strlen(val);
+	int fd, size;
+
+	fd = __igt_pm_get_power_attr_fd(pci_dev, "wakeup", O_RDWR);
+	igt_assert_f(fd >= 0, "Device has no power/wakeup attribute\n");
+
+	if (!__igt_pm_wakeup.pci_dev) {
+		__igt_pm_wakeup.orig_enabled = igt_pm_get_wakeup_enabled(pci_dev);
+		__igt_pm_wakeup.pci_dev = pci_dev;
+		igt_install_exit_handler(__igt_pm_wakeup_exit_handler);
+	}
+
+	size = write(fd, val, len);
+	close(fd);
+
+	igt_assert_f(size == len, "Failed to %s power/wakeup\n",
+		     enable ? "enable" : "disable");
+
+	igt_debug("PCI '%04x:%02x:%02x.%01x' power/wakeup = %s\n",
+		  pci_dev->domain, pci_dev->bus, pci_dev->dev, pci_dev->func,
+		  enable ? "enabled" : "disabled");
+}
+
+/**
+ * igt_pm_restore_wakeup:
+ *
+ * Restores power/wakeup to the value it had before the first
+ * igt_pm_set_wakeup_enabled() call. Does nothing if it was never changed.
+ */
+void igt_pm_restore_wakeup(void)
+{
+	struct pci_device *pci_dev = __igt_pm_wakeup.pci_dev;
+	const char *val;
+	int fd;
+
+	if (!pci_dev)
+		return;
+
+	val = __igt_pm_wakeup.orig_enabled ? IGT_PM_WAKEUP_ENABLED_STR :
+					     IGT_PM_WAKEUP_DISABLED_STR;
+
+	fd = __igt_pm_get_power_attr_fd(pci_dev, "wakeup", O_RDWR);
+	if (fd >= 0) {
+		igt_ignore_warn(write(fd, val, strlen(val)));
+		close(fd);
+	}
+
+	__igt_pm_wakeup.pci_dev = NULL;
+}
+
 /**
  * igt_pm_ignore_slpc_efficient_freq:
  * @i915: open i915 drm file descriptor
diff --git a/lib/igt_pm.h b/lib/igt_pm.h
index ccb000998..d15b01ec9 100644
--- a/lib/igt_pm.h
+++ b/lib/igt_pm.h
@@ -103,6 +103,9 @@ bool i915_is_slpc_enabled(int drm_fd);
 uint64_t igt_pm_get_runtime_suspended_time(struct pci_device *pci_dev);
 uint64_t igt_pm_get_runtime_active_time(struct pci_device *pci_dev);
 int igt_pm_get_runtime_usage(struct pci_device *pci_dev);
+bool igt_pm_has_wakeup_support(struct pci_device *pci_dev);
+void igt_pm_set_wakeup_enabled(struct pci_device *pci_dev, bool enable);
+void igt_pm_restore_wakeup(void);
 void igt_pm_ignore_slpc_efficient_freq(int i915, int gtfd, bool val);
 bool igt_has_pci_pm_capability(struct pci_device *pci_dev);
 bool igt_pm_pci_pme_supported(struct pci_device *pci_dev,
-- 
2.53.0

RE: [PATCH i-g-t v2 4/7] lib/igt_pm: Add power/wakeup accessors

[Joshi, Kunal1]

Hello Pranay,

> -----Original Message-----
> From: Samala, Pranay <pranay.samala@intel.com>
> Sent: Friday, October 9, 2026 10:56 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Joshi, Kunal1 <kunal1.joshi@intel.com>; Lattannavar, Sameer
> <sameer.lattannavar@intel.com>; Samala, Pranay
> <pranay.samala@intel.com>
> Subject: [PATCH i-g-t v2 4/7] lib/igt_pm: Add power/wakeup accessors
> 
> Add PCI power/wakeup accessors for igt_pm:
> 
> igt_pm_has_wakeup_support()
> igt_pm_set_wakeup_enabled()
> igt_pm_restore_wakeup()
> 
> These helpers expose whether the device supports wakeup accounting and
> allow tests to enable/restore the power/wakeup sysfs attribute. This is
> needed for PME-based HPD tests, where both device wakeup support and
> the PM wakeup source must be enabled.
> 
> Assisted-by: GitHub_Copilot:claude-opus-5
> Signed-off-by: Pranay Samala <pranay.samala@intel.com>
> ---
>  lib/igt_pm.c | 133
> +++++++++++++++++++++++++++++++++++++++++++++++++++
>  lib/igt_pm.h |   3 ++
>  2 files changed, 136 insertions(+)
> 
> diff --git a/lib/igt_pm.c b/lib/igt_pm.c index 7ad56fbce..b8b66e120 100644
> --- a/lib/igt_pm.c
> +++ b/lib/igt_pm.c
> @@ -1498,6 +1498,139 @@ int igt_pm_get_runtime_usage(struct pci_device
> *pci_dev)
>  	return usage;
>  }
> 
> +#define IGT_PM_WAKEUP_ENABLED_STR "enabled\n"
> +#define IGT_PM_WAKEUP_DISABLED_STR "disabled\n"
> +
> +static struct {
> +	struct pci_device *pci_dev;
> +	bool orig_enabled;
> +} __igt_pm_wakeup;
> +
> +static void __igt_pm_wakeup_exit_handler(int sig) {
> +	igt_pm_restore_wakeup();
> +}
> +
> +/**
> + * igt_pm_has_wakeup_support:
> + * @pci_dev: PCI device struct
> + *
> + * The power/wakeup* sysfs attributes only exist for devices the PM
> +core
> + * considers wakeup capable, so their presence is the check for whether
> +wakeup
> + * source accounting is available at all for @pci_dev.
> + *
> + * Returns: true if the device exposes power/wakeup, false otherwise.
> + */
> +bool igt_pm_has_wakeup_support(struct pci_device *pci_dev) {
> +	int fd = __igt_pm_get_power_attr_fd(pci_dev, "wakeup", O_RDONLY);
> +
> +	if (fd < 0)
> +		return false;
> +
> +	close(fd);
> +
> +	return true;
> +}
> +
> +/*
> + * Read power/wakeup, i.e. whether the device is permitted to wake the
> system.
> + * Returns false if wakeup is disabled or the device is not wakeup capable.
> + *
> + * This gates two separate things. It is the device_may_wakeup()
> +policy, which
> + * the system suspend path requires before arming PME, and which a
> +driver may
> + * also consult from its own runtime suspend hook - xe does, so on xe
> +this
> + * decides whether PME is armed for a runtime suspend at all, see
> + * igt_pm_pci_pme_enabled().
> + *
> + * It also gates the device's wakeup source object: writing "disabled"
> +makes the
> + * PM core drop dev->power.wakeup, after which wakeup events are not
> +accounted
> + * at all and the power/wakeup_* counters read back as a bare newline.
> +Tests

Same comments as on patch 3 for xe part.

Also please mention that writing "enabled" again creates a new wakeup
source, so all counters restart from 0. Callers need to take a fresh
baseline after any toggle.

Thanks and Regards
Kunal Joshi


> + * that sample those counters therefore need wakeup enabled, whether or
> +not they
> + * care about system wakeup.
> + */
> +static bool igt_pm_get_wakeup_enabled(struct pci_device *pci_dev) {
> +	char buf[64];
> +	int fd;
> +	bool enabled;
> +
> +	fd = __igt_pm_get_power_attr_fd(pci_dev, "wakeup", O_RDONLY);
> +	if (fd < 0)
> +		return false;
> +
> +	enabled = igt_pm_read_power_attr(fd, buf, sizeof(buf), false) &&
> +		  !strcmp(buf, "enabled");
> +
> +	close(fd);
> +
> +	return enabled;
> +}
> +
> +/**
> + * igt_pm_set_wakeup_enabled:
> + * @pci_dev: PCI device struct
> + * @enable: whether to allow the device to wake the system
> + *
> + * Writes power/wakeup. The original value is saved on the first call
> +and
> + * restored by an exit handler, or explicitly via igt_pm_restore_wakeup().
> + *
> + * Callers must gate on igt_pm_has_wakeup_support() first.
> + */
> +void igt_pm_set_wakeup_enabled(struct pci_device *pci_dev, bool enable)
> +{
> +	const char *val = enable ? IGT_PM_WAKEUP_ENABLED_STR :
> +				   IGT_PM_WAKEUP_DISABLED_STR;
> +	int len = strlen(val);
> +	int fd, size;
> +
> +	fd = __igt_pm_get_power_attr_fd(pci_dev, "wakeup", O_RDWR);
> +	igt_assert_f(fd >= 0, "Device has no power/wakeup attribute\n");
> +
> +	if (!__igt_pm_wakeup.pci_dev) {
> +		__igt_pm_wakeup.orig_enabled =
> igt_pm_get_wakeup_enabled(pci_dev);
> +		__igt_pm_wakeup.pci_dev = pci_dev;
> +		igt_install_exit_handler(__igt_pm_wakeup_exit_handler);
> +	}
> +
> +	size = write(fd, val, len);
> +	close(fd);
> +
> +	igt_assert_f(size == len, "Failed to %s power/wakeup\n",
> +		     enable ? "enable" : "disable");
> +
> +	igt_debug("PCI '%04x:%02x:%02x.%01x' power/wakeup = %s\n",
> +		  pci_dev->domain, pci_dev->bus, pci_dev->dev, pci_dev-
> >func,
> +		  enable ? "enabled" : "disabled");
> +}
> +
> +/**
> + * igt_pm_restore_wakeup:
> + *
> + * Restores power/wakeup to the value it had before the first
> + * igt_pm_set_wakeup_enabled() call. Does nothing if it was never changed.
> + */
> +void igt_pm_restore_wakeup(void)
> +{
> +	struct pci_device *pci_dev = __igt_pm_wakeup.pci_dev;
> +	const char *val;
> +	int fd;
> +
> +	if (!pci_dev)
> +		return;
> +
> +	val = __igt_pm_wakeup.orig_enabled ?
> IGT_PM_WAKEUP_ENABLED_STR :
> +					     IGT_PM_WAKEUP_DISABLED_STR;
> +
> +	fd = __igt_pm_get_power_attr_fd(pci_dev, "wakeup", O_RDWR);
> +	if (fd >= 0) {
> +		igt_ignore_warn(write(fd, val, strlen(val)));
> +		close(fd);
> +	}
> +
> +	__igt_pm_wakeup.pci_dev = NULL;
> +}
> +
>  /**
>   * igt_pm_ignore_slpc_efficient_freq:
>   * @i915: open i915 drm file descriptor diff --git a/lib/igt_pm.h
> b/lib/igt_pm.h index ccb000998..d15b01ec9 100644
> --- a/lib/igt_pm.h
> +++ b/lib/igt_pm.h
> @@ -103,6 +103,9 @@ bool i915_is_slpc_enabled(int drm_fd);  uint64_t
> igt_pm_get_runtime_suspended_time(struct pci_device *pci_dev);  uint64_t
> igt_pm_get_runtime_active_time(struct pci_device *pci_dev);  int
> igt_pm_get_runtime_usage(struct pci_device *pci_dev);
> +bool igt_pm_has_wakeup_support(struct pci_device *pci_dev); void
> +igt_pm_set_wakeup_enabled(struct pci_device *pci_dev, bool enable);
> +void igt_pm_restore_wakeup(void);
>  void igt_pm_ignore_slpc_efficient_freq(int i915, int gtfd, bool val);  bool
> igt_has_pci_pm_capability(struct pci_device *pci_dev);  bool
> igt_pm_pci_pme_supported(struct pci_device *pci_dev,
> --
> 2.53.0

[PATCH i-g-t v2 5/7] lib/igt_pm: Add power/wakeup_active_count accessor

[Pranay Samala]

Add igt_pm_get_wakeup_active_count(), which reads how many times the
device's wakeup source has been activated.

wakeup_source_activate() bumps this unconditionally, so it counts runtime
resumes too, on both the PCIe (pci_pme_wakeup()) and ACPI GPE
(pci_acpi_wake_dev()) delivery routes. An increment across a suspended
window therefore means the device signalled the resume itself, i.e. a PME
arrived, rather than the host waking it.

Neither alternative works: power/wakeup_count only moves under
events_check_enabled, which the PM core sets for system suspend and
hibernate, and PME_Status is cleared by the PCI/PM core as it handles the
wakeup, so it cannot be sampled afterwards.

Parsing uses a checked sscanf() rather than an asserted one, since the
counter reads back as a bare newline when the device has no wakeup source,
that is when power/wakeup is disabled. That has to give 0, not a failure.

Assisted-by: GitHub_Copilot:claude-opus-5
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
---
 lib/igt_pm.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_pm.h |  1 +
 2 files changed, 49 insertions(+)

diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index b8b66e120..4ed80b27a 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -1498,6 +1498,34 @@ int igt_pm_get_runtime_usage(struct pci_device *pci_dev)
 	return usage;
 }
 
+/*
+ * Read an unsigned power attribute of @pci_dev, returning 0 if the attribute
+ * does not exist or does not hold a number.
+ *
+ * The latter is not hypothetical: the wakeup counters exist for every wakeup
+ * capable device, but the PM core emits a bare newline for them while the
+ * device has no wakeup source, i.e. while power/wakeup is disabled.
+ */
+static uint64_t igt_pm_read_power_attr_u64(struct pci_device *pci_dev,
+					   const char *attr)
+{
+	char buf[64];
+	uint64_t val;
+	int fd;
+
+	fd = __igt_pm_get_power_attr_fd(pci_dev, attr, O_RDONLY);
+	if (fd < 0)
+		return 0;
+
+	if (!igt_pm_read_power_attr(fd, buf, sizeof(buf), false) ||
+	    sscanf(buf, "%" SCNu64, &val) != 1)
+		val = 0;
+
+	close(fd);
+
+	return val;
+}
+
 #define IGT_PM_WAKEUP_ENABLED_STR "enabled\n"
 #define IGT_PM_WAKEUP_DISABLED_STR "disabled\n"
 
@@ -1631,6 +1659,26 @@ void igt_pm_restore_wakeup(void)
 	__igt_pm_wakeup.pci_dev = NULL;
 }
 
+/**
+ * igt_pm_get_wakeup_active_count:
+ * @pci_dev: PCI device struct
+ *
+ * Reads power/wakeup_active_count, the number of times the device's wakeup
+ * source was activated. An increment across a runtime suspended window means
+ * the resume was signalled by the device, i.e. a PME arrived, rather than
+ * initiated by something host side such as HPD polling.
+ *
+ * Use this and not power/wakeup_count, which is only incremented under
+ * events_check_enabled and so never moves for a runtime resume.
+ *
+ * Return: the wakeup active count, or 0 if the device is not wakeup capable or
+ * has power/wakeup disabled.
+ */
+uint64_t igt_pm_get_wakeup_active_count(struct pci_device *pci_dev)
+{
+	return igt_pm_read_power_attr_u64(pci_dev, "wakeup_active_count");
+}
+
 /**
  * igt_pm_ignore_slpc_efficient_freq:
  * @i915: open i915 drm file descriptor
diff --git a/lib/igt_pm.h b/lib/igt_pm.h
index d15b01ec9..1e9234154 100644
--- a/lib/igt_pm.h
+++ b/lib/igt_pm.h
@@ -106,6 +106,7 @@ int igt_pm_get_runtime_usage(struct pci_device *pci_dev);
 bool igt_pm_has_wakeup_support(struct pci_device *pci_dev);
 void igt_pm_set_wakeup_enabled(struct pci_device *pci_dev, bool enable);
 void igt_pm_restore_wakeup(void);
+uint64_t igt_pm_get_wakeup_active_count(struct pci_device *pci_dev);
 void igt_pm_ignore_slpc_efficient_freq(int i915, int gtfd, bool val);
 bool igt_has_pci_pm_capability(struct pci_device *pci_dev);
 bool igt_pm_pci_pme_supported(struct pci_device *pci_dev,
-- 
2.53.0

RE: [PATCH i-g-t v2 5/7] lib/igt_pm: Add power/wakeup_active_count accessor

[Joshi, Kunal1]

Hello Pranay,

> -----Original Message-----
> From: Samala, Pranay <pranay.samala@intel.com>
> Sent: Friday, October 9, 2026 10:56 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Joshi, Kunal1 <kunal1.joshi@intel.com>; Lattannavar, Sameer
> <sameer.lattannavar@intel.com>; Samala, Pranay
> <pranay.samala@intel.com>
> Subject: [PATCH i-g-t v2 5/7] lib/igt_pm: Add power/wakeup_active_count
> accessor
> 
> Add igt_pm_get_wakeup_active_count(), which reads how many times the
> device's wakeup source has been activated.
> 
> wakeup_source_activate() bumps this unconditionally, so it counts runtime
> resumes too, on both the PCIe (pci_pme_wakeup()) and ACPI GPE
> (pci_acpi_wake_dev()) delivery routes. An increment across a suspended


There is one more route: the PCI core PME poll (pci_pme_list_scan() ->
pci_pme_wakeup(), every 1s).
pci_pm_init() sets pme_poll for every PME capable function, and for an integrated GPU (RCiEP) without a GPE route, this is the most likely path. Please mention it.


> window therefore means the device signalled the resume itself, i.e. a PME
> arrived, rather than the host waking it.
> 
> Neither alternative works: power/wakeup_count only moves under
> events_check_enabled, which the PM core sets for system suspend and
> hibernate, and PME_Status is cleared by the PCI/PM core as it handles the
> wakeup, so it cannot be sampled afterwards.
> 
> Parsing uses a checked sscanf() rather than an asserted one, since the
> counter reads back as a bare newline when the device has no wakeup source,
> that is when power/wakeup is disabled. That has to give 0, not a failure.
> 
> Assisted-by: GitHub_Copilot:claude-opus-5
> Signed-off-by: Pranay Samala <pranay.samala@intel.com>
> ---
>  lib/igt_pm.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
>  lib/igt_pm.h |  1 +
>  2 files changed, 49 insertions(+)
> 
> diff --git a/lib/igt_pm.c b/lib/igt_pm.c index b8b66e120..4ed80b27a 100644
> --- a/lib/igt_pm.c
> +++ b/lib/igt_pm.c
> @@ -1498,6 +1498,34 @@ int igt_pm_get_runtime_usage(struct pci_device
> *pci_dev)
>  	return usage;
>  }
> 
> +/*
> + * Read an unsigned power attribute of @pci_dev, returning 0 if the
> +attribute
> + * does not exist or does not hold a number.
> + *
> + * The latter is not hypothetical: the wakeup counters exist for every
> +wakeup
> + * capable device, but the PM core emits a bare newline for them while
> +the
> + * device has no wakeup source, i.e. while power/wakeup is disabled.
> + */
> +static uint64_t igt_pm_read_power_attr_u64(struct pci_device *pci_dev,
> +					   const char *attr)
> +{
> +	char buf[64];
> +	uint64_t val;
> +	int fd;
> +
> +	fd = __igt_pm_get_power_attr_fd(pci_dev, attr, O_RDONLY);
> +	if (fd < 0)
> +		return 0;
> +
> +	if (!igt_pm_read_power_attr(fd, buf, sizeof(buf), false) ||
> +	    sscanf(buf, "%" SCNu64, &val) != 1)
> +		val = 0;
> +
> +	close(fd);
> +
> +	return val;
> +}
> +
>  #define IGT_PM_WAKEUP_ENABLED_STR "enabled\n"
>  #define IGT_PM_WAKEUP_DISABLED_STR "disabled\n"
> 
> @@ -1631,6 +1659,26 @@ void igt_pm_restore_wakeup(void)
>  	__igt_pm_wakeup.pci_dev = NULL;
>  }
> 
> +/**
> + * igt_pm_get_wakeup_active_count:
> + * @pci_dev: PCI device struct
> + *
> + * Reads power/wakeup_active_count, the number of times the device's
> +wakeup
> + * source was activated. An increment across a runtime suspended window
> +means
> + * the resume was signalled by the device, i.e. a PME arrived, rather
> +than
> + * initiated by something host side such as HPD polling.
> + *
> + * Use this and not power/wakeup_count, which is only incremented under
> + * events_check_enabled and so never moves for a runtime resume.
> + *
> + * Return: the wakeup active count, or 0 if the device is not wakeup
> +capable or
> + * has power/wakeup disabled.
> + */

0 is a valid count also. If power/wakeup gets disabled in between, the
test will report "resume was not triggered by a PME", which is
misleading. Better to return int64_t with -1 when there is no wakeup
source, and let the caller assert on it.

Thanks and Regards
Kunal Joshi

> +uint64_t igt_pm_get_wakeup_active_count(struct pci_device *pci_dev) {
> +	return igt_pm_read_power_attr_u64(pci_dev,
> "wakeup_active_count"); }
> +
>  /**
>   * igt_pm_ignore_slpc_efficient_freq:
>   * @i915: open i915 drm file descriptor diff --git a/lib/igt_pm.h
> b/lib/igt_pm.h index d15b01ec9..1e9234154 100644
> --- a/lib/igt_pm.h
> +++ b/lib/igt_pm.h
> @@ -106,6 +106,7 @@ int igt_pm_get_runtime_usage(struct pci_device
> *pci_dev);  bool igt_pm_has_wakeup_support(struct pci_device *pci_dev);
> void igt_pm_set_wakeup_enabled(struct pci_device *pci_dev, bool enable);
> void igt_pm_restore_wakeup(void);
> +uint64_t igt_pm_get_wakeup_active_count(struct pci_device *pci_dev);
>  void igt_pm_ignore_slpc_efficient_freq(int i915, int gtfd, bool val);  bool
> igt_has_pci_pm_capability(struct pci_device *pci_dev);  bool
> igt_pm_pci_pme_supported(struct pci_device *pci_dev,
> --
> 2.53.0

[PATCH i-g-t v2 6/7] lib/igt_pm: Add drm_kms_helper.poll save/restore helpers

[Pranay Samala]

The new PME hotplug subtest needs to save the drm_kms_helper.poll module
parameter and put it back on exit, so that an earlier test cannot leave
polling disabled and make the measurement pass for the wrong reason.

tests/intel/kms_pm_dc.c and tests/kms_prime.c already open code exactly
that, each with its own copy of the KMS_HELPER and KMS_POLL_DISABLE
defines and its own file scope kms_poll_saved_state global. Rather than
add a third copy, add igt_pm_kms_poll_save(), _set() and _restore().
Converting those two existing callers is left to a separate patch.

Save and set stay separate rather than becoming one "save and disable"
helper, because a caller may want to record the original value and put it
back on exit while leaving polling switched on.

igt_pm_kms_poll_save() installs the exit handler itself, and
igt_pm_kms_poll_restore() does nothing unless a save actually happened, so
a restore can never run without a matching save.

Assisted-by: GitHub_Copilot:claude-opus-5
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
---
 lib/igt_pm.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_pm.h |  3 ++
 2 files changed, 93 insertions(+)

diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 4ed80b27a..5c4c86036 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -1679,6 +1679,96 @@ uint64_t igt_pm_get_wakeup_active_count(struct pci_device *pci_dev)
 	return igt_pm_read_power_attr_u64(pci_dev, "wakeup_active_count");
 }
 
+#define IGT_KMS_HELPER_PARAMS "/sys/module/drm_kms_helper/parameters"
+
+static struct {
+	bool saved;
+	bool orig_poll;
+} __igt_pm_kms_poll;
+
+static void __igt_pm_kms_poll_exit_handler(int sig)
+{
+	igt_pm_kms_poll_restore();
+}
+
+/**
+ * igt_pm_kms_poll_save:
+ *
+ * Saves the current drm_kms_helper.poll value and installs an exit handler to
+ * restore it. Safe to call more than once, only the first value is kept.
+ *
+ * Returns: false if the module parameter is not available, in which case
+ * nothing was saved.
+ */
+bool igt_pm_kms_poll_save(void)
+{
+	int dir;
+
+	if (__igt_pm_kms_poll.saved)
+		return true;
+
+	dir = open(IGT_KMS_HELPER_PARAMS, O_RDONLY);
+	if (dir < 0)
+		return false;
+
+	if (!__igt_sysfs_get_boolean(dir, "poll", &__igt_pm_kms_poll.orig_poll)) {
+		close(dir);
+		return false;
+	}
+	close(dir);
+
+	__igt_pm_kms_poll.saved = true;
+	igt_install_exit_handler(__igt_pm_kms_poll_exit_handler);
+
+	igt_debug("Saved drm_kms_helper.poll = %s\n",
+		  __igt_pm_kms_poll.orig_poll ? "Y" : "N");
+
+	return true;
+}
+
+/**
+ * igt_pm_kms_poll_set:
+ * @enable: whether to enable connector polling
+ *
+ * Writes the drm_kms_helper.poll module parameter. Callers are expected to have
+ * called igt_pm_kms_poll_save() first so the original value is restored on exit.
+ */
+void igt_pm_kms_poll_set(bool enable)
+{
+	int dir;
+
+	dir = open(IGT_KMS_HELPER_PARAMS, O_RDONLY);
+	igt_assert_f(dir >= 0, "Can't open %s\n", IGT_KMS_HELPER_PARAMS);
+
+	igt_sysfs_set_boolean(dir, "poll", enable);
+	close(dir);
+
+	igt_debug("drm_kms_helper.poll = %s\n", enable ? "Y" : "N");
+}
+
+/**
+ * igt_pm_kms_poll_restore:
+ *
+ * Restores drm_kms_helper.poll to the value saved by
+ * igt_pm_kms_poll_save(). Does nothing if it was never saved, so it is safe to
+ * use as an exit handler that may run before any save happened.
+ */
+void igt_pm_kms_poll_restore(void)
+{
+	int dir;
+
+	if (!__igt_pm_kms_poll.saved)
+		return;
+
+	dir = open(IGT_KMS_HELPER_PARAMS, O_RDONLY);
+	if (dir >= 0) {
+		__igt_sysfs_set_boolean(dir, "poll", __igt_pm_kms_poll.orig_poll);
+		close(dir);
+	}
+
+	__igt_pm_kms_poll.saved = false;
+}
+
 /**
  * igt_pm_ignore_slpc_efficient_freq:
  * @i915: open i915 drm file descriptor
diff --git a/lib/igt_pm.h b/lib/igt_pm.h
index 1e9234154..5d91c4d5a 100644
--- a/lib/igt_pm.h
+++ b/lib/igt_pm.h
@@ -107,6 +107,9 @@ bool igt_pm_has_wakeup_support(struct pci_device *pci_dev);
 void igt_pm_set_wakeup_enabled(struct pci_device *pci_dev, bool enable);
 void igt_pm_restore_wakeup(void);
 uint64_t igt_pm_get_wakeup_active_count(struct pci_device *pci_dev);
+bool igt_pm_kms_poll_save(void);
+void igt_pm_kms_poll_set(bool enable);
+void igt_pm_kms_poll_restore(void);
 void igt_pm_ignore_slpc_efficient_freq(int i915, int gtfd, bool val);
 bool igt_has_pci_pm_capability(struct pci_device *pci_dev);
 bool igt_pm_pci_pme_supported(struct pci_device *pci_dev,
-- 
2.53.0

RE: [PATCH i-g-t v2 6/7] lib/igt_pm: Add drm_kms_helper.poll save/restore helpers

[Joshi, Kunal1]

Hello Pranay,

> -----Original Message-----
> From: Samala, Pranay <pranay.samala@intel.com>
> Sent: Friday, October 9, 2026 10:56 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Joshi, Kunal1 <kunal1.joshi@intel.com>; Lattannavar, Sameer
> <sameer.lattannavar@intel.com>; Samala, Pranay
> <pranay.samala@intel.com>
> Subject: [PATCH i-g-t v2 6/7] lib/igt_pm: Add drm_kms_helper.poll
> save/restore helpers
> 
> The new PME hotplug subtest needs to save the drm_kms_helper.poll
> module parameter and put it back on exit, so that an earlier test cannot leave
> polling disabled and make the measurement pass for the wrong reason.
> 
> tests/intel/kms_pm_dc.c and tests/kms_prime.c already open code exactly
> that, each with its own copy of the KMS_HELPER and KMS_POLL_DISABLE
> defines and its own file scope kms_poll_saved_state global. Rather than add
> a third copy, add igt_pm_kms_poll_save(), _set() and _restore().
> Converting those two existing callers is left to a separate patch.
> 
> Save and set stay separate rather than becoming one "save and disable"
> helper, because a caller may want to record the original value and put it back
> on exit while leaving polling switched on.
> 
> igt_pm_kms_poll_save() installs the exit handler itself, and
> igt_pm_kms_poll_restore() does nothing unless a save actually happened, so
> a restore can never run without a matching save.
> 
> Assisted-by: GitHub_Copilot:claude-opus-5
> Signed-off-by: Pranay Samala <pranay.samala@intel.com>
> ---
>  lib/igt_pm.c | 90
> ++++++++++++++++++++++++++++++++++++++++++++++++++++
>  lib/igt_pm.h |  3 ++
>  2 files changed, 93 insertions(+)
> 
> diff --git a/lib/igt_pm.c b/lib/igt_pm.c index 4ed80b27a..5c4c86036 100644
> --- a/lib/igt_pm.c
> +++ b/lib/igt_pm.c
> @@ -1679,6 +1679,96 @@ uint64_t igt_pm_get_wakeup_active_count(struct
> pci_device *pci_dev)
>  	return igt_pm_read_power_attr_u64(pci_dev,
> "wakeup_active_count");  }
> 
> +#define IGT_KMS_HELPER_PARAMS
> "/sys/module/drm_kms_helper/parameters"
> +
> +static struct {
> +	bool saved;
> +	bool orig_poll;
> +} __igt_pm_kms_poll;
> +
> +static void __igt_pm_kms_poll_exit_handler(int sig) {
> +	igt_pm_kms_poll_restore();
> +}
> +
> +/**
> + * igt_pm_kms_poll_save:
> + *
> + * Saves the current drm_kms_helper.poll value and installs an exit
> +handler to
> + * restore it. Safe to call more than once, only the first value is kept.
> + *
> + * Returns: false if the module parameter is not available, in which
> +case
> + * nothing was saved.
> + */
> +bool igt_pm_kms_poll_save(void)
> +{
> +	int dir;
> +
> +	if (__igt_pm_kms_poll.saved)
> +		return true;
> +
> +	dir = open(IGT_KMS_HELPER_PARAMS, O_RDONLY);
> +	if (dir < 0)
> +		return false;
> +
> +	if (!__igt_sysfs_get_boolean(dir, "poll",
> &__igt_pm_kms_poll.orig_poll)) {
> +		close(dir);
> +		return false;
> +	}
> +	close(dir);
> +
> +	__igt_pm_kms_poll.saved = true;
> +	igt_install_exit_handler(__igt_pm_kms_poll_exit_handler);
> +
> +	igt_debug("Saved drm_kms_helper.poll = %s\n",
> +		  __igt_pm_kms_poll.orig_poll ? "Y" : "N");
> +
> +	return true;
> +}
> +
> +/**
> + * igt_pm_kms_poll_set:
> + * @enable: whether to enable connector polling

Please check if this alone enable's connector polling
Else document so callers can handle accordingly,


Also all the 3 functions seems to be well suited for igt_kms

Thanks and Regards
Kunal Joshi

> + *
> + * Writes the drm_kms_helper.poll module parameter. Callers are
> +expected to have
> + * called igt_pm_kms_poll_save() first so the original value is restored on
> exit.
> + */
> +void igt_pm_kms_poll_set(bool enable)
> +{
> +	int dir;
> +
> +	dir = open(IGT_KMS_HELPER_PARAMS, O_RDONLY);
> +	igt_assert_f(dir >= 0, "Can't open %s\n", IGT_KMS_HELPER_PARAMS);
> +
> +	igt_sysfs_set_boolean(dir, "poll", enable);
> +	close(dir);
> +
> +	igt_debug("drm_kms_helper.poll = %s\n", enable ? "Y" : "N"); }
> +
> +/**
> + * igt_pm_kms_poll_restore:
> + *
> + * Restores drm_kms_helper.poll to the value saved by
> + * igt_pm_kms_poll_save(). Does nothing if it was never saved, so it is
> +safe to
> + * use as an exit handler that may run before any save happened.
> + */
> +void igt_pm_kms_poll_restore(void)
> +{
> +	int dir;
> +
> +	if (!__igt_pm_kms_poll.saved)
> +		return;
> +
> +	dir = open(IGT_KMS_HELPER_PARAMS, O_RDONLY);
> +	if (dir >= 0) {
> +		__igt_sysfs_set_boolean(dir, "poll",
> __igt_pm_kms_poll.orig_poll);
> +		close(dir);
> +	}
> +
> +	__igt_pm_kms_poll.saved = false;
> +}
> +
>  /**
>   * igt_pm_ignore_slpc_efficient_freq:
>   * @i915: open i915 drm file descriptor diff --git a/lib/igt_pm.h
> b/lib/igt_pm.h index 1e9234154..5d91c4d5a 100644
> --- a/lib/igt_pm.h
> +++ b/lib/igt_pm.h
> @@ -107,6 +107,9 @@ bool igt_pm_has_wakeup_support(struct pci_device
> *pci_dev);  void igt_pm_set_wakeup_enabled(struct pci_device *pci_dev,
> bool enable);  void igt_pm_restore_wakeup(void);  uint64_t
> igt_pm_get_wakeup_active_count(struct pci_device *pci_dev);
> +bool igt_pm_kms_poll_save(void);
> +void igt_pm_kms_poll_set(bool enable);
> +void igt_pm_kms_poll_restore(void);
>  void igt_pm_ignore_slpc_efficient_freq(int i915, int gtfd, bool val);  bool
> igt_has_pci_pm_capability(struct pci_device *pci_dev);  bool
> igt_pm_pci_pme_supported(struct pci_device *pci_dev,
> --
> 2.53.0

[PATCH i-g-t v2 7/7] tests/chamelium/kms_chamelium_hpd: Add HPD from runtime suspended D3hot

[Pranay Samala]

Add dp-hpd-after-runtime-suspend-d3hot and
hdmi-hpd-after-runtime-suspend-d3hot, covering a hotplug signalled by a
PME while the device is runtime suspended in D3hot. The existing
*-hpd-after-suspend subtests use system suspend instead.

Checking only that the display comes back would pass whether or not the
driver fell back to the ~10s connector poll, so the subtest runs two
phases against the same suspended device.

Phase 1 parks the device in D3hot with PME_En set and samples the D
state from the PCI Power Management Control/Status register across a
window longer than two poll periods, requiring that it never leaves
D3hot. Any resume there means polling is still enabled.

Phase 2 toggles the HPD from the chamelium and requires a prompt uevent,
an updated connector status, and an increase in
power/wakeup_active_count. The counter is what shows the device
signalled its own resume rather than the host initiating one.

Both phases report the D state, PME_Status and the counter delta on
failure rather than asserting a cause, which separates a device that
never signalled from one whose PME was not delivered and from one that
resumed and dropped the HPD afterwards.

Assisted-by: GitHub_Copilot:claude-opus-5
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
---
 tests/chamelium/kms_chamelium_hpd.c | 344 ++++++++++++++++++++++++++++
 1 file changed, 344 insertions(+)

diff --git a/tests/chamelium/kms_chamelium_hpd.c b/tests/chamelium/kms_chamelium_hpd.c
index bd8731c02..1135019c4 100644
--- a/tests/chamelium/kms_chamelium_hpd.c
+++ b/tests/chamelium/kms_chamelium_hpd.c
@@ -33,6 +33,7 @@
  */
 
 #include "kms_chamelium_helper.h"
+#include "igt_device.h"
 
 /**
  * SUBTEST: dp-hpd-fast
@@ -114,6 +115,18 @@
  * Description: Toggle HPD during Suspend, check that uevents are sent and
  *              connector status is updated
  *
+ * SUBTEST: dp-hpd-after-runtime-suspend-d3hot
+ * Description: Toggle HPD while runtime suspended in D3hot with PME signalling
+ *              available, check that connector polling stayed disabled, that the
+ *              device woke itself up and that uevents are sent and connector
+ *              status is updated
+ *
+ * SUBTEST: hdmi-hpd-after-runtime-suspend-d3hot
+ * Description: Toggle HPD while runtime suspended in D3hot with PME signalling
+ *              available, check that connector polling stayed disabled, that the
+ *              device woke itself up and that uevents are sent and connector
+ *              status is updated
+ *
  * SUBTEST: common-hpd-after-suspend
  * Description: Toggle HPD during suspend on all connectors, check that uevents
  * 		are sent and connector status is updated
@@ -152,6 +165,33 @@
 #define HPD_TOGGLE_COUNT_DP_HDMI 15
 #define HPD_TOGGLE_COUNT_FAST 3
 
+/*
+ * The KMS helper polls connectors every 10s, so watch for longer than two poll
+ * periods: a single delayed or coalesced poll then cannot make the test pass.
+ */
+#define PME_POLL_PROOF_WINDOW_MS 25000
+/*
+ * How often to sample the D state during that window. Config space reads do not
+ * resume a device suspended into D3hot, so this catches a poll induced resume
+ * that is too brief to stand out in the runtime PM accounting.
+ */
+#define PME_D_STATE_SAMPLE_MS 100
+/*
+ * If the device never leaves D3hot, all elapsed time is accounted to
+ * runtime_suspended_time and runtime_active_time does not move at all. Allow a
+ * small amount for one unrelated wakeup rather than requiring exactly zero,
+ * while staying well under what two or three poll induced resumes would cost.
+ */
+#define PME_ACTIVE_TIME_SLACK_MS 100
+/* Tolerance for accounting granularity and usleep() overshoot. */
+#define PME_POLL_PROOF_SLACK_MS 500
+/*
+ * A PME is delivered as an interrupt, so the wake is expected to be prompt. The
+ * whole point of the feature is that this is not the ~10s a poll would take.
+ */
+#define PME_WAKE_LATENCY_MAX_MS 3000
+#define PME_HPD_TOGGLE_DELAY_MS 1000
+
 enum test_modeset_mode {
 	TEST_MODESET_ON,
 	TEST_MODESET_ON_OFF,
@@ -383,6 +423,302 @@ static void test_suspend_resume_hpd_common(chamelium_data_t *data,
 	igt_cleanup_uevents(mon);
 }
 
+/*
+ * Name a D state read back from config space, for failure messages. PMCS cannot
+ * report D3cold - a device in D3cold is resumed by the read itself and answers
+ * as D0 - so an unknown state here means the read failed outright, i.e. the
+ * device has gone away.
+ */
+static const char *pme_d_state_name(enum igt_acpi_d_state state)
+{
+	switch (state) {
+	case IGT_ACPI_D0:
+		return "D0";
+	case IGT_ACPI_D1:
+		return "D1";
+	case IGT_ACPI_D2:
+		return "D2";
+	case IGT_ACPI_D3Hot:
+		return "D3hot";
+	case IGT_ACPI_D3Cold:
+		return "D3cold";
+	default:
+		return "an unreadable state";
+	}
+}
+
+static void try_hpd_runtime_suspend_pme(chamelium_data_t *data,
+					struct chamelium_port *port,
+					struct pci_device *pci_dev,
+					struct udev_monitor *mon,
+					bool connected)
+{
+	drmModeConnection target_state = connected ? DRM_MODE_DISCONNECTED :
+						     DRM_MODE_CONNECTED;
+	int timeout = CHAMELIUM_HOTPLUG_TIMEOUT;
+	uint64_t susp_before, active_before, wakeups_before, wakeups_after;
+	uint64_t wakeups_at_toggle;
+	uint64_t susp_delta, active_delta;
+	struct timespec start, end;
+	int latency;
+
+	igt_flush_uevents(mon);
+
+	igt_assert_f(igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED),
+		     "Device did not runtime suspend\n");
+
+	/*
+	 * Intel graphics devices support PME in D3hot but not in D3cold, and xe
+	 * chooses the target state itself, so there is nothing to force from
+	 * userspace. In practice an integrated device always lands in D3hot,
+	 * since xe needs an ACPI _PR3 power resource on the upstream port before
+	 * it considers D3cold at all. Check anyway: on a device that did drop to
+	 * D3cold there is no PME to observe and everything below would only
+	 * exercise the polling fallback, so skip.
+	 *
+	 * A device in D3cold answers this read as D0 rather than as D3cold, for
+	 * the reason described above pme_d_state_name(), which fails the check
+	 * just the same.
+	 */
+	igt_require_f(igt_pm_pci_get_d_state(pci_dev) == IGT_ACPI_D3Hot,
+		      "Device is not suspended in D3hot, so there is no PME to "
+		      "observe\n");
+
+	/*
+	 * PME_En is the direct sign that the feature engaged; without it, the test
+	 * would only be measuring the polling fallback.
+	 */
+	igt_assert_f(igt_pm_pci_pme_enabled(pci_dev),
+		     "PME_En is not set after suspending into D3hot\n");
+
+	/*
+	 * Phase 1: ensure the device stays in D3hot while idle. If polling remains on,
+	 * the KMS helper will resume it to probe connectors.
+	 */
+	susp_before = igt_pm_get_runtime_suspended_time(pci_dev);
+	active_before = igt_pm_get_runtime_active_time(pci_dev);
+	wakeups_before = igt_pm_get_wakeup_active_count(pci_dev);
+
+	igt_assert_eq(igt_gettime(&start), 0);
+	do {
+		enum igt_acpi_d_state d_state = igt_pm_pci_get_d_state(pci_dev);
+
+		/*
+		 * Distinguish self-woken resumes from host-driven ones. A self-wakeup bumps
+		 * wakeup_active_count; a host-driven resume does not.
+		 */
+		if (d_state != IGT_ACPI_D3Hot) {
+			bool self_woke;
+
+			wakeups_after = igt_pm_get_wakeup_active_count(pci_dev);
+			self_woke = wakeups_after > wakeups_before;
+
+			igt_assert_eq(igt_gettime(&end), 0);
+			igt_assert_f(false,
+				     "Device left D3hot into %s after %.0fms of "
+				     "a %dms idle window.\n"
+				     "wakeup_active_count %" PRIu64 " -> %" PRIu64
+				     ", so the resume was %s.\n%s\n",
+				     pme_d_state_name(d_state),
+				     igt_time_elapsed(&start, &end) * 1000,
+				     PME_POLL_PROOF_WINDOW_MS,
+				     wakeups_before, wakeups_after,
+				     self_woke ? "signalled by the device" :
+						 "initiated by the host",
+				     self_woke ?
+				     "No hotplug was requested yet, so this is a "
+				     "spurious or still pending PME rather than "
+				     "the polling fallback." :
+				     "The polling fallback resumes on a 10s period, "
+				     "or 1s while a delayed event is pending, so "
+				     "compare the elapsed time above: a wake at an "
+				     "unrelated delay is some other client or "
+				     "driver taking a display power reference "
+				     "rather than connector polling.");
+		}
+
+		usleep(PME_D_STATE_SAMPLE_MS * 1000);
+
+		igt_assert_eq(igt_gettime(&end), 0);
+	} while (igt_time_elapsed(&start, &end) * 1000 < PME_POLL_PROOF_WINDOW_MS);
+
+	susp_delta = igt_pm_get_runtime_suspended_time(pci_dev) - susp_before;
+	active_delta = igt_pm_get_runtime_active_time(pci_dev) - active_before;
+
+	igt_info("Idle for %dms in D3hot: suspended +%" PRIu64 "ms, active +%" PRIu64 "ms\n",
+		 PME_POLL_PROOF_WINDOW_MS, susp_delta, active_delta);
+
+	/*
+	 * Belt and braces on top of the D state sampling above, which covers
+	 * resumes shorter than the sample interval: with the device parked in
+	 * D3hot for the whole window, all of the elapsed time is accounted to
+	 * runtime_suspended_time and runtime_active_time should barely move.
+	 */
+	igt_assert_f(active_delta <= PME_ACTIVE_TIME_SLACK_MS,
+		     "Device was active for %" PRIu64 "ms of a %dms idle window, "
+		     "so it resumed for shorter than the %dms sample interval. "
+		     "Something is still waking the device while idle and the "
+		     "feature saves no power\n",
+		     active_delta, PME_POLL_PROOF_WINDOW_MS,
+		     PME_D_STATE_SAMPLE_MS);
+	igt_assert_lte(PME_POLL_PROOF_WINDOW_MS - PME_POLL_PROOF_SLACK_MS,
+		       susp_delta);
+
+	/*
+	 * Phase 2: fire the HPD and check the device wakes up promptly. The
+	 * toggle is scheduled over XMLRPC, which travels over the network and so
+	 * does not disturb the GPU while we wait for the uevent.
+	 *
+	 * Take a fresh wakeup baseline rather than reusing the one from phase 1,
+	 * which is a whole idle window old by now. Phase 1 only requires that
+	 * the device stayed in D3hot, which a PME that resumed nothing at all
+	 * would not violate, so the counter is not guaranteed to be unchanged.
+	 */
+	wakeups_at_toggle = igt_pm_get_wakeup_active_count(pci_dev);
+
+	chamelium_schedule_hpd_toggle(data->chamelium, port,
+				      PME_HPD_TOGGLE_DELAY_MS, !connected);
+
+	igt_assert_eq(igt_gettime(&start), 0);
+	if (!chamelium_wait_for_hotplug(mon, &timeout)) {
+		enum igt_acpi_d_state d_state = igt_pm_pci_get_d_state(pci_dev);
+		bool pending = igt_pm_pci_pme_status(pci_dev);
+		const char *cause;
+
+		wakeups_after = igt_pm_get_wakeup_active_count(pci_dev);
+
+		/*
+		 * If the device stays in D3hot, the wake is from PME. If it returns to D0,
+		 * the HPD was handled by the driver resume path.
+		 */
+		if (d_state == IGT_ACPI_D3Hot)
+			cause = pending ?
+				"The device signalled a PME that was never "
+				"delivered, so the PME is not reaching the OS." :
+				"The device never signalled a PME, so the HPD "
+				"is not reaching the PME logic.";
+		else
+			cause = "The device resumed but sent no uevent, so the "
+				"HPD was dropped on the resume path.";
+
+		igt_assert_f(false,
+			     "No hotplug uevent %ds after an HPD toggle in D3hot.\n"
+			     "Device is in %s, PME_Status is %s, "
+			     "wakeup_active_count %" PRIu64 " -> %" PRIu64 ".\n%s\n",
+			     CHAMELIUM_HOTPLUG_TIMEOUT,
+			     pme_d_state_name(d_state),
+			     pending ? "set" : "clear",
+			     wakeups_at_toggle, wakeups_after, cause);
+	}
+	igt_assert_eq(igt_gettime(&end), 0);
+
+	latency = igt_time_elapsed(&start, &end) * 1000 -
+		  PME_HPD_TOGGLE_DELAY_MS;
+
+	/*
+	 * wakeup_active_count incrementing means the resume was signalled by the
+	 * device itself, i.e. by a PME. Unlike PME_Status, which the PCI/PM core
+	 * clears on the way back to D0, this counter survives the resume and so
+	 * is not racy to sample here.
+	 */
+	wakeups_after = igt_pm_get_wakeup_active_count(pci_dev);
+
+	igt_info("HPD to uevent latency %dms, wakeup_active_count %" PRIu64 " -> %" PRIu64 "\n",
+		 latency, wakeups_at_toggle, wakeups_after);
+
+	igt_assert_f(wakeups_after > wakeups_at_toggle,
+		     "power/wakeup_active_count did not increment, so the resume "
+		     "was not triggered by a PME from the device\n");
+	igt_assert_lt(latency, PME_WAKE_LATENCY_MAX_MS);
+
+	chamelium_assert_reachable(data->chamelium, ONLINE_TIMEOUT);
+	igt_assert_eq(chamelium_reprobe_connector(&data->display,
+						  data->chamelium, port),
+		      target_state);
+}
+
+/*
+ * Mirror of the driver's own HAS_PM_PME_SUPPORT(): only xe reports PME
+ * capability to the display code, and only from graphics IP 35.10 on.
+ */
+#define PME_HPD_MIN_GRAPHICS_VERX100 3500
+
+static bool pme_hpd_supported(int fd)
+{
+	const struct intel_device_info *info;
+
+	if (!is_xe_device(fd))
+		return false;
+
+	info = intel_get_device_info(intel_get_drm_devid(fd));
+
+	return info->graphics_ver * 100 + info->graphics_rel >=
+	       PME_HPD_MIN_GRAPHICS_VERX100;
+}
+
+static const char test_hpd_runtime_suspend_pme_desc[] =
+	"Toggle HPD while runtime suspended in D3hot with PME signalling "
+	"available, check that connector polling stayed disabled, that the "
+	"device woke itself up and that uevents are sent and connector status "
+	"is updated";
+static void test_hpd_runtime_suspend_pme(chamelium_data_t *data,
+					 struct chamelium_port *port)
+{
+	struct pci_device *pci_dev;
+	struct udev_monitor *mon;
+
+	pci_dev = igt_device_get_pci_device(data->drm_fd);
+
+	/*
+	 * Without driver support the device keeps HPD polling enabled and phase
+	 * 1 would fail rather than skip, so gate on the platform before looking
+	 * at the hardware capability at all.
+	 */
+	igt_require_f(pme_hpd_supported(data->drm_fd),
+		      "Driver does not use PME for HPD on this platform\n");
+
+	igt_require_f(igt_pm_pci_pme_supported(pci_dev, IGT_ACPI_D3Hot),
+		      "Device does not advertise PME support in D3hot\n");
+	igt_require_f(igt_pm_has_wakeup_support(pci_dev),
+		      "Device does not expose power/wakeup\n");
+	igt_require(igt_setup_runtime_pm(data->drm_fd));
+	igt_require_hpd_storm_ctl(data->drm_fd);
+
+	/*
+	 * Need both: PME is only armed when device_may_wakeup() is true, and
+	 * without wakeup support the PM core never records the PME wakeup.
+	 */
+	igt_pm_set_wakeup_enabled(pci_dev, true);
+
+	/*
+	 * Save the poll setting so a previous test cannot leave it disabled and
+	 * fake a pass. Polling must stay enabled; the test checks that the driver
+	 * does not use it when PME is available.
+	 */
+	igt_require(igt_pm_kms_poll_save());
+	igt_pm_kms_poll_set(true);
+
+	/* Don't let our own toggles trip the storm detection into polling. */
+	igt_hpd_storm_set_threshold(data->drm_fd, 0);
+
+	igt_modeset_disable_all_outputs(&data->display);
+
+	mon = igt_watch_uevents();
+	chamelium_reset_state(&data->display, data->chamelium, port,
+			      data->ports, data->port_count);
+
+	/* Ports are left disconnected by the reset, so plug first. */
+	try_hpd_runtime_suspend_pme(data, port, pci_dev, mon, false);
+
+	/* Now check we notice a disconnect signalled from D3hot too. */
+	try_hpd_runtime_suspend_pme(data, port, pci_dev, mon, true);
+
+	igt_cleanup_uevents(mon);
+	igt_hpd_storm_reset(data->drm_fd);
+	igt_pm_kms_poll_restore();
+	igt_pm_restore_wakeup();
+}
+
 static const char test_hpd_without_ddc_desc[] =
 	"Disable DDC on a VGA connector, check we still get a uevent on hotplug";
 static void test_hpd_without_ddc(chamelium_data_t *data,
@@ -500,6 +836,10 @@ int igt_main()
 	connector_subtest("dp-hpd-after-hibernate", DisplayPort, &data, test_suspend_resume_hpd,
 			  SUSPEND_STATE_DISK, SUSPEND_TEST_DEVICES);
 
+	igt_describe(test_hpd_runtime_suspend_pme_desc);
+	connector_subtest("dp-hpd-after-runtime-suspend-d3hot", DisplayPort,
+			  &data, test_hpd_runtime_suspend_pme);
+
 	igt_describe(test_hpd_storm_detect_desc);
 	connector_subtest("dp-hpd-storm", DisplayPort, &data, test_hpd_storm_detect,
 			  HPD_STORM_PULSE_INTERVAL_DP);
@@ -538,6 +878,10 @@ int igt_main()
 	connector_subtest("hdmi-hpd-after-hibernate", HDMIA, &data, test_suspend_resume_hpd,
 			  SUSPEND_STATE_DISK, SUSPEND_TEST_DEVICES);
 
+	igt_describe(test_hpd_runtime_suspend_pme_desc);
+	connector_subtest("hdmi-hpd-after-runtime-suspend-d3hot", HDMIA,
+			  &data, test_hpd_runtime_suspend_pme);
+
 	igt_describe(test_hpd_storm_detect_desc);
 	connector_subtest("hdmi-hpd-storm", HDMIA, &data, test_hpd_storm_detect,
 			  HPD_STORM_PULSE_INTERVAL_HDMI);
-- 
2.53.0

RE: [PATCH i-g-t v2 7/7] tests/chamelium/kms_chamelium_hpd: Add HPD from runtime suspended D3hot

[Joshi, Kunal1]

Hello Pranay,

> -----Original Message-----
> From: Samala, Pranay <pranay.samala@intel.com>
> Sent: Friday, October 9, 2026 10:56 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Joshi, Kunal1 <kunal1.joshi@intel.com>; Lattannavar, Sameer
> <sameer.lattannavar@intel.com>; Samala, Pranay
> <pranay.samala@intel.com>
> Subject: [PATCH i-g-t v2 7/7] tests/chamelium/kms_chamelium_hpd: Add
> HPD from runtime suspended D3hot
> 
> Add dp-hpd-after-runtime-suspend-d3hot and hdmi-hpd-after-runtime-
> suspend-d3hot, covering a hotplug signalled by a PME while the device is
> runtime suspended in D3hot. The existing *-hpd-after-suspend subtests use
> system suspend instead.
> 
> Checking only that the display comes back would pass whether or not the
> driver fell back to the ~10s connector poll, so the subtest runs two phases
> against the same suspended device.
> 
> Phase 1 parks the device in D3hot with PME_En set and samples the D state
> from the PCI Power Management Control/Status register across a window
> longer than two poll periods, requiring that it never leaves D3hot. Any
> resume there means polling is still enabled.
> 
> Phase 2 toggles the HPD from the chamelium and requires a prompt uevent,
> an updated connector status, and an increase in
> power/wakeup_active_count. The counter is what shows the device signalled
> its own resume rather than the host initiating one.
> 
> Both phases report the D state, PME_Status and the counter delta on failure
> rather than asserting a cause, which separates a device that never signalled
> from one whose PME was not delivered and from one that resumed and
> dropped the HPD afterwards.
> 
> Assisted-by: GitHub_Copilot:claude-opus-5
> Signed-off-by: Pranay Samala <pranay.samala@intel.com>
> ---
>  tests/chamelium/kms_chamelium_hpd.c | 344
> ++++++++++++++++++++++++++++
>  1 file changed, 344 insertions(+)
> 
> diff --git a/tests/chamelium/kms_chamelium_hpd.c
> b/tests/chamelium/kms_chamelium_hpd.c
> index bd8731c02..1135019c4 100644
> --- a/tests/chamelium/kms_chamelium_hpd.c
> +++ b/tests/chamelium/kms_chamelium_hpd.c
> @@ -33,6 +33,7 @@
>   */
> 
>  #include "kms_chamelium_helper.h"
> +#include "igt_device.h"
> 
>  /**
>   * SUBTEST: dp-hpd-fast
> @@ -114,6 +115,18 @@
>   * Description: Toggle HPD during Suspend, check that uevents are sent and
>   *              connector status is updated
>   *
> + * SUBTEST: dp-hpd-after-runtime-suspend-d3hot
> + * Description: Toggle HPD while runtime suspended in D3hot with PME
> signalling
> + *              available, check that connector polling stayed disabled, that the
> + *              device woke itself up and that uevents are sent and connector
> + *              status is updated
> + *
> + * SUBTEST: hdmi-hpd-after-runtime-suspend-d3hot
> + * Description: Toggle HPD while runtime suspended in D3hot with PME
> signalling
> + *              available, check that connector polling stayed disabled, that the
> + *              device woke itself up and that uevents are sent and connector
> + *              status is updated
> + *
>   * SUBTEST: common-hpd-after-suspend
>   * Description: Toggle HPD during suspend on all connectors, check that
> uevents
>   * 		are sent and connector status is updated
> @@ -152,6 +165,33 @@
>  #define HPD_TOGGLE_COUNT_DP_HDMI 15
>  #define HPD_TOGGLE_COUNT_FAST 3
> 
> +/*
> + * The KMS helper polls connectors every 10s, so watch for longer than
> +two poll
> + * periods: a single delayed or coalesced poll then cannot make the test
> pass.
> + */
> +#define PME_POLL_PROOF_WINDOW_MS 25000
> +/*
> + * How often to sample the D state during that window. Config space
> +reads do not
> + * resume a device suspended into D3hot, so this catches a poll induced
> +resume
> + * that is too brief to stand out in the runtime PM accounting.
> + */
> +#define PME_D_STATE_SAMPLE_MS 100
> +/*
> + * If the device never leaves D3hot, all elapsed time is accounted to
> + * runtime_suspended_time and runtime_active_time does not move at all.
> +Allow a
> + * small amount for one unrelated wakeup rather than requiring exactly
> +zero,
> + * while staying well under what two or three poll induced resumes would
> cost.
> + */
> +#define PME_ACTIVE_TIME_SLACK_MS 100
> +/* Tolerance for accounting granularity and usleep() overshoot. */
> +#define PME_POLL_PROOF_SLACK_MS 500
> +/*
> + * A PME is delivered as an interrupt, so the wake is expected to be
> +prompt. The
> + * whole point of the feature is that this is not the ~10s a poll would take.
> + */
> +#define PME_WAKE_LATENCY_MAX_MS 3000

It is not always an interrupt. Without a GPE / PCIe PME route, the PCI
core PME poll delivers it within 1s. The 3s budget is fine, please fix
the comment.

> +#define PME_HPD_TOGGLE_DELAY_MS 1000
> +
>  enum test_modeset_mode {
>  	TEST_MODESET_ON,
>  	TEST_MODESET_ON_OFF,
> @@ -383,6 +423,302 @@ static void
> test_suspend_resume_hpd_common(chamelium_data_t *data,
>  	igt_cleanup_uevents(mon);
>  }
> 
> +/*
> + * Name a D state read back from config space, for failure messages.
> +PMCS cannot
> + * report D3cold - a device in D3cold is resumed by the read itself and
> +answers
> + * as D0 - so an unknown state here means the read failed outright,
> +i.e. the
> + * device has gone away.
> + */
> +static const char *pme_d_state_name(enum igt_acpi_d_state state) {
> +	switch (state) {
> +	case IGT_ACPI_D0:
> +		return "D0";
> +	case IGT_ACPI_D1:
> +		return "D1";
> +	case IGT_ACPI_D2:
> +		return "D2";
> +	case IGT_ACPI_D3Hot:
> +		return "D3hot";
> +	case IGT_ACPI_D3Cold:
> +		return "D3cold";
> +	default:
> +		return "an unreadable state";
> +	}
> +}
> +
> +static void try_hpd_runtime_suspend_pme(chamelium_data_t *data,
> +					struct chamelium_port *port,
> +					struct pci_device *pci_dev,
> +					struct udev_monitor *mon,
> +					bool connected)
> +{
> +	drmModeConnection target_state = connected ?
> DRM_MODE_DISCONNECTED :
> +						     DRM_MODE_CONNECTED;
> +	int timeout = CHAMELIUM_HOTPLUG_TIMEOUT;
> +	uint64_t susp_before, active_before, wakeups_before,
> wakeups_after;
> +	uint64_t wakeups_at_toggle;
> +	uint64_t susp_delta, active_delta;
> +	struct timespec start, end;
> +	int latency;
> +
> +	igt_flush_uevents(mon);
> +
> +
> 	igt_assert_f(igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUS
> PENDED),
> +		     "Device did not runtime suspend\n");
> +
> +	/*
> +	 * Intel graphics devices support PME in D3hot but not in D3cold, and
> xe
> +	 * chooses the target state itself, so there is nothing to force from
> +	 * userspace. In practice an integrated device always lands in D3hot,
> +	 * since xe needs an ACPI _PR3 power resource on the upstream port
> before
> +	 * it considers D3cold at all. Check anyway: on a device that did drop
> to
> +	 * D3cold there is no PME to observe and everything below would
> only
> +	 * exercise the polling fallback, so skip.
> +	 *
> +	 * A device in D3cold answers this read as D0 rather than as D3cold,
> for
> +	 * the reason described above pme_d_state_name(), which fails the
> check
> +	 * just the same.
> +	 */
> +	igt_require_f(igt_pm_pci_get_d_state(pci_dev) == IGT_ACPI_D3Hot,
> +		      "Device is not suspended in D3hot, so there is no PME to
> "
> +		      "observe\n");

A few issues here:
- This runs in every try. If something wakes the device between the
  runtime_status check and this read (or in the 2nd try after the 1st
  passed), we report SKIP instead of FAIL. That is exactly the spurious
  wake phase 1 wants to catch.
- For D3cold the read itself resumes the device (see 2/7).
- For iGPU, d3cold is never capable because pcie_find_root_port()
  returns NULL; _PR3 is not even checked. For dGPU, D3hot can be forced
  with vram_d3cold_threshold = 0, so "nothing to force" is not correct.

Please decide D3hot once upfront (power_state sysfs) and use igt_assert
here.

> +
> +	/*
> +	 * PME_En is the direct sign that the feature engaged; without it, the
> test
> +	 * would only be measuring the polling fallback.
> +	 */
> +	igt_assert_f(igt_pm_pci_pme_enabled(pci_dev),
> +		     "PME_En is not set after suspending into D3hot\n");
> +
> +	/*
> +	 * Phase 1: ensure the device stays in D3hot while idle. If polling
> remains on,
> +	 * the KMS helper will resume it to probe connectors.
> +	 */
> +	susp_before = igt_pm_get_runtime_suspended_time(pci_dev);
> +	active_before = igt_pm_get_runtime_active_time(pci_dev);
> +	wakeups_before = igt_pm_get_wakeup_active_count(pci_dev);

The window starts as soon as the device is seen suspended. Leftover HPD
retry work (HPD_RETRY_DELAY 1s) from the previous plug, an HDA runtime
resume, etc. can still wake the device, and then we blame polling.
Please let it stay suspended for 2-3s before taking the baselines.

Also 25s x 2 tries x every port of that type comes to ~1 min per port.
The idle window is needed only once; the 2nd try can go directly to
phase 2.


> +
> +	igt_assert_eq(igt_gettime(&start), 0);
> +	do {
> +		enum igt_acpi_d_state d_state =
> igt_pm_pci_get_d_state(pci_dev);
> +
> +		/*
> +		 * Distinguish self-woken resumes from host-driven ones. A
> self-wakeup bumps
> +		 * wakeup_active_count; a host-driven resume does not.
> +		 */
> +		if (d_state != IGT_ACPI_D3Hot) {
> +			bool self_woke;
> +
> +			wakeups_after =
> igt_pm_get_wakeup_active_count(pci_dev);
> +			self_woke = wakeups_after > wakeups_before;
> +
> +			igt_assert_eq(igt_gettime(&end), 0);
> +			igt_assert_f(false,
nit: igt_assert_f(false, ...) is used in two places. Better to assert on
the actual condition or use igt_fail_on_f().

> +				     "Device left D3hot into %s after %.0fms of
> "
> +				     "a %dms idle window.\n"
> +				     "wakeup_active_count %" PRIu64 " -> %"
> PRIu64
> +				     ", so the resume was %s.\n%s\n",
> +				     pme_d_state_name(d_state),
> +				     igt_time_elapsed(&start, &end) * 1000,
> +				     PME_POLL_PROOF_WINDOW_MS,
> +				     wakeups_before, wakeups_after,
> +				     self_woke ? "signalled by the device" :
> +						 "initiated by the host",
> +				     self_woke ?
> +				     "No hotplug was requested yet, so this is a
> "
> +				     "spurious or still pending PME rather than
> "
> +				     "the polling fallback." :
> +				     "The polling fallback resumes on a 10s
> period, "
> +				     "or 1s while a delayed event is pending, so
> "
> +				     "compare the elapsed time above: a wake
> at an "
> +				     "unrelated delay is some other client or "
> +				     "driver taking a display power reference "
> +				     "rather than connector polling.");
> +		}
> +
> +		usleep(PME_D_STATE_SAMPLE_MS * 1000);
> +
> +		igt_assert_eq(igt_gettime(&end), 0);
> +	} while (igt_time_elapsed(&start, &end) * 1000 <
> +PME_POLL_PROOF_WINDOW_MS);
> +
> +	susp_delta = igt_pm_get_runtime_suspended_time(pci_dev) -
> susp_before;
> +	active_delta = igt_pm_get_runtime_active_time(pci_dev) -
> +active_before;
> +
> +	igt_info("Idle for %dms in D3hot: suspended +%" PRIu64 "ms, active
> +%" PRIu64 "ms\n",
> +		 PME_POLL_PROOF_WINDOW_MS, susp_delta, active_delta);
> +
> +	/*
> +	 * Belt and braces on top of the D state sampling above, which covers
> +	 * resumes shorter than the sample interval: with the device parked
> in
> +	 * D3hot for the whole window, all of the elapsed time is accounted
> to
> +	 * runtime_suspended_time and runtime_active_time should barely
> move.
> +	 */
> +	igt_assert_f(active_delta <= PME_ACTIVE_TIME_SLACK_MS,
> +		     "Device was active for %" PRIu64 "ms of a %dms idle
> window, "
> +		     "so it resumed for shorter than the %dms sample interval.
> "
> +		     "Something is still waking the device while idle and the "
> +		     "feature saves no power\n",
> +		     active_delta, PME_POLL_PROOF_WINDOW_MS,
> +		     PME_D_STATE_SAMPLE_MS);
> +	igt_assert_lte(PME_POLL_PROOF_WINDOW_MS -
> PME_POLL_PROOF_SLACK_MS,
> +		       susp_delta);

susp_delta is uint64_t, please use igt_assert_lte_u64().

> +
> +	/*
> +	 * Phase 2: fire the HPD and check the device wakes up promptly. The
> +	 * toggle is scheduled over XMLRPC, which travels over the network
> and so
> +	 * does not disturb the GPU while we wait for the uevent.
> +	 *
> +	 * Take a fresh wakeup baseline rather than reusing the one from
> phase 1,
> +	 * which is a whole idle window old by now. Phase 1 only requires
> that
> +	 * the device stayed in D3hot, which a PME that resumed nothing at
> all
> +	 * would not violate, so the counter is not guaranteed to be
> unchanged.
> +	 */
> +	wakeups_at_toggle = igt_pm_get_wakeup_active_count(pci_dev);
> +
> +	chamelium_schedule_hpd_toggle(data->chamelium, port,
> +				      PME_HPD_TOGGLE_DELAY_MS,
> !connected);
> +
> +	igt_assert_eq(igt_gettime(&start), 0);
> +	if (!chamelium_wait_for_hotplug(mon, &timeout)) {

uevents are flushed at the start of the try, ~25s before this. Any
uevent in between satisfies the wait immediately, latency goes negative,
and it still passes the < 3000 check. Please flush here just before
scheduling the toggle, take start before the XMLRPC call, and assert
latency >= 0.

> +		enum igt_acpi_d_state d_state =
> igt_pm_pci_get_d_state(pci_dev);
> +		bool pending = igt_pm_pci_pme_status(pci_dev);
> +		const char *cause;
> +
> +		wakeups_after = igt_pm_get_wakeup_active_count(pci_dev);
> +
> +		/*
> +		 * If the device stays in D3hot, the wake is from PME. If it
> returns to D0,
> +		 * the HPD was handled by the driver resume path.
> +		 */
> +		if (d_state == IGT_ACPI_D3Hot)
> +			cause = pending ?
> +				"The device signalled a PME that was never "
> +				"delivered, so the PME is not reaching the
> OS." :
> +				"The device never signalled a PME, so the
> HPD "
> +				"is not reaching the PME logic.";
> +		else
> +			cause = "The device resumed but sent no uevent, so
> the "
> +				"HPD was dropped on the resume path.";
> +
> +		igt_assert_f(false,
> +			     "No hotplug uevent %ds after an HPD toggle in
> D3hot.\n"
> +			     "Device is in %s, PME_Status is %s, "
> +			     "wakeup_active_count %" PRIu64 " -> %" PRIu64
> ".\n%s\n",
> +			     CHAMELIUM_HOTPLUG_TIMEOUT,
> +			     pme_d_state_name(d_state),
> +			     pending ? "set" : "clear",
> +			     wakeups_at_toggle, wakeups_after, cause);
> +	}
> +	igt_assert_eq(igt_gettime(&end), 0);
> +
> +	latency = igt_time_elapsed(&start, &end) * 1000 -
> +		  PME_HPD_TOGGLE_DELAY_MS;
> +
> +	/*
> +	 * wakeup_active_count incrementing means the resume was
> signalled by the
> +	 * device itself, i.e. by a PME. Unlike PME_Status, which the PCI/PM
> core
> +	 * clears on the way back to D0, this counter survives the resume and
> so
> +	 * is not racy to sample here.
> +	 */
> +	wakeups_after = igt_pm_get_wakeup_active_count(pci_dev);
> +
> +	igt_info("HPD to uevent latency %dms, wakeup_active_count %"
> PRIu64 " -> %" PRIu64 "\n",
> +		 latency, wakeups_at_toggle, wakeups_after);
> +
> +	igt_assert_f(wakeups_after > wakeups_at_toggle,
> +		     "power/wakeup_active_count did not increment, so the
> resume "
> +		     "was not triggered by a PME from the device\n");
> +	igt_assert_lt(latency, PME_WAKE_LATENCY_MAX_MS);
> +
> +	chamelium_assert_reachable(data->chamelium, ONLINE_TIMEOUT);
> +	igt_assert_eq(chamelium_reprobe_connector(&data->display,
> +						  data->chamelium, port),
> +		      target_state);
> +}
> +
> +/*
> + * Mirror of the driver's own HAS_PM_PME_SUPPORT(): only xe reports
> PME
> + * capability to the display code, and only from graphics IP 35.10 on.
> + */
> +#define PME_HPD_MIN_GRAPHICS_VERX100 3500
> +
> +static bool pme_hpd_supported(int fd)
> +{
> +	const struct intel_device_info *info;
> +
> +	if (!is_xe_device(fd))
> +		return false;
> +
> +	info = intel_get_device_info(intel_get_drm_devid(fd));
> +
> +	return info->graphics_ver * 100 + info->graphics_rel >=
> +	       PME_HPD_MIN_GRAPHICS_VERX100;

The comment says 35.10 but the value is 35.00 (same as kernel). Also no
need to open code this; we already have intel_graphics_ver() + IP_VER(),
see lib/xe/xe_query.c:
> +}
> +
> +static const char test_hpd_runtime_suspend_pme_desc[] =
> +	"Toggle HPD while runtime suspended in D3hot with PME signalling "
> +	"available, check that connector polling stayed disabled, that the "
> +	"device woke itself up and that uevents are sent and connector status
> "
> +	"is updated";
> +static void test_hpd_runtime_suspend_pme(chamelium_data_t *data,
> +					 struct chamelium_port *port)
> +{
> +	struct pci_device *pci_dev;
> +	struct udev_monitor *mon;
> +
> +	pci_dev = igt_device_get_pci_device(data->drm_fd);
> +
> +	/*
> +	 * Without driver support the device keeps HPD polling enabled and
> phase
> +	 * 1 would fail rather than skip, so gate on the platform before
> looking
> +	 * at the hardware capability at all.
> +	 */
> +	igt_require_f(pme_hpd_supported(data->drm_fd),
> +		      "Driver does not use PME for HPD on this platform\n");
> +
> +	igt_require_f(igt_pm_pci_pme_supported(pci_dev,
> IGT_ACPI_D3Hot),
> +		      "Device does not advertise PME support in D3hot\n");
> +	igt_require_f(igt_pm_has_wakeup_support(pci_dev),
> +		      "Device does not expose power/wakeup\n");
> +	igt_require(igt_setup_runtime_pm(data->drm_fd));
> +	igt_require_hpd_storm_ctl(data->drm_fd);
> +
> +	/*
> +	 * Need both: PME is only armed when device_may_wakeup() is true,
> and
> +	 * without wakeup support the PM core never records the PME
> wakeup.
> +	 */
> +	igt_pm_set_wakeup_enabled(pci_dev, true);
> +
> +	/*
> +	 * Save the poll setting so a previous test cannot leave it disabled and
> +	 * fake a pass. Polling must stay enabled; the test checks that the
> driver
> +	 * does not use it when PME is available.
> +	 */
> +	igt_require(igt_pm_kms_poll_save());
> +	igt_pm_kms_poll_set(true);

This doesn't guarantee polling is actually running.
Also nothing proves that 100ms sampling + 100ms slack will catch a poll
wakeup on this machine. So phase 1 can pass even on a kernel which still
polls.

Can we add a control step before arming PME, something like:

        igt_pm_set_wakeup_enabled(pci_dev, false);
        /* resume once so that next suspend re-evaluates pme.enabled */
        ...wait for suspend...
        igt_assert(!igt_pm_pci_pme_enabled(pci_dev));
        igt_skip_on_f(!device_woke_within(pci_dev, 2 * 10000),
                      "Connector polling not running, can't validate\n");

        igt_pm_set_wakeup_enabled(pci_dev, true);
        /* resume again, take fresh wakeup_active_count baseline */

This proves polling is live, and the only difference is PME armed or
not. It also gives the real poll wakeup cost to tune
PME_ACTIVE_TIME_SLACK_MS.

Also, igt_require() here comes after we already changed power/wakeup.
Please do all requires first and then modify the state. Restore happens
only on the success path, so on fail/skip the next subtest (hdmi after
dp) runs with the modified state.


Thanks and Regards
Kunal Joshi


> +
> +	/* Don't let our own toggles trip the storm detection into polling. */
> +	igt_hpd_storm_set_threshold(data->drm_fd, 0);
> +
> +	igt_modeset_disable_all_outputs(&data->display);
> +
> +	mon = igt_watch_uevents();
> +	chamelium_reset_state(&data->display, data->chamelium, port,
> +			      data->ports, data->port_count);
> +
> +	/* Ports are left disconnected by the reset, so plug first. */
> +	try_hpd_runtime_suspend_pme(data, port, pci_dev, mon, false);
> +
> +	/* Now check we notice a disconnect signalled from D3hot too. */
> +	try_hpd_runtime_suspend_pme(data, port, pci_dev, mon, true);
> +
> +	igt_cleanup_uevents(mon);
> +	igt_hpd_storm_reset(data->drm_fd);
> +	igt_pm_kms_poll_restore();
> +	igt_pm_restore_wakeup();
> +}
> +
>  static const char test_hpd_without_ddc_desc[] =
>  	"Disable DDC on a VGA connector, check we still get a uevent on
> hotplug";  static void test_hpd_without_ddc(chamelium_data_t *data, @@ -
> 500,6 +836,10 @@ int igt_main()
>  	connector_subtest("dp-hpd-after-hibernate", DisplayPort, &data,
> test_suspend_resume_hpd,
>  			  SUSPEND_STATE_DISK, SUSPEND_TEST_DEVICES);
> 
> +	igt_describe(test_hpd_runtime_suspend_pme_desc);
> +	connector_subtest("dp-hpd-after-runtime-suspend-d3hot",
> DisplayPort,
> +			  &data, test_hpd_runtime_suspend_pme);
> +
>  	igt_describe(test_hpd_storm_detect_desc);
>  	connector_subtest("dp-hpd-storm", DisplayPort, &data,
> test_hpd_storm_detect,
>  			  HPD_STORM_PULSE_INTERVAL_DP);
> @@ -538,6 +878,10 @@ int igt_main()
>  	connector_subtest("hdmi-hpd-after-hibernate", HDMIA, &data,
> test_suspend_resume_hpd,
>  			  SUSPEND_STATE_DISK, SUSPEND_TEST_DEVICES);
> 
> +	igt_describe(test_hpd_runtime_suspend_pme_desc);
> +	connector_subtest("hdmi-hpd-after-runtime-suspend-d3hot",
> HDMIA,
> +			  &data, test_hpd_runtime_suspend_pme);
> +
>  	igt_describe(test_hpd_storm_detect_desc);
>  	connector_subtest("hdmi-hpd-storm", HDMIA, &data,
> test_hpd_storm_detect,
>  			  HPD_STORM_PULSE_INTERVAL_HDMI);
> --
> 2.53.0

✓ Xe.CI.BAT: success for Validate PM_PME signalling on display hotplug (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 782 bytes --]

== Series Details ==

Series: Validate PM_PME signalling on display hotplug (rev3)
URL   : https://patchwork.freedesktop.org/series/172774/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_9138_BAT -> XEIGTPW_15966_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_9138 -> IGTPW_15966

  IGTPW_15966: 15966
  IGT_9138: 9138
  xe-5912-4f1de47ae94bb8aee6bc1c6105609646d9411650: 4f1de47ae94bb8aee6bc1c6105609646d9411650

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/index.html

[-- Attachment #2: Type: text/html, Size: 1327 bytes --]

✗ i915.CI.BAT: failure for Validate PM_PME signalling on display hotplug (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3684 bytes --]

== Series Details ==

Series: Validate PM_PME signalling on display hotplug (rev3)
URL   : https://patchwork.freedesktop.org/series/172774/
State : failure

== Summary ==

CI Bug Log - changes from IGT_9138 -> IGTPW_15966
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_15966 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_15966, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15966/index.html

Participating hosts (39 -> 38)
------------------------------

  Missing    (1): bat-dg2-13 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_15966:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live:
    - bat-rpls-4:         [PASS][1] -> [DMESG-FAIL][2] +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9138/bat-rpls-4/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15966/bat-rpls-4/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in IGTPW_15966 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-dg2-14:         [PASS][3] -> [ABORT][4] ([i915#17063])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9138/bat-dg2-14/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15966/bat-dg2-14/igt@i915_selftest@live.html

  * igt@i915_selftest@live@guc_hang:
    - bat-dg2-14:         [PASS][5] -> [ABORT][6] ([i915#16999])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9138/bat-dg2-14/igt@i915_selftest@live@guc_hang.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15966/bat-dg2-14/igt@i915_selftest@live@guc_hang.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-tgl-1115g4:      [PASS][7] -> [FAIL][8] ([i915#16664])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9138/fi-tgl-1115g4/igt@kms_hdmi_inject@inject-audio.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15966/fi-tgl-1115g4/igt@kms_hdmi_inject@inject-audio.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@late_gt_pm:
    - fi-bsw-nick:        [ABORT][9] -> [PASS][10] +1 other test pass
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9138/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15966/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_selftest@live@requests:
    - bat-atsm-1:         [INCOMPLETE][11] -> [PASS][12] +1 other test pass
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9138/bat-atsm-1/igt@i915_selftest@live@requests.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15966/bat-atsm-1/igt@i915_selftest@live@requests.html

  
  [i915#16664]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16664
  [i915#16999]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16999
  [i915#17063]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17063


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_9138 -> IGTPW_15966

  CI-20190529: 20190529
  CI_DRM_19303: 4f1de47ae94bb8aee6bc1c6105609646d9411650 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_15966: 15966
  IGT_9138: 9138

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15966/index.html

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✗ Xe.CI.FULL: failure for Validate PM_PME signalling on display hotplug (rev3)

[Patchwork]

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== Series Details ==

Series: Validate PM_PME signalling on display hotplug (rev3)
URL   : https://patchwork.freedesktop.org/series/172774/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_9138_FULL -> XEIGTPW_15966_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_15966_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_15966_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_15966_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_chamelium_hpd@dp-hpd-after-runtime-suspend-d3hot (NEW):
    - shard-bmg:          NOTRUN -> [SKIP][1] +1 other test skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-10/igt@kms_chamelium_hpd@dp-hpd-after-runtime-suspend-d3hot.html
    - shard-lnl:          NOTRUN -> [SKIP][2] +1 other test skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-3/igt@kms_chamelium_hpd@dp-hpd-after-runtime-suspend-d3hot.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-runtime-suspend-d3hot (NEW):
    - shard-ptl:          NOTRUN -> [SKIP][3]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@kms_chamelium_hpd@hdmi-hpd-after-runtime-suspend-d3hot.html

  * igt@kms_pm_rpm@legacy-planes:
    - shard-ptl:          [PASS][4] -> [SKIP][5]
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-3/igt@kms_pm_rpm@legacy-planes.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@kms_pm_rpm@legacy-planes.html

  
New tests
---------

  New tests have been introduced between XEIGT_9138_FULL and XEIGTPW_15966_FULL:

### New IGT tests (2) ###

  * igt@kms_chamelium_hpd@dp-hpd-after-runtime-suspend-d3hot:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_chamelium_hpd@hdmi-hpd-after-runtime-suspend-d3hot:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_15966_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-read:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#1125] / [Intel XE#7312])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-ptl:          NOTRUN -> [SKIP][7] ([Intel XE#5765])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-2/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-ptl:          NOTRUN -> [SKIP][8] ([Intel XE#3157])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-ptl:          [PASS][9] -> [ABORT][10] ([Intel XE#9387]) +1 other test abort
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-4/igt@kms_async_flips@async-flip-suspend-resume.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#1407]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-ptl:          NOTRUN -> [SKIP][12] ([Intel XE#6925])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2327])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-7/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#7059] / [Intel XE#7085])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-180:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#1124]) +5 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-ptl:          NOTRUN -> [SKIP][16] ([Intel XE#5808]) +12 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#1124])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-9/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-ptl:          NOTRUN -> [SKIP][18] ([Intel XE#5855])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p:
    - shard-ptl:          NOTRUN -> [SKIP][19] ([Intel XE#7679])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#367])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-7/igt@kms_bw@linear-tiling-2-displays-target-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#367])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-6/igt@kms_bw@linear-tiling-3-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-target-1920x1080p:
    - shard-ptl:          NOTRUN -> [SKIP][22] ([Intel XE#367]) +2 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@kms_bw@linear-tiling-4-displays-target-1920x1080p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc:
    - shard-ptl:          NOTRUN -> [SKIP][23] ([Intel XE#5822]) +12 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2887]) +8 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-7/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#2669] / [Intel XE#7389]) +3 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#2887]) +6 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][27] -> [ABORT][28] ([Intel XE#9406] / [Intel XE#9422]) +1 other test abort
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#3432]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#306] / [Intel XE#7358])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_color@gamma:
    - shard-ptl:          NOTRUN -> [SKIP][31] ([Intel XE#5824])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lim-lut1d:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#7358])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lim-lut1d.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-pre-ctm3x4:
    - shard-ptl:          NOTRUN -> [SKIP][33] ([Intel XE#8391])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@kms_chamelium_color_pipeline@plane-lut1d-pre-ctm3x4.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-ptl:          NOTRUN -> [SKIP][34] ([Intel XE#2252]) +5 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-2/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#373]) +2 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-6/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2252]) +3 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-2/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_color_pipeline@plane-ctm3x4@pipe-a-plane-3:
    - shard-ptl:          NOTRUN -> [SKIP][37] ([Intel XE#6969]) +7 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@kms_color_pipeline@plane-ctm3x4@pipe-a-plane-3.html

  * igt@kms_color_pipeline@plane-lut3d-green-only:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#6969] / [Intel XE#7006]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-2/igt@kms_color_pipeline@plane-lut3d-green-only.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-b-plane-4:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#6969]) +13 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-2/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-b-plane-4.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-ptl:          NOTRUN -> [SKIP][40] ([Intel XE#6974])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@lic-type-0:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#7642])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-1/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][42] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-1/igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2.html

  * igt@kms_content_protection@mei-interface:
    - shard-ptl:          NOTRUN -> [SKIP][43] ([Intel XE#5845])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@suspend-resume@pipe-a-dp-1:
    - shard-bmg:          NOTRUN -> [FAIL][44] ([Intel XE#3304]) +1 other test fail
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-7/igt@kms_content_protection@suspend-resume@pipe-a-dp-1.html

  * igt@kms_content_protection@uevent:
    - shard-ptl:          NOTRUN -> [SKIP][45] ([Intel XE#7642]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-7/igt@kms_content_protection@uevent.html

  * igt@kms_content_protection@uevent-hdcp14@pipe-a-dp-1:
    - shard-bmg:          NOTRUN -> [FAIL][46] ([Intel XE#6707] / [Intel XE#7439])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-7/igt@kms_content_protection@uevent-hdcp14@pipe-a-dp-1.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-ptl:          NOTRUN -> [SKIP][47] ([Intel XE#5846]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@kms_cursor_crc@cursor-onscreen-512x512.html
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-4/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-256x85:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#1424]) +2 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-3/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2320])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-7/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-128x42:
    - shard-ptl:          NOTRUN -> [SKIP][51] ([Intel XE#5900]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@kms_cursor_crc@cursor-sliding-128x42.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1:
    - shard-ptl:          [PASS][52] -> [ABORT][53] ([Intel XE#9362]) +4 other tests abort
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-1/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#309] / [Intel XE#7343]) +5 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-6/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-ptl:          NOTRUN -> [SKIP][55] ([Intel XE#5962]) +2 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-ptl:          NOTRUN -> [SKIP][56] ([Intel XE#5962] / [Intel XE#7343])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-ptl:          NOTRUN -> [SKIP][57] ([Intel XE#6035])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dp_link_training@uhbr-sst-tbtalt-train:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#9537])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_dp_link_training@uhbr-sst-tbtalt-train.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#4331] / [Intel XE#7227])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-3/igt@kms_dp_linktrain_fallback@dsc-fallback.html
    - shard-ptl:          NOTRUN -> [SKIP][60] ([Intel XE#7227])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback:
    - shard-ptl:          NOTRUN -> [SKIP][61] ([Intel XE#9009])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-2/igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#8265]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
    - shard-ptl:          NOTRUN -> [SKIP][63] ([Intel XE#5907])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc-bigjoiner:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#8265])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc-bigjoiner.html

  * igt@kms_fbcon_fbt@psr:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#8680])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-5/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@dsc:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#8586])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_feature_discovery@dsc.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-dp2-hdmi-a3:
    - shard-bmg:          NOTRUN -> [FAIL][67] ([Intel XE#5408] / [Intel XE#6266]) +1 other test fail
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-ptl:          NOTRUN -> [SKIP][68] ([Intel XE#2316]) +7 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-bmg:          [PASS][69] -> [FAIL][70] ([Intel XE#3321]) +1 other test fail
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#1421]) +3 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          NOTRUN -> [FAIL][72] ([Intel XE#301]) +3 other tests fail
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-edp1:
    - shard-ptl:          [PASS][73] -> [FAIL][74] ([Intel XE#3149] / [Intel XE#3321]) +1 other test fail
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-edp1.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385] / [Intel XE#9144])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#1397] / [Intel XE#7385] / [Intel XE#9144])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
    - shard-ptl:          NOTRUN -> [SKIP][77] ([Intel XE#5828]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-7/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-ptl:          NOTRUN -> [SKIP][78] ([Intel XE#7178]) +4 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#7178] / [Intel XE#7351]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff:
    - shard-ptl:          NOTRUN -> [SKIP][80] ([Intel XE#5800] / [Intel XE#6312]) +5 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#6312] / [Intel XE#651]) +8 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][82] ([Intel XE#7061] / [Intel XE#7356]) +4 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-7/igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-spr-indfb-onoff:
    - shard-ptl:          NOTRUN -> [SKIP][83] ([Intel XE#6312]) +9 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#7905]) +23 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-7/igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#4141]) +4 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#656] / [Intel XE#7905]) +21 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#2311]) +16 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-spr-indfb-move:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#6312]) +5 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-spr-indfb-move:
    - shard-ptl:          NOTRUN -> [SKIP][90] ([Intel XE#5812]) +48 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][91] ([Intel XE#7061]) +1 other test skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#7865]) +15 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-4/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#2313]) +9 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-pri-indfb-draw-blt:
    - shard-ptl:          NOTRUN -> [SKIP][94] ([Intel XE#7865]) +22 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#7399])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y.html
    - shard-ptl:          NOTRUN -> [SKIP][96] ([Intel XE#7399])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y.html

  * igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#7061]) +2 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-mmap-wc.html

  * igt@kms_hdmi_audio_bw@audio-bw-hblank160:
    - shard-bmg:          [PASS][98] -> [FAIL][99] ([Intel XE#9313])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-4/igt@kms_hdmi_audio_bw@audio-bw-hblank160.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-6/igt@kms_hdmi_audio_bw@audio-bw-hblank160.html

  * igt@kms_hdmi_audio_bw@audio-bw-hblank80:
    - shard-ptl:          NOTRUN -> [SKIP][100] ([Intel XE#9312])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-ptl:          [PASS][101] -> [SKIP][102] ([Intel XE#7308])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-3/igt@kms_hdmi_inject@inject-audio.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@kms_hdmi_inject@inject-audio.html
    - shard-bmg:          [PASS][103] -> [SKIP][104] ([Intel XE#7308])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-3/igt@kms_hdmi_inject@inject-audio.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-6/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-ptl:          NOTRUN -> [SKIP][105] ([Intel XE#5917] / [Intel XE#6174])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][106] ([Intel XE#7086] / [Intel XE#7390])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-ptl:          NOTRUN -> [SKIP][107] ([Intel XE#6900])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-ptl:          NOTRUN -> [SKIP][108] ([Intel XE#7591])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@pixel-format-x-tiled-modifier:
    - shard-ptl:          NOTRUN -> [SKIP][109] ([Intel XE#7283]) +4 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-2/igt@kms_plane@pixel-format-x-tiled-modifier.html

  * igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5:
    - shard-lnl:          NOTRUN -> [SKIP][110] ([Intel XE#8303]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-1/igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][111] ([Intel XE#7283]) +2 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-2/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-ptl:          NOTRUN -> [ABORT][112] ([Intel XE#9362]) +1 other test abort
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane_lowres@tiling-x:
    - shard-ptl:          NOTRUN -> [SKIP][113] ([Intel XE#5946])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@kms_plane_lowres@tiling-x.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#5020] / [Intel XE#7348])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-9/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5:
    - shard-lnl:          NOTRUN -> [SKIP][115] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-1/igt@kms_plane_scaling@planes-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d:
    - shard-ptl:          NOTRUN -> [SKIP][116] ([Intel XE#6886]) +4 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][117] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-1/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-psr-suspend-resume:
    - shard-lnl:          [PASS][118] -> [FAIL][119] ([Intel XE#8399])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-lnl-2/igt@kms_pm_dc@dc5-psr-suspend-resume.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-4/igt@kms_pm_dc@dc5-psr-suspend-resume.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-lnl:          NOTRUN -> [SKIP][120] ([Intel XE#3309] / [Intel XE#7368])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-2/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-lnl:          NOTRUN -> [SKIP][121] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-ptl:          NOTRUN -> [SKIP][122] ([Intel XE#7304]) +2 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][123] ([Intel XE#1489]) +1 other test skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-1/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          NOTRUN -> [SKIP][124] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][125] ([Intel XE#4608])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][126] ([Intel XE#4608] / [Intel XE#7304])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-a-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][127] ([Intel XE#5858]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-b-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][128] ([Intel XE#5858] / [Intel XE#7304]) +3 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][129] ([Intel XE#2893] / [Intel XE#7304]) +2 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-ptl:          NOTRUN -> [SKIP][130] ([Intel XE#7413])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-7/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr-sprite-render:
    - shard-bmg:          NOTRUN -> [SKIP][131] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-6/igt@kms_psr@fbc-psr-sprite-render.html

  * igt@kms_psr@fbc-psr2-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][132] ([Intel XE#1406] / [Intel XE#7345]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_psr@fbc-psr2-dpms.html

  * igt@kms_psr@fbc-psr2-dpms@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][133] ([Intel XE#1406] / [Intel XE#4609] / [Intel XE#7345]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_psr@fbc-psr2-dpms@edp-1.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff@edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][134] ([Intel XE#1406] / [Intel XE#5835]) +1 other test skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@kms_psr@fbc-psr2-sprite-plane-onoff@edp-1.html

  * igt@kms_psr@pr-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][135] ([Intel XE#1406]) +3 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@kms_psr@pr-dpms.html

  * igt@kms_psr@pr-no-drrs:
    - shard-ptl:          NOTRUN -> [SKIP][136] ([Intel XE#1406]) +3 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@kms_psr@pr-no-drrs.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][137] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][138] ([Intel XE#1127] / [Intel XE#5813])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-ptl:          NOTRUN -> [SKIP][139] ([Intel XE#5813])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-lnl:          NOTRUN -> [SKIP][140] ([Intel XE#1435] / [Intel XE#9142])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-2/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_sharpness_filter@filter-basic:
    - shard-bmg:          NOTRUN -> [SKIP][141] ([Intel XE#6503])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-3/igt@kms_sharpness_filter@filter-basic.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-ptl:          [PASS][142] -> [ABORT][143] ([Intel XE#9375]) +1 other test abort
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-1/igt@kms_vblank@ts-continuation-suspend.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@kms_vblank@ts-continuation-suspend.html

  * igt@xe_compute@ccs-mode-basic:
    - shard-lnl:          NOTRUN -> [SKIP][144] ([Intel XE#1447] / [Intel XE#7471])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-2/igt@xe_compute@ccs-mode-basic.html

  * igt@xe_compute_preempt@compute-preempt-many-vram-evict:
    - shard-ptl:          NOTRUN -> [SKIP][145] ([Intel XE#5191])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@xe_compute_preempt@compute-preempt-many-vram-evict.html
    - shard-lnl:          NOTRUN -> [SKIP][146] ([Intel XE#5191] / [Intel XE#7316] / [Intel XE#7346])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-2/igt@xe_compute_preempt@compute-preempt-many-vram-evict.html

  * igt@xe_cw_post_sync@walker-post-sync:
    - shard-lnl:          NOTRUN -> [SKIP][147] ([Intel XE#8608])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-1/igt@xe_cw_post_sync@walker-post-sync.html

  * igt@xe_evict@evict-beng-large-cm:
    - shard-lnl:          NOTRUN -> [SKIP][148] ([Intel XE#6540] / [Intel XE#688]) +2 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-7/igt@xe_evict@evict-beng-large-cm.html

  * igt@xe_evict@evict-threads-small-multi-vm:
    - shard-ptl:          NOTRUN -> [SKIP][149] ([Intel XE#5764]) +7 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@xe_evict@evict-threads-small-multi-vm.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd:
    - shard-ptl:          NOTRUN -> [SKIP][150] ([Intel XE#6144])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd.html

  * igt@xe_exec_balancer@many-parallel-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][151] ([Intel XE#7482]) +9 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-3/igt@xe_exec_balancer@many-parallel-userptr-invalidate-race.html

  * igt@xe_exec_balancer@no-exec-parallel-userptr-rebind:
    - shard-ptl:          NOTRUN -> [SKIP][152] ([Intel XE#7482]) +20 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@xe_exec_balancer@no-exec-parallel-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][153] ([Intel XE#1392]) +2 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-3/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][154] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-7/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html
    - shard-ptl:          NOTRUN -> [SKIP][155] ([Intel XE#5575] / [Intel XE#7484]) +9 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-2/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][156] ([Intel XE#8374]) +5 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-3/igt@xe_exec_fault_mode@many-execqueues-multi-queue-prefetch.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][157] ([Intel XE#8374]) +1 other test skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-9/igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind-prefetch.html

  * igt@xe_exec_fault_mode@twice-multi-queue-invalid-fault:
    - shard-ptl:          NOTRUN -> [SKIP][158] ([Intel XE#8374]) +6 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@xe_exec_fault_mode@twice-multi-queue-invalid-fault.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-basic:
    - shard-lnl:          NOTRUN -> [SKIP][159] ([Intel XE#8364]) +12 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-4/igt@xe_exec_multi_queue@many-queues-preempt-mode-basic.html

  * igt@xe_exec_multi_queue@one-queue-basic:
    - shard-ptl:          NOTRUN -> [SKIP][160] ([Intel XE#8364]) +20 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-7/igt@xe_exec_multi_queue@one-queue-basic.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-basic-smem:
    - shard-bmg:          NOTRUN -> [SKIP][161] ([Intel XE#8364]) +12 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-1/igt@xe_exec_multi_queue@two-queues-preempt-mode-basic-smem.html

  * igt@xe_exec_reset@multi-queue-close-execqueues:
    - shard-ptl:          NOTRUN -> [SKIP][162] ([Intel XE#8369]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@xe_exec_reset@multi-queue-close-execqueues.html
    - shard-lnl:          NOTRUN -> [SKIP][163] ([Intel XE#8369]) +1 other test skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-7/igt@xe_exec_reset@multi-queue-close-execqueues.html

  * igt@xe_exec_system_allocator@many-stride-new-prefetch:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][164] ([Intel XE#7098] / [Intel XE#8159])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-9/igt@xe_exec_system_allocator@many-stride-new-prefetch.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-multi-vma:
    - shard-ptl:          NOTRUN -> [SKIP][165] ([Intel XE#6196])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-multi-vma.html

  * igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
    - shard-ptl:          [PASS][166] -> [FAIL][167] ([Intel XE#9096])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-2/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-basic:
    - shard-bmg:          NOTRUN -> [SKIP][168] ([Intel XE#8378]) +4 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-10/igt@xe_exec_threads@threads-multi-queue-cm-fd-basic.html

  * igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race:
    - shard-ptl:          NOTRUN -> [SKIP][169] ([Intel XE#8378]) +4 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@xe_exec_threads@threads-multi-queue-cm-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][170] ([Intel XE#8378]) +3 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-7/igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_sriov_init:
    - shard-bmg:          [PASS][171] -> [ABORT][172] ([Intel XE#9463]) +1 other test abort
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-1/igt@xe_fault_injection@inject-fault-probe-function-xe_sriov_init.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-4/igt@xe_fault_injection@inject-fault-probe-function-xe_sriov_init.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-bmg:          NOTRUN -> [SKIP][173] ([Intel XE#2833])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-2/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_mmap@pci-membarrier-parallel:
    - shard-ptl:          NOTRUN -> [SKIP][174] ([Intel XE#5100] / [Intel XE#7408])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-7/igt@xe_mmap@pci-membarrier-parallel.html

  * igt@xe_mmap@vram:
    - shard-lnl:          NOTRUN -> [SKIP][175] ([Intel XE#1416])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-7/igt@xe_mmap@vram.html

  * igt@xe_multigpu_svm@mgpu-coherency-fail-basic:
    - shard-lnl:          NOTRUN -> [SKIP][176] ([Intel XE#6964])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-6/igt@xe_multigpu_svm@mgpu-coherency-fail-basic.html

  * igt@xe_multigpu_svm@mgpu-latency-copy-basic:
    - shard-bmg:          NOTRUN -> [SKIP][177] ([Intel XE#6964])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-8/igt@xe_multigpu_svm@mgpu-latency-copy-basic.html

  * igt@xe_multigpu_svm@mgpu-xgpu-access-prefetch:
    - shard-ptl:          NOTRUN -> [SKIP][178] ([Intel XE#6964]) +3 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@xe_multigpu_svm@mgpu-xgpu-access-prefetch.html

  * igt@xe_page_reclaim@basic-mixed:
    - shard-ptl:          NOTRUN -> [SKIP][179] ([Intel XE#7793])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@xe_page_reclaim@basic-mixed.html
    - shard-lnl:          NOTRUN -> [SKIP][180] ([Intel XE#7793])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-7/igt@xe_page_reclaim@basic-mixed.html

  * igt@xe_page_reclaim@binds-1g-partial:
    - shard-bmg:          NOTRUN -> [SKIP][181] ([Intel XE#7793])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-10/igt@xe_page_reclaim@binds-1g-partial.html

  * igt@xe_pm@s3-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][182] ([Intel XE#584] / [Intel XE#7369]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@xe_pm@s3-basic-exec.html

  * igt@xe_pm@s4-mocs:
    - shard-lnl:          [PASS][183] -> [ABORT][184] ([Intel XE#9362])
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-lnl-5/igt@xe_pm@s4-mocs.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-7/igt@xe_pm@s4-mocs.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-lnl:          [PASS][185] -> [DMESG-WARN][186] ([Intel XE#7727])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-lnl-2/igt@xe_pm@s4-vm-bind-userptr.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-8/igt@xe_pm@s4-vm-bind-userptr.html

  * igt@xe_pmu@all-fn-engine-activity-load:
    - shard-lnl:          NOTRUN -> [SKIP][187] ([Intel XE#4650] / [Intel XE#7347])
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@xe_pmu@all-fn-engine-activity-load.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-ptl:          NOTRUN -> [SKIP][188] ([Intel XE#7599])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_pxp@pxp-termination-key-update-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][189] ([Intel XE#4733] / [Intel XE#7417])
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-8/igt@xe_pxp@pxp-termination-key-update-post-termination-irq.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-ptl:          NOTRUN -> [SKIP][190] ([Intel XE#6019]) +1 other test skip
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@xe_query@multigpu-query-mem-usage.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-lnl:          NOTRUN -> [SKIP][191] ([Intel XE#944]) +1 other test skip
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-1/igt@xe_query@multigpu-query-oa-units.html

  * igt@xe_sriov_admin@bulk-sched-priority-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][192] ([Intel XE#7174])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-7/igt@xe_sriov_admin@bulk-sched-priority-vfs-disabled.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][193] ([Intel XE#4273])
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-5/igt@xe_sriov_flr@flr-vfs-parallel.html

  * igt@xe_wedged@basic-wedged:
    - shard-lnl:          NOTRUN -> [DMESG-WARN][194] ([Intel XE#8963])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-3/igt@xe_wedged@basic-wedged.html

  * igt@xe_wedged@wedged-at-any-timeout:
    - shard-ptl:          NOTRUN -> [DMESG-WARN][195] ([Intel XE#8963])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@xe_wedged@wedged-at-any-timeout.html

  
#### Possible fixes ####

  * igt@kms_bw@linear-tiling-1-displays-target-1920x1080p:
    - shard-bmg:          [SKIP][196] ([Intel XE#367]) -> [PASS][197]
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-3/igt@kms_bw@linear-tiling-1-displays-target-1920x1080p.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-7/igt@kms_bw@linear-tiling-1-displays-target-1920x1080p.html

  * igt@kms_hdmi_audio_bw@audio-bw-hblank80:
    - shard-bmg:          [FAIL][198] ([Intel XE#9313]) -> [PASS][199]
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-6/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-6/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][200] ([Intel XE#1503]) -> [PASS][201]
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-9/igt@kms_hdr@invalid-hdr.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-7/igt@kms_hdr@invalid-hdr.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-ptl:          [ABORT][202] ([Intel XE#9362]) -> [PASS][203] +5 other tests pass
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-8/igt@kms_pm_backlight@fade-with-suspend.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_vrr@flip-dpms@pipe-a-edp-1:
    - shard-ptl:          [FAIL][204] ([Intel XE#4227] / [Intel XE#7397]) -> [PASS][205] +1 other test pass
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-6/igt@kms_vrr@flip-dpms@pipe-a-edp-1.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@kms_vrr@flip-dpms@pipe-a-edp-1.html

  * igt@xe_configfs@ctx-restore-mid-bb-invalid:
    - shard-bmg:          [ABORT][206] ([Intel XE#9463]) -> [PASS][207]
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-4/igt@xe_configfs@ctx-restore-mid-bb-invalid.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-10/igt@xe_configfs@ctx-restore-mid-bb-invalid.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][208] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][209]
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-7/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_module_load@load:
    - shard-ptl:          ([PASS][210], [PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232], [PASS][233], [PASS][234], [SKIP][235]) ([Intel XE#9286]) -> ([PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [PASS][241], [PASS][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248], [PASS][249], [PASS][250], [PASS][251], [PASS][252], [PASS][253], [PASS][254], [PASS][255], [PASS][256], [PASS][257], [PASS][258], [PASS][259], [PASS][260])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-5/igt@xe_module_load@load.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-6/igt@xe_module_load@load.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-7/igt@xe_module_load@load.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-5/igt@xe_module_load@load.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-5/igt@xe_module_load@load.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-3/igt@xe_module_load@load.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-6/igt@xe_module_load@load.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-6/igt@xe_module_load@load.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-1/igt@xe_module_load@load.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-3/igt@xe_module_load@load.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-2/igt@xe_module_load@load.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-4/igt@xe_module_load@load.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-2/igt@xe_module_load@load.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-2/igt@xe_module_load@load.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-1/igt@xe_module_load@load.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-7/igt@xe_module_load@load.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-7/igt@xe_module_load@load.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-4/igt@xe_module_load@load.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-4/igt@xe_module_load@load.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-8/igt@xe_module_load@load.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-8/igt@xe_module_load@load.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-8/igt@xe_module_load@load.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-1/igt@xe_module_load@load.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-8/igt@xe_module_load@load.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-3/igt@xe_module_load@load.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-2/igt@xe_module_load@load.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-2/igt@xe_module_load@load.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@xe_module_load@load.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@xe_module_load@load.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@xe_module_load@load.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@xe_module_load@load.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@xe_module_load@load.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@xe_module_load@load.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@xe_module_load@load.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@xe_module_load@load.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-1/igt@xe_module_load@load.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@xe_module_load@load.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@xe_module_load@load.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-4/igt@xe_module_load@load.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-2/igt@xe_module_load@load.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-2/igt@xe_module_load@load.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@xe_module_load@load.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-8/igt@xe_module_load@load.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-7/igt@xe_module_load@load.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-7/igt@xe_module_load@load.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-7/igt@xe_module_load@load.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@xe_module_load@load.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@xe_module_load@load.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-5/igt@xe_module_load@load.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@xe_module_load@load.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-6/igt@xe_module_load@load.html

  * igt@xe_pm@s4-basic-exec:
    - shard-ptl:          [DMESG-WARN][261] ([Intel XE#7727]) -> [PASS][262]
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-ptl-6/igt@xe_pm@s4-basic-exec.html
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-ptl-3/igt@xe_pm@s4-basic-exec.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-lnl:          [ABORT][263] ([Intel XE#9362]) -> [PASS][264] +1 other test pass
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-lnl-1/igt@xe_pm@s4-vm-bind-unbind-all.html

  
#### Warnings ####

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][265] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][266] ([Intel XE#3544])
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][267] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][268] ([Intel XE#1729] / [Intel XE#7424])
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9138/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1416
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3157]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3157
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
  [Intel XE#5765]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5765
  [Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
  [Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
  [Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
  [Intel XE#5824]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5824
  [Intel XE#5828]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5828
  [Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5845]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5845
  [Intel XE#5846]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5846
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5855]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5855
  [Intel XE#5858]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5858
  [Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
  [Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
  [Intel XE#5917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5917
  [Intel XE#5946]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5946
  [Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
  [Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6144
  [Intel XE#6174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6174
  [Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6925
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7006
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7086]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7086
  [Intel XE#7098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7098
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7227
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7308
  [Intel XE#7312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7312
  [Intel XE#7316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7316
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7346
  [Intel XE#7347]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7347
  [Intel XE#7348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7348
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7368]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7368
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7390
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
  [Intel XE#7471]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7471
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
  [Intel XE#7591]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7591
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7727
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#8159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8159
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8391
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
  [Intel XE#8586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8586
  [Intel XE#8608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8608
  [Intel XE#8680]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8680
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#8963]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8963
  [Intel XE#9009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9009
  [Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
  [Intel XE#9142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9142
  [Intel XE#9144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9144
  [Intel XE#9286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9286
  [Intel XE#9312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9312
  [Intel XE#9313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9313
  [Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
  [Intel XE#9375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9375
  [Intel XE#9387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9387
  [Intel XE#9406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9406
  [Intel XE#9422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9422
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463
  [Intel XE#9537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9537


Build changes
-------------

  * IGT: IGT_9138 -> IGTPW_15966

  IGTPW_15966: 15966
  IGT_9138: 9138
  xe-5912-4f1de47ae94bb8aee6bc1c6105609646d9411650: 4f1de47ae94bb8aee6bc1c6105609646d9411650

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15966/index.html

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