Re: [PATCH v4 3/4] lib/gpgpu_shader: pass surface desription to shaders via inline data

["Grzegorzek, Dominik" <dominik.grzegorzek@intel.com>]

On Mon, 2024-11-25 at 08:31 +0100, Andrzej Hajda wrote:
> Since newer architectures require stateless load/stores we need to pass
> surface description to the shader. Instead of doing it for every call
> we can use inline data which is passed by COMPUTE_WALKER and is stored
> in GRF register r1.
> 
> v4:
>   - moved gpgpu_alloc_gpu_addr changes from next patch here (Dominik),
>   - pass vm_id to intel_allocator (Dominik).
> 
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Looks good to me.

It is:
Reviewed-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> ---
>  lib/gpgpu_shader.c | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
> index 363435e7efd3..52506705e517 100644
> --- a/lib/gpgpu_shader.c
> +++ b/lib/gpgpu_shader.c
> @@ -148,6 +148,16 @@ __xelp_gpgpu_execfunc(struct intel_bb *ibb,
>  		      engine | I915_EXEC_NO_RELOC, false);
>  }
>  
> +static void
> +fill_inline_data(uint32_t *inline_data, uint64_t target_offset, struct intel_buf *target)
> +{
> +	igt_assert(target->surface[0].stride == intel_buf_width(target) * target->bpp/8);
> +	*inline_data++ = lower_32_bits(target_offset);
> +	*inline_data++ = upper_32_bits(target_offset);
> +	*inline_data++ = target->surface[0].stride;
> +	*inline_data++ = intel_buf_height(target);
> +}
> +
>  static void
>  __xehp_gpgpu_execfunc(struct intel_bb *ibb,
>  		      struct intel_buf *target,
> @@ -159,6 +169,7 @@ __xehp_gpgpu_execfunc(struct intel_bb *ibb,
>  	struct xehp_interface_descriptor_data idd;
>  	uint32_t sip_offset;
>  	uint64_t engine;
> +	uint32_t *inline_data;
>  
>  	intel_bb_add_intel_buf(ibb, target, true);
>  
> @@ -186,7 +197,10 @@ __xehp_gpgpu_execfunc(struct intel_bb *ibb,
>  	if (sip_offset)
>  		emit_sip(ibb, sip_offset);
>  
> +	/* Inline data is at 31th/32th dword of COMPUTE_WALKER, BSpec: 67028 */
> +	inline_data = intel_bb_ptr(ibb) + 4 * (shdr->gen_ver < 2000 ? 31 : 32);
>  	xehp_emit_compute_walk(ibb, 0, 0, x_dim * 16, y_dim, &idd, 0x0);
> +	fill_inline_data(inline_data, CANONICAL(target->addr.offset), target);
>  
>  	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
>  	intel_bb_ptr_align(ibb, 32);
> @@ -196,6 +210,17 @@ __xehp_gpgpu_execfunc(struct intel_bb *ibb,
>  		      engine | I915_EXEC_NO_RELOC, false);
>  }
>  
> +static void gpgpu_alloc_gpu_addr(struct intel_bb *ibb, struct intel_buf *target)
> +{
> +	uint64_t ahnd;
> +
> +	ahnd = intel_allocator_open_vm_full(ibb->fd, ibb->vm_id, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> +					 ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> +	target->addr.offset = intel_allocator_alloc(ahnd, target->handle,
> +						    target->surface[0].size, 0);
> +	intel_allocator_close(ahnd);
> +}
> +
>  /**
>   * gpgpu_shader_exec:
>   * @ibb: pointer to initialized intel_bb
> @@ -221,6 +246,9 @@ void gpgpu_shader_exec(struct intel_bb *ibb,
>  	igt_assert(ibb->size >= PAGE_SIZE);
>  	igt_assert(ibb->ptr == ibb->batch);
>  
> +	if (target->addr.offset == INTEL_BUF_INVALID_ADDRESS)
> +		gpgpu_alloc_gpu_addr(ibb, target);
> +
>  	if (shdr->gen_ver >= 1250)
>  		__xehp_gpgpu_execfunc(ibb, target, x_dim, y_dim, shdr, sip,
>  				      ring, explicit_engine);
>