From: "Grzegorzek, Dominik" <dominik.grzegorzek@intel.com>
To: "igt-dev@lists.freedesktop.org" <igt-dev@lists.freedesktop.org>,
"Hajda, Andrzej" <andrzej.hajda@intel.com>
Cc: "Kempczynski, Zbigniew" <zbigniew.kempczynski@intel.com>,
"Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com>,
"Manszewski, Christoph" <christoph.manszewski@intel.com>,
"kamil.konieczny@linux.intel.com"
<kamil.konieczny@linux.intel.com>
Subject: Re: [PATCH v4 4/4] lib/gpgpu_shader: add support for Xe3 platforms
Date: Mon, 25 Nov 2024 14:08:09 +0000 [thread overview]
Message-ID: <7f1698d519d08d158043339681300cee95da2b0e.camel@intel.com> (raw)
In-Reply-To: <20241125-gpgpu_send_rework-v4-4-c16b568a1f3d@intel.com>
On Mon, 2024-11-25 at 08:31 +0100, Andrzej Hajda wrote:
> > Xe3 platforms disallow indirect load/store addressing. Surface descriptor
> > must be passed in 2DBlock payload. Use for it inline data passed from
> > thread dispatcher.
To be clear, mention that system routine is the entity which adds
this constrain.
> >
> > v4:
> > - moved gpgpu_alloc_gpu_addr changes to previous patch (Dominik)
> >
> > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
> > ---
> > lib/iga64_generated_codes.c | 13 ++++++++-----
> > lib/iga64_macros.h | 37 +++++++++++++++++++++++++++++++++----
> > 2 files changed, 41 insertions(+), 9 deletions(-)
> >
> > diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
> > index 04015b0b6d29..a12135e7dbfd 100644
> > --- a/lib/iga64_generated_codes.c
> > +++ b/lib/iga64_generated_codes.c
> > @@ -3,7 +3,7 @@
> >
> > #include "gpgpu_shader.h"
> >
> > -#define MD5_SUM_IGA64_ASMS da66be3cf9bec819a61429de75943011
> > +#define MD5_SUM_IGA64_ASMS 7b1db60d1de46cf35666f2a7f51e8fc2
> >
> > struct iga64_template const iga64_code_gpgpu_fill[] = {
> > { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> > @@ -80,10 +80,11 @@ struct iga64_template const iga64_code_gpgpu_fill[] = {
> > };
> >
> > struct iga64_template const iga64_code_end_system_routine_step_if_eq[] = {
> > - { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> > + { .gen_ver = 2000, .size = 48, .code = (const uint32_t []) {
> > 0x80000966, 0x80018220, 0x02008000, 0x00008000,
> > 0x80000965, 0x80118220, 0x02008010, 0xc0ded000,
> > 0x800c0961, 0x1e054220, 0x00000000, 0x00000000,
> > + 0x80000061, 0x1e554220, 0x00000000, 0x00000000,
> > 0x80000061, 0x1e654220, 0x00000000, 0xc0ded000,
> > 0x80000061, 0x1e754220, 0x00000000, 0x00000003,
> > 0x80032031, 0x1f0c0000, 0xd0061e8c, 0x04000000,
> > @@ -484,13 +485,14 @@ struct iga64_template const iga64_code_media_block_write_aip[] = {
> > };
> >
> > struct iga64_template const iga64_code_common_target_write[] = {
> > - { .gen_ver = 2000, .size = 48, .code = (const uint32_t []) {
> > + { .gen_ver = 2000, .size = 52, .code = (const uint32_t []) {
> > 0x80100061, 0x1f054220, 0x00000000, 0x00000000,
> > 0x80000061, 0x1f054220, 0x00000000, 0xc0ded001,
> > 0x80000061, 0x1f154220, 0x00000000, 0xc0ded002,
> > 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
> > 0x80000061, 0x1f354220, 0x00000000, 0xc0ded004,
> > 0x800c0061, 0x1e054220, 0x00000000, 0x00000000,
> > + 0x80000061, 0x1e554220, 0x00000000, 0x00000000,
> > 0x80000061, 0x1e654220, 0x00000000, 0xc0ded000,
> > 0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
> > 0x80032031, 0x00000000, 0xd00e1e94, 0x04000000,
> > @@ -612,14 +614,15 @@ struct iga64_template const iga64_code_clear_r40[] = {
> > };
> >
> > struct iga64_template const iga64_code_jump_dw_neq[] = {
> > - { .gen_ver = 2000, .size = 32, .code = (const uint32_t []) {
> > + { .gen_ver = 2000, .size = 36, .code = (const uint32_t []) {
> > 0x800c0061, 0x1e054220, 0x00000000, 0x00000000,
> > + 0x80000061, 0x1e554220, 0x00000000, 0x00000000,
> > 0x80000061, 0x1e654220, 0x00000000, 0xc0ded000,
> > 0x80000061, 0x1e754220, 0x00000000, 0x00000003,
> > 0x80032031, 0x1f0c0000, 0xd0061e8c, 0x04000000,
> > 0x80000061, 0x30014220, 0x00000000, 0x00000000,
> > 0x80008070, 0x00018220, 0x22001f04, 0xc0ded001,
> > - 0x84000020, 0x00004000, 0x00000000, 0xffffffa0,
> > + 0x84000020, 0x00004000, 0x00000000, 0xffffff90,
> > 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> > }},
> > { .gen_ver = 1270, .size = 40, .code = (const uint32_t []) {
> > diff --git a/lib/iga64_macros.h b/lib/iga64_macros.h
> > index 40b6338928e1..f82785610207 100644
> > --- a/lib/iga64_macros.h
> > +++ b/lib/iga64_macros.h
> > @@ -21,6 +21,13 @@
> > #define R0_TGIDY r0.6<0;1,0>:ud
> > #define R0_FFTID r0.5<0;1,0>:ud
> >
> > +/* Inline data from COMPUTE_WALKER*, Bspec: 47203, 73584
> > + * Filled by __xe*_gpgpu_execfunc.
> > + */
> > +#define R1_TGT_ADDRESS r1.0<0;1,0>:uq
> > +#define R1_TGT_WIDTH r1.2<0;1,0>:ud
> > +#define R1_TGT_HEIGHT r1.3<0;1,0>:ud
> > +
> > #define SET_SHARED_MEDIA_BLOCK_MSG_HDR(dst, y, width) \
> > (W) mov (8) dst.0<1>:ud 0x0:ud ;\
> > (W) mov (1) dst.1<1>:ud y ;\
> > @@ -35,28 +42,50 @@
> > (W) mov (1) dst.2<1>:ud (width - 1):ud ;\
> > (W) mov (1) dst.4<1>:ud R0_FFTID
> >
> > +#if GEN_VER < 3000
> > +#define SET_SURFACE_DESC(dst) \
> > +(W) mov (8) dst.0<1>:ud 0x0:ud
> > +#else
> > +#define SET_SURFACE_DESC(dst) \
> > +(W) mov (1) dst.0<1>:uq R1_TGT_ADDRESS ;\
> > +(W) add (1) dst.2<1>:ud R1_TGT_WIDTH -1:d ;\
> > +(W) add (1) dst.3<1>:ud R1_TGT_HEIGHT -1:d ;\
> > +(W) add (1) dst.4<1>:ud R1_TGT_WIDTH -1:d
> > +#endif
> > +
> > #define SET_SHARED_MEDIA_A2DBLOCK_PAYLOAD(dst, y, width) \
> > -(W) mov (8) dst.0<1>:ud 0x0:ud ;\
> > -(W) mov (1) dst.6<1>:ud y ;\
> > + SET_SURFACE_DESC(dst) ;\
> > +(W) mov (1) dst.5<1>:ud 0x0:ud ;\
> > +(W) mov (1) dst.6<1>:ud y ;\
> > (W) mov (1) dst.7<1>:ud (width - 1):ud
> >
> > -#define SET_THREAD_MEDIA_A2DBLOCK_PAYLOAD(dst, x, y, width) \
> > -(W) mov (8) dst.0<1>:ud 0x0:ud ;\
> > +#define SET_THREAD_MEDIA_A2DBLOCK_PAYLOAD(dst, x, y, width) \
> > + SET_SURFACE_DESC(dst) ;\
> > (W) shl (1) dst.5<1>:ud R0_TGIDX 0x2:ud ;\
> > (W) add (1) dst.5<1>:ud dst.5<0;1,0>:ud x:ud ;\
> > (W) add (1) dst.6<1>:ud R0_TGIDY y ;\
> > (W) mov (1) dst.7<1>:ud (width - 1):ud ;\
> >
> > #if GEN_VER < 2000
> > +
> > #define SET_SHARED_SPACE_ADDR(dst, y, width) SET_SHARED_MEDIA_BLOCK_MSG_HDR(dst, y, width)
> > #define SET_THREAD_SPACE_ADDR(dst, x, y, width) SET_THREAD_MEDIA_BLOCK_MSG_HDR(dst, x, y, width)
> > #define LOAD_SPACE_DW(dst, src) send.dc1 (1) dst src src1_null 0x0 0x2190000
> > #define STORE_SPACE_DW(dst, src) send.dc1 (1) null dst null 0x0 0x40A8000
> > +
> > #else
> > +
> > #define SET_SHARED_SPACE_ADDR(dst, y, width) SET_SHARED_MEDIA_A2DBLOCK_PAYLOAD(dst, y, width)
> > #define SET_THREAD_SPACE_ADDR(dst, x, y, width) SET_THREAD_MEDIA_A2DBLOCK_PAYLOAD(dst, x, y, width)
> > +
nit: comparing to other definitions these 4 newlines looks extra. Keep styling same.
Reviewed-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Patch no longer applies. I've tested it by reseting few top commits, so probably this needs resend
anyway.
Regards,
Dominik
> > +#if GEN_VER < 3000
> > #define LOAD_SPACE_DW(dst, src) send.tgm (1) dst src null:0 0x0 0x62100003
> > #define STORE_SPACE_DW(dst, src) send.tgm (1) null dst null:0 0x0 0x64000007
> > +#else
> > +#define LOAD_SPACE_DW(dst, src) send.ugm (1) dst src null:0 0x0 0x2120003
> > +#define STORE_SPACE_DW(dst, src) send.ugm (1) null dst src:1 0x0 0x2020007
> > +#endif
> > +
> > #endif
> >
> > #endif
> >
next prev parent reply other threads:[~2024-11-25 14:08 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-25 7:31 [PATCH v4 0/4] lib/gpgpu_shader: simplify load/store shaders and add Xe3 support Andrzej Hajda
2024-11-25 7:31 ` [PATCH v4 1/4] scripts/generate_iga64_codes: add iga64_macros.h to checksum calculation Andrzej Hajda
2024-11-25 7:31 ` [PATCH v4 2/4] lib/gpgpu_shader: simplify load/store shaders Andrzej Hajda
2024-11-25 7:31 ` [PATCH v4 3/4] lib/gpgpu_shader: pass surface desription to shaders via inline data Andrzej Hajda
2024-11-25 8:50 ` Grzegorzek, Dominik
2024-11-25 7:31 ` [PATCH v4 4/4] lib/gpgpu_shader: add support for Xe3 platforms Andrzej Hajda
2024-11-25 14:08 ` Grzegorzek, Dominik [this message]
2024-11-25 9:19 ` ✓ Xe.CI.BAT: success for lib/gpgpu_shader: simplify load/store shaders and add Xe3 support (rev2) Patchwork
2024-11-25 9:29 ` ✗ i915.CI.BAT: failure " Patchwork
2024-11-25 10:40 ` ✗ Xe.CI.Full: " Patchwork
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