* [PATCH i-g-t 0/2] benchmarks/gem_wsim: Extend engine selection syntax
@ 2024-01-15 15:44 Marcin Bernatowicz
2024-01-15 15:44 ` [PATCH i-g-t 1/2] " Marcin Bernatowicz
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Marcin Bernatowicz @ 2024-01-15 15:44 UTC (permalink / raw)
To: igt-dev
Introduces significant changes to the engine selection syntax:
- Dynamically generates the list of available physical engines.
- Identifies engines using [class:instance:gt] tuples.
- Allows specifying engine instance and gt as
`engine_class[<engine_instance>-<gt_id>]`.
- Adds support for compute engine class (CCS).
- Maintains 1-based engine instance ids for compatibility
with existing workload definitions.
- Enhances `w_step` with `engine_idx`
and `request_idx` for throttling functionality
(both populated during prepare workload phase).
Adds command line option (-l) to list physical engines.
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Marcin Bernatowicz (2):
benchmarks/gem_wsim: Extend engine selection syntax
benchmarks/gem_wsim: Option to list physical engines
benchmarks/gem_wsim.c | 831 ++++++++++++++++++++++--------------------
1 file changed, 444 insertions(+), 387 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH i-g-t 1/2] benchmarks/gem_wsim: Extend engine selection syntax
2024-01-15 15:44 [PATCH i-g-t 0/2] benchmarks/gem_wsim: Extend engine selection syntax Marcin Bernatowicz
@ 2024-01-15 15:44 ` Marcin Bernatowicz
2024-01-24 11:41 ` Laguna, Lukasz
2024-01-24 12:24 ` Tvrtko Ursulin
2024-01-15 15:44 ` [PATCH i-g-t 2/2] benchmarks/gem_wsim: Option to list physical engines Marcin Bernatowicz
` (3 subsequent siblings)
4 siblings, 2 replies; 11+ messages in thread
From: Marcin Bernatowicz @ 2024-01-15 15:44 UTC (permalink / raw)
To: igt-dev
This commit introduces significant changes to the engine selection
syntax:
- Dynamically generates the list of available physical engines by
querying the device.
- Identifies engines using [class:instance:gt] tuples.
- Allows specifying engine instance and gt as
`engine_class[<engine_instance>-<gt_id>]`
ex. First VCS engine may be specified as VCS, VCS1, and VCS1-0.
- Adds support for compute engine class (CCS).
- Maintains 1-based engine instance ids for compatibility with existing
workload definitions.
- Each `w_step` now includes an `engine_idx` (populated during prepare
workload phase), simplifying the run phase with an index in the
device/context engine map.
Second index field `request_idx` was introduced to support throttling
functionality, enabling control over the rate of requests on a given
engine.
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
---
benchmarks/gem_wsim.c | 788 +++++++++++++++++++++---------------------
1 file changed, 402 insertions(+), 386 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 955b6799e..e79d26513 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -68,17 +68,6 @@
#include "xe/xe_ioctl.h"
#include "xe/xe_spin.h"
-enum intel_engine_id {
- DEFAULT,
- RCS,
- BCS,
- VCS,
- VCS1,
- VCS2,
- VECS,
- NUM_ENGINES
-};
-
struct duration {
unsigned int min, max;
bool unbound;
@@ -126,9 +115,16 @@ struct w_arg {
bool sseu;
};
+typedef struct drm_xe_engine_class_instance intel_engine_t;
+
+struct intel_engines {
+ unsigned int nr_engines;
+ intel_engine_t *engines;
+};
+
struct bond {
- uint64_t mask;
- enum intel_engine_id master;
+ struct intel_engines mask;
+ intel_engine_t master;
};
struct work_buffer_size {
@@ -153,7 +149,8 @@ struct w_step {
/* Workload step metadata */
enum w_type type;
unsigned int context;
- unsigned int engine;
+ unsigned int engine_idx;
+ intel_engine_t engine;
struct duration duration;
struct deps data_deps;
struct deps fence_deps;
@@ -165,15 +162,9 @@ struct w_step {
int target;
int throttle;
int priority;
- struct {
- unsigned int engine_map_count;
- enum intel_engine_id *engine_map;
- };
+ struct intel_engines engine_map;
bool load_balance;
- struct {
- uint64_t bond_mask;
- enum intel_engine_id bond_master;
- };
+ struct bond bond;
int sseu;
struct working_set working_set;
};
@@ -181,7 +172,7 @@ struct w_step {
/* Implementation details */
unsigned int idx;
struct igt_list_head rq_link;
- unsigned int request;
+ unsigned int request_idx;
unsigned int preempt_us;
union {
@@ -220,8 +211,7 @@ struct xe_exec_queue {
struct ctx {
uint32_t id;
int priority;
- unsigned int engine_map_count;
- enum intel_engine_id *engine_map;
+ struct intel_engines engine_map;
unsigned int bond_count;
struct bond *bonds;
bool load_balance;
@@ -267,8 +257,8 @@ struct workload {
int sync_timeline;
uint32_t sync_seqno;
- struct igt_list_head requests[NUM_ENGINES];
- unsigned int nrequest[NUM_ENGINES];
+ struct igt_list_head *requests;
+ unsigned int *nrequest;
};
#define __for_each_ctx(__ctx, __wrk, __ctx_idx) \
@@ -296,16 +286,44 @@ static struct drm_i915_gem_context_param_sseu device_sseu = {
#define FLAG_DEPSYNC (1<<2)
#define FLAG_SSEU (1<<3)
-static const char *ring_str_map[NUM_ENGINES] = {
- [DEFAULT] = "DEFAULT",
- [RCS] = "RCS",
- [BCS] = "BCS",
- [VCS] = "VCS",
- [VCS1] = "VCS1",
- [VCS2] = "VCS2",
- [VECS] = "VECS",
+enum intel_engine_class {
+ RCS,
+ BCS,
+ VCS,
+ VECS,
+ CCS,
+ NUM_ENGINE_CLASSES,
};
+_Static_assert(RCS == DRM_XE_ENGINE_CLASS_RENDER, "mismatch");
+_Static_assert(BCS == DRM_XE_ENGINE_CLASS_COPY, "mismatch");
+_Static_assert(VCS == DRM_XE_ENGINE_CLASS_VIDEO_DECODE, "mismatch");
+_Static_assert(VECS == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE, "mismatch");
+_Static_assert(CCS == DRM_XE_ENGINE_CLASS_COMPUTE, "mismatch");
+_Static_assert((int)RCS == (int)I915_ENGINE_CLASS_RENDER, "mismatch");
+_Static_assert((int)BCS == (int)I915_ENGINE_CLASS_COPY, "mismatch");
+_Static_assert((int)VCS == (int)I915_ENGINE_CLASS_VIDEO, "mismatch");
+_Static_assert((int)VECS == (int)I915_ENGINE_CLASS_VIDEO_ENHANCE, "mismatch");
+_Static_assert((int)CCS == (int)I915_ENGINE_CLASS_COMPUTE, "mismatch");
+
+static const char *intel_engine_class_string(uint16_t engine_class)
+{
+ switch (engine_class) {
+ case RCS:
+ return "RCS";
+ case BCS:
+ return "BCS";
+ case VCS:
+ return "VCS";
+ case VECS:
+ return "VECS";
+ case CCS:
+ return "CCS";
+ default:
+ igt_assert(0);
+ }
+}
+
static void w_step_sync(struct w_step *w)
{
if (is_xe)
@@ -521,218 +539,261 @@ out:
} \
}
-static int str_to_engine(const char *str)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(ring_str_map); i++) {
- if (!strcasecmp(str, ring_str_map[i]))
- return i;
- }
-
- return -1;
-}
+#define INVALID_ID ((uint16_t)-2)
+#define DEFAULT_ID ((uint16_t)-1)
-static struct intel_engine_data *query_engines(void)
+static struct intel_engines *query_engines(void)
{
- static struct intel_engine_data engines = {};
+ static struct intel_engines engines = {};
- if (engines.nengines)
+ if (engines.nr_engines)
return &engines;
if (is_xe) {
struct drm_xe_engine_class_instance *hwe;
- xe_for_each_engine(fd, hwe) {
- engines.engines[engines.nengines].class = hwe->engine_class;
- engines.engines[engines.nengines].instance = hwe->engine_instance;
- engines.nengines++;
+ engines.engines = calloc(xe_number_engines(fd), sizeof(intel_engine_t));
+ igt_assert(engines.engines);
+ engines.nr_engines = 0;
+ xe_for_each_engine(fd, hwe)
+ engines.engines[engines.nr_engines++] = *hwe;
+ igt_assert(engines.nr_engines);
+ } else {
+ struct intel_engine_data ed = {};
+
+ ed = intel_engine_list_of_physical(fd);
+ igt_assert(ed.nengines);
+ engines.nr_engines = ed.nengines;
+ engines.engines = calloc(engines.nr_engines, sizeof(intel_engine_t));
+ igt_assert(engines.engines);
+ for (int i = 0; i < ed.nengines; ++i) {
+ engines.engines[i].engine_class = ed.engines[i].class;
+ engines.engines[i].engine_instance = ed.engines[i].instance;
+ engines.engines[i].gt_id = DEFAULT_ID;
}
- } else
- engines = intel_engine_list_of_physical(fd);
+ }
- igt_assert(engines.nengines);
return &engines;
}
-static unsigned int num_engines_in_class(enum intel_engine_id class)
-{
- const struct intel_engine_data *engines = query_engines();
- unsigned int i, count = 0;
+/* engine_class[<engine_instance>-<gt_id>] */
+static intel_engine_t str_to_engine(const char *str)
+{
+ intel_engine_t e = {INVALID_ID, DEFAULT_ID, DEFAULT_ID};
+ size_t pos;
+
+ if (!strcasecmp("DEFAULT", str)) {
+ e.engine_class = DEFAULT_ID;
+ return e;
+ } else if (!strncasecmp("RCS", str, 3)) {
+ e.engine_class = RCS;
+ pos = 3;
+ } else if (!strncasecmp("BCS", str, 3)) {
+ e.engine_class = BCS;
+ pos = 3;
+ } else if (!strncasecmp("VCS", str, 3)) {
+ e.engine_class = VCS;
+ pos = 3;
+ } else if (!strncasecmp("VECS", str, 4)) {
+ e.engine_class = VECS;
+ pos = 4;
+ } else if (!strncasecmp("CCS", str, 3)) {
+ e.engine_class = CCS;
+ pos = 3;
+ } else
+ return (intel_engine_t){INVALID_ID};
+
+ if (str[pos]) {
+ char *s = strchr(&str[pos], '-');
+ char *endptr = NULL;
+ long id;
+
+ if (!s || (s && *s != str[pos])) {
+ id = strtol(&str[pos], &endptr, 10);
+ if (endptr == &str[pos] || id < 1 || id >= INVALID_ID)
+ return (intel_engine_t){INVALID_ID};
+ e.engine_instance = id - 1;
+ }
- igt_assert(class == VCS);
+ if (s && *(++s)) {
+ id = strtol(s, &endptr, 10);
+ if (endptr == s || id < 0 || id >= INVALID_ID)
+ return (intel_engine_t){INVALID_ID};
+ e.gt_id = id;
+ }
- for (i = 0; i < engines->nengines; i++) {
- if (engines->engines[i].class == I915_ENGINE_CLASS_VIDEO)
- count++;
+ if (endptr && endptr != (str + strlen(str)))
+ return (intel_engine_t){INVALID_ID};
}
- igt_assert(count);
- return count;
+ return e;
}
-static void
-fill_engines_id_class(enum intel_engine_id *list,
- enum intel_engine_id class)
+static bool is_valid_engine(const intel_engine_t *engine)
{
- const struct intel_engine_data *engines = query_engines();
- enum intel_engine_id engine = VCS1;
- unsigned int i, j = 0;
-
- igt_assert(class == VCS);
- igt_assert(num_engines_in_class(VCS) <= 2);
-
- for (i = 0; i < engines->nengines; i++) {
- if (engines->engines[i].class != I915_ENGINE_CLASS_VIDEO)
- continue;
-
- list[j++] = engine++;
- }
+ return engine->engine_class != INVALID_ID;
}
-static unsigned int
-find_physical_instance(enum intel_engine_id class, unsigned int logical)
+static bool is_default_engine(const intel_engine_t *engine)
{
- const struct intel_engine_data *engines = query_engines();
- unsigned int i, j = 0;
-
- igt_assert(class == VCS);
-
- for (i = 0; i < engines->nengines; i++) {
- if (engines->engines[i].class != I915_ENGINE_CLASS_VIDEO)
- continue;
-
- /* Map logical to physical instances. */
- if (logical == j++)
- return engines->engines[i].instance;
- }
-
- igt_assert(0);
- return 0;
+ return engine->engine_class == DEFAULT_ID &&
+ engine->engine_instance == DEFAULT_ID &&
+ engine->gt_id == DEFAULT_ID;
}
-static struct i915_engine_class_instance
-get_engine(enum intel_engine_id engine)
+static struct i915_engine_class_instance to_i915_engine_class(const intel_engine_t *engine)
{
- struct i915_engine_class_instance ci;
-
- query_engines();
+ return (struct i915_engine_class_instance){engine->engine_class, engine->engine_instance};
+}
- switch (engine) {
+static unsigned int to_i915_legacy_ring(const intel_engine_t *engine)
+{
+ switch (engine->engine_class) {
+ case DEFAULT_ID:
+ return I915_EXEC_DEFAULT;
case RCS:
- ci.engine_class = I915_ENGINE_CLASS_RENDER;
- ci.engine_instance = 0;
- break;
+ return I915_EXEC_RENDER;
case BCS:
- ci.engine_class = I915_ENGINE_CLASS_COPY;
- ci.engine_instance = 0;
- break;
- case VCS1:
- case VCS2:
- ci.engine_class = I915_ENGINE_CLASS_VIDEO;
- ci.engine_instance = find_physical_instance(VCS, engine - VCS1);
+ return I915_EXEC_BLT;
+ case VCS:
+ if (engine->engine_instance == DEFAULT_ID)
+ return I915_EXEC_BSD;
+ else if (engine->engine_instance == 0)
+ return I915_EXEC_BSD | I915_EXEC_BSD_RING1;
+ else if (engine->engine_instance == 1)
+ return I915_EXEC_BSD | I915_EXEC_BSD_RING2;
break;
case VECS:
- ci.engine_class = I915_ENGINE_CLASS_VIDEO_ENHANCE;
- ci.engine_instance = 0;
- break;
- default:
- igt_assert(0);
+ return I915_EXEC_VEBOX;
};
- return ci;
+ igt_assert(0);
}
-static struct drm_xe_engine_class_instance
-xe_get_engine(enum intel_engine_id engine)
+static bool are_equal_engines(const intel_engine_t *e1, const intel_engine_t *e2)
{
- struct drm_xe_engine_class_instance hwe = {}, *hwe1;
- bool found_physical = false;
-
- switch (engine) {
- case RCS:
- hwe.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
- break;
- case BCS:
- hwe.engine_class = DRM_XE_ENGINE_CLASS_COPY;
- break;
- case VCS1:
- hwe.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
- break;
- case VCS2:
- hwe.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
- hwe.engine_instance = 1;
- break;
- case VECS:
- hwe.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;
- break;
- default:
- igt_assert(0);
- };
+ return e1->engine_class == e2->engine_class &&
+ e1->engine_instance == e2->engine_instance &&
+ e1->gt_id == e2->gt_id;
+}
- xe_for_each_engine(fd, hwe1) {
- if (hwe.engine_class == hwe1->engine_class &&
- hwe.engine_instance == hwe1->engine_instance) {
- hwe = *hwe1;
- found_physical = true;
- break;
+static bool
+find_engine_in_map(const intel_engine_t *engine, struct intel_engines *engines, unsigned int *idx)
+{
+ igt_assert(idx);
+ for (unsigned int i = 0; i < engines->nr_engines; ++i)
+ if (are_equal_engines(engine, &engines->engines[i])) {
+ *idx = i;
+ return true;
}
- }
- igt_assert(found_physical);
- return hwe;
+ return false;
}
-static struct drm_xe_engine_class_instance
-xe_get_default_engine(void)
+static bool engine_matches_filter(const intel_engine_t *engine, const intel_engine_t *filter)
{
- struct drm_xe_engine_class_instance default_hwe, *hwe;
+ return (filter->engine_class == DEFAULT_ID ||
+ filter->engine_class == engine->engine_class) &&
+ (filter->engine_instance == DEFAULT_ID ||
+ filter->engine_instance == engine->engine_instance) &&
+ (filter->gt_id == DEFAULT_ID ||
+ filter->gt_id == engine->gt_id);
+}
- /* select RCS0 | CCS0 or first available engine */
- default_hwe = xe_engine(fd, 0)->instance;
- xe_for_each_engine(fd, hwe) {
- if ((hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
- hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) &&
- hwe->engine_instance == 0) {
- default_hwe = *hwe;
- break;
- }
+#define for_each_matching_engine(__engine, __filter, __engines) \
+ for (unsigned int __i = 0; __i < __engines->nr_engines && \
+ (__engine = &__engines->engines[__i]); __i++) \
+ for_if(engine_matches_filter(__engine, __filter))
+
+static unsigned int
+append_matching_engines(const intel_engine_t *filter, struct intel_engines *engines)
+{
+ unsigned int prev_nr_engines;
+ struct intel_engines *all = query_engines();
+ intel_engine_t *engine;
+
+ igt_assert(engines);
+ prev_nr_engines = engines->nr_engines;
+
+ for_each_matching_engine(engine, filter, all) {
+ engines->nr_engines++;
+ engines->engines = realloc(engines->engines,
+ engines->nr_engines * sizeof(intel_engine_t));
+ igt_assert(engines->engines);
+ engines->engines[engines->nr_engines - 1] = *engine;
}
- return default_hwe;
+ return engines->nr_engines - prev_nr_engines;
+}
+
+static intel_engine_t get_default_engine(void)
+{
+ struct intel_engines *all_engines = query_engines();
+ const intel_engine_t filters[] = {
+ {RCS, DEFAULT_ID, DEFAULT_ID},
+ {CCS, DEFAULT_ID, DEFAULT_ID},
+ {DEFAULT_ID, DEFAULT_ID, DEFAULT_ID},
+ {INVALID_ID}
+ }, *filter, *default_engine;
+
+ for (filter = filters; is_valid_engine(filter); filter++)
+ for_each_matching_engine(default_engine, filter, all_engines)
+ return *default_engine;
+
+ igt_assert(0);
+}
+
+static intel_engine_t resolve_to_physical_engine_(const intel_engine_t *engine)
+{
+ struct intel_engines *all_engines = query_engines();
+ intel_engine_t *resolved;
+
+ igt_assert(engine);
+ if (is_default_engine(engine))
+ return get_default_engine();
+
+ for_each_matching_engine(resolved, engine, all_engines)
+ return *resolved;
+
+ return (intel_engine_t){INVALID_ID};
+}
+
+static void resolve_to_physical_engine(intel_engine_t *engine)
+{
+ *engine = resolve_to_physical_engine_(engine);
+ igt_assert(is_valid_engine(engine));
}
static int parse_engine_map(struct w_step *step, const char *_str)
{
char *token, *tctx = NULL, *tstart = (char *)_str;
+ intel_engine_t engine;
while ((token = strtok_r(tstart, "|", &tctx))) {
- enum intel_engine_id engine;
- unsigned int add;
-
tstart = NULL;
- if (!strcmp(token, "DEFAULT"))
+ engine = str_to_engine(token);
+ if (!is_valid_engine(&engine) || is_default_engine(&engine))
return -1;
- engine = str_to_engine(token);
- if ((int)engine < 0)
+ if (!append_matching_engines(&engine, &step->engine_map))
return -1;
+ }
+
+ return 0;
+}
- if (engine != VCS && engine != VCS1 && engine != VCS2 &&
- engine != RCS)
- return -1; /* TODO */
+static int parse_bond_engines(struct w_step *step, const char *_str)
+{
+ char *token, *tctx = NULL, *tstart = (char *)_str;
+ intel_engine_t engine;
- add = engine == VCS ? num_engines_in_class(VCS) : 1;
- step->engine_map_count += add;
- step->engine_map = realloc(step->engine_map,
- step->engine_map_count *
- sizeof(step->engine_map[0]));
+ while ((token = strtok_r(tstart, "|", &tctx))) {
+ tstart = NULL;
- if (engine != VCS)
- step->engine_map[step->engine_map_count - add] = engine;
- else
- fill_engines_id_class(&step->engine_map[step->engine_map_count - add], VCS);
+ engine = str_to_engine(token);
+ if (append_matching_engines(&engine, &step->bond.mask) != 1)
+ return -1;
}
return 0;
@@ -854,26 +915,6 @@ static int parse_working_set(struct working_set *set, char *str)
return 0;
}
-static uint64_t engine_list_mask(const char *_str)
-{
- uint64_t mask = 0;
-
- char *token, *tctx = NULL, *tstart = (char *)_str;
-
- while ((token = strtok_r(tstart, "|", &tctx))) {
- enum intel_engine_id engine = str_to_engine(token);
-
- if ((int)engine < 0 || engine == DEFAULT || engine == VCS)
- return 0;
-
- mask |= 1 << engine;
-
- tstart = NULL;
- }
-
- return mask;
-}
-
static unsigned long
allocate_working_set(struct workload *wrk, struct working_set *set);
@@ -1145,18 +1186,19 @@ parse_workload(struct w_arg *arg, unsigned int flags, double scale_dur,
"Invalid context at step %u!\n",
nr_steps);
} else if (nr == 1) {
- step.bond_mask = engine_list_mask(field);
- check_arg(step.bond_mask == 0,
- "Invalid siblings list at step %u!\n",
- nr_steps);
+ tmp = parse_bond_engines(&step, field);
+ check_arg(tmp < 0,
+ "Invalid siblings list at step %u!\n",
+ nr_steps);
} else if (nr == 2) {
- tmp = str_to_engine(field);
- check_arg(tmp <= 0 ||
- tmp == VCS ||
- tmp == DEFAULT,
+ struct intel_engines engines;
+
+ step.bond.master = str_to_engine(field);
+ check_arg(append_matching_engines(&step.bond.master,
+ &engines) != 1,
"Invalid master engine at step %u!\n",
nr_steps);
- step.bond_master = tmp;
+ free(engines.engines);
}
nr++;
@@ -1214,13 +1256,11 @@ parse_workload(struct w_arg *arg, unsigned int flags, double scale_dur,
if (field) {
fstart = NULL;
- i = str_to_engine(field);
- check_arg(i < 0,
+ step.engine = str_to_engine(field);
+ check_arg(!is_valid_engine(&step.engine),
"Invalid engine id at step %u!\n", nr_steps);
valid++;
-
- step.engine = i;
}
field = strtok_r(fstart, ".", &fctx);
@@ -1266,7 +1306,7 @@ add_step:
step.delay = __duration(step.delay, scale_time);
step.idx = nr_steps++;
- step.request = -1;
+ step.rq_link.next = step.rq_link.prev = NULL;
steps = realloc(steps, sizeof(step) * nr_steps);
igt_assert(steps);
@@ -1386,9 +1426,9 @@ add_step:
static struct workload *
clone_workload(struct workload *_wrk)
{
+ int nr_engines = query_engines()->nr_engines;
struct workload *wrk;
struct w_step *w;
- int i;
wrk = malloc(sizeof(*wrk));
igt_assert(wrk);
@@ -1423,8 +1463,12 @@ clone_workload(struct workload *_wrk)
}
}
- for (i = 0; i < NUM_ENGINES; i++)
- IGT_INIT_LIST_HEAD(&wrk->requests[i]);
+ wrk->requests = calloc(nr_engines, sizeof(*wrk->requests));
+ igt_assert(wrk->requests);
+ wrk->nrequest = calloc(nr_engines, sizeof(*wrk->nrequest));
+ igt_assert(wrk->nrequest);
+ while (--nr_engines >= 0)
+ IGT_INIT_LIST_HEAD(&wrk->requests[nr_engines]);
return wrk;
}
@@ -1451,37 +1495,32 @@ __get_ctx(struct workload *wrk, const struct w_step *w)
return &wrk->ctx_list[w->context];
}
-static uint32_t mmio_base(int i915, enum intel_engine_id engine, int gen)
+static uint32_t mmio_base(int i915, const intel_engine_t *engine, int gen)
{
- const char *name;
+ char name[16];
if (gen >= 11)
return 0;
- switch (engine) {
- case NUM_ENGINES:
+ switch (engine->engine_class) {
default:
return 0;
- case DEFAULT:
+ case DEFAULT_ID:
case RCS:
- name = "rcs0";
+ snprintf(name, sizeof(name), "rcs%u", engine->engine_instance);
break;
-
case BCS:
- name = "bcs0";
+ snprintf(name, sizeof(name), "bcs%u", engine->engine_instance);
break;
-
case VCS:
- case VCS1:
- name = "vcs0";
- break;
- case VCS2:
- name = "vcs1";
+ snprintf(name, sizeof(name), "vcs%u", engine->engine_instance);
break;
-
case VECS:
- name = "vecs0";
+ snprintf(name, sizeof(name), "vecs%u", engine->engine_instance);
+ break;
+ case CCS:
+ snprintf(name, sizeof(name), "ccs%u", engine->engine_instance);
break;
}
@@ -1491,7 +1530,7 @@ static uint32_t mmio_base(int i915, enum intel_engine_id engine, int gen)
static unsigned int create_bb(struct w_step *w, int self)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
- const uint32_t base = mmio_base(fd, w->engine, gen);
+ const uint32_t base = mmio_base(fd, &w->engine, gen);
#define CS_GPR(x) (base + 0x600 + 8 * (x))
#define TIMESTAMP (base + 0x3a8)
const int use_64b = gen >= 8;
@@ -1574,47 +1613,10 @@ static unsigned int create_bb(struct w_step *w, int self)
return r;
}
-static const unsigned int eb_engine_map[NUM_ENGINES] = {
- [DEFAULT] = I915_EXEC_DEFAULT,
- [RCS] = I915_EXEC_RENDER,
- [BCS] = I915_EXEC_BLT,
- [VCS] = I915_EXEC_BSD,
- [VCS1] = I915_EXEC_BSD | I915_EXEC_BSD_RING1,
- [VCS2] = I915_EXEC_BSD | I915_EXEC_BSD_RING2,
- [VECS] = I915_EXEC_VEBOX
-};
-
static void
-eb_set_engine(struct drm_i915_gem_execbuffer2 *eb, enum intel_engine_id engine)
+eb_update_flags(struct workload *wrk, struct w_step *w)
{
- eb->flags = eb_engine_map[engine];
-}
-
-static unsigned int
-find_engine_in_map(struct ctx *ctx, enum intel_engine_id engine)
-{
- unsigned int i;
-
- for (i = 0; i < ctx->engine_map_count; i++) {
- if (ctx->engine_map[i] == engine)
- return i + 1;
- }
-
- igt_assert(ctx->load_balance);
- return 0;
-}
-
-static void
-eb_update_flags(struct workload *wrk, struct w_step *w,
- enum intel_engine_id engine)
-{
- struct ctx *ctx = __get_ctx(wrk, w);
-
- if (ctx->engine_map)
- w->i915.eb.flags = find_engine_in_map(ctx, engine);
- else
- eb_set_engine(&w->i915.eb, engine);
-
+ w->i915.eb.flags = w->engine_idx;
w->i915.eb.flags |= I915_EXEC_HANDLE_LUT;
w->i915.eb.flags |= I915_EXEC_NO_RELOC;
@@ -1633,19 +1635,9 @@ static struct xe_exec_queue *
xe_get_eq(struct workload *wrk, const struct w_step *w)
{
struct ctx *ctx = __get_ctx(wrk, w);
- struct xe_exec_queue *eq;
- if (ctx->engine_map) {
- igt_assert_eq(ctx->xe.nr_queues, 1);
- igt_assert(ctx->xe.queue_list[0].id);
- eq = &ctx->xe.queue_list[0];
- } else {
- igt_assert(w->engine >= 0 && w->engine < ctx->xe.nr_queues);
- igt_assert(ctx->xe.queue_list[w->engine].id);
- eq = &ctx->xe.queue_list[w->engine];
- }
-
- return eq;
+ igt_assert_lt(w->engine_idx, ctx->xe.nr_queues);
+ return &ctx->xe.queue_list[w->engine_idx];
}
static struct xe_vm *
@@ -1669,7 +1661,6 @@ static uint32_t alloc_bo(int i915, unsigned long *size)
static void
alloc_step_batch(struct workload *wrk, struct w_step *w)
{
- enum intel_engine_id engine = w->engine;
struct dep_entry *dep;
unsigned int j = 0;
unsigned int nr_obj = 2 + w->data_deps.nr;
@@ -1724,7 +1715,7 @@ alloc_step_batch(struct workload *wrk, struct w_step *w)
w->i915.eb.buffer_count = j + 1;
w->i915.eb.rsvd1 = get_ctxid(wrk, w);
- eb_update_flags(wrk, w, engine);
+ eb_update_flags(wrk, w);
#ifdef DEBUG
printf("%u: %u:|", w->idx, w->i915.eb.buffer_count);
for (i = 0; i <= j; i++)
@@ -1853,22 +1844,6 @@ static void vm_destroy(int i915, uint32_t vm_id)
igt_assert_eq(__vm_destroy(i915, vm_id), 0);
}
-static unsigned int
-find_engine(struct i915_engine_class_instance *ci, unsigned int count,
- enum intel_engine_id engine)
-{
- struct i915_engine_class_instance e = get_engine(engine);
- unsigned int i;
-
- for (i = 0; i < count; i++, ci++) {
- if (!memcmp(&e, ci, sizeof(*ci)))
- return i;
- }
-
- igt_assert(0);
- return 0;
-}
-
static struct drm_i915_gem_context_param_sseu get_device_sseu(void)
{
struct drm_i915_gem_context_param param = { };
@@ -1892,7 +1867,7 @@ set_ctx_sseu(struct ctx *ctx, uint64_t slice_mask)
if (slice_mask == -1)
slice_mask = device_sseu.slice_mask;
- if (ctx->engine_map && ctx->load_balance) {
+ if (ctx->engine_map.nr_engines && ctx->load_balance) {
sseu.flags = I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX;
sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID;
sseu.engine.engine_instance = 0;
@@ -2102,9 +2077,8 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
if (w->type == ENGINE_MAP) {
ctx->engine_map = w->engine_map;
- ctx->engine_map_count = w->engine_map_count;
} else if (w->type == LOAD_BALANCE) {
- if (!ctx->engine_map) {
+ if (!ctx->engine_map.nr_engines) {
wsim_err("Load balancing needs an engine map!\n");
return 1;
}
@@ -2123,10 +2097,7 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
ctx->bond_count *
sizeof(struct bond));
igt_assert(ctx->bonds);
- ctx->bonds[ctx->bond_count - 1].mask =
- w->bond_mask;
- ctx->bonds[ctx->bond_count - 1].master =
- w->bond_master;
+ ctx->bonds[ctx->bond_count - 1] = w->bond;
}
}
}
@@ -2134,7 +2105,7 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
/*
* Create and configure contexts.
*/
- for_each_ctx(ctx, wrk) {
+ __for_each_ctx(ctx, wrk, ctx_idx) {
struct drm_i915_gem_context_create_ext_setparam ext = {
.base.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
.param.param = I915_CONTEXT_PARAM_VM,
@@ -2176,19 +2147,40 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
__configure_context(ctx_id, wrk->prio);
- if (ctx->engine_map) {
+ if (ctx->engine_map.nr_engines) {
struct i915_context_param_engines *set_engines =
- alloca0(sizeof_param_engines(ctx->engine_map_count + 1));
+ alloca0(sizeof_param_engines(ctx->engine_map.nr_engines + 1));
struct i915_context_engines_load_balance *load_balance =
- alloca0(sizeof_load_balance(ctx->engine_map_count));
+ alloca0(sizeof_load_balance(ctx->engine_map.nr_engines));
struct drm_i915_gem_context_param param = {
.ctx_id = ctx_id,
.param = I915_CONTEXT_PARAM_ENGINES,
- .size = sizeof_param_engines(ctx->engine_map_count + 1),
+ .size = sizeof_param_engines(ctx->engine_map.nr_engines + 1),
.value = to_user_pointer(set_engines),
};
struct i915_context_engines_bond *last = NULL;
+ /* update engine_idx and request_idx */
+ for_each_w_step(w, wrk) {
+ if (w->context != ctx_idx)
+ continue;
+ if (w->type == BATCH) {
+ unsigned int map_idx = 0;
+
+ if (find_engine_in_map(&w->engine, &ctx->engine_map,
+ &map_idx))
+ /* 0 is virtual, map indexes are shifted by one */
+ w->engine_idx = map_idx + 1;
+ else
+ igt_assert(ctx->load_balance);
+
+ igt_assert(find_engine_in_map(
+ &ctx->engine_map.engines[map_idx],
+ query_engines(),
+ &w->request_idx));
+ }
+ }
+
if (ctx->load_balance) {
set_engines->extensions =
to_user_pointer(load_balance);
@@ -2196,11 +2188,11 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
load_balance->base.name =
I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
load_balance->num_siblings =
- ctx->engine_map_count;
+ ctx->engine_map.nr_engines;
- for (j = 0; j < ctx->engine_map_count; j++)
+ for (j = 0; j < ctx->engine_map.nr_engines; j++)
load_balance->engines[j] =
- get_engine(ctx->engine_map[j]);
+ to_i915_engine_class(&ctx->engine_map.engines[j]);
}
/* Reserve slot for virtual engine. */
@@ -2209,34 +2201,31 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
set_engines->engines[0].engine_instance =
I915_ENGINE_CLASS_INVALID_NONE;
- for (j = 1; j <= ctx->engine_map_count; j++)
+ for (j = 1; j <= ctx->engine_map.nr_engines; j++)
set_engines->engines[j] =
- get_engine(ctx->engine_map[j - 1]);
+ to_i915_engine_class(&ctx->engine_map.engines[j - 1]);
last = NULL;
for (j = 0; j < ctx->bond_count; j++) {
- unsigned long mask = ctx->bonds[j].mask;
+ struct intel_engines *mask = &ctx->bonds[j].mask;
struct i915_context_engines_bond *bond =
- alloca0(sizeof_engines_bond(__builtin_popcount(mask)));
+ alloca0(sizeof_engines_bond(mask->nr_engines));
unsigned int b, e;
bond->base.next_extension = to_user_pointer(last);
bond->base.name = I915_CONTEXT_ENGINES_EXT_BOND;
bond->virtual_index = 0;
- bond->master = get_engine(ctx->bonds[j].master);
+ bond->master = to_i915_engine_class(&ctx->bonds[j].master);
- for (b = 0, e = 0; mask; e++, mask >>= 1) {
+ for (b = 0, e = 0; e < mask->nr_engines; e++) {
unsigned int idx;
- if (!(mask & 1))
- continue;
+ igt_assert(find_engine_in_map(&mask->engines[e],
+ &ctx->engine_map,
+ &idx));
- idx = find_engine(&set_engines->engines[1],
- ctx->engine_map_count,
- e);
- bond->engines[b++] =
- set_engines->engines[1 + idx];
+ bond->engines[b++] = set_engines->engines[1 + idx];
}
last = bond;
@@ -2244,6 +2233,20 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
load_balance->base.next_extension = to_user_pointer(last);
gem_context_set_param(fd, ¶m);
+ } else {
+ /* update engine_idx and request_idx */
+ for_each_w_step(w, wrk) {
+ if (w->context != ctx_idx)
+ continue;
+ if (w->type == BATCH) {
+ w->engine_idx = to_i915_legacy_ring(&w->engine);
+ resolve_to_physical_engine(&w->engine);
+ igt_assert(find_engine_in_map(
+ &w->engine,
+ query_engines(),
+ &w->request_idx));
+ }
+ }
}
if (wrk->sseu) {
@@ -2281,9 +2284,8 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
continue;
if (w->type == ENGINE_MAP) {
ctx->engine_map = w->engine_map;
- ctx->engine_map_count = w->engine_map_count;
} else if (w->type == LOAD_BALANCE) {
- if (!ctx->engine_map) {
+ if (!ctx->engine_map.nr_engines) {
wsim_err("Load balancing needs an engine map!\n");
return 1;
}
@@ -2292,15 +2294,15 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
}
/* create exec queue for each referenced engine */
- if (ctx->engine_map) {
+ if (ctx->engine_map.nr_engines) {
ctx->xe.nr_queues = 1;
ctx->xe.queue_list = calloc(ctx->xe.nr_queues, sizeof(*ctx->xe.queue_list));
igt_assert(ctx->xe.queue_list);
eq = &ctx->xe.queue_list[ctx->xe.nr_queues - 1];
- eq->nr_hwes = ctx->engine_map_count;
+ eq->nr_hwes = ctx->engine_map.nr_engines;
eq->hwe_list = calloc(eq->nr_hwes, sizeof(*eq->hwe_list));
for (i = 0; i < eq->nr_hwes; ++i) {
- eq->hwe_list[i] = xe_get_engine(ctx->engine_map[i]);
+ eq->hwe_list[i] = ctx->engine_map.engines[i];
/* check no mixing classes and no duplicates */
for (int j = 0; j < i; ++j) {
@@ -2322,8 +2324,10 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
}
if (verbose > 3)
- printf("%u ctx[%d] %s [%u:%u:%u]\n",
- id, ctx_idx, ring_str_map[ctx->engine_map[i]],
+ printf("%u ctx[%d] %s [%d:%d:%d]\n",
+ id, ctx_idx,
+ intel_engine_class_string(
+ ctx->engine_map.engines[i].engine_class),
eq->hwe_list[i].engine_class,
eq->hwe_list[i].engine_instance,
eq->hwe_list[i].gt_id);
@@ -2331,41 +2335,56 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
xe_exec_queue_create_(ctx, eq);
} else {
- int engine_classes[NUM_ENGINES] = {};
-
- ctx->xe.nr_queues = NUM_ENGINES;
- ctx->xe.queue_list = calloc(ctx->xe.nr_queues, sizeof(*ctx->xe.queue_list));
-
+ /* create engine_map, update engine_idx */
for_each_w_step(w, wrk) {
if (w->context != ctx_idx)
continue;
- if (w->type == BATCH)
- engine_classes[w->engine]++;
+ if (w->type == BATCH) {
+ resolve_to_physical_engine(&w->engine);
+ if (!find_engine_in_map(&w->engine, &ctx->engine_map,
+ &w->engine_idx)) {
+ igt_assert_eq(1, append_matching_engines(&w->engine,
+ &ctx->engine_map));
+ w->engine_idx = ctx->engine_map.nr_engines - 1;
+ }
+ }
}
- for (i = 0; i < NUM_ENGINES; i++) {
- if (engine_classes[i]) {
- eq = &ctx->xe.queue_list[i];
- eq->nr_hwes = 1;
- eq->hwe_list = calloc(1, sizeof(*eq->hwe_list));
+ /* skip not referenced context */
+ if (!ctx->engine_map.nr_engines)
+ continue;
- if (i == DEFAULT)
- eq->hwe_list[0] = xe_get_default_engine();
- else if (i == VCS)
- eq->hwe_list[0] = xe_get_engine(VCS1);
- else
- eq->hwe_list[0] = xe_get_engine(i);
+ ctx->xe.nr_queues = ctx->engine_map.nr_engines;
+ ctx->xe.queue_list = calloc(ctx->xe.nr_queues, sizeof(*ctx->xe.queue_list));
- if (verbose > 3)
- printf("%u ctx[%d] %s [%u:%u:%u]\n",
- id, ctx_idx, ring_str_map[i],
- eq->hwe_list[0].engine_class,
- eq->hwe_list[0].engine_instance,
- eq->hwe_list[0].gt_id);
+ for (i = 0; i < ctx->xe.nr_queues; i++) {
+ eq = &ctx->xe.queue_list[i];
+ eq->nr_hwes = 1;
+ eq->hwe_list = calloc(1, sizeof(*eq->hwe_list));
+ eq->hwe_list[0] = ctx->engine_map.engines[i];
- xe_exec_queue_create_(ctx, eq);
- }
- engine_classes[i] = 0;
+ if (verbose > 3)
+ printf("%u ctx[%d] %s [%d:%d:%d]\n",
+ id, ctx_idx,
+ intel_engine_class_string(
+ ctx->engine_map.engines[i].engine_class),
+ eq->hwe_list[0].engine_class,
+ eq->hwe_list[0].engine_instance,
+ eq->hwe_list[0].gt_id);
+
+ xe_exec_queue_create_(ctx, eq);
+ }
+ }
+
+ /* update request_idx */
+ for_each_w_step(w, wrk) {
+ if (w->context != ctx_idx)
+ continue;
+ if (w->type == BATCH) {
+ igt_assert(find_engine_in_map(
+ &ctx->engine_map.engines[w->engine_idx],
+ query_engines(),
+ &w->request_idx));
}
}
}
@@ -2577,12 +2596,12 @@ static void do_xe_exec(struct workload *wrk, struct w_step *w)
}
static void
-do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine)
+do_eb(struct workload *wrk, struct w_step *w)
{
struct dep_entry *dep;
unsigned int i;
- eb_update_flags(wrk, w, engine);
+ eb_update_flags(wrk, w);
update_bb_start(wrk, w);
for_each_dep(dep, w->fence_deps) {
@@ -2656,7 +2675,6 @@ static void *run_workload(void *data)
clock_gettime(CLOCK_MONOTONIC, &repeat_start);
for_each_w_step(w, wrk) {
- enum intel_engine_id engine = w->engine;
int do_sleep = 0;
if (!wrk->run)
@@ -2775,15 +2793,14 @@ static void *run_workload(void *data)
if (is_xe)
do_xe_exec(wrk, w);
else
- do_eb(wrk, w, engine);
+ do_eb(wrk, w);
- if (w->request != -1) {
+ if (w->rq_link.next) {
igt_list_del(&w->rq_link);
- wrk->nrequest[w->request]--;
+ wrk->nrequest[w->request_idx]--;
}
- w->request = engine;
- igt_list_add_tail(&w->rq_link, &wrk->requests[engine]);
- wrk->nrequest[engine]++;
+ igt_list_add_tail(&w->rq_link, &wrk->requests[w->request_idx]);
+ wrk->nrequest[w->request_idx]++;
if (!wrk->run)
break;
@@ -2792,17 +2809,16 @@ static void *run_workload(void *data)
w_step_sync(w);
if (qd_throttle > 0) {
- while (wrk->nrequest[engine] > qd_throttle) {
+ while (wrk->nrequest[w->request_idx] > qd_throttle) {
struct w_step *s;
- s = igt_list_first_entry(&wrk->requests[engine],
+ s = igt_list_first_entry(&wrk->requests[w->request_idx],
s, rq_link);
w_step_sync(s);
- s->request = -1;
igt_list_del(&s->rq_link);
- wrk->nrequest[engine]--;
+ wrk->nrequest[w->request_idx]--;
}
}
}
@@ -2831,7 +2847,7 @@ static void *run_workload(void *data)
}
}
- for (int i = 0; i < NUM_ENGINES; i++) {
+ for (int i = query_engines()->nr_engines; --i >= 0;) {
if (!wrk->nrequest[i])
continue;
--
2.31.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH i-g-t 2/2] benchmarks/gem_wsim: Option to list physical engines
2024-01-15 15:44 [PATCH i-g-t 0/2] benchmarks/gem_wsim: Extend engine selection syntax Marcin Bernatowicz
2024-01-15 15:44 ` [PATCH i-g-t 1/2] " Marcin Bernatowicz
@ 2024-01-15 15:44 ` Marcin Bernatowicz
2024-01-24 11:41 ` Laguna, Lukasz
2024-01-24 12:25 ` Tvrtko Ursulin
2024-01-15 16:54 ` ✓ Fi.CI.BAT: success for benchmarks/gem_wsim: Extend engine selection syntax Patchwork
` (2 subsequent siblings)
4 siblings, 2 replies; 11+ messages in thread
From: Marcin Bernatowicz @ 2024-01-15 15:44 UTC (permalink / raw)
To: igt-dev
Added command line option (-l) to list physical engines.
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
---
benchmarks/gem_wsim.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index e79d26513..aa70b1770 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -2924,6 +2924,7 @@ static void print_help(void)
" -f <scale> Scale factor for batch durations.\n"
" -F <scale> Scale factor for delays.\n"
" -L List GPUs.\n"
+" -l List physical engines.\n"
" -D <gpu> One of the GPUs from -L.\n"
);
}
@@ -2983,10 +2984,42 @@ add_workload_arg(struct w_arg *w_args, unsigned int nr_args, char *w_arg,
return w_args;
}
+static void list_engines(void)
+{
+ struct intel_engines *engines = query_engines();
+ int engine_class_count[NUM_ENGINE_CLASSES] = {};
+ unsigned int i;
+
+ for (i = 0; i < engines->nr_engines; ++i) {
+ igt_assert_lt(engines->engines[i].engine_class, NUM_ENGINE_CLASSES);
+ engine_class_count[engines->engines[i].engine_class]++;
+ }
+
+ for (i = 0; i < engines->nr_engines; ++i) {
+ if (engine_class_count[engines->engines[i].engine_class] > 1)
+ printf("%s%u",
+ intel_engine_class_string(engines->engines[i].engine_class),
+ engines->engines[i].engine_instance + 1);
+ else
+ printf("%s",
+ intel_engine_class_string(engines->engines[i].engine_class));
+
+ if (is_xe && engines->engines[i].gt_id)
+ printf("-%u", engines->engines[i].gt_id);
+
+ if (verbose > 3)
+ printf(" [%d:%d:%d]", engines->engines[i].engine_class,
+ engines->engines[i].engine_instance,
+ engines->engines[i].gt_id);
+ printf("\n");
+ }
+}
+
int main(int argc, char **argv)
{
struct igt_device_card card = { };
bool list_devices_arg = false;
+ bool list_engines_arg = false;
unsigned int repeat = 1;
unsigned int clients = 1;
unsigned int flags = 0;
@@ -3009,11 +3042,14 @@ int main(int argc, char **argv)
master_prng = time(NULL);
while ((c = getopt(argc, argv,
- "LhqvsSdc:r:w:W:a:p:I:f:F:D:")) != -1) {
+ "LlhqvsSdc:r:w:W:a:p:I:f:F:D:")) != -1) {
switch (c) {
case 'L':
list_devices_arg = true;
break;
+ case 'l':
+ list_engines_arg = true;
+ break;
case 'D':
device_arg = strdup(optarg);
break;
@@ -3134,6 +3170,11 @@ int main(int argc, char **argv)
if (is_xe)
xe_device_get(fd);
+ if (list_engines_arg) {
+ list_engines();
+ goto out;
+ }
+
if (!nr_w_args) {
wsim_err("No workload descriptor(s)!\n");
goto err;
--
2.31.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for benchmarks/gem_wsim: Extend engine selection syntax
2024-01-15 15:44 [PATCH i-g-t 0/2] benchmarks/gem_wsim: Extend engine selection syntax Marcin Bernatowicz
2024-01-15 15:44 ` [PATCH i-g-t 1/2] " Marcin Bernatowicz
2024-01-15 15:44 ` [PATCH i-g-t 2/2] benchmarks/gem_wsim: Option to list physical engines Marcin Bernatowicz
@ 2024-01-15 16:54 ` Patchwork
2024-01-15 17:06 ` ✓ CI.xeBAT: " Patchwork
2024-01-15 19:10 ` ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2024-01-15 16:54 UTC (permalink / raw)
To: Marcin Bernatowicz; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 6861 bytes --]
== Series Details ==
Series: benchmarks/gem_wsim: Extend engine selection syntax
URL : https://patchwork.freedesktop.org/series/128780/
State : success
== Summary ==
CI Bug Log - changes from IGT_7674 -> IGTPW_10534
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/index.html
Participating hosts (39 -> 38)
------------------------------
Additional (1): bat-dg2-8
Missing (2): bat-jsl-1 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_10534:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_engines:
- {bat-adls-6}: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/bat-adls-6/igt@i915_selftest@live@gt_engines.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-adls-6/igt@i915_selftest@live@gt_engines.html
Known issues
------------
Here are the changes found in IGTPW_10534 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap@basic:
- bat-dg2-8: NOTRUN -> [SKIP][3] ([i915#4083])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-8: NOTRUN -> [SKIP][4] ([i915#4077]) +2 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@gem_mmap_gtt@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg2-8: NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-8: NOTRUN -> [SKIP][6] ([i915#6621])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@i915_pm_rps@basic-api.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-dg2-8: NOTRUN -> [SKIP][7] ([i915#6645])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][8] ([i915#5190])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][9] ([i915#4215] / [i915#5190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-8: NOTRUN -> [SKIP][10] ([i915#4212]) +7 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][11] ([i915#4103] / [i915#4213]) +1 other test skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-8: NOTRUN -> [SKIP][12] ([fdo#109285])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-8: NOTRUN -> [SKIP][13] ([i915#5274])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pm_backlight@basic-brightness:
- bat-dg2-8: NOTRUN -> [SKIP][14] ([i915#5354])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-8: NOTRUN -> [SKIP][15] ([i915#3555])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-8: NOTRUN -> [SKIP][16] ([i915#3708])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-8: NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- bat-dg2-8: NOTRUN -> [SKIP][18] ([i915#3291] / [i915#3708]) +2 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/bat-dg2-8/igt@prime_vgem@basic-write.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9943]: https://gitlab.freedesktop.org/drm/intel/issues/9943
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7674 -> IGTPW_10534
CI-20190529: 20190529
CI_DRM_14124: 985e8077e53ee3ed954356d355a4277ea38d7157 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_10534: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/index.html
IGT_7674: 7674
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/index.html
[-- Attachment #2: Type: text/html, Size: 7892 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ CI.xeBAT: success for benchmarks/gem_wsim: Extend engine selection syntax
2024-01-15 15:44 [PATCH i-g-t 0/2] benchmarks/gem_wsim: Extend engine selection syntax Marcin Bernatowicz
` (2 preceding siblings ...)
2024-01-15 16:54 ` ✓ Fi.CI.BAT: success for benchmarks/gem_wsim: Extend engine selection syntax Patchwork
@ 2024-01-15 17:06 ` Patchwork
2024-01-15 19:10 ` ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2024-01-15 17:06 UTC (permalink / raw)
To: Marcin Bernatowicz; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 836 bytes --]
== Series Details ==
Series: benchmarks/gem_wsim: Extend engine selection syntax
URL : https://patchwork.freedesktop.org/series/128780/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7674_BAT -> XEIGTPW_10534_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_7674 -> IGTPW_10534
IGTPW_10534: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/index.html
IGT_7674: 7674
xe-629-3a1d727c0061b96ddf8e653130f94ab331e2f065: 3a1d727c0061b96ddf8e653130f94ab331e2f065
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10534/index.html
[-- Attachment #2: Type: text/html, Size: 1381 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ Fi.CI.IGT: failure for benchmarks/gem_wsim: Extend engine selection syntax
2024-01-15 15:44 [PATCH i-g-t 0/2] benchmarks/gem_wsim: Extend engine selection syntax Marcin Bernatowicz
` (3 preceding siblings ...)
2024-01-15 17:06 ` ✓ CI.xeBAT: " Patchwork
@ 2024-01-15 19:10 ` Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2024-01-15 19:10 UTC (permalink / raw)
To: Marcin Bernatowicz; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 75406 bytes --]
== Series Details ==
Series: benchmarks/gem_wsim: Extend engine selection syntax
URL : https://patchwork.freedesktop.org/series/128780/
State : failure
== Summary ==
CI Bug Log - changes from IGT_7674_full -> IGTPW_10534_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_10534_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_10534_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/index.html
Participating hosts (8 -> 8)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_10534_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pm_rpm@i2c:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-glk4/igt@kms_pm_rpm@i2c.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-glk4/igt@kms_pm_rpm@i2c.html
Known issues
------------
Here are the changes found in IGTPW_10534_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@unbind-cold-reset-rebind:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#7701])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-3/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@busy-idle-check-all@ccs0:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8414]) +7 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@drm_fdinfo@busy-idle-check-all@ccs0.html
* igt@drm_fdinfo@busy-idle-check-all@ccs3:
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8414]) +30 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@drm_fdinfo@busy-idle-check-all@ccs3.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: NOTRUN -> [FAIL][6] ([i915#7742])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@drm_fdinfo@virtual-idle:
- shard-rkl: [PASS][7] -> [FAIL][8] ([i915#7742])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-rkl-5/igt@drm_fdinfo@virtual-idle.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-5/igt@drm_fdinfo@virtual-idle.html
* igt@gem_ccs@suspend-resume:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#9323])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-2/igt@gem_ccs@suspend-resume.html
* igt@gem_compute@compute-square:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#9310])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@gem_compute@compute-square.html
* igt@gem_create@create-ext-set-pat:
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#8562])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@gem_create@create-ext-set-pat.html
* igt@gem_eio@reset-stress:
- shard-dg2: [PASS][12] -> [FAIL][13] ([i915#5784])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg2-7/igt@gem_eio@reset-stress.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-dual:
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#4771])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-3/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@bonded-sync:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#4771])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@hog:
- shard-dg2: NOTRUN -> [SKIP][16] ([i915#4812])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@gem_exec_balancer@hog.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-mtlp: NOTRUN -> [SKIP][17] ([i915#4036])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_capture@many-4k-incremental:
- shard-mtlp: NOTRUN -> [FAIL][18] ([i915#9606])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@gem_exec_capture@many-4k-incremental.html
- shard-dg2: NOTRUN -> [FAIL][19] ([i915#9606])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-7/igt@gem_exec_capture@many-4k-incremental.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: [PASS][20] -> [FAIL][21] ([i915#2846])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-rkl-4/igt@gem_exec_fair@basic-deadline.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow:
- shard-mtlp: NOTRUN -> [SKIP][22] ([i915#4473] / [i915#4771]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-2/igt@gem_exec_fair@basic-flow.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: NOTRUN -> [FAIL][23] ([i915#2842])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-glk9/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [PASS][24] -> [FAIL][25] ([i915#2842])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][26] -> [FAIL][27] ([i915#2842])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-glk4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-glk4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [PASS][28] -> [FAIL][29] ([i915#2842]) +2 other tests fail
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#3539])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-7/igt@gem_exec_fair@basic-throttle.html
* igt@gem_exec_flush@basic-wb-ro-before-default:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#3539] / [i915#4852]) +3 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@gem_exec_flush@basic-wb-ro-before-default.html
* igt@gem_exec_params@secure-non-root:
- shard-dg2: NOTRUN -> [SKIP][32] ([fdo#112283]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-7/igt@gem_exec_params@secure-non-root.html
- shard-rkl: NOTRUN -> [SKIP][33] ([fdo#112283])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-7/igt@gem_exec_params@secure-non-root.html
- shard-tglu: NOTRUN -> [SKIP][34] ([fdo#112283])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-8/igt@gem_exec_params@secure-non-root.html
* igt@gem_exec_reloc@basic-gtt-wc:
- shard-mtlp: NOTRUN -> [SKIP][35] ([i915#3281]) +9 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@gem_exec_reloc@basic-gtt-wc.html
* igt@gem_exec_reloc@basic-wc:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#3281]) +7 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-10/igt@gem_exec_reloc@basic-wc.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#4537] / [i915#4812]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#4860]) +1 other test skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@gem_fenced_exec_thrash@2-spare-fences.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#4860]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
* igt@gem_lmem_swapping@random-engines:
- shard-glk: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#4613]) +4 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-glk4/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@smem-oom:
- shard-mtlp: NOTRUN -> [SKIP][41] ([i915#4613])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [PASS][42] -> [TIMEOUT][43] ([i915#5493])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_media_vme:
- shard-mtlp: NOTRUN -> [SKIP][44] ([i915#284])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@gem_media_vme.html
* igt@gem_mmap_gtt@cpuset-medium-copy-odd:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4077]) +4 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-6/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4077]) +12 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_mmap_wc@copy:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#4083]) +4 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-3/igt@gem_mmap_wc@copy.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-rkl: NOTRUN -> [SKIP][48] ([i915#3282])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-1/igt@gem_partial_pwrite_pread@reads-display.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-mtlp: NOTRUN -> [SKIP][49] ([i915#3282]) +4 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pread@self:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#3282]) +8 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-10/igt@gem_pread@self.html
* igt@gem_pxp@create-regular-buffer:
- shard-mtlp: NOTRUN -> [SKIP][51] ([i915#4270]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@gem_pxp@create-regular-buffer.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#4270]) +3 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#8428]) +6 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-2/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#5190]) +9 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-7/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_set_tiling_vs_pwrite:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#4079])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_softpin@evict-snoop:
- shard-mtlp: NOTRUN -> [SKIP][56] ([i915#4885])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-6/igt@gem_softpin@evict-snoop.html
* igt@gem_tiled_pread_basic:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#4079]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@gem_tiled_pread_basic.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#3297]) +2 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#3297]) +3 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-6/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-mtlp: NOTRUN -> [SKIP][60] ([fdo#109289]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-2/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@batch-without-end:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#2856]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#2856]) +3 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@load:
- shard-mtlp: NOTRUN -> [SKIP][63] ([i915#6227])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [PASS][64] -> [INCOMPLETE][65] ([i915#9820] / [i915#9849])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-rkl-7/igt@i915_module_load@reload-with-fault-injection.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg1: [PASS][66] -> [INCOMPLETE][67] ([i915#9820] / [i915#9849])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg1-14/igt@i915_module_load@reload-with-fault-injection.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-19/igt@i915_module_load@reload-with-fault-injection.html
- shard-tglu: [PASS][68] -> [INCOMPLETE][69] ([i915#9200])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-tglu-7/igt@i915_module_load@reload-with-fault-injection.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-6/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: [PASS][70] -> [ABORT][71] ([i915#9820])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg2-7/igt@i915_module_load@reload-with-fault-injection.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-rkl: NOTRUN -> [SKIP][72] ([fdo#109289])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-4/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
- shard-tglu: NOTRUN -> [SKIP][73] ([fdo#109289])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-9/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-dg1: [PASS][74] -> [FAIL][75] ([i915#3591])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@i915_pm_rpm@gem-mmap-type@gtt-smem0:
- shard-mtlp: NOTRUN -> [SKIP][76] ([i915#8431])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@i915_pm_rpm@gem-mmap-type@gtt-smem0.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#6621])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-10/igt@i915_pm_rps@min-max-config-idle.html
- shard-mtlp: NOTRUN -> [SKIP][78] ([i915#6621])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-7/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_rps@thresholds-idle-park@gt0:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#8925])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@i915_pm_rps@thresholds-idle-park@gt0.html
* igt@i915_pm_rps@thresholds-idle-park@gt1:
- shard-mtlp: NOTRUN -> [SKIP][80] ([i915#3555] / [i915#8925])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@i915_pm_rps@thresholds-idle-park@gt1.html
* igt@i915_pm_sseu@full-enable:
- shard-dg2: NOTRUN -> [SKIP][81] ([i915#4387])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-10/igt@i915_pm_sseu@full-enable.html
- shard-mtlp: NOTRUN -> [SKIP][82] ([i915#8437])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-7/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#6188])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-2/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@intel_hwmon@hwmon-write:
- shard-mtlp: NOTRUN -> [SKIP][84] ([i915#7707])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@intel_hwmon@hwmon-write.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#4212]) +2 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
- shard-mtlp: NOTRUN -> [SKIP][86] ([i915#4212])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-3/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-4-rc-ccs-cc:
- shard-mtlp: NOTRUN -> [SKIP][87] ([i915#8709]) +11 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-4-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#8709]) +11 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#1769] / [i915#3555])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][90] ([fdo#111614]) +3 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-6/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglu: NOTRUN -> [SKIP][91] ([fdo#111615] / [i915#5286]) +1 other test skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-9/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
- shard-rkl: NOTRUN -> [SKIP][92] ([i915#5286])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][93] ([fdo#111614]) +2 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180:
- shard-mtlp: NOTRUN -> [FAIL][94] ([i915#5138])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][95] ([fdo#111615]) +7 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglu: [PASS][96] -> [FAIL][97] ([i915#3743])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#4538] / [i915#5190]) +7 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-3/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-glk: NOTRUN -> [SKIP][99] ([fdo#109271]) +184 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-glk9/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglu: NOTRUN -> [SKIP][100] ([fdo#111615])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
- shard-rkl: NOTRUN -> [SKIP][101] ([fdo#110723])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
- shard-dg1: NOTRUN -> [SKIP][102] ([i915#4538])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-17/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_joiner@2x-modeset:
- shard-mtlp: NOTRUN -> [SKIP][103] ([i915#2705])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@kms_big_joiner@2x-modeset.html
* igt@kms_big_joiner@basic:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#2705]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-7/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-a-bad-rotation-90-4-tiled-dg2-rc-ccs-cc:
- shard-tglu: NOTRUN -> [SKIP][105] ([i915#5354] / [i915#6095]) +4 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-2/igt@kms_ccs@pipe-a-bad-rotation-90-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-4-tiled-mtl-rc-ccs:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#5354] / [i915#6095]) +3 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-5/igt@kms_ccs@pipe-b-ccs-on-another-bo-4-tiled-mtl-rc-ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y-tiled-gen12-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#5354]) +97 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@kms_ccs@pipe-b-ccs-on-another-bo-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf-tiled-ccs:
- shard-rkl: NOTRUN -> [SKIP][108] ([i915#5354]) +3 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-7/igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf-tiled-ccs.html
- shard-dg1: NOTRUN -> [SKIP][109] ([i915#5354] / [i915#6095]) +2 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-15/igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf-tiled-ccs.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#5354] / [i915#6095]) +32 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-2/igt@kms_ccs@pipe-d-ccs-on-another-bo-yf-tiled-ccs.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-mtlp: NOTRUN -> [SKIP][111] ([i915#7213])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-3/igt@kms_cdclk@mode-transition-all-outputs.html
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#4087] / [i915#7213])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#7213]) +3 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2.html
* igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#4087]) +3 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html
* igt@kms_chamelium_audio@dp-audio:
- shard-rkl: NOTRUN -> [SKIP][115] ([i915#7828]) +1 other test skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-1/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_audio@hdmi-audio:
- shard-dg2: NOTRUN -> [SKIP][116] ([i915#7828]) +10 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_chamelium_audio@hdmi-audio.html
* igt@kms_chamelium_color@ctm-blue-to-red:
- shard-dg2: NOTRUN -> [SKIP][117] ([fdo#111827]) +2 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-10/igt@kms_chamelium_color@ctm-blue-to-red.html
* igt@kms_chamelium_color@ctm-limited-range:
- shard-mtlp: NOTRUN -> [SKIP][118] ([fdo#111827]) +3 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@kms_chamelium_color@ctm-limited-range.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-tglu: NOTRUN -> [SKIP][119] ([i915#7828])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-8/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-mtlp: NOTRUN -> [SKIP][120] ([i915#7828]) +3 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_content_protection@srm:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#7118]) +1 other test skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_content_protection@srm.html
- shard-mtlp: NOTRUN -> [SKIP][122] ([i915#6944])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-5/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-mtlp: NOTRUN -> [SKIP][123] ([i915#3555] / [i915#8814]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-7/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#3359])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-2/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#3359]) +4 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-256x85:
- shard-mtlp: NOTRUN -> [SKIP][126] ([i915#8814]) +1 other test skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-6/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-tglu: NOTRUN -> [SKIP][127] ([fdo#109274])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-3/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-rkl: NOTRUN -> [SKIP][128] ([fdo#111825]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
- shard-mtlp: NOTRUN -> [SKIP][129] ([i915#9809]) +3 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-mtlp: NOTRUN -> [SKIP][130] ([fdo#111767])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
- shard-dg2: NOTRUN -> [SKIP][131] ([fdo#109274] / [fdo#111767] / [i915#5354])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-dg2: NOTRUN -> [SKIP][132] ([fdo#109274] / [i915#5354]) +2 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][133] -> [FAIL][134] ([i915#2346])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#4103] / [i915#4213])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][136] ([i915#9723])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-12/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3.html
* igt@kms_display_modes@extended-mode-basic:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#3555]) +6 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][138] ([i915#3804])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-mtlp: NOTRUN -> [SKIP][139] ([i915#3555] / [i915#3840])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-6/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_feature_discovery@display-2x:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#1839])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@kms_feature_discovery@display-2x.html
- shard-rkl: NOTRUN -> [SKIP][141] ([i915#1839])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-7/igt@kms_feature_discovery@display-2x.html
- shard-tglu: NOTRUN -> [SKIP][142] ([i915#1839])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-9/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@psr2:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#658])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@kms_feature_discovery@psr2.html
* igt@kms_fence_pin_leak:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#4881])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-3/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-dg2: NOTRUN -> [SKIP][145] ([fdo#109274] / [fdo#111767])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-dg2: NOTRUN -> [SKIP][146] ([fdo#109274]) +8 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-tglu: NOTRUN -> [SKIP][147] ([fdo#109274] / [i915#3637]) +1 other test skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#3637]) +1 other test skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip@flip-vs-fences:
- shard-mtlp: NOTRUN -> [SKIP][149] ([i915#8381])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-5/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#8381])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#2587] / [i915#2672]) +1 other test skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][152] ([i915#2672]) +1 other test skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][153] ([i915#8810])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][154] ([i915#3555] / [i915#8810])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#2672]) +4 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][156] ([i915#8708]) +6 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt:
- shard-tglu: NOTRUN -> [SKIP][157] ([fdo#109280]) +3 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
- shard-snb: [PASS][158] -> [SKIP][159] ([fdo#109271]) +11 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#3458]) +22 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][161] ([i915#9766])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-6/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-tglu: NOTRUN -> [SKIP][162] ([i915#9766])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-5/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-dg2: NOTRUN -> [SKIP][163] ([i915#9766])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#8708]) +14 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt:
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#1825]) +22 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render:
- shard-rkl: NOTRUN -> [SKIP][166] ([fdo#111825] / [i915#1825]) +5 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite:
- shard-rkl: NOTRUN -> [SKIP][167] ([i915#3023]) +2 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html
- shard-tglu: NOTRUN -> [SKIP][168] ([fdo#110189]) +2 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-9/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#3555] / [i915#8228]) +2 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-5/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-toggle:
- shard-dg2: NOTRUN -> [SKIP][170] ([i915#3555] / [i915#8228]) +2 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-7/igt@kms_hdr@static-toggle.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-dg2: NOTRUN -> [SKIP][171] ([i915#6301])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-dg2: NOTRUN -> [SKIP][172] ([fdo#109289]) +5 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][173] ([i915#4573]) +3 other tests fail
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-glk9/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1.html
* igt@kms_plane_lowres@tiling-4@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][174] ([i915#3582]) +3 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@kms_plane_lowres@tiling-4@pipe-b-edp-1.html
* igt@kms_plane_lowres@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#3555] / [i915#8821])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-3/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@tiling-yf:
- shard-mtlp: NOTRUN -> [SKIP][176] ([i915#3555] / [i915#8806])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-3/igt@kms_plane_multiple@tiling-yf.html
- shard-dg2: NOTRUN -> [SKIP][177] ([i915#3555] / [i915#8806])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#9423]) +3 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#9423]) +7 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][180] ([i915#9423]) +11 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-13/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][181] ([i915#5176] / [i915#9423]) +1 other test skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#5235]) +11 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-19/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#5235] / [i915#9423]) +15 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-3/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][184] ([i915#5235]) +20 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][185] ([i915#3555] / [i915#5235]) +2 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-7/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][186] ([i915#5235]) +5 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#9519]) +2 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-3/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-mtlp: NOTRUN -> [SKIP][188] ([i915#9519])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-7/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [PASS][189] -> [SKIP][190] ([i915#9519])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp.html
- shard-rkl: [PASS][191] -> [SKIP][192] ([i915#9519])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@pc8-residency:
- shard-mtlp: NOTRUN -> [SKIP][193] ([fdo#109293])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-6/igt@kms_pm_rpm@pc8-residency.html
- shard-dg2: NOTRUN -> [SKIP][194] ([fdo#109293] / [fdo#109506]) +1 other test skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-7/igt@kms_pm_rpm@pc8-residency.html
* igt@kms_prime@basic-crc-vgem:
- shard-dg2: NOTRUN -> [SKIP][195] ([i915#6524] / [i915#6805])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_prime@basic-crc-vgem.html
* igt@kms_prime@d3hot:
- shard-mtlp: NOTRUN -> [SKIP][196] ([i915#6524])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-5/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#9683])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-mtlp: NOTRUN -> [SKIP][198] ([i915#4348])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-rkl: NOTRUN -> [SKIP][199] ([i915#9685])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
- shard-dg1: NOTRUN -> [SKIP][200] ([i915#9685])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-15/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
- shard-tglu: NOTRUN -> [SKIP][201] ([i915#9685])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg2: NOTRUN -> [SKIP][202] ([i915#9685]) +2 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#4235])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-rkl: [PASS][204] -> [INCOMPLETE][205] ([i915#8875] / [i915#9569]) +1 other test incomplete
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-rkl-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-snb: NOTRUN -> [SKIP][206] ([fdo#109271]) +19 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-snb6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-mtlp: NOTRUN -> [SKIP][207] ([i915#3555] / [i915#8809])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-mtlp: NOTRUN -> [SKIP][208] ([i915#3555] / [i915#8823])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-5/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-rkl: NOTRUN -> [SKIP][209] ([i915#3555])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-1/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
- shard-tglu: NOTRUN -> [SKIP][210] ([i915#3555]) +1 other test skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-3/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2: NOTRUN -> [SKIP][211] ([fdo#109309])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-1/igt@kms_tv_load_detect@load-detect.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1:
- shard-tglu: [PASS][212] -> [FAIL][213] ([i915#9196]) +1 other test fail
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-tglu-10/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1:
- shard-mtlp: [PASS][214] -> [FAIL][215] ([i915#9196])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-2/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
* igt@kms_writeback@writeback-fb-id:
- shard-dg2: NOTRUN -> [SKIP][216] ([i915#2437]) +1 other test skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-5/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-mtlp: NOTRUN -> [SKIP][217] ([i915#2437])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-glk: NOTRUN -> [SKIP][218] ([fdo#109271] / [i915#2437]) +1 other test skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-glk9/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@global-sseu-config:
- shard-mtlp: NOTRUN -> [SKIP][219] ([i915#7387])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@perf@global-sseu-config.html
- shard-dg2: NOTRUN -> [SKIP][220] ([i915#7387])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@perf@global-sseu-config.html
* igt@perf_pmu@frequency@gt0:
- shard-dg2: NOTRUN -> [FAIL][221] ([i915#6806])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@perf_pmu@frequency@gt0.html
* igt@prime_udl:
- shard-mtlp: NOTRUN -> [SKIP][222] ([fdo#109291])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@prime_udl.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> [SKIP][223] ([i915#3708] / [i915#4077]) +1 other test skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-7/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-flip-hang:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#3708]) +1 other test skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-7/igt@prime_vgem@fence-flip-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#9917])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-7/igt@sriov_basic@bind-unbind-vf.html
- shard-mtlp: NOTRUN -> [SKIP][226] ([i915#9917])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-6/igt@sriov_basic@bind-unbind-vf.html
* igt@v3d/v3d_get_param@base-params:
- shard-mtlp: NOTRUN -> [SKIP][227] ([i915#2575]) +6 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-8/igt@v3d/v3d_get_param@base-params.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-dg2: NOTRUN -> [SKIP][228] ([i915#2575]) +11 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-3/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@v3d/v3d_submit_csd@bad-perfmon:
- shard-dg1: NOTRUN -> [SKIP][229] ([i915#2575]) +1 other test skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-17/igt@v3d/v3d_submit_csd@bad-perfmon.html
- shard-tglu: NOTRUN -> [SKIP][230] ([fdo#109315] / [i915#2575])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-3/igt@v3d/v3d_submit_csd@bad-perfmon.html
- shard-rkl: NOTRUN -> [SKIP][231] ([fdo#109315])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-6/igt@v3d/v3d_submit_csd@bad-perfmon.html
* igt@vc4/vc4_create_bo@create-bo-0:
- shard-mtlp: NOTRUN -> [SKIP][232] ([i915#7711]) +7 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-4/igt@vc4/vc4_create_bo@create-bo-0.html
* igt@vc4/vc4_label_bo@set-kernel-name:
- shard-dg1: NOTRUN -> [SKIP][233] ([i915#7711])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-12/igt@vc4/vc4_label_bo@set-kernel-name.html
- shard-tglu: NOTRUN -> [SKIP][234] ([i915#2575])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-8/igt@vc4/vc4_label_bo@set-kernel-name.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained:
- shard-dg2: NOTRUN -> [SKIP][235] ([i915#7711]) +8 other tests skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-6/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [FAIL][236] ([i915#6268]) -> [PASS][237]
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-8/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-rkl: [FAIL][238] ([i915#2842]) -> [PASS][239]
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-rkl-5/igt@gem_exec_fair@basic-none-solo@rcs0.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglu: [FAIL][240] ([i915#2842]) -> [PASS][241] +1 other test pass
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-tglu-3/igt@gem_exec_fair@basic-pace@rcs0.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-tglu: [ABORT][242] ([i915#7975] / [i915#8213]) -> [PASS][243]
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-4/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-dg1: [FAIL][244] ([i915#3591]) -> [PASS][245] +1 other test pass
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [FAIL][246] ([i915#5138]) -> [PASS][247]
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-mtlp-2/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu: [FAIL][248] ([i915#3743]) -> [PASS][249] +1 other test pass
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-tglu-10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-tglu-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][250] ([i915#2346]) -> [PASS][251]
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-dg2: [FAIL][252] ([i915#6880]) -> [PASS][253]
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-snb: [SKIP][254] ([fdo#109271]) -> [PASS][255] +10 other tests pass
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-rkl: [SKIP][256] ([i915#9519]) -> [PASS][257] +1 other test pass
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-6/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-1:
- shard-snb: [FAIL][258] ([i915#5465]) -> [PASS][259] +1 other test pass
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-snb5/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-snb1/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
- shard-mtlp: [FAIL][260] ([i915#9196]) -> [PASS][261]
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-snb: [FAIL][262] ([i915#9196]) -> [PASS][263]
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-snb6/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-snb2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-2:
- shard-rkl: [FAIL][264] ([i915#9196]) -> [PASS][265]
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-rkl-6/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-2.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-6/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-2.html
#### Warnings ####
* igt@device_reset@unbind-reset-rebind:
- shard-dg1: [INCOMPLETE][266] ([i915#9408] / [i915#9618]) -> [INCOMPLETE][267] ([i915#9618])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg1-18/igt@device_reset@unbind-reset-rebind.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-18/igt@device_reset@unbind-reset-rebind.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [ABORT][268] ([i915#9846]) -> [INCOMPLETE][269] ([i915#9364])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg2-3/igt@gem_create@create-ext-cpu-access-big.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg2-2/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_pread@exhaustion:
- shard-glk: [WARN][270] ([i915#2658]) -> [INCOMPLETE][271] ([i915#10042]) +1 other test incomplete
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-glk9/igt@gem_pread@exhaustion.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-glk3/igt@gem_pread@exhaustion.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [ABORT][272] ([i915#9820]) -> [ABORT][273] ([i915#9697])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_async_flips@crc@pipe-d-edp-1:
- shard-mtlp: [DMESG-FAIL][274] ([i915#8561]) -> [FAIL][275] ([i915#8247]) +2 other tests fail
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-mtlp-2/igt@kms_async_flips@crc@pipe-d-edp-1.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-mtlp-2/igt@kms_async_flips@crc@pipe-d-edp-1.html
* igt@kms_content_protection@atomic:
- shard-snb: [SKIP][276] ([fdo#109271]) -> [INCOMPLETE][277] ([i915#8816])
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-snb6/igt@kms_content_protection@atomic.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-snb7/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: [SKIP][278] ([i915#9424]) -> [SKIP][279] ([i915#9433])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-dg1-17/igt@kms_content_protection@mei-interface.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-dg1-14/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@uevent:
- shard-snb: [INCOMPLETE][280] ([i915#8816]) -> [SKIP][281] ([fdo#109271])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-snb7/igt@kms_content_protection@uevent.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-snb1/igt@kms_content_protection@uevent.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][282] ([fdo#110189] / [i915#3955]) -> [SKIP][283] ([i915#3955])
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7674/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#10042]: https://gitlab.freedesktop.org/drm/intel/issues/10042
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6188]: https://gitlab.freedesktop.org/drm/intel/issues/6188
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6806]: https://gitlab.freedesktop.org/drm/intel/issues/6806
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8431]: https://gitlab.freedesktop.org/drm/intel/issues/8431
[i915#8437]: https://gitlab.freedesktop.org/drm/intel/issues/8437
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8806]: https://gitlab.freedesktop.org/drm/intel/issues/8806
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8816]: https://gitlab.freedesktop.org/drm/intel/issues/8816
[i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821
[i915#8823]: https://gitlab.freedesktop.org/drm/intel/issues/8823
[i915#8875]: https://gitlab.freedesktop.org/drm/intel/issues/8875
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9200]: https://gitlab.freedesktop.org/drm/intel/issues/9200
[i915#9310]: https://gitlab.freedesktop.org/drm/intel/issues/9310
[i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
[i915#9364]: https://gitlab.freedesktop.org/drm/intel/issues/9364
[i915#9408]: https://gitlab.freedesktop.org/drm/intel/issues/9408
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/intel/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9569]: https://gitlab.freedesktop.org/drm/intel/issues/9569
[i915#9606]: https://gitlab.freedesktop.org/drm/intel/issues/9606
[i915#9618]: https://gitlab.freedesktop.org/drm/intel/issues/9618
[i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9697]: https://gitlab.freedesktop.org/drm/intel/issues/9697
[i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/intel/issues/9766
[i915#9808]: https://gitlab.freedesktop.org/drm/intel/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
[i915#9846]: https://gitlab.freedesktop.org/drm/intel/issues/9846
[i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
[i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7674 -> IGTPW_10534
CI-20190529: 20190529
CI_DRM_14124: 985e8077e53ee3ed954356d355a4277ea38d7157 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_10534: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/index.html
IGT_7674: 7674
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10534/index.html
[-- Attachment #2: Type: text/html, Size: 90527 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH i-g-t 1/2] benchmarks/gem_wsim: Extend engine selection syntax
2024-01-15 15:44 ` [PATCH i-g-t 1/2] " Marcin Bernatowicz
@ 2024-01-24 11:41 ` Laguna, Lukasz
2024-01-24 12:24 ` Tvrtko Ursulin
1 sibling, 0 replies; 11+ messages in thread
From: Laguna, Lukasz @ 2024-01-24 11:41 UTC (permalink / raw)
To: Marcin Bernatowicz, igt-dev
[-- Attachment #1: Type: text/plain, Size: 38856 bytes --]
On 1/15/2024 16:44, Marcin Bernatowicz wrote:
> This commit introduces significant changes to the engine selection
> syntax:
> - Dynamically generates the list of available physical engines by
> querying the device.
> - Identifies engines using [class:instance:gt] tuples.
> - Allows specifying engine instance and gt as
> `engine_class[<engine_instance>-<gt_id>]`
> ex. First VCS engine may be specified as VCS, VCS1, and VCS1-0.
> - Adds support for compute engine class (CCS).
> - Maintains 1-based engine instance ids for compatibility with existing
> workload definitions.
> - Each `w_step` now includes an `engine_idx` (populated during prepare
> workload phase), simplifying the run phase with an index in the
> device/context engine map.
> Second index field `request_idx` was introduced to support throttling
> functionality, enabling control over the rate of requests on a given
> engine.
>
> Signed-off-by: Marcin Bernatowicz<marcin.bernatowicz@linux.intel.com>
> ---
> benchmarks/gem_wsim.c | 788 +++++++++++++++++++++---------------------
> 1 file changed, 402 insertions(+), 386 deletions(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index 955b6799e..e79d26513 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -68,17 +68,6 @@
> #include "xe/xe_ioctl.h"
> #include "xe/xe_spin.h"
>
> -enum intel_engine_id {
> - DEFAULT,
> - RCS,
> - BCS,
> - VCS,
> - VCS1,
> - VCS2,
> - VECS,
> - NUM_ENGINES
> -};
> -
> struct duration {
> unsigned int min, max;
> bool unbound;
> @@ -126,9 +115,16 @@ struct w_arg {
> bool sseu;
> };
>
> +typedef struct drm_xe_engine_class_instance intel_engine_t;
> +
> +struct intel_engines {
> + unsigned int nr_engines;
> + intel_engine_t *engines;
> +};
> +
> struct bond {
> - uint64_t mask;
> - enum intel_engine_id master;
> + struct intel_engines mask;
> + intel_engine_t master;
> };
>
> struct work_buffer_size {
> @@ -153,7 +149,8 @@ struct w_step {
> /* Workload step metadata */
> enum w_type type;
> unsigned int context;
> - unsigned int engine;
> + unsigned int engine_idx;
> + intel_engine_t engine;
> struct duration duration;
> struct deps data_deps;
> struct deps fence_deps;
> @@ -165,15 +162,9 @@ struct w_step {
> int target;
> int throttle;
> int priority;
> - struct {
> - unsigned int engine_map_count;
> - enum intel_engine_id *engine_map;
> - };
> + struct intel_engines engine_map;
> bool load_balance;
> - struct {
> - uint64_t bond_mask;
> - enum intel_engine_id bond_master;
> - };
> + struct bond bond;
> int sseu;
> struct working_set working_set;
> };
> @@ -181,7 +172,7 @@ struct w_step {
> /* Implementation details */
> unsigned int idx;
> struct igt_list_head rq_link;
> - unsigned int request;
> + unsigned int request_idx;
> unsigned int preempt_us;
>
> union {
> @@ -220,8 +211,7 @@ struct xe_exec_queue {
> struct ctx {
> uint32_t id;
> int priority;
> - unsigned int engine_map_count;
> - enum intel_engine_id *engine_map;
> + struct intel_engines engine_map;
> unsigned int bond_count;
> struct bond *bonds;
> bool load_balance;
> @@ -267,8 +257,8 @@ struct workload {
> int sync_timeline;
> uint32_t sync_seqno;
>
> - struct igt_list_head requests[NUM_ENGINES];
> - unsigned int nrequest[NUM_ENGINES];
> + struct igt_list_head *requests;
> + unsigned int *nrequest;
> };
>
> #define __for_each_ctx(__ctx, __wrk, __ctx_idx) \
> @@ -296,16 +286,44 @@ static struct drm_i915_gem_context_param_sseu device_sseu = {
> #define FLAG_DEPSYNC (1<<2)
> #define FLAG_SSEU (1<<3)
>
> -static const char *ring_str_map[NUM_ENGINES] = {
> - [DEFAULT] = "DEFAULT",
> - [RCS] = "RCS",
> - [BCS] = "BCS",
> - [VCS] = "VCS",
> - [VCS1] = "VCS1",
> - [VCS2] = "VCS2",
> - [VECS] = "VECS",
> +enum intel_engine_class {
> + RCS,
> + BCS,
> + VCS,
> + VECS,
> + CCS,
> + NUM_ENGINE_CLASSES,
> };
>
> +_Static_assert(RCS == DRM_XE_ENGINE_CLASS_RENDER, "mismatch");
> +_Static_assert(BCS == DRM_XE_ENGINE_CLASS_COPY, "mismatch");
> +_Static_assert(VCS == DRM_XE_ENGINE_CLASS_VIDEO_DECODE, "mismatch");
> +_Static_assert(VECS == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE, "mismatch");
> +_Static_assert(CCS == DRM_XE_ENGINE_CLASS_COMPUTE, "mismatch");
> +_Static_assert((int)RCS == (int)I915_ENGINE_CLASS_RENDER, "mismatch");
> +_Static_assert((int)BCS == (int)I915_ENGINE_CLASS_COPY, "mismatch");
> +_Static_assert((int)VCS == (int)I915_ENGINE_CLASS_VIDEO, "mismatch");
> +_Static_assert((int)VECS == (int)I915_ENGINE_CLASS_VIDEO_ENHANCE, "mismatch");
> +_Static_assert((int)CCS == (int)I915_ENGINE_CLASS_COMPUTE, "mismatch");
> +
> +static const char *intel_engine_class_string(uint16_t engine_class)
nit: static const char *intel_engine_class_to_string(enum
intel_engine_class engine_class) ?
> +{
> + switch (engine_class) {
> + case RCS:
> + return "RCS";
> + case BCS:
> + return "BCS";
> + case VCS:
> + return "VCS";
> + case VECS:
> + return "VECS";
> + case CCS:
> + return "CCS";
> + default:
> + igt_assert(0);
> + }
> +}
> +
> static void w_step_sync(struct w_step *w)
> {
> if (is_xe)
> @@ -521,218 +539,261 @@ out:
> } \
> }
>
> -static int str_to_engine(const char *str)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < ARRAY_SIZE(ring_str_map); i++) {
> - if (!strcasecmp(str, ring_str_map[i]))
> - return i;
> - }
> -
> - return -1;
> -}
> +#define INVALID_ID ((uint16_t)-2)
> +#define DEFAULT_ID ((uint16_t)-1)
>
> -static struct intel_engine_data *query_engines(void)
> +static struct intel_engines *query_engines(void)
> {
> - static struct intel_engine_data engines = {};
> + static struct intel_engines engines = {};
>
> - if (engines.nengines)
> + if (engines.nr_engines)
> return &engines;
>
> if (is_xe) {
> struct drm_xe_engine_class_instance *hwe;
>
> - xe_for_each_engine(fd, hwe) {
> - engines.engines[engines.nengines].class = hwe->engine_class;
> - engines.engines[engines.nengines].instance = hwe->engine_instance;
> - engines.nengines++;
> + engines.engines = calloc(xe_number_engines(fd), sizeof(intel_engine_t));
> + igt_assert(engines.engines);
> + engines.nr_engines = 0;
> + xe_for_each_engine(fd, hwe)
> + engines.engines[engines.nr_engines++] = *hwe;
> + igt_assert(engines.nr_engines);
> + } else {
> + struct intel_engine_data ed = {};
> +
> + ed = intel_engine_list_of_physical(fd);
> + igt_assert(ed.nengines);
> + engines.nr_engines = ed.nengines;
> + engines.engines = calloc(engines.nr_engines, sizeof(intel_engine_t));
> + igt_assert(engines.engines);
> + for (int i = 0; i < ed.nengines; ++i) {
> + engines.engines[i].engine_class = ed.engines[i].class;
> + engines.engines[i].engine_instance = ed.engines[i].instance;
> + engines.engines[i].gt_id = DEFAULT_ID;
> }
> - } else
> - engines = intel_engine_list_of_physical(fd);
> + }
>
> - igt_assert(engines.nengines);
> return &engines;
> }
>
> -static unsigned int num_engines_in_class(enum intel_engine_id class)
> -{
> - const struct intel_engine_data *engines = query_engines();
> - unsigned int i, count = 0;
> +/* engine_class[<engine_instance>-<gt_id>] */
> +static intel_engine_t str_to_engine(const char *str)
> +{
> + intel_engine_t e = {INVALID_ID, DEFAULT_ID, DEFAULT_ID};
> + size_t pos;
> +
> + if (!strcasecmp("DEFAULT", str)) {
> + e.engine_class = DEFAULT_ID;
> + return e;
> + } else if (!strncasecmp("RCS", str, 3)) {
> + e.engine_class = RCS;
> + pos = 3;
> + } else if (!strncasecmp("BCS", str, 3)) {
> + e.engine_class = BCS;
> + pos = 3;
> + } else if (!strncasecmp("VCS", str, 3)) {
> + e.engine_class = VCS;
> + pos = 3;
> + } else if (!strncasecmp("VECS", str, 4)) {
> + e.engine_class = VECS;
> + pos = 4;
> + } else if (!strncasecmp("CCS", str, 3)) {
> + e.engine_class = CCS;
> + pos = 3;
> + } else
> + return (intel_engine_t){INVALID_ID};
> +
> + if (str[pos]) {
> + char *s = strchr(&str[pos], '-');
> + char *endptr = NULL;
> + long id;
> +
> + if (!s || (s && *s != str[pos])) {
> + id = strtol(&str[pos], &endptr, 10);
> + if (endptr == &str[pos] || id < 1 || id >= INVALID_ID)
> + return (intel_engine_t){INVALID_ID};
> + e.engine_instance = id - 1;
> + }
>
> - igt_assert(class == VCS);
> + if (s && *(++s)) {
> + id = strtol(s, &endptr, 10);
> + if (endptr == s || id < 0 || id >= INVALID_ID)
> + return (intel_engine_t){INVALID_ID};
> + e.gt_id = id;
> + }
>
> - for (i = 0; i < engines->nengines; i++) {
> - if (engines->engines[i].class == I915_ENGINE_CLASS_VIDEO)
> - count++;
> + if (endptr && endptr != (str + strlen(str)))
> + return (intel_engine_t){INVALID_ID};
> }
>
> - igt_assert(count);
> - return count;
> + return e;
> }
>
> -static void
> -fill_engines_id_class(enum intel_engine_id *list,
> - enum intel_engine_id class)
> +static bool is_valid_engine(const intel_engine_t *engine)
> {
> - const struct intel_engine_data *engines = query_engines();
> - enum intel_engine_id engine = VCS1;
> - unsigned int i, j = 0;
> -
> - igt_assert(class == VCS);
> - igt_assert(num_engines_in_class(VCS) <= 2);
> -
> - for (i = 0; i < engines->nengines; i++) {
> - if (engines->engines[i].class != I915_ENGINE_CLASS_VIDEO)
> - continue;
> -
> - list[j++] = engine++;
> - }
> + return engine->engine_class != INVALID_ID;
> }
>
> -static unsigned int
> -find_physical_instance(enum intel_engine_id class, unsigned int logical)
> +static bool is_default_engine(const intel_engine_t *engine)
> {
> - const struct intel_engine_data *engines = query_engines();
> - unsigned int i, j = 0;
> -
> - igt_assert(class == VCS);
> -
> - for (i = 0; i < engines->nengines; i++) {
> - if (engines->engines[i].class != I915_ENGINE_CLASS_VIDEO)
> - continue;
> -
> - /* Map logical to physical instances. */
> - if (logical == j++)
> - return engines->engines[i].instance;
> - }
> -
> - igt_assert(0);
> - return 0;
> + return engine->engine_class == DEFAULT_ID &&
> + engine->engine_instance == DEFAULT_ID &&
> + engine->gt_id == DEFAULT_ID;
> }
>
> -static struct i915_engine_class_instance
> -get_engine(enum intel_engine_id engine)
> +static struct i915_engine_class_instance to_i915_engine_class(const intel_engine_t *engine)
nit: engine_to_i915_engine_class() ?
> {
> - struct i915_engine_class_instance ci;
> -
> - query_engines();
> + return (struct i915_engine_class_instance){engine->engine_class, engine->engine_instance};
> +}
>
> - switch (engine) {
> +static unsigned int to_i915_legacy_ring(const intel_engine_t *engine)
nit: engine_to_i915_legacy_ring() ?
> +{
> + switch (engine->engine_class) {
> + case DEFAULT_ID:
> + return I915_EXEC_DEFAULT;
> case RCS:
> - ci.engine_class = I915_ENGINE_CLASS_RENDER;
> - ci.engine_instance = 0;
> - break;
> + return I915_EXEC_RENDER;
> case BCS:
> - ci.engine_class = I915_ENGINE_CLASS_COPY;
> - ci.engine_instance = 0;
> - break;
> - case VCS1:
> - case VCS2:
> - ci.engine_class = I915_ENGINE_CLASS_VIDEO;
> - ci.engine_instance = find_physical_instance(VCS, engine - VCS1);
> + return I915_EXEC_BLT;
> + case VCS:
> + if (engine->engine_instance == DEFAULT_ID)
> + return I915_EXEC_BSD;
> + else if (engine->engine_instance == 0)
> + return I915_EXEC_BSD | I915_EXEC_BSD_RING1;
> + else if (engine->engine_instance == 1)
> + return I915_EXEC_BSD | I915_EXEC_BSD_RING2;
> break;
> case VECS:
> - ci.engine_class = I915_ENGINE_CLASS_VIDEO_ENHANCE;
> - ci.engine_instance = 0;
> - break;
> - default:
> - igt_assert(0);
> + return I915_EXEC_VEBOX;
> };
>
> - return ci;
> + igt_assert(0);
> }
>
> -static struct drm_xe_engine_class_instance
> -xe_get_engine(enum intel_engine_id engine)
> +static bool are_equal_engines(const intel_engine_t *e1, const intel_engine_t *e2)
> {
> - struct drm_xe_engine_class_instance hwe = {}, *hwe1;
> - bool found_physical = false;
> -
> - switch (engine) {
> - case RCS:
> - hwe.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
> - break;
> - case BCS:
> - hwe.engine_class = DRM_XE_ENGINE_CLASS_COPY;
> - break;
> - case VCS1:
> - hwe.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
> - break;
> - case VCS2:
> - hwe.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
> - hwe.engine_instance = 1;
> - break;
> - case VECS:
> - hwe.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;
> - break;
> - default:
> - igt_assert(0);
> - };
> + return e1->engine_class == e2->engine_class &&
> + e1->engine_instance == e2->engine_instance &&
> + e1->gt_id == e2->gt_id;
> +}
>
> - xe_for_each_engine(fd, hwe1) {
> - if (hwe.engine_class == hwe1->engine_class &&
> - hwe.engine_instance == hwe1->engine_instance) {
> - hwe = *hwe1;
> - found_physical = true;
> - break;
> +static bool
> +find_engine_in_map(const intel_engine_t *engine, struct intel_engines *engines, unsigned int *idx)
> +{
> + igt_assert(idx);
> + for (unsigned int i = 0; i < engines->nr_engines; ++i)
> + if (are_equal_engines(engine, &engines->engines[i])) {
> + *idx = i;
> + return true;
> }
> - }
>
> - igt_assert(found_physical);
> - return hwe;
> + return false;
> }
>
> -static struct drm_xe_engine_class_instance
> -xe_get_default_engine(void)
> +static bool engine_matches_filter(const intel_engine_t *engine, const intel_engine_t *filter)
> {
> - struct drm_xe_engine_class_instance default_hwe, *hwe;
> + return (filter->engine_class == DEFAULT_ID ||
> + filter->engine_class == engine->engine_class) &&
> + (filter->engine_instance == DEFAULT_ID ||
> + filter->engine_instance == engine->engine_instance) &&
> + (filter->gt_id == DEFAULT_ID ||
> + filter->gt_id == engine->gt_id);
> +}
>
> - /* select RCS0 | CCS0 or first available engine */
> - default_hwe = xe_engine(fd, 0)->instance;
> - xe_for_each_engine(fd, hwe) {
> - if ((hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
> - hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) &&
> - hwe->engine_instance == 0) {
> - default_hwe = *hwe;
> - break;
> - }
> +#define for_each_matching_engine(__engine, __filter, __engines) \
> + for (unsigned int __i = 0; __i < __engines->nr_engines && \
> + (__engine = &__engines->engines[__i]); __i++) \
> + for_if(engine_matches_filter(__engine, __filter))
> +
> +static unsigned int
> +append_matching_engines(const intel_engine_t *filter, struct intel_engines *engines)
> +{
> + unsigned int prev_nr_engines;
> + struct intel_engines *all = query_engines();
> + intel_engine_t *engine;
> +
> + igt_assert(engines);
> + prev_nr_engines = engines->nr_engines;
> +
> + for_each_matching_engine(engine, filter, all) {
> + engines->nr_engines++;
> + engines->engines = realloc(engines->engines,
> + engines->nr_engines * sizeof(intel_engine_t));
> + igt_assert(engines->engines);
> + engines->engines[engines->nr_engines - 1] = *engine;
> }
>
> - return default_hwe;
> + return engines->nr_engines - prev_nr_engines;
> +}
> +
> +static intel_engine_t get_default_engine(void)
> +{
> + struct intel_engines *all_engines = query_engines();
> + const intel_engine_t filters[] = {
> + {RCS, DEFAULT_ID, DEFAULT_ID},
> + {CCS, DEFAULT_ID, DEFAULT_ID},
> + {DEFAULT_ID, DEFAULT_ID, DEFAULT_ID},
> + {INVALID_ID}
> + }, *filter, *default_engine;
> +
> + for (filter = filters; is_valid_engine(filter); filter++)
> + for_each_matching_engine(default_engine, filter, all_engines)
> + return *default_engine;
> +
> + igt_assert(0);
> +}
> +
> +static intel_engine_t resolve_to_physical_engine_(const intel_engine_t *engine)
> +{
> + struct intel_engines *all_engines = query_engines();
> + intel_engine_t *resolved;
> +
> + igt_assert(engine);
> + if (is_default_engine(engine))
> + return get_default_engine();
> +
> + for_each_matching_engine(resolved, engine, all_engines)
> + return *resolved;
> +
> + return (intel_engine_t){INVALID_ID};
> +}
> +
> +static void resolve_to_physical_engine(intel_engine_t *engine)
> +{
> + *engine = resolve_to_physical_engine_(engine);
> + igt_assert(is_valid_engine(engine));
> }
>
> static int parse_engine_map(struct w_step *step, const char *_str)
> {
> char *token, *tctx = NULL, *tstart = (char *)_str;
> + intel_engine_t engine;
>
> while ((token = strtok_r(tstart, "|", &tctx))) {
> - enum intel_engine_id engine;
> - unsigned int add;
> -
> tstart = NULL;
>
> - if (!strcmp(token, "DEFAULT"))
> + engine = str_to_engine(token);
> + if (!is_valid_engine(&engine) || is_default_engine(&engine))
> return -1;
>
> - engine = str_to_engine(token);
> - if ((int)engine < 0)
> + if (!append_matching_engines(&engine, &step->engine_map))
> return -1;
> + }
> +
> + return 0;
> +}
>
> - if (engine != VCS && engine != VCS1 && engine != VCS2 &&
> - engine != RCS)
> - return -1; /* TODO */
> +static int parse_bond_engines(struct w_step *step, const char *_str)
> +{
> + char *token, *tctx = NULL, *tstart = (char *)_str;
> + intel_engine_t engine;
>
> - add = engine == VCS ? num_engines_in_class(VCS) : 1;
> - step->engine_map_count += add;
> - step->engine_map = realloc(step->engine_map,
> - step->engine_map_count *
> - sizeof(step->engine_map[0]));
> + while ((token = strtok_r(tstart, "|", &tctx))) {
> + tstart = NULL;
>
> - if (engine != VCS)
> - step->engine_map[step->engine_map_count - add] = engine;
> - else
> - fill_engines_id_class(&step->engine_map[step->engine_map_count - add], VCS);
> + engine = str_to_engine(token);
> + if (append_matching_engines(&engine, &step->bond.mask) != 1)
> + return -1;
> }
>
> return 0;
> @@ -854,26 +915,6 @@ static int parse_working_set(struct working_set *set, char *str)
> return 0;
> }
>
> -static uint64_t engine_list_mask(const char *_str)
> -{
> - uint64_t mask = 0;
> -
> - char *token, *tctx = NULL, *tstart = (char *)_str;
> -
> - while ((token = strtok_r(tstart, "|", &tctx))) {
> - enum intel_engine_id engine = str_to_engine(token);
> -
> - if ((int)engine < 0 || engine == DEFAULT || engine == VCS)
> - return 0;
> -
> - mask |= 1 << engine;
> -
> - tstart = NULL;
> - }
> -
> - return mask;
> -}
> -
> static unsigned long
> allocate_working_set(struct workload *wrk, struct working_set *set);
>
> @@ -1145,18 +1186,19 @@ parse_workload(struct w_arg *arg, unsigned int flags, double scale_dur,
> "Invalid context at step %u!\n",
> nr_steps);
> } else if (nr == 1) {
> - step.bond_mask = engine_list_mask(field);
> - check_arg(step.bond_mask == 0,
> - "Invalid siblings list at step %u!\n",
> - nr_steps);
> + tmp = parse_bond_engines(&step, field);
> + check_arg(tmp < 0,
> + "Invalid siblings list at step %u!\n",
> + nr_steps);
> } else if (nr == 2) {
> - tmp = str_to_engine(field);
> - check_arg(tmp <= 0 ||
> - tmp == VCS ||
> - tmp == DEFAULT,
> + struct intel_engines engines;
> +
> + step.bond.master = str_to_engine(field);
> + check_arg(append_matching_engines(&step.bond.master,
> + &engines) != 1,
> "Invalid master engine at step %u!\n",
> nr_steps);
> - step.bond_master = tmp;
> + free(engines.engines);
> }
>
> nr++;
> @@ -1214,13 +1256,11 @@ parse_workload(struct w_arg *arg, unsigned int flags, double scale_dur,
> if (field) {
> fstart = NULL;
>
> - i = str_to_engine(field);
> - check_arg(i < 0,
> + step.engine = str_to_engine(field);
> + check_arg(!is_valid_engine(&step.engine),
> "Invalid engine id at step %u!\n", nr_steps);
>
> valid++;
> -
> - step.engine = i;
> }
>
> field = strtok_r(fstart, ".", &fctx);
> @@ -1266,7 +1306,7 @@ add_step:
> step.delay = __duration(step.delay, scale_time);
>
> step.idx = nr_steps++;
> - step.request = -1;
> + step.rq_link.next = step.rq_link.prev = NULL;
> steps = realloc(steps, sizeof(step) * nr_steps);
> igt_assert(steps);
>
> @@ -1386,9 +1426,9 @@ add_step:
> static struct workload *
> clone_workload(struct workload *_wrk)
> {
> + int nr_engines = query_engines()->nr_engines;
> struct workload *wrk;
> struct w_step *w;
> - int i;
>
> wrk = malloc(sizeof(*wrk));
> igt_assert(wrk);
> @@ -1423,8 +1463,12 @@ clone_workload(struct workload *_wrk)
> }
> }
>
> - for (i = 0; i < NUM_ENGINES; i++)
> - IGT_INIT_LIST_HEAD(&wrk->requests[i]);
> + wrk->requests = calloc(nr_engines, sizeof(*wrk->requests));
> + igt_assert(wrk->requests);
> + wrk->nrequest = calloc(nr_engines, sizeof(*wrk->nrequest));
> + igt_assert(wrk->nrequest);
> + while (--nr_engines >= 0)
> + IGT_INIT_LIST_HEAD(&wrk->requests[nr_engines]);
>
> return wrk;
> }
> @@ -1451,37 +1495,32 @@ __get_ctx(struct workload *wrk, const struct w_step *w)
> return &wrk->ctx_list[w->context];
> }
>
> -static uint32_t mmio_base(int i915, enum intel_engine_id engine, int gen)
> +static uint32_t mmio_base(int i915, const intel_engine_t *engine, int gen)
> {
> - const char *name;
> + char name[16];
>
> if (gen >= 11)
> return 0;
>
> - switch (engine) {
> - case NUM_ENGINES:
> + switch (engine->engine_class) {
> default:
> return 0;
>
> - case DEFAULT:
> + case DEFAULT_ID:
> case RCS:
> - name = "rcs0";
> + snprintf(name, sizeof(name), "rcs%u", engine->engine_instance);
> break;
> -
> case BCS:
> - name = "bcs0";
> + snprintf(name, sizeof(name), "bcs%u", engine->engine_instance);
> break;
> -
> case VCS:
> - case VCS1:
> - name = "vcs0";
> - break;
> - case VCS2:
> - name = "vcs1";
> + snprintf(name, sizeof(name), "vcs%u", engine->engine_instance);
> break;
> -
> case VECS:
> - name = "vecs0";
> + snprintf(name, sizeof(name), "vecs%u", engine->engine_instance);
> + break;
> + case CCS:
> + snprintf(name, sizeof(name), "ccs%u", engine->engine_instance);
> break;
> }
>
> @@ -1491,7 +1530,7 @@ static uint32_t mmio_base(int i915, enum intel_engine_id engine, int gen)
> static unsigned int create_bb(struct w_step *w, int self)
> {
> const int gen = intel_gen(intel_get_drm_devid(fd));
> - const uint32_t base = mmio_base(fd, w->engine, gen);
> + const uint32_t base = mmio_base(fd, &w->engine, gen);
> #define CS_GPR(x) (base + 0x600 + 8 * (x))
> #define TIMESTAMP (base + 0x3a8)
> const int use_64b = gen >= 8;
> @@ -1574,47 +1613,10 @@ static unsigned int create_bb(struct w_step *w, int self)
> return r;
> }
>
> -static const unsigned int eb_engine_map[NUM_ENGINES] = {
> - [DEFAULT] = I915_EXEC_DEFAULT,
> - [RCS] = I915_EXEC_RENDER,
> - [BCS] = I915_EXEC_BLT,
> - [VCS] = I915_EXEC_BSD,
> - [VCS1] = I915_EXEC_BSD | I915_EXEC_BSD_RING1,
> - [VCS2] = I915_EXEC_BSD | I915_EXEC_BSD_RING2,
> - [VECS] = I915_EXEC_VEBOX
> -};
> -
> static void
> -eb_set_engine(struct drm_i915_gem_execbuffer2 *eb, enum intel_engine_id engine)
> +eb_update_flags(struct workload *wrk, struct w_step *w)
> {
> - eb->flags = eb_engine_map[engine];
> -}
> -
> -static unsigned int
> -find_engine_in_map(struct ctx *ctx, enum intel_engine_id engine)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < ctx->engine_map_count; i++) {
> - if (ctx->engine_map[i] == engine)
> - return i + 1;
> - }
> -
> - igt_assert(ctx->load_balance);
> - return 0;
> -}
> -
> -static void
> -eb_update_flags(struct workload *wrk, struct w_step *w,
> - enum intel_engine_id engine)
> -{
> - struct ctx *ctx = __get_ctx(wrk, w);
> -
> - if (ctx->engine_map)
> - w->i915.eb.flags = find_engine_in_map(ctx, engine);
> - else
> - eb_set_engine(&w->i915.eb, engine);
> -
> + w->i915.eb.flags = w->engine_idx;
> w->i915.eb.flags |= I915_EXEC_HANDLE_LUT;
> w->i915.eb.flags |= I915_EXEC_NO_RELOC;
>
> @@ -1633,19 +1635,9 @@ static struct xe_exec_queue *
> xe_get_eq(struct workload *wrk, const struct w_step *w)
> {
> struct ctx *ctx = __get_ctx(wrk, w);
> - struct xe_exec_queue *eq;
>
> - if (ctx->engine_map) {
> - igt_assert_eq(ctx->xe.nr_queues, 1);
> - igt_assert(ctx->xe.queue_list[0].id);
> - eq = &ctx->xe.queue_list[0];
> - } else {
> - igt_assert(w->engine >= 0 && w->engine < ctx->xe.nr_queues);
> - igt_assert(ctx->xe.queue_list[w->engine].id);
> - eq = &ctx->xe.queue_list[w->engine];
> - }
> -
> - return eq;
> + igt_assert_lt(w->engine_idx, ctx->xe.nr_queues);
> + return &ctx->xe.queue_list[w->engine_idx];
> }
>
> static struct xe_vm *
> @@ -1669,7 +1661,6 @@ static uint32_t alloc_bo(int i915, unsigned long *size)
> static void
> alloc_step_batch(struct workload *wrk, struct w_step *w)
> {
> - enum intel_engine_id engine = w->engine;
> struct dep_entry *dep;
> unsigned int j = 0;
> unsigned int nr_obj = 2 + w->data_deps.nr;
> @@ -1724,7 +1715,7 @@ alloc_step_batch(struct workload *wrk, struct w_step *w)
> w->i915.eb.buffer_count = j + 1;
> w->i915.eb.rsvd1 = get_ctxid(wrk, w);
>
> - eb_update_flags(wrk, w, engine);
> + eb_update_flags(wrk, w);
> #ifdef DEBUG
> printf("%u: %u:|", w->idx, w->i915.eb.buffer_count);
> for (i = 0; i <= j; i++)
> @@ -1853,22 +1844,6 @@ static void vm_destroy(int i915, uint32_t vm_id)
> igt_assert_eq(__vm_destroy(i915, vm_id), 0);
> }
>
> -static unsigned int
> -find_engine(struct i915_engine_class_instance *ci, unsigned int count,
> - enum intel_engine_id engine)
> -{
> - struct i915_engine_class_instance e = get_engine(engine);
> - unsigned int i;
> -
> - for (i = 0; i < count; i++, ci++) {
> - if (!memcmp(&e, ci, sizeof(*ci)))
> - return i;
> - }
> -
> - igt_assert(0);
> - return 0;
> -}
> -
> static struct drm_i915_gem_context_param_sseu get_device_sseu(void)
> {
> struct drm_i915_gem_context_param param = { };
> @@ -1892,7 +1867,7 @@ set_ctx_sseu(struct ctx *ctx, uint64_t slice_mask)
> if (slice_mask == -1)
> slice_mask = device_sseu.slice_mask;
>
> - if (ctx->engine_map && ctx->load_balance) {
> + if (ctx->engine_map.nr_engines && ctx->load_balance) {
> sseu.flags = I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX;
> sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID;
> sseu.engine.engine_instance = 0;
> @@ -2102,9 +2077,8 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
>
> if (w->type == ENGINE_MAP) {
> ctx->engine_map = w->engine_map;
> - ctx->engine_map_count = w->engine_map_count;
> } else if (w->type == LOAD_BALANCE) {
> - if (!ctx->engine_map) {
> + if (!ctx->engine_map.nr_engines) {
> wsim_err("Load balancing needs an engine map!\n");
> return 1;
> }
> @@ -2123,10 +2097,7 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
> ctx->bond_count *
> sizeof(struct bond));
> igt_assert(ctx->bonds);
> - ctx->bonds[ctx->bond_count - 1].mask =
> - w->bond_mask;
> - ctx->bonds[ctx->bond_count - 1].master =
> - w->bond_master;
> + ctx->bonds[ctx->bond_count - 1] = w->bond;
> }
> }
> }
> @@ -2134,7 +2105,7 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
> /*
> * Create and configure contexts.
> */
> - for_each_ctx(ctx, wrk) {
> + __for_each_ctx(ctx, wrk, ctx_idx) {
> struct drm_i915_gem_context_create_ext_setparam ext = {
> .base.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> .param.param = I915_CONTEXT_PARAM_VM,
> @@ -2176,19 +2147,40 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
>
> __configure_context(ctx_id, wrk->prio);
>
> - if (ctx->engine_map) {
> + if (ctx->engine_map.nr_engines) {
> struct i915_context_param_engines *set_engines =
> - alloca0(sizeof_param_engines(ctx->engine_map_count + 1));
> + alloca0(sizeof_param_engines(ctx->engine_map.nr_engines + 1));
> struct i915_context_engines_load_balance *load_balance =
> - alloca0(sizeof_load_balance(ctx->engine_map_count));
> + alloca0(sizeof_load_balance(ctx->engine_map.nr_engines));
> struct drm_i915_gem_context_param param = {
> .ctx_id = ctx_id,
> .param = I915_CONTEXT_PARAM_ENGINES,
> - .size = sizeof_param_engines(ctx->engine_map_count + 1),
> + .size = sizeof_param_engines(ctx->engine_map.nr_engines + 1),
> .value = to_user_pointer(set_engines),
> };
> struct i915_context_engines_bond *last = NULL;
>
> + /* update engine_idx and request_idx */
> + for_each_w_step(w, wrk) {
> + if (w->context != ctx_idx)
> + continue;
> + if (w->type == BATCH) {
> + unsigned int map_idx = 0;
> +
> + if (find_engine_in_map(&w->engine, &ctx->engine_map,
> + &map_idx))
> + /* 0 is virtual, map indexes are shifted by one */
> + w->engine_idx = map_idx + 1;
> + else
> + igt_assert(ctx->load_balance);
> +
> + igt_assert(find_engine_in_map(
> + &ctx->engine_map.engines[map_idx],
> + query_engines(),
> + &w->request_idx));
> + }
> + }
> +
> if (ctx->load_balance) {
> set_engines->extensions =
> to_user_pointer(load_balance);
> @@ -2196,11 +2188,11 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
> load_balance->base.name =
> I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
> load_balance->num_siblings =
> - ctx->engine_map_count;
> + ctx->engine_map.nr_engines;
>
> - for (j = 0; j < ctx->engine_map_count; j++)
> + for (j = 0; j < ctx->engine_map.nr_engines; j++)
> load_balance->engines[j] =
> - get_engine(ctx->engine_map[j]);
> + to_i915_engine_class(&ctx->engine_map.engines[j]);
> }
>
> /* Reserve slot for virtual engine. */
> @@ -2209,34 +2201,31 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
> set_engines->engines[0].engine_instance =
> I915_ENGINE_CLASS_INVALID_NONE;
>
> - for (j = 1; j <= ctx->engine_map_count; j++)
> + for (j = 1; j <= ctx->engine_map.nr_engines; j++)
> set_engines->engines[j] =
> - get_engine(ctx->engine_map[j - 1]);
> + to_i915_engine_class(&ctx->engine_map.engines[j - 1]);
>
> last = NULL;
> for (j = 0; j < ctx->bond_count; j++) {
> - unsigned long mask = ctx->bonds[j].mask;
> + struct intel_engines *mask = &ctx->bonds[j].mask;
> struct i915_context_engines_bond *bond =
> - alloca0(sizeof_engines_bond(__builtin_popcount(mask)));
> + alloca0(sizeof_engines_bond(mask->nr_engines));
> unsigned int b, e;
>
> bond->base.next_extension = to_user_pointer(last);
> bond->base.name = I915_CONTEXT_ENGINES_EXT_BOND;
>
> bond->virtual_index = 0;
> - bond->master = get_engine(ctx->bonds[j].master);
> + bond->master = to_i915_engine_class(&ctx->bonds[j].master);
>
> - for (b = 0, e = 0; mask; e++, mask >>= 1) {
> + for (b = 0, e = 0; e < mask->nr_engines; e++) {
> unsigned int idx;
>
> - if (!(mask & 1))
> - continue;
> + igt_assert(find_engine_in_map(&mask->engines[e],
> + &ctx->engine_map,
> + &idx));
>
> - idx = find_engine(&set_engines->engines[1],
> - ctx->engine_map_count,
> - e);
> - bond->engines[b++] =
> - set_engines->engines[1 + idx];
> + bond->engines[b++] = set_engines->engines[1 + idx];
> }
>
> last = bond;
> @@ -2244,6 +2233,20 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
> load_balance->base.next_extension = to_user_pointer(last);
>
> gem_context_set_param(fd, ¶m);
> + } else {
> + /* update engine_idx and request_idx */
> + for_each_w_step(w, wrk) {
> + if (w->context != ctx_idx)
> + continue;
> + if (w->type == BATCH) {
> + w->engine_idx = to_i915_legacy_ring(&w->engine);
> + resolve_to_physical_engine(&w->engine);
> + igt_assert(find_engine_in_map(
> + &w->engine,
> + query_engines(),
> + &w->request_idx));
> + }
> + }
> }
>
> if (wrk->sseu) {
> @@ -2281,9 +2284,8 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
> continue;
> if (w->type == ENGINE_MAP) {
> ctx->engine_map = w->engine_map;
> - ctx->engine_map_count = w->engine_map_count;
> } else if (w->type == LOAD_BALANCE) {
> - if (!ctx->engine_map) {
> + if (!ctx->engine_map.nr_engines) {
> wsim_err("Load balancing needs an engine map!\n");
> return 1;
> }
> @@ -2292,15 +2294,15 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
> }
>
> /* create exec queue for each referenced engine */
> - if (ctx->engine_map) {
> + if (ctx->engine_map.nr_engines) {
> ctx->xe.nr_queues = 1;
> ctx->xe.queue_list = calloc(ctx->xe.nr_queues, sizeof(*ctx->xe.queue_list));
> igt_assert(ctx->xe.queue_list);
> eq = &ctx->xe.queue_list[ctx->xe.nr_queues - 1];
> - eq->nr_hwes = ctx->engine_map_count;
> + eq->nr_hwes = ctx->engine_map.nr_engines;
> eq->hwe_list = calloc(eq->nr_hwes, sizeof(*eq->hwe_list));
> for (i = 0; i < eq->nr_hwes; ++i) {
> - eq->hwe_list[i] = xe_get_engine(ctx->engine_map[i]);
> + eq->hwe_list[i] = ctx->engine_map.engines[i];
>
> /* check no mixing classes and no duplicates */
> for (int j = 0; j < i; ++j) {
> @@ -2322,8 +2324,10 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
> }
>
> if (verbose > 3)
> - printf("%u ctx[%d] %s [%u:%u:%u]\n",
> - id, ctx_idx, ring_str_map[ctx->engine_map[i]],
> + printf("%u ctx[%d] %s [%d:%d:%d]\n",
> + id, ctx_idx,
> + intel_engine_class_string(
> + ctx->engine_map.engines[i].engine_class),
> eq->hwe_list[i].engine_class,
> eq->hwe_list[i].engine_instance,
> eq->hwe_list[i].gt_id);
> @@ -2331,41 +2335,56 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
>
> xe_exec_queue_create_(ctx, eq);
> } else {
> - int engine_classes[NUM_ENGINES] = {};
> -
> - ctx->xe.nr_queues = NUM_ENGINES;
> - ctx->xe.queue_list = calloc(ctx->xe.nr_queues, sizeof(*ctx->xe.queue_list));
> -
> + /* create engine_map, update engine_idx */
> for_each_w_step(w, wrk) {
> if (w->context != ctx_idx)
> continue;
> - if (w->type == BATCH)
> - engine_classes[w->engine]++;
> + if (w->type == BATCH) {
> + resolve_to_physical_engine(&w->engine);
> + if (!find_engine_in_map(&w->engine, &ctx->engine_map,
> + &w->engine_idx)) {
> + igt_assert_eq(1, append_matching_engines(&w->engine,
> + &ctx->engine_map));
> + w->engine_idx = ctx->engine_map.nr_engines - 1;
> + }
> + }
> }
>
> - for (i = 0; i < NUM_ENGINES; i++) {
> - if (engine_classes[i]) {
> - eq = &ctx->xe.queue_list[i];
> - eq->nr_hwes = 1;
> - eq->hwe_list = calloc(1, sizeof(*eq->hwe_list));
> + /* skip not referenced context */
> + if (!ctx->engine_map.nr_engines)
> + continue;
>
> - if (i == DEFAULT)
> - eq->hwe_list[0] = xe_get_default_engine();
> - else if (i == VCS)
> - eq->hwe_list[0] = xe_get_engine(VCS1);
> - else
> - eq->hwe_list[0] = xe_get_engine(i);
> + ctx->xe.nr_queues = ctx->engine_map.nr_engines;
> + ctx->xe.queue_list = calloc(ctx->xe.nr_queues, sizeof(*ctx->xe.queue_list));
>
> - if (verbose > 3)
> - printf("%u ctx[%d] %s [%u:%u:%u]\n",
> - id, ctx_idx, ring_str_map[i],
> - eq->hwe_list[0].engine_class,
> - eq->hwe_list[0].engine_instance,
> - eq->hwe_list[0].gt_id);
> + for (i = 0; i < ctx->xe.nr_queues; i++) {
> + eq = &ctx->xe.queue_list[i];
> + eq->nr_hwes = 1;
> + eq->hwe_list = calloc(1, sizeof(*eq->hwe_list));
> + eq->hwe_list[0] = ctx->engine_map.engines[i];
>
> - xe_exec_queue_create_(ctx, eq);
> - }
> - engine_classes[i] = 0;
> + if (verbose > 3)
> + printf("%u ctx[%d] %s [%d:%d:%d]\n",
> + id, ctx_idx,
> + intel_engine_class_string(
> + ctx->engine_map.engines[i].engine_class),
> + eq->hwe_list[0].engine_class,
> + eq->hwe_list[0].engine_instance,
> + eq->hwe_list[0].gt_id);
> +
> + xe_exec_queue_create_(ctx, eq);
> + }
> + }
> +
> + /* update request_idx */
> + for_each_w_step(w, wrk) {
> + if (w->context != ctx_idx)
> + continue;
> + if (w->type == BATCH) {
> + igt_assert(find_engine_in_map(
> + &ctx->engine_map.engines[w->engine_idx],
> + query_engines(),
> + &w->request_idx));
> }
> }
> }
> @@ -2577,12 +2596,12 @@ static void do_xe_exec(struct workload *wrk, struct w_step *w)
> }
>
> static void
> -do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine)
> +do_eb(struct workload *wrk, struct w_step *w)
> {
> struct dep_entry *dep;
> unsigned int i;
>
> - eb_update_flags(wrk, w, engine);
> + eb_update_flags(wrk, w);
> update_bb_start(wrk, w);
>
> for_each_dep(dep, w->fence_deps) {
> @@ -2656,7 +2675,6 @@ static void *run_workload(void *data)
> clock_gettime(CLOCK_MONOTONIC, &repeat_start);
>
> for_each_w_step(w, wrk) {
> - enum intel_engine_id engine = w->engine;
> int do_sleep = 0;
>
> if (!wrk->run)
> @@ -2775,15 +2793,14 @@ static void *run_workload(void *data)
> if (is_xe)
> do_xe_exec(wrk, w);
> else
> - do_eb(wrk, w, engine);
> + do_eb(wrk, w);
>
> - if (w->request != -1) {
> + if (w->rq_link.next) {
> igt_list_del(&w->rq_link);
> - wrk->nrequest[w->request]--;
> + wrk->nrequest[w->request_idx]--;
> }
> - w->request = engine;
> - igt_list_add_tail(&w->rq_link, &wrk->requests[engine]);
> - wrk->nrequest[engine]++;
> + igt_list_add_tail(&w->rq_link, &wrk->requests[w->request_idx]);
> + wrk->nrequest[w->request_idx]++;
>
> if (!wrk->run)
> break;
> @@ -2792,17 +2809,16 @@ static void *run_workload(void *data)
> w_step_sync(w);
>
> if (qd_throttle > 0) {
> - while (wrk->nrequest[engine] > qd_throttle) {
> + while (wrk->nrequest[w->request_idx] > qd_throttle) {
> struct w_step *s;
>
> - s = igt_list_first_entry(&wrk->requests[engine],
> + s = igt_list_first_entry(&wrk->requests[w->request_idx],
> s, rq_link);
>
> w_step_sync(s);
>
> - s->request = -1;
> igt_list_del(&s->rq_link);
> - wrk->nrequest[engine]--;
> + wrk->nrequest[w->request_idx]--;
> }
> }
> }
> @@ -2831,7 +2847,7 @@ static void *run_workload(void *data)
> }
> }
>
> - for (int i = 0; i < NUM_ENGINES; i++) {
> + for (int i = query_engines()->nr_engines; --i >= 0;) {
> if (!wrk->nrequest[i])
> continue;
>
You can consider mentioned changes, but overall LGTM, Reviewed-by:
Lukasz Laguna <lukasz.laguna@intel.com>
[-- Attachment #2: Type: text/html, Size: 39236 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH i-g-t 2/2] benchmarks/gem_wsim: Option to list physical engines
2024-01-15 15:44 ` [PATCH i-g-t 2/2] benchmarks/gem_wsim: Option to list physical engines Marcin Bernatowicz
@ 2024-01-24 11:41 ` Laguna, Lukasz
2024-01-24 12:25 ` Tvrtko Ursulin
1 sibling, 0 replies; 11+ messages in thread
From: Laguna, Lukasz @ 2024-01-24 11:41 UTC (permalink / raw)
To: Marcin Bernatowicz, igt-dev
[-- Attachment #1: Type: text/plain, Size: 2972 bytes --]
On 1/15/2024 16:44, Marcin Bernatowicz wrote:
> Added command line option (-l) to list physical engines.
>
> Signed-off-by: Marcin Bernatowicz<marcin.bernatowicz@linux.intel.com>
> ---
> benchmarks/gem_wsim.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 42 insertions(+), 1 deletion(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index e79d26513..aa70b1770 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -2924,6 +2924,7 @@ static void print_help(void)
> " -f <scale> Scale factor for batch durations.\n"
> " -F <scale> Scale factor for delays.\n"
> " -L List GPUs.\n"
> +" -l List physical engines.\n"
> " -D <gpu> One of the GPUs from -L.\n"
> );
> }
> @@ -2983,10 +2984,42 @@ add_workload_arg(struct w_arg *w_args, unsigned int nr_args, char *w_arg,
> return w_args;
> }
>
> +static void list_engines(void)
> +{
> + struct intel_engines *engines = query_engines();
> + int engine_class_count[NUM_ENGINE_CLASSES] = {};
> + unsigned int i;
> +
> + for (i = 0; i < engines->nr_engines; ++i) {
> + igt_assert_lt(engines->engines[i].engine_class, NUM_ENGINE_CLASSES);
> + engine_class_count[engines->engines[i].engine_class]++;
> + }
> +
> + for (i = 0; i < engines->nr_engines; ++i) {
> + if (engine_class_count[engines->engines[i].engine_class] > 1)
> + printf("%s%u",
> + intel_engine_class_string(engines->engines[i].engine_class),
> + engines->engines[i].engine_instance + 1);
> + else
> + printf("%s",
> + intel_engine_class_string(engines->engines[i].engine_class));
> +
> + if (is_xe && engines->engines[i].gt_id)
> + printf("-%u", engines->engines[i].gt_id);
> +
> + if (verbose > 3)
> + printf(" [%d:%d:%d]", engines->engines[i].engine_class,
> + engines->engines[i].engine_instance,
> + engines->engines[i].gt_id);
> + printf("\n");
> + }
> +}
> +
> int main(int argc, char **argv)
> {
> struct igt_device_card card = { };
> bool list_devices_arg = false;
> + bool list_engines_arg = false;
> unsigned int repeat = 1;
> unsigned int clients = 1;
> unsigned int flags = 0;
> @@ -3009,11 +3042,14 @@ int main(int argc, char **argv)
> master_prng = time(NULL);
>
> while ((c = getopt(argc, argv,
> - "LhqvsSdc:r:w:W:a:p:I:f:F:D:")) != -1) {
> + "LlhqvsSdc:r:w:W:a:p:I:f:F:D:")) != -1) {
> switch (c) {
> case 'L':
> list_devices_arg = true;
> break;
> + case 'l':
> + list_engines_arg = true;
> + break;
> case 'D':
> device_arg = strdup(optarg);
> break;
> @@ -3134,6 +3170,11 @@ int main(int argc, char **argv)
> if (is_xe)
> xe_device_get(fd);
>
> + if (list_engines_arg) {
> + list_engines();
> + goto out;
> + }
> +
> if (!nr_w_args) {
> wsim_err("No workload descriptor(s)!\n");
> goto err;
LGTM, Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com>
[-- Attachment #2: Type: text/html, Size: 3621 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH i-g-t 1/2] benchmarks/gem_wsim: Extend engine selection syntax
2024-01-15 15:44 ` [PATCH i-g-t 1/2] " Marcin Bernatowicz
2024-01-24 11:41 ` Laguna, Lukasz
@ 2024-01-24 12:24 ` Tvrtko Ursulin
1 sibling, 0 replies; 11+ messages in thread
From: Tvrtko Ursulin @ 2024-01-24 12:24 UTC (permalink / raw)
To: Marcin Bernatowicz, igt-dev
Hi,
On 15/01/2024 15:44, Marcin Bernatowicz wrote:
> This commit introduces significant changes to the engine selection
> syntax:
> - Dynamically generates the list of available physical engines by
> querying the device.
> - Identifies engines using [class:instance:gt] tuples.
> - Allows specifying engine instance and gt as
> `engine_class[<engine_instance>-<gt_id>]`
> ex. First VCS engine may be specified as VCS, VCS1, and VCS1-0.
> - Adds support for compute engine class (CCS).
> - Maintains 1-based engine instance ids for compatibility with existing
> workload definitions.
> - Each `w_step` now includes an `engine_idx` (populated during prepare
> workload phase), simplifying the run phase with an index in the
> device/context engine map.
> Second index field `request_idx` was introduced to support throttling
> functionality, enabling control over the rate of requests on a given
> engine.
I wanted to have a look but keep getting discouraged by the sheer size
of the patch. Becase when I look at the list of bullet points above I
wonder if it could be split into more manageable (for review) chunks.
Worry is the regression potential given we have no test suite and there
is quite a number of engine selection combos across platforms, drivers
and uapis.
What is your opinion on the splitability?
Regards,
Tvrtko
>
> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> ---
> benchmarks/gem_wsim.c | 788 +++++++++++++++++++++---------------------
> 1 file changed, 402 insertions(+), 386 deletions(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index 955b6799e..e79d26513 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -68,17 +68,6 @@
> #include "xe/xe_ioctl.h"
> #include "xe/xe_spin.h"
>
> -enum intel_engine_id {
> - DEFAULT,
> - RCS,
> - BCS,
> - VCS,
> - VCS1,
> - VCS2,
> - VECS,
> - NUM_ENGINES
> -};
> -
> struct duration {
> unsigned int min, max;
> bool unbound;
> @@ -126,9 +115,16 @@ struct w_arg {
> bool sseu;
> };
>
> +typedef struct drm_xe_engine_class_instance intel_engine_t;
> +
> +struct intel_engines {
> + unsigned int nr_engines;
> + intel_engine_t *engines;
> +};
> +
> struct bond {
> - uint64_t mask;
> - enum intel_engine_id master;
> + struct intel_engines mask;
> + intel_engine_t master;
> };
>
> struct work_buffer_size {
> @@ -153,7 +149,8 @@ struct w_step {
> /* Workload step metadata */
> enum w_type type;
> unsigned int context;
> - unsigned int engine;
> + unsigned int engine_idx;
> + intel_engine_t engine;
> struct duration duration;
> struct deps data_deps;
> struct deps fence_deps;
> @@ -165,15 +162,9 @@ struct w_step {
> int target;
> int throttle;
> int priority;
> - struct {
> - unsigned int engine_map_count;
> - enum intel_engine_id *engine_map;
> - };
> + struct intel_engines engine_map;
> bool load_balance;
> - struct {
> - uint64_t bond_mask;
> - enum intel_engine_id bond_master;
> - };
> + struct bond bond;
> int sseu;
> struct working_set working_set;
> };
> @@ -181,7 +172,7 @@ struct w_step {
> /* Implementation details */
> unsigned int idx;
> struct igt_list_head rq_link;
> - unsigned int request;
> + unsigned int request_idx;
> unsigned int preempt_us;
>
> union {
> @@ -220,8 +211,7 @@ struct xe_exec_queue {
> struct ctx {
> uint32_t id;
> int priority;
> - unsigned int engine_map_count;
> - enum intel_engine_id *engine_map;
> + struct intel_engines engine_map;
> unsigned int bond_count;
> struct bond *bonds;
> bool load_balance;
> @@ -267,8 +257,8 @@ struct workload {
> int sync_timeline;
> uint32_t sync_seqno;
>
> - struct igt_list_head requests[NUM_ENGINES];
> - unsigned int nrequest[NUM_ENGINES];
> + struct igt_list_head *requests;
> + unsigned int *nrequest;
> };
>
> #define __for_each_ctx(__ctx, __wrk, __ctx_idx) \
> @@ -296,16 +286,44 @@ static struct drm_i915_gem_context_param_sseu device_sseu = {
> #define FLAG_DEPSYNC (1<<2)
> #define FLAG_SSEU (1<<3)
>
> -static const char *ring_str_map[NUM_ENGINES] = {
> - [DEFAULT] = "DEFAULT",
> - [RCS] = "RCS",
> - [BCS] = "BCS",
> - [VCS] = "VCS",
> - [VCS1] = "VCS1",
> - [VCS2] = "VCS2",
> - [VECS] = "VECS",
> +enum intel_engine_class {
> + RCS,
> + BCS,
> + VCS,
> + VECS,
> + CCS,
> + NUM_ENGINE_CLASSES,
> };
>
> +_Static_assert(RCS == DRM_XE_ENGINE_CLASS_RENDER, "mismatch");
> +_Static_assert(BCS == DRM_XE_ENGINE_CLASS_COPY, "mismatch");
> +_Static_assert(VCS == DRM_XE_ENGINE_CLASS_VIDEO_DECODE, "mismatch");
> +_Static_assert(VECS == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE, "mismatch");
> +_Static_assert(CCS == DRM_XE_ENGINE_CLASS_COMPUTE, "mismatch");
> +_Static_assert((int)RCS == (int)I915_ENGINE_CLASS_RENDER, "mismatch");
> +_Static_assert((int)BCS == (int)I915_ENGINE_CLASS_COPY, "mismatch");
> +_Static_assert((int)VCS == (int)I915_ENGINE_CLASS_VIDEO, "mismatch");
> +_Static_assert((int)VECS == (int)I915_ENGINE_CLASS_VIDEO_ENHANCE, "mismatch");
> +_Static_assert((int)CCS == (int)I915_ENGINE_CLASS_COMPUTE, "mismatch");
> +
> +static const char *intel_engine_class_string(uint16_t engine_class)
> +{
> + switch (engine_class) {
> + case RCS:
> + return "RCS";
> + case BCS:
> + return "BCS";
> + case VCS:
> + return "VCS";
> + case VECS:
> + return "VECS";
> + case CCS:
> + return "CCS";
> + default:
> + igt_assert(0);
> + }
> +}
> +
> static void w_step_sync(struct w_step *w)
> {
> if (is_xe)
> @@ -521,218 +539,261 @@ out:
> } \
> }
>
> -static int str_to_engine(const char *str)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < ARRAY_SIZE(ring_str_map); i++) {
> - if (!strcasecmp(str, ring_str_map[i]))
> - return i;
> - }
> -
> - return -1;
> -}
> +#define INVALID_ID ((uint16_t)-2)
> +#define DEFAULT_ID ((uint16_t)-1)
>
> -static struct intel_engine_data *query_engines(void)
> +static struct intel_engines *query_engines(void)
> {
> - static struct intel_engine_data engines = {};
> + static struct intel_engines engines = {};
>
> - if (engines.nengines)
> + if (engines.nr_engines)
> return &engines;
>
> if (is_xe) {
> struct drm_xe_engine_class_instance *hwe;
>
> - xe_for_each_engine(fd, hwe) {
> - engines.engines[engines.nengines].class = hwe->engine_class;
> - engines.engines[engines.nengines].instance = hwe->engine_instance;
> - engines.nengines++;
> + engines.engines = calloc(xe_number_engines(fd), sizeof(intel_engine_t));
> + igt_assert(engines.engines);
> + engines.nr_engines = 0;
> + xe_for_each_engine(fd, hwe)
> + engines.engines[engines.nr_engines++] = *hwe;
> + igt_assert(engines.nr_engines);
> + } else {
> + struct intel_engine_data ed = {};
> +
> + ed = intel_engine_list_of_physical(fd);
> + igt_assert(ed.nengines);
> + engines.nr_engines = ed.nengines;
> + engines.engines = calloc(engines.nr_engines, sizeof(intel_engine_t));
> + igt_assert(engines.engines);
> + for (int i = 0; i < ed.nengines; ++i) {
> + engines.engines[i].engine_class = ed.engines[i].class;
> + engines.engines[i].engine_instance = ed.engines[i].instance;
> + engines.engines[i].gt_id = DEFAULT_ID;
> }
> - } else
> - engines = intel_engine_list_of_physical(fd);
> + }
>
> - igt_assert(engines.nengines);
> return &engines;
> }
>
> -static unsigned int num_engines_in_class(enum intel_engine_id class)
> -{
> - const struct intel_engine_data *engines = query_engines();
> - unsigned int i, count = 0;
> +/* engine_class[<engine_instance>-<gt_id>] */
> +static intel_engine_t str_to_engine(const char *str)
> +{
> + intel_engine_t e = {INVALID_ID, DEFAULT_ID, DEFAULT_ID};
> + size_t pos;
> +
> + if (!strcasecmp("DEFAULT", str)) {
> + e.engine_class = DEFAULT_ID;
> + return e;
> + } else if (!strncasecmp("RCS", str, 3)) {
> + e.engine_class = RCS;
> + pos = 3;
> + } else if (!strncasecmp("BCS", str, 3)) {
> + e.engine_class = BCS;
> + pos = 3;
> + } else if (!strncasecmp("VCS", str, 3)) {
> + e.engine_class = VCS;
> + pos = 3;
> + } else if (!strncasecmp("VECS", str, 4)) {
> + e.engine_class = VECS;
> + pos = 4;
> + } else if (!strncasecmp("CCS", str, 3)) {
> + e.engine_class = CCS;
> + pos = 3;
> + } else
> + return (intel_engine_t){INVALID_ID};
> +
> + if (str[pos]) {
> + char *s = strchr(&str[pos], '-');
> + char *endptr = NULL;
> + long id;
> +
> + if (!s || (s && *s != str[pos])) {
> + id = strtol(&str[pos], &endptr, 10);
> + if (endptr == &str[pos] || id < 1 || id >= INVALID_ID)
> + return (intel_engine_t){INVALID_ID};
> + e.engine_instance = id - 1;
> + }
>
> - igt_assert(class == VCS);
> + if (s && *(++s)) {
> + id = strtol(s, &endptr, 10);
> + if (endptr == s || id < 0 || id >= INVALID_ID)
> + return (intel_engine_t){INVALID_ID};
> + e.gt_id = id;
> + }
>
> - for (i = 0; i < engines->nengines; i++) {
> - if (engines->engines[i].class == I915_ENGINE_CLASS_VIDEO)
> - count++;
> + if (endptr && endptr != (str + strlen(str)))
> + return (intel_engine_t){INVALID_ID};
> }
>
> - igt_assert(count);
> - return count;
> + return e;
> }
>
> -static void
> -fill_engines_id_class(enum intel_engine_id *list,
> - enum intel_engine_id class)
> +static bool is_valid_engine(const intel_engine_t *engine)
> {
> - const struct intel_engine_data *engines = query_engines();
> - enum intel_engine_id engine = VCS1;
> - unsigned int i, j = 0;
> -
> - igt_assert(class == VCS);
> - igt_assert(num_engines_in_class(VCS) <= 2);
> -
> - for (i = 0; i < engines->nengines; i++) {
> - if (engines->engines[i].class != I915_ENGINE_CLASS_VIDEO)
> - continue;
> -
> - list[j++] = engine++;
> - }
> + return engine->engine_class != INVALID_ID;
> }
>
> -static unsigned int
> -find_physical_instance(enum intel_engine_id class, unsigned int logical)
> +static bool is_default_engine(const intel_engine_t *engine)
> {
> - const struct intel_engine_data *engines = query_engines();
> - unsigned int i, j = 0;
> -
> - igt_assert(class == VCS);
> -
> - for (i = 0; i < engines->nengines; i++) {
> - if (engines->engines[i].class != I915_ENGINE_CLASS_VIDEO)
> - continue;
> -
> - /* Map logical to physical instances. */
> - if (logical == j++)
> - return engines->engines[i].instance;
> - }
> -
> - igt_assert(0);
> - return 0;
> + return engine->engine_class == DEFAULT_ID &&
> + engine->engine_instance == DEFAULT_ID &&
> + engine->gt_id == DEFAULT_ID;
> }
>
> -static struct i915_engine_class_instance
> -get_engine(enum intel_engine_id engine)
> +static struct i915_engine_class_instance to_i915_engine_class(const intel_engine_t *engine)
> {
> - struct i915_engine_class_instance ci;
> -
> - query_engines();
> + return (struct i915_engine_class_instance){engine->engine_class, engine->engine_instance};
> +}
>
> - switch (engine) {
> +static unsigned int to_i915_legacy_ring(const intel_engine_t *engine)
> +{
> + switch (engine->engine_class) {
> + case DEFAULT_ID:
> + return I915_EXEC_DEFAULT;
> case RCS:
> - ci.engine_class = I915_ENGINE_CLASS_RENDER;
> - ci.engine_instance = 0;
> - break;
> + return I915_EXEC_RENDER;
> case BCS:
> - ci.engine_class = I915_ENGINE_CLASS_COPY;
> - ci.engine_instance = 0;
> - break;
> - case VCS1:
> - case VCS2:
> - ci.engine_class = I915_ENGINE_CLASS_VIDEO;
> - ci.engine_instance = find_physical_instance(VCS, engine - VCS1);
> + return I915_EXEC_BLT;
> + case VCS:
> + if (engine->engine_instance == DEFAULT_ID)
> + return I915_EXEC_BSD;
> + else if (engine->engine_instance == 0)
> + return I915_EXEC_BSD | I915_EXEC_BSD_RING1;
> + else if (engine->engine_instance == 1)
> + return I915_EXEC_BSD | I915_EXEC_BSD_RING2;
> break;
> case VECS:
> - ci.engine_class = I915_ENGINE_CLASS_VIDEO_ENHANCE;
> - ci.engine_instance = 0;
> - break;
> - default:
> - igt_assert(0);
> + return I915_EXEC_VEBOX;
> };
>
> - return ci;
> + igt_assert(0);
> }
>
> -static struct drm_xe_engine_class_instance
> -xe_get_engine(enum intel_engine_id engine)
> +static bool are_equal_engines(const intel_engine_t *e1, const intel_engine_t *e2)
> {
> - struct drm_xe_engine_class_instance hwe = {}, *hwe1;
> - bool found_physical = false;
> -
> - switch (engine) {
> - case RCS:
> - hwe.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
> - break;
> - case BCS:
> - hwe.engine_class = DRM_XE_ENGINE_CLASS_COPY;
> - break;
> - case VCS1:
> - hwe.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
> - break;
> - case VCS2:
> - hwe.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
> - hwe.engine_instance = 1;
> - break;
> - case VECS:
> - hwe.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;
> - break;
> - default:
> - igt_assert(0);
> - };
> + return e1->engine_class == e2->engine_class &&
> + e1->engine_instance == e2->engine_instance &&
> + e1->gt_id == e2->gt_id;
> +}
>
> - xe_for_each_engine(fd, hwe1) {
> - if (hwe.engine_class == hwe1->engine_class &&
> - hwe.engine_instance == hwe1->engine_instance) {
> - hwe = *hwe1;
> - found_physical = true;
> - break;
> +static bool
> +find_engine_in_map(const intel_engine_t *engine, struct intel_engines *engines, unsigned int *idx)
> +{
> + igt_assert(idx);
> + for (unsigned int i = 0; i < engines->nr_engines; ++i)
> + if (are_equal_engines(engine, &engines->engines[i])) {
> + *idx = i;
> + return true;
> }
> - }
>
> - igt_assert(found_physical);
> - return hwe;
> + return false;
> }
>
> -static struct drm_xe_engine_class_instance
> -xe_get_default_engine(void)
> +static bool engine_matches_filter(const intel_engine_t *engine, const intel_engine_t *filter)
> {
> - struct drm_xe_engine_class_instance default_hwe, *hwe;
> + return (filter->engine_class == DEFAULT_ID ||
> + filter->engine_class == engine->engine_class) &&
> + (filter->engine_instance == DEFAULT_ID ||
> + filter->engine_instance == engine->engine_instance) &&
> + (filter->gt_id == DEFAULT_ID ||
> + filter->gt_id == engine->gt_id);
> +}
>
> - /* select RCS0 | CCS0 or first available engine */
> - default_hwe = xe_engine(fd, 0)->instance;
> - xe_for_each_engine(fd, hwe) {
> - if ((hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
> - hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) &&
> - hwe->engine_instance == 0) {
> - default_hwe = *hwe;
> - break;
> - }
> +#define for_each_matching_engine(__engine, __filter, __engines) \
> + for (unsigned int __i = 0; __i < __engines->nr_engines && \
> + (__engine = &__engines->engines[__i]); __i++) \
> + for_if(engine_matches_filter(__engine, __filter))
> +
> +static unsigned int
> +append_matching_engines(const intel_engine_t *filter, struct intel_engines *engines)
> +{
> + unsigned int prev_nr_engines;
> + struct intel_engines *all = query_engines();
> + intel_engine_t *engine;
> +
> + igt_assert(engines);
> + prev_nr_engines = engines->nr_engines;
> +
> + for_each_matching_engine(engine, filter, all) {
> + engines->nr_engines++;
> + engines->engines = realloc(engines->engines,
> + engines->nr_engines * sizeof(intel_engine_t));
> + igt_assert(engines->engines);
> + engines->engines[engines->nr_engines - 1] = *engine;
> }
>
> - return default_hwe;
> + return engines->nr_engines - prev_nr_engines;
> +}
> +
> +static intel_engine_t get_default_engine(void)
> +{
> + struct intel_engines *all_engines = query_engines();
> + const intel_engine_t filters[] = {
> + {RCS, DEFAULT_ID, DEFAULT_ID},
> + {CCS, DEFAULT_ID, DEFAULT_ID},
> + {DEFAULT_ID, DEFAULT_ID, DEFAULT_ID},
> + {INVALID_ID}
> + }, *filter, *default_engine;
> +
> + for (filter = filters; is_valid_engine(filter); filter++)
> + for_each_matching_engine(default_engine, filter, all_engines)
> + return *default_engine;
> +
> + igt_assert(0);
> +}
> +
> +static intel_engine_t resolve_to_physical_engine_(const intel_engine_t *engine)
> +{
> + struct intel_engines *all_engines = query_engines();
> + intel_engine_t *resolved;
> +
> + igt_assert(engine);
> + if (is_default_engine(engine))
> + return get_default_engine();
> +
> + for_each_matching_engine(resolved, engine, all_engines)
> + return *resolved;
> +
> + return (intel_engine_t){INVALID_ID};
> +}
> +
> +static void resolve_to_physical_engine(intel_engine_t *engine)
> +{
> + *engine = resolve_to_physical_engine_(engine);
> + igt_assert(is_valid_engine(engine));
> }
>
> static int parse_engine_map(struct w_step *step, const char *_str)
> {
> char *token, *tctx = NULL, *tstart = (char *)_str;
> + intel_engine_t engine;
>
> while ((token = strtok_r(tstart, "|", &tctx))) {
> - enum intel_engine_id engine;
> - unsigned int add;
> -
> tstart = NULL;
>
> - if (!strcmp(token, "DEFAULT"))
> + engine = str_to_engine(token);
> + if (!is_valid_engine(&engine) || is_default_engine(&engine))
> return -1;
>
> - engine = str_to_engine(token);
> - if ((int)engine < 0)
> + if (!append_matching_engines(&engine, &step->engine_map))
> return -1;
> + }
> +
> + return 0;
> +}
>
> - if (engine != VCS && engine != VCS1 && engine != VCS2 &&
> - engine != RCS)
> - return -1; /* TODO */
> +static int parse_bond_engines(struct w_step *step, const char *_str)
> +{
> + char *token, *tctx = NULL, *tstart = (char *)_str;
> + intel_engine_t engine;
>
> - add = engine == VCS ? num_engines_in_class(VCS) : 1;
> - step->engine_map_count += add;
> - step->engine_map = realloc(step->engine_map,
> - step->engine_map_count *
> - sizeof(step->engine_map[0]));
> + while ((token = strtok_r(tstart, "|", &tctx))) {
> + tstart = NULL;
>
> - if (engine != VCS)
> - step->engine_map[step->engine_map_count - add] = engine;
> - else
> - fill_engines_id_class(&step->engine_map[step->engine_map_count - add], VCS);
> + engine = str_to_engine(token);
> + if (append_matching_engines(&engine, &step->bond.mask) != 1)
> + return -1;
> }
>
> return 0;
> @@ -854,26 +915,6 @@ static int parse_working_set(struct working_set *set, char *str)
> return 0;
> }
>
> -static uint64_t engine_list_mask(const char *_str)
> -{
> - uint64_t mask = 0;
> -
> - char *token, *tctx = NULL, *tstart = (char *)_str;
> -
> - while ((token = strtok_r(tstart, "|", &tctx))) {
> - enum intel_engine_id engine = str_to_engine(token);
> -
> - if ((int)engine < 0 || engine == DEFAULT || engine == VCS)
> - return 0;
> -
> - mask |= 1 << engine;
> -
> - tstart = NULL;
> - }
> -
> - return mask;
> -}
> -
> static unsigned long
> allocate_working_set(struct workload *wrk, struct working_set *set);
>
> @@ -1145,18 +1186,19 @@ parse_workload(struct w_arg *arg, unsigned int flags, double scale_dur,
> "Invalid context at step %u!\n",
> nr_steps);
> } else if (nr == 1) {
> - step.bond_mask = engine_list_mask(field);
> - check_arg(step.bond_mask == 0,
> - "Invalid siblings list at step %u!\n",
> - nr_steps);
> + tmp = parse_bond_engines(&step, field);
> + check_arg(tmp < 0,
> + "Invalid siblings list at step %u!\n",
> + nr_steps);
> } else if (nr == 2) {
> - tmp = str_to_engine(field);
> - check_arg(tmp <= 0 ||
> - tmp == VCS ||
> - tmp == DEFAULT,
> + struct intel_engines engines;
> +
> + step.bond.master = str_to_engine(field);
> + check_arg(append_matching_engines(&step.bond.master,
> + &engines) != 1,
> "Invalid master engine at step %u!\n",
> nr_steps);
> - step.bond_master = tmp;
> + free(engines.engines);
> }
>
> nr++;
> @@ -1214,13 +1256,11 @@ parse_workload(struct w_arg *arg, unsigned int flags, double scale_dur,
> if (field) {
> fstart = NULL;
>
> - i = str_to_engine(field);
> - check_arg(i < 0,
> + step.engine = str_to_engine(field);
> + check_arg(!is_valid_engine(&step.engine),
> "Invalid engine id at step %u!\n", nr_steps);
>
> valid++;
> -
> - step.engine = i;
> }
>
> field = strtok_r(fstart, ".", &fctx);
> @@ -1266,7 +1306,7 @@ add_step:
> step.delay = __duration(step.delay, scale_time);
>
> step.idx = nr_steps++;
> - step.request = -1;
> + step.rq_link.next = step.rq_link.prev = NULL;
> steps = realloc(steps, sizeof(step) * nr_steps);
> igt_assert(steps);
>
> @@ -1386,9 +1426,9 @@ add_step:
> static struct workload *
> clone_workload(struct workload *_wrk)
> {
> + int nr_engines = query_engines()->nr_engines;
> struct workload *wrk;
> struct w_step *w;
> - int i;
>
> wrk = malloc(sizeof(*wrk));
> igt_assert(wrk);
> @@ -1423,8 +1463,12 @@ clone_workload(struct workload *_wrk)
> }
> }
>
> - for (i = 0; i < NUM_ENGINES; i++)
> - IGT_INIT_LIST_HEAD(&wrk->requests[i]);
> + wrk->requests = calloc(nr_engines, sizeof(*wrk->requests));
> + igt_assert(wrk->requests);
> + wrk->nrequest = calloc(nr_engines, sizeof(*wrk->nrequest));
> + igt_assert(wrk->nrequest);
> + while (--nr_engines >= 0)
> + IGT_INIT_LIST_HEAD(&wrk->requests[nr_engines]);
>
> return wrk;
> }
> @@ -1451,37 +1495,32 @@ __get_ctx(struct workload *wrk, const struct w_step *w)
> return &wrk->ctx_list[w->context];
> }
>
> -static uint32_t mmio_base(int i915, enum intel_engine_id engine, int gen)
> +static uint32_t mmio_base(int i915, const intel_engine_t *engine, int gen)
> {
> - const char *name;
> + char name[16];
>
> if (gen >= 11)
> return 0;
>
> - switch (engine) {
> - case NUM_ENGINES:
> + switch (engine->engine_class) {
> default:
> return 0;
>
> - case DEFAULT:
> + case DEFAULT_ID:
> case RCS:
> - name = "rcs0";
> + snprintf(name, sizeof(name), "rcs%u", engine->engine_instance);
> break;
> -
> case BCS:
> - name = "bcs0";
> + snprintf(name, sizeof(name), "bcs%u", engine->engine_instance);
> break;
> -
> case VCS:
> - case VCS1:
> - name = "vcs0";
> - break;
> - case VCS2:
> - name = "vcs1";
> + snprintf(name, sizeof(name), "vcs%u", engine->engine_instance);
> break;
> -
> case VECS:
> - name = "vecs0";
> + snprintf(name, sizeof(name), "vecs%u", engine->engine_instance);
> + break;
> + case CCS:
> + snprintf(name, sizeof(name), "ccs%u", engine->engine_instance);
> break;
> }
>
> @@ -1491,7 +1530,7 @@ static uint32_t mmio_base(int i915, enum intel_engine_id engine, int gen)
> static unsigned int create_bb(struct w_step *w, int self)
> {
> const int gen = intel_gen(intel_get_drm_devid(fd));
> - const uint32_t base = mmio_base(fd, w->engine, gen);
> + const uint32_t base = mmio_base(fd, &w->engine, gen);
> #define CS_GPR(x) (base + 0x600 + 8 * (x))
> #define TIMESTAMP (base + 0x3a8)
> const int use_64b = gen >= 8;
> @@ -1574,47 +1613,10 @@ static unsigned int create_bb(struct w_step *w, int self)
> return r;
> }
>
> -static const unsigned int eb_engine_map[NUM_ENGINES] = {
> - [DEFAULT] = I915_EXEC_DEFAULT,
> - [RCS] = I915_EXEC_RENDER,
> - [BCS] = I915_EXEC_BLT,
> - [VCS] = I915_EXEC_BSD,
> - [VCS1] = I915_EXEC_BSD | I915_EXEC_BSD_RING1,
> - [VCS2] = I915_EXEC_BSD | I915_EXEC_BSD_RING2,
> - [VECS] = I915_EXEC_VEBOX
> -};
> -
> static void
> -eb_set_engine(struct drm_i915_gem_execbuffer2 *eb, enum intel_engine_id engine)
> +eb_update_flags(struct workload *wrk, struct w_step *w)
> {
> - eb->flags = eb_engine_map[engine];
> -}
> -
> -static unsigned int
> -find_engine_in_map(struct ctx *ctx, enum intel_engine_id engine)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < ctx->engine_map_count; i++) {
> - if (ctx->engine_map[i] == engine)
> - return i + 1;
> - }
> -
> - igt_assert(ctx->load_balance);
> - return 0;
> -}
> -
> -static void
> -eb_update_flags(struct workload *wrk, struct w_step *w,
> - enum intel_engine_id engine)
> -{
> - struct ctx *ctx = __get_ctx(wrk, w);
> -
> - if (ctx->engine_map)
> - w->i915.eb.flags = find_engine_in_map(ctx, engine);
> - else
> - eb_set_engine(&w->i915.eb, engine);
> -
> + w->i915.eb.flags = w->engine_idx;
> w->i915.eb.flags |= I915_EXEC_HANDLE_LUT;
> w->i915.eb.flags |= I915_EXEC_NO_RELOC;
>
> @@ -1633,19 +1635,9 @@ static struct xe_exec_queue *
> xe_get_eq(struct workload *wrk, const struct w_step *w)
> {
> struct ctx *ctx = __get_ctx(wrk, w);
> - struct xe_exec_queue *eq;
>
> - if (ctx->engine_map) {
> - igt_assert_eq(ctx->xe.nr_queues, 1);
> - igt_assert(ctx->xe.queue_list[0].id);
> - eq = &ctx->xe.queue_list[0];
> - } else {
> - igt_assert(w->engine >= 0 && w->engine < ctx->xe.nr_queues);
> - igt_assert(ctx->xe.queue_list[w->engine].id);
> - eq = &ctx->xe.queue_list[w->engine];
> - }
> -
> - return eq;
> + igt_assert_lt(w->engine_idx, ctx->xe.nr_queues);
> + return &ctx->xe.queue_list[w->engine_idx];
> }
>
> static struct xe_vm *
> @@ -1669,7 +1661,6 @@ static uint32_t alloc_bo(int i915, unsigned long *size)
> static void
> alloc_step_batch(struct workload *wrk, struct w_step *w)
> {
> - enum intel_engine_id engine = w->engine;
> struct dep_entry *dep;
> unsigned int j = 0;
> unsigned int nr_obj = 2 + w->data_deps.nr;
> @@ -1724,7 +1715,7 @@ alloc_step_batch(struct workload *wrk, struct w_step *w)
> w->i915.eb.buffer_count = j + 1;
> w->i915.eb.rsvd1 = get_ctxid(wrk, w);
>
> - eb_update_flags(wrk, w, engine);
> + eb_update_flags(wrk, w);
> #ifdef DEBUG
> printf("%u: %u:|", w->idx, w->i915.eb.buffer_count);
> for (i = 0; i <= j; i++)
> @@ -1853,22 +1844,6 @@ static void vm_destroy(int i915, uint32_t vm_id)
> igt_assert_eq(__vm_destroy(i915, vm_id), 0);
> }
>
> -static unsigned int
> -find_engine(struct i915_engine_class_instance *ci, unsigned int count,
> - enum intel_engine_id engine)
> -{
> - struct i915_engine_class_instance e = get_engine(engine);
> - unsigned int i;
> -
> - for (i = 0; i < count; i++, ci++) {
> - if (!memcmp(&e, ci, sizeof(*ci)))
> - return i;
> - }
> -
> - igt_assert(0);
> - return 0;
> -}
> -
> static struct drm_i915_gem_context_param_sseu get_device_sseu(void)
> {
> struct drm_i915_gem_context_param param = { };
> @@ -1892,7 +1867,7 @@ set_ctx_sseu(struct ctx *ctx, uint64_t slice_mask)
> if (slice_mask == -1)
> slice_mask = device_sseu.slice_mask;
>
> - if (ctx->engine_map && ctx->load_balance) {
> + if (ctx->engine_map.nr_engines && ctx->load_balance) {
> sseu.flags = I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX;
> sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID;
> sseu.engine.engine_instance = 0;
> @@ -2102,9 +2077,8 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
>
> if (w->type == ENGINE_MAP) {
> ctx->engine_map = w->engine_map;
> - ctx->engine_map_count = w->engine_map_count;
> } else if (w->type == LOAD_BALANCE) {
> - if (!ctx->engine_map) {
> + if (!ctx->engine_map.nr_engines) {
> wsim_err("Load balancing needs an engine map!\n");
> return 1;
> }
> @@ -2123,10 +2097,7 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
> ctx->bond_count *
> sizeof(struct bond));
> igt_assert(ctx->bonds);
> - ctx->bonds[ctx->bond_count - 1].mask =
> - w->bond_mask;
> - ctx->bonds[ctx->bond_count - 1].master =
> - w->bond_master;
> + ctx->bonds[ctx->bond_count - 1] = w->bond;
> }
> }
> }
> @@ -2134,7 +2105,7 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
> /*
> * Create and configure contexts.
> */
> - for_each_ctx(ctx, wrk) {
> + __for_each_ctx(ctx, wrk, ctx_idx) {
> struct drm_i915_gem_context_create_ext_setparam ext = {
> .base.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> .param.param = I915_CONTEXT_PARAM_VM,
> @@ -2176,19 +2147,40 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
>
> __configure_context(ctx_id, wrk->prio);
>
> - if (ctx->engine_map) {
> + if (ctx->engine_map.nr_engines) {
> struct i915_context_param_engines *set_engines =
> - alloca0(sizeof_param_engines(ctx->engine_map_count + 1));
> + alloca0(sizeof_param_engines(ctx->engine_map.nr_engines + 1));
> struct i915_context_engines_load_balance *load_balance =
> - alloca0(sizeof_load_balance(ctx->engine_map_count));
> + alloca0(sizeof_load_balance(ctx->engine_map.nr_engines));
> struct drm_i915_gem_context_param param = {
> .ctx_id = ctx_id,
> .param = I915_CONTEXT_PARAM_ENGINES,
> - .size = sizeof_param_engines(ctx->engine_map_count + 1),
> + .size = sizeof_param_engines(ctx->engine_map.nr_engines + 1),
> .value = to_user_pointer(set_engines),
> };
> struct i915_context_engines_bond *last = NULL;
>
> + /* update engine_idx and request_idx */
> + for_each_w_step(w, wrk) {
> + if (w->context != ctx_idx)
> + continue;
> + if (w->type == BATCH) {
> + unsigned int map_idx = 0;
> +
> + if (find_engine_in_map(&w->engine, &ctx->engine_map,
> + &map_idx))
> + /* 0 is virtual, map indexes are shifted by one */
> + w->engine_idx = map_idx + 1;
> + else
> + igt_assert(ctx->load_balance);
> +
> + igt_assert(find_engine_in_map(
> + &ctx->engine_map.engines[map_idx],
> + query_engines(),
> + &w->request_idx));
> + }
> + }
> +
> if (ctx->load_balance) {
> set_engines->extensions =
> to_user_pointer(load_balance);
> @@ -2196,11 +2188,11 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
> load_balance->base.name =
> I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
> load_balance->num_siblings =
> - ctx->engine_map_count;
> + ctx->engine_map.nr_engines;
>
> - for (j = 0; j < ctx->engine_map_count; j++)
> + for (j = 0; j < ctx->engine_map.nr_engines; j++)
> load_balance->engines[j] =
> - get_engine(ctx->engine_map[j]);
> + to_i915_engine_class(&ctx->engine_map.engines[j]);
> }
>
> /* Reserve slot for virtual engine. */
> @@ -2209,34 +2201,31 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
> set_engines->engines[0].engine_instance =
> I915_ENGINE_CLASS_INVALID_NONE;
>
> - for (j = 1; j <= ctx->engine_map_count; j++)
> + for (j = 1; j <= ctx->engine_map.nr_engines; j++)
> set_engines->engines[j] =
> - get_engine(ctx->engine_map[j - 1]);
> + to_i915_engine_class(&ctx->engine_map.engines[j - 1]);
>
> last = NULL;
> for (j = 0; j < ctx->bond_count; j++) {
> - unsigned long mask = ctx->bonds[j].mask;
> + struct intel_engines *mask = &ctx->bonds[j].mask;
> struct i915_context_engines_bond *bond =
> - alloca0(sizeof_engines_bond(__builtin_popcount(mask)));
> + alloca0(sizeof_engines_bond(mask->nr_engines));
> unsigned int b, e;
>
> bond->base.next_extension = to_user_pointer(last);
> bond->base.name = I915_CONTEXT_ENGINES_EXT_BOND;
>
> bond->virtual_index = 0;
> - bond->master = get_engine(ctx->bonds[j].master);
> + bond->master = to_i915_engine_class(&ctx->bonds[j].master);
>
> - for (b = 0, e = 0; mask; e++, mask >>= 1) {
> + for (b = 0, e = 0; e < mask->nr_engines; e++) {
> unsigned int idx;
>
> - if (!(mask & 1))
> - continue;
> + igt_assert(find_engine_in_map(&mask->engines[e],
> + &ctx->engine_map,
> + &idx));
>
> - idx = find_engine(&set_engines->engines[1],
> - ctx->engine_map_count,
> - e);
> - bond->engines[b++] =
> - set_engines->engines[1 + idx];
> + bond->engines[b++] = set_engines->engines[1 + idx];
> }
>
> last = bond;
> @@ -2244,6 +2233,20 @@ static int prepare_contexts(unsigned int id, struct workload *wrk)
> load_balance->base.next_extension = to_user_pointer(last);
>
> gem_context_set_param(fd, ¶m);
> + } else {
> + /* update engine_idx and request_idx */
> + for_each_w_step(w, wrk) {
> + if (w->context != ctx_idx)
> + continue;
> + if (w->type == BATCH) {
> + w->engine_idx = to_i915_legacy_ring(&w->engine);
> + resolve_to_physical_engine(&w->engine);
> + igt_assert(find_engine_in_map(
> + &w->engine,
> + query_engines(),
> + &w->request_idx));
> + }
> + }
> }
>
> if (wrk->sseu) {
> @@ -2281,9 +2284,8 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
> continue;
> if (w->type == ENGINE_MAP) {
> ctx->engine_map = w->engine_map;
> - ctx->engine_map_count = w->engine_map_count;
> } else if (w->type == LOAD_BALANCE) {
> - if (!ctx->engine_map) {
> + if (!ctx->engine_map.nr_engines) {
> wsim_err("Load balancing needs an engine map!\n");
> return 1;
> }
> @@ -2292,15 +2294,15 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
> }
>
> /* create exec queue for each referenced engine */
> - if (ctx->engine_map) {
> + if (ctx->engine_map.nr_engines) {
> ctx->xe.nr_queues = 1;
> ctx->xe.queue_list = calloc(ctx->xe.nr_queues, sizeof(*ctx->xe.queue_list));
> igt_assert(ctx->xe.queue_list);
> eq = &ctx->xe.queue_list[ctx->xe.nr_queues - 1];
> - eq->nr_hwes = ctx->engine_map_count;
> + eq->nr_hwes = ctx->engine_map.nr_engines;
> eq->hwe_list = calloc(eq->nr_hwes, sizeof(*eq->hwe_list));
> for (i = 0; i < eq->nr_hwes; ++i) {
> - eq->hwe_list[i] = xe_get_engine(ctx->engine_map[i]);
> + eq->hwe_list[i] = ctx->engine_map.engines[i];
>
> /* check no mixing classes and no duplicates */
> for (int j = 0; j < i; ++j) {
> @@ -2322,8 +2324,10 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
> }
>
> if (verbose > 3)
> - printf("%u ctx[%d] %s [%u:%u:%u]\n",
> - id, ctx_idx, ring_str_map[ctx->engine_map[i]],
> + printf("%u ctx[%d] %s [%d:%d:%d]\n",
> + id, ctx_idx,
> + intel_engine_class_string(
> + ctx->engine_map.engines[i].engine_class),
> eq->hwe_list[i].engine_class,
> eq->hwe_list[i].engine_instance,
> eq->hwe_list[i].gt_id);
> @@ -2331,41 +2335,56 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk)
>
> xe_exec_queue_create_(ctx, eq);
> } else {
> - int engine_classes[NUM_ENGINES] = {};
> -
> - ctx->xe.nr_queues = NUM_ENGINES;
> - ctx->xe.queue_list = calloc(ctx->xe.nr_queues, sizeof(*ctx->xe.queue_list));
> -
> + /* create engine_map, update engine_idx */
> for_each_w_step(w, wrk) {
> if (w->context != ctx_idx)
> continue;
> - if (w->type == BATCH)
> - engine_classes[w->engine]++;
> + if (w->type == BATCH) {
> + resolve_to_physical_engine(&w->engine);
> + if (!find_engine_in_map(&w->engine, &ctx->engine_map,
> + &w->engine_idx)) {
> + igt_assert_eq(1, append_matching_engines(&w->engine,
> + &ctx->engine_map));
> + w->engine_idx = ctx->engine_map.nr_engines - 1;
> + }
> + }
> }
>
> - for (i = 0; i < NUM_ENGINES; i++) {
> - if (engine_classes[i]) {
> - eq = &ctx->xe.queue_list[i];
> - eq->nr_hwes = 1;
> - eq->hwe_list = calloc(1, sizeof(*eq->hwe_list));
> + /* skip not referenced context */
> + if (!ctx->engine_map.nr_engines)
> + continue;
>
> - if (i == DEFAULT)
> - eq->hwe_list[0] = xe_get_default_engine();
> - else if (i == VCS)
> - eq->hwe_list[0] = xe_get_engine(VCS1);
> - else
> - eq->hwe_list[0] = xe_get_engine(i);
> + ctx->xe.nr_queues = ctx->engine_map.nr_engines;
> + ctx->xe.queue_list = calloc(ctx->xe.nr_queues, sizeof(*ctx->xe.queue_list));
>
> - if (verbose > 3)
> - printf("%u ctx[%d] %s [%u:%u:%u]\n",
> - id, ctx_idx, ring_str_map[i],
> - eq->hwe_list[0].engine_class,
> - eq->hwe_list[0].engine_instance,
> - eq->hwe_list[0].gt_id);
> + for (i = 0; i < ctx->xe.nr_queues; i++) {
> + eq = &ctx->xe.queue_list[i];
> + eq->nr_hwes = 1;
> + eq->hwe_list = calloc(1, sizeof(*eq->hwe_list));
> + eq->hwe_list[0] = ctx->engine_map.engines[i];
>
> - xe_exec_queue_create_(ctx, eq);
> - }
> - engine_classes[i] = 0;
> + if (verbose > 3)
> + printf("%u ctx[%d] %s [%d:%d:%d]\n",
> + id, ctx_idx,
> + intel_engine_class_string(
> + ctx->engine_map.engines[i].engine_class),
> + eq->hwe_list[0].engine_class,
> + eq->hwe_list[0].engine_instance,
> + eq->hwe_list[0].gt_id);
> +
> + xe_exec_queue_create_(ctx, eq);
> + }
> + }
> +
> + /* update request_idx */
> + for_each_w_step(w, wrk) {
> + if (w->context != ctx_idx)
> + continue;
> + if (w->type == BATCH) {
> + igt_assert(find_engine_in_map(
> + &ctx->engine_map.engines[w->engine_idx],
> + query_engines(),
> + &w->request_idx));
> }
> }
> }
> @@ -2577,12 +2596,12 @@ static void do_xe_exec(struct workload *wrk, struct w_step *w)
> }
>
> static void
> -do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine)
> +do_eb(struct workload *wrk, struct w_step *w)
> {
> struct dep_entry *dep;
> unsigned int i;
>
> - eb_update_flags(wrk, w, engine);
> + eb_update_flags(wrk, w);
> update_bb_start(wrk, w);
>
> for_each_dep(dep, w->fence_deps) {
> @@ -2656,7 +2675,6 @@ static void *run_workload(void *data)
> clock_gettime(CLOCK_MONOTONIC, &repeat_start);
>
> for_each_w_step(w, wrk) {
> - enum intel_engine_id engine = w->engine;
> int do_sleep = 0;
>
> if (!wrk->run)
> @@ -2775,15 +2793,14 @@ static void *run_workload(void *data)
> if (is_xe)
> do_xe_exec(wrk, w);
> else
> - do_eb(wrk, w, engine);
> + do_eb(wrk, w);
>
> - if (w->request != -1) {
> + if (w->rq_link.next) {
> igt_list_del(&w->rq_link);
> - wrk->nrequest[w->request]--;
> + wrk->nrequest[w->request_idx]--;
> }
> - w->request = engine;
> - igt_list_add_tail(&w->rq_link, &wrk->requests[engine]);
> - wrk->nrequest[engine]++;
> + igt_list_add_tail(&w->rq_link, &wrk->requests[w->request_idx]);
> + wrk->nrequest[w->request_idx]++;
>
> if (!wrk->run)
> break;
> @@ -2792,17 +2809,16 @@ static void *run_workload(void *data)
> w_step_sync(w);
>
> if (qd_throttle > 0) {
> - while (wrk->nrequest[engine] > qd_throttle) {
> + while (wrk->nrequest[w->request_idx] > qd_throttle) {
> struct w_step *s;
>
> - s = igt_list_first_entry(&wrk->requests[engine],
> + s = igt_list_first_entry(&wrk->requests[w->request_idx],
> s, rq_link);
>
> w_step_sync(s);
>
> - s->request = -1;
> igt_list_del(&s->rq_link);
> - wrk->nrequest[engine]--;
> + wrk->nrequest[w->request_idx]--;
> }
> }
> }
> @@ -2831,7 +2847,7 @@ static void *run_workload(void *data)
> }
> }
>
> - for (int i = 0; i < NUM_ENGINES; i++) {
> + for (int i = query_engines()->nr_engines; --i >= 0;) {
> if (!wrk->nrequest[i])
> continue;
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH i-g-t 2/2] benchmarks/gem_wsim: Option to list physical engines
2024-01-15 15:44 ` [PATCH i-g-t 2/2] benchmarks/gem_wsim: Option to list physical engines Marcin Bernatowicz
2024-01-24 11:41 ` Laguna, Lukasz
@ 2024-01-24 12:25 ` Tvrtko Ursulin
2024-04-17 8:22 ` Bernatowicz, Marcin
1 sibling, 1 reply; 11+ messages in thread
From: Tvrtko Ursulin @ 2024-01-24 12:25 UTC (permalink / raw)
To: Marcin Bernatowicz, igt-dev
On 15/01/2024 15:44, Marcin Bernatowicz wrote:
> Added command line option (-l) to list physical engines.
What is the use case and could you paste the example output please (both
drivers if possible)?
Regards,
Tvrtko
> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> ---
> benchmarks/gem_wsim.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 42 insertions(+), 1 deletion(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index e79d26513..aa70b1770 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -2924,6 +2924,7 @@ static void print_help(void)
> " -f <scale> Scale factor for batch durations.\n"
> " -F <scale> Scale factor for delays.\n"
> " -L List GPUs.\n"
> +" -l List physical engines.\n"
> " -D <gpu> One of the GPUs from -L.\n"
> );
> }
> @@ -2983,10 +2984,42 @@ add_workload_arg(struct w_arg *w_args, unsigned int nr_args, char *w_arg,
> return w_args;
> }
>
> +static void list_engines(void)
> +{
> + struct intel_engines *engines = query_engines();
> + int engine_class_count[NUM_ENGINE_CLASSES] = {};
> + unsigned int i;
> +
> + for (i = 0; i < engines->nr_engines; ++i) {
> + igt_assert_lt(engines->engines[i].engine_class, NUM_ENGINE_CLASSES);
> + engine_class_count[engines->engines[i].engine_class]++;
> + }
> +
> + for (i = 0; i < engines->nr_engines; ++i) {
> + if (engine_class_count[engines->engines[i].engine_class] > 1)
> + printf("%s%u",
> + intel_engine_class_string(engines->engines[i].engine_class),
> + engines->engines[i].engine_instance + 1);
> + else
> + printf("%s",
> + intel_engine_class_string(engines->engines[i].engine_class));
> +
> + if (is_xe && engines->engines[i].gt_id)
> + printf("-%u", engines->engines[i].gt_id);
> +
> + if (verbose > 3)
> + printf(" [%d:%d:%d]", engines->engines[i].engine_class,
> + engines->engines[i].engine_instance,
> + engines->engines[i].gt_id);
> + printf("\n");
> + }
> +}
> +
> int main(int argc, char **argv)
> {
> struct igt_device_card card = { };
> bool list_devices_arg = false;
> + bool list_engines_arg = false;
> unsigned int repeat = 1;
> unsigned int clients = 1;
> unsigned int flags = 0;
> @@ -3009,11 +3042,14 @@ int main(int argc, char **argv)
> master_prng = time(NULL);
>
> while ((c = getopt(argc, argv,
> - "LhqvsSdc:r:w:W:a:p:I:f:F:D:")) != -1) {
> + "LlhqvsSdc:r:w:W:a:p:I:f:F:D:")) != -1) {
> switch (c) {
> case 'L':
> list_devices_arg = true;
> break;
> + case 'l':
> + list_engines_arg = true;
> + break;
> case 'D':
> device_arg = strdup(optarg);
> break;
> @@ -3134,6 +3170,11 @@ int main(int argc, char **argv)
> if (is_xe)
> xe_device_get(fd);
>
> + if (list_engines_arg) {
> + list_engines();
> + goto out;
> + }
> +
> if (!nr_w_args) {
> wsim_err("No workload descriptor(s)!\n");
> goto err;
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH i-g-t 2/2] benchmarks/gem_wsim: Option to list physical engines
2024-01-24 12:25 ` Tvrtko Ursulin
@ 2024-04-17 8:22 ` Bernatowicz, Marcin
0 siblings, 0 replies; 11+ messages in thread
From: Bernatowicz, Marcin @ 2024-04-17 8:22 UTC (permalink / raw)
To: Tvrtko Ursulin, igt-dev; +Cc: kamil.konieczny, lukasz.laguna
On 1/24/2024 1:25 PM, Tvrtko Ursulin wrote:
>
> On 15/01/2024 15:44, Marcin Bernatowicz wrote:
>> Added command line option (-l) to list physical engines.
>
> What is the use case and could you paste the example output please (both
> drivers if possible)?
Not a must have patch, just lists physical engines.
Sample output with extra verbosity to see [class:instance:gt] tuple:
ATSM:~# lspci -ks 0000:4d:00.0 && ~/igt/benchmarks/gem_wsim -vvvl -D
"pci:slot=0000:4d:00.0"
4d:00.0 Display controller: Intel Corporation Device 56c0 (rev 08)
Subsystem: Intel Corporation Device 4905
Kernel driver in use: i915
Kernel modules: i915, xe
Using device /dev/dri/card0
RCS [0:0:65535]
BCS [1:0:65535]
VCS1 [2:0:65535]
VCS2 [2:1:65535]
VECS1 [3:0:65535]
VECS2 [3:1:65535]
CCS1 [4:0:65535]
CCS2 [4:1:65535]
CCS3 [4:2:65535]
CCS4 [4:3:65535]
ATSM:~# lspci -ks 0000:4d:00.0 && ~/igt/benchmarks/gem_wsim -vvvl -D
"pci:slot=0000:4d:00.0"
4d:00.0 Display controller: Intel Corporation Device 56c0 (rev 08)
Subsystem: Intel Corporation Device 4905
Kernel driver in use: xe
Kernel modules: i915, xe
Using device /dev/dri/card1
RCS [0:0:0]
BCS [1:0:0]
VCS1 [2:0:0]
VCS2 [2:1:0]
VECS1 [3:0:0]
VECS2 [3:1:0]
CCS [4:0:0] - when ccs_mode = 1
ex. for ccs_mode = 4:
CCS1 [4:0:0]
CCS2 [4:1:0]
CCS3 [4:2:0]
CCS4 [4:3:0]
ADLP:~# lspci -ks 0000:00:02.0 && ~/igt/benchmarks/gem_wsim -vvvl -D
"pci:slot=0000:00:02.0"
00:02.0 VGA compatible controller: Intel Corporation Alder Lake-P
Integrated Graphics Controller (rev 0c)
DeviceName: To Be Filled by O.E.M.
Subsystem: Intel Corporation Device 2212
Kernel driver in use: i915
Kernel modules: i915, xe
Using device /dev/dri/card0
RCS [0:0:65535]
BCS [1:0:65535]
VCS1 [2:0:65535]
VCS2 [2:1:65535]
VECS [3:0:65535]
ADLP:~# lspci -ks 0000:00:02.0 && ~/igt/benchmarks/gem_wsim -vvvl -D
"pci:slot=0000:00:02.0"
00:02.0 VGA compatible controller: Intel Corporation Alder Lake-P
Integrated Graphics Controller (rev 0c)
DeviceName: To Be Filled by O.E.M.
Subsystem: Intel Corporation Device 2212
Kernel driver in use: xe
Kernel modules: i915, xe
Using device /dev/dri/card0
RCS [0:0:0]
BCS [1:0:0]
VCS1 [2:0:0]
VCS2 [2:1:0]
VECS [3:0:0]
MTLH:~# lspci -ks 0000:00:02.0 && ~/igt/benchmarks/gem_wsim -vvvl -D
"pci:slot=0000:00:02.0"
00:02.0 VGA compatible controller: Intel Corporation Device 7d55 (rev 08)
DeviceName: To Be Filled by O.E.M.
Subsystem: Intel Corporation Device 2212
Kernel driver in use: i915
Kernel modules: i915, xe
Using device /dev/dri/card0
RCS [0:0:65535]
BCS [1:0:65535]
VCS1 [2:0:65535]
VCS2 [2:1:65535]
VECS [3:0:65535]
CCS [4:0:65535]
MTLH:~# lspci -ks 0000:00:02.0 && ~/igt/benchmarks/gem_wsim -vvvl -D
"pci:slot=0000:00:02.0"
00:02.0 VGA compatible controller: Intel Corporation Device 7d55 (rev 08)
DeviceName: To Be Filled by O.E.M.
Subsystem: Intel Corporation Device 2212
Kernel driver in use: xe
Kernel modules: i915, xe
Using device /dev/dri/card0
RCS [0:0:0]
BCS [1:0:0]
CCS [4:0:0]
VCS1-1 [2:0:1]
VCS2-1 [2:1:1]
VECS-1 [3:0:1]
We see *-1 as gt is != 0, but workload definitions with VCS, VCS1,
VCS1-1 are equivalent:
MTLH:~# ~/igt/benchmarks/gem_wsim -vvv -D "pci:slot=0000:00:02.0" -w
"1.VCS1.100000.0.1"
Using device /dev/dri/card0
Random seed is 1713261312.
1 client.
0 ctx[1] VCS [2:0:1]
0: 0 bytes in working sets.
0: 0 bytes active working set in 0 buffers. 8192 in batch buffers.
*0: 0.108s elapsed (1 cycles, 9.234 workloads/s).
0.111s elapsed (9.043 workloads/s)
MTLH:~# ~/igt/benchmarks/gem_wsim -vvv -D "pci:slot=0000:00:02.0" -w
"1.VCS1-1.100000.0.1"
Using device /dev/dri/card0
Random seed is 1713261375.
1 client.
0 ctx[1] VCS [2:0:1]
0: 0 bytes in working sets.
0: 0 bytes active working set in 0 buffers. 8192 in batch buffers.
*0: 0.105s elapsed (1 cycles, 9.530 workloads/s).
0.107s elapsed (9.381 workloads/s)
MTLH:~# ~/igt/benchmarks/gem_wsim -vvv -D "pci:slot=0000:00:02.0" -w
"1.VCS.100000.0.1"
Using device /dev/dri/card0
Random seed is 1713262682.
1 client.
0 ctx[1] VCS [2:0:1]
0: 0 bytes in working sets.
0: 0 bytes active working set in 0 buffers. 8192 in batch buffers.
*0: 0.107s elapsed (1 cycles, 9.362 workloads/s).
0.108s elapsed (9.237 workloads/s)
>
> Regards,
>
> Tvrtko
>
>> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
>> ---
>> benchmarks/gem_wsim.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 42 insertions(+), 1 deletion(-)
>>
>> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
>> index e79d26513..aa70b1770 100644
>> --- a/benchmarks/gem_wsim.c
>> +++ b/benchmarks/gem_wsim.c
>> @@ -2924,6 +2924,7 @@ static void print_help(void)
>> " -f <scale> Scale factor for batch durations.\n"
>> " -F <scale> Scale factor for delays.\n"
>> " -L List GPUs.\n"
>> +" -l List physical engines.\n"
>> " -D <gpu> One of the GPUs from -L.\n"
>> );
>> }
>> @@ -2983,10 +2984,42 @@ add_workload_arg(struct w_arg *w_args,
>> unsigned int nr_args, char *w_arg,
>> return w_args;
>> }
>> +static void list_engines(void)
>> +{
>> + struct intel_engines *engines = query_engines();
>> + int engine_class_count[NUM_ENGINE_CLASSES] = {};
>> + unsigned int i;
>> +
>> + for (i = 0; i < engines->nr_engines; ++i) {
>> + igt_assert_lt(engines->engines[i].engine_class,
>> NUM_ENGINE_CLASSES);
>> + engine_class_count[engines->engines[i].engine_class]++;
>> + }
>> +
>> + for (i = 0; i < engines->nr_engines; ++i) {
>> + if (engine_class_count[engines->engines[i].engine_class] > 1)
>> + printf("%s%u",
>> +
>> intel_engine_class_string(engines->engines[i].engine_class),
>> + engines->engines[i].engine_instance + 1);
>> + else
>> + printf("%s",
>> +
>> intel_engine_class_string(engines->engines[i].engine_class));
>> +
>> + if (is_xe && engines->engines[i].gt_id)
>> + printf("-%u", engines->engines[i].gt_id);
>> +
>> + if (verbose > 3)
>> + printf(" [%d:%d:%d]", engines->engines[i].engine_class,
>> + engines->engines[i].engine_instance,
>> + engines->engines[i].gt_id);
>> + printf("\n");
>> + }
>> +}
>> +
>> int main(int argc, char **argv)
>> {
>> struct igt_device_card card = { };
>> bool list_devices_arg = false;
>> + bool list_engines_arg = false;
>> unsigned int repeat = 1;
>> unsigned int clients = 1;
>> unsigned int flags = 0;
>> @@ -3009,11 +3042,14 @@ int main(int argc, char **argv)
>> master_prng = time(NULL);
>> while ((c = getopt(argc, argv,
>> - "LhqvsSdc:r:w:W:a:p:I:f:F:D:")) != -1) {
>> + "LlhqvsSdc:r:w:W:a:p:I:f:F:D:")) != -1) {
>> switch (c) {
>> case 'L':
>> list_devices_arg = true;
>> break;
>> + case 'l':
>> + list_engines_arg = true;
>> + break;
>> case 'D':
>> device_arg = strdup(optarg);
>> break;
>> @@ -3134,6 +3170,11 @@ int main(int argc, char **argv)
>> if (is_xe)
>> xe_device_get(fd);
>> + if (list_engines_arg) {
>> + list_engines();
>> + goto out;
>> + }
>> +
>> if (!nr_w_args) {
>> wsim_err("No workload descriptor(s)!\n");
>> goto err;
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2024-04-17 8:23 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-01-15 15:44 [PATCH i-g-t 0/2] benchmarks/gem_wsim: Extend engine selection syntax Marcin Bernatowicz
2024-01-15 15:44 ` [PATCH i-g-t 1/2] " Marcin Bernatowicz
2024-01-24 11:41 ` Laguna, Lukasz
2024-01-24 12:24 ` Tvrtko Ursulin
2024-01-15 15:44 ` [PATCH i-g-t 2/2] benchmarks/gem_wsim: Option to list physical engines Marcin Bernatowicz
2024-01-24 11:41 ` Laguna, Lukasz
2024-01-24 12:25 ` Tvrtko Ursulin
2024-04-17 8:22 ` Bernatowicz, Marcin
2024-01-15 16:54 ` ✓ Fi.CI.BAT: success for benchmarks/gem_wsim: Extend engine selection syntax Patchwork
2024-01-15 17:06 ` ✓ CI.xeBAT: " Patchwork
2024-01-15 19:10 ` ✗ Fi.CI.IGT: failure " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox