* [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr
@ 2020-10-09 16:22 Chris Wilson
2020-10-09 16:22 ` [igt-dev] [PATCH i-g-t 2/3] i915/gem_exec_schedule: Include userptr scheduling tests Chris Wilson
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Chris Wilson @ 2020-10-09 16:22 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/igt_dummyload.c | 87 ++++++++++++++++++++++++-------------
lib/igt_dummyload.h | 13 ++++--
tests/i915/gem_spin_batch.c | 23 ++++++----
3 files changed, 80 insertions(+), 43 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 26ea154ac..d58f73108 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -68,6 +68,24 @@ static const int LOOP_START_OFFSET = 64;
static IGT_LIST_HEAD(spin_list);
static pthread_mutex_t list_lock = PTHREAD_MUTEX_INITIALIZER;
+static uint32_t
+handle_create(int fd, size_t sz, unsigned long flags, uint32_t **mem)
+{
+ *mem = NULL;
+
+ if (flags & IGT_SPIN_USERPTR) {
+ uint32_t handle;
+
+ *mem = mmap(NULL, sz, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+ igt_assert(*mem != (uint32_t *)-1);
+ gem_userptr(fd, *mem, sz, 0, 0, &handle);
+
+ return handle;
+ }
+
+ return gem_create(fd, sz);
+}
+
static int
emit_recursive_batch(igt_spin_t *spin,
int fd, const struct igt_spin_factory *opts)
@@ -81,8 +99,8 @@ emit_recursive_batch(igt_spin_t *spin,
unsigned int flags[GEM_MAX_ENGINES];
unsigned int nengine;
int fence_fd = -1;
- uint32_t *cs, *batch;
uint64_t addr;
+ uint32_t *cs;
int i;
/*
@@ -126,13 +144,16 @@ emit_recursive_batch(igt_spin_t *spin,
execbuf->flags = I915_EXEC_NO_RELOC;
obj = memset(spin->obj, 0, sizeof(spin->obj));
- obj[BATCH].handle = gem_create(fd, BATCH_SIZE);
- batch = gem_mmap__device_coherent(fd, obj[BATCH].handle,
- 0, BATCH_SIZE, PROT_WRITE);
- gem_set_domain(fd, obj[BATCH].handle,
- I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+ obj[BATCH].handle =
+ handle_create(fd, BATCH_SIZE, opts->flags, &spin->batch);
+ if (!spin->batch) {
+ spin->batch = gem_mmap__device_coherent(fd, obj[BATCH].handle,
+ 0, BATCH_SIZE, PROT_WRITE);
+ gem_set_domain(fd, obj[BATCH].handle,
+ I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+ }
execbuf->buffer_count++;
- cs = batch;
+ cs = spin->batch;
obj[BATCH].offset = addr;
addr += BATCH_SIZE;
@@ -165,19 +186,22 @@ emit_recursive_batch(igt_spin_t *spin,
igt_require(__igt_device_set_master(fd) == 0);
}
- spin->poll_handle = gem_create(fd, 4096);
+ spin->poll_handle =
+ handle_create(fd, 4096, opts->flags, &spin->poll);
obj[SCRATCH].handle = spin->poll_handle;
- if (__gem_set_caching(fd, spin->poll_handle,
- I915_CACHING_CACHED) == 0)
- spin->poll = gem_mmap__cpu(fd, spin->poll_handle,
- 0, 4096,
- PROT_READ | PROT_WRITE);
- else
- spin->poll = gem_mmap__device_coherent(fd,
- spin->poll_handle,
- 0, 4096,
- PROT_READ | PROT_WRITE);
+ if (!spin->poll) {
+ if (__gem_set_caching(fd, spin->poll_handle,
+ I915_CACHING_CACHED) == 0)
+ spin->poll = gem_mmap__cpu(fd, spin->poll_handle,
+ 0, 4096,
+ PROT_READ | PROT_WRITE);
+ else
+ spin->poll = gem_mmap__device_coherent(fd,
+ spin->poll_handle,
+ 0, 4096,
+ PROT_READ | PROT_WRITE);
+ }
addr += 4096; /* guard page */
obj[SCRATCH].offset = addr;
addr += 4096;
@@ -210,8 +234,8 @@ emit_recursive_batch(igt_spin_t *spin,
spin->handle = obj[BATCH].handle;
- igt_assert_lt(cs - batch, LOOP_START_OFFSET / sizeof(*cs));
- spin->condition = batch + LOOP_START_OFFSET / sizeof(*cs);
+ igt_assert_lt(cs - spin->batch, LOOP_START_OFFSET / sizeof(*cs));
+ spin->condition = spin->batch + LOOP_START_OFFSET / sizeof(*cs);
cs = spin->condition;
/* Allow ourselves to be preempted */
@@ -255,15 +279,15 @@ emit_recursive_batch(igt_spin_t *spin,
* (using 5 << 12).
* For simplicity, we try to stick to a one-size fits all.
*/
- spin->condition = batch + BATCH_SIZE / sizeof(*batch) - 2;
+ spin->condition = spin->batch + BATCH_SIZE / sizeof(*spin->batch) - 2;
spin->condition[0] = 0xffffffff;
spin->condition[1] = 0xffffffff;
r->presumed_offset = obj[BATCH].offset;
r->target_handle = obj[BATCH].handle;
- r->offset = (cs + 2 - batch) * sizeof(*cs);
+ r->offset = (cs + 2 - spin->batch) * sizeof(*cs);
r->read_domains = I915_GEM_DOMAIN_COMMAND;
- r->delta = (spin->condition - batch) * sizeof(*cs);
+ r->delta = (spin->condition - spin->batch) * sizeof(*cs);
*cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2;
*cs++ = MI_BATCH_BUFFER_END;
@@ -275,7 +299,7 @@ emit_recursive_batch(igt_spin_t *spin,
r = &relocs[obj[BATCH].relocation_count++];
r->target_handle = obj[BATCH].handle;
r->presumed_offset = obj[BATCH].offset;
- r->offset = (cs + 1 - batch) * sizeof(*cs);
+ r->offset = (cs + 1 - spin->batch) * sizeof(*cs);
r->read_domains = I915_GEM_DOMAIN_COMMAND;
r->delta = LOOP_START_OFFSET;
if (gen >= 8) {
@@ -294,8 +318,8 @@ emit_recursive_batch(igt_spin_t *spin,
}
obj[BATCH].relocs_ptr = to_user_pointer(relocs);
- execbuf->buffers_ptr = to_user_pointer(obj +
- (2 - execbuf->buffer_count));
+ execbuf->buffers_ptr =
+ to_user_pointer(obj + (2 - execbuf->buffer_count));
execbuf->rsvd1 = opts->ctx;
if (opts->flags & IGT_SPIN_FENCE_OUT)
@@ -329,7 +353,7 @@ emit_recursive_batch(igt_spin_t *spin,
}
}
- igt_assert_lt(cs - batch, BATCH_SIZE / sizeof(*cs));
+ igt_assert_lt(cs - spin->batch, BATCH_SIZE / sizeof(*cs));
/* Make it easier for callers to resubmit. */
for (i = 0; i < ARRAY_SIZE(spin->obj); i++) {
@@ -532,13 +556,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
}
igt_spin_end(spin);
- gem_munmap((void *)((unsigned long)spin->condition & (~4095UL)),
- BATCH_SIZE);
- if (spin->poll) {
+ if (spin->poll)
gem_munmap(spin->poll, 4096);
+ if (spin->batch)
+ gem_munmap(spin->batch, BATCH_SIZE);
+
+ if (spin->poll_handle)
gem_close(fd, spin->poll_handle);
- }
if (spin->handle)
gem_close(fd, spin->handle);
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index aac0c83a9..6d3e65ce2 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -33,12 +33,19 @@
#include "i915_drm.h"
typedef struct igt_spin {
- unsigned int handle;
struct igt_list_head link;
+ uint32_t handle;
+ uint32_t poll_handle;
+
+ uint32_t *batch;
+
uint32_t *condition;
uint32_t cmd_precondition;
+ uint32_t *poll;
+#define SPIN_POLL_START_IDX 0
+
struct timespec last_signal;
pthread_t timer_thread;
int timerfd;
@@ -47,9 +54,6 @@ typedef struct igt_spin {
struct drm_i915_gem_exec_object2 obj[2];
#define IGT_SPIN_BATCH 1
struct drm_i915_gem_execbuffer2 execbuf;
- uint32_t poll_handle;
- uint32_t *poll;
-#define SPIN_POLL_START_IDX 0
} igt_spin_t;
struct igt_spin_factory {
@@ -66,6 +70,7 @@ struct igt_spin_factory {
#define IGT_SPIN_FAST (1 << 3)
#define IGT_SPIN_NO_PREEMPTION (1 << 4)
#define IGT_SPIN_INVALID_CS (1 << 5)
+#define IGT_SPIN_USERPTR (1 << 6)
igt_spin_t *
__igt_spin_factory(int fd, const struct igt_spin_factory *opts);
diff --git a/tests/i915/gem_spin_batch.c b/tests/i915/gem_spin_batch.c
index e7dd58ec2..19bc4638d 100644
--- a/tests/i915/gem_spin_batch.c
+++ b/tests/i915/gem_spin_batch.c
@@ -33,7 +33,9 @@
"'%s' != '%s' (%lld not within %d%% tolerance of %lld)\n",\
#x, #ref, (long long)x, tolerance, (long long)ref)
-static void spin(int fd, const struct intel_execution_engine2 *e2,
+static void spin(int fd,
+ const struct intel_execution_engine2 *e2,
+ unsigned int flags,
unsigned int timeout_sec)
{
const uint64_t timeout_100ms = 100000000LL;
@@ -43,9 +45,10 @@ static void spin(int fd, const struct intel_execution_engine2 *e2,
struct timespec itv = { };
uint64_t elapsed;
- spin = __igt_spin_new(fd, .engine = e2->flags);
+ spin = __igt_spin_new(fd, .engine = e2->flags, .flags = flags);
while ((elapsed = igt_nsec_elapsed(&tv)) >> 30 < timeout_sec) {
- igt_spin_t *next = __igt_spin_new(fd, .engine = e2->flags);
+ igt_spin_t *next =
+ __igt_spin_new(fd, .engine = e2->flags, .flags = flags);
igt_spin_set_timeout(spin,
timeout_100ms - igt_nsec_elapsed(&itv));
@@ -120,14 +123,15 @@ static void spin_exit_handler(int sig)
igt_terminate_spins();
}
-static void spin_on_all_engines(int fd, unsigned int timeout_sec)
+static void
+spin_on_all_engines(int fd, unsigned long flags, unsigned int timeout_sec)
{
const struct intel_execution_engine2 *e2;
__for_each_physical_engine(fd, e2) {
igt_fork(child, 1) {
igt_install_exit_handler(spin_exit_handler);
- spin(fd, e2, timeout_sec);
+ spin(fd, e2, flags, timeout_sec);
}
}
@@ -186,7 +190,7 @@ igt_main
e2 = &e2__;
igt_subtest_f("legacy-%s", e->name)
- spin(fd, e2, 3);
+ spin(fd, e2, 0, 3);
igt_subtest_f("legacy-resubmit-%s", e->name)
spin_resubmit(fd, e2, 0);
@@ -202,7 +206,7 @@ igt_main
__for_each_physical_engine(fd, e2) {
igt_subtest_f("%s", e2->name)
- spin(fd, e2, 3);
+ spin(fd, e2, 0, 3);
igt_subtest_f("resubmit-%s", e2->name)
spin_resubmit(fd, e2, 0);
@@ -220,7 +224,10 @@ igt_main
}
igt_subtest("spin-each")
- spin_on_all_engines(fd, 3);
+ spin_on_all_engines(fd, 0, 3);
+
+ igt_subtest("user-each")
+ spin_on_all_engines(fd, IGT_SPIN_USERPTR, 3);
igt_fixture {
igt_stop_hang_detector();
--
2.28.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH i-g-t 2/3] i915/gem_exec_schedule: Include userptr scheduling tests
2020-10-09 16:22 [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr Chris Wilson
@ 2020-10-09 16:22 ` Chris Wilson
2020-10-09 16:36 ` Mika Kuoppala
2020-10-09 16:22 ` [Intel-gfx] [PATCH i-g-t 3/3] i915/gem_exec_balancer: Check interactions between bonds and userptr Chris Wilson
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2020-10-09 16:22 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Chris Wilson
In practice, it turns out that compute likes to use userptr for
everything, and so in turn so must we.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/gem_exec_schedule.c | 41 +++++++++++++++++++++++-----------
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 488d93511..57c20560a 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -805,7 +805,7 @@ static uint32_t batch_create(int i915)
return __batch_create(i915, 0);
}
-static void semaphore_userlock(int i915)
+static void semaphore_userlock(int i915, unsigned long flags)
{
const struct intel_execution_engine2 *e;
struct drm_i915_gem_exec_object2 obj = {
@@ -828,7 +828,8 @@ static void semaphore_userlock(int i915)
if (!spin) {
spin = igt_spin_new(i915,
.dependency = scratch,
- .engine = e->flags);
+ .engine = e->flags,
+ .flags = flags);
} else {
uint64_t saved = spin->execbuf.flags;
@@ -869,7 +870,7 @@ static void semaphore_userlock(int i915)
igt_spin_free(i915, spin);
}
-static void semaphore_codependency(int i915)
+static void semaphore_codependency(int i915, unsigned long flags)
{
const struct intel_execution_engine2 *e;
struct {
@@ -903,7 +904,7 @@ static void semaphore_codependency(int i915)
__igt_spin_new(i915,
.ctx = ctx,
.engine = e->flags,
- .flags = IGT_SPIN_POLL_RUN);
+ .flags = IGT_SPIN_POLL_RUN | flags);
igt_spin_busywait_until_started(task[i].xcs);
/* Common rcs tasks will be queued in FIFO */
@@ -925,13 +926,18 @@ static void semaphore_codependency(int i915)
igt_spin_end(task[1].rcs);
gem_sync(i915, task[1].rcs->handle); /* to hang if task[0] hogs rcs */
+ for (i = 0; i < ARRAY_SIZE(task); i++) {
+ igt_spin_end(task[i].xcs);
+ igt_spin_end(task[i].rcs);
+ }
+
for (i = 0; i < ARRAY_SIZE(task); i++) {
igt_spin_free(i915, task[i].xcs);
igt_spin_free(i915, task[i].rcs);
}
}
-static void semaphore_resolve(int i915)
+static void semaphore_resolve(int i915, unsigned long flags)
{
const struct intel_execution_engine2 *e;
const uint32_t SEMAPHORE_ADDR = 64 << 10;
@@ -966,7 +972,7 @@ static void semaphore_resolve(int i915)
if (!gem_class_can_store_dword(i915, e->class))
continue;
- spin = __igt_spin_new(i915, .engine = e->flags);
+ spin = __igt_spin_new(i915, .engine = e->flags, .flags = flags);
igt_spin_end(spin); /* we just want its address for later */
gem_sync(i915, spin->handle);
igt_spin_reset(spin);
@@ -1060,7 +1066,7 @@ static void semaphore_resolve(int i915)
gem_context_destroy(i915, outer);
}
-static void semaphore_noskip(int i915)
+static void semaphore_noskip(int i915, unsigned long flags)
{
const int gen = intel_gen(intel_get_drm_devid(i915));
const struct intel_execution_engine2 *outer, *inner;
@@ -1081,9 +1087,9 @@ static void semaphore_noskip(int i915)
!gem_class_can_store_dword(i915, inner->class))
continue;
- chain = __igt_spin_new(i915, .engine = outer->flags);
+ chain = __igt_spin_new(i915, .engine = outer->flags, .flags = flags);
- spin = __igt_spin_new(i915, .engine = inner->flags);
+ spin = __igt_spin_new(i915, .engine = inner->flags, .flags = flags);
igt_spin_end(spin); /* we just want its address for later */
gem_sync(i915, spin->handle);
igt_spin_reset(spin);
@@ -2577,13 +2583,22 @@ igt_main
submit_slice(fd, e, LATE_SUBMIT);
igt_subtest("semaphore-user")
- semaphore_userlock(fd);
+ semaphore_userlock(fd, 0);
igt_subtest("semaphore-codependency")
- semaphore_codependency(fd);
+ semaphore_codependency(fd, 0);
igt_subtest("semaphore-resolve")
- semaphore_resolve(fd);
+ semaphore_resolve(fd, 0);
igt_subtest("semaphore-noskip")
- semaphore_noskip(fd);
+ semaphore_noskip(fd, 0);
+
+ igt_subtest("u-semaphore-user")
+ semaphore_userlock(fd, IGT_SPIN_USERPTR);
+ igt_subtest("u-semaphore-codependency")
+ semaphore_codependency(fd, IGT_SPIN_USERPTR);
+ igt_subtest("u-semaphore-resolve")
+ semaphore_resolve(fd, IGT_SPIN_USERPTR);
+ igt_subtest("u-semaphore-noskip")
+ semaphore_noskip(fd, IGT_SPIN_USERPTR);
igt_subtest("smoketest-all")
smoketest(fd, ALL_ENGINES, 30);
--
2.28.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH i-g-t 3/3] i915/gem_exec_balancer: Check interactions between bonds and userptr
2020-10-09 16:22 [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr Chris Wilson
2020-10-09 16:22 ` [igt-dev] [PATCH i-g-t 2/3] i915/gem_exec_schedule: Include userptr scheduling tests Chris Wilson
@ 2020-10-09 16:22 ` Chris Wilson
2020-10-09 16:39 ` [igt-dev] " Mika Kuoppala
2020-10-09 16:35 ` [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr Mika Kuoppala
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2020-10-09 16:22 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/gem_exec_balancer.c | 46 +++++++++++++++++++++++-----------
1 file changed, 31 insertions(+), 15 deletions(-)
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index 35a032ccb..0ccb94ba1 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -34,6 +34,10 @@
IGT_TEST_DESCRIPTION("Exercise in-kernel load-balancing");
+#define CORK (1ul << 0)
+#define VIRTUAL_ENGINE (1ul << 1)
+#define USERPTR (1ul << 2)
+
#define MI_SEMAPHORE_WAIT (0x1c << 23)
#define MI_SEMAPHORE_POLL (1 << 15)
#define MI_SEMAPHORE_SAD_GT_SDD (0 << 12)
@@ -578,7 +582,6 @@ static void individual(int i915)
}
static void bonded(int i915, unsigned int flags)
-#define CORK 0x1
{
I915_DEFINE_CONTEXT_ENGINES_BOND(bonds[16], 1);
struct i915_engine_class_instance *master_engines;
@@ -660,13 +663,15 @@ static void bonded(int i915, unsigned int flags)
plug = __igt_spin_new(i915,
.ctx = master,
.engine = bond,
- .dependency = igt_cork_plug(&cork, i915));
+ .dependency = igt_cork_plug(&cork, i915),
+ .flags = (flags & USERPTR ? IGT_SPIN_USERPTR : 0));
}
spin = __igt_spin_new(i915,
.ctx = master,
.engine = bond,
- .flags = IGT_SPIN_FENCE_OUT);
+ .flags = IGT_SPIN_FENCE_OUT |
+ (flags & USERPTR ? IGT_SPIN_USERPTR : 0));
eb = spin->execbuf;
eb.rsvd1 = ctx;
@@ -717,8 +722,6 @@ static void bonded(int i915, unsigned int flags)
gem_context_destroy(i915, master);
}
-#define VIRTUAL_ENGINE (1u << 0)
-
static unsigned int offset_in_page(void *addr)
{
return (uintptr_t)addr & 4095;
@@ -1057,7 +1060,8 @@ static void bonded_chain(int i915)
static void __bonded_sema(int i915, uint32_t ctx,
const struct i915_engine_class_instance *siblings,
- unsigned int count)
+ unsigned int count,
+ unsigned long flags)
{
const int priorities[] = { -1023, 0, 1023 };
struct drm_i915_gem_exec_object2 batch = {
@@ -1074,7 +1078,8 @@ static void __bonded_sema(int i915, uint32_t ctx,
/* A: spin forever on seperate render engine */
spin = igt_spin_new(i915,
.flags = (IGT_SPIN_POLL_RUN |
- IGT_SPIN_FENCE_OUT));
+ IGT_SPIN_FENCE_OUT |
+ (flags & USERPTR ? IGT_SPIN_USERPTR : 0)));
igt_spin_busywait_until_started(spin);
/*
@@ -1128,7 +1133,7 @@ static void __bonded_sema(int i915, uint32_t ctx,
gem_close(i915, batch.handle);
}
-static void bonded_semaphore(int i915)
+static void bonded_semaphore(int i915, unsigned long flags)
{
uint32_t ctx;
@@ -1149,7 +1154,7 @@ static void bonded_semaphore(int i915)
siblings = list_engines(i915, 1u << class, &count);
if (count > 1)
- __bonded_sema(i915, ctx, siblings, count);
+ __bonded_sema(i915, ctx, siblings, count, flags);
free(siblings);
}
@@ -1839,7 +1844,7 @@ static void __bonded_early(int i915, uint32_t ctx,
spin = igt_spin_new(i915,
.ctx = ctx,
.engine = (flags & VIRTUAL_ENGINE) ? 0 : 1,
- .flags = IGT_SPIN_NO_PREEMPTION);
+ .flags = IGT_SPIN_NO_PREEMPTION | (flags & USERPTR ? IGT_SPIN_USERPTR : 0));
/* B: runs after A on engine 1 */
execbuf.flags = I915_EXEC_FENCE_OUT;
@@ -1882,7 +1887,7 @@ static void __bonded_early(int i915, uint32_t ctx,
igt_spin_free(i915, spin);
}
-static void bonded_early(int i915)
+static void bonded_early(int i915, unsigned long flags)
{
uint32_t ctx;
@@ -1909,8 +1914,8 @@ static void bonded_early(int i915)
siblings = list_engines(i915, 1u << class, &count);
if (count > 1) {
- __bonded_early(i915, ctx, siblings, count, 0);
- __bonded_early(i915, ctx, siblings, count, VIRTUAL_ENGINE);
+ __bonded_early(i915, ctx, siblings, count, flags);
+ __bonded_early(i915, ctx, siblings, count, flags | VIRTUAL_ENGINE);
}
free(siblings);
}
@@ -2876,7 +2881,16 @@ igt_main
bonded(i915, CORK);
igt_subtest("bonded-early")
- bonded_early(i915);
+ bonded_early(i915, 0);
+
+ igt_subtest("u-bonded-imm")
+ bonded(i915, USERPTR);
+
+ igt_subtest("u-bonded-cork")
+ bonded(i915, CORK | USERPTR);
+
+ igt_subtest("u-bonded-early")
+ bonded_early(i915, USERPTR);
}
igt_subtest("bonded-slice")
@@ -2886,7 +2900,9 @@ igt_main
bonded_chain(i915);
igt_subtest("bonded-semaphore")
- bonded_semaphore(i915);
+ bonded_semaphore(i915, 0);
+ igt_subtest("u-bonded-semaphore")
+ bonded_semaphore(i915, USERPTR);
igt_subtest("bonded-pair")
bonded_runner(i915, __bonded_pair);
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr
2020-10-09 16:22 [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr Chris Wilson
2020-10-09 16:22 ` [igt-dev] [PATCH i-g-t 2/3] i915/gem_exec_schedule: Include userptr scheduling tests Chris Wilson
2020-10-09 16:22 ` [Intel-gfx] [PATCH i-g-t 3/3] i915/gem_exec_balancer: Check interactions between bonds and userptr Chris Wilson
@ 2020-10-09 16:35 ` Mika Kuoppala
2020-10-09 17:26 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] " Patchwork
2020-10-09 19:32 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Mika Kuoppala @ 2020-10-09 16:35 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
Needs a commit message like:
Add support for dummyload to be userptr.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> lib/igt_dummyload.c | 87 ++++++++++++++++++++++++-------------
> lib/igt_dummyload.h | 13 ++++--
> tests/i915/gem_spin_batch.c | 23 ++++++----
> 3 files changed, 80 insertions(+), 43 deletions(-)
>
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 26ea154ac..d58f73108 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -68,6 +68,24 @@ static const int LOOP_START_OFFSET = 64;
> static IGT_LIST_HEAD(spin_list);
> static pthread_mutex_t list_lock = PTHREAD_MUTEX_INITIALIZER;
>
> +static uint32_t
> +handle_create(int fd, size_t sz, unsigned long flags, uint32_t **mem)
> +{
> + *mem = NULL;
> +
> + if (flags & IGT_SPIN_USERPTR) {
> + uint32_t handle;
> +
> + *mem = mmap(NULL, sz, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
> + igt_assert(*mem != (uint32_t *)-1);
> + gem_userptr(fd, *mem, sz, 0, 0, &handle);
> +
> + return handle;
> + }
> +
> + return gem_create(fd, sz);
> +}
> +
> static int
> emit_recursive_batch(igt_spin_t *spin,
> int fd, const struct igt_spin_factory *opts)
> @@ -81,8 +99,8 @@ emit_recursive_batch(igt_spin_t *spin,
> unsigned int flags[GEM_MAX_ENGINES];
> unsigned int nengine;
> int fence_fd = -1;
> - uint32_t *cs, *batch;
> uint64_t addr;
> + uint32_t *cs;
> int i;
>
> /*
> @@ -126,13 +144,16 @@ emit_recursive_batch(igt_spin_t *spin,
> execbuf->flags = I915_EXEC_NO_RELOC;
> obj = memset(spin->obj, 0, sizeof(spin->obj));
>
> - obj[BATCH].handle = gem_create(fd, BATCH_SIZE);
> - batch = gem_mmap__device_coherent(fd, obj[BATCH].handle,
> - 0, BATCH_SIZE, PROT_WRITE);
> - gem_set_domain(fd, obj[BATCH].handle,
> - I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> + obj[BATCH].handle =
> + handle_create(fd, BATCH_SIZE, opts->flags, &spin->batch);
> + if (!spin->batch) {
> + spin->batch = gem_mmap__device_coherent(fd, obj[BATCH].handle,
> + 0, BATCH_SIZE, PROT_WRITE);
> + gem_set_domain(fd, obj[BATCH].handle,
> + I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> + }
> execbuf->buffer_count++;
> - cs = batch;
> + cs = spin->batch;
>
> obj[BATCH].offset = addr;
> addr += BATCH_SIZE;
> @@ -165,19 +186,22 @@ emit_recursive_batch(igt_spin_t *spin,
> igt_require(__igt_device_set_master(fd) == 0);
> }
>
> - spin->poll_handle = gem_create(fd, 4096);
> + spin->poll_handle =
> + handle_create(fd, 4096, opts->flags, &spin->poll);
> obj[SCRATCH].handle = spin->poll_handle;
>
> - if (__gem_set_caching(fd, spin->poll_handle,
> - I915_CACHING_CACHED) == 0)
> - spin->poll = gem_mmap__cpu(fd, spin->poll_handle,
> - 0, 4096,
> - PROT_READ | PROT_WRITE);
> - else
> - spin->poll = gem_mmap__device_coherent(fd,
> - spin->poll_handle,
> - 0, 4096,
> - PROT_READ | PROT_WRITE);
> + if (!spin->poll) {
> + if (__gem_set_caching(fd, spin->poll_handle,
> + I915_CACHING_CACHED) == 0)
> + spin->poll = gem_mmap__cpu(fd, spin->poll_handle,
> + 0, 4096,
> + PROT_READ | PROT_WRITE);
> + else
> + spin->poll = gem_mmap__device_coherent(fd,
> + spin->poll_handle,
> + 0, 4096,
> + PROT_READ | PROT_WRITE);
> + }
> addr += 4096; /* guard page */
> obj[SCRATCH].offset = addr;
> addr += 4096;
> @@ -210,8 +234,8 @@ emit_recursive_batch(igt_spin_t *spin,
>
> spin->handle = obj[BATCH].handle;
>
> - igt_assert_lt(cs - batch, LOOP_START_OFFSET / sizeof(*cs));
> - spin->condition = batch + LOOP_START_OFFSET / sizeof(*cs);
> + igt_assert_lt(cs - spin->batch, LOOP_START_OFFSET / sizeof(*cs));
> + spin->condition = spin->batch + LOOP_START_OFFSET / sizeof(*cs);
> cs = spin->condition;
>
> /* Allow ourselves to be preempted */
> @@ -255,15 +279,15 @@ emit_recursive_batch(igt_spin_t *spin,
> * (using 5 << 12).
> * For simplicity, we try to stick to a one-size fits all.
> */
> - spin->condition = batch + BATCH_SIZE / sizeof(*batch) - 2;
> + spin->condition = spin->batch + BATCH_SIZE / sizeof(*spin->batch) - 2;
> spin->condition[0] = 0xffffffff;
> spin->condition[1] = 0xffffffff;
>
> r->presumed_offset = obj[BATCH].offset;
> r->target_handle = obj[BATCH].handle;
> - r->offset = (cs + 2 - batch) * sizeof(*cs);
> + r->offset = (cs + 2 - spin->batch) * sizeof(*cs);
> r->read_domains = I915_GEM_DOMAIN_COMMAND;
> - r->delta = (spin->condition - batch) * sizeof(*cs);
> + r->delta = (spin->condition - spin->batch) * sizeof(*cs);
>
> *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2;
> *cs++ = MI_BATCH_BUFFER_END;
> @@ -275,7 +299,7 @@ emit_recursive_batch(igt_spin_t *spin,
> r = &relocs[obj[BATCH].relocation_count++];
> r->target_handle = obj[BATCH].handle;
> r->presumed_offset = obj[BATCH].offset;
> - r->offset = (cs + 1 - batch) * sizeof(*cs);
> + r->offset = (cs + 1 - spin->batch) * sizeof(*cs);
> r->read_domains = I915_GEM_DOMAIN_COMMAND;
> r->delta = LOOP_START_OFFSET;
> if (gen >= 8) {
> @@ -294,8 +318,8 @@ emit_recursive_batch(igt_spin_t *spin,
> }
> obj[BATCH].relocs_ptr = to_user_pointer(relocs);
>
> - execbuf->buffers_ptr = to_user_pointer(obj +
> - (2 - execbuf->buffer_count));
> + execbuf->buffers_ptr =
> + to_user_pointer(obj + (2 - execbuf->buffer_count));
> execbuf->rsvd1 = opts->ctx;
>
> if (opts->flags & IGT_SPIN_FENCE_OUT)
> @@ -329,7 +353,7 @@ emit_recursive_batch(igt_spin_t *spin,
> }
> }
>
> - igt_assert_lt(cs - batch, BATCH_SIZE / sizeof(*cs));
> + igt_assert_lt(cs - spin->batch, BATCH_SIZE / sizeof(*cs));
>
> /* Make it easier for callers to resubmit. */
> for (i = 0; i < ARRAY_SIZE(spin->obj); i++) {
> @@ -532,13 +556,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
> }
>
> igt_spin_end(spin);
> - gem_munmap((void *)((unsigned long)spin->condition & (~4095UL)),
> - BATCH_SIZE);
>
> - if (spin->poll) {
> + if (spin->poll)
> gem_munmap(spin->poll, 4096);
> + if (spin->batch)
> + gem_munmap(spin->batch, BATCH_SIZE);
> +
> + if (spin->poll_handle)
> gem_close(fd, spin->poll_handle);
> - }
>
> if (spin->handle)
> gem_close(fd, spin->handle);
> diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
> index aac0c83a9..6d3e65ce2 100644
> --- a/lib/igt_dummyload.h
> +++ b/lib/igt_dummyload.h
> @@ -33,12 +33,19 @@
> #include "i915_drm.h"
>
> typedef struct igt_spin {
> - unsigned int handle;
> struct igt_list_head link;
>
> + uint32_t handle;
> + uint32_t poll_handle;
> +
> + uint32_t *batch;
> +
> uint32_t *condition;
> uint32_t cmd_precondition;
>
> + uint32_t *poll;
> +#define SPIN_POLL_START_IDX 0
> +
> struct timespec last_signal;
> pthread_t timer_thread;
> int timerfd;
> @@ -47,9 +54,6 @@ typedef struct igt_spin {
> struct drm_i915_gem_exec_object2 obj[2];
> #define IGT_SPIN_BATCH 1
> struct drm_i915_gem_execbuffer2 execbuf;
> - uint32_t poll_handle;
> - uint32_t *poll;
> -#define SPIN_POLL_START_IDX 0
> } igt_spin_t;
>
> struct igt_spin_factory {
> @@ -66,6 +70,7 @@ struct igt_spin_factory {
> #define IGT_SPIN_FAST (1 << 3)
> #define IGT_SPIN_NO_PREEMPTION (1 << 4)
> #define IGT_SPIN_INVALID_CS (1 << 5)
> +#define IGT_SPIN_USERPTR (1 << 6)
>
> igt_spin_t *
> __igt_spin_factory(int fd, const struct igt_spin_factory *opts);
> diff --git a/tests/i915/gem_spin_batch.c b/tests/i915/gem_spin_batch.c
> index e7dd58ec2..19bc4638d 100644
> --- a/tests/i915/gem_spin_batch.c
> +++ b/tests/i915/gem_spin_batch.c
> @@ -33,7 +33,9 @@
> "'%s' != '%s' (%lld not within %d%% tolerance of %lld)\n",\
> #x, #ref, (long long)x, tolerance, (long long)ref)
>
> -static void spin(int fd, const struct intel_execution_engine2 *e2,
> +static void spin(int fd,
> + const struct intel_execution_engine2 *e2,
> + unsigned int flags,
> unsigned int timeout_sec)
> {
> const uint64_t timeout_100ms = 100000000LL;
> @@ -43,9 +45,10 @@ static void spin(int fd, const struct intel_execution_engine2 *e2,
> struct timespec itv = { };
> uint64_t elapsed;
>
> - spin = __igt_spin_new(fd, .engine = e2->flags);
> + spin = __igt_spin_new(fd, .engine = e2->flags, .flags = flags);
> while ((elapsed = igt_nsec_elapsed(&tv)) >> 30 < timeout_sec) {
> - igt_spin_t *next = __igt_spin_new(fd, .engine = e2->flags);
> + igt_spin_t *next =
> + __igt_spin_new(fd, .engine = e2->flags, .flags = flags);
>
> igt_spin_set_timeout(spin,
> timeout_100ms - igt_nsec_elapsed(&itv));
> @@ -120,14 +123,15 @@ static void spin_exit_handler(int sig)
> igt_terminate_spins();
> }
>
> -static void spin_on_all_engines(int fd, unsigned int timeout_sec)
> +static void
> +spin_on_all_engines(int fd, unsigned long flags, unsigned int timeout_sec)
> {
> const struct intel_execution_engine2 *e2;
>
> __for_each_physical_engine(fd, e2) {
> igt_fork(child, 1) {
> igt_install_exit_handler(spin_exit_handler);
> - spin(fd, e2, timeout_sec);
> + spin(fd, e2, flags, timeout_sec);
> }
> }
>
> @@ -186,7 +190,7 @@ igt_main
> e2 = &e2__;
>
> igt_subtest_f("legacy-%s", e->name)
> - spin(fd, e2, 3);
> + spin(fd, e2, 0, 3);
>
> igt_subtest_f("legacy-resubmit-%s", e->name)
> spin_resubmit(fd, e2, 0);
> @@ -202,7 +206,7 @@ igt_main
>
> __for_each_physical_engine(fd, e2) {
> igt_subtest_f("%s", e2->name)
> - spin(fd, e2, 3);
> + spin(fd, e2, 0, 3);
>
> igt_subtest_f("resubmit-%s", e2->name)
> spin_resubmit(fd, e2, 0);
> @@ -220,7 +224,10 @@ igt_main
> }
>
> igt_subtest("spin-each")
> - spin_on_all_engines(fd, 3);
> + spin_on_all_engines(fd, 0, 3);
> +
> + igt_subtest("user-each")
> + spin_on_all_engines(fd, IGT_SPIN_USERPTR, 3);
>
> igt_fixture {
> igt_stop_hang_detector();
> --
> 2.28.0
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/3] i915/gem_exec_schedule: Include userptr scheduling tests
2020-10-09 16:22 ` [igt-dev] [PATCH i-g-t 2/3] i915/gem_exec_schedule: Include userptr scheduling tests Chris Wilson
@ 2020-10-09 16:36 ` Mika Kuoppala
0 siblings, 0 replies; 8+ messages in thread
From: Mika Kuoppala @ 2020-10-09 16:36 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> In practice, it turns out that compute likes to use userptr for
> everything, and so in turn so must we.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> tests/i915/gem_exec_schedule.c | 41 +++++++++++++++++++++++-----------
> 1 file changed, 28 insertions(+), 13 deletions(-)
>
> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> index 488d93511..57c20560a 100644
> --- a/tests/i915/gem_exec_schedule.c
> +++ b/tests/i915/gem_exec_schedule.c
> @@ -805,7 +805,7 @@ static uint32_t batch_create(int i915)
> return __batch_create(i915, 0);
> }
>
> -static void semaphore_userlock(int i915)
> +static void semaphore_userlock(int i915, unsigned long flags)
> {
> const struct intel_execution_engine2 *e;
> struct drm_i915_gem_exec_object2 obj = {
> @@ -828,7 +828,8 @@ static void semaphore_userlock(int i915)
> if (!spin) {
> spin = igt_spin_new(i915,
> .dependency = scratch,
> - .engine = e->flags);
> + .engine = e->flags,
> + .flags = flags);
> } else {
> uint64_t saved = spin->execbuf.flags;
>
> @@ -869,7 +870,7 @@ static void semaphore_userlock(int i915)
> igt_spin_free(i915, spin);
> }
>
> -static void semaphore_codependency(int i915)
> +static void semaphore_codependency(int i915, unsigned long flags)
> {
> const struct intel_execution_engine2 *e;
> struct {
> @@ -903,7 +904,7 @@ static void semaphore_codependency(int i915)
> __igt_spin_new(i915,
> .ctx = ctx,
> .engine = e->flags,
> - .flags = IGT_SPIN_POLL_RUN);
> + .flags = IGT_SPIN_POLL_RUN | flags);
> igt_spin_busywait_until_started(task[i].xcs);
>
> /* Common rcs tasks will be queued in FIFO */
> @@ -925,13 +926,18 @@ static void semaphore_codependency(int i915)
> igt_spin_end(task[1].rcs);
> gem_sync(i915, task[1].rcs->handle); /* to hang if task[0] hogs rcs */
>
> + for (i = 0; i < ARRAY_SIZE(task); i++) {
> + igt_spin_end(task[i].xcs);
> + igt_spin_end(task[i].rcs);
> + }
> +
> for (i = 0; i < ARRAY_SIZE(task); i++) {
> igt_spin_free(i915, task[i].xcs);
> igt_spin_free(i915, task[i].rcs);
> }
> }
>
> -static void semaphore_resolve(int i915)
> +static void semaphore_resolve(int i915, unsigned long flags)
> {
> const struct intel_execution_engine2 *e;
> const uint32_t SEMAPHORE_ADDR = 64 << 10;
> @@ -966,7 +972,7 @@ static void semaphore_resolve(int i915)
> if (!gem_class_can_store_dword(i915, e->class))
> continue;
>
> - spin = __igt_spin_new(i915, .engine = e->flags);
> + spin = __igt_spin_new(i915, .engine = e->flags, .flags = flags);
> igt_spin_end(spin); /* we just want its address for later */
> gem_sync(i915, spin->handle);
> igt_spin_reset(spin);
> @@ -1060,7 +1066,7 @@ static void semaphore_resolve(int i915)
> gem_context_destroy(i915, outer);
> }
>
> -static void semaphore_noskip(int i915)
> +static void semaphore_noskip(int i915, unsigned long flags)
> {
> const int gen = intel_gen(intel_get_drm_devid(i915));
> const struct intel_execution_engine2 *outer, *inner;
> @@ -1081,9 +1087,9 @@ static void semaphore_noskip(int i915)
> !gem_class_can_store_dword(i915, inner->class))
> continue;
>
> - chain = __igt_spin_new(i915, .engine = outer->flags);
> + chain = __igt_spin_new(i915, .engine = outer->flags, .flags = flags);
>
> - spin = __igt_spin_new(i915, .engine = inner->flags);
> + spin = __igt_spin_new(i915, .engine = inner->flags, .flags = flags);
> igt_spin_end(spin); /* we just want its address for later */
> gem_sync(i915, spin->handle);
> igt_spin_reset(spin);
> @@ -2577,13 +2583,22 @@ igt_main
> submit_slice(fd, e, LATE_SUBMIT);
>
> igt_subtest("semaphore-user")
> - semaphore_userlock(fd);
> + semaphore_userlock(fd, 0);
> igt_subtest("semaphore-codependency")
> - semaphore_codependency(fd);
> + semaphore_codependency(fd, 0);
> igt_subtest("semaphore-resolve")
> - semaphore_resolve(fd);
> + semaphore_resolve(fd, 0);
> igt_subtest("semaphore-noskip")
> - semaphore_noskip(fd);
> + semaphore_noskip(fd, 0);
> +
> + igt_subtest("u-semaphore-user")
> + semaphore_userlock(fd, IGT_SPIN_USERPTR);
> + igt_subtest("u-semaphore-codependency")
> + semaphore_codependency(fd, IGT_SPIN_USERPTR);
> + igt_subtest("u-semaphore-resolve")
> + semaphore_resolve(fd, IGT_SPIN_USERPTR);
> + igt_subtest("u-semaphore-noskip")
> + semaphore_noskip(fd, IGT_SPIN_USERPTR);
>
> igt_subtest("smoketest-all")
> smoketest(fd, ALL_ENGINES, 30);
> --
> 2.28.0
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/3] i915/gem_exec_balancer: Check interactions between bonds and userptr
2020-10-09 16:22 ` [Intel-gfx] [PATCH i-g-t 3/3] i915/gem_exec_balancer: Check interactions between bonds and userptr Chris Wilson
@ 2020-10-09 16:39 ` Mika Kuoppala
0 siblings, 0 replies; 8+ messages in thread
From: Mika Kuoppala @ 2020-10-09 16:39 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> tests/i915/gem_exec_balancer.c | 46 +++++++++++++++++++++++-----------
> 1 file changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
> index 35a032ccb..0ccb94ba1 100644
> --- a/tests/i915/gem_exec_balancer.c
> +++ b/tests/i915/gem_exec_balancer.c
> @@ -34,6 +34,10 @@
>
> IGT_TEST_DESCRIPTION("Exercise in-kernel load-balancing");
>
> +#define CORK (1ul << 0)
> +#define VIRTUAL_ENGINE (1ul << 1)
> +#define USERPTR (1ul << 2)
> +
> #define MI_SEMAPHORE_WAIT (0x1c << 23)
> #define MI_SEMAPHORE_POLL (1 << 15)
> #define MI_SEMAPHORE_SAD_GT_SDD (0 << 12)
> @@ -578,7 +582,6 @@ static void individual(int i915)
> }
>
> static void bonded(int i915, unsigned int flags)
> -#define CORK 0x1
> {
> I915_DEFINE_CONTEXT_ENGINES_BOND(bonds[16], 1);
> struct i915_engine_class_instance *master_engines;
> @@ -660,13 +663,15 @@ static void bonded(int i915, unsigned int flags)
> plug = __igt_spin_new(i915,
> .ctx = master,
> .engine = bond,
> - .dependency = igt_cork_plug(&cork, i915));
> + .dependency = igt_cork_plug(&cork, i915),
> + .flags = (flags & USERPTR ? IGT_SPIN_USERPTR : 0));
> }
>
> spin = __igt_spin_new(i915,
> .ctx = master,
> .engine = bond,
> - .flags = IGT_SPIN_FENCE_OUT);
> + .flags = IGT_SPIN_FENCE_OUT |
> + (flags & USERPTR ? IGT_SPIN_USERPTR : 0));
>
> eb = spin->execbuf;
> eb.rsvd1 = ctx;
> @@ -717,8 +722,6 @@ static void bonded(int i915, unsigned int flags)
> gem_context_destroy(i915, master);
> }
>
> -#define VIRTUAL_ENGINE (1u << 0)
> -
> static unsigned int offset_in_page(void *addr)
> {
> return (uintptr_t)addr & 4095;
> @@ -1057,7 +1060,8 @@ static void bonded_chain(int i915)
>
> static void __bonded_sema(int i915, uint32_t ctx,
> const struct i915_engine_class_instance *siblings,
> - unsigned int count)
> + unsigned int count,
> + unsigned long flags)
> {
> const int priorities[] = { -1023, 0, 1023 };
> struct drm_i915_gem_exec_object2 batch = {
> @@ -1074,7 +1078,8 @@ static void __bonded_sema(int i915, uint32_t ctx,
> /* A: spin forever on seperate render engine */
> spin = igt_spin_new(i915,
> .flags = (IGT_SPIN_POLL_RUN |
> - IGT_SPIN_FENCE_OUT));
> + IGT_SPIN_FENCE_OUT |
> + (flags & USERPTR ? IGT_SPIN_USERPTR : 0)));
> igt_spin_busywait_until_started(spin);
>
> /*
> @@ -1128,7 +1133,7 @@ static void __bonded_sema(int i915, uint32_t ctx,
> gem_close(i915, batch.handle);
> }
>
> -static void bonded_semaphore(int i915)
> +static void bonded_semaphore(int i915, unsigned long flags)
> {
> uint32_t ctx;
>
> @@ -1149,7 +1154,7 @@ static void bonded_semaphore(int i915)
>
> siblings = list_engines(i915, 1u << class, &count);
> if (count > 1)
> - __bonded_sema(i915, ctx, siblings, count);
> + __bonded_sema(i915, ctx, siblings, count, flags);
> free(siblings);
> }
>
> @@ -1839,7 +1844,7 @@ static void __bonded_early(int i915, uint32_t ctx,
> spin = igt_spin_new(i915,
> .ctx = ctx,
> .engine = (flags & VIRTUAL_ENGINE) ? 0 : 1,
> - .flags = IGT_SPIN_NO_PREEMPTION);
> + .flags = IGT_SPIN_NO_PREEMPTION | (flags & USERPTR ? IGT_SPIN_USERPTR : 0));
>
> /* B: runs after A on engine 1 */
> execbuf.flags = I915_EXEC_FENCE_OUT;
> @@ -1882,7 +1887,7 @@ static void __bonded_early(int i915, uint32_t ctx,
> igt_spin_free(i915, spin);
> }
>
> -static void bonded_early(int i915)
> +static void bonded_early(int i915, unsigned long flags)
> {
> uint32_t ctx;
>
> @@ -1909,8 +1914,8 @@ static void bonded_early(int i915)
>
> siblings = list_engines(i915, 1u << class, &count);
> if (count > 1) {
> - __bonded_early(i915, ctx, siblings, count, 0);
> - __bonded_early(i915, ctx, siblings, count, VIRTUAL_ENGINE);
> + __bonded_early(i915, ctx, siblings, count, flags);
> + __bonded_early(i915, ctx, siblings, count, flags | VIRTUAL_ENGINE);
> }
> free(siblings);
> }
> @@ -2876,7 +2881,16 @@ igt_main
> bonded(i915, CORK);
>
> igt_subtest("bonded-early")
> - bonded_early(i915);
> + bonded_early(i915, 0);
> +
> + igt_subtest("u-bonded-imm")
> + bonded(i915, USERPTR);
> +
> + igt_subtest("u-bonded-cork")
> + bonded(i915, CORK | USERPTR);
> +
> + igt_subtest("u-bonded-early")
> + bonded_early(i915, USERPTR);
> }
>
> igt_subtest("bonded-slice")
> @@ -2886,7 +2900,9 @@ igt_main
> bonded_chain(i915);
>
> igt_subtest("bonded-semaphore")
> - bonded_semaphore(i915);
> + bonded_semaphore(i915, 0);
> + igt_subtest("u-bonded-semaphore")
> + bonded_semaphore(i915, USERPTR);
>
> igt_subtest("bonded-pair")
> bonded_runner(i915, __bonded_pair);
> --
> 2.28.0
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] lib: Launch spinners from inside userptr
2020-10-09 16:22 [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr Chris Wilson
` (2 preceding siblings ...)
2020-10-09 16:35 ` [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr Mika Kuoppala
@ 2020-10-09 17:26 ` Patchwork
2020-10-09 19:32 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-10-09 17:26 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 5986 bytes --]
== Series Details ==
Series: series starting with [i-g-t,1/3] lib: Launch spinners from inside userptr
URL : https://patchwork.freedesktop.org/series/82518/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9120 -> IGTPW_5049
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/index.html
Known issues
------------
Here are the changes found in IGTPW_5049 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_pm:
- {fi-kbl-7560u}: [DMESG-FAIL][7] ([i915#2524]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/fi-kbl-7560u/igt@i915_selftest@live@gt_pm.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/fi-kbl-7560u/igt@i915_selftest@live@gt_pm.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][11] ([i915#2203]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/fi-skl-guc/igt@vgem_basic@unload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/fi-skl-guc/igt@vgem_basic@unload.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [DMESG-FAIL][13] ([i915#62] / [i915#95]) -> [DMESG-FAIL][14] ([i915#62])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
* igt@vgem_basic@unload:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#95])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/fi-kbl-x1275/igt@vgem_basic@unload.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/fi-kbl-x1275/igt@vgem_basic@unload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2524]: https://gitlab.freedesktop.org/drm/intel/issues/2524
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (46 -> 39)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5806 -> IGTPW_5049
CI-20190529: 20190529
CI_DRM_9120: c68cc26e956a13687638a89bdec9e25cc6eb2411 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5049: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/index.html
IGT_5806: 6adb80cd84310b6d90a5259768d03ebb2c30fe50 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_exec_balancer@u-bonded-cork
+igt@gem_exec_balancer@u-bonded-early
+igt@gem_exec_balancer@u-bonded-imm
+igt@gem_exec_balancer@u-bonded-semaphore
+igt@gem_exec_schedule@u-semaphore-codependency
+igt@gem_exec_schedule@u-semaphore-noskip
+igt@gem_exec_schedule@u-semaphore-resolve
+igt@gem_exec_schedule@u-semaphore-user
+igt@gem_spin_batch@user-each
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/index.html
[-- Attachment #1.2: Type: text/html, Size: 7993 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/3] lib: Launch spinners from inside userptr
2020-10-09 16:22 [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr Chris Wilson
` (3 preceding siblings ...)
2020-10-09 17:26 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] " Patchwork
@ 2020-10-09 19:32 ` Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-10-09 19:32 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 18590 bytes --]
== Series Details ==
Series: series starting with [i-g-t,1/3] lib: Launch spinners from inside userptr
URL : https://patchwork.freedesktop.org/series/82518/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9120_full -> IGTPW_5049_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_5049_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_5049_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_5049_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_create@forked:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-glk7/igt@gem_exec_create@forked.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-glk7/igt@gem_exec_create@forked.html
New tests
---------
New tests have been introduced between CI_DRM_9120_full and IGTPW_5049_full:
### New IGT tests (8) ###
* igt@gem_exec_balancer@u-bonded-cork:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 4.05] s
* igt@gem_exec_balancer@u-bonded-early:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 4.02] s
* igt@gem_exec_balancer@u-bonded-imm:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 4.14] s
* igt@gem_exec_balancer@u-bonded-semaphore:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 4.38] s
* igt@gem_exec_schedule@u-semaphore-codependency:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.03] s
* igt@gem_exec_schedule@u-semaphore-noskip:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.31] s
* igt@gem_exec_schedule@u-semaphore-resolve:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.06] s
* igt@gem_exec_schedule@u-semaphore-user:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.02] s
Known issues
------------
Here are the changes found in IGTPW_5049_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#1635] / [i915#2389])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-apl2/igt@gem_exec_reloc@basic-many-active@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-apl6/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2389])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-glk2/igt@gem_exec_reloc@basic-many-active@vcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-glk6/igt@gem_exec_reloc@basic-many-active@vcs0.html
* igt@gem_userptr_blits@coherency-sync:
- shard-hsw: [PASS][7] -> [FAIL][8] ([i915#1888]) +4 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-hsw4/igt@gem_userptr_blits@coherency-sync.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-hsw2/igt@gem_userptr_blits@coherency-sync.html
- shard-snb: [PASS][9] -> [INCOMPLETE][10] ([i915#82])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-snb6/igt@gem_userptr_blits@coherency-sync.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-snb7/igt@gem_userptr_blits@coherency-sync.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-iclb1/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-iclb3/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][13] -> [FAIL][14] ([i915#96])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
- shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([i915#2055])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-hsw1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-hsw4/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109642] / [fdo#111068])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][25] -> [FAIL][26] ([i915#1635] / [i915#31])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-apl7/igt@kms_setmode@basic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-apl4/igt@kms_setmode@basic.html
* igt@prime_vgem@sync@vcs0:
- shard-tglb: [PASS][27] -> [INCOMPLETE][28] ([i915#409])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-tglb2/igt@prime_vgem@sync@vcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-tglb2/igt@prime_vgem@sync@vcs0.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][29] ([i915#658]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-iclb6/igt@feature_discovery@psr2.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-iclb2/igt@feature_discovery@psr2.html
* {igt@gem_exec_capture@pi@rcs0}:
- shard-glk: [INCOMPLETE][31] ([i915#2553]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-glk5/igt@gem_exec_capture@pi@rcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-glk1/igt@gem_exec_capture@pi@rcs0.html
* {igt@gem_exec_capture@pi@vcs0}:
- shard-iclb: [INCOMPLETE][33] -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-iclb7/igt@gem_exec_capture@pi@vcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-iclb4/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk: [DMESG-WARN][35] ([i915#118] / [i915#95]) -> [PASS][36] +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-glk9/igt@gem_exec_whisper@basic-queues-forked-all.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-glk5/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][37] ([i915#2190]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-tglb2/igt@gem_huc_copy@huc-copy.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-tglb: [FAIL][39] -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-tglb2/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-tglb2/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw: [WARN][41] ([i915#1519]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-hsw4/igt@i915_pm_rc6_residency@rc6-idle.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-hsw4/igt@i915_pm_rc6_residency@rc6-idle.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-kbl: [FAIL][43] ([i915#2521]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-kbl4/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-apl: [DMESG-WARN][45] ([i915#1635] / [i915#1982]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-apl2/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-apl2/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
- shard-kbl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-kbl4/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-kbl6/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][49] ([i915#96]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-snb: [FAIL][51] -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-snb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-snb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
- shard-tglb: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-tglb8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-tglb1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +6 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html
* igt@perf@polling:
- shard-glk: [SKIP][57] ([fdo#109271] / [i915#1354]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-glk4/igt@perf@polling.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-glk5/igt@perf@polling.html
- shard-tglb: [SKIP][59] ([i915#1354]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-tglb2/igt@perf@polling.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-tglb8/igt@perf@polling.html
- shard-apl: [SKIP][61] ([fdo#109271] / [i915#1354] / [i915#1635]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-apl3/igt@perf@polling.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-apl1/igt@perf@polling.html
- shard-kbl: [SKIP][63] ([fdo#109271] / [i915#1354]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-kbl7/igt@perf@polling.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-kbl2/igt@perf@polling.html
- shard-hsw: [SKIP][65] ([fdo#109271]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-hsw2/igt@perf@polling.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-hsw8/igt@perf@polling.html
- shard-iclb: [SKIP][67] ([i915#1354]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-iclb6/igt@perf@polling.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-iclb6/igt@perf@polling.html
#### Warnings ####
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-snb: [FAIL][69] -> [SKIP][70] ([fdo#109271])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-snb6/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-snb6/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
- shard-iclb: [FAIL][71] -> [SKIP][72] ([i915#768])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-iclb6/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-iclb2/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
- shard-kbl: [FAIL][73] -> [SKIP][74] ([fdo#109271])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-kbl7/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-kbl2/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
- shard-hsw: [FAIL][75] -> [SKIP][76] ([fdo#109271])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-hsw2/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-hsw8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
- shard-glk: [FAIL][77] -> [SKIP][78] ([fdo#109271])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-glk4/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-glk4/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
- shard-apl: [FAIL][79] ([i915#1635]) -> [SKIP][80] ([fdo#109271] / [i915#1635])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-apl3/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-apl3/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@kms_content_protection@lic:
- shard-apl: [TIMEOUT][81] ([i915#1319] / [i915#1635]) -> [FAIL][82] ([fdo#110321] / [i915#1635])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9120/shard-apl3/igt@kms_content_protection@lic.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/shard-apl3/igt@kms_content_protection@lic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354
[i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2553]: https://gitlab.freedesktop.org/drm/intel/issues/2553
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
Participating hosts (11 -> 8)
------------------------------
Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5806 -> IGTPW_5049
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_9120: c68cc26e956a13687638a89bdec9e25cc6eb2411 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5049: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/index.html
IGT_5806: 6adb80cd84310b6d90a5259768d03ebb2c30fe50 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5049/index.html
[-- Attachment #1.2: Type: text/html, Size: 22082 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-10-09 19:32 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-10-09 16:22 [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr Chris Wilson
2020-10-09 16:22 ` [igt-dev] [PATCH i-g-t 2/3] i915/gem_exec_schedule: Include userptr scheduling tests Chris Wilson
2020-10-09 16:36 ` Mika Kuoppala
2020-10-09 16:22 ` [Intel-gfx] [PATCH i-g-t 3/3] i915/gem_exec_balancer: Check interactions between bonds and userptr Chris Wilson
2020-10-09 16:39 ` [igt-dev] " Mika Kuoppala
2020-10-09 16:35 ` [igt-dev] [PATCH i-g-t 1/3] lib: Launch spinners from inside userptr Mika Kuoppala
2020-10-09 17:26 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] " Patchwork
2020-10-09 19:32 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox