[igt-dev] [PATCH i-g-t 0/2] Keep tests working without relocations

[igt-dev] [PATCH i-g-t 0/2] Keep tests working without relocations

[Andrzej Turko]

With relocations disabled for newer generations
the addresses of buffer objects in memory need
to be known in advance and, hence, assigned in
userspace.
If relocations are not supported, the tests now
use the intel allocator to find offsets and
update the contents of batches correspondingly.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Andrzej Turko (2):
  tests/gem_exec_store: Support gens without relocations
  tests/gem_softpin: Exercise eviction with softpinning

 tests/i915/gem_exec_store.c | 134 ++++++++++++++++++-----
 tests/i915/gem_softpin.c    | 212 +++++++++++++++++++++++++++++++++++-
 2 files changed, 317 insertions(+), 29 deletions(-)

-- 
2.25.1

[igt-dev] [PATCH i-g-t 1/2] tests/gem_exec_store: Support gens without relocations

[Andrzej Turko]

With relocations disabled on newer generations
tests must assign addresses to objects by
themselves instead of relying on the driver.

Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_exec_store.c | 134 ++++++++++++++++++++++++++++--------
 1 file changed, 106 insertions(+), 28 deletions(-)

diff --git a/tests/i915/gem_exec_store.c b/tests/i915/gem_exec_store.c
index 0798f61d7..cb99f9510 100644
--- a/tests/i915/gem_exec_store.c
+++ b/tests/i915/gem_exec_store.c
@@ -37,6 +37,9 @@
 
 #define ENGINE_MASK  (I915_EXEC_RING_MASK | I915_EXEC_BSD_MASK)
 
+/* Without alignment detection we assume the worst-case scenario. */
+#define ALIGNMENT (1 << 21)
+
 static void store_dword(int fd, const intel_ctx_t *ctx,
 			const struct intel_execution_engine2 *e)
 {
@@ -45,6 +48,7 @@ static void store_dword(int fd, const intel_ctx_t *ctx,
 	struct drm_i915_gem_relocation_entry reloc;
 	struct drm_i915_gem_execbuffer2 execbuf;
 	uint32_t batch[16];
+	uint64_t ahnd;
 	int i;
 
 	intel_detect_and_clear_missed_interrupts(fd);
@@ -56,43 +60,63 @@ static void store_dword(int fd, const intel_ctx_t *ctx,
 		execbuf.flags |= I915_EXEC_SECURE;
 	execbuf.rsvd1 = ctx->id;
 
+	ahnd = intel_allocator_open(fd, ctx->id, INTEL_ALLOCATOR_SIMPLE);
+
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = gem_create(fd, 4096);
+	obj[0].offset = intel_allocator_alloc(ahnd, obj[0].handle,
+					      4096, ALIGNMENT);
+	obj[0].offset = CANONICAL(obj[0].offset);
+	obj[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_WRITE;
 	obj[1].handle = gem_create(fd, 4096);
+	obj[1].offset = intel_allocator_alloc(ahnd, obj[1].handle,
+					      4096, ALIGNMENT);
+	obj[1].offset = CANONICAL(obj[1].offset);
+	obj[1].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
 
 	memset(&reloc, 0, sizeof(reloc));
 	reloc.target_handle = obj[0].handle;
-	reloc.presumed_offset = 0;
+	reloc.presumed_offset = obj[0].offset;
 	reloc.offset = sizeof(uint32_t);
 	reloc.delta = 0;
 	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
 	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-	obj[1].relocs_ptr = to_user_pointer(&reloc);
-	obj[1].relocation_count = 1;
+
+	if (gem_has_relocations(fd)) {
+		obj[1].relocs_ptr = to_user_pointer(&reloc);
+		obj[1].relocation_count = 1;
+	} else {
+		obj[0].flags |= EXEC_OBJECT_PINNED;
+		obj[1].flags |= EXEC_OBJECT_PINNED;
+		execbuf.flags |= I915_EXEC_NO_RELOC;
+	}
 
 	i = 0;
 	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
 	if (gen >= 8) {
-		batch[++i] = 0;
-		batch[++i] = 0;
+		batch[++i] = obj[0].offset;
+		batch[++i] = obj[0].offset >> 32;
 	} else if (gen >= 4) {
 		batch[++i] = 0;
-		batch[++i] = 0;
+		batch[++i] = obj[0].offset;
 		reloc.offset += sizeof(uint32_t);
 	} else {
 		batch[i]--;
-		batch[++i] = 0;
+		batch[++i] = obj[0].offset;
 	}
 	batch[++i] = 0xc0ffee;
 	batch[++i] = MI_BATCH_BUFFER_END;
 	gem_write(fd, obj[1].handle, 0, batch, sizeof(batch));
 	gem_execbuf(fd, &execbuf);
 	gem_close(fd, obj[1].handle);
+	intel_allocator_free(ahnd, obj[1].handle);
 
 	gem_read(fd, obj[0].handle, 0, batch, sizeof(batch));
 	gem_close(fd, obj[0].handle);
+	intel_allocator_free(ahnd, obj[0].handle);
 	igt_assert_eq(*batch, 0xc0ffee);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+	intel_allocator_close(ahnd);
 }
 
 #define PAGES 1
@@ -106,7 +130,9 @@ static void store_cachelines(int fd, const intel_ctx_t *ctx,
 	struct drm_i915_gem_execbuffer2 execbuf;
 #define NCACHELINES (4096/64)
 	uint32_t *batch;
+	uint64_t ahnd, dst_offset;
 	int i;
+	bool do_relocs = gem_has_relocations(fd);
 
 	reloc = calloc(NCACHELINES, sizeof(*reloc));
 	igt_assert(reloc);
@@ -119,12 +145,25 @@ static void store_cachelines(int fd, const intel_ctx_t *ctx,
 		execbuf.flags |= I915_EXEC_SECURE;
 	execbuf.rsvd1 = ctx->id;
 
+	ahnd = intel_allocator_open(fd, ctx->id, INTEL_ALLOCATOR_SIMPLE);
 	obj = calloc(execbuf.buffer_count, sizeof(*obj));
 	igt_assert(obj);
-	for (i = 0; i < execbuf.buffer_count; i++)
+	for (i = 0; i < execbuf.buffer_count; i++) {
 		obj[i].handle = gem_create(fd, 4096);
-	obj[i-1].relocs_ptr = to_user_pointer(reloc);
-	obj[i-1].relocation_count = NCACHELINES;
+		obj[i].offset = intel_allocator_alloc(ahnd, obj[i].handle,
+						      4096, ALIGNMENT);
+		obj[i].offset = CANONICAL(obj[i].offset);
+		obj[i].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
+			       (do_relocs ? 0 : EXEC_OBJECT_PINNED);
+		if (i + 1 < execbuf.buffer_count)
+			obj[i].flags |= EXEC_OBJECT_WRITE;
+	}
+	if (do_relocs) {
+		obj[i-1].relocs_ptr = to_user_pointer(reloc);
+		obj[i-1].relocation_count = NCACHELINES;
+	} else {
+		execbuf.flags |= I915_EXEC_NO_RELOC;
+	}
 	execbuf.buffers_ptr = to_user_pointer(obj);
 
 	batch = gem_mmap__cpu(fd, obj[i-1].handle, 0, 4096, PROT_WRITE);
@@ -132,23 +171,24 @@ static void store_cachelines(int fd, const intel_ctx_t *ctx,
 	i = 0;
 	for (unsigned n = 0; n < NCACHELINES; n++) {
 		reloc[n].target_handle = obj[n % (execbuf.buffer_count-1)].handle;
-		reloc[n].presumed_offset = -1;
+		reloc[n].presumed_offset = obj[n % (execbuf.buffer_count-1)].offset;
 		reloc[n].offset = (i + 1)*sizeof(uint32_t);
 		reloc[n].delta = 4 * (n * 16 + n % 16);
 		reloc[n].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
 		reloc[n].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+		dst_offset = CANONICAL(reloc[n].presumed_offset + reloc[n].delta);
 
 		batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
 		if (gen >= 8) {
-			batch[++i] = 0;
-			batch[++i] = 0;
+			batch[++i] = dst_offset;
+			batch[++i] = dst_offset >> 32;
 		} else if (gen >= 4) {
 			batch[++i] = 0;
-			batch[++i] = 0;
+			batch[++i] = dst_offset;
 			reloc[n].offset += sizeof(uint32_t);
 		} else {
 			batch[i]--;
-			batch[++i] = 0;
+			batch[++i] = dst_offset;
 		}
 		batch[++i] = n | ~n << 16;
 		i++;
@@ -168,11 +208,14 @@ static void store_cachelines(int fd, const intel_ctx_t *ctx,
 	}
 	free(reloc);
 
-	for (unsigned n = 0; n < execbuf.buffer_count; n++)
+	for (unsigned n = 0; n < execbuf.buffer_count; n++) {
 		gem_close(fd, obj[n].handle);
+		intel_allocator_free(ahnd, obj[n].handle);
+	}
 	free(obj);
 
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+	intel_allocator_close(ahnd);
 }
 
 static void store_all(int fd, const intel_ctx_t *ctx)
@@ -184,10 +227,11 @@ static void store_all(int fd, const intel_ctx_t *ctx)
 	struct drm_i915_gem_execbuffer2 execbuf;
 	unsigned *engines, *permuted;
 	uint32_t batch[16];
-	uint64_t offset;
+	uint64_t offset, ahnd, dst_offset;
 	unsigned nengine;
-	int value;
+	int value, address;
 	int i, j;
+	bool do_relocs = gem_has_relocations(fd);
 
 	nengine = 0;
 	for_each_ctx_engine(fd, ctx, engine) {
@@ -213,24 +257,41 @@ static void store_all(int fd, const intel_ctx_t *ctx)
 		execbuf.flags |= I915_EXEC_SECURE;
 	execbuf.rsvd1 = ctx->id;
 
+	ahnd = intel_allocator_open(fd, ctx->id, INTEL_ALLOCATOR_SIMPLE);
+
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = gem_create(fd, nengine*sizeof(uint32_t));
+	obj[0].offset = intel_allocator_alloc(ahnd, obj[0].handle,
+					      nengine*sizeof(uint32_t), ALIGNMENT);
+	obj[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_WRITE;
+	obj[0].offset = CANONICAL(obj[0].offset);
 	obj[1].handle = gem_create(fd, 2*nengine*sizeof(batch));
-	obj[1].relocation_count = 1;
+	obj[1].offset = intel_allocator_alloc(ahnd, obj[1].handle,
+					      nengine*sizeof(uint32_t), ALIGNMENT);
+	obj[1].offset = CANONICAL(obj[1].offset);
+	obj[1].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+	if (do_relocs) {
+		obj[1].relocation_count = 1;
+	} else {
+		obj[0].flags |= EXEC_OBJECT_PINNED;
+		obj[1].flags |= EXEC_OBJECT_PINNED;
+		execbuf.flags |= I915_EXEC_NO_RELOC;
+	}
 
 	offset = sizeof(uint32_t);
 	i = 0;
 	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
 	if (gen >= 8) {
-		batch[++i] = 0;
+		batch[address = ++i] = 0;
 		batch[++i] = 0;
 	} else if (gen >= 4) {
 		batch[++i] = 0;
-		batch[++i] = 0;
+		batch[address = ++i] = 0;
 		offset += sizeof(uint32_t);
 	} else {
 		batch[i]--;
-		batch[++i] = 0;
+		batch[address = ++i] = 0;
 	}
 	batch[value = ++i] = 0xc0ffee;
 	batch[++i] = MI_BATCH_BUFFER_END;
@@ -246,12 +307,17 @@ static void store_all(int fd, const intel_ctx_t *ctx)
 
 		j = 2*nengine;
 		reloc[j].target_handle = obj[0].handle;
-		reloc[j].presumed_offset = ~0;
+		reloc[j].presumed_offset = obj[0].offset;
 		reloc[j].offset = j*sizeof(batch) + offset;
 		reloc[j].delta = nengine*sizeof(uint32_t);
 		reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
 		reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-		obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
+		dst_offset = CANONICAL(obj[0].offset + reloc[j].delta);
+		batch[address] = dst_offset;
+		if (gen >= 8)
+			batch[address + 1] = dst_offset >> 32;
+		if (do_relocs)
+			obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
 
 		batch[value] = 0xdeadbeef;
 		gem_write(fd, obj[1].handle, j*sizeof(batch),
@@ -261,12 +327,17 @@ static void store_all(int fd, const intel_ctx_t *ctx)
 
 		j = 2*nengine + 1;
 		reloc[j].target_handle = obj[0].handle;
-		reloc[j].presumed_offset = ~0;
+		reloc[j].presumed_offset = obj[0].offset;
 		reloc[j].offset = j*sizeof(batch) + offset;
 		reloc[j].delta = nengine*sizeof(uint32_t);
 		reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
 		reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-		obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
+		dst_offset = CANONICAL(obj[0].offset + reloc[j].delta);
+		batch[address] = dst_offset;
+		if (gen >= 8)
+			batch[address + 1] = dst_offset >> 32;
+		if (do_relocs)
+			obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
 
 		batch[value] = nengine;
 		gem_write(fd, obj[1].handle, j*sizeof(batch),
@@ -279,30 +350,37 @@ static void store_all(int fd, const intel_ctx_t *ctx)
 	gem_sync(fd, obj[1].handle);
 
 	for (i = 0; i < nengine; i++) {
-		obj[1].relocs_ptr = to_user_pointer(&reloc[2*i]);
 		execbuf.batch_start_offset = 2*i*sizeof(batch);
 		memcpy(permuted, engines, nengine*sizeof(engines[0]));
 		igt_permute_array(permuted, nengine, igt_exchange_int);
+		if (do_relocs)
+			obj[1].relocs_ptr = to_user_pointer(&reloc[2*i]);
+
 		for (j = 0; j < nengine; j++) {
 			execbuf.flags &= ~ENGINE_MASK;
 			execbuf.flags |= permuted[j];
 			gem_execbuf(fd, &execbuf);
 		}
-		obj[1].relocs_ptr = to_user_pointer(&reloc[2*i+1]);
 		execbuf.batch_start_offset = (2*i+1)*sizeof(batch);
 		execbuf.flags &= ~ENGINE_MASK;
 		execbuf.flags |= engines[i];
+		if (do_relocs)
+			obj[1].relocs_ptr = to_user_pointer(&reloc[2*i+1]);
+
 		gem_execbuf(fd, &execbuf);
 	}
 	gem_close(fd, obj[1].handle);
+	intel_allocator_free(ahnd, obj[1].handle);
 
 	gem_read(fd, obj[0].handle, 0, engines, nengine*sizeof(engines[0]));
 	gem_close(fd, obj[0].handle);
+	intel_allocator_free(ahnd, obj[0].handle);
 
 	for (i = 0; i < nengine; i++)
 		igt_assert_eq_u32(engines[i], i);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 
+	intel_allocator_close(ahnd);
 	free(permuted);
 	free(engines);
 	free(reloc);
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t 1/2] tests/gem_exec_store: Support gens without relocations

[Zbigniew Kempczyński]

On Tue, Aug 10, 2021 at 09:14:24PM +0200, Andrzej Turko wrote:
> With relocations disabled on newer generations
> tests must assign addresses to objects by
> themselves instead of relying on the driver.
> 
> Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  tests/i915/gem_exec_store.c | 134 ++++++++++++++++++++++++++++--------
>  1 file changed, 106 insertions(+), 28 deletions(-)
> 
> diff --git a/tests/i915/gem_exec_store.c b/tests/i915/gem_exec_store.c
> index 0798f61d7..cb99f9510 100644
> --- a/tests/i915/gem_exec_store.c
> +++ b/tests/i915/gem_exec_store.c
> @@ -37,6 +37,9 @@
>  
>  #define ENGINE_MASK  (I915_EXEC_RING_MASK | I915_EXEC_BSD_MASK)
>  
> +/* Without alignment detection we assume the worst-case scenario. */
> +#define ALIGNMENT (1 << 21)
> +
>  static void store_dword(int fd, const intel_ctx_t *ctx,
>  			const struct intel_execution_engine2 *e)
>  {
> @@ -45,6 +48,7 @@ static void store_dword(int fd, const intel_ctx_t *ctx,
>  	struct drm_i915_gem_relocation_entry reloc;
>  	struct drm_i915_gem_execbuffer2 execbuf;
>  	uint32_t batch[16];
> +	uint64_t ahnd;
>  	int i;
>  
>  	intel_detect_and_clear_missed_interrupts(fd);
> @@ -56,43 +60,63 @@ static void store_dword(int fd, const intel_ctx_t *ctx,
>  		execbuf.flags |= I915_EXEC_SECURE;
>  	execbuf.rsvd1 = ctx->id;
>  
> +	ahnd = intel_allocator_open(fd, ctx->id, INTEL_ALLOCATOR_SIMPLE);
> +
>  	memset(obj, 0, sizeof(obj));
>  	obj[0].handle = gem_create(fd, 4096);
> +	obj[0].offset = intel_allocator_alloc(ahnd, obj[0].handle,
> +					      4096, ALIGNMENT);
> +	obj[0].offset = CANONICAL(obj[0].offset);
> +	obj[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_WRITE;
>  	obj[1].handle = gem_create(fd, 4096);
> +	obj[1].offset = intel_allocator_alloc(ahnd, obj[1].handle,
> +					      4096, ALIGNMENT);
> +	obj[1].offset = CANONICAL(obj[1].offset);
> +	obj[1].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>  
>  	memset(&reloc, 0, sizeof(reloc));
>  	reloc.target_handle = obj[0].handle;
> -	reloc.presumed_offset = 0;
> +	reloc.presumed_offset = obj[0].offset;
>  	reloc.offset = sizeof(uint32_t);
>  	reloc.delta = 0;
>  	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>  	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> -	obj[1].relocs_ptr = to_user_pointer(&reloc);
> -	obj[1].relocation_count = 1;
> +
> +	if (gem_has_relocations(fd)) {
> +		obj[1].relocs_ptr = to_user_pointer(&reloc);
> +		obj[1].relocation_count = 1;
> +	} else {
> +		obj[0].flags |= EXEC_OBJECT_PINNED;
> +		obj[1].flags |= EXEC_OBJECT_PINNED;
> +		execbuf.flags |= I915_EXEC_NO_RELOC;
> +	}
>  
>  	i = 0;
>  	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>  	if (gen >= 8) {
> -		batch[++i] = 0;
> -		batch[++i] = 0;
> +		batch[++i] = obj[0].offset;
> +		batch[++i] = obj[0].offset >> 32;
>  	} else if (gen >= 4) {
>  		batch[++i] = 0;
> -		batch[++i] = 0;
> +		batch[++i] = obj[0].offset;
>  		reloc.offset += sizeof(uint32_t);
>  	} else {
>  		batch[i]--;
> -		batch[++i] = 0;
> +		batch[++i] = obj[0].offset;
>  	}
>  	batch[++i] = 0xc0ffee;
>  	batch[++i] = MI_BATCH_BUFFER_END;
>  	gem_write(fd, obj[1].handle, 0, batch, sizeof(batch));
>  	gem_execbuf(fd, &execbuf);
>  	gem_close(fd, obj[1].handle);
> +	intel_allocator_free(ahnd, obj[1].handle);
>  
>  	gem_read(fd, obj[0].handle, 0, batch, sizeof(batch));
>  	gem_close(fd, obj[0].handle);
> +	intel_allocator_free(ahnd, obj[0].handle);
>  	igt_assert_eq(*batch, 0xc0ffee);
>  	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> +	intel_allocator_close(ahnd);
>  }
>  
>  #define PAGES 1
> @@ -106,7 +130,9 @@ static void store_cachelines(int fd, const intel_ctx_t *ctx,
>  	struct drm_i915_gem_execbuffer2 execbuf;
>  #define NCACHELINES (4096/64)
>  	uint32_t *batch;
> +	uint64_t ahnd, dst_offset;
>  	int i;
> +	bool do_relocs = gem_has_relocations(fd);
>  
>  	reloc = calloc(NCACHELINES, sizeof(*reloc));
>  	igt_assert(reloc);
> @@ -119,12 +145,25 @@ static void store_cachelines(int fd, const intel_ctx_t *ctx,
>  		execbuf.flags |= I915_EXEC_SECURE;
>  	execbuf.rsvd1 = ctx->id;
>  
> +	ahnd = intel_allocator_open(fd, ctx->id, INTEL_ALLOCATOR_SIMPLE);
>  	obj = calloc(execbuf.buffer_count, sizeof(*obj));
>  	igt_assert(obj);
> -	for (i = 0; i < execbuf.buffer_count; i++)
> +	for (i = 0; i < execbuf.buffer_count; i++) {
>  		obj[i].handle = gem_create(fd, 4096);
> -	obj[i-1].relocs_ptr = to_user_pointer(reloc);
> -	obj[i-1].relocation_count = NCACHELINES;
> +		obj[i].offset = intel_allocator_alloc(ahnd, obj[i].handle,
> +						      4096, ALIGNMENT);
> +		obj[i].offset = CANONICAL(obj[i].offset);
> +		obj[i].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
> +			       (do_relocs ? 0 : EXEC_OBJECT_PINNED);
> +		if (i + 1 < execbuf.buffer_count)
> +			obj[i].flags |= EXEC_OBJECT_WRITE;
> +	}
> +	if (do_relocs) {
> +		obj[i-1].relocs_ptr = to_user_pointer(reloc);
> +		obj[i-1].relocation_count = NCACHELINES;
> +	} else {
> +		execbuf.flags |= I915_EXEC_NO_RELOC;
> +	}
>  	execbuf.buffers_ptr = to_user_pointer(obj);
>  
>  	batch = gem_mmap__cpu(fd, obj[i-1].handle, 0, 4096, PROT_WRITE);
> @@ -132,23 +171,24 @@ static void store_cachelines(int fd, const intel_ctx_t *ctx,
>  	i = 0;
>  	for (unsigned n = 0; n < NCACHELINES; n++) {
>  		reloc[n].target_handle = obj[n % (execbuf.buffer_count-1)].handle;
> -		reloc[n].presumed_offset = -1;
> +		reloc[n].presumed_offset = obj[n % (execbuf.buffer_count-1)].offset;
>  		reloc[n].offset = (i + 1)*sizeof(uint32_t);
>  		reloc[n].delta = 4 * (n * 16 + n % 16);
>  		reloc[n].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>  		reloc[n].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> +		dst_offset = CANONICAL(reloc[n].presumed_offset + reloc[n].delta);
>  
>  		batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>  		if (gen >= 8) {
> -			batch[++i] = 0;
> -			batch[++i] = 0;
> +			batch[++i] = dst_offset;
> +			batch[++i] = dst_offset >> 32;
>  		} else if (gen >= 4) {
>  			batch[++i] = 0;
> -			batch[++i] = 0;
> +			batch[++i] = dst_offset;
>  			reloc[n].offset += sizeof(uint32_t);
>  		} else {
>  			batch[i]--;
> -			batch[++i] = 0;
> +			batch[++i] = dst_offset;
>  		}
>  		batch[++i] = n | ~n << 16;
>  		i++;
> @@ -168,11 +208,14 @@ static void store_cachelines(int fd, const intel_ctx_t *ctx,
>  	}
>  	free(reloc);
>  
> -	for (unsigned n = 0; n < execbuf.buffer_count; n++)
> +	for (unsigned n = 0; n < execbuf.buffer_count; n++) {
>  		gem_close(fd, obj[n].handle);
> +		intel_allocator_free(ahnd, obj[n].handle);
> +	}
>  	free(obj);
>  
>  	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> +	intel_allocator_close(ahnd);
>  }
>  
>  static void store_all(int fd, const intel_ctx_t *ctx)
> @@ -184,10 +227,11 @@ static void store_all(int fd, const intel_ctx_t *ctx)
>  	struct drm_i915_gem_execbuffer2 execbuf;
>  	unsigned *engines, *permuted;
>  	uint32_t batch[16];
> -	uint64_t offset;
> +	uint64_t offset, ahnd, dst_offset;
>  	unsigned nengine;
> -	int value;
> +	int value, address;
>  	int i, j;
> +	bool do_relocs = gem_has_relocations(fd);
>  
>  	nengine = 0;
>  	for_each_ctx_engine(fd, ctx, engine) {
> @@ -213,24 +257,41 @@ static void store_all(int fd, const intel_ctx_t *ctx)
>  		execbuf.flags |= I915_EXEC_SECURE;
>  	execbuf.rsvd1 = ctx->id;
>  
> +	ahnd = intel_allocator_open(fd, ctx->id, INTEL_ALLOCATOR_SIMPLE);
> +
>  	memset(obj, 0, sizeof(obj));
>  	obj[0].handle = gem_create(fd, nengine*sizeof(uint32_t));
> +	obj[0].offset = intel_allocator_alloc(ahnd, obj[0].handle,
> +					      nengine*sizeof(uint32_t), ALIGNMENT);
> +	obj[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_WRITE;
> +	obj[0].offset = CANONICAL(obj[0].offset);
>  	obj[1].handle = gem_create(fd, 2*nengine*sizeof(batch));
> -	obj[1].relocation_count = 1;
> +	obj[1].offset = intel_allocator_alloc(ahnd, obj[1].handle,
> +					      nengine*sizeof(uint32_t), ALIGNMENT);
> +	obj[1].offset = CANONICAL(obj[1].offset);
> +	obj[1].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +
> +	if (do_relocs) {
> +		obj[1].relocation_count = 1;
> +	} else {
> +		obj[0].flags |= EXEC_OBJECT_PINNED;
> +		obj[1].flags |= EXEC_OBJECT_PINNED;
> +		execbuf.flags |= I915_EXEC_NO_RELOC;
> +	}
>  
>  	offset = sizeof(uint32_t);
>  	i = 0;
>  	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>  	if (gen >= 8) {
> -		batch[++i] = 0;
> +		batch[address = ++i] = 0;
>  		batch[++i] = 0;
>  	} else if (gen >= 4) {
>  		batch[++i] = 0;
> -		batch[++i] = 0;
> +		batch[address = ++i] = 0;
>  		offset += sizeof(uint32_t);
>  	} else {
>  		batch[i]--;
> -		batch[++i] = 0;
> +		batch[address = ++i] = 0;
>  	}
>  	batch[value = ++i] = 0xc0ffee;
>  	batch[++i] = MI_BATCH_BUFFER_END;
> @@ -246,12 +307,17 @@ static void store_all(int fd, const intel_ctx_t *ctx)
>  
>  		j = 2*nengine;
>  		reloc[j].target_handle = obj[0].handle;
> -		reloc[j].presumed_offset = ~0;
> +		reloc[j].presumed_offset = obj[0].offset;
>  		reloc[j].offset = j*sizeof(batch) + offset;
>  		reloc[j].delta = nengine*sizeof(uint32_t);
>  		reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>  		reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> -		obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
> +		dst_offset = CANONICAL(obj[0].offset + reloc[j].delta);
> +		batch[address] = dst_offset;
> +		if (gen >= 8)
> +			batch[address + 1] = dst_offset >> 32;
> +		if (do_relocs)
> +			obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
>  
>  		batch[value] = 0xdeadbeef;
>  		gem_write(fd, obj[1].handle, j*sizeof(batch),
> @@ -261,12 +327,17 @@ static void store_all(int fd, const intel_ctx_t *ctx)
>  
>  		j = 2*nengine + 1;
>  		reloc[j].target_handle = obj[0].handle;
> -		reloc[j].presumed_offset = ~0;
> +		reloc[j].presumed_offset = obj[0].offset;
>  		reloc[j].offset = j*sizeof(batch) + offset;
>  		reloc[j].delta = nengine*sizeof(uint32_t);
>  		reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>  		reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> -		obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
> +		dst_offset = CANONICAL(obj[0].offset + reloc[j].delta);
> +		batch[address] = dst_offset;
> +		if (gen >= 8)
> +			batch[address + 1] = dst_offset >> 32;
> +		if (do_relocs)
> +			obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
>  
>  		batch[value] = nengine;
>  		gem_write(fd, obj[1].handle, j*sizeof(batch),
> @@ -279,30 +350,37 @@ static void store_all(int fd, const intel_ctx_t *ctx)
>  	gem_sync(fd, obj[1].handle);
>  
>  	for (i = 0; i < nengine; i++) {
> -		obj[1].relocs_ptr = to_user_pointer(&reloc[2*i]);
>  		execbuf.batch_start_offset = 2*i*sizeof(batch);
>  		memcpy(permuted, engines, nengine*sizeof(engines[0]));
>  		igt_permute_array(permuted, nengine, igt_exchange_int);
> +		if (do_relocs)
> +			obj[1].relocs_ptr = to_user_pointer(&reloc[2*i]);
> +
>  		for (j = 0; j < nengine; j++) {
>  			execbuf.flags &= ~ENGINE_MASK;
>  			execbuf.flags |= permuted[j];
>  			gem_execbuf(fd, &execbuf);
>  		}
> -		obj[1].relocs_ptr = to_user_pointer(&reloc[2*i+1]);
>  		execbuf.batch_start_offset = (2*i+1)*sizeof(batch);
>  		execbuf.flags &= ~ENGINE_MASK;
>  		execbuf.flags |= engines[i];
> +		if (do_relocs)
> +			obj[1].relocs_ptr = to_user_pointer(&reloc[2*i+1]);
> +
>  		gem_execbuf(fd, &execbuf);
>  	}
>  	gem_close(fd, obj[1].handle);
> +	intel_allocator_free(ahnd, obj[1].handle);
>  
>  	gem_read(fd, obj[0].handle, 0, engines, nengine*sizeof(engines[0]));
>  	gem_close(fd, obj[0].handle);
> +	intel_allocator_free(ahnd, obj[0].handle);
>  
>  	for (i = 0; i < nengine; i++)
>  		igt_assert_eq_u32(engines[i], i);
>  	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
>  
> +	intel_allocator_close(ahnd);
>  	free(permuted);
>  	free(engines);
>  	free(reloc);
> -- 
> 2.25.1
> 

LGTM

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

Re: [igt-dev] [PATCH i-g-t 1/2] tests/gem_exec_store: Support gens without relocations

[Dixit, Ashutosh]

On Tue, 10 Aug 2021 12:14:24 -0700, Andrzej Turko wrote:
>
> @@ -213,24 +257,41 @@ static void store_all(int fd, const intel_ctx_t *ctx)
>		execbuf.flags |= I915_EXEC_SECURE;
>	execbuf.rsvd1 = ctx->id;
>
> +	ahnd = intel_allocator_open(fd, ctx->id, INTEL_ALLOCATOR_SIMPLE);
> +
>	memset(obj, 0, sizeof(obj));
>	obj[0].handle = gem_create(fd, nengine*sizeof(uint32_t));
> +	obj[0].offset = intel_allocator_alloc(ahnd, obj[0].handle,
> +					      nengine*sizeof(uint32_t), ALIGNMENT);
> +	obj[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_WRITE;
> +	obj[0].offset = CANONICAL(obj[0].offset);
>	obj[1].handle = gem_create(fd, 2*nengine*sizeof(batch));
> -	obj[1].relocation_count = 1;
> +	obj[1].offset = intel_allocator_alloc(ahnd, obj[1].handle,
> +					      nengine*sizeof(uint32_t), ALIGNMENT);

Is this correct, or should the size argument be 2*nengine*sizeof(batch)
(instead of nengine*sizeof(uint32_t))?

> +	obj[1].offset = CANONICAL(obj[1].offset);
> +	obj[1].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;

Re: [igt-dev] [PATCH i-g-t 1/2] tests/gem_exec_store: Support gens without relocations

[Zbigniew Kempczyński]

On Tue, Mar 29, 2022 at 11:08:11PM -0700, Dixit, Ashutosh wrote:
> On Tue, 10 Aug 2021 12:14:24 -0700, Andrzej Turko wrote:
> >
> > @@ -213,24 +257,41 @@ static void store_all(int fd, const intel_ctx_t *ctx)
> >		execbuf.flags |= I915_EXEC_SECURE;
> >	execbuf.rsvd1 = ctx->id;
> >
> > +	ahnd = intel_allocator_open(fd, ctx->id, INTEL_ALLOCATOR_SIMPLE);
> > +
> >	memset(obj, 0, sizeof(obj));
> >	obj[0].handle = gem_create(fd, nengine*sizeof(uint32_t));
> > +	obj[0].offset = intel_allocator_alloc(ahnd, obj[0].handle,
> > +					      nengine*sizeof(uint32_t), ALIGNMENT);
> > +	obj[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_WRITE;
> > +	obj[0].offset = CANONICAL(obj[0].offset);
> >	obj[1].handle = gem_create(fd, 2*nengine*sizeof(batch));
> > -	obj[1].relocation_count = 1;
> > +	obj[1].offset = intel_allocator_alloc(ahnd, obj[1].handle,
> > +					      nengine*sizeof(uint32_t), ALIGNMENT);
> 
> Is this correct, or should the size argument be 2*nengine*sizeof(batch)
> (instead of nengine*sizeof(uint32_t))?

Definitely yes. Further allocations still can fit into hole between objects.
I would remove ALIGNMENT at all. It should work because we now use safe
alignment as you proposed couple of weeks ago (that was very good idea).

--
Zbigniew

> 
> > +	obj[1].offset = CANONICAL(obj[1].offset);
> > +	obj[1].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;

[igt-dev] [PATCH i-g-t 2/2] tests/gem_softpin: Exercise eviction with softpinning

[Andrzej Turko]

Exercise eviction of many gem objects. The added tests are analogous
to gem_exec_gttfill, but they use softpin and do not require relocation
support.

Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/i915/gem_softpin.c | 212 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 211 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
index 5e47a0ce3..d085dea34 100644
--- a/tests/i915/gem_softpin.c
+++ b/tests/i915/gem_softpin.c
@@ -29,6 +29,7 @@
 #include "i915/gem.h"
 #include "i915/gem_create.h"
 #include "igt.h"
+#include "igt_rand.h"
 #include "intel_allocator.h"
 
 #define EXEC_OBJECT_PINNED	(1<<4)
@@ -878,9 +879,208 @@ static void test_allocator_fork(int fd)
 	intel_allocator_multiprocess_stop();
 }
 
+#define BATCH_SIZE (4096<<10)
+/* We don't have alignment detection yet, so assume the worst-case scenario. */
+#define BATCH_ALIGNMENT (1 << 21)
+
+struct batch {
+	uint32_t handle;
+	void *ptr;
+};
+
+static void xchg_batch(void *array, unsigned int i, unsigned int j)
+{
+	struct batch *batches = array;
+	struct batch tmp;
+
+	tmp = batches[i];
+	batches[i] = batches[j];
+	batches[j] = tmp;
+}
+
+static void submit(int fd, int gen,
+		   struct drm_i915_gem_execbuffer2 *eb,
+		   struct batch *batches, unsigned int count,
+		   uint64_t ahnd)
+{
+	struct drm_i915_gem_exec_object2 obj;
+	uint32_t batch[16];
+	uint64_t address;
+	unsigned n;
+
+	memset(&obj, 0, sizeof(obj));
+	obj.flags = EXEC_OBJECT_PINNED;
+
+	for (unsigned i = 0; i < count; i++) {
+		obj.handle = batches[i].handle;
+		obj.offset = intel_allocator_alloc(ahnd, obj.handle,
+						   BATCH_SIZE,
+						   BATCH_ALIGNMENT);
+		address = obj.offset + BATCH_SIZE - eb->batch_start_offset - 8;
+		n = 0;
+		batch[n] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+		if (gen >= 8) {
+			batch[n] |= 1 << 21;
+			batch[n]++;
+			batch[++n] = address;
+			batch[++n] = address >> 32;
+		} else if (gen >= 4) {
+			batch[++n] = 0;
+			batch[++n] = address;
+		} else {
+			batch[n]--;
+			batch[++n] = address;
+		}
+		batch[++n] = obj.offset; /* lower_32_bits(value) */
+		batch[++n] = obj.offset >> 32; /* upper_32_bits(value) / nop */
+		batch[++n] = MI_BATCH_BUFFER_END;
+		eb->buffers_ptr = to_user_pointer(&obj);
+
+		memcpy(batches[i].ptr + eb->batch_start_offset,
+		       batch, sizeof(batch));
+
+		gem_execbuf(fd, eb);
+	}
+	/* As we have been lying about the write_domain, we need to do a sync */
+	gem_sync(fd, obj.handle);
+}
+
+static void test_allocator_evict(int fd, const intel_ctx_t *ctx,
+				 unsigned ring, int timeout)
+{
+	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+	struct drm_i915_gem_execbuffer2 execbuf;
+	unsigned engines[I915_EXEC_RING_MASK + 1];
+	volatile uint64_t *shared;
+	struct timespec tv = {};
+	struct batch *batches;
+	unsigned nengine;
+	unsigned count;
+	uint64_t size, ahnd;
+
+	shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+	igt_assert(shared != MAP_FAILED);
+
+	nengine = 0;
+	if (ring == ALL_ENGINES) {
+		struct intel_execution_engine2 *e;
+
+		for_each_ctx_engine(fd, ctx, e) {
+			if (!gem_class_can_store_dword(fd, e->class))
+				continue;
+
+			engines[nengine++] = e->flags;
+		}
+	} else {
+		engines[nengine++] = ring;
+	}
+	igt_require(nengine);
+	igt_assert(nengine * 64 <= BATCH_SIZE);
+
+	size = gem_aperture_size(fd);
+	if (!gem_uses_full_ppgtt(fd))
+		size /= 2;
+	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
+		size = 1ull << 32;
+	igt_require(size < (1ull<<32) * BATCH_SIZE);
+
+	count = size / BATCH_SIZE + 1;
+	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
+		  count, (long long)size, nengine);
+
+	intel_allocator_multiprocess_start();
+	ahnd = intel_allocator_open_full(fd, 0, 0, size / 16,
+					 INTEL_ALLOCATOR_RELOC,
+					 ALLOC_STRATEGY_NONE);
+
+	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
+	intel_detect_and_clear_missed_interrupts(fd);
+
+	igt_nsec_elapsed(&tv);
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffer_count = 1;
+	if (gen < 6)
+		execbuf.flags |= I915_EXEC_SECURE;
+
+	batches = calloc(count, sizeof(*batches));
+	igt_assert(batches);
+	for (unsigned i = 0; i < count; i++) {
+		batches[i].handle = gem_create(fd, BATCH_SIZE);
+		batches[i].ptr =
+			gem_mmap__device_coherent(fd, batches[i].handle,
+						  0, BATCH_SIZE, PROT_WRITE);
+	}
+
+	/* Flush all memory before we start the timer */
+	submit(fd, gen, &execbuf, batches, count, ahnd);
+
+	igt_info("Setup %u batches in %.2fms\n",
+		 count, 1e-6 * igt_nsec_elapsed(&tv));
+
+	igt_fork(child, nengine) {
+		uint64_t dst, src, dst_offset, src_offset;
+		uint64_t cycles = 0;
+
+		hars_petruska_f54_1_random_perturb(child);
+		igt_permute_array(batches, count, xchg_batch);
+		execbuf.batch_start_offset = child * 64;
+		execbuf.flags |= engines[child];
+
+		dst_offset = BATCH_SIZE - child*64 - 8;
+		if (gen >= 8)
+			src_offset = child*64 + 3*sizeof(uint32_t);
+		else if (gen >= 4)
+			src_offset = child*64 + 4*sizeof(uint32_t);
+		else
+			src_offset = child*64 + 2*sizeof(uint32_t);
+
+		/* We need to open the allocator again in the new process */
+		ahnd = intel_allocator_open_full(fd, 0, 0, size / 16,
+						 INTEL_ALLOCATOR_RELOC,
+						 ALLOC_STRATEGY_NONE);
+
+		igt_until_timeout(timeout) {
+			submit(fd, gen, &execbuf, batches, count, ahnd);
+			for (unsigned i = 0; i < count; i++) {
+				dst = *(uint64_t *)(batches[i].ptr + dst_offset);
+				src = *(uint64_t *)(batches[i].ptr + src_offset);
+				igt_assert_eq_u64(dst, src);
+			}
+			cycles++;
+		}
+		shared[child] = cycles;
+		igt_info("engine[%d]: %llu cycles\n", child, (long long)cycles);
+		intel_allocator_close(ahnd);
+	}
+	igt_waitchildren();
+
+	intel_allocator_close(ahnd);
+	intel_allocator_multiprocess_stop();
+
+	for (unsigned i = 0; i < count; i++) {
+		munmap(batches[i].ptr, BATCH_SIZE);
+		gem_close(fd, batches[i].handle);
+	}
+	free(batches);
+
+	shared[nengine] = 0;
+	for (unsigned i = 0; i < nengine; i++)
+		shared[nengine] += shared[i];
+	igt_info("Total: %llu cycles\n", (long long)shared[nengine]);
+
+	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+}
+
+#define test_each_engine(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
+		igt_dynamic_f("%s", e->name)
+
 igt_main
 {
+	const struct intel_execution_engine2 *e;
 	int fd = -1;
+	const intel_ctx_t *ctx;
 
 	igt_fixture {
 		fd = drm_open_driver_master(DRIVER_INTEL);
@@ -888,6 +1088,8 @@ igt_main
 		gem_require_blitter(fd);
 		igt_require(gem_has_softpin(fd));
 		igt_require(gem_can_store_dword(fd, 0));
+
+		ctx = intel_ctx_create_all_physical(fd);
 	}
 
 	igt_subtest("invalid")
@@ -923,6 +1125,12 @@ igt_main
 
 		igt_subtest("allocator-fork")
 			test_allocator_fork(fd);
+
+		test_each_engine("allocator-evict", fd, ctx, e)
+			test_allocator_evict(fd, ctx, e->flags, 20);
+
+		igt_subtest("allocator-evict-all-engines")
+			test_allocator_evict(fd, ctx, ALL_ENGINES, 20);
 	}
 
 	igt_subtest("softpin")
@@ -950,6 +1158,8 @@ igt_main
 	igt_subtest("evict-hang")
 		test_evict_hang(fd);
 
-	igt_fixture
+	igt_fixture {
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
+	}
 }
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t 2/2] tests/gem_softpin: Exercise eviction with softpinning

[Zbigniew Kempczyński]

On Tue, Aug 10, 2021 at 09:14:25PM +0200, Andrzej Turko wrote:
> Exercise eviction of many gem objects. The added tests are analogous
> to gem_exec_gttfill, but they use softpin and do not require relocation
> support.
> 
> Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
>  tests/i915/gem_softpin.c | 212 ++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 211 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
> index 5e47a0ce3..d085dea34 100644
> --- a/tests/i915/gem_softpin.c
> +++ b/tests/i915/gem_softpin.c
> @@ -29,6 +29,7 @@
>  #include "i915/gem.h"
>  #include "i915/gem_create.h"
>  #include "igt.h"
> +#include "igt_rand.h"
>  #include "intel_allocator.h"
>  
>  #define EXEC_OBJECT_PINNED	(1<<4)
> @@ -878,9 +879,208 @@ static void test_allocator_fork(int fd)
>  	intel_allocator_multiprocess_stop();
>  }
>  
> +#define BATCH_SIZE (4096<<10)
> +/* We don't have alignment detection yet, so assume the worst-case scenario. */
> +#define BATCH_ALIGNMENT (1 << 21)
> +
> +struct batch {
> +	uint32_t handle;
> +	void *ptr;
> +};
> +
> +static void xchg_batch(void *array, unsigned int i, unsigned int j)
> +{
> +	struct batch *batches = array;
> +	struct batch tmp;
> +
> +	tmp = batches[i];
> +	batches[i] = batches[j];
> +	batches[j] = tmp;
> +}
> +
> +static void submit(int fd, int gen,
> +		   struct drm_i915_gem_execbuffer2 *eb,
> +		   struct batch *batches, unsigned int count,
> +		   uint64_t ahnd)
> +{
> +	struct drm_i915_gem_exec_object2 obj;
> +	uint32_t batch[16];
> +	uint64_t address;
> +	unsigned n;
> +
> +	memset(&obj, 0, sizeof(obj));
> +	obj.flags = EXEC_OBJECT_PINNED;
> +
> +	for (unsigned i = 0; i < count; i++) {
> +		obj.handle = batches[i].handle;
> +		obj.offset = intel_allocator_alloc(ahnd, obj.handle,
> +						   BATCH_SIZE,
> +						   BATCH_ALIGNMENT);
> +		address = obj.offset + BATCH_SIZE - eb->batch_start_offset - 8;
> +		n = 0;
> +		batch[n] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> +		if (gen >= 8) {
> +			batch[n] |= 1 << 21;
> +			batch[n]++;
> +			batch[++n] = address;
> +			batch[++n] = address >> 32;
> +		} else if (gen >= 4) {
> +			batch[++n] = 0;
> +			batch[++n] = address;
> +		} else {
> +			batch[n]--;
> +			batch[++n] = address;
> +		}
> +		batch[++n] = obj.offset; /* lower_32_bits(value) */
> +		batch[++n] = obj.offset >> 32; /* upper_32_bits(value) / nop */
> +		batch[++n] = MI_BATCH_BUFFER_END;
> +		eb->buffers_ptr = to_user_pointer(&obj);
> +
> +		memcpy(batches[i].ptr + eb->batch_start_offset,
> +		       batch, sizeof(batch));
> +
> +		gem_execbuf(fd, eb);
> +	}
> +	/* As we have been lying about the write_domain, we need to do a sync */
> +	gem_sync(fd, obj.handle);
> +}
> +
> +static void test_allocator_evict(int fd, const intel_ctx_t *ctx,
> +				 unsigned ring, int timeout)
> +{
> +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	unsigned engines[I915_EXEC_RING_MASK + 1];
> +	volatile uint64_t *shared;
> +	struct timespec tv = {};
> +	struct batch *batches;
> +	unsigned nengine;
> +	unsigned count;
> +	uint64_t size, ahnd;
> +
> +	shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
> +	igt_assert(shared != MAP_FAILED);
> +
> +	nengine = 0;
> +	if (ring == ALL_ENGINES) {
> +		struct intel_execution_engine2 *e;
> +
> +		for_each_ctx_engine(fd, ctx, e) {
> +			if (!gem_class_can_store_dword(fd, e->class))
> +				continue;
> +
> +			engines[nengine++] = e->flags;
> +		}
> +	} else {
> +		engines[nengine++] = ring;
> +	}
> +	igt_require(nengine);
> +	igt_assert(nengine * 64 <= BATCH_SIZE);
> +
> +	size = gem_aperture_size(fd);
> +	if (!gem_uses_full_ppgtt(fd))
> +		size /= 2;
> +	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
> +		size = 1ull << 32;
> +	igt_require(size < (1ull<<32) * BATCH_SIZE);
> +
> +	count = size / BATCH_SIZE + 1;
> +	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
> +		  count, (long long)size, nengine);
> +
> +	intel_allocator_multiprocess_start();
> +	ahnd = intel_allocator_open_full(fd, 0, 0, size / 16,
> +					 INTEL_ALLOCATOR_RELOC,
> +					 ALLOC_STRATEGY_NONE);

Ok, narrowing vm end will increase evictions.

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

> +
> +	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
> +	intel_detect_and_clear_missed_interrupts(fd);
> +
> +	igt_nsec_elapsed(&tv);
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffer_count = 1;
> +	if (gen < 6)
> +		execbuf.flags |= I915_EXEC_SECURE;
> +
> +	batches = calloc(count, sizeof(*batches));
> +	igt_assert(batches);
> +	for (unsigned i = 0; i < count; i++) {
> +		batches[i].handle = gem_create(fd, BATCH_SIZE);
> +		batches[i].ptr =
> +			gem_mmap__device_coherent(fd, batches[i].handle,
> +						  0, BATCH_SIZE, PROT_WRITE);
> +	}
> +
> +	/* Flush all memory before we start the timer */
> +	submit(fd, gen, &execbuf, batches, count, ahnd);
> +
> +	igt_info("Setup %u batches in %.2fms\n",
> +		 count, 1e-6 * igt_nsec_elapsed(&tv));
> +
> +	igt_fork(child, nengine) {
> +		uint64_t dst, src, dst_offset, src_offset;
> +		uint64_t cycles = 0;
> +
> +		hars_petruska_f54_1_random_perturb(child);
> +		igt_permute_array(batches, count, xchg_batch);
> +		execbuf.batch_start_offset = child * 64;
> +		execbuf.flags |= engines[child];
> +
> +		dst_offset = BATCH_SIZE - child*64 - 8;
> +		if (gen >= 8)
> +			src_offset = child*64 + 3*sizeof(uint32_t);
> +		else if (gen >= 4)
> +			src_offset = child*64 + 4*sizeof(uint32_t);
> +		else
> +			src_offset = child*64 + 2*sizeof(uint32_t);
> +
> +		/* We need to open the allocator again in the new process */
> +		ahnd = intel_allocator_open_full(fd, 0, 0, size / 16,
> +						 INTEL_ALLOCATOR_RELOC,
> +						 ALLOC_STRATEGY_NONE);
> +
> +		igt_until_timeout(timeout) {
> +			submit(fd, gen, &execbuf, batches, count, ahnd);
> +			for (unsigned i = 0; i < count; i++) {
> +				dst = *(uint64_t *)(batches[i].ptr + dst_offset);
> +				src = *(uint64_t *)(batches[i].ptr + src_offset);
> +				igt_assert_eq_u64(dst, src);
> +			}
> +			cycles++;
> +		}
> +		shared[child] = cycles;
> +		igt_info("engine[%d]: %llu cycles\n", child, (long long)cycles);
> +		intel_allocator_close(ahnd);
> +	}
> +	igt_waitchildren();
> +
> +	intel_allocator_close(ahnd);
> +	intel_allocator_multiprocess_stop();
> +
> +	for (unsigned i = 0; i < count; i++) {
> +		munmap(batches[i].ptr, BATCH_SIZE);
> +		gem_close(fd, batches[i].handle);
> +	}
> +	free(batches);
> +
> +	shared[nengine] = 0;
> +	for (unsigned i = 0; i < nengine; i++)
> +		shared[nengine] += shared[i];
> +	igt_info("Total: %llu cycles\n", (long long)shared[nengine]);
> +
> +	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> +}
> +
> +#define test_each_engine(T, i915, ctx, e) \
> +	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
> +		igt_dynamic_f("%s", e->name)
> +
>  igt_main
>  {
> +	const struct intel_execution_engine2 *e;
>  	int fd = -1;
> +	const intel_ctx_t *ctx;
>  
>  	igt_fixture {
>  		fd = drm_open_driver_master(DRIVER_INTEL);
> @@ -888,6 +1088,8 @@ igt_main
>  		gem_require_blitter(fd);
>  		igt_require(gem_has_softpin(fd));
>  		igt_require(gem_can_store_dword(fd, 0));
> +
> +		ctx = intel_ctx_create_all_physical(fd);
>  	}
>  
>  	igt_subtest("invalid")
> @@ -923,6 +1125,12 @@ igt_main
>  
>  		igt_subtest("allocator-fork")
>  			test_allocator_fork(fd);
> +
> +		test_each_engine("allocator-evict", fd, ctx, e)
> +			test_allocator_evict(fd, ctx, e->flags, 20);
> +
> +		igt_subtest("allocator-evict-all-engines")
> +			test_allocator_evict(fd, ctx, ALL_ENGINES, 20);
>  	}
>  
>  	igt_subtest("softpin")
> @@ -950,6 +1158,8 @@ igt_main
>  	igt_subtest("evict-hang")
>  		test_evict_hang(fd);
>  
> -	igt_fixture
> +	igt_fixture {
> +		intel_ctx_destroy(fd, ctx);
>  		close(fd);
> +	}
>  }
> -- 
> 2.25.1
> 

[igt-dev] ✓ Fi.CI.BAT: success for Keep tests working without relocations (rev9)

[Patchwork]

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== Series Details ==

Series: Keep tests working without relocations (rev9)
URL   : https://patchwork.freedesktop.org/series/90049/
State : success

== Summary ==

CI Bug Log - changes from IGT_6167 -> IGTPW_6112
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/index.html

Known issues
------------

  Here are the changes found in IGTPW_6112 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-rkl-guc:         [PASS][1] -> [DMESG-WARN][2] ([i915#3925])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/fi-rkl-guc/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/fi-rkl-guc/igt@core_hotunplug@unbind-rebind.html

  * igt@runner@aborted:
    - fi-rkl-guc:         NOTRUN -> [FAIL][3] ([i915#1602])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/fi-rkl-guc/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_store@basic:
    - {fi-dg1-1}:         [FAIL][4] ([i915#3717]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/fi-dg1-1/igt@gem_exec_store@basic.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/fi-dg1-1/igt@gem_exec_store@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#3717]: https://gitlab.freedesktop.org/drm/intel/issues/3717
  [i915#3925]: https://gitlab.freedesktop.org/drm/intel/issues/3925


Participating hosts (36 -> 33)
------------------------------

  Missing    (3): fi-bsw-cyan fi-icl-u2 fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6167 -> IGTPW_6112

  CI-20190529: 20190529
  CI_DRM_10465: b183cdc9ca5e84a70c1d9d57ab317319fb6bed65 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6112: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/index.html
  IGT_6167: 9e8cedeaf26344c7afd7185d6c2cf4b174560a33 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@gem_softpin@allocator-evict
+igt@gem_softpin@allocator-evict-all-engines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/index.html

[-- Attachment #2: Type: text/html, Size: 3125 bytes --]

[igt-dev] ✓ Fi.CI.IGT: success for Keep tests working without relocations (rev9)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30263 bytes --]

== Series Details ==

Series: Keep tests working without relocations (rev9)
URL   : https://patchwork.freedesktop.org/series/90049/
State : success

== Summary ==

CI Bug Log - changes from IGT_6167_full -> IGTPW_6112_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/index.html

New tests
---------

  New tests have been introduced between IGT_6167_full and IGTPW_6112_full:

### New IGT tests (7) ###

  * igt@gem_softpin@allocator-evict:
    - Statuses :
    - Exec time: [None] s

  * igt@gem_softpin@allocator-evict-all-engines:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0, 37.86] s

  * igt@gem_softpin@allocator-evict@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [27.81, 44.12] s

  * igt@gem_softpin@allocator-evict@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [27.32, 41.81] s

  * igt@gem_softpin@allocator-evict@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [28.05, 44.51] s

  * igt@gem_softpin@allocator-evict@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [28.31, 29.23] s

  * igt@gem_softpin@allocator-evict@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [27.81, 45.58] s

  

Known issues
------------

  Here are the changes found in IGTPW_6112_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_import_export@prime:
    - shard-kbl:          [PASS][1] -> [INCOMPLETE][2] ([i915#2895] / [i915#2944])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-kbl3/igt@drm_import_export@prime.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl3/igt@drm_import_export@prime.html

  * igt@gem_ctx_persistence@engines-queued:
    - shard-snb:          NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-snb5/igt@gem_ctx_persistence@engines-queued.html

  * igt@gem_eio@in-flight-contexts-10ms:
    - shard-tglb:         [PASS][4] -> [TIMEOUT][5] ([i915#3063])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-tglb5/igt@gem_eio@in-flight-contexts-10ms.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb1/igt@gem_eio@in-flight-contexts-10ms.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-apl:          NOTRUN -> [FAIL][6] ([i915#2846])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl8/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-kbl:          [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-kbl7/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_flush@basic-wb-rw-default:
    - shard-glk:          [PASS][14] -> [INCOMPLETE][15] ([i915#2055])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-glk3/igt@gem_exec_flush@basic-wb-rw-default.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk5/igt@gem_exec_flush@basic-wb-rw-default.html

  * igt@gem_exec_whisper@basic-contexts-forked:
    - shard-glk:          [PASS][16] -> [DMESG-WARN][17] ([i915#118] / [i915#95]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-glk6/igt@gem_exec_whisper@basic-contexts-forked.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk5/igt@gem_exec_whisper@basic-contexts-forked.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3323])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-iclb:         NOTRUN -> [SKIP][19] ([i915#3297])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb4/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
    - shard-tglb:         NOTRUN -> [SKIP][20] ([i915#3297])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb2/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-iclb:         NOTRUN -> [SKIP][21] ([i915#2856])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb3/igt@gen9_exec_parse@bb-start-far.html
    - shard-tglb:         NOTRUN -> [SKIP][22] ([i915#2856])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb3/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglb:         NOTRUN -> [WARN][23] ([i915#2681])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb2/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rpm@cursor-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][24] ([i915#579])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb5/igt@i915_pm_rpm@cursor-dpms.html
    - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#579])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb5/igt@i915_pm_rpm@cursor-dpms.html

  * igt@i915_pm_rpm@gem-execbuf-stress:
    - shard-glk:          NOTRUN -> [SKIP][26] ([fdo#109271]) +62 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk9/igt@i915_pm_rpm@gem-execbuf-stress.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglb:         NOTRUN -> [SKIP][27] ([fdo#109288])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb3/igt@i915_pm_sseu@full-enable.html
    - shard-iclb:         NOTRUN -> [SKIP][28] ([fdo#109288])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb3/igt@i915_pm_sseu@full-enable.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [PASS][29] -> [INCOMPLETE][30] ([i915#3921])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-snb7/igt@i915_selftest@live@hangcheck.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-snb7/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@perf@engine_cs:
    - shard-apl:          NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#2292])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl1/igt@i915_selftest@perf@engine_cs.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-apl:          NOTRUN -> [SKIP][34] ([fdo#109271]) +252 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-iclb:         NOTRUN -> [SKIP][35] ([fdo#110723])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
    - shard-tglb:         NOTRUN -> [SKIP][36] ([fdo#111615])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +9 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl6/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk6/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
    - shard-iclb:         NOTRUN -> [SKIP][39] ([fdo#109278] / [i915#3886]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb1/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([i915#3689] / [i915#3886])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb7/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886]) +4 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl4/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([i915#3689]) +7 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb2/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([fdo#109278]) +11 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb6/igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-tglb:         NOTRUN -> [SKIP][44] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb2/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-hpd:
    - shard-glk:          NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk7/igt@kms_chamelium@hdmi-hpd.html

  * igt@kms_chamelium@vga-hpd:
    - shard-apl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +19 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl6/igt@kms_chamelium@vga-hpd.html

  * igt@kms_color_chamelium@pipe-a-ctm-max:
    - shard-iclb:         NOTRUN -> [SKIP][47] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb3/igt@kms_color_chamelium@pipe-a-ctm-max.html

  * igt@kms_color_chamelium@pipe-b-degamma:
    - shard-kbl:          NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl1/igt@kms_color_chamelium@pipe-b-degamma.html

  * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
    - shard-snb:          NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +17 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-snb7/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          NOTRUN -> [TIMEOUT][50] ([i915#1319]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl7/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@srm:
    - shard-tglb:         NOTRUN -> [SKIP][51] ([fdo#111828])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb8/igt@kms_content_protection@srm.html
    - shard-iclb:         NOTRUN -> [SKIP][52] ([fdo#109300] / [fdo#111066])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb1/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen:
    - shard-iclb:         NOTRUN -> [SKIP][53] ([fdo#109278] / [fdo#109279])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb1/igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-max-size-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][54] ([i915#3359]) +3 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-max-size-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([fdo#109279] / [i915#3359]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-kbl:          NOTRUN -> [SKIP][56] ([fdo#109271]) +103 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl4/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([fdo#109274] / [fdo#109278]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-fences:
    - shard-iclb:         NOTRUN -> [SKIP][58] ([fdo#109274])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb7/igt@kms_flip@2x-flip-vs-fences.html

  * igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
    - shard-glk:          [PASS][59] -> [FAIL][60] ([i915#79]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [PASS][61] -> [DMESG-WARN][62] ([i915#180]) +5 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-iclb:         NOTRUN -> [SKIP][63] ([fdo#109280]) +11 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
    - shard-iclb:         [PASS][64] -> [FAIL][65] ([i915#2546])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-tglb:         NOTRUN -> [SKIP][66] ([fdo#111825]) +17 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#533])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl4/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265]) +3 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][69] ([i915#265])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-kbl:          NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
    - shard-glk:          NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk6/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2733])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl6/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
    - shard-apl:          NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +4 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
    - shard-tglb:         NOTRUN -> [SKIP][74] ([i915#2920]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb3/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
    - shard-iclb:         NOTRUN -> [SKIP][75] ([i915#658])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
    - shard-glk:          NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk9/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
    - shard-kbl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) +2 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][78] -> [SKIP][79] ([fdo#109642] / [fdo#111068] / [i915#658])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb7/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-tglb:         NOTRUN -> [FAIL][80] ([i915#132] / [i915#3467])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb8/igt@kms_psr@psr2_primary_mmap_gtt.html
    - shard-iclb:         NOTRUN -> [SKIP][81] ([fdo#109441])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb1/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [PASS][82] -> [SKIP][83] ([fdo#109441]) +1 similar issue
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-iclb2/igt@kms_psr@psr2_suspend.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb4/igt@kms_psr@psr2_suspend.html

  * igt@kms_setmode@basic:
    - shard-snb:          NOTRUN -> [FAIL][84] ([i915#31])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-snb6/igt@kms_setmode@basic.html

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
    - shard-snb:          NOTRUN -> [SKIP][85] ([fdo#109271]) +397 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-snb7/igt@kms_universal_plane@disable-primary-vs-flip-pipe-d.html

  * igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm:
    - shard-tglb:         NOTRUN -> [SKIP][86] ([i915#3841])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb3/igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-glk:          NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#533])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk9/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_vrr@flipline:
    - shard-tglb:         NOTRUN -> [SKIP][88] ([fdo#109502])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb2/igt@kms_vrr@flipline.html
    - shard-iclb:         NOTRUN -> [SKIP][89] ([fdo#109502])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb7/igt@kms_vrr@flipline.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-apl:          NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2437])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl3/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@nouveau_crc@pipe-c-source-rg:
    - shard-iclb:         NOTRUN -> [SKIP][91] ([i915#2530])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb6/igt@nouveau_crc@pipe-c-source-rg.html
    - shard-tglb:         NOTRUN -> [SKIP][92] ([i915#2530])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb8/igt@nouveau_crc@pipe-c-source-rg.html

  * igt@perf@polling-parameterized:
    - shard-iclb:         [PASS][93] -> [FAIL][94] ([i915#1542])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-iclb6/igt@perf@polling-parameterized.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb4/igt@perf@polling-parameterized.html

  * igt@perf_pmu@event-wait@rcs0:
    - shard-iclb:         NOTRUN -> [SKIP][95] ([fdo#112283])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb8/igt@perf_pmu@event-wait@rcs0.html
    - shard-tglb:         NOTRUN -> [SKIP][96] ([fdo#112283])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb3/igt@perf_pmu@event-wait@rcs0.html

  * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
    - shard-tglb:         NOTRUN -> [SKIP][97] ([fdo#109291]) +2 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb8/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
    - shard-iclb:         NOTRUN -> [SKIP][98] ([fdo#109291]) +1 similar issue
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb1/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html

  * igt@sysfs_clients@fair-7:
    - shard-apl:          NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2994]) +4 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl3/igt@sysfs_clients@fair-7.html

  * igt@sysfs_clients@sema-25:
    - shard-iclb:         NOTRUN -> [SKIP][100] ([i915#2994])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb7/igt@sysfs_clients@sema-25.html
    - shard-kbl:          NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#2994]) +1 similar issue
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl4/igt@sysfs_clients@sema-25.html
    - shard-tglb:         NOTRUN -> [SKIP][102] ([i915#2994])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb5/igt@sysfs_clients@sema-25.html
    - shard-glk:          NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#2994])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk6/igt@sysfs_clients@sema-25.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-kbl:          [FAIL][104] ([i915#2842]) -> [PASS][105] +1 similar issue
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-kbl2/igt@gem_exec_fair@basic-none-share@rcs0.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl3/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][106] ([i915#2842]) -> [PASS][107] +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][108] ([i915#2190]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-tglb6/igt@gem_huc_copy@huc-copy.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-tglb7/igt@gem_huc_copy@huc-copy.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][110] ([i915#454]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb5/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - shard-glk:          [DMESG-WARN][112] ([i915#118] / [i915#95]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-glk3/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk6/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a:
    - shard-iclb:         [SKIP][114] ([i915#3788]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-iclb2/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb3/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html

  * igt@kms_flip@2x-plain-flip-ts-check@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][116] ([i915#2122]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check@ac-hdmi-a1-hdmi-a2.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-glk7/igt@kms_flip@2x-plain-flip-ts-check@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend@b-dp1:
    - shard-apl:          [DMESG-WARN][118] ([i915#180]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-apl1/igt@kms_flip@flip-vs-suspend@b-dp1.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl6/igt@kms_flip@flip-vs-suspend@b-dp1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-kbl:          [DMESG-WARN][120] ([i915#180]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [SKIP][122] ([fdo#109441]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-iclb5/igt@kms_psr@psr2_basic.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb2/igt@kms_psr@psr2_basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [DMESG-WARN][124] ([i915#180] / [i915#295]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][126] ([i915#658]) -> [SKIP][127] ([i915#588])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-iclb4/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
    - shard-iclb:         [SKIP][128] ([i915#2920]) -> [SKIP][129] ([i915#658])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-iclb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363]) -> ([FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141]) ([i915#180] / [i915#1814] / [i915#2505] / [i915#2722] / [i915#3002] / [i915#3363])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-kbl6/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-kbl1/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-kbl6/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-kbl1/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6167/shard-kbl2/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl1/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl6/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl6/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl1/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl6/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl6/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/shard-kbl3/igt@runner@aborted.html
    - shard-apl:          ([FAIL][142], [FAIL][143], [FAIL][144], [FAIL][14

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6112/index.html

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