* [igt-dev] [PATCH i-g-t] tools/intel_vbt_decode: update vbt defs from kernel
@ 2019-06-05 12:33 Jani Nikula
2019-06-05 12:57 ` Ville Syrjälä
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Jani Nikula @ 2019-06-05 12:33 UTC (permalink / raw)
To: igt-dev; +Cc: jani.nikula
Sync up to commit f41c615310d2 ("drm/i915/bios: add an enum for BDB
block IDs") in kernel intel_vbt_defs.h, and update the tool with the
struct renames.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
tools/intel_vbt_decode.c | 6 +-
tools/intel_vbt_defs.h | 657 +++++++++++++++++----------------------
2 files changed, 280 insertions(+), 383 deletions(-)
diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
index d80b1dae7725..38eccc48f38b 100644
--- a/tools/intel_vbt_decode.c
+++ b/tools/intel_vbt_decode.c
@@ -228,7 +228,7 @@ static void dump_backlight_info(struct context *context,
const struct bdb_block *block)
{
const struct bdb_lfp_backlight_data *backlight = block->data;
- const struct bdb_lfp_backlight_data_entry *blc;
+ const struct lfp_backlight_data_entry *blc;
if (sizeof(*blc) != backlight->entry_size) {
printf("\tBacklight struct sizes don't match (expected %zu, got %u), skipping\n",
@@ -629,8 +629,8 @@ static void dump_lvds_data(struct context *context,
const uint8_t *lfp_data_ptr =
(const uint8_t *) lvds_data->data + lfp_data_size * i;
const uint8_t *timing_data = lfp_data_ptr + dvo_offset;
- const struct bdb_lvds_lfp_data_entry *lfp_data =
- (const struct bdb_lvds_lfp_data_entry *)lfp_data_ptr;
+ const struct lvds_lfp_data_entry *lfp_data =
+ (const struct lvds_lfp_data_entry *)lfp_data_ptr;
char marker;
if (i != context->panel_type && !context->dump_all_panel_types)
diff --git a/tools/intel_vbt_defs.h b/tools/intel_vbt_defs.h
index 3f5eff49105b..89ef14cafb6b 100644
--- a/tools/intel_vbt_defs.h
+++ b/tools/intel_vbt_defs.h
@@ -75,65 +75,51 @@ struct bdb_header {
u16 bdb_size;
} __packed;
-/* strictly speaking, this is a "skip" block, but it has interesting info */
-struct vbios_data {
- u8 type; /* 0 == desktop, 1 == mobile */
- u8 relstage;
- u8 chipset;
- u8 lvds_present:1;
- u8 tv_present:1;
- u8 rsvd2:6; /* finish byte */
- u8 rsvd3[4];
- u8 signon[155];
- u8 copyright[61];
- u16 code_segment;
- u8 dos_boot_mode;
- u8 bandwidth_percent;
- u8 rsvd4; /* popup memory size */
- u8 resize_pci_bios;
- u8 rsvd5; /* is crt already on ddc2 */
-} __packed;
-
/*
* There are several types of BIOS data blocks (BDBs), each block has
* an ID and size in the first 3 bytes (ID in first, size in next 2).
* Known types are listed below.
*/
-#define BDB_GENERAL_FEATURES 1
-#define BDB_GENERAL_DEFINITIONS 2
-#define BDB_OLD_TOGGLE_LIST 3
-#define BDB_MODE_SUPPORT_LIST 4
-#define BDB_GENERIC_MODE_TABLE 5
-#define BDB_EXT_MMIO_REGS 6
-#define BDB_SWF_IO 7
-#define BDB_SWF_MMIO 8
-#define BDB_PSR 9
-#define BDB_MODE_REMOVAL_TABLE 10
-#define BDB_CHILD_DEVICE_TABLE 11
-#define BDB_DRIVER_FEATURES 12
-#define BDB_DRIVER_PERSISTENCE 13
-#define BDB_EXT_TABLE_PTRS 14
-#define BDB_DOT_CLOCK_OVERRIDE 15
-#define BDB_DISPLAY_SELECT 16
-/* 17 rsvd */
-#define BDB_DRIVER_ROTATION 18
-#define BDB_DISPLAY_REMOVE 19
-#define BDB_OEM_CUSTOM 20
-#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
-#define BDB_SDVO_LVDS_OPTIONS 22
-#define BDB_SDVO_PANEL_DTDS 23
-#define BDB_SDVO_LVDS_PNP_IDS 24
-#define BDB_SDVO_LVDS_POWER_SEQ 25
-#define BDB_TV_OPTIONS 26
-#define BDB_EDP 27
-#define BDB_LVDS_OPTIONS 40
-#define BDB_LVDS_LFP_DATA_PTRS 41
-#define BDB_LVDS_LFP_DATA 42
-#define BDB_LVDS_BACKLIGHT 43
-#define BDB_LVDS_POWER 44
-#define BDB_MIPI_CONFIG 52
-#define BDB_MIPI_SEQUENCE 53
-#define BDB_SKIP 254 /* VBIOS private block, ignore */
+enum bdb_block_id {
+ BDB_GENERAL_FEATURES = 1,
+ BDB_GENERAL_DEFINITIONS = 2,
+ BDB_OLD_TOGGLE_LIST = 3,
+ BDB_MODE_SUPPORT_LIST = 4,
+ BDB_GENERIC_MODE_TABLE = 5,
+ BDB_EXT_MMIO_REGS = 6,
+ BDB_SWF_IO = 7,
+ BDB_SWF_MMIO = 8,
+ BDB_PSR = 9,
+ BDB_MODE_REMOVAL_TABLE = 10,
+ BDB_CHILD_DEVICE_TABLE = 11,
+ BDB_DRIVER_FEATURES = 12,
+ BDB_DRIVER_PERSISTENCE = 13,
+ BDB_EXT_TABLE_PTRS = 14,
+ BDB_DOT_CLOCK_OVERRIDE = 15,
+ BDB_DISPLAY_SELECT = 16,
+ BDB_DRIVER_ROTATION = 18,
+ BDB_DISPLAY_REMOVE = 19,
+ BDB_OEM_CUSTOM = 20,
+ BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */
+ BDB_SDVO_LVDS_OPTIONS = 22,
+ BDB_SDVO_PANEL_DTDS = 23,
+ BDB_SDVO_LVDS_PNP_IDS = 24,
+ BDB_SDVO_LVDS_POWER_SEQ = 25,
+ BDB_TV_OPTIONS = 26,
+ BDB_EDP = 27,
+ BDB_LVDS_OPTIONS = 40,
+ BDB_LVDS_LFP_DATA_PTRS = 41,
+ BDB_LVDS_LFP_DATA = 42,
+ BDB_LVDS_BACKLIGHT = 43,
+ BDB_LVDS_POWER = 44,
+ BDB_MIPI_CONFIG = 52,
+ BDB_MIPI_SEQUENCE = 53,
+ BDB_SKIP = 254, /* VBIOS private block, ignore */
+};
+
+/*
+ * Block 1 - General Bit Definitions
+ */
struct bdb_general_features {
/* bits 1 */
@@ -176,6 +162,10 @@ struct bdb_general_features {
u8 rsvd11:2; /* finish byte */
} __packed;
+/*
+ * Block 2 - General Bytes Definition
+ */
+
/* pre-915 */
#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
@@ -299,6 +289,8 @@ struct bdb_general_features {
#define DVO_PORT_DPA 10
#define DVO_PORT_DPE 11 /* 193 */
#define DVO_PORT_HDMIE 12 /* 193 */
+#define DVO_PORT_DPF 13 /* N/A */
+#define DVO_PORT_HDMIF 14 /* N/A */
#define DVO_PORT_MIPIA 21 /* 171 */
#define DVO_PORT_MIPIB 22 /* 171 */
#define DVO_PORT_MIPIC 23 /* 171 */
@@ -316,8 +308,26 @@ enum vbt_gmbus_ddi {
DDC_BUS_DDI_C,
DDC_BUS_DDI_D,
DDC_BUS_DDI_F,
+ ICL_DDC_BUS_DDI_A = 0x1,
+ ICL_DDC_BUS_DDI_B,
+ ICL_DDC_BUS_PORT_1 = 0x4,
+ ICL_DDC_BUS_PORT_2,
+ ICL_DDC_BUS_PORT_3,
+ ICL_DDC_BUS_PORT_4,
};
+#define DP_AUX_A 0x40
+#define DP_AUX_B 0x10
+#define DP_AUX_C 0x20
+#define DP_AUX_D 0x30
+#define DP_AUX_E 0x50
+#define DP_AUX_F 0x60
+
+#define VBT_DP_MAX_LINK_RATE_HBR3 0
+#define VBT_DP_MAX_LINK_RATE_HBR2 1
+#define VBT_DP_MAX_LINK_RATE_HBR 2
+#define VBT_DP_MAX_LINK_RATE_LBR 3
+
/*
* The child device config, aka the display device data structure, provides a
* description of a port and its configuration on the platform.
@@ -382,7 +392,8 @@ struct child_device_config {
u8 lspcon:1; /* 192 */
u8 iboost:1; /* 196 */
u8 hpd_invert:1; /* 196 */
- u8 flag_reserved:3;
+ u8 use_vbt_vswing:1; /* 218 */
+ u8 flag_reserved:2;
u8 hdmi_support:1; /* 158 */
u8 dp_support:1; /* 158 */
u8 tmds_support:1; /* 158 */
@@ -407,7 +418,9 @@ struct child_device_config {
u16 extended_type;
u8 dvo_function;
u8 dp_usb_type_c:1; /* 195 */
- u8 flags2_reserved:7; /* 195 */
+ u8 tbt:1; /* 209 */
+ u8 flags2_reserved:2; /* 195 */
+ u8 dp_port_trace_length:4; /* 209 */
u8 dp_gpio_index; /* 195 */
u16 dp_gpio_pin_num; /* 195 */
u8 dp_iboost_level:4; /* 196 */
@@ -441,194 +454,44 @@ struct bdb_general_definitions {
* number = (block_size - sizeof(bdb_general_definitions))/
* defs->child_dev_size;
*/
- uint8_t devices[0];
-} __packed;
-
-/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
-#define MODE_MASK 0x3
-
-struct bdb_lvds_options {
- u8 panel_type;
- u8 rsvd1;
- /* LVDS capabilities, stored in a dword */
- u8 pfit_mode:2;
- u8 pfit_text_mode_enhanced:1;
- u8 pfit_gfx_mode_enhanced:1;
- u8 pfit_ratio_auto:1;
- u8 pixel_dither:1;
- u8 lvds_edid:1;
- u8 rsvd2:1;
- u8 rsvd4;
- /* LVDS Panel channel bits stored here */
- u32 lvds_panel_channel_bits;
- /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
- u16 ssc_bits;
- u16 ssc_freq;
- u16 ssc_ddt;
- /* Panel color depth defined here */
- u16 panel_color_depth;
- /* LVDS panel type bits stored here */
- u32 dps_panel_type_bits;
- /* LVDS backlight control type bits stored here */
- u32 blt_control_type_bits;
-} __packed;
-
-/* LFP pointer table contains entries to the struct below */
-struct bdb_lvds_lfp_data_ptr {
- u16 fp_timing_offset; /* offsets are from start of bdb */
- u8 fp_table_size;
- u16 dvo_timing_offset;
- u8 dvo_table_size;
- u16 panel_pnp_id_offset;
- u8 pnp_table_size;
-} __packed;
-
-struct bdb_lvds_lfp_data_ptrs {
- u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
- struct bdb_lvds_lfp_data_ptr ptr[16];
-} __packed;
-
-/* LFP data has 3 blocks per entry */
-struct lvds_fp_timing {
- u16 x_res;
- u16 y_res;
- u32 lvds_reg;
- u32 lvds_reg_val;
- u32 pp_on_reg;
- u32 pp_on_reg_val;
- u32 pp_off_reg;
- u32 pp_off_reg_val;
- u32 pp_cycle_reg;
- u32 pp_cycle_reg_val;
- u32 pfit_reg;
- u32 pfit_reg_val;
- u16 terminator;
+ u8 devices[0];
} __packed;
-struct lvds_dvo_timing {
- u16 clock; /**< In 10khz */
- u8 hactive_lo;
- u8 hblank_lo;
- u8 hblank_hi:4;
- u8 hactive_hi:4;
- u8 vactive_lo;
- u8 vblank_lo;
- u8 vblank_hi:4;
- u8 vactive_hi:4;
- u8 hsync_off_lo;
- u8 hsync_pulse_width_lo;
- u8 vsync_pulse_width_lo:4;
- u8 vsync_off_lo:4;
- u8 vsync_pulse_width_hi:2;
- u8 vsync_off_hi:2;
- u8 hsync_pulse_width_hi:2;
- u8 hsync_off_hi:2;
- u8 himage_lo;
- u8 vimage_lo;
- u8 vimage_hi:4;
- u8 himage_hi:4;
- u8 h_border;
- u8 v_border;
- u8 rsvd1:3;
- u8 digital:2;
- u8 vsync_positive:1;
- u8 hsync_positive:1;
- u8 non_interlaced:1;
-} __packed;
-
-struct lvds_pnp_id {
- u16 mfg_name;
- u16 product_code;
- u32 serial;
- u8 mfg_week;
- u8 mfg_year;
-} __packed;
-
-struct bdb_lvds_lfp_data_entry {
- struct lvds_fp_timing fp_timing;
- struct lvds_dvo_timing dvo_timing;
- struct lvds_pnp_id pnp_id;
-} __packed;
-
-struct bdb_lvds_lfp_data {
- struct bdb_lvds_lfp_data_entry data[16];
-} __packed;
-
-#define BDB_BACKLIGHT_TYPE_NONE 0
-#define BDB_BACKLIGHT_TYPE_PWM 2
-
-struct bdb_lfp_backlight_data_entry {
- u8 type:2;
- u8 active_low_pwm:1;
- u8 obsolete1:5;
- u16 pwm_freq_hz;
- u8 min_brightness;
- u8 obsolete2;
- u8 obsolete3;
-} __packed;
-
-struct bdb_lfp_backlight_control_method {
- u8 type:4;
- u8 controller:4;
-} __packed;
-
-struct bdb_lfp_backlight_data {
- u8 entry_size;
- struct bdb_lfp_backlight_data_entry data[16];
- u8 level[16];
- struct bdb_lfp_backlight_control_method backlight_control[16];
-} __packed;
+/*
+ * Block 9 - SRD Feature Block
+ */
-struct aimdb_header {
- char signature[16];
- char oem_device[20];
- u16 aimdb_version;
- u16 aimdb_header_size;
- u16 aimdb_size;
-} __packed;
+struct psr_table {
+ /* Feature bits */
+ u8 full_link:1;
+ u8 require_aux_to_wakeup:1;
+ u8 feature_bits_rsvd:6;
-struct aimdb_block {
- u8 aimdb_id;
- u16 aimdb_size;
-} __packed;
+ /* Wait times */
+ u8 idle_frames:4;
+ u8 lines_to_wait:3;
+ u8 wait_times_rsvd:1;
-struct vch_panel_data {
- u16 fp_timing_offset;
- u8 fp_timing_size;
- u16 dvo_timing_offset;
- u8 dvo_timing_size;
- u16 text_fitting_offset;
- u8 text_fitting_size;
- u16 graphics_fitting_offset;
- u8 graphics_fitting_size;
-} __packed;
+ /* TP wake up time in multiple of 100 */
+ u16 tp1_wakeup_time;
+ u16 tp2_tp3_wakeup_time;
-struct vch_bdb_22 {
- struct aimdb_block aimdb_block;
- struct vch_panel_data panels[16];
+ /* PSR2 TP2/TP3 wakeup time for 16 panels */
+ u32 psr2_tp2_tp3_wakeup_time;
} __packed;
-struct bdb_sdvo_lvds_options {
- u8 panel_backlight;
- u8 h40_set_panel_type;
- u8 panel_type;
- u8 ssc_clk_freq;
- u16 als_low_trip;
- u16 als_high_trip;
- u8 sclalarcoeff_tab_row_num;
- u8 sclalarcoeff_tab_row_size;
- u8 coefficient[8];
- u8 panel_misc_bits_1;
- u8 panel_misc_bits_2;
- u8 panel_misc_bits_3;
- u8 panel_misc_bits_4;
+struct bdb_psr {
+ struct psr_table psr_table[16];
} __packed;
+/*
+ * Block 12 - Driver Features Data Block
+ */
#define BDB_DRIVER_FEATURE_NO_LVDS 0
#define BDB_DRIVER_FEATURE_INT_LVDS 1
#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
-#define BDB_DRIVER_FEATURE_EDP 3
+#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3
struct bdb_driver_features {
u8 boot_dev_algorithm:1;
@@ -684,6 +547,69 @@ struct bdb_driver_features {
u16 pc_feature_valid:1;
} __packed;
+/*
+ * Block 22 - SDVO LVDS General Options
+ */
+
+struct bdb_sdvo_lvds_options {
+ u8 panel_backlight;
+ u8 h40_set_panel_type;
+ u8 panel_type;
+ u8 ssc_clk_freq;
+ u16 als_low_trip;
+ u16 als_high_trip;
+ u8 sclalarcoeff_tab_row_num;
+ u8 sclalarcoeff_tab_row_size;
+ u8 coefficient[8];
+ u8 panel_misc_bits_1;
+ u8 panel_misc_bits_2;
+ u8 panel_misc_bits_3;
+ u8 panel_misc_bits_4;
+} __packed;
+
+/*
+ * Block 23 - SDVO LVDS Panel DTDs
+ */
+
+struct lvds_dvo_timing {
+ u16 clock; /**< In 10khz */
+ u8 hactive_lo;
+ u8 hblank_lo;
+ u8 hblank_hi:4;
+ u8 hactive_hi:4;
+ u8 vactive_lo;
+ u8 vblank_lo;
+ u8 vblank_hi:4;
+ u8 vactive_hi:4;
+ u8 hsync_off_lo;
+ u8 hsync_pulse_width_lo;
+ u8 vsync_pulse_width_lo:4;
+ u8 vsync_off_lo:4;
+ u8 vsync_pulse_width_hi:2;
+ u8 vsync_off_hi:2;
+ u8 hsync_pulse_width_hi:2;
+ u8 hsync_off_hi:2;
+ u8 himage_lo;
+ u8 vimage_lo;
+ u8 vimage_hi:4;
+ u8 himage_hi:4;
+ u8 h_border;
+ u8 v_border;
+ u8 rsvd1:3;
+ u8 digital:2;
+ u8 vsync_positive:1;
+ u8 hsync_positive:1;
+ u8 non_interlaced:1;
+} __packed;
+
+struct bdb_sdvo_panel_dtds {
+ struct lvds_dvo_timing dtds[4];
+} __packed;
+
+/*
+ * Block 27 - eDP VBT Block
+ */
+
#define EDP_18BPP 0
#define EDP_24BPP 1
#define EDP_30BPP 2
@@ -736,151 +662,133 @@ struct bdb_edp {
struct edp_full_link_params full_link_params[16]; /* 199 */
} __packed;
-struct psr_table {
- /* Feature bits */
- u8 full_link:1;
- u8 require_aux_to_wakeup:1;
- u8 feature_bits_rsvd:6;
+/*
+ * Block 40 - LFP Data Block
+ */
- /* Wait times */
- u8 idle_frames:4;
- u8 lines_to_wait:3;
- u8 wait_times_rsvd:1;
+/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
+#define MODE_MASK 0x3
- /* TP wake up time in multiple of 100 */
- u16 tp1_wakeup_time;
- u16 tp2_tp3_wakeup_time;
+struct bdb_lvds_options {
+ u8 panel_type;
+ u8 panel_type2; /* 212 */
+ /* LVDS capabilities, stored in a dword */
+ u8 pfit_mode:2;
+ u8 pfit_text_mode_enhanced:1;
+ u8 pfit_gfx_mode_enhanced:1;
+ u8 pfit_ratio_auto:1;
+ u8 pixel_dither:1;
+ u8 lvds_edid:1;
+ u8 rsvd2:1;
+ u8 rsvd4;
+ /* LVDS Panel channel bits stored here */
+ u32 lvds_panel_channel_bits;
+ /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
+ u16 ssc_bits;
+ u16 ssc_freq;
+ u16 ssc_ddt;
+ /* Panel color depth defined here */
+ u16 panel_color_depth;
+ /* LVDS panel type bits stored here */
+ u32 dps_panel_type_bits;
+ /* LVDS backlight control type bits stored here */
+ u32 blt_control_type_bits;
+
+ u16 lcdvcc_s0_enable; /* 200 */
+ u32 rotation; /* 228 */
} __packed;
-struct bdb_psr {
- struct psr_table psr_table[16];
+/*
+ * Block 41 - LFP Data Table Pointers
+ */
+
+/* LFP pointer table contains entries to the struct below */
+struct lvds_lfp_data_ptr {
+ u16 fp_timing_offset; /* offsets are from start of bdb */
+ u8 fp_table_size;
+ u16 dvo_timing_offset;
+ u8 dvo_table_size;
+ u16 panel_pnp_id_offset;
+ u8 pnp_table_size;
+} __packed;
+
+struct bdb_lvds_lfp_data_ptrs {
+ u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
+ struct lvds_lfp_data_ptr ptr[16];
} __packed;
/*
- * Driver<->VBIOS interaction occurs through scratch bits in
- * GR18 & SWF*.
+ * Block 42 - LFP Data Tables
*/
-/* GR18 bits are set on display switch and hotkey events */
-#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
-#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
-#define GR18_HK_NONE (0x0<<3)
-#define GR18_HK_LFP_STRETCH (0x1<<3)
-#define GR18_HK_TOGGLE_DISP (0x2<<3)
-#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
-#define GR18_HK_POPUP_DISABLED (0x6<<3)
-#define GR18_HK_POPUP_ENABLED (0x7<<3)
-#define GR18_HK_PFIT (0x8<<3)
-#define GR18_HK_APM_CHANGE (0xa<<3)
-#define GR18_HK_MULTIPLE (0xc<<3)
-#define GR18_USER_INT_EN (1<<2)
-#define GR18_A0000_FLUSH_EN (1<<1)
-#define GR18_SMM_EN (1<<0)
-
-/* Set by driver, cleared by VBIOS */
-#define SWF00_YRES_SHIFT 16
-#define SWF00_XRES_SHIFT 0
-#define SWF00_RES_MASK 0xffff
-
-/* Set by VBIOS at boot time and driver at runtime */
-#define SWF01_TV2_FORMAT_SHIFT 8
-#define SWF01_TV1_FORMAT_SHIFT 0
-#define SWF01_TV_FORMAT_MASK 0xffff
-
-#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
-#define SWF10_GTT_OVERRIDE_EN (1<<28)
-#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
-#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
-#define SWF10_OLD_TOGGLE 0x0
-#define SWF10_TOGGLE_LIST_1 0x1
-#define SWF10_TOGGLE_LIST_2 0x2
-#define SWF10_TOGGLE_LIST_3 0x3
-#define SWF10_TOGGLE_LIST_4 0x4
-#define SWF10_PANNING_EN (1<<23)
-#define SWF10_DRIVER_LOADED (1<<22)
-#define SWF10_EXTENDED_DESKTOP (1<<21)
-#define SWF10_EXCLUSIVE_MODE (1<<20)
-#define SWF10_OVERLAY_EN (1<<19)
-#define SWF10_PLANEB_HOLDOFF (1<<18)
-#define SWF10_PLANEA_HOLDOFF (1<<17)
-#define SWF10_VGA_HOLDOFF (1<<16)
-#define SWF10_ACTIVE_DISP_MASK 0xffff
-#define SWF10_PIPEB_LFP2 (1<<15)
-#define SWF10_PIPEB_EFP2 (1<<14)
-#define SWF10_PIPEB_TV2 (1<<13)
-#define SWF10_PIPEB_CRT2 (1<<12)
-#define SWF10_PIPEB_LFP (1<<11)
-#define SWF10_PIPEB_EFP (1<<10)
-#define SWF10_PIPEB_TV (1<<9)
-#define SWF10_PIPEB_CRT (1<<8)
-#define SWF10_PIPEA_LFP2 (1<<7)
-#define SWF10_PIPEA_EFP2 (1<<6)
-#define SWF10_PIPEA_TV2 (1<<5)
-#define SWF10_PIPEA_CRT2 (1<<4)
-#define SWF10_PIPEA_LFP (1<<3)
-#define SWF10_PIPEA_EFP (1<<2)
-#define SWF10_PIPEA_TV (1<<1)
-#define SWF10_PIPEA_CRT (1<<0)
-
-#define SWF11_MEMORY_SIZE_SHIFT 16
-#define SWF11_SV_TEST_EN (1<<15)
-#define SWF11_IS_AGP (1<<14)
-#define SWF11_DISPLAY_HOLDOFF (1<<13)
-#define SWF11_DPMS_REDUCED (1<<12)
-#define SWF11_IS_VBE_MODE (1<<11)
-#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
-#define SWF11_DPMS_MASK 0x07
-#define SWF11_DPMS_OFF (1<<2)
-#define SWF11_DPMS_SUSPEND (1<<1)
-#define SWF11_DPMS_STANDBY (1<<0)
-#define SWF11_DPMS_ON 0
-
-#define SWF14_GFX_PFIT_EN (1<<31)
-#define SWF14_TEXT_PFIT_EN (1<<30)
-#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
-#define SWF14_POPUP_EN (1<<28)
-#define SWF14_DISPLAY_HOLDOFF (1<<27)
-#define SWF14_DISP_DETECT_EN (1<<26)
-#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
-#define SWF14_DRIVER_STATUS (1<<24)
-#define SWF14_OS_TYPE_WIN9X (1<<23)
-#define SWF14_OS_TYPE_WINNT (1<<22)
-/* 21:19 rsvd */
-#define SWF14_PM_TYPE_MASK 0x00070000
-#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
-#define SWF14_PM_ACPI (0x3 << 16)
-#define SWF14_PM_APM_12 (0x2 << 16)
-#define SWF14_PM_APM_11 (0x1 << 16)
-#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
- /* if GR18 indicates a display switch */
-#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
-#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
-#define SWF14_DS_PIPEB_TV2_EN (1<<13)
-#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
-#define SWF14_DS_PIPEB_LFP_EN (1<<11)
-#define SWF14_DS_PIPEB_EFP_EN (1<<10)
-#define SWF14_DS_PIPEB_TV_EN (1<<9)
-#define SWF14_DS_PIPEB_CRT_EN (1<<8)
-#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
-#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
-#define SWF14_DS_PIPEA_TV2_EN (1<<5)
-#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
-#define SWF14_DS_PIPEA_LFP_EN (1<<3)
-#define SWF14_DS_PIPEA_EFP_EN (1<<2)
-#define SWF14_DS_PIPEA_TV_EN (1<<1)
-#define SWF14_DS_PIPEA_CRT_EN (1<<0)
- /* if GR18 indicates a panel fitting request */
-#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
- /* if GR18 indicates an APM change request */
-#define SWF14_APM_HIBERNATE 0x4
-#define SWF14_APM_SUSPEND 0x3
-#define SWF14_APM_STANDBY 0x1
-#define SWF14_APM_RESTORE 0x0
-
-/* Block 52 contains MIPI configuration block
- * 6 * bdb_mipi_config, followed by 6 pps data block
- * block below
+/* LFP data has 3 blocks per entry */
+struct lvds_fp_timing {
+ u16 x_res;
+ u16 y_res;
+ u32 lvds_reg;
+ u32 lvds_reg_val;
+ u32 pp_on_reg;
+ u32 pp_on_reg_val;
+ u32 pp_off_reg;
+ u32 pp_off_reg_val;
+ u32 pp_cycle_reg;
+ u32 pp_cycle_reg_val;
+ u32 pfit_reg;
+ u32 pfit_reg_val;
+ u16 terminator;
+} __packed;
+
+struct lvds_pnp_id {
+ u16 mfg_name;
+ u16 product_code;
+ u32 serial;
+ u8 mfg_week;
+ u8 mfg_year;
+} __packed;
+
+struct lvds_lfp_data_entry {
+ struct lvds_fp_timing fp_timing;
+ struct lvds_dvo_timing dvo_timing;
+ struct lvds_pnp_id pnp_id;
+} __packed;
+
+struct bdb_lvds_lfp_data {
+ struct lvds_lfp_data_entry data[16];
+} __packed;
+
+/*
+ * Block 43 - LFP Backlight Control Data Block
*/
+
+#define BDB_BACKLIGHT_TYPE_NONE 0
+#define BDB_BACKLIGHT_TYPE_PWM 2
+
+struct lfp_backlight_data_entry {
+ u8 type:2;
+ u8 active_low_pwm:1;
+ u8 obsolete1:5;
+ u16 pwm_freq_hz;
+ u8 min_brightness;
+ u8 obsolete2;
+ u8 obsolete3;
+} __packed;
+
+struct lfp_backlight_control_method {
+ u8 type:4;
+ u8 controller:4;
+} __packed;
+
+struct bdb_lfp_backlight_data {
+ u8 entry_size;
+ struct lfp_backlight_data_entry data[16];
+ u8 level[16];
+ struct lfp_backlight_control_method backlight_control[16];
+} __packed;
+
+/*
+ * Block 52 - MIPI Configuration Block
+ */
+
#define MAX_MIPI_CONFIGURATIONS 6
struct bdb_mipi_config {
@@ -888,24 +796,13 @@ struct bdb_mipi_config {
struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
} __packed;
-/* Block 53 contains MIPI sequences as needed by the panel
- * for enabling it. This block can be variable in size and
- * can be maximum of 6 blocks
+/*
+ * Block 53 - MIPI Sequence Block
*/
+
struct bdb_mipi_sequence {
u8 version;
- u8 data[0];
+ u8 data[0]; /* up to 6 variable length blocks */
} __packed;
-enum mipi_gpio_pin_index {
- MIPI_GPIO_UNDEFINED = 0,
- MIPI_GPIO_PANEL_ENABLE,
- MIPI_GPIO_BL_ENABLE,
- MIPI_GPIO_PWM_ENABLE,
- MIPI_GPIO_RESET_N,
- MIPI_GPIO_PWR_DOWN_R,
- MIPI_GPIO_STDBY_RST_N,
- MIPI_GPIO_MAX
-};
-
#endif /* _INTEL_VBT_DEFS_H_ */
--
2.20.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] tools/intel_vbt_decode: update vbt defs from kernel
2019-06-05 12:33 [igt-dev] [PATCH i-g-t] tools/intel_vbt_decode: update vbt defs from kernel Jani Nikula
@ 2019-06-05 12:57 ` Ville Syrjälä
2019-06-05 13:22 ` Jani Nikula
2019-06-05 13:49 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2019-06-06 20:28 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2019-06-05 12:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: igt-dev
On Wed, Jun 05, 2019 at 03:33:00PM +0300, Jani Nikula wrote:
> Sync up to commit f41c615310d2 ("drm/i915/bios: add an enum for BDB
> block IDs") in kernel intel_vbt_defs.h, and update the tool with the
> struct renames.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> tools/intel_vbt_decode.c | 6 +-
> tools/intel_vbt_defs.h | 657 +++++++++++++++++----------------------
> 2 files changed, 280 insertions(+), 383 deletions(-)
>
> diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
> index d80b1dae7725..38eccc48f38b 100644
> --- a/tools/intel_vbt_decode.c
> +++ b/tools/intel_vbt_decode.c
> @@ -228,7 +228,7 @@ static void dump_backlight_info(struct context *context,
> const struct bdb_block *block)
> {
> const struct bdb_lfp_backlight_data *backlight = block->data;
> - const struct bdb_lfp_backlight_data_entry *blc;
> + const struct lfp_backlight_data_entry *blc;
>
> if (sizeof(*blc) != backlight->entry_size) {
> printf("\tBacklight struct sizes don't match (expected %zu, got %u), skipping\n",
> @@ -629,8 +629,8 @@ static void dump_lvds_data(struct context *context,
> const uint8_t *lfp_data_ptr =
> (const uint8_t *) lvds_data->data + lfp_data_size * i;
> const uint8_t *timing_data = lfp_data_ptr + dvo_offset;
> - const struct bdb_lvds_lfp_data_entry *lfp_data =
> - (const struct bdb_lvds_lfp_data_entry *)lfp_data_ptr;
> + const struct lvds_lfp_data_entry *lfp_data =
> + (const struct lvds_lfp_data_entry *)lfp_data_ptr;
> char marker;
>
> if (i != context->panel_type && !context->dump_all_panel_types)
> diff --git a/tools/intel_vbt_defs.h b/tools/intel_vbt_defs.h
> index 3f5eff49105b..89ef14cafb6b 100644
> --- a/tools/intel_vbt_defs.h
> +++ b/tools/intel_vbt_defs.h
> @@ -75,65 +75,51 @@ struct bdb_header {
> u16 bdb_size;
> } __packed;
>
> -/* strictly speaking, this is a "skip" block, but it has interesting info */
> -struct vbios_data {
> - u8 type; /* 0 == desktop, 1 == mobile */
> - u8 relstage;
> - u8 chipset;
> - u8 lvds_present:1;
> - u8 tv_present:1;
> - u8 rsvd2:6; /* finish byte */
> - u8 rsvd3[4];
> - u8 signon[155];
> - u8 copyright[61];
> - u16 code_segment;
> - u8 dos_boot_mode;
> - u8 bandwidth_percent;
> - u8 rsvd4; /* popup memory size */
> - u8 resize_pci_bios;
> - u8 rsvd5; /* is crt already on ddc2 */
> -} __packed;
> -
> /*
> * There are several types of BIOS data blocks (BDBs), each block has
> * an ID and size in the first 3 bytes (ID in first, size in next 2).
> * Known types are listed below.
> */
> -#define BDB_GENERAL_FEATURES 1
> -#define BDB_GENERAL_DEFINITIONS 2
> -#define BDB_OLD_TOGGLE_LIST 3
> -#define BDB_MODE_SUPPORT_LIST 4
> -#define BDB_GENERIC_MODE_TABLE 5
> -#define BDB_EXT_MMIO_REGS 6
> -#define BDB_SWF_IO 7
> -#define BDB_SWF_MMIO 8
> -#define BDB_PSR 9
> -#define BDB_MODE_REMOVAL_TABLE 10
> -#define BDB_CHILD_DEVICE_TABLE 11
> -#define BDB_DRIVER_FEATURES 12
> -#define BDB_DRIVER_PERSISTENCE 13
> -#define BDB_EXT_TABLE_PTRS 14
> -#define BDB_DOT_CLOCK_OVERRIDE 15
> -#define BDB_DISPLAY_SELECT 16
> -/* 17 rsvd */
> -#define BDB_DRIVER_ROTATION 18
> -#define BDB_DISPLAY_REMOVE 19
> -#define BDB_OEM_CUSTOM 20
> -#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
> -#define BDB_SDVO_LVDS_OPTIONS 22
> -#define BDB_SDVO_PANEL_DTDS 23
> -#define BDB_SDVO_LVDS_PNP_IDS 24
> -#define BDB_SDVO_LVDS_POWER_SEQ 25
> -#define BDB_TV_OPTIONS 26
> -#define BDB_EDP 27
> -#define BDB_LVDS_OPTIONS 40
> -#define BDB_LVDS_LFP_DATA_PTRS 41
> -#define BDB_LVDS_LFP_DATA 42
> -#define BDB_LVDS_BACKLIGHT 43
> -#define BDB_LVDS_POWER 44
> -#define BDB_MIPI_CONFIG 52
> -#define BDB_MIPI_SEQUENCE 53
> -#define BDB_SKIP 254 /* VBIOS private block, ignore */
> +enum bdb_block_id {
> + BDB_GENERAL_FEATURES = 1,
> + BDB_GENERAL_DEFINITIONS = 2,
> + BDB_OLD_TOGGLE_LIST = 3,
> + BDB_MODE_SUPPORT_LIST = 4,
> + BDB_GENERIC_MODE_TABLE = 5,
> + BDB_EXT_MMIO_REGS = 6,
> + BDB_SWF_IO = 7,
> + BDB_SWF_MMIO = 8,
> + BDB_PSR = 9,
> + BDB_MODE_REMOVAL_TABLE = 10,
> + BDB_CHILD_DEVICE_TABLE = 11,
> + BDB_DRIVER_FEATURES = 12,
> + BDB_DRIVER_PERSISTENCE = 13,
> + BDB_EXT_TABLE_PTRS = 14,
> + BDB_DOT_CLOCK_OVERRIDE = 15,
> + BDB_DISPLAY_SELECT = 16,
> + BDB_DRIVER_ROTATION = 18,
> + BDB_DISPLAY_REMOVE = 19,
> + BDB_OEM_CUSTOM = 20,
> + BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */
> + BDB_SDVO_LVDS_OPTIONS = 22,
> + BDB_SDVO_PANEL_DTDS = 23,
> + BDB_SDVO_LVDS_PNP_IDS = 24,
> + BDB_SDVO_LVDS_POWER_SEQ = 25,
> + BDB_TV_OPTIONS = 26,
> + BDB_EDP = 27,
> + BDB_LVDS_OPTIONS = 40,
> + BDB_LVDS_LFP_DATA_PTRS = 41,
> + BDB_LVDS_LFP_DATA = 42,
> + BDB_LVDS_BACKLIGHT = 43,
> + BDB_LVDS_POWER = 44,
> + BDB_MIPI_CONFIG = 52,
> + BDB_MIPI_SEQUENCE = 53,
> + BDB_SKIP = 254, /* VBIOS private block, ignore */
> +};
> +
> +/*
> + * Block 1 - General Bit Definitions
> + */
>
> struct bdb_general_features {
> /* bits 1 */
> @@ -176,6 +162,10 @@ struct bdb_general_features {
> u8 rsvd11:2; /* finish byte */
> } __packed;
>
> +/*
> + * Block 2 - General Bytes Definition
> + */
> +
> /* pre-915 */
> #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
> #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
> @@ -299,6 +289,8 @@ struct bdb_general_features {
> #define DVO_PORT_DPA 10
> #define DVO_PORT_DPE 11 /* 193 */
> #define DVO_PORT_HDMIE 12 /* 193 */
> +#define DVO_PORT_DPF 13 /* N/A */
> +#define DVO_PORT_HDMIF 14 /* N/A */
> #define DVO_PORT_MIPIA 21 /* 171 */
> #define DVO_PORT_MIPIB 22 /* 171 */
> #define DVO_PORT_MIPIC 23 /* 171 */
> @@ -316,8 +308,26 @@ enum vbt_gmbus_ddi {
> DDC_BUS_DDI_C,
> DDC_BUS_DDI_D,
> DDC_BUS_DDI_F,
> + ICL_DDC_BUS_DDI_A = 0x1,
> + ICL_DDC_BUS_DDI_B,
> + ICL_DDC_BUS_PORT_1 = 0x4,
> + ICL_DDC_BUS_PORT_2,
> + ICL_DDC_BUS_PORT_3,
> + ICL_DDC_BUS_PORT_4,
> };
>
> +#define DP_AUX_A 0x40
> +#define DP_AUX_B 0x10
> +#define DP_AUX_C 0x20
> +#define DP_AUX_D 0x30
> +#define DP_AUX_E 0x50
> +#define DP_AUX_F 0x60
> +
> +#define VBT_DP_MAX_LINK_RATE_HBR3 0
> +#define VBT_DP_MAX_LINK_RATE_HBR2 1
> +#define VBT_DP_MAX_LINK_RATE_HBR 2
> +#define VBT_DP_MAX_LINK_RATE_LBR 3
> +
> /*
> * The child device config, aka the display device data structure, provides a
> * description of a port and its configuration on the platform.
> @@ -382,7 +392,8 @@ struct child_device_config {
> u8 lspcon:1; /* 192 */
> u8 iboost:1; /* 196 */
> u8 hpd_invert:1; /* 196 */
> - u8 flag_reserved:3;
> + u8 use_vbt_vswing:1; /* 218 */
> + u8 flag_reserved:2;
> u8 hdmi_support:1; /* 158 */
> u8 dp_support:1; /* 158 */
> u8 tmds_support:1; /* 158 */
> @@ -407,7 +418,9 @@ struct child_device_config {
> u16 extended_type;
> u8 dvo_function;
> u8 dp_usb_type_c:1; /* 195 */
> - u8 flags2_reserved:7; /* 195 */
> + u8 tbt:1; /* 209 */
> + u8 flags2_reserved:2; /* 195 */
> + u8 dp_port_trace_length:4; /* 209 */
> u8 dp_gpio_index; /* 195 */
> u16 dp_gpio_pin_num; /* 195 */
> u8 dp_iboost_level:4; /* 196 */
> @@ -441,194 +454,44 @@ struct bdb_general_definitions {
> * number = (block_size - sizeof(bdb_general_definitions))/
> * defs->child_dev_size;
> */
> - uint8_t devices[0];
> -} __packed;
> -
> -/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
> -#define MODE_MASK 0x3
> -
> -struct bdb_lvds_options {
> - u8 panel_type;
> - u8 rsvd1;
> - /* LVDS capabilities, stored in a dword */
> - u8 pfit_mode:2;
> - u8 pfit_text_mode_enhanced:1;
> - u8 pfit_gfx_mode_enhanced:1;
> - u8 pfit_ratio_auto:1;
> - u8 pixel_dither:1;
> - u8 lvds_edid:1;
> - u8 rsvd2:1;
> - u8 rsvd4;
> - /* LVDS Panel channel bits stored here */
> - u32 lvds_panel_channel_bits;
> - /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
> - u16 ssc_bits;
> - u16 ssc_freq;
> - u16 ssc_ddt;
> - /* Panel color depth defined here */
> - u16 panel_color_depth;
> - /* LVDS panel type bits stored here */
> - u32 dps_panel_type_bits;
> - /* LVDS backlight control type bits stored here */
> - u32 blt_control_type_bits;
> -} __packed;
> -
> -/* LFP pointer table contains entries to the struct below */
> -struct bdb_lvds_lfp_data_ptr {
> - u16 fp_timing_offset; /* offsets are from start of bdb */
> - u8 fp_table_size;
> - u16 dvo_timing_offset;
> - u8 dvo_table_size;
> - u16 panel_pnp_id_offset;
> - u8 pnp_table_size;
> -} __packed;
> -
> -struct bdb_lvds_lfp_data_ptrs {
> - u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
> - struct bdb_lvds_lfp_data_ptr ptr[16];
> -} __packed;
> -
> -/* LFP data has 3 blocks per entry */
> -struct lvds_fp_timing {
> - u16 x_res;
> - u16 y_res;
> - u32 lvds_reg;
> - u32 lvds_reg_val;
> - u32 pp_on_reg;
> - u32 pp_on_reg_val;
> - u32 pp_off_reg;
> - u32 pp_off_reg_val;
> - u32 pp_cycle_reg;
> - u32 pp_cycle_reg_val;
> - u32 pfit_reg;
> - u32 pfit_reg_val;
> - u16 terminator;
> + u8 devices[0];
> } __packed;
>
> -struct lvds_dvo_timing {
> - u16 clock; /**< In 10khz */
> - u8 hactive_lo;
> - u8 hblank_lo;
> - u8 hblank_hi:4;
> - u8 hactive_hi:4;
> - u8 vactive_lo;
> - u8 vblank_lo;
> - u8 vblank_hi:4;
> - u8 vactive_hi:4;
> - u8 hsync_off_lo;
> - u8 hsync_pulse_width_lo;
> - u8 vsync_pulse_width_lo:4;
> - u8 vsync_off_lo:4;
> - u8 vsync_pulse_width_hi:2;
> - u8 vsync_off_hi:2;
> - u8 hsync_pulse_width_hi:2;
> - u8 hsync_off_hi:2;
> - u8 himage_lo;
> - u8 vimage_lo;
> - u8 vimage_hi:4;
> - u8 himage_hi:4;
> - u8 h_border;
> - u8 v_border;
> - u8 rsvd1:3;
> - u8 digital:2;
> - u8 vsync_positive:1;
> - u8 hsync_positive:1;
> - u8 non_interlaced:1;
> -} __packed;
> -
> -struct lvds_pnp_id {
> - u16 mfg_name;
> - u16 product_code;
> - u32 serial;
> - u8 mfg_week;
> - u8 mfg_year;
> -} __packed;
> -
> -struct bdb_lvds_lfp_data_entry {
> - struct lvds_fp_timing fp_timing;
> - struct lvds_dvo_timing dvo_timing;
> - struct lvds_pnp_id pnp_id;
> -} __packed;
> -
> -struct bdb_lvds_lfp_data {
> - struct bdb_lvds_lfp_data_entry data[16];
> -} __packed;
> -
> -#define BDB_BACKLIGHT_TYPE_NONE 0
> -#define BDB_BACKLIGHT_TYPE_PWM 2
> -
> -struct bdb_lfp_backlight_data_entry {
> - u8 type:2;
> - u8 active_low_pwm:1;
> - u8 obsolete1:5;
> - u16 pwm_freq_hz;
> - u8 min_brightness;
> - u8 obsolete2;
> - u8 obsolete3;
> -} __packed;
> -
> -struct bdb_lfp_backlight_control_method {
> - u8 type:4;
> - u8 controller:4;
> -} __packed;
> -
> -struct bdb_lfp_backlight_data {
> - u8 entry_size;
> - struct bdb_lfp_backlight_data_entry data[16];
> - u8 level[16];
> - struct bdb_lfp_backlight_control_method backlight_control[16];
> -} __packed;
> +/*
> + * Block 9 - SRD Feature Block
> + */
>
> -struct aimdb_header {
> - char signature[16];
> - char oem_device[20];
> - u16 aimdb_version;
> - u16 aimdb_header_size;
> - u16 aimdb_size;
> -} __packed;
> +struct psr_table {
> + /* Feature bits */
> + u8 full_link:1;
> + u8 require_aux_to_wakeup:1;
> + u8 feature_bits_rsvd:6;
>
> -struct aimdb_block {
> - u8 aimdb_id;
> - u16 aimdb_size;
> -} __packed;
> + /* Wait times */
> + u8 idle_frames:4;
> + u8 lines_to_wait:3;
> + u8 wait_times_rsvd:1;
>
> -struct vch_panel_data {
> - u16 fp_timing_offset;
> - u8 fp_timing_size;
> - u16 dvo_timing_offset;
> - u8 dvo_timing_size;
> - u16 text_fitting_offset;
> - u8 text_fitting_size;
> - u16 graphics_fitting_offset;
> - u8 graphics_fitting_size;
> -} __packed;
> + /* TP wake up time in multiple of 100 */
> + u16 tp1_wakeup_time;
> + u16 tp2_tp3_wakeup_time;
>
> -struct vch_bdb_22 {
> - struct aimdb_block aimdb_block;
> - struct vch_panel_data panels[16];
> + /* PSR2 TP2/TP3 wakeup time for 16 panels */
> + u32 psr2_tp2_tp3_wakeup_time;
> } __packed;
>
> -struct bdb_sdvo_lvds_options {
> - u8 panel_backlight;
> - u8 h40_set_panel_type;
> - u8 panel_type;
> - u8 ssc_clk_freq;
> - u16 als_low_trip;
> - u16 als_high_trip;
> - u8 sclalarcoeff_tab_row_num;
> - u8 sclalarcoeff_tab_row_size;
> - u8 coefficient[8];
> - u8 panel_misc_bits_1;
> - u8 panel_misc_bits_2;
> - u8 panel_misc_bits_3;
> - u8 panel_misc_bits_4;
> +struct bdb_psr {
> + struct psr_table psr_table[16];
> } __packed;
>
> +/*
> + * Block 12 - Driver Features Data Block
> + */
>
> #define BDB_DRIVER_FEATURE_NO_LVDS 0
> #define BDB_DRIVER_FEATURE_INT_LVDS 1
> #define BDB_DRIVER_FEATURE_SDVO_LVDS 2
> -#define BDB_DRIVER_FEATURE_EDP 3
> +#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3
>
> struct bdb_driver_features {
> u8 boot_dev_algorithm:1;
> @@ -684,6 +547,69 @@ struct bdb_driver_features {
> u16 pc_feature_valid:1;
> } __packed;
>
> +/*
> + * Block 22 - SDVO LVDS General Options
> + */
> +
> +struct bdb_sdvo_lvds_options {
> + u8 panel_backlight;
> + u8 h40_set_panel_type;
> + u8 panel_type;
> + u8 ssc_clk_freq;
> + u16 als_low_trip;
> + u16 als_high_trip;
> + u8 sclalarcoeff_tab_row_num;
> + u8 sclalarcoeff_tab_row_size;
> + u8 coefficient[8];
> + u8 panel_misc_bits_1;
> + u8 panel_misc_bits_2;
> + u8 panel_misc_bits_3;
> + u8 panel_misc_bits_4;
> +} __packed;
> +
> +/*
> + * Block 23 - SDVO LVDS Panel DTDs
> + */
> +
> +struct lvds_dvo_timing {
> + u16 clock; /**< In 10khz */
> + u8 hactive_lo;
> + u8 hblank_lo;
> + u8 hblank_hi:4;
> + u8 hactive_hi:4;
> + u8 vactive_lo;
> + u8 vblank_lo;
> + u8 vblank_hi:4;
> + u8 vactive_hi:4;
> + u8 hsync_off_lo;
> + u8 hsync_pulse_width_lo;
> + u8 vsync_pulse_width_lo:4;
> + u8 vsync_off_lo:4;
> + u8 vsync_pulse_width_hi:2;
> + u8 vsync_off_hi:2;
> + u8 hsync_pulse_width_hi:2;
> + u8 hsync_off_hi:2;
> + u8 himage_lo;
> + u8 vimage_lo;
> + u8 vimage_hi:4;
> + u8 himage_hi:4;
> + u8 h_border;
> + u8 v_border;
> + u8 rsvd1:3;
> + u8 digital:2;
> + u8 vsync_positive:1;
> + u8 hsync_positive:1;
> + u8 non_interlaced:1;
> +} __packed;
> +
> +struct bdb_sdvo_panel_dtds {
> + struct lvds_dvo_timing dtds[4];
> +} __packed;
> +
> +/*
> + * Block 27 - eDP VBT Block
> + */
> +
> #define EDP_18BPP 0
> #define EDP_24BPP 1
> #define EDP_30BPP 2
> @@ -736,151 +662,133 @@ struct bdb_edp {
> struct edp_full_link_params full_link_params[16]; /* 199 */
> } __packed;
>
> -struct psr_table {
> - /* Feature bits */
> - u8 full_link:1;
> - u8 require_aux_to_wakeup:1;
> - u8 feature_bits_rsvd:6;
> +/*
> + * Block 40 - LFP Data Block
> + */
>
> - /* Wait times */
> - u8 idle_frames:4;
> - u8 lines_to_wait:3;
> - u8 wait_times_rsvd:1;
> +/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
> +#define MODE_MASK 0x3
>
> - /* TP wake up time in multiple of 100 */
> - u16 tp1_wakeup_time;
> - u16 tp2_tp3_wakeup_time;
> +struct bdb_lvds_options {
> + u8 panel_type;
> + u8 panel_type2; /* 212 */
> + /* LVDS capabilities, stored in a dword */
> + u8 pfit_mode:2;
> + u8 pfit_text_mode_enhanced:1;
> + u8 pfit_gfx_mode_enhanced:1;
> + u8 pfit_ratio_auto:1;
> + u8 pixel_dither:1;
> + u8 lvds_edid:1;
> + u8 rsvd2:1;
> + u8 rsvd4;
> + /* LVDS Panel channel bits stored here */
> + u32 lvds_panel_channel_bits;
> + /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
> + u16 ssc_bits;
> + u16 ssc_freq;
> + u16 ssc_ddt;
> + /* Panel color depth defined here */
> + u16 panel_color_depth;
> + /* LVDS panel type bits stored here */
> + u32 dps_panel_type_bits;
> + /* LVDS backlight control type bits stored here */
> + u32 blt_control_type_bits;
> +
> + u16 lcdvcc_s0_enable; /* 200 */
> + u32 rotation; /* 228 */
> } __packed;
>
> -struct bdb_psr {
> - struct psr_table psr_table[16];
> +/*
> + * Block 41 - LFP Data Table Pointers
> + */
> +
> +/* LFP pointer table contains entries to the struct below */
> +struct lvds_lfp_data_ptr {
> + u16 fp_timing_offset; /* offsets are from start of bdb */
> + u8 fp_table_size;
> + u16 dvo_timing_offset;
> + u8 dvo_table_size;
> + u16 panel_pnp_id_offset;
> + u8 pnp_table_size;
> +} __packed;
> +
> +struct bdb_lvds_lfp_data_ptrs {
> + u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
> + struct lvds_lfp_data_ptr ptr[16];
> } __packed;
>
> /*
> - * Driver<->VBIOS interaction occurs through scratch bits in
> - * GR18 & SWF*.
> + * Block 42 - LFP Data Tables
> */
>
> -/* GR18 bits are set on display switch and hotkey events */
> -#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
> -#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
> -#define GR18_HK_NONE (0x0<<3)
> -#define GR18_HK_LFP_STRETCH (0x1<<3)
> -#define GR18_HK_TOGGLE_DISP (0x2<<3)
> -#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
> -#define GR18_HK_POPUP_DISABLED (0x6<<3)
> -#define GR18_HK_POPUP_ENABLED (0x7<<3)
> -#define GR18_HK_PFIT (0x8<<3)
> -#define GR18_HK_APM_CHANGE (0xa<<3)
> -#define GR18_HK_MULTIPLE (0xc<<3)
> -#define GR18_USER_INT_EN (1<<2)
> -#define GR18_A0000_FLUSH_EN (1<<1)
> -#define GR18_SMM_EN (1<<0)
> -
> -/* Set by driver, cleared by VBIOS */
> -#define SWF00_YRES_SHIFT 16
> -#define SWF00_XRES_SHIFT 0
> -#define SWF00_RES_MASK 0xffff
> -
> -/* Set by VBIOS at boot time and driver at runtime */
> -#define SWF01_TV2_FORMAT_SHIFT 8
> -#define SWF01_TV1_FORMAT_SHIFT 0
> -#define SWF01_TV_FORMAT_MASK 0xffff
> -
> -#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
> -#define SWF10_GTT_OVERRIDE_EN (1<<28)
> -#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
> -#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
> -#define SWF10_OLD_TOGGLE 0x0
> -#define SWF10_TOGGLE_LIST_1 0x1
> -#define SWF10_TOGGLE_LIST_2 0x2
> -#define SWF10_TOGGLE_LIST_3 0x3
> -#define SWF10_TOGGLE_LIST_4 0x4
> -#define SWF10_PANNING_EN (1<<23)
> -#define SWF10_DRIVER_LOADED (1<<22)
> -#define SWF10_EXTENDED_DESKTOP (1<<21)
> -#define SWF10_EXCLUSIVE_MODE (1<<20)
> -#define SWF10_OVERLAY_EN (1<<19)
> -#define SWF10_PLANEB_HOLDOFF (1<<18)
> -#define SWF10_PLANEA_HOLDOFF (1<<17)
> -#define SWF10_VGA_HOLDOFF (1<<16)
> -#define SWF10_ACTIVE_DISP_MASK 0xffff
> -#define SWF10_PIPEB_LFP2 (1<<15)
> -#define SWF10_PIPEB_EFP2 (1<<14)
> -#define SWF10_PIPEB_TV2 (1<<13)
> -#define SWF10_PIPEB_CRT2 (1<<12)
> -#define SWF10_PIPEB_LFP (1<<11)
> -#define SWF10_PIPEB_EFP (1<<10)
> -#define SWF10_PIPEB_TV (1<<9)
> -#define SWF10_PIPEB_CRT (1<<8)
> -#define SWF10_PIPEA_LFP2 (1<<7)
> -#define SWF10_PIPEA_EFP2 (1<<6)
> -#define SWF10_PIPEA_TV2 (1<<5)
> -#define SWF10_PIPEA_CRT2 (1<<4)
> -#define SWF10_PIPEA_LFP (1<<3)
> -#define SWF10_PIPEA_EFP (1<<2)
> -#define SWF10_PIPEA_TV (1<<1)
> -#define SWF10_PIPEA_CRT (1<<0)
> -
> -#define SWF11_MEMORY_SIZE_SHIFT 16
> -#define SWF11_SV_TEST_EN (1<<15)
> -#define SWF11_IS_AGP (1<<14)
> -#define SWF11_DISPLAY_HOLDOFF (1<<13)
> -#define SWF11_DPMS_REDUCED (1<<12)
> -#define SWF11_IS_VBE_MODE (1<<11)
> -#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
> -#define SWF11_DPMS_MASK 0x07
> -#define SWF11_DPMS_OFF (1<<2)
> -#define SWF11_DPMS_SUSPEND (1<<1)
> -#define SWF11_DPMS_STANDBY (1<<0)
> -#define SWF11_DPMS_ON 0
> -
> -#define SWF14_GFX_PFIT_EN (1<<31)
> -#define SWF14_TEXT_PFIT_EN (1<<30)
> -#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
> -#define SWF14_POPUP_EN (1<<28)
> -#define SWF14_DISPLAY_HOLDOFF (1<<27)
> -#define SWF14_DISP_DETECT_EN (1<<26)
> -#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
> -#define SWF14_DRIVER_STATUS (1<<24)
> -#define SWF14_OS_TYPE_WIN9X (1<<23)
> -#define SWF14_OS_TYPE_WINNT (1<<22)
> -/* 21:19 rsvd */
> -#define SWF14_PM_TYPE_MASK 0x00070000
> -#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
> -#define SWF14_PM_ACPI (0x3 << 16)
> -#define SWF14_PM_APM_12 (0x2 << 16)
> -#define SWF14_PM_APM_11 (0x1 << 16)
> -#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
> - /* if GR18 indicates a display switch */
> -#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
> -#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
> -#define SWF14_DS_PIPEB_TV2_EN (1<<13)
> -#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
> -#define SWF14_DS_PIPEB_LFP_EN (1<<11)
> -#define SWF14_DS_PIPEB_EFP_EN (1<<10)
> -#define SWF14_DS_PIPEB_TV_EN (1<<9)
> -#define SWF14_DS_PIPEB_CRT_EN (1<<8)
> -#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
> -#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
> -#define SWF14_DS_PIPEA_TV2_EN (1<<5)
> -#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
> -#define SWF14_DS_PIPEA_LFP_EN (1<<3)
> -#define SWF14_DS_PIPEA_EFP_EN (1<<2)
> -#define SWF14_DS_PIPEA_TV_EN (1<<1)
> -#define SWF14_DS_PIPEA_CRT_EN (1<<0)
> - /* if GR18 indicates a panel fitting request */
> -#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
> - /* if GR18 indicates an APM change request */
> -#define SWF14_APM_HIBERNATE 0x4
> -#define SWF14_APM_SUSPEND 0x3
> -#define SWF14_APM_STANDBY 0x1
> -#define SWF14_APM_RESTORE 0x0
> -
> -/* Block 52 contains MIPI configuration block
> - * 6 * bdb_mipi_config, followed by 6 pps data block
> - * block below
> +/* LFP data has 3 blocks per entry */
> +struct lvds_fp_timing {
> + u16 x_res;
> + u16 y_res;
> + u32 lvds_reg;
> + u32 lvds_reg_val;
> + u32 pp_on_reg;
> + u32 pp_on_reg_val;
> + u32 pp_off_reg;
> + u32 pp_off_reg_val;
> + u32 pp_cycle_reg;
> + u32 pp_cycle_reg_val;
> + u32 pfit_reg;
> + u32 pfit_reg_val;
> + u16 terminator;
> +} __packed;
> +
> +struct lvds_pnp_id {
> + u16 mfg_name;
> + u16 product_code;
> + u32 serial;
> + u8 mfg_week;
> + u8 mfg_year;
> +} __packed;
> +
> +struct lvds_lfp_data_entry {
> + struct lvds_fp_timing fp_timing;
> + struct lvds_dvo_timing dvo_timing;
> + struct lvds_pnp_id pnp_id;
> +} __packed;
> +
> +struct bdb_lvds_lfp_data {
> + struct lvds_lfp_data_entry data[16];
> +} __packed;
> +
> +/*
> + * Block 43 - LFP Backlight Control Data Block
> */
> +
> +#define BDB_BACKLIGHT_TYPE_NONE 0
> +#define BDB_BACKLIGHT_TYPE_PWM 2
> +
> +struct lfp_backlight_data_entry {
> + u8 type:2;
> + u8 active_low_pwm:1;
> + u8 obsolete1:5;
> + u16 pwm_freq_hz;
> + u8 min_brightness;
> + u8 obsolete2;
> + u8 obsolete3;
> +} __packed;
> +
> +struct lfp_backlight_control_method {
> + u8 type:4;
> + u8 controller:4;
> +} __packed;
> +
> +struct bdb_lfp_backlight_data {
> + u8 entry_size;
> + struct lfp_backlight_data_entry data[16];
> + u8 level[16];
> + struct lfp_backlight_control_method backlight_control[16];
> +} __packed;
> +
> +/*
> + * Block 52 - MIPI Configuration Block
> + */
> +
> #define MAX_MIPI_CONFIGURATIONS 6
>
> struct bdb_mipi_config {
> @@ -888,24 +796,13 @@ struct bdb_mipi_config {
> struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
> } __packed;
>
> -/* Block 53 contains MIPI sequences as needed by the panel
> - * for enabling it. This block can be variable in size and
> - * can be maximum of 6 blocks
> +/*
> + * Block 53 - MIPI Sequence Block
> */
> +
> struct bdb_mipi_sequence {
> u8 version;
> - u8 data[0];
> + u8 data[0]; /* up to 6 variable length blocks */
> } __packed;
>
> -enum mipi_gpio_pin_index {
> - MIPI_GPIO_UNDEFINED = 0,
> - MIPI_GPIO_PANEL_ENABLE,
> - MIPI_GPIO_BL_ENABLE,
> - MIPI_GPIO_PWM_ENABLE,
> - MIPI_GPIO_RESET_N,
> - MIPI_GPIO_PWR_DOWN_R,
> - MIPI_GPIO_STDBY_RST_N,
> - MIPI_GPIO_MAX
> -};
> -
> #endif /* _INTEL_VBT_DEFS_H_ */
> --
> 2.20.1
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
--
Ville Syrjälä
Intel
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] tools/intel_vbt_decode: update vbt defs from kernel
2019-06-05 12:57 ` Ville Syrjälä
@ 2019-06-05 13:22 ` Jani Nikula
0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2019-06-05 13:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: igt-dev
On Wed, 05 Jun 2019, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Jun 05, 2019 at 03:33:00PM +0300, Jani Nikula wrote:
>> Sync up to commit f41c615310d2 ("drm/i915/bios: add an enum for BDB
>> block IDs") in kernel intel_vbt_defs.h, and update the tool with the
>> struct renames.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks, pushed.
BR,
Jani.
>
>> ---
>> tools/intel_vbt_decode.c | 6 +-
>> tools/intel_vbt_defs.h | 657 +++++++++++++++++----------------------
>> 2 files changed, 280 insertions(+), 383 deletions(-)
>>
>> diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
>> index d80b1dae7725..38eccc48f38b 100644
>> --- a/tools/intel_vbt_decode.c
>> +++ b/tools/intel_vbt_decode.c
>> @@ -228,7 +228,7 @@ static void dump_backlight_info(struct context *context,
>> const struct bdb_block *block)
>> {
>> const struct bdb_lfp_backlight_data *backlight = block->data;
>> - const struct bdb_lfp_backlight_data_entry *blc;
>> + const struct lfp_backlight_data_entry *blc;
>>
>> if (sizeof(*blc) != backlight->entry_size) {
>> printf("\tBacklight struct sizes don't match (expected %zu, got %u), skipping\n",
>> @@ -629,8 +629,8 @@ static void dump_lvds_data(struct context *context,
>> const uint8_t *lfp_data_ptr =
>> (const uint8_t *) lvds_data->data + lfp_data_size * i;
>> const uint8_t *timing_data = lfp_data_ptr + dvo_offset;
>> - const struct bdb_lvds_lfp_data_entry *lfp_data =
>> - (const struct bdb_lvds_lfp_data_entry *)lfp_data_ptr;
>> + const struct lvds_lfp_data_entry *lfp_data =
>> + (const struct lvds_lfp_data_entry *)lfp_data_ptr;
>> char marker;
>>
>> if (i != context->panel_type && !context->dump_all_panel_types)
>> diff --git a/tools/intel_vbt_defs.h b/tools/intel_vbt_defs.h
>> index 3f5eff49105b..89ef14cafb6b 100644
>> --- a/tools/intel_vbt_defs.h
>> +++ b/tools/intel_vbt_defs.h
>> @@ -75,65 +75,51 @@ struct bdb_header {
>> u16 bdb_size;
>> } __packed;
>>
>> -/* strictly speaking, this is a "skip" block, but it has interesting info */
>> -struct vbios_data {
>> - u8 type; /* 0 == desktop, 1 == mobile */
>> - u8 relstage;
>> - u8 chipset;
>> - u8 lvds_present:1;
>> - u8 tv_present:1;
>> - u8 rsvd2:6; /* finish byte */
>> - u8 rsvd3[4];
>> - u8 signon[155];
>> - u8 copyright[61];
>> - u16 code_segment;
>> - u8 dos_boot_mode;
>> - u8 bandwidth_percent;
>> - u8 rsvd4; /* popup memory size */
>> - u8 resize_pci_bios;
>> - u8 rsvd5; /* is crt already on ddc2 */
>> -} __packed;
>> -
>> /*
>> * There are several types of BIOS data blocks (BDBs), each block has
>> * an ID and size in the first 3 bytes (ID in first, size in next 2).
>> * Known types are listed below.
>> */
>> -#define BDB_GENERAL_FEATURES 1
>> -#define BDB_GENERAL_DEFINITIONS 2
>> -#define BDB_OLD_TOGGLE_LIST 3
>> -#define BDB_MODE_SUPPORT_LIST 4
>> -#define BDB_GENERIC_MODE_TABLE 5
>> -#define BDB_EXT_MMIO_REGS 6
>> -#define BDB_SWF_IO 7
>> -#define BDB_SWF_MMIO 8
>> -#define BDB_PSR 9
>> -#define BDB_MODE_REMOVAL_TABLE 10
>> -#define BDB_CHILD_DEVICE_TABLE 11
>> -#define BDB_DRIVER_FEATURES 12
>> -#define BDB_DRIVER_PERSISTENCE 13
>> -#define BDB_EXT_TABLE_PTRS 14
>> -#define BDB_DOT_CLOCK_OVERRIDE 15
>> -#define BDB_DISPLAY_SELECT 16
>> -/* 17 rsvd */
>> -#define BDB_DRIVER_ROTATION 18
>> -#define BDB_DISPLAY_REMOVE 19
>> -#define BDB_OEM_CUSTOM 20
>> -#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
>> -#define BDB_SDVO_LVDS_OPTIONS 22
>> -#define BDB_SDVO_PANEL_DTDS 23
>> -#define BDB_SDVO_LVDS_PNP_IDS 24
>> -#define BDB_SDVO_LVDS_POWER_SEQ 25
>> -#define BDB_TV_OPTIONS 26
>> -#define BDB_EDP 27
>> -#define BDB_LVDS_OPTIONS 40
>> -#define BDB_LVDS_LFP_DATA_PTRS 41
>> -#define BDB_LVDS_LFP_DATA 42
>> -#define BDB_LVDS_BACKLIGHT 43
>> -#define BDB_LVDS_POWER 44
>> -#define BDB_MIPI_CONFIG 52
>> -#define BDB_MIPI_SEQUENCE 53
>> -#define BDB_SKIP 254 /* VBIOS private block, ignore */
>> +enum bdb_block_id {
>> + BDB_GENERAL_FEATURES = 1,
>> + BDB_GENERAL_DEFINITIONS = 2,
>> + BDB_OLD_TOGGLE_LIST = 3,
>> + BDB_MODE_SUPPORT_LIST = 4,
>> + BDB_GENERIC_MODE_TABLE = 5,
>> + BDB_EXT_MMIO_REGS = 6,
>> + BDB_SWF_IO = 7,
>> + BDB_SWF_MMIO = 8,
>> + BDB_PSR = 9,
>> + BDB_MODE_REMOVAL_TABLE = 10,
>> + BDB_CHILD_DEVICE_TABLE = 11,
>> + BDB_DRIVER_FEATURES = 12,
>> + BDB_DRIVER_PERSISTENCE = 13,
>> + BDB_EXT_TABLE_PTRS = 14,
>> + BDB_DOT_CLOCK_OVERRIDE = 15,
>> + BDB_DISPLAY_SELECT = 16,
>> + BDB_DRIVER_ROTATION = 18,
>> + BDB_DISPLAY_REMOVE = 19,
>> + BDB_OEM_CUSTOM = 20,
>> + BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */
>> + BDB_SDVO_LVDS_OPTIONS = 22,
>> + BDB_SDVO_PANEL_DTDS = 23,
>> + BDB_SDVO_LVDS_PNP_IDS = 24,
>> + BDB_SDVO_LVDS_POWER_SEQ = 25,
>> + BDB_TV_OPTIONS = 26,
>> + BDB_EDP = 27,
>> + BDB_LVDS_OPTIONS = 40,
>> + BDB_LVDS_LFP_DATA_PTRS = 41,
>> + BDB_LVDS_LFP_DATA = 42,
>> + BDB_LVDS_BACKLIGHT = 43,
>> + BDB_LVDS_POWER = 44,
>> + BDB_MIPI_CONFIG = 52,
>> + BDB_MIPI_SEQUENCE = 53,
>> + BDB_SKIP = 254, /* VBIOS private block, ignore */
>> +};
>> +
>> +/*
>> + * Block 1 - General Bit Definitions
>> + */
>>
>> struct bdb_general_features {
>> /* bits 1 */
>> @@ -176,6 +162,10 @@ struct bdb_general_features {
>> u8 rsvd11:2; /* finish byte */
>> } __packed;
>>
>> +/*
>> + * Block 2 - General Bytes Definition
>> + */
>> +
>> /* pre-915 */
>> #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
>> #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
>> @@ -299,6 +289,8 @@ struct bdb_general_features {
>> #define DVO_PORT_DPA 10
>> #define DVO_PORT_DPE 11 /* 193 */
>> #define DVO_PORT_HDMIE 12 /* 193 */
>> +#define DVO_PORT_DPF 13 /* N/A */
>> +#define DVO_PORT_HDMIF 14 /* N/A */
>> #define DVO_PORT_MIPIA 21 /* 171 */
>> #define DVO_PORT_MIPIB 22 /* 171 */
>> #define DVO_PORT_MIPIC 23 /* 171 */
>> @@ -316,8 +308,26 @@ enum vbt_gmbus_ddi {
>> DDC_BUS_DDI_C,
>> DDC_BUS_DDI_D,
>> DDC_BUS_DDI_F,
>> + ICL_DDC_BUS_DDI_A = 0x1,
>> + ICL_DDC_BUS_DDI_B,
>> + ICL_DDC_BUS_PORT_1 = 0x4,
>> + ICL_DDC_BUS_PORT_2,
>> + ICL_DDC_BUS_PORT_3,
>> + ICL_DDC_BUS_PORT_4,
>> };
>>
>> +#define DP_AUX_A 0x40
>> +#define DP_AUX_B 0x10
>> +#define DP_AUX_C 0x20
>> +#define DP_AUX_D 0x30
>> +#define DP_AUX_E 0x50
>> +#define DP_AUX_F 0x60
>> +
>> +#define VBT_DP_MAX_LINK_RATE_HBR3 0
>> +#define VBT_DP_MAX_LINK_RATE_HBR2 1
>> +#define VBT_DP_MAX_LINK_RATE_HBR 2
>> +#define VBT_DP_MAX_LINK_RATE_LBR 3
>> +
>> /*
>> * The child device config, aka the display device data structure, provides a
>> * description of a port and its configuration on the platform.
>> @@ -382,7 +392,8 @@ struct child_device_config {
>> u8 lspcon:1; /* 192 */
>> u8 iboost:1; /* 196 */
>> u8 hpd_invert:1; /* 196 */
>> - u8 flag_reserved:3;
>> + u8 use_vbt_vswing:1; /* 218 */
>> + u8 flag_reserved:2;
>> u8 hdmi_support:1; /* 158 */
>> u8 dp_support:1; /* 158 */
>> u8 tmds_support:1; /* 158 */
>> @@ -407,7 +418,9 @@ struct child_device_config {
>> u16 extended_type;
>> u8 dvo_function;
>> u8 dp_usb_type_c:1; /* 195 */
>> - u8 flags2_reserved:7; /* 195 */
>> + u8 tbt:1; /* 209 */
>> + u8 flags2_reserved:2; /* 195 */
>> + u8 dp_port_trace_length:4; /* 209 */
>> u8 dp_gpio_index; /* 195 */
>> u16 dp_gpio_pin_num; /* 195 */
>> u8 dp_iboost_level:4; /* 196 */
>> @@ -441,194 +454,44 @@ struct bdb_general_definitions {
>> * number = (block_size - sizeof(bdb_general_definitions))/
>> * defs->child_dev_size;
>> */
>> - uint8_t devices[0];
>> -} __packed;
>> -
>> -/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
>> -#define MODE_MASK 0x3
>> -
>> -struct bdb_lvds_options {
>> - u8 panel_type;
>> - u8 rsvd1;
>> - /* LVDS capabilities, stored in a dword */
>> - u8 pfit_mode:2;
>> - u8 pfit_text_mode_enhanced:1;
>> - u8 pfit_gfx_mode_enhanced:1;
>> - u8 pfit_ratio_auto:1;
>> - u8 pixel_dither:1;
>> - u8 lvds_edid:1;
>> - u8 rsvd2:1;
>> - u8 rsvd4;
>> - /* LVDS Panel channel bits stored here */
>> - u32 lvds_panel_channel_bits;
>> - /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
>> - u16 ssc_bits;
>> - u16 ssc_freq;
>> - u16 ssc_ddt;
>> - /* Panel color depth defined here */
>> - u16 panel_color_depth;
>> - /* LVDS panel type bits stored here */
>> - u32 dps_panel_type_bits;
>> - /* LVDS backlight control type bits stored here */
>> - u32 blt_control_type_bits;
>> -} __packed;
>> -
>> -/* LFP pointer table contains entries to the struct below */
>> -struct bdb_lvds_lfp_data_ptr {
>> - u16 fp_timing_offset; /* offsets are from start of bdb */
>> - u8 fp_table_size;
>> - u16 dvo_timing_offset;
>> - u8 dvo_table_size;
>> - u16 panel_pnp_id_offset;
>> - u8 pnp_table_size;
>> -} __packed;
>> -
>> -struct bdb_lvds_lfp_data_ptrs {
>> - u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
>> - struct bdb_lvds_lfp_data_ptr ptr[16];
>> -} __packed;
>> -
>> -/* LFP data has 3 blocks per entry */
>> -struct lvds_fp_timing {
>> - u16 x_res;
>> - u16 y_res;
>> - u32 lvds_reg;
>> - u32 lvds_reg_val;
>> - u32 pp_on_reg;
>> - u32 pp_on_reg_val;
>> - u32 pp_off_reg;
>> - u32 pp_off_reg_val;
>> - u32 pp_cycle_reg;
>> - u32 pp_cycle_reg_val;
>> - u32 pfit_reg;
>> - u32 pfit_reg_val;
>> - u16 terminator;
>> + u8 devices[0];
>> } __packed;
>>
>> -struct lvds_dvo_timing {
>> - u16 clock; /**< In 10khz */
>> - u8 hactive_lo;
>> - u8 hblank_lo;
>> - u8 hblank_hi:4;
>> - u8 hactive_hi:4;
>> - u8 vactive_lo;
>> - u8 vblank_lo;
>> - u8 vblank_hi:4;
>> - u8 vactive_hi:4;
>> - u8 hsync_off_lo;
>> - u8 hsync_pulse_width_lo;
>> - u8 vsync_pulse_width_lo:4;
>> - u8 vsync_off_lo:4;
>> - u8 vsync_pulse_width_hi:2;
>> - u8 vsync_off_hi:2;
>> - u8 hsync_pulse_width_hi:2;
>> - u8 hsync_off_hi:2;
>> - u8 himage_lo;
>> - u8 vimage_lo;
>> - u8 vimage_hi:4;
>> - u8 himage_hi:4;
>> - u8 h_border;
>> - u8 v_border;
>> - u8 rsvd1:3;
>> - u8 digital:2;
>> - u8 vsync_positive:1;
>> - u8 hsync_positive:1;
>> - u8 non_interlaced:1;
>> -} __packed;
>> -
>> -struct lvds_pnp_id {
>> - u16 mfg_name;
>> - u16 product_code;
>> - u32 serial;
>> - u8 mfg_week;
>> - u8 mfg_year;
>> -} __packed;
>> -
>> -struct bdb_lvds_lfp_data_entry {
>> - struct lvds_fp_timing fp_timing;
>> - struct lvds_dvo_timing dvo_timing;
>> - struct lvds_pnp_id pnp_id;
>> -} __packed;
>> -
>> -struct bdb_lvds_lfp_data {
>> - struct bdb_lvds_lfp_data_entry data[16];
>> -} __packed;
>> -
>> -#define BDB_BACKLIGHT_TYPE_NONE 0
>> -#define BDB_BACKLIGHT_TYPE_PWM 2
>> -
>> -struct bdb_lfp_backlight_data_entry {
>> - u8 type:2;
>> - u8 active_low_pwm:1;
>> - u8 obsolete1:5;
>> - u16 pwm_freq_hz;
>> - u8 min_brightness;
>> - u8 obsolete2;
>> - u8 obsolete3;
>> -} __packed;
>> -
>> -struct bdb_lfp_backlight_control_method {
>> - u8 type:4;
>> - u8 controller:4;
>> -} __packed;
>> -
>> -struct bdb_lfp_backlight_data {
>> - u8 entry_size;
>> - struct bdb_lfp_backlight_data_entry data[16];
>> - u8 level[16];
>> - struct bdb_lfp_backlight_control_method backlight_control[16];
>> -} __packed;
>> +/*
>> + * Block 9 - SRD Feature Block
>> + */
>>
>> -struct aimdb_header {
>> - char signature[16];
>> - char oem_device[20];
>> - u16 aimdb_version;
>> - u16 aimdb_header_size;
>> - u16 aimdb_size;
>> -} __packed;
>> +struct psr_table {
>> + /* Feature bits */
>> + u8 full_link:1;
>> + u8 require_aux_to_wakeup:1;
>> + u8 feature_bits_rsvd:6;
>>
>> -struct aimdb_block {
>> - u8 aimdb_id;
>> - u16 aimdb_size;
>> -} __packed;
>> + /* Wait times */
>> + u8 idle_frames:4;
>> + u8 lines_to_wait:3;
>> + u8 wait_times_rsvd:1;
>>
>> -struct vch_panel_data {
>> - u16 fp_timing_offset;
>> - u8 fp_timing_size;
>> - u16 dvo_timing_offset;
>> - u8 dvo_timing_size;
>> - u16 text_fitting_offset;
>> - u8 text_fitting_size;
>> - u16 graphics_fitting_offset;
>> - u8 graphics_fitting_size;
>> -} __packed;
>> + /* TP wake up time in multiple of 100 */
>> + u16 tp1_wakeup_time;
>> + u16 tp2_tp3_wakeup_time;
>>
>> -struct vch_bdb_22 {
>> - struct aimdb_block aimdb_block;
>> - struct vch_panel_data panels[16];
>> + /* PSR2 TP2/TP3 wakeup time for 16 panels */
>> + u32 psr2_tp2_tp3_wakeup_time;
>> } __packed;
>>
>> -struct bdb_sdvo_lvds_options {
>> - u8 panel_backlight;
>> - u8 h40_set_panel_type;
>> - u8 panel_type;
>> - u8 ssc_clk_freq;
>> - u16 als_low_trip;
>> - u16 als_high_trip;
>> - u8 sclalarcoeff_tab_row_num;
>> - u8 sclalarcoeff_tab_row_size;
>> - u8 coefficient[8];
>> - u8 panel_misc_bits_1;
>> - u8 panel_misc_bits_2;
>> - u8 panel_misc_bits_3;
>> - u8 panel_misc_bits_4;
>> +struct bdb_psr {
>> + struct psr_table psr_table[16];
>> } __packed;
>>
>> +/*
>> + * Block 12 - Driver Features Data Block
>> + */
>>
>> #define BDB_DRIVER_FEATURE_NO_LVDS 0
>> #define BDB_DRIVER_FEATURE_INT_LVDS 1
>> #define BDB_DRIVER_FEATURE_SDVO_LVDS 2
>> -#define BDB_DRIVER_FEATURE_EDP 3
>> +#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3
>>
>> struct bdb_driver_features {
>> u8 boot_dev_algorithm:1;
>> @@ -684,6 +547,69 @@ struct bdb_driver_features {
>> u16 pc_feature_valid:1;
>> } __packed;
>>
>> +/*
>> + * Block 22 - SDVO LVDS General Options
>> + */
>> +
>> +struct bdb_sdvo_lvds_options {
>> + u8 panel_backlight;
>> + u8 h40_set_panel_type;
>> + u8 panel_type;
>> + u8 ssc_clk_freq;
>> + u16 als_low_trip;
>> + u16 als_high_trip;
>> + u8 sclalarcoeff_tab_row_num;
>> + u8 sclalarcoeff_tab_row_size;
>> + u8 coefficient[8];
>> + u8 panel_misc_bits_1;
>> + u8 panel_misc_bits_2;
>> + u8 panel_misc_bits_3;
>> + u8 panel_misc_bits_4;
>> +} __packed;
>> +
>> +/*
>> + * Block 23 - SDVO LVDS Panel DTDs
>> + */
>> +
>> +struct lvds_dvo_timing {
>> + u16 clock; /**< In 10khz */
>> + u8 hactive_lo;
>> + u8 hblank_lo;
>> + u8 hblank_hi:4;
>> + u8 hactive_hi:4;
>> + u8 vactive_lo;
>> + u8 vblank_lo;
>> + u8 vblank_hi:4;
>> + u8 vactive_hi:4;
>> + u8 hsync_off_lo;
>> + u8 hsync_pulse_width_lo;
>> + u8 vsync_pulse_width_lo:4;
>> + u8 vsync_off_lo:4;
>> + u8 vsync_pulse_width_hi:2;
>> + u8 vsync_off_hi:2;
>> + u8 hsync_pulse_width_hi:2;
>> + u8 hsync_off_hi:2;
>> + u8 himage_lo;
>> + u8 vimage_lo;
>> + u8 vimage_hi:4;
>> + u8 himage_hi:4;
>> + u8 h_border;
>> + u8 v_border;
>> + u8 rsvd1:3;
>> + u8 digital:2;
>> + u8 vsync_positive:1;
>> + u8 hsync_positive:1;
>> + u8 non_interlaced:1;
>> +} __packed;
>> +
>> +struct bdb_sdvo_panel_dtds {
>> + struct lvds_dvo_timing dtds[4];
>> +} __packed;
>> +
>> +/*
>> + * Block 27 - eDP VBT Block
>> + */
>> +
>> #define EDP_18BPP 0
>> #define EDP_24BPP 1
>> #define EDP_30BPP 2
>> @@ -736,151 +662,133 @@ struct bdb_edp {
>> struct edp_full_link_params full_link_params[16]; /* 199 */
>> } __packed;
>>
>> -struct psr_table {
>> - /* Feature bits */
>> - u8 full_link:1;
>> - u8 require_aux_to_wakeup:1;
>> - u8 feature_bits_rsvd:6;
>> +/*
>> + * Block 40 - LFP Data Block
>> + */
>>
>> - /* Wait times */
>> - u8 idle_frames:4;
>> - u8 lines_to_wait:3;
>> - u8 wait_times_rsvd:1;
>> +/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
>> +#define MODE_MASK 0x3
>>
>> - /* TP wake up time in multiple of 100 */
>> - u16 tp1_wakeup_time;
>> - u16 tp2_tp3_wakeup_time;
>> +struct bdb_lvds_options {
>> + u8 panel_type;
>> + u8 panel_type2; /* 212 */
>> + /* LVDS capabilities, stored in a dword */
>> + u8 pfit_mode:2;
>> + u8 pfit_text_mode_enhanced:1;
>> + u8 pfit_gfx_mode_enhanced:1;
>> + u8 pfit_ratio_auto:1;
>> + u8 pixel_dither:1;
>> + u8 lvds_edid:1;
>> + u8 rsvd2:1;
>> + u8 rsvd4;
>> + /* LVDS Panel channel bits stored here */
>> + u32 lvds_panel_channel_bits;
>> + /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
>> + u16 ssc_bits;
>> + u16 ssc_freq;
>> + u16 ssc_ddt;
>> + /* Panel color depth defined here */
>> + u16 panel_color_depth;
>> + /* LVDS panel type bits stored here */
>> + u32 dps_panel_type_bits;
>> + /* LVDS backlight control type bits stored here */
>> + u32 blt_control_type_bits;
>> +
>> + u16 lcdvcc_s0_enable; /* 200 */
>> + u32 rotation; /* 228 */
>> } __packed;
>>
>> -struct bdb_psr {
>> - struct psr_table psr_table[16];
>> +/*
>> + * Block 41 - LFP Data Table Pointers
>> + */
>> +
>> +/* LFP pointer table contains entries to the struct below */
>> +struct lvds_lfp_data_ptr {
>> + u16 fp_timing_offset; /* offsets are from start of bdb */
>> + u8 fp_table_size;
>> + u16 dvo_timing_offset;
>> + u8 dvo_table_size;
>> + u16 panel_pnp_id_offset;
>> + u8 pnp_table_size;
>> +} __packed;
>> +
>> +struct bdb_lvds_lfp_data_ptrs {
>> + u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
>> + struct lvds_lfp_data_ptr ptr[16];
>> } __packed;
>>
>> /*
>> - * Driver<->VBIOS interaction occurs through scratch bits in
>> - * GR18 & SWF*.
>> + * Block 42 - LFP Data Tables
>> */
>>
>> -/* GR18 bits are set on display switch and hotkey events */
>> -#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
>> -#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
>> -#define GR18_HK_NONE (0x0<<3)
>> -#define GR18_HK_LFP_STRETCH (0x1<<3)
>> -#define GR18_HK_TOGGLE_DISP (0x2<<3)
>> -#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
>> -#define GR18_HK_POPUP_DISABLED (0x6<<3)
>> -#define GR18_HK_POPUP_ENABLED (0x7<<3)
>> -#define GR18_HK_PFIT (0x8<<3)
>> -#define GR18_HK_APM_CHANGE (0xa<<3)
>> -#define GR18_HK_MULTIPLE (0xc<<3)
>> -#define GR18_USER_INT_EN (1<<2)
>> -#define GR18_A0000_FLUSH_EN (1<<1)
>> -#define GR18_SMM_EN (1<<0)
>> -
>> -/* Set by driver, cleared by VBIOS */
>> -#define SWF00_YRES_SHIFT 16
>> -#define SWF00_XRES_SHIFT 0
>> -#define SWF00_RES_MASK 0xffff
>> -
>> -/* Set by VBIOS at boot time and driver at runtime */
>> -#define SWF01_TV2_FORMAT_SHIFT 8
>> -#define SWF01_TV1_FORMAT_SHIFT 0
>> -#define SWF01_TV_FORMAT_MASK 0xffff
>> -
>> -#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
>> -#define SWF10_GTT_OVERRIDE_EN (1<<28)
>> -#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
>> -#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
>> -#define SWF10_OLD_TOGGLE 0x0
>> -#define SWF10_TOGGLE_LIST_1 0x1
>> -#define SWF10_TOGGLE_LIST_2 0x2
>> -#define SWF10_TOGGLE_LIST_3 0x3
>> -#define SWF10_TOGGLE_LIST_4 0x4
>> -#define SWF10_PANNING_EN (1<<23)
>> -#define SWF10_DRIVER_LOADED (1<<22)
>> -#define SWF10_EXTENDED_DESKTOP (1<<21)
>> -#define SWF10_EXCLUSIVE_MODE (1<<20)
>> -#define SWF10_OVERLAY_EN (1<<19)
>> -#define SWF10_PLANEB_HOLDOFF (1<<18)
>> -#define SWF10_PLANEA_HOLDOFF (1<<17)
>> -#define SWF10_VGA_HOLDOFF (1<<16)
>> -#define SWF10_ACTIVE_DISP_MASK 0xffff
>> -#define SWF10_PIPEB_LFP2 (1<<15)
>> -#define SWF10_PIPEB_EFP2 (1<<14)
>> -#define SWF10_PIPEB_TV2 (1<<13)
>> -#define SWF10_PIPEB_CRT2 (1<<12)
>> -#define SWF10_PIPEB_LFP (1<<11)
>> -#define SWF10_PIPEB_EFP (1<<10)
>> -#define SWF10_PIPEB_TV (1<<9)
>> -#define SWF10_PIPEB_CRT (1<<8)
>> -#define SWF10_PIPEA_LFP2 (1<<7)
>> -#define SWF10_PIPEA_EFP2 (1<<6)
>> -#define SWF10_PIPEA_TV2 (1<<5)
>> -#define SWF10_PIPEA_CRT2 (1<<4)
>> -#define SWF10_PIPEA_LFP (1<<3)
>> -#define SWF10_PIPEA_EFP (1<<2)
>> -#define SWF10_PIPEA_TV (1<<1)
>> -#define SWF10_PIPEA_CRT (1<<0)
>> -
>> -#define SWF11_MEMORY_SIZE_SHIFT 16
>> -#define SWF11_SV_TEST_EN (1<<15)
>> -#define SWF11_IS_AGP (1<<14)
>> -#define SWF11_DISPLAY_HOLDOFF (1<<13)
>> -#define SWF11_DPMS_REDUCED (1<<12)
>> -#define SWF11_IS_VBE_MODE (1<<11)
>> -#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
>> -#define SWF11_DPMS_MASK 0x07
>> -#define SWF11_DPMS_OFF (1<<2)
>> -#define SWF11_DPMS_SUSPEND (1<<1)
>> -#define SWF11_DPMS_STANDBY (1<<0)
>> -#define SWF11_DPMS_ON 0
>> -
>> -#define SWF14_GFX_PFIT_EN (1<<31)
>> -#define SWF14_TEXT_PFIT_EN (1<<30)
>> -#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
>> -#define SWF14_POPUP_EN (1<<28)
>> -#define SWF14_DISPLAY_HOLDOFF (1<<27)
>> -#define SWF14_DISP_DETECT_EN (1<<26)
>> -#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
>> -#define SWF14_DRIVER_STATUS (1<<24)
>> -#define SWF14_OS_TYPE_WIN9X (1<<23)
>> -#define SWF14_OS_TYPE_WINNT (1<<22)
>> -/* 21:19 rsvd */
>> -#define SWF14_PM_TYPE_MASK 0x00070000
>> -#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
>> -#define SWF14_PM_ACPI (0x3 << 16)
>> -#define SWF14_PM_APM_12 (0x2 << 16)
>> -#define SWF14_PM_APM_11 (0x1 << 16)
>> -#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
>> - /* if GR18 indicates a display switch */
>> -#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
>> -#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
>> -#define SWF14_DS_PIPEB_TV2_EN (1<<13)
>> -#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
>> -#define SWF14_DS_PIPEB_LFP_EN (1<<11)
>> -#define SWF14_DS_PIPEB_EFP_EN (1<<10)
>> -#define SWF14_DS_PIPEB_TV_EN (1<<9)
>> -#define SWF14_DS_PIPEB_CRT_EN (1<<8)
>> -#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
>> -#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
>> -#define SWF14_DS_PIPEA_TV2_EN (1<<5)
>> -#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
>> -#define SWF14_DS_PIPEA_LFP_EN (1<<3)
>> -#define SWF14_DS_PIPEA_EFP_EN (1<<2)
>> -#define SWF14_DS_PIPEA_TV_EN (1<<1)
>> -#define SWF14_DS_PIPEA_CRT_EN (1<<0)
>> - /* if GR18 indicates a panel fitting request */
>> -#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
>> - /* if GR18 indicates an APM change request */
>> -#define SWF14_APM_HIBERNATE 0x4
>> -#define SWF14_APM_SUSPEND 0x3
>> -#define SWF14_APM_STANDBY 0x1
>> -#define SWF14_APM_RESTORE 0x0
>> -
>> -/* Block 52 contains MIPI configuration block
>> - * 6 * bdb_mipi_config, followed by 6 pps data block
>> - * block below
>> +/* LFP data has 3 blocks per entry */
>> +struct lvds_fp_timing {
>> + u16 x_res;
>> + u16 y_res;
>> + u32 lvds_reg;
>> + u32 lvds_reg_val;
>> + u32 pp_on_reg;
>> + u32 pp_on_reg_val;
>> + u32 pp_off_reg;
>> + u32 pp_off_reg_val;
>> + u32 pp_cycle_reg;
>> + u32 pp_cycle_reg_val;
>> + u32 pfit_reg;
>> + u32 pfit_reg_val;
>> + u16 terminator;
>> +} __packed;
>> +
>> +struct lvds_pnp_id {
>> + u16 mfg_name;
>> + u16 product_code;
>> + u32 serial;
>> + u8 mfg_week;
>> + u8 mfg_year;
>> +} __packed;
>> +
>> +struct lvds_lfp_data_entry {
>> + struct lvds_fp_timing fp_timing;
>> + struct lvds_dvo_timing dvo_timing;
>> + struct lvds_pnp_id pnp_id;
>> +} __packed;
>> +
>> +struct bdb_lvds_lfp_data {
>> + struct lvds_lfp_data_entry data[16];
>> +} __packed;
>> +
>> +/*
>> + * Block 43 - LFP Backlight Control Data Block
>> */
>> +
>> +#define BDB_BACKLIGHT_TYPE_NONE 0
>> +#define BDB_BACKLIGHT_TYPE_PWM 2
>> +
>> +struct lfp_backlight_data_entry {
>> + u8 type:2;
>> + u8 active_low_pwm:1;
>> + u8 obsolete1:5;
>> + u16 pwm_freq_hz;
>> + u8 min_brightness;
>> + u8 obsolete2;
>> + u8 obsolete3;
>> +} __packed;
>> +
>> +struct lfp_backlight_control_method {
>> + u8 type:4;
>> + u8 controller:4;
>> +} __packed;
>> +
>> +struct bdb_lfp_backlight_data {
>> + u8 entry_size;
>> + struct lfp_backlight_data_entry data[16];
>> + u8 level[16];
>> + struct lfp_backlight_control_method backlight_control[16];
>> +} __packed;
>> +
>> +/*
>> + * Block 52 - MIPI Configuration Block
>> + */
>> +
>> #define MAX_MIPI_CONFIGURATIONS 6
>>
>> struct bdb_mipi_config {
>> @@ -888,24 +796,13 @@ struct bdb_mipi_config {
>> struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
>> } __packed;
>>
>> -/* Block 53 contains MIPI sequences as needed by the panel
>> - * for enabling it. This block can be variable in size and
>> - * can be maximum of 6 blocks
>> +/*
>> + * Block 53 - MIPI Sequence Block
>> */
>> +
>> struct bdb_mipi_sequence {
>> u8 version;
>> - u8 data[0];
>> + u8 data[0]; /* up to 6 variable length blocks */
>> } __packed;
>>
>> -enum mipi_gpio_pin_index {
>> - MIPI_GPIO_UNDEFINED = 0,
>> - MIPI_GPIO_PANEL_ENABLE,
>> - MIPI_GPIO_BL_ENABLE,
>> - MIPI_GPIO_PWM_ENABLE,
>> - MIPI_GPIO_RESET_N,
>> - MIPI_GPIO_PWR_DOWN_R,
>> - MIPI_GPIO_STDBY_RST_N,
>> - MIPI_GPIO_MAX
>> -};
>> -
>> #endif /* _INTEL_VBT_DEFS_H_ */
>> --
>> 2.20.1
>>
>> _______________________________________________
>> igt-dev mailing list
>> igt-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/igt-dev
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 5+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for tools/intel_vbt_decode: update vbt defs from kernel
2019-06-05 12:33 [igt-dev] [PATCH i-g-t] tools/intel_vbt_decode: update vbt defs from kernel Jani Nikula
2019-06-05 12:57 ` Ville Syrjälä
@ 2019-06-05 13:49 ` Patchwork
2019-06-06 20:28 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2019-06-05 13:49 UTC (permalink / raw)
To: Jani Nikula; +Cc: igt-dev
== Series Details ==
Series: tools/intel_vbt_decode: update vbt defs from kernel
URL : https://patchwork.freedesktop.org/series/61652/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6195 -> IGTPW_3117
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/61652/revisions/1/mbox/
Known issues
------------
Here are the changes found in IGTPW_3117 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-icl-u3/igt@gem_ctx_create@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/fi-icl-u3/igt@gem_ctx_create@basic.html
* igt@gem_ctx_create@basic-files:
- fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#109100])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-icl-y/igt@gem_ctx_create@basic-files.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/fi-icl-y/igt@gem_ctx_create@basic-files.html
#### Possible fixes ####
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][5] ([fdo#102614]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-icl-u3/igt@prime_vgem@basic-fence-flip.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/fi-icl-u3/igt@prime_vgem@basic-fence-flip.html
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
Participating hosts (52 -> 42)
------------------------------
Additional (1): fi-apl-guc
Missing (11): fi-kbl-7567u fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-ivb-3770 fi-pnv-d510 fi-kbl-7560u fi-icl-dsi fi-bdw-samus
Build changes
-------------
* IGT: IGT_5039 -> IGTPW_3117
CI_DRM_6195: 06b71939f2477c76f9eecb1dd5e99dcb25cb8371 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3117: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/
IGT_5039: 2d4f470bba1cb51ed116fb80b170f717c6294714 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 5+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for tools/intel_vbt_decode: update vbt defs from kernel
2019-06-05 12:33 [igt-dev] [PATCH i-g-t] tools/intel_vbt_decode: update vbt defs from kernel Jani Nikula
2019-06-05 12:57 ` Ville Syrjälä
2019-06-05 13:49 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
@ 2019-06-06 20:28 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2019-06-06 20:28 UTC (permalink / raw)
To: Jani Nikula; +Cc: igt-dev
== Series Details ==
Series: tools/intel_vbt_decode: update vbt defs from kernel
URL : https://patchwork.freedesktop.org/series/61652/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6195_full -> IGTPW_3117_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/61652/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_3117_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_balancer@smoke}:
- shard-iclb: [PASS][1] -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb1/igt@gem_exec_balancer@smoke.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-iclb6/igt@gem_exec_balancer@smoke.html
Known issues
------------
Here are the changes found in IGTPW_3117_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@forked-medium-copy:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb5/igt@gem_mmap_gtt@forked-medium-copy.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-iclb3/igt@gem_mmap_gtt@forked-medium-copy.html
* igt@gem_pwrite@big-gtt-backwards:
- shard-glk: [PASS][5] -> [INCOMPLETE][6] ([fdo#103359] / [k.org#198133])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-glk8/igt@gem_pwrite@big-gtt-backwards.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-glk2/igt@gem_pwrite@big-gtt-backwards.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
- shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271]) +33 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-hsw4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb2/igt@kms_psr@psr2_primary_render.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-iclb6/igt@kms_psr@psr2_primary_render.html
* igt@kms_sysfs_edid_timing:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#100047])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb4/igt@kms_sysfs_edid_timing.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-iclb2/igt@kms_sysfs_edid_timing.html
#### Possible fixes ####
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [DMESG-WARN][17] ([fdo#108686]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-apl2/igt@gem_tiled_swapping@non-threaded.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-apl6/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [DMESG-WARN][19] ([fdo#108566]) -> [PASS][20] +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-apl5/igt@gem_workarounds@suspend-resume.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-apl1/igt@gem_workarounds@suspend-resume.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][21] ([fdo#109349]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [INCOMPLETE][23] ([fdo#103665]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-kbl6/igt@kms_flip@flip-vs-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-kbl1/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render:
- shard-iclb: [FAIL][25] ([fdo#103167]) -> [PASS][26] +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-iclb: [FAIL][27] ([fdo#103167] / [fdo#110378]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite:
- shard-hsw: [SKIP][29] ([fdo#109271]) -> [PASS][30] +14 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-hsw4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][31] ([fdo#109441]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][33] ([fdo#99912]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-apl8/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-apl1/igt@kms_setmode@basic.html
#### Warnings ####
* igt@gem_tiled_swapping@non-threaded:
- shard-hsw: [FAIL][35] ([fdo#108686]) -> [INCOMPLETE][36] ([fdo#103540])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/shard-hsw1/igt@gem_tiled_swapping@non-threaded.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/shard-hsw1/igt@gem_tiled_swapping@non-threaded.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 6)
------------------------------
Missing (4): pig-skl-6260u shard-skl pig-hsw-4770r pig-glk-j5005
Build changes
-------------
* IGT: IGT_5039 -> IGTPW_3117
* Piglit: piglit_4509 -> None
CI_DRM_6195: 06b71939f2477c76f9eecb1dd5e99dcb25cb8371 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3117: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/
IGT_5039: 2d4f470bba1cb51ed116fb80b170f717c6294714 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3117/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-06-06 20:28 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-06-05 12:33 [igt-dev] [PATCH i-g-t] tools/intel_vbt_decode: update vbt defs from kernel Jani Nikula
2019-06-05 12:57 ` Ville Syrjälä
2019-06-05 13:22 ` Jani Nikula
2019-06-05 13:49 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2019-06-06 20:28 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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