[PATCH v2 i-g-t 0/4] OA: Run MMIO trigger tests on all OA units

[PATCH v2 i-g-t 0/4] OA: Run MMIO trigger tests on all OA units

[Ashutosh Dixit]

v2: Same as v1 except that Patch 1 now has a real kernel commit

Ashutosh Dixit (4):
  drm-uapi/xe: Sync with DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition
  tests/intel/xe_oa: Return hwe from same gt from oa_unit_engine()
  tests/intel/xe_oa: Run mmio-trigger tests on all OA units
  tests/intel/xe_oa: Use separate oa unit variables for caps and
    iterator

 include/drm-uapi/xe_drm.h |  55 ++++++++++++++--
 tests/intel/xe_oa.c       | 135 +++++++++++++++++++++++++++++++-------
 2 files changed, 162 insertions(+), 28 deletions(-)

-- 
2.48.1

[PATCH i-g-t 1/4] drm-uapi/xe: Sync with DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition

[Ashutosh Dixit]

Align with kernel commit 16e076b03658 ("drm/xe/oa/uapi: Add gt_id to struct
drm_xe_oa_unit") to bring in DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 include/drm-uapi/xe_drm.h | 55 ++++++++++++++++++++++++++++++++++++---
 1 file changed, 51 insertions(+), 4 deletions(-)

diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 89ab549354..62e3221f59 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -210,8 +210,12 @@ struct drm_xe_ext_set_property {
 	/** @pad: MBZ */
 	__u32 pad;
 
-	/** @value: property value */
-	__u64 value;
+	union {
+		/** @value: property value */
+		__u64 value;
+		/** @ptr: pointer to user value */
+		__u64 ptr;
+	};
 
 	/** @reserved: Reserved */
 	__u64 reserved[2];
@@ -403,6 +407,9 @@ struct drm_xe_query_mem_regions {
  *      has low latency hint support
  *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
  *      device has CPU address mirroring support
+ *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the
+ *      device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION.
+ *      This is exposed only on Xe2+.
  *  - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
  *    required by this device, typically SZ_4K or SZ_64K
  *  - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
@@ -421,6 +428,7 @@ struct drm_xe_query_config {
 	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM	(1 << 0)
 	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY	(1 << 1)
 	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR	(1 << 2)
+	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3)
 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT		2
 #define DRM_XE_QUERY_CONFIG_VA_BITS			3
 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY	4
@@ -771,7 +779,11 @@ struct drm_xe_device_query {
  *    until the object is either bound to a virtual memory region via
  *    VM_BIND or accessed by the CPU. As a result, no backing memory is
  *    reserved at the time of GEM object creation.
- *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
+ *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is
+ *    intended for scanout via the display engine. When set, kernel ensures
+ *    that the allocation is placed in a memory region compatible with the
+ *    display engine requirements. This may impose restrictions on tiling,
+ *    alignment, and memory placement to guarantee proper display functionality.
  *  - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
  *    possible placement, ensure that the corresponding VRAM allocation
  *    will always use the CPU accessible part of VRAM. This is important
@@ -787,6 +799,17 @@ struct drm_xe_device_query {
  *    need to use VRAM for display surfaces, therefore the kernel requires
  *    setting this flag for such objects, otherwise an error is thrown on
  *    small-bar systems.
+ *  - %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION - Allows userspace to
+ *    hint that compression (CCS) should be disabled for the buffer being
+ *    created. This can avoid unnecessary memory operations and CCS state
+ *    management.
+ *    On pre-Xe2 platforms, this flag is currently rejected as compression
+ *    control is not supported via PAT index. On Xe2+ platforms, compression
+ *    is controlled via PAT entries. If this flag is set, the driver will reject
+ *    any VM bind that requests a PAT index enabling compression for this BO.
+ *    Note: On dGPU platforms, there is currently no change in behavior with
+ *    this flag, but future improvements may leverage it. The current benefit is
+ *    primarily applicable to iGPU platforms.
  *
  * @cpu_caching supports the following values:
  *  - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
@@ -833,6 +856,7 @@ struct drm_xe_gem_create {
 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING		(1 << 0)
 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT			(1 << 1)
 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(1 << 2)
+#define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION		(1 << 3)
 	/**
 	 * @flags: Flags, currently a mask of memory instances of where BO can
 	 * be placed
@@ -1013,6 +1037,20 @@ struct drm_xe_vm_destroy {
  *    valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
  *    mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
  *    handle MBZ, and the BO offset MBZ.
+ *  - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
+ *    %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying
+ *    CPU address space range is unmapped (typically with munmap(2) or brk(2)).
+ *    The madvise values set with &DRM_IOCTL_XE_MADVISE are reset to the values
+ *    that were present immediately after the &DRM_IOCTL_XE_VM_BIND.
+ *    The reset GPU virtual address range is the intersection of the range bound
+ *    using &DRM_IOCTL_XE_VM_BIND and the virtual CPU address space range
+ *    unmapped.
+ *    This functionality is present to mimic the behaviour of CPU address space
+ *    madvises set using madvise(2), which are typically reset on unmap.
+ *    Note: free(3) may or may not call munmap(2) and/or brk(2), and may thus
+ *    not invoke autoreset. Neither will stack variables going out of scope.
+ *    Therefore it's recommended to always explicitly reset the madvises when
+ *    freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call.
  *
  * The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be:
  *  - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
@@ -1119,6 +1157,7 @@ struct drm_xe_vm_bind_op {
 #define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
 #define DRM_XE_VM_BIND_FLAG_CHECK_PXP	(1 << 4)
 #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR	(1 << 5)
+#define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET	(1 << 6)
 	/** @flags: Bind flags */
 	__u32 flags;
 
@@ -1273,6 +1312,7 @@ struct drm_xe_exec_queue_create {
 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY		0
 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE		1
 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE		2
+#define   DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE		3
 	/** @extensions: Pointer to the first extension struct, if any */
 	__u64 extensions;
 
@@ -1657,12 +1697,19 @@ struct drm_xe_oa_unit {
 #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE	(1 << 2)
 #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS	(1 << 3)
 #define DRM_XE_OA_CAPS_OAM		(1 << 4)
+#define DRM_XE_OA_CAPS_OA_UNIT_GT_ID	(1 << 5)
 
 	/** @oa_timestamp_freq: OA timestamp freq */
 	__u64 oa_timestamp_freq;
 
+	/** @gt_id: gt id for this OA unit */
+	__u16 gt_id;
+
+	/** @reserved1: MBZ */
+	__u16 reserved1[3];
+
 	/** @reserved: MBZ */
-	__u64 reserved[4];
+	__u64 reserved[3];
 
 	/** @num_engines: number of engines in @eci array */
 	__u64 num_engines;
-- 
2.48.1

Re: [PATCH i-g-t 1/4] drm-uapi/xe: Sync with DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition

[Umesh Nerlige Ramappa]

On Thu, Dec 04, 2025 at 04:05:25PM -0800, Ashutosh Dixit wrote:
>Align with kernel commit 16e076b03658 ("drm/xe/oa/uapi: Add gt_id to struct
>drm_xe_oa_unit") to bring in DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition.
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Is the intention also to bring non-OA changes in this commit? Then you 
may want to change the commit message to sync header file or something.

Thanks,
Umesh

>---
> include/drm-uapi/xe_drm.h | 55 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 51 insertions(+), 4 deletions(-)
>
>diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
>index 89ab549354..62e3221f59 100644
>--- a/include/drm-uapi/xe_drm.h
>+++ b/include/drm-uapi/xe_drm.h
>@@ -210,8 +210,12 @@ struct drm_xe_ext_set_property {
> 	/** @pad: MBZ */
> 	__u32 pad;
>
>-	/** @value: property value */
>-	__u64 value;
>+	union {
>+		/** @value: property value */
>+		__u64 value;
>+		/** @ptr: pointer to user value */
>+		__u64 ptr;
>+	};
>
> 	/** @reserved: Reserved */
> 	__u64 reserved[2];
>@@ -403,6 +407,9 @@ struct drm_xe_query_mem_regions {
>  *      has low latency hint support
>  *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
>  *      device has CPU address mirroring support
>+ *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the
>+ *      device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION.
>+ *      This is exposed only on Xe2+.
>  *  - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
>  *    required by this device, typically SZ_4K or SZ_64K
>  *  - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
>@@ -421,6 +428,7 @@ struct drm_xe_query_config {
> 	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM	(1 << 0)
> 	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY	(1 << 1)
> 	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR	(1 << 2)
>+	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3)
> #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT		2
> #define DRM_XE_QUERY_CONFIG_VA_BITS			3
> #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY	4
>@@ -771,7 +779,11 @@ struct drm_xe_device_query {
>  *    until the object is either bound to a virtual memory region via
>  *    VM_BIND or accessed by the CPU. As a result, no backing memory is
>  *    reserved at the time of GEM object creation.
>- *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
>+ *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is
>+ *    intended for scanout via the display engine. When set, kernel ensures
>+ *    that the allocation is placed in a memory region compatible with the
>+ *    display engine requirements. This may impose restrictions on tiling,
>+ *    alignment, and memory placement to guarantee proper display functionality.
>  *  - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
>  *    possible placement, ensure that the corresponding VRAM allocation
>  *    will always use the CPU accessible part of VRAM. This is important
>@@ -787,6 +799,17 @@ struct drm_xe_device_query {
>  *    need to use VRAM for display surfaces, therefore the kernel requires
>  *    setting this flag for such objects, otherwise an error is thrown on
>  *    small-bar systems.
>+ *  - %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION - Allows userspace to
>+ *    hint that compression (CCS) should be disabled for the buffer being
>+ *    created. This can avoid unnecessary memory operations and CCS state
>+ *    management.
>+ *    On pre-Xe2 platforms, this flag is currently rejected as compression
>+ *    control is not supported via PAT index. On Xe2+ platforms, compression
>+ *    is controlled via PAT entries. If this flag is set, the driver will reject
>+ *    any VM bind that requests a PAT index enabling compression for this BO.
>+ *    Note: On dGPU platforms, there is currently no change in behavior with
>+ *    this flag, but future improvements may leverage it. The current benefit is
>+ *    primarily applicable to iGPU platforms.
>  *
>  * @cpu_caching supports the following values:
>  *  - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
>@@ -833,6 +856,7 @@ struct drm_xe_gem_create {
> #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING		(1 << 0)
> #define DRM_XE_GEM_CREATE_FLAG_SCANOUT			(1 << 1)
> #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(1 << 2)
>+#define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION		(1 << 3)
> 	/**
> 	 * @flags: Flags, currently a mask of memory instances of where BO can
> 	 * be placed
>@@ -1013,6 +1037,20 @@ struct drm_xe_vm_destroy {
>  *    valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
>  *    mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
>  *    handle MBZ, and the BO offset MBZ.
>+ *  - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
>+ *    %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying
>+ *    CPU address space range is unmapped (typically with munmap(2) or brk(2)).
>+ *    The madvise values set with &DRM_IOCTL_XE_MADVISE are reset to the values
>+ *    that were present immediately after the &DRM_IOCTL_XE_VM_BIND.
>+ *    The reset GPU virtual address range is the intersection of the range bound
>+ *    using &DRM_IOCTL_XE_VM_BIND and the virtual CPU address space range
>+ *    unmapped.
>+ *    This functionality is present to mimic the behaviour of CPU address space
>+ *    madvises set using madvise(2), which are typically reset on unmap.
>+ *    Note: free(3) may or may not call munmap(2) and/or brk(2), and may thus
>+ *    not invoke autoreset. Neither will stack variables going out of scope.
>+ *    Therefore it's recommended to always explicitly reset the madvises when
>+ *    freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call.
>  *
>  * The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be:
>  *  - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
>@@ -1119,6 +1157,7 @@ struct drm_xe_vm_bind_op {
> #define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
> #define DRM_XE_VM_BIND_FLAG_CHECK_PXP	(1 << 4)
> #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR	(1 << 5)
>+#define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET	(1 << 6)
> 	/** @flags: Bind flags */
> 	__u32 flags;
>
>@@ -1273,6 +1312,7 @@ struct drm_xe_exec_queue_create {
> #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY		0
> #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE		1
> #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE		2
>+#define   DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE		3
> 	/** @extensions: Pointer to the first extension struct, if any */
> 	__u64 extensions;
>
>@@ -1657,12 +1697,19 @@ struct drm_xe_oa_unit {
> #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE	(1 << 2)
> #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS	(1 << 3)
> #define DRM_XE_OA_CAPS_OAM		(1 << 4)
>+#define DRM_XE_OA_CAPS_OA_UNIT_GT_ID	(1 << 5)
>
> 	/** @oa_timestamp_freq: OA timestamp freq */
> 	__u64 oa_timestamp_freq;
>
>+	/** @gt_id: gt id for this OA unit */
>+	__u16 gt_id;
>+
>+	/** @reserved1: MBZ */
>+	__u16 reserved1[3];
>+
> 	/** @reserved: MBZ */
>-	__u64 reserved[4];
>+	__u64 reserved[3];
>
> 	/** @num_engines: number of engines in @eci array */
> 	__u64 num_engines;
>-- 
>2.48.1
>

Re: [PATCH i-g-t 1/4] drm-uapi/xe: Sync with DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition

[Dixit, Ashutosh]

On Thu, 04 Dec 2025 17:11:58 -0800, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> On Thu, Dec 04, 2025 at 04:05:25PM -0800, Ashutosh Dixit wrote:
> > Align with kernel commit 16e076b03658 ("drm/xe/oa/uapi: Add gt_id to struct
> > drm_xe_oa_unit") to bring in DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition.
> >
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
> Is the intention also to bring non-OA changes in this commit?

It's just a sync with kernel xe_drm.h at the commit (latest one) mentioned
above. So yes it will pull in all the changes till that commit.

> Then you may want to change the commit message to sync header file or
> something.

It already says sync. Otherwise I just titled the commit as the last change
that went into the header file. I think anything is ok, but if you or
anyone else has any suggestions, I will change the title to that one.

Also, if anyone else merges their changes to the header file first (I have
seen several pending merges on the mail list), this commit will change. But
it will always be a sync with the kernel header at the mentioned commit.

Thanks.
--
Ashutosh


> > ---
> > include/drm-uapi/xe_drm.h | 55 ++++++++++++++++++++++++++++++++++++---
> > 1 file changed, 51 insertions(+), 4 deletions(-)
> >
> > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
> > index 89ab549354..62e3221f59 100644
> > --- a/include/drm-uapi/xe_drm.h
> > +++ b/include/drm-uapi/xe_drm.h
> > @@ -210,8 +210,12 @@ struct drm_xe_ext_set_property {
> >	/** @pad: MBZ */
> >	__u32 pad;
> >
> > -	/** @value: property value */
> > -	__u64 value;
> > +	union {
> > +		/** @value: property value */
> > +		__u64 value;
> > +		/** @ptr: pointer to user value */
> > +		__u64 ptr;
> > +	};
> >
> >	/** @reserved: Reserved */
> >	__u64 reserved[2];
> > @@ -403,6 +407,9 @@ struct drm_xe_query_mem_regions {
> >  *      has low latency hint support
> >  *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
> >  *      device has CPU address mirroring support
> > + *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the
> > + *      device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION.
> > + *      This is exposed only on Xe2+.
> >  *  - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
> >  *    required by this device, typically SZ_4K or SZ_64K
> >  *  - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
> > @@ -421,6 +428,7 @@ struct drm_xe_query_config {
> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM	(1 << 0)
> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY	(1 << 1)
> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR	(1 << 2)
> > +	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3)
> > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT		2
> > #define DRM_XE_QUERY_CONFIG_VA_BITS			3
> > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY	4
> > @@ -771,7 +779,11 @@ struct drm_xe_device_query {
> >  *    until the object is either bound to a virtual memory region via
> >  *    VM_BIND or accessed by the CPU. As a result, no backing memory is
> >  *    reserved at the time of GEM object creation.
> > - *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
> > + *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is
> > + *    intended for scanout via the display engine. When set, kernel ensures
> > + *    that the allocation is placed in a memory region compatible with the
> > + *    display engine requirements. This may impose restrictions on tiling,
> > + *    alignment, and memory placement to guarantee proper display functionality.
> >  *  - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
> >  *    possible placement, ensure that the corresponding VRAM allocation
> >  *    will always use the CPU accessible part of VRAM. This is important
> > @@ -787,6 +799,17 @@ struct drm_xe_device_query {
> >  *    need to use VRAM for display surfaces, therefore the kernel requires
> >  *    setting this flag for such objects, otherwise an error is thrown on
> >  *    small-bar systems.
> > + *  - %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION - Allows userspace to
> > + *    hint that compression (CCS) should be disabled for the buffer being
> > + *    created. This can avoid unnecessary memory operations and CCS state
> > + *    management.
> > + *    On pre-Xe2 platforms, this flag is currently rejected as compression
> > + *    control is not supported via PAT index. On Xe2+ platforms, compression
> > + *    is controlled via PAT entries. If this flag is set, the driver will reject
> > + *    any VM bind that requests a PAT index enabling compression for this BO.
> > + *    Note: On dGPU platforms, there is currently no change in behavior with
> > + *    this flag, but future improvements may leverage it. The current benefit is
> > + *    primarily applicable to iGPU platforms.
> >  *
> >  * @cpu_caching supports the following values:
> >  *  - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
> > @@ -833,6 +856,7 @@ struct drm_xe_gem_create {
> > #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING		(1 << 0)
> > #define DRM_XE_GEM_CREATE_FLAG_SCANOUT			(1 << 1)
> > #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(1 << 2)
> > +#define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION		(1 << 3)
> >	/**
> >	 * @flags: Flags, currently a mask of memory instances of where BO can
> >	 * be placed
> > @@ -1013,6 +1037,20 @@ struct drm_xe_vm_destroy {
> >  *    valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
> >  *    mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
> >  *    handle MBZ, and the BO offset MBZ.
> > + *  - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
> > + *    %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying
> > + *    CPU address space range is unmapped (typically with munmap(2) or brk(2)).
> > + *    The madvise values set with &DRM_IOCTL_XE_MADVISE are reset to the values
> > + *    that were present immediately after the &DRM_IOCTL_XE_VM_BIND.
> > + *    The reset GPU virtual address range is the intersection of the range bound
> > + *    using &DRM_IOCTL_XE_VM_BIND and the virtual CPU address space range
> > + *    unmapped.
> > + *    This functionality is present to mimic the behaviour of CPU address space
> > + *    madvises set using madvise(2), which are typically reset on unmap.
> > + *    Note: free(3) may or may not call munmap(2) and/or brk(2), and may thus
> > + *    not invoke autoreset. Neither will stack variables going out of scope.
> > + *    Therefore it's recommended to always explicitly reset the madvises when
> > + *    freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call.
> >  *
> >  * The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be:
> >  *  - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
> > @@ -1119,6 +1157,7 @@ struct drm_xe_vm_bind_op {
> > #define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
> > #define DRM_XE_VM_BIND_FLAG_CHECK_PXP	(1 << 4)
> > #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR	(1 << 5)
> > +#define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET	(1 << 6)
> >	/** @flags: Bind flags */
> >	__u32 flags;
> >
> > @@ -1273,6 +1312,7 @@ struct drm_xe_exec_queue_create {
> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY		0
> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE		1
> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE		2
> > +#define   DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE		3
> >	/** @extensions: Pointer to the first extension struct, if any */
> >	__u64 extensions;
> >
> > @@ -1657,12 +1697,19 @@ struct drm_xe_oa_unit {
> > #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE	(1 << 2)
> > #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS	(1 << 3)
> > #define DRM_XE_OA_CAPS_OAM		(1 << 4)
> > +#define DRM_XE_OA_CAPS_OA_UNIT_GT_ID	(1 << 5)
> >
> >	/** @oa_timestamp_freq: OA timestamp freq */
> >	__u64 oa_timestamp_freq;
> >
> > +	/** @gt_id: gt id for this OA unit */
> > +	__u16 gt_id;
> > +
> > +	/** @reserved1: MBZ */
> > +	__u16 reserved1[3];
> > +
> >	/** @reserved: MBZ */
> > -	__u64 reserved[4];
> > +	__u64 reserved[3];
> >
> >	/** @num_engines: number of engines in @eci array */
> >	__u64 num_engines;
> > --
> > 2.48.1
> >

Re: [PATCH i-g-t 1/4] drm-uapi/xe: Sync with DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition

[Umesh Nerlige Ramappa]

On Thu, Dec 04, 2025 at 06:44:23PM -0800, Dixit, Ashutosh wrote:
>On Thu, 04 Dec 2025 17:11:58 -0800, Umesh Nerlige Ramappa wrote:
>>
>
>Hi Umesh,
>
>> On Thu, Dec 04, 2025 at 04:05:25PM -0800, Ashutosh Dixit wrote:
>> > Align with kernel commit 16e076b03658 ("drm/xe/oa/uapi: Add gt_id to struct
>> > drm_xe_oa_unit") to bring in DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition.
>> >
>> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>>
>> Is the intention also to bring non-OA changes in this commit?
>
>It's just a sync with kernel xe_drm.h at the commit (latest one) mentioned
>above. So yes it will pull in all the changes till that commit.
>
>> Then you may want to change the commit message to sync header file or
>> something.
>
>It already says sync. Otherwise I just titled the commit as the last change
>that went into the header file. I think anything is ok, but if you or
>anyone else has any suggestions, I will change the title to that one.
>
>Also, if anyone else merges their changes to the header file first (I have
>seen several pending merges on the mail list), this commit will change. But
>it will always be a sync with the kernel header at the mentioned commit.

I'd recommend - "Sync with kernel header".

With that,

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Thanks,
Umesh
>
>Thanks.
>--
>Ashutosh
>
>
>> > ---
>> > include/drm-uapi/xe_drm.h | 55 ++++++++++++++++++++++++++++++++++++---
>> > 1 file changed, 51 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
>> > index 89ab549354..62e3221f59 100644
>> > --- a/include/drm-uapi/xe_drm.h
>> > +++ b/include/drm-uapi/xe_drm.h
>> > @@ -210,8 +210,12 @@ struct drm_xe_ext_set_property {
>> >	/** @pad: MBZ */
>> >	__u32 pad;
>> >
>> > -	/** @value: property value */
>> > -	__u64 value;
>> > +	union {
>> > +		/** @value: property value */
>> > +		__u64 value;
>> > +		/** @ptr: pointer to user value */
>> > +		__u64 ptr;
>> > +	};
>> >
>> >	/** @reserved: Reserved */
>> >	__u64 reserved[2];
>> > @@ -403,6 +407,9 @@ struct drm_xe_query_mem_regions {
>> >  *      has low latency hint support
>> >  *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
>> >  *      device has CPU address mirroring support
>> > + *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the
>> > + *      device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION.
>> > + *      This is exposed only on Xe2+.
>> >  *  - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
>> >  *    required by this device, typically SZ_4K or SZ_64K
>> >  *  - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
>> > @@ -421,6 +428,7 @@ struct drm_xe_query_config {
>> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM	(1 << 0)
>> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY	(1 << 1)
>> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR	(1 << 2)
>> > +	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3)
>> > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT		2
>> > #define DRM_XE_QUERY_CONFIG_VA_BITS			3
>> > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY	4
>> > @@ -771,7 +779,11 @@ struct drm_xe_device_query {
>> >  *    until the object is either bound to a virtual memory region via
>> >  *    VM_BIND or accessed by the CPU. As a result, no backing memory is
>> >  *    reserved at the time of GEM object creation.
>> > - *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
>> > + *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is
>> > + *    intended for scanout via the display engine. When set, kernel ensures
>> > + *    that the allocation is placed in a memory region compatible with the
>> > + *    display engine requirements. This may impose restrictions on tiling,
>> > + *    alignment, and memory placement to guarantee proper display functionality.
>> >  *  - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
>> >  *    possible placement, ensure that the corresponding VRAM allocation
>> >  *    will always use the CPU accessible part of VRAM. This is important
>> > @@ -787,6 +799,17 @@ struct drm_xe_device_query {
>> >  *    need to use VRAM for display surfaces, therefore the kernel requires
>> >  *    setting this flag for such objects, otherwise an error is thrown on
>> >  *    small-bar systems.
>> > + *  - %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION - Allows userspace to
>> > + *    hint that compression (CCS) should be disabled for the buffer being
>> > + *    created. This can avoid unnecessary memory operations and CCS state
>> > + *    management.
>> > + *    On pre-Xe2 platforms, this flag is currently rejected as compression
>> > + *    control is not supported via PAT index. On Xe2+ platforms, compression
>> > + *    is controlled via PAT entries. If this flag is set, the driver will reject
>> > + *    any VM bind that requests a PAT index enabling compression for this BO.
>> > + *    Note: On dGPU platforms, there is currently no change in behavior with
>> > + *    this flag, but future improvements may leverage it. The current benefit is
>> > + *    primarily applicable to iGPU platforms.
>> >  *
>> >  * @cpu_caching supports the following values:
>> >  *  - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
>> > @@ -833,6 +856,7 @@ struct drm_xe_gem_create {
>> > #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING		(1 << 0)
>> > #define DRM_XE_GEM_CREATE_FLAG_SCANOUT			(1 << 1)
>> > #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(1 << 2)
>> > +#define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION		(1 << 3)
>> >	/**
>> >	 * @flags: Flags, currently a mask of memory instances of where BO can
>> >	 * be placed
>> > @@ -1013,6 +1037,20 @@ struct drm_xe_vm_destroy {
>> >  *    valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
>> >  *    mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
>> >  *    handle MBZ, and the BO offset MBZ.
>> > + *  - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
>> > + *    %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying
>> > + *    CPU address space range is unmapped (typically with munmap(2) or brk(2)).
>> > + *    The madvise values set with &DRM_IOCTL_XE_MADVISE are reset to the values
>> > + *    that were present immediately after the &DRM_IOCTL_XE_VM_BIND.
>> > + *    The reset GPU virtual address range is the intersection of the range bound
>> > + *    using &DRM_IOCTL_XE_VM_BIND and the virtual CPU address space range
>> > + *    unmapped.
>> > + *    This functionality is present to mimic the behaviour of CPU address space
>> > + *    madvises set using madvise(2), which are typically reset on unmap.
>> > + *    Note: free(3) may or may not call munmap(2) and/or brk(2), and may thus
>> > + *    not invoke autoreset. Neither will stack variables going out of scope.
>> > + *    Therefore it's recommended to always explicitly reset the madvises when
>> > + *    freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call.
>> >  *
>> >  * The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be:
>> >  *  - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
>> > @@ -1119,6 +1157,7 @@ struct drm_xe_vm_bind_op {
>> > #define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
>> > #define DRM_XE_VM_BIND_FLAG_CHECK_PXP	(1 << 4)
>> > #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR	(1 << 5)
>> > +#define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET	(1 << 6)
>> >	/** @flags: Bind flags */
>> >	__u32 flags;
>> >
>> > @@ -1273,6 +1312,7 @@ struct drm_xe_exec_queue_create {
>> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY		0
>> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE		1
>> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE		2
>> > +#define   DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE		3
>> >	/** @extensions: Pointer to the first extension struct, if any */
>> >	__u64 extensions;
>> >
>> > @@ -1657,12 +1697,19 @@ struct drm_xe_oa_unit {
>> > #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE	(1 << 2)
>> > #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS	(1 << 3)
>> > #define DRM_XE_OA_CAPS_OAM		(1 << 4)
>> > +#define DRM_XE_OA_CAPS_OA_UNIT_GT_ID	(1 << 5)
>> >
>> >	/** @oa_timestamp_freq: OA timestamp freq */
>> >	__u64 oa_timestamp_freq;
>> >
>> > +	/** @gt_id: gt id for this OA unit */
>> > +	__u16 gt_id;
>> > +
>> > +	/** @reserved1: MBZ */
>> > +	__u16 reserved1[3];
>> > +
>> >	/** @reserved: MBZ */
>> > -	__u64 reserved[4];
>> > +	__u64 reserved[3];
>> >
>> >	/** @num_engines: number of engines in @eci array */
>> >	__u64 num_engines;
>> > --
>> > 2.48.1
>> >

Re: [PATCH i-g-t 1/4] drm-uapi/xe: Sync with DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition

[Dixit, Ashutosh]

On Fri, 05 Dec 2025 12:21:48 -0800, Umesh Nerlige Ramappa wrote:
>
> On Thu, Dec 04, 2025 at 06:44:23PM -0800, Dixit, Ashutosh wrote:
> > On Thu, 04 Dec 2025 17:11:58 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >
> > Hi Umesh,
> >
> >> On Thu, Dec 04, 2025 at 04:05:25PM -0800, Ashutosh Dixit wrote:
> >> > Align with kernel commit 16e076b03658 ("drm/xe/oa/uapi: Add gt_id to struct
> >> > drm_xe_oa_unit") to bring in DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition.
> >> >
> >> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >>
> >> Is the intention also to bring non-OA changes in this commit?
> >
> > It's just a sync with kernel xe_drm.h at the commit (latest one) mentioned
> > above. So yes it will pull in all the changes till that commit.
> >
> >> Then you may want to change the commit message to sync header file or
> >> something.
> >
> > It already says sync. Otherwise I just titled the commit as the last change
> > that went into the header file. I think anything is ok, but if you or
> > anyone else has any suggestions, I will change the title to that one.
> >
> > Also, if anyone else merges their changes to the header file first (I have
> > seen several pending merges on the mail list), this commit will change. But
> > it will always be a sync with the kernel header at the mentioned commit.
>
> I'd recommend - "Sync with kernel header".

Hmm, it already says "drm-uapi/xe". See other commit titles for the
file. So we need some more indication on what we are adding in the commit
title.

>
> With that,
>
> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>
> Thanks,
> Umesh
> >
> > Thanks.
> > --
> > Ashutosh
> >
> >
> >> > ---
> >> > include/drm-uapi/xe_drm.h | 55 ++++++++++++++++++++++++++++++++++++---
> >> > 1 file changed, 51 insertions(+), 4 deletions(-)
> >> >
> >> > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
> >> > index 89ab549354..62e3221f59 100644
> >> > --- a/include/drm-uapi/xe_drm.h
> >> > +++ b/include/drm-uapi/xe_drm.h
> >> > @@ -210,8 +210,12 @@ struct drm_xe_ext_set_property {
> >> >	/** @pad: MBZ */
> >> >	__u32 pad;
> >> >
> >> > -	/** @value: property value */
> >> > -	__u64 value;
> >> > +	union {
> >> > +		/** @value: property value */
> >> > +		__u64 value;
> >> > +		/** @ptr: pointer to user value */
> >> > +		__u64 ptr;
> >> > +	};
> >> >
> >> >	/** @reserved: Reserved */
> >> >	__u64 reserved[2];
> >> > @@ -403,6 +407,9 @@ struct drm_xe_query_mem_regions {
> >> >  *      has low latency hint support
> >> >  *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
> >> >  *      device has CPU address mirroring support
> >> > + *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the
> >> > + *      device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION.
> >> > + *      This is exposed only on Xe2+.
> >> >  *  - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
> >> >  *    required by this device, typically SZ_4K or SZ_64K
> >> >  *  - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
> >> > @@ -421,6 +428,7 @@ struct drm_xe_query_config {
> >> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM	(1 << 0)
> >> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY	(1 << 1)
> >> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR	(1 << 2)
> >> > +	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3)
> >> > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT		2
> >> > #define DRM_XE_QUERY_CONFIG_VA_BITS			3
> >> > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY	4
> >> > @@ -771,7 +779,11 @@ struct drm_xe_device_query {
> >> >  *    until the object is either bound to a virtual memory region via
> >> >  *    VM_BIND or accessed by the CPU. As a result, no backing memory is
> >> >  *    reserved at the time of GEM object creation.
> >> > - *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
> >> > + *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is
> >> > + *    intended for scanout via the display engine. When set, kernel ensures
> >> > + *    that the allocation is placed in a memory region compatible with the
> >> > + *    display engine requirements. This may impose restrictions on tiling,
> >> > + *    alignment, and memory placement to guarantee proper display functionality.
> >> >  *  - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
> >> >  *    possible placement, ensure that the corresponding VRAM allocation
> >> >  *    will always use the CPU accessible part of VRAM. This is important
> >> > @@ -787,6 +799,17 @@ struct drm_xe_device_query {
> >> >  *    need to use VRAM for display surfaces, therefore the kernel requires
> >> >  *    setting this flag for such objects, otherwise an error is thrown on
> >> >  *    small-bar systems.
> >> > + *  - %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION - Allows userspace to
> >> > + *    hint that compression (CCS) should be disabled for the buffer being
> >> > + *    created. This can avoid unnecessary memory operations and CCS state
> >> > + *    management.
> >> > + *    On pre-Xe2 platforms, this flag is currently rejected as compression
> >> > + *    control is not supported via PAT index. On Xe2+ platforms, compression
> >> > + *    is controlled via PAT entries. If this flag is set, the driver will reject
> >> > + *    any VM bind that requests a PAT index enabling compression for this BO.
> >> > + *    Note: On dGPU platforms, there is currently no change in behavior with
> >> > + *    this flag, but future improvements may leverage it. The current benefit is
> >> > + *    primarily applicable to iGPU platforms.
> >> >  *
> >> >  * @cpu_caching supports the following values:
> >> >  *  - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
> >> > @@ -833,6 +856,7 @@ struct drm_xe_gem_create {
> >> > #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING		(1 << 0)
> >> > #define DRM_XE_GEM_CREATE_FLAG_SCANOUT			(1 << 1)
> >> > #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(1 << 2)
> >> > +#define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION		(1 << 3)
> >> >	/**
> >> >	 * @flags: Flags, currently a mask of memory instances of where BO can
> >> >	 * be placed
> >> > @@ -1013,6 +1037,20 @@ struct drm_xe_vm_destroy {
> >> >  *    valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
> >> >  *    mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
> >> >  *    handle MBZ, and the BO offset MBZ.
> >> > + *  - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
> >> > + *    %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying
> >> > + *    CPU address space range is unmapped (typically with munmap(2) or brk(2)).
> >> > + *    The madvise values set with &DRM_IOCTL_XE_MADVISE are reset to the values
> >> > + *    that were present immediately after the &DRM_IOCTL_XE_VM_BIND.
> >> > + *    The reset GPU virtual address range is the intersection of the range bound
> >> > + *    using &DRM_IOCTL_XE_VM_BIND and the virtual CPU address space range
> >> > + *    unmapped.
> >> > + *    This functionality is present to mimic the behaviour of CPU address space
> >> > + *    madvises set using madvise(2), which are typically reset on unmap.
> >> > + *    Note: free(3) may or may not call munmap(2) and/or brk(2), and may thus
> >> > + *    not invoke autoreset. Neither will stack variables going out of scope.
> >> > + *    Therefore it's recommended to always explicitly reset the madvises when
> >> > + *    freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call.
> >> >  *
> >> >  * The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be:
> >> >  *  - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
> >> > @@ -1119,6 +1157,7 @@ struct drm_xe_vm_bind_op {
> >> > #define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
> >> > #define DRM_XE_VM_BIND_FLAG_CHECK_PXP	(1 << 4)
> >> > #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR	(1 << 5)
> >> > +#define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET	(1 << 6)
> >> >	/** @flags: Bind flags */
> >> >	__u32 flags;
> >> >
> >> > @@ -1273,6 +1312,7 @@ struct drm_xe_exec_queue_create {
> >> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY		0
> >> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE		1
> >> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE		2
> >> > +#define   DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE		3
> >> >	/** @extensions: Pointer to the first extension struct, if any */
> >> >	__u64 extensions;
> >> >
> >> > @@ -1657,12 +1697,19 @@ struct drm_xe_oa_unit {
> >> > #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE	(1 << 2)
> >> > #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS	(1 << 3)
> >> > #define DRM_XE_OA_CAPS_OAM		(1 << 4)
> >> > +#define DRM_XE_OA_CAPS_OA_UNIT_GT_ID	(1 << 5)
> >> >
> >> >	/** @oa_timestamp_freq: OA timestamp freq */
> >> >	__u64 oa_timestamp_freq;
> >> >
> >> > +	/** @gt_id: gt id for this OA unit */
> >> > +	__u16 gt_id;
> >> > +
> >> > +	/** @reserved1: MBZ */
> >> > +	__u16 reserved1[3];
> >> > +
> >> >	/** @reserved: MBZ */
> >> > -	__u64 reserved[4];
> >> > +	__u64 reserved[3];
> >> >
> >> >	/** @num_engines: number of engines in @eci array */
> >> >	__u64 num_engines;
> >> > --
> >> > 2.48.1
> >> >

Re: [PATCH i-g-t 1/4] drm-uapi/xe: Sync with DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition

[Umesh Nerlige Ramappa]

On Fri, Dec 05, 2025 at 12:28:54PM -0800, Dixit, Ashutosh wrote:
>On Fri, 05 Dec 2025 12:21:48 -0800, Umesh Nerlige Ramappa wrote:
>>
>> On Thu, Dec 04, 2025 at 06:44:23PM -0800, Dixit, Ashutosh wrote:
>> > On Thu, 04 Dec 2025 17:11:58 -0800, Umesh Nerlige Ramappa wrote:
>> >>
>> >
>> > Hi Umesh,
>> >
>> >> On Thu, Dec 04, 2025 at 04:05:25PM -0800, Ashutosh Dixit wrote:
>> >> > Align with kernel commit 16e076b03658 ("drm/xe/oa/uapi: Add gt_id to struct
>> >> > drm_xe_oa_unit") to bring in DRM_XE_OA_CAPS_OA_UNIT_GT_ID definition.
>> >> >
>> >> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>> >>
>> >> Is the intention also to bring non-OA changes in this commit?
>> >
>> > It's just a sync with kernel xe_drm.h at the commit (latest one) mentioned
>> > above. So yes it will pull in all the changes till that commit.
>> >
>> >> Then you may want to change the commit message to sync header file or
>> >> something.
>> >
>> > It already says sync. Otherwise I just titled the commit as the last change
>> > that went into the header file. I think anything is ok, but if you or
>> > anyone else has any suggestions, I will change the title to that one.
>> >
>> > Also, if anyone else merges their changes to the header file first (I have
>> > seen several pending merges on the mail list), this commit will change. But
>> > it will always be a sync with the kernel header at the mentioned commit.
>>
>> I'd recommend - "Sync with kernel header".
>
>Hmm, it already says "drm-uapi/xe". See other commit titles for the
>file. So we need some more indication on what we are adding in the commit
>title.

I see, you can keep it as is for now, if I can think of a better way, 
will share.

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh


>
>>
>> With that,
>>
>> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>
>> Thanks,
>> Umesh
>> >
>> > Thanks.
>> > --
>> > Ashutosh
>> >
>> >
>> >> > ---
>> >> > include/drm-uapi/xe_drm.h | 55 ++++++++++++++++++++++++++++++++++++---
>> >> > 1 file changed, 51 insertions(+), 4 deletions(-)
>> >> >
>> >> > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
>> >> > index 89ab549354..62e3221f59 100644
>> >> > --- a/include/drm-uapi/xe_drm.h
>> >> > +++ b/include/drm-uapi/xe_drm.h
>> >> > @@ -210,8 +210,12 @@ struct drm_xe_ext_set_property {
>> >> >	/** @pad: MBZ */
>> >> >	__u32 pad;
>> >> >
>> >> > -	/** @value: property value */
>> >> > -	__u64 value;
>> >> > +	union {
>> >> > +		/** @value: property value */
>> >> > +		__u64 value;
>> >> > +		/** @ptr: pointer to user value */
>> >> > +		__u64 ptr;
>> >> > +	};
>> >> >
>> >> >	/** @reserved: Reserved */
>> >> >	__u64 reserved[2];
>> >> > @@ -403,6 +407,9 @@ struct drm_xe_query_mem_regions {
>> >> >  *      has low latency hint support
>> >> >  *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
>> >> >  *      device has CPU address mirroring support
>> >> > + *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the
>> >> > + *      device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION.
>> >> > + *      This is exposed only on Xe2+.
>> >> >  *  - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
>> >> >  *    required by this device, typically SZ_4K or SZ_64K
>> >> >  *  - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
>> >> > @@ -421,6 +428,7 @@ struct drm_xe_query_config {
>> >> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM	(1 << 0)
>> >> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY	(1 << 1)
>> >> >	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR	(1 << 2)
>> >> > +	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3)
>> >> > #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT		2
>> >> > #define DRM_XE_QUERY_CONFIG_VA_BITS			3
>> >> > #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY	4
>> >> > @@ -771,7 +779,11 @@ struct drm_xe_device_query {
>> >> >  *    until the object is either bound to a virtual memory region via
>> >> >  *    VM_BIND or accessed by the CPU. As a result, no backing memory is
>> >> >  *    reserved at the time of GEM object creation.
>> >> > - *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
>> >> > + *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is
>> >> > + *    intended for scanout via the display engine. When set, kernel ensures
>> >> > + *    that the allocation is placed in a memory region compatible with the
>> >> > + *    display engine requirements. This may impose restrictions on tiling,
>> >> > + *    alignment, and memory placement to guarantee proper display functionality.
>> >> >  *  - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
>> >> >  *    possible placement, ensure that the corresponding VRAM allocation
>> >> >  *    will always use the CPU accessible part of VRAM. This is important
>> >> > @@ -787,6 +799,17 @@ struct drm_xe_device_query {
>> >> >  *    need to use VRAM for display surfaces, therefore the kernel requires
>> >> >  *    setting this flag for such objects, otherwise an error is thrown on
>> >> >  *    small-bar systems.
>> >> > + *  - %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION - Allows userspace to
>> >> > + *    hint that compression (CCS) should be disabled for the buffer being
>> >> > + *    created. This can avoid unnecessary memory operations and CCS state
>> >> > + *    management.
>> >> > + *    On pre-Xe2 platforms, this flag is currently rejected as compression
>> >> > + *    control is not supported via PAT index. On Xe2+ platforms, compression
>> >> > + *    is controlled via PAT entries. If this flag is set, the driver will reject
>> >> > + *    any VM bind that requests a PAT index enabling compression for this BO.
>> >> > + *    Note: On dGPU platforms, there is currently no change in behavior with
>> >> > + *    this flag, but future improvements may leverage it. The current benefit is
>> >> > + *    primarily applicable to iGPU platforms.
>> >> >  *
>> >> >  * @cpu_caching supports the following values:
>> >> >  *  - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
>> >> > @@ -833,6 +856,7 @@ struct drm_xe_gem_create {
>> >> > #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING		(1 << 0)
>> >> > #define DRM_XE_GEM_CREATE_FLAG_SCANOUT			(1 << 1)
>> >> > #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(1 << 2)
>> >> > +#define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION		(1 << 3)
>> >> >	/**
>> >> >	 * @flags: Flags, currently a mask of memory instances of where BO can
>> >> >	 * be placed
>> >> > @@ -1013,6 +1037,20 @@ struct drm_xe_vm_destroy {
>> >> >  *    valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
>> >> >  *    mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
>> >> >  *    handle MBZ, and the BO offset MBZ.
>> >> > + *  - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
>> >> > + *    %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying
>> >> > + *    CPU address space range is unmapped (typically with munmap(2) or brk(2)).
>> >> > + *    The madvise values set with &DRM_IOCTL_XE_MADVISE are reset to the values
>> >> > + *    that were present immediately after the &DRM_IOCTL_XE_VM_BIND.
>> >> > + *    The reset GPU virtual address range is the intersection of the range bound
>> >> > + *    using &DRM_IOCTL_XE_VM_BIND and the virtual CPU address space range
>> >> > + *    unmapped.
>> >> > + *    This functionality is present to mimic the behaviour of CPU address space
>> >> > + *    madvises set using madvise(2), which are typically reset on unmap.
>> >> > + *    Note: free(3) may or may not call munmap(2) and/or brk(2), and may thus
>> >> > + *    not invoke autoreset. Neither will stack variables going out of scope.
>> >> > + *    Therefore it's recommended to always explicitly reset the madvises when
>> >> > + *    freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call.
>> >> >  *
>> >> >  * The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be:
>> >> >  *  - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
>> >> > @@ -1119,6 +1157,7 @@ struct drm_xe_vm_bind_op {
>> >> > #define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
>> >> > #define DRM_XE_VM_BIND_FLAG_CHECK_PXP	(1 << 4)
>> >> > #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR	(1 << 5)
>> >> > +#define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET	(1 << 6)
>> >> >	/** @flags: Bind flags */
>> >> >	__u32 flags;
>> >> >
>> >> > @@ -1273,6 +1312,7 @@ struct drm_xe_exec_queue_create {
>> >> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY		0
>> >> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE		1
>> >> > #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE		2
>> >> > +#define   DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE		3
>> >> >	/** @extensions: Pointer to the first extension struct, if any */
>> >> >	__u64 extensions;
>> >> >
>> >> > @@ -1657,12 +1697,19 @@ struct drm_xe_oa_unit {
>> >> > #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE	(1 << 2)
>> >> > #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS	(1 << 3)
>> >> > #define DRM_XE_OA_CAPS_OAM		(1 << 4)
>> >> > +#define DRM_XE_OA_CAPS_OA_UNIT_GT_ID	(1 << 5)
>> >> >
>> >> >	/** @oa_timestamp_freq: OA timestamp freq */
>> >> >	__u64 oa_timestamp_freq;
>> >> >
>> >> > +	/** @gt_id: gt id for this OA unit */
>> >> > +	__u16 gt_id;
>> >> > +
>> >> > +	/** @reserved1: MBZ */
>> >> > +	__u16 reserved1[3];
>> >> > +
>> >> >	/** @reserved: MBZ */
>> >> > -	__u64 reserved[4];
>> >> > +	__u64 reserved[3];
>> >> >
>> >> >	/** @num_engines: number of engines in @eci array */
>> >> >	__u64 num_engines;
>> >> > --
>> >> > 2.48.1
>> >> >

[PATCH i-g-t 2/4] tests/intel/xe_oa: Return hwe from same gt from oa_unit_engine()

[Ashutosh Dixit]

For some tests (e.g. mmio trigger) a hwe (and exec_queue) is needed for
batch submissions, even when the OA unit does not have any attached
hwe's (e.g. OAM SAG). To enable such use cases, return a hwe from the same
gt when an OA unit has no attached engines.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/intel/xe_oa.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 9302d1c83a..c8475720c5 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -486,7 +486,22 @@ static u64 oa_format_fields(u64 name)
 
 static const struct drm_xe_engine_class_instance *oa_unit_engine(const struct drm_xe_oa_unit *oau)
 {
-	return !oau ? NULL : oau->num_engines ? &oau->eci[random() % oau->num_engines] : NULL;
+	const struct drm_xe_engine_class_instance *hwe;
+
+	igt_assert(oau);
+
+	hwe = oau->num_engines ? &oau->eci[random() % oau->num_engines] : NULL;
+
+	/* If an OA unit has no hwe's, return a hwe from the same gt */
+	if (hwe || !(oau->capabilities & DRM_XE_OA_CAPS_OA_UNIT_GT_ID))
+		goto exit;
+
+	xe_for_each_engine(drm_fd, hwe)
+		if (hwe->gt_id == oau->gt_id)
+			break;
+	igt_assert(hwe);
+exit:
+	return hwe;
 }
 
 static int __first_and_num_oa_units(const struct drm_xe_oa_unit **oau)
-- 
2.48.1

Re: [PATCH i-g-t 2/4] tests/intel/xe_oa: Return hwe from same gt from oa_unit_engine()

[Umesh Nerlige Ramappa]

On Thu, Dec 04, 2025 at 04:05:26PM -0800, Ashutosh Dixit wrote:
>For some tests (e.g. mmio trigger) a hwe (and exec_queue) is needed for
>batch submissions, even when the OA unit does not have any attached
>hwe's (e.g. OAM SAG). To enable such use cases, return a hwe from the same
>gt when an OA unit has no attached engines.
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Assuming the gt->ids are intentionally populated by the KMD, this should 
return an engine from the corresponding gt for units that do not have 
any assigned engines.

LGTM

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

>---
> tests/intel/xe_oa.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
>diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>index 9302d1c83a..c8475720c5 100644
>--- a/tests/intel/xe_oa.c
>+++ b/tests/intel/xe_oa.c
>@@ -486,7 +486,22 @@ static u64 oa_format_fields(u64 name)
>
> static const struct drm_xe_engine_class_instance *oa_unit_engine(const struct drm_xe_oa_unit *oau)
> {
>-	return !oau ? NULL : oau->num_engines ? &oau->eci[random() % oau->num_engines] : NULL;
>+	const struct drm_xe_engine_class_instance *hwe;
>+
>+	igt_assert(oau);
>+
>+	hwe = oau->num_engines ? &oau->eci[random() % oau->num_engines] : NULL;
>+
>+	/* If an OA unit has no hwe's, return a hwe from the same gt */
>+	if (hwe || !(oau->capabilities & DRM_XE_OA_CAPS_OA_UNIT_GT_ID))
>+		goto exit;
>+
>+	xe_for_each_engine(drm_fd, hwe)
>+		if (hwe->gt_id == oau->gt_id)
>+			break;
>+	igt_assert(hwe);
>+exit:
>+	return hwe;
> }
>
> static int __first_and_num_oa_units(const struct drm_xe_oa_unit **oau)
>-- 
>2.48.1
>

[PATCH i-g-t 3/4] tests/intel/xe_oa: Run mmio-trigger tests on all OA units

[Ashutosh Dixit]

Expand mmio-trigger tests to all OA units (rather than just OAG unit).

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 102 +++++++++++++++++++++++++++++++++++++-------
 1 file changed, 87 insertions(+), 15 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index c8475720c5..2f966e808f 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -73,9 +73,7 @@
 
 #define OAG_OASTATUS (0xdafc)
 #define OAG_PERF_COUNTER_B(idx) (0xDA94 + 4 * (idx))
-#define OAG_OATAILPTR (0xdb04)
 #define OAG_OATAILPTR_MASK 0xffffffc0
-#define OAG_OABUFFER (0xdb08)
 
 #define XE_OA_MAX_SET_PROPERTIES 16
 
@@ -93,6 +91,24 @@ struct accumulator {
 	uint64_t deltas[MAX_RAW_OA_COUNTERS];
 };
 
+#define MEDIA_GT_GSI_OFFSET		0x380000
+#define XE_OAM_SAG_BASE_ADJ		(MEDIA_GT_GSI_OFFSET + 0x13000)
+#define XE_OAM_SCMI_0_BASE_ADJ		(MEDIA_GT_GSI_OFFSET + 0x14000)
+#define XE_OAM_SCMI_1_BASE_ADJ		(MEDIA_GT_GSI_OFFSET + 0x14800)
+
+/** struct xe_oa_regs - Registers for each OA unit */
+struct xe_oa_regs {
+	u32 base;
+	u32 oa_head_ptr;
+	u32 oa_tail_ptr;
+	u32 oa_buffer;
+	u32 oa_ctx_ctrl;
+	u32 oa_ctrl;
+	u32 oa_debug;
+	u32 oa_status;
+	u32 oa_mmio_trg;
+};
+
 struct oa_buf_size {
 	char name[12];
 	uint32_t size;
@@ -3901,10 +3917,10 @@ emit_oa_reg_read(struct intel_bb *ibb, struct intel_buf *dst, uint32_t offset,
 }
 
 static void
-emit_mmio_triggered_report(struct intel_bb *ibb, uint32_t value)
+emit_mmio_triggered_report(struct intel_bb *ibb, uint32_t reg, uint32_t value)
 {
 	intel_bb_out(ibb, MI_LOAD_REGISTER_IMM(1));
-	intel_bb_out(ibb, OAG_MMIOTRIGGER);
+	intel_bb_out(ibb, reg);
 	intel_bb_out(ibb, value);
 }
 
@@ -3979,6 +3995,58 @@ static u32 oa_get_mmio_base(const struct drm_xe_engine_class_instance *hwe)
 	return mmio_base;
 }
 
+/* For register mmio offsets look at drivers/gpu/drm/xe/regs/xe_oa_regs.h in the kernel */
+static struct xe_oa_regs __oag_regs(void)
+{
+	return (struct xe_oa_regs) {
+		.base		= 0,
+		.oa_head_ptr	= 0xdb00,
+		.oa_tail_ptr	= 0xdb04,
+		.oa_buffer	= 0xdb08,
+		.oa_ctx_ctrl	= 0x2b28,
+		.oa_ctrl	= 0xdaf4,
+		.oa_debug	= 0xdaf8,
+		.oa_status	= 0xdafc,
+		.oa_mmio_trg	= 0xdb1c,
+	};
+}
+
+static struct xe_oa_regs __oam_regs(u32 base)
+{
+	return (struct xe_oa_regs) {
+		.base		= base,
+		.oa_head_ptr	= base + 0x1a0,
+		.oa_tail_ptr	= base + 0x1a4,
+		.oa_buffer	= base + 0x1a8,
+		.oa_ctx_ctrl	= base + 0x1bc,
+		.oa_ctrl	= base + 0x194,
+		.oa_debug	= base + 0x198,
+		.oa_status	= base + 0x19c,
+		.oa_mmio_trg	= base + 0x1d0,
+	};
+}
+
+static struct xe_oa_regs oa_unit_regs(const struct drm_xe_oa_unit *oau)
+{
+	switch (oau->oa_unit_type) {
+	case DRM_XE_OA_UNIT_TYPE_OAM: {
+		const struct drm_xe_oa_unit *first_oam_unit =
+			oa_unit_by_type(drm_fd, DRM_XE_OA_UNIT_TYPE_OAM);
+
+		igt_assert(first_oam_unit);
+		if (oau->oa_unit_id == first_oam_unit->oa_unit_id)
+			return __oam_regs(XE_OAM_SCMI_0_BASE_ADJ);
+		else
+			return __oam_regs(XE_OAM_SCMI_1_BASE_ADJ);
+	}
+	case DRM_XE_OA_UNIT_TYPE_OAM_SAG:
+		return __oam_regs(XE_OAM_SAG_BASE_ADJ);
+	case DRM_XE_OA_UNIT_TYPE_OAG:
+	default:
+		return __oag_regs();
+	}
+}
+
 /**
  * SUBTEST: oa-regs-whitelisted
  * Description: Verify that OA registers are whitelisted
@@ -4034,6 +4102,7 @@ __test_mmio_triggered_reports(const struct drm_xe_oa_unit *oau)
 {
 	struct intel_xe_perf_metric_set *test_set = oa_unit_metric_set(oau);
 	const struct drm_xe_engine_class_instance *hwe = oa_unit_engine(oau);
+	struct xe_oa_regs regs = oa_unit_regs(oau);
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, oau->oa_unit_id,
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
@@ -4078,18 +4147,18 @@ __test_mmio_triggered_reports(const struct drm_xe_oa_unit *oau)
 	buf = mmap(0, default_oa_buffer_size, PROT_READ, MAP_PRIVATE, stream_fd, 0);
 	igt_assert(buf != NULL);
 
-	emit_oa_reg_read(ibb, dst_buf, 0, OAG_OABUFFER);
-	emit_oa_reg_read(ibb, dst_buf, 4, OAG_OATAILPTR);
-	emit_mmio_triggered_report(ibb, 0xc0ffee11);
+	emit_oa_reg_read(ibb, dst_buf, 0, regs.oa_buffer);
+	emit_oa_reg_read(ibb, dst_buf, 4, regs.oa_tail_ptr);
+	emit_mmio_triggered_report(ibb, regs.oa_mmio_trg, 0xc0ffee11);
 
-	if (render_copy)
+	if (render_copy && oau->oa_unit_type == DRM_XE_OA_UNIT_TYPE_OAG)
 		render_copy(ibb,
 			    &src, 0, 0, rc_width, rc_height,
 			    &dst, 0, 0);
 
-	emit_mmio_triggered_report(ibb, 0xc0ffee22);
+	emit_mmio_triggered_report(ibb, regs.oa_mmio_trg, 0xc0ffee22);
 
-	emit_oa_reg_read(ibb, dst_buf, 8, OAG_OATAILPTR);
+	emit_oa_reg_read(ibb, dst_buf, 8, regs.oa_tail_ptr);
 
 	intel_bb_flush_render(ibb);
 	intel_bb_sync(ibb);
@@ -4141,6 +4210,7 @@ __test_mmio_triggered_reports_read(const struct drm_xe_oa_unit *oau)
 {
 	struct intel_xe_perf_metric_set *test_set = oa_unit_metric_set(oau);
 	const struct drm_xe_engine_class_instance *hwe = oa_unit_engine(oau);
+	struct xe_oa_regs regs = oa_unit_regs(oau);
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, oau->oa_unit_id,
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
@@ -4174,14 +4244,14 @@ __test_mmio_triggered_reports_read(const struct drm_xe_oa_unit *oau)
 	stream_fd = __perf_open(drm_fd, &param, false);
 	set_fd_flags(stream_fd, O_CLOEXEC);
 
-	emit_mmio_triggered_report(ibb, 0xc0ffee11);
+	emit_mmio_triggered_report(ibb, regs.oa_mmio_trg, 0xc0ffee11);
 
-	if (render_copy)
+	if (render_copy && oau->oa_unit_type == DRM_XE_OA_UNIT_TYPE_OAG)
 		render_copy(ibb,
 			    &src, 0, 0, rc_width, rc_height,
 			    &dst, 0, 0);
 
-	emit_mmio_triggered_report(ibb, 0xc0ffee22);
+	emit_mmio_triggered_report(ibb, regs.oa_mmio_trg, 0xc0ffee22);
 
 	intel_bb_flush_render(ibb);
 	intel_bb_sync(ibb);
@@ -5195,13 +5265,15 @@ igt_main_args("b:t", long_options, help_str, opt_handler, NULL)
 
 		igt_subtest_with_dynamic("mmio-triggered-reports") {
 			igt_require(HAS_OA_MMIO_TRIGGER(devid));
-			__for_oa_unit_by_type(DRM_XE_OA_UNIT_TYPE_OAG)
+			igt_require(oau->capabilities & DRM_XE_OA_CAPS_OA_UNIT_GT_ID);
+			__for_each_oa_unit(oau)
 				test_mmio_triggered_reports(oau, false);
 		}
 
 		igt_subtest_with_dynamic("mmio-triggered-reports-read") {
 			igt_require(HAS_OA_MMIO_TRIGGER(devid));
-			__for_oa_unit_by_type(DRM_XE_OA_UNIT_TYPE_OAG)
+			igt_require(oau->capabilities & DRM_XE_OA_CAPS_OA_UNIT_GT_ID);
+			__for_each_oa_unit(oau)
 				test_mmio_triggered_reports(oau, true);
 		}
 	}
-- 
2.48.1

[PATCH i-g-t 4/4] tests/intel/xe_oa: Use separate oa unit variables for caps and iterator

[Ashutosh Dixit]

The __for_each_oa_unit() iterator places the oau pointer at the end of the
oa unit array. If the iterator is followed by 'oau->capabilities' check,
'oau->capabilities' is undefined after the end of the oa unit array. To
resolve this situation use separate oa unit variables for checking the
caps and for the iterator.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 2f966e808f..502fa47323 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -5031,7 +5031,7 @@ igt_main_args("b:t", long_options, help_str, opt_handler, NULL)
 		{ "ufence-wait", OA_SYNC_TYPE_UFENCE, WAIT },
 		{ NULL },
 	};
-	const struct drm_xe_oa_unit *oau;
+	const struct drm_xe_oa_unit *oau0, *oau;
 	struct xe_device *xe_dev;
 
 	igt_fixture {
@@ -5063,7 +5063,7 @@ igt_main_args("b:t", long_options, help_str, opt_handler, NULL)
 		/* See xe_query_oa_units_new() */
 		igt_require(xe_dev->oa_units);
 		igt_require(xe_dev->oa_units->num_oa_units);
-		oau = oa_unit_by_id(drm_fd, 0);
+		oau0 = oa_unit_by_id(drm_fd, 0);
 
 		devid = intel_get_drm_devid(drm_fd);
 		sysfs = igt_sysfs_open(drm_fd);
@@ -5102,7 +5102,7 @@ igt_main_args("b:t", long_options, help_str, opt_handler, NULL)
 			test_oa_exponents(oau);
 
 	igt_subtest_with_dynamic("buffer-fill") {
-		igt_require(oau->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE);
+		igt_require(oau0->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE);
 		__for_oa_unit_by_type(DRM_XE_OA_UNIT_TYPE_OAG)
 			test_buffer_fill(oau);
 	}
@@ -5114,14 +5114,14 @@ igt_main_args("b:t", long_options, help_str, opt_handler, NULL)
 	igt_subtest_with_dynamic("buffer-size") {
 		long k = random() % num_buf_sizes;
 
-		igt_require(oau->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE);
+		igt_require(oau0->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE);
 		__for_oa_unit_by_type_w_arg(DRM_XE_OA_UNIT_TYPE_OAG, buf_sizes[k].name)
 			test_non_zero_reason(oau, buf_sizes[k].size);
 	}
 
 	igt_subtest_with_dynamic("non-zero-reason") {
 		igt_require(!igt_run_in_simulation());
-		igt_require(oau->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE);
+		igt_require(oau0->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE);
 		__for_oa_unit_by_type(DRM_XE_OA_UNIT_TYPE_OAG)
 			test_non_zero_reason(oau, 0);
 	}
@@ -5131,7 +5131,7 @@ igt_main_args("b:t", long_options, help_str, opt_handler, NULL)
 	 * Description: Non zero reason over all OA units
 	 */
 	igt_subtest_with_dynamic("non-zero-reason-all") {
-		igt_require(oau->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE);
+		igt_require(oau0->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE);
 		__for_each_oa_unit(oau)
 			test_non_zero_reason(oau, SZ_128K);
 	}
@@ -5249,7 +5249,7 @@ igt_main_args("b:t", long_options, help_str, opt_handler, NULL)
 	igt_subtest_with_dynamic("tail-address-wrap") {
 		long k = random() % num_buf_sizes;
 
-		igt_require(oau->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE);
+		igt_require(oau0->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE);
 		__for_oa_unit_by_type_w_arg(DRM_XE_OA_UNIT_TYPE_OAG, buf_sizes[k].name)
 			test_tail_address_wrap(oau, buf_sizes[k].size);
 	}
@@ -5265,14 +5265,14 @@ igt_main_args("b:t", long_options, help_str, opt_handler, NULL)
 
 		igt_subtest_with_dynamic("mmio-triggered-reports") {
 			igt_require(HAS_OA_MMIO_TRIGGER(devid));
-			igt_require(oau->capabilities & DRM_XE_OA_CAPS_OA_UNIT_GT_ID);
+			igt_require(oau0->capabilities & DRM_XE_OA_CAPS_OA_UNIT_GT_ID);
 			__for_each_oa_unit(oau)
 				test_mmio_triggered_reports(oau, false);
 		}
 
 		igt_subtest_with_dynamic("mmio-triggered-reports-read") {
 			igt_require(HAS_OA_MMIO_TRIGGER(devid));
-			igt_require(oau->capabilities & DRM_XE_OA_CAPS_OA_UNIT_GT_ID);
+			igt_require(oau0->capabilities & DRM_XE_OA_CAPS_OA_UNIT_GT_ID);
 			__for_each_oa_unit(oau)
 				test_mmio_triggered_reports(oau, true);
 		}
@@ -5280,7 +5280,7 @@ igt_main_args("b:t", long_options, help_str, opt_handler, NULL)
 
 	igt_subtest_group {
 		igt_fixture {
-			igt_require(oau->capabilities & DRM_XE_OA_CAPS_SYNCS);
+			igt_require(oau0->capabilities & DRM_XE_OA_CAPS_SYNCS);
 		}
 
 		for (const struct sync_section *s = sync_sections; s->name; s++) {
-- 
2.48.1

✗ i915.CI.BAT: failure for OA: Run MMIO trigger tests on all OA units (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3216 bytes --]

== Series Details ==

Series: OA: Run MMIO trigger tests on all OA units (rev2)
URL   : https://patchwork.freedesktop.org/series/158083/
State : failure

== Summary ==

CI Bug Log - changes from IGT_8657 -> IGTPW_14162
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_14162 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_14162, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14162/index.html

Participating hosts (45 -> 19)
------------------------------

  ERROR: It appears as if the changes made in IGTPW_14162 prevented too many machines from booting.

  Missing    (26): fi-snb-2520m bat-adlp-6 fi-skl-6600u bat-mtlp-9 fi-bsw-n3050 bat-dg2-8 bat-dg2-9 bat-twl-1 bat-rplp-1 bat-apl-1 bat-dg2-11 bat-arls-5 fi-bsw-nick bat-twl-2 bat-dg1-7 bat-arlh-3 bat-adlp-9 fi-glk-j4005 bat-dg1-6 bat-arls-6 bat-jsl-1 bat-mtlp-8 bat-adlp-11 bat-jsl-5 fi-kbl-x1275 bat-dg2-14 

Known issues
------------

  Here are the changes found in IGTPW_14162 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_pm_rpm@basic-rte:
    - bat-rpls-4:         [PASS][1] -> [DMESG-WARN][2] ([i915#13400])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8657/bat-rpls-4/igt@kms_pm_rpm@basic-rte.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14162/bat-rpls-4/igt@kms_pm_rpm@basic-rte.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][3] ([i915#12061] / [i915#13929]) -> [DMESG-FAIL][4] ([i915#12061] / [i915#14204])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8657/bat-atsm-1/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14162/bat-atsm-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [DMESG-FAIL][5] ([i915#13929]) -> [DMESG-FAIL][6] ([i915#14204])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8657/bat-atsm-1/igt@i915_selftest@live@mman.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14162/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13400]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13400
  [i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8657 -> IGTPW_14162

  CI-20190529: 20190529
  CI_DRM_17641: abc20a831a03dc608256340159c23e01ee6b6ead @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_14162: 1b560d5d0542bc2e385c92a61bb9985e810c9c8d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8657: 71c70567a9a965cb2942f01832e0b23aca4672f0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14162/index.html

[-- Attachment #2: Type: text/html, Size: 4106 bytes --]

✓ Xe.CI.BAT: success for OA: Run MMIO trigger tests on all OA units (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1464 bytes --]

== Series Details ==

Series: OA: Run MMIO trigger tests on all OA units (rev2)
URL   : https://patchwork.freedesktop.org/series/158083/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8657_BAT -> XEIGTPW_14162_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_14162_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_waitfence@abstime:
    - bat-dg2-oem2:       [TIMEOUT][1] ([Intel XE#6506]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/bat-dg2-oem2/igt@xe_waitfence@abstime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/bat-dg2-oem2/igt@xe_waitfence@abstime.html

  
  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506


Build changes
-------------

  * IGT: IGT_8657 -> IGTPW_14162

  IGTPW_14162: 1b560d5d0542bc2e385c92a61bb9985e810c9c8d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8657: 71c70567a9a965cb2942f01832e0b23aca4672f0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4202-abc20a831a03dc608256340159c23e01ee6b6ead: abc20a831a03dc608256340159c23e01ee6b6ead

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/index.html

[-- Attachment #2: Type: text/html, Size: 2026 bytes --]

✗ Xe.CI.Full: failure for OA: Run MMIO trigger tests on all OA units (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 62470 bytes --]

== Series Details ==

Series: OA: Run MMIO trigger tests on all OA units (rev2)
URL   : https://patchwork.freedesktop.org/series/158083/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8657_FULL -> XEIGTPW_14162_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_14162_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_14162_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 3)
------------------------------

  Missing    (1): shard-adlp 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_14162_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@2x-plain-flip-fb-recreate@bd-dp2-hdmi-a3:
    - shard-bmg:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-3/igt@kms_flip@2x-plain-flip-fb-recreate@bd-dp2-hdmi-a3.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-3/igt@kms_flip@2x-plain-flip-fb-recreate@bd-dp2-hdmi-a3.html

  * igt@xe_ccs@suspend-resume:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][3] +1 other test incomplete
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-8/igt@xe_ccs@suspend-resume.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_uc_fw_init:
    - shard-dg2-set2:     [PASS][4] -> [DMESG-WARN][5]
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-dg2-433/igt@xe_fault_injection@inject-fault-probe-function-xe_uc_fw_init.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@xe_fault_injection@inject-fault-probe-function-xe_uc_fw_init.html
    - shard-lnl:          [PASS][6] -> [DMESG-WARN][7]
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-lnl-8/igt@xe_fault_injection@inject-fault-probe-function-xe_uc_fw_init.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-8/igt@xe_fault_injection@inject-fault-probe-function-xe_uc_fw_init.html

  
New tests
---------

  New tests have been introduced between XEIGT_8657_FULL and XEIGTPW_14162_FULL:

### New IGT tests (21) ###

  * igt@kms_psr@fbc-psr-cursor-plane-move@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [1.96] s

  * igt@kms_psr@fbc-psr-dpms@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [3.25] s

  * igt@kms_psr@fbc-psr-primary-render@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [1.97] s

  * igt@kms_psr@fbc-psr-sprite-blt@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [1.91] s

  * igt@kms_psr@fbc-psr2-basic@edp-1:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_psr@fbc-psr2-cursor-plane-move@edp-1:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_psr@fbc-psr2-cursor-plane-onoff@edp-1:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_psr@fbc-psr2-dpms@edp-1:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_psr@fbc-psr2-primary-page-flip@edp-1:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_psr@fbc-psr2-primary-render@edp-1:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_psr@fbc-psr2-sprite-render@edp-1:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_psr@psr-basic@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [1.81] s

  * igt@kms_psr@psr-cursor-plane-move@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [1.95] s

  * igt@kms_psr@psr-primary-page-flip@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [1.93] s

  * igt@kms_psr@psr-sprite-blt@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [2.02] s

  * igt@kms_psr@psr-sprite-render@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [1.90] s

  * igt@kms_psr@psr-suspend@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [3.80] s

  * igt@kms_psr@psr2-no-drrs@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [1.73] s

  * igt@kms_psr@psr2-primary-blt@edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [1.99] s

  * igt@xe_oa@mmio-triggered-reports@oam-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.03] s

  * igt@xe_oa@mmio-triggered-reports@sag-1:
    - Statuses : 1 pass(s)
    - Exec time: [0.04] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_14162_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-bmg:          [PASS][8] -> [FAIL][9] ([Intel XE#4665])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@intel_hwmon@hwmon-write.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-6/igt@intel_hwmon@hwmon-write.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-bmg:          [PASS][10] -> [FAIL][11] ([Intel XE#3718] / [Intel XE#6078])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-4/igt@kms_async_flips@alternate-sync-async-flip.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2:
    - shard-bmg:          [PASS][12] -> [FAIL][13] ([Intel XE#6078])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-4/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2327])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-6/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#3658])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#619])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][17] ([Intel XE#1124]) +7 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-436/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#1124]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#1124]) +9 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#2191])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-1/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-8/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#2191]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-464/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-1-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#367]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-6/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#367])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-435/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#455] / [Intel XE#787]) +13 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-464/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#2887]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-8/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-dp-2:
    - shard-bmg:          [PASS][27] -> [FAIL][28] ([Intel XE#6173]) +3 other tests fail
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-dp-2.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#3432]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][30] ([Intel XE#787]) +48 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#3432]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2887]) +10 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [PASS][33] -> [INCOMPLETE][34] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][35] -> [INCOMPLETE][36] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [PASS][37] -> [INCOMPLETE][38] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [PASS][39] -> [INCOMPLETE][40] ([Intel XE#1727] / [Intel XE#3113])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-8/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#306])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-1/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@degamma:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#2325]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@kms_chamelium_color@degamma.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][44] ([Intel XE#306]) +2 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-435/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2252]) +4 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-8/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][46] ([Intel XE#373]) +4 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-434/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@vga-hpd-without-ddc:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#373]) +3 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-8/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html

  * igt@kms_colorop@plane-xr24-xr24-ctm_3x4_bt709_enc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#6704]) +3 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-434/igt@kms_colorop@plane-xr24-xr24-ctm_3x4_bt709_enc.html

  * igt@kms_colorop@plane-xr24-xr24-ctm_3x4_bt709_enc_dec:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#6704]) +8 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-8/igt@kms_colorop@plane-xr24-xr24-ctm_3x4_bt709_enc_dec.html
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#6704])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-2/igt@kms_colorop@plane-xr24-xr24-ctm_3x4_bt709_enc_dec.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          NOTRUN -> [FAIL][51] ([Intel XE#1178]) +4 other tests fail
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@kms_content_protection@legacy.html
    - shard-dg2-set2:     NOTRUN -> [FAIL][52] ([Intel XE#1178]) +1 other test fail
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-433/igt@kms_content_protection@legacy.html
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#3278])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-5/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#1424]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-5/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#2320]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-3/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2321])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg2-set2:     NOTRUN -> [SKIP][57] ([Intel XE#308])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-434/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#309]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          NOTRUN -> [FAIL][59] ([Intel XE#5299])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-dg2-set2:     NOTRUN -> [SKIP][60] ([Intel XE#323])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-435/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#2286])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][62] ([Intel XE#4494] / [i915#3804])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-464/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6.html

  * igt@kms_dsc@dsc-basic:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#2244])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-2/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#2244]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-dg2-set2:     NOTRUN -> [SKIP][65] ([Intel XE#4422])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-435/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#4422])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#1421]) +2 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-2/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-bmg:          [PASS][68] -> [ABORT][69] ([Intel XE#5545]) +1 other test abort
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-3/igt@kms_flip@2x-plain-flip-fb-recreate.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-3/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-bmg:          [PASS][70] -> [DMESG-FAIL][71] ([Intel XE#5545]) +1 other test dmesg-fail
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
    - shard-lnl:          [PASS][72] -> [FAIL][73] ([Intel XE#301]) +1 other test fail
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][74] -> [FAIL][75] ([Intel XE#301] / [Intel XE#3149])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#2293] / [Intel XE#2380]) +2 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#2293]) +2 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#1401] / [Intel XE#1745])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#1401])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][80] ([Intel XE#651]) +12 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#651]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-4/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#656]) +10 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#4141]) +11 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#2311]) +22 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][85] ([Intel XE#6312]) +3 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#6312])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#2352])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][88] ([Intel XE#653]) +14 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#2313]) +24 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [ABORT][90] ([Intel XE#6740])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-5/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][91] ([Intel XE#1503])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-2/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_invalid_mode@clock-too-high@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#1450]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-3/igt@kms_invalid_mode@clock-too-high@pipe-a-edp-1.html

  * igt@kms_invalid_mode@clock-too-high@pipe-c-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#1450] / [Intel XE#2568]) +1 other test skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-3/igt@kms_invalid_mode@clock-too-high@pipe-c-edp-1.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][94] ([Intel XE#2925] / [Intel XE#2927])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@kms_joiner@basic-ultra-joiner.html
    - shard-lnl:          NOTRUN -> [SKIP][95] ([Intel XE#2925] / [Intel XE#2927])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-4/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#5624])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][97] ([Intel XE#5624])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-463/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane_multiple@tiling-x@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [FAIL][98] ([Intel XE#4658]) +3 other tests fail
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-4/igt@kms_plane_multiple@tiling-x@pipe-b-edp-1.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#5020])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-2/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#5825]) +11 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [PASS][101] -> [FAIL][102] ([Intel XE#718])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-lnl-1/igt@kms_pm_dc@dc5-dpms.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-3/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - shard-dg2-set2:     [PASS][103] -> [FAIL][104] ([Intel XE#4741])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-dg2-435/igt@kms_pm_rpm@basic-pci-d3-state.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-433/igt@kms_pm_rpm@basic-pci-d3-state.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][105] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][106] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#1406] / [Intel XE#2893]) +3 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-2/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-cursor-plane-update-sf:
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-5/igt@kms_psr2_sf@psr2-cursor-plane-update-sf.html

  * igt@kms_psr@fbc-psr-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +9 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-5/igt@kms_psr@fbc-psr-primary-render.html

  * igt@kms_psr@fbc-psr2-basic:
    - shard-lnl:          NOTRUN -> [SKIP][110] ([Intel XE#1406])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-5/igt@kms_psr@fbc-psr2-basic.html

  * igt@kms_psr@fbc-psr2-basic@edp-1 (NEW):
    - shard-lnl:          NOTRUN -> [SKIP][111] ([Intel XE#1406] / [Intel XE#4609])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-5/igt@kms_psr@fbc-psr2-basic@edp-1.html

  * igt@kms_psr@psr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][112] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +8 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@kms_psr@psr-dpms.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][113] ([Intel XE#1406] / [Intel XE#2414])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][114] ([Intel XE#1406] / [Intel XE#2939])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-463/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][115] ([Intel XE#3414] / [Intel XE#3904])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-8/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-bmg:          NOTRUN -> [SKIP][116] ([Intel XE#3414] / [Intel XE#3904])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_sharpness_filter@filter-modifiers:
    - shard-bmg:          NOTRUN -> [SKIP][117] ([Intel XE#6503]) +2 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@kms_sharpness_filter@filter-modifiers.html

  * igt@kms_sharpness_filter@filter-toggle:
    - shard-dg2-set2:     NOTRUN -> [SKIP][118] ([Intel XE#455]) +3 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-434/igt@kms_sharpness_filter@filter-toggle.html

  * igt@kms_vrr@flip-basic:
    - shard-bmg:          NOTRUN -> [SKIP][119] ([Intel XE#1499])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-6/igt@kms_vrr@flip-basic.html

  * igt@xe_compute_preempt@compute-preempt-many-vram:
    - shard-dg2-set2:     NOTRUN -> [SKIP][120] ([Intel XE#6360])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-435/igt@xe_compute_preempt@compute-preempt-many-vram.html

  * igt@xe_copy_basic@mem-page-copy-17:
    - shard-dg2-set2:     NOTRUN -> [SKIP][121] ([Intel XE#5300])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-464/igt@xe_copy_basic@mem-page-copy-17.html

  * igt@xe_eudebug@basic-exec-queues:
    - shard-bmg:          NOTRUN -> [SKIP][122] ([Intel XE#4837]) +7 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@xe_eudebug@basic-exec-queues.html

  * igt@xe_eudebug@basic-vm-bind-extended:
    - shard-lnl:          NOTRUN -> [SKIP][123] ([Intel XE#4837])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-8/igt@xe_eudebug@basic-vm-bind-extended.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          NOTRUN -> [SKIP][124] ([Intel XE#4837] / [Intel XE#6665]) +4 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@xe_eudebug_online@single-step.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][125] ([Intel XE#4837] / [Intel XE#6665]) +2 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-435/igt@xe_eudebug_online@single-step.html
    - shard-lnl:          NOTRUN -> [SKIP][126] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-2/igt@xe_eudebug_online@single-step.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][127] ([Intel XE#6321])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-beng-threads-small:
    - shard-lnl:          NOTRUN -> [SKIP][128] ([Intel XE#688]) +3 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-1/igt@xe_evict@evict-beng-threads-small.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][129] -> [INCOMPLETE][130] ([Intel XE#6321])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue:
    - shard-bmg:          NOTRUN -> [SKIP][131] ([Intel XE#2322]) +4 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][132] ([Intel XE#1392]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-8/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@once-rebind-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][133] ([Intel XE#288]) +16 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-436/igt@xe_exec_fault_mode@once-rebind-prefetch.html

  * igt@xe_exec_sip_eudebug@wait-writesip-nodebug:
    - shard-dg2-set2:     NOTRUN -> [SKIP][134] ([Intel XE#4837]) +4 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@xe_exec_sip_eudebug@wait-writesip-nodebug.html

  * igt@xe_exec_system_allocator@once-mmap-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][135] ([Intel XE#4943]) +18 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@xe_exec_system_allocator@once-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@process-many-mmap-huge:
    - shard-lnl:          NOTRUN -> [SKIP][136] ([Intel XE#4943]) +4 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-4/igt@xe_exec_system_allocator@process-many-mmap-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-malloc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][137] ([Intel XE#4915]) +204 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@xe_exec_system_allocator@threads-shared-vm-many-large-malloc.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-new-nomemset:
    - shard-bmg:          [PASS][138] -> [SKIP][139] ([Intel XE#6703]) +4 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-new-nomemset.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-new-nomemset.html

  * igt@xe_noexec_ping_pong@basic:
    - shard-lnl:          NOTRUN -> [SKIP][140] ([Intel XE#6259])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-8/igt@xe_noexec_ping_pong@basic.html

  * igt@xe_oa@non-privileged-map-oa-buffer:
    - shard-dg2-set2:     NOTRUN -> [SKIP][141] ([Intel XE#3573]) +4 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-436/igt@xe_oa@non-privileged-map-oa-buffer.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-bmg:          NOTRUN -> [SKIP][142] ([Intel XE#2236])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@xe_pat@pat-index-xelpg.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][143] ([Intel XE#979])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-463/igt@xe_pat@pat-index-xelpg.html
    - shard-lnl:          NOTRUN -> [SKIP][144] ([Intel XE#979])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-1/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pm@d3hot-i2c:
    - shard-lnl:          NOTRUN -> [SKIP][145] ([Intel XE#5742])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-5/igt@xe_pm@d3hot-i2c.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][146] ([Intel XE#2284]) +1 other test skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@xe_pm@s2idle-d3cold-basic-exec.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][147] ([Intel XE#2284] / [Intel XE#366])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-463/igt@xe_pm@s2idle-d3cold-basic-exec.html
    - shard-lnl:          NOTRUN -> [SKIP][148] ([Intel XE#2284] / [Intel XE#366])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-5/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pmu@all-fn-engine-activity-load:
    - shard-dg2-set2:     NOTRUN -> [SKIP][149] ([Intel XE#4650])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@xe_pmu@all-fn-engine-activity-load.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0:
    - shard-lnl:          [PASS][150] -> [FAIL][151] ([Intel XE#6251]) +1 other test fail
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-lnl-5/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][152] ([Intel XE#4733]) +1 other test skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][153] ([Intel XE#4733]) +2 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-432/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-bmg:          NOTRUN -> [SKIP][154] ([Intel XE#944]) +4 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@xe_query@multigpu-query-invalid-cs-cycles.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][155] ([Intel XE#944]) +1 other test skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-464/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  * igt@xe_query@multigpu-query-pxp-status:
    - shard-lnl:          NOTRUN -> [SKIP][156] ([Intel XE#944])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-3/igt@xe_query@multigpu-query-pxp-status.html

  * igt@xe_render_copy@render-stress-0-copies:
    - shard-dg2-set2:     NOTRUN -> [SKIP][157] ([Intel XE#4814])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-433/igt@xe_render_copy@render-stress-0-copies.html

  * igt@xe_sriov_flr@flr-twice:
    - shard-bmg:          NOTRUN -> [FAIL][158] ([Intel XE#6569])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-6/igt@xe_sriov_flr@flr-twice.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][159] ([Intel XE#4273])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-435/igt@xe_sriov_flr@flr-twice.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-bmg:          [PASS][160] -> [FAIL][161] ([Intel XE#6569])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-2/igt@xe_sriov_flr@flr-vf1-clear.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@xe_sriov_flr@flr-vf1-clear.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-transition-nonblocking:
    - shard-bmg:          [INCOMPLETE][162] -> [PASS][163] +1 other test pass
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-3/igt@kms_atomic_transition@plane-all-transition-nonblocking.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-8/igt@kms_atomic_transition@plane-all-transition-nonblocking.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [SKIP][164] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][165]
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-hdmi-a-3:
    - shard-bmg:          [DMESG-WARN][166] ([Intel XE#3428]) -> [PASS][167] +1 other test pass
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-hdmi-a-3.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-3/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][168] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345]) -> [PASS][169]
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][170] ([Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212]) -> [PASS][171]
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-bmg:          [SKIP][172] ([Intel XE#2291]) -> [PASS][173] +1 other test pass
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-bmg:          [SKIP][174] ([Intel XE#4302]) -> [PASS][175]
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3:
    - shard-bmg:          [DMESG-WARN][176] -> [PASS][177]
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3:
    - shard-bmg:          [ABORT][178] ([Intel XE#5545]) -> [PASS][179] +1 other test pass
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-plain-flip:
    - shard-bmg:          [SKIP][180] ([Intel XE#2316]) -> [PASS][181] +6 other tests pass
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@kms_flip@2x-plain-flip.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][182] ([Intel XE#301]) -> [PASS][183]
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * {igt@kms_sharpness_filter@filter-formats@pipe-a-edp-1-nv12}:
    - shard-lnl:          [DMESG-WARN][184] ([Intel XE#4537]) -> [PASS][185] +1 other test pass
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-lnl-8/igt@kms_sharpness_filter@filter-formats@pipe-a-edp-1-nv12.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-8/igt@kms_sharpness_filter@filter-formats@pipe-a-edp-1-nv12.html

  * igt@testdisplay:
    - shard-bmg:          [ABORT][186] ([Intel XE#6740]) -> [PASS][187]
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-5/igt@testdisplay.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@testdisplay.html

  * igt@xe_configfs@ctx-restore-post-bb-invalid:
    - shard-dg2-set2:     [ABORT][188] -> [PASS][189]
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-dg2-464/igt@xe_configfs@ctx-restore-post-bb-invalid.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-464/igt@xe_configfs@ctx-restore-post-bb-invalid.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0:
    - shard-lnl:          [FAIL][190] ([Intel XE#6251]) -> [PASS][191] +4 other tests pass
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-lnl-5/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-bmg:          [FAIL][192] ([Intel XE#6569]) -> [PASS][193]
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-4/igt@xe_sriov_flr@flr-vfs-parallel.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-4/igt@xe_sriov_flr@flr-vfs-parallel.html

  
#### Warnings ####

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs:
    - shard-bmg:          [SKIP][194] ([Intel XE#2887]) -> [SKIP][195] ([Intel XE#6703])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-1/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [SKIP][196] ([Intel XE#2341]) -> [FAIL][197] ([Intel XE#1178])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@kms_content_protection@atomic.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@srm:
    - shard-dg2-set2:     [FAIL][198] ([Intel XE#1178]) -> [SKIP][199] ([Intel XE#455])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-dg2-464/igt@kms_content_protection@srm.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-dg2-436/igt@kms_content_protection@srm.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-bmg:          [SKIP][200] ([Intel XE#2244]) -> [SKIP][201] ([Intel XE#6703])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-3/igt@kms_dsc@dsc-with-formats.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][202] ([Intel XE#301]) -> [FAIL][203] ([Intel XE#301] / [Intel XE#3149])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][204] ([Intel XE#2312]) -> [SKIP][205] ([Intel XE#2311]) +11 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][206] ([Intel XE#2312]) -> [SKIP][207] ([Intel XE#4141]) +4 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-bmg:          [SKIP][208] ([Intel XE#2312]) -> [SKIP][209] ([Intel XE#2313]) +7 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][210] ([Intel XE#1503]) -> [ABORT][211] ([Intel XE#6740])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-4/igt@kms_hdr@invalid-hdr.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-5/igt@kms_hdr@invalid-hdr.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-bmg:          [SKIP][212] ([Intel XE#3414] / [Intel XE#3904]) -> [SKIP][213] ([Intel XE#6703])
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][214] ([Intel XE#1729]) -> [SKIP][215] ([Intel XE#2426])
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html

  * igt@xe_eudebug_online@pagefault-read:
    - shard-bmg:          [SKIP][216] ([Intel XE#4837] / [Intel XE#6665]) -> [SKIP][217] ([Intel XE#6703])
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8657/shard-bmg-6/igt@xe_eudebug_online@pagefault-read.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/shard-bmg-2/igt@xe_eudebug_online@pagefault-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1450
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2568]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2568
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4494]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4494
  [Intel XE#4537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4537
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4658
  [Intel XE#4665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4665
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4741
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#5825]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5825
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#6173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6173
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6259]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6259
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6704]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6704
  [Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804


Build changes
-------------

  * IGT: IGT_8657 -> IGTPW_14162

  IGTPW_14162: 1b560d5d0542bc2e385c92a61bb9985e810c9c8d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8657: 71c70567a9a965cb2942f01832e0b23aca4672f0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4202-abc20a831a03dc608256340159c23e01ee6b6ead: abc20a831a03dc608256340159c23e01ee6b6ead

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14162/index.html

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