* [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next
@ 2023-06-23 3:24 Ashutosh Dixit
2023-06-23 7:11 ` [igt-dev] ✓ Fi.CI.BAT: success for drm-uapi/xe_drm: Sync from drm-xe-next (rev2) Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Ashutosh Dixit @ 2023-06-23 3:24 UTC (permalink / raw)
To: igt-dev
Our include/drm-uapi/xe_drm.h is from March. Pull in the latest xe_drm.h
from drm-xe-next kernel branch. Generated after 'make headers_install'.
v2: Fix build break in tests/xe/xe_vm.c
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
include/drm-uapi/xe_drm.h | 315 +++++++++++++++++++++++++++-----------
tests/xe/xe_vm.c | 2 +-
2 files changed, 224 insertions(+), 93 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 593b01ba5919..bcec0df6d115 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -1,26 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
- * Copyright 2021 Intel Corporation. All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ * Copyright © 2023 Intel Corporation
*/
#ifndef _UAPI_XE_DRM_H_
@@ -37,7 +17,7 @@ extern "C" {
*/
/**
- * struct i915_user_extension - Base class for defining a chain of extensions
+ * struct xe_user_extension - Base class for defining a chain of extensions
*
* Many interfaces need to grow over time. In most cases we can simply
* extend the struct and have userspace pass in more data. Another option,
@@ -55,20 +35,20 @@ extern "C" {
*
* .. code-block:: C
*
- * struct i915_user_extension ext3 {
+ * struct xe_user_extension ext3 {
* .next_extension = 0, // end
* .name = ...,
* };
- * struct i915_user_extension ext2 {
+ * struct xe_user_extension ext2 {
* .next_extension = (uintptr_t)&ext3,
* .name = ...,
* };
- * struct i915_user_extension ext1 {
+ * struct xe_user_extension ext1 {
* .next_extension = (uintptr_t)&ext2,
* .name = ...,
* };
*
- * Typically the struct i915_user_extension would be embedded in some uAPI
+ * Typically the struct xe_user_extension would be embedded in some uAPI
* struct, and in this case we would feed it the head of the chain(i.e ext1),
* which would then apply all of the above extensions.
*
@@ -77,9 +57,10 @@ struct xe_user_extension {
/**
* @next_extension:
*
- * Pointer to the next struct i915_user_extension, or zero if the end.
+ * Pointer to the next struct xe_user_extension, or zero if the end.
*/
__u64 next_extension;
+
/**
* @name: Name of the extension.
*
@@ -87,11 +68,12 @@ struct xe_user_extension {
*
* Also note that the name space for this is not global for the whole
* driver, but rather its scope/meaning is limited to the specific piece
- * of uAPI which has embedded the struct i915_user_extension.
+ * of uAPI which has embedded the struct xe_user_extension.
*/
__u32 name;
+
/**
- * @flags: MBZ
+ * @pad: MBZ
*
* All undefined bits must be zero.
*/
@@ -99,7 +81,7 @@ struct xe_user_extension {
};
/*
- * i915 specific ioctls.
+ * xe specific ioctls.
*
* The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
* [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
@@ -125,40 +107,32 @@ struct xe_user_extension {
#define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)
#define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)
#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
-#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
-#define DRM_IOCTL_XE_VM_BIND DRM_IOW( DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
+#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
+#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
#define DRM_IOCTL_XE_ENGINE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_CREATE, struct drm_xe_engine_create)
#define DRM_IOCTL_XE_ENGINE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_GET_PROPERTY, struct drm_xe_engine_get_property)
-#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy)
-#define DRM_IOCTL_XE_EXEC DRM_IOW( DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
+#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy)
+#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
#define DRM_IOCTL_XE_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_MMIO, struct drm_xe_mmio)
-#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property)
+#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property)
#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
-#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW( DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
-
-struct drm_xe_engine_class_instance {
- __u16 engine_class;
-
-#define DRM_XE_ENGINE_CLASS_RENDER 0
-#define DRM_XE_ENGINE_CLASS_COPY 1
-#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
-#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
-#define DRM_XE_ENGINE_CLASS_COMPUTE 4
- /*
- * Kernel only class (not actual hardware engine class). Used for
- * creating ordered queues of VM bind operations.
- */
-#define DRM_XE_ENGINE_CLASS_VM_BIND 5
-
- __u16 engine_instance;
- __u16 gt_id;
-};
+#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
#define XE_MEM_REGION_CLASS_SYSMEM 0
#define XE_MEM_REGION_CLASS_VRAM 1
+/**
+ * struct drm_xe_query_mem_usage - describe memory regions and usage
+ *
+ * If a query is made with a struct drm_xe_device_query where .query
+ * is equal to DRM_XE_DEVICE_QUERY_MEM_USAGE, then the reply uses
+ * struct drm_xe_query_mem_usage in .data.
+ */
struct drm_xe_query_mem_usage {
+ /** @num_params: number of memory regions returned in regions */
__u32 num_regions;
+
+ /** @pad: MBZ */
__u32 pad;
struct drm_xe_query_mem_region {
@@ -173,9 +147,20 @@ struct drm_xe_query_mem_usage {
} regions[];
};
+/**
+ * struct drm_xe_query_config - describe the device configuration
+ *
+ * If a query is made with a struct drm_xe_device_query where .query
+ * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses
+ * struct drm_xe_query_config in .data.
+ */
struct drm_xe_query_config {
+ /** @num_params: number of parameters returned in info */
__u32 num_params;
+
+ /** @pad: MBZ */
__u32 pad;
+
#define XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
#define XE_QUERY_CONFIG_FLAGS 1
#define XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0)
@@ -184,12 +169,24 @@ struct drm_xe_query_config {
#define XE_QUERY_CONFIG_VA_BITS 3
#define XE_QUERY_CONFIG_GT_COUNT 4
#define XE_QUERY_CONFIG_MEM_REGION_COUNT 5
-#define XE_QUERY_CONFIG_NUM_PARAM XE_QUERY_CONFIG_MEM_REGION_COUNT + 1
+#define XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY 6
+#define XE_QUERY_CONFIG_NUM_PARAM (XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY + 1)
+ /** @info: array of elements containing the config info */
__u64 info[];
};
+/**
+ * struct drm_xe_query_gts - describe GTs
+ *
+ * If a query is made with a struct drm_xe_device_query where .query
+ * is equal to DRM_XE_DEVICE_QUERY_GTS, then the reply uses struct
+ * drm_xe_query_gts in .data.
+ */
struct drm_xe_query_gts {
+ /** @num_gt: number of GTs returned in gts */
__u32 num_gt;
+
+ /** @pad: MBZ */
__u32 pad;
/*
@@ -212,15 +209,46 @@ struct drm_xe_query_gts {
} gts[];
};
+/**
+ * struct drm_xe_query_topology_mask - describe the topology mask of a GT
+ *
+ * This is the hardware topology which reflects the internal physical
+ * structure of the GPU.
+ *
+ * If a query is made with a struct drm_xe_device_query where .query
+ * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses
+ * struct drm_xe_query_topology_mask in .data.
+ */
struct drm_xe_query_topology_mask {
/** @gt_id: GT ID the mask is associated with */
__u16 gt_id;
- /** @type: type of mask */
- __u16 type;
+ /*
+ * To query the mask of Dual Sub Slices (DSS) available for geometry
+ * operations. For example a query response containing the following
+ * in mask:
+ * DSS_GEOMETRY ff ff ff ff 00 00 00 00
+ * means 32 DSS are available for geometry.
+ */
#define XE_TOPO_DSS_GEOMETRY (1 << 0)
+ /*
+ * To query the mask of Dual Sub Slices (DSS) available for compute
+ * operations. For example a query response containing the following
+ * in mask:
+ * DSS_COMPUTE ff ff ff ff 00 00 00 00
+ * means 32 DSS are available for compute.
+ */
#define XE_TOPO_DSS_COMPUTE (1 << 1)
+ /*
+ * To query the mask of Execution Units (EU) available per Dual Sub
+ * Slices (DSS). For example a query response containing the following
+ * in mask:
+ * EU_PER_DSS ff ff 00 00 00 00 00 00
+ * means each DSS has 16 EU.
+ */
#define XE_TOPO_EU_PER_DSS (1 << 2)
+ /** @type: type of mask */
+ __u16 type;
/** @num_bytes: number of bytes in requested mask */
__u32 num_bytes;
@@ -229,19 +257,53 @@ struct drm_xe_query_topology_mask {
__u8 mask[];
};
+/**
+ * struct drm_xe_device_query - main structure to query device information
+ *
+ * If size is set to 0, the driver fills it with the required size for the
+ * requested type of data to query. If size is equal to the required size,
+ * the queried information is copied into data.
+ *
+ * For example the following code snippet allows retrieving and printing
+ * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_xe_engine_class_instance *hwe;
+ * struct drm_xe_device_query query = {
+ * .extensions = 0,
+ * .query = DRM_XE_DEVICE_QUERY_ENGINES,
+ * .size = 0,
+ * .data = 0,
+ * };
+ * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
+ * hwe = malloc(query.size);
+ * query.data = (uintptr_t)hwe;
+ * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
+ * int num_engines = query.size / sizeof(*hwe);
+ * for (int i = 0; i < num_engines; i++) {
+ * printf("Engine %d: %s\n", i,
+ * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER":
+ * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY":
+ * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE":
+ * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE":
+ * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE":
+ * "UNKNOWN");
+ * }
+ * free(hwe);
+ */
struct drm_xe_device_query {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
- /** @query: The type of data to query */
- __u32 query;
-
#define DRM_XE_DEVICE_QUERY_ENGINES 0
#define DRM_XE_DEVICE_QUERY_MEM_USAGE 1
#define DRM_XE_DEVICE_QUERY_CONFIG 2
#define DRM_XE_DEVICE_QUERY_GTS 3
#define DRM_XE_DEVICE_QUERY_HWCONFIG 4
#define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
+ /** @query: The type of data to query */
+ __u32 query;
/** @size: Size of the queried data */
__u32 size;
@@ -264,12 +326,12 @@ struct drm_xe_gem_create {
*/
__u64 size;
+#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
+#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
/**
* @flags: Flags, currently a mask of memory instances of where BO can
* be placed
*/
-#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
-#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
__u32 flags;
/**
@@ -290,6 +352,9 @@ struct drm_xe_gem_create {
*/
__u32 handle;
+ /** @pad: MBZ */
+ __u32 pad;
+
/** @reserved: Reserved */
__u64 reserved[2];
};
@@ -317,10 +382,13 @@ struct drm_xe_gem_mmap_offset {
struct drm_xe_vm_bind_op_error_capture {
/** @error: errno that occured */
__s32 error;
+
/** @op: operation that encounter an error */
__u32 op;
+
/** @addr: address of bind op */
__u64 addr;
+
/** @size: size of bind */
__u64 size;
};
@@ -330,10 +398,13 @@ struct drm_xe_ext_vm_set_property {
/** @base: base user extension */
struct xe_user_extension base;
- /** @property: property to set */
#define XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS 0
+ /** @property: property to set */
__u32 property;
+ /** @pad: MBZ */
+ __u32 pad;
+
/** @value: property value */
__u64 value;
@@ -342,17 +413,16 @@ struct drm_xe_ext_vm_set_property {
};
struct drm_xe_vm_create {
- /** @extensions: Pointer to the first extension struct, if any */
#define XE_VM_EXTENSION_SET_PROPERTY 0
+ /** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
- /** @flags: Flags */
- __u32 flags;
-
#define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0)
#define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1)
#define DRM_XE_VM_CREATE_ASYNC_BIND_OPS (0x1 << 2)
#define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3)
+ /** @flags: Flags */
+ __u32 flags;
/** @vm_id: Returned VM ID */
__u32 vm_id;
@@ -378,12 +448,16 @@ struct drm_xe_vm_bind_op {
*/
__u32 obj;
+ /** @pad: MBZ */
+ __u32 pad;
+
union {
/**
* @obj_offset: Offset into the object, MBZ for CLEAR_RANGE,
* ignored for unbind
*/
__u64 obj_offset;
+
/** @userptr: user pointer to bind on */
__u64 userptr;
};
@@ -397,16 +471,10 @@ struct drm_xe_vm_bind_op {
__u64 addr;
/**
- * @gt_mask: Mask for which GTs to create binds for, 0 == All GTs,
+ * @tile_mask: Mask for which tiles to create binds for, 0 == All tiles,
* only applies to creating new VMAs
*/
- __u64 gt_mask;
-
- /** @op: Operation to perform (lower 16 bits) and flags (upper 16 bits) */
- __u32 op;
-
- /** @mem_region: Memory region to prefetch VMA to, instance not a mask */
- __u32 region;
+ __u64 tile_mask;
#define XE_VM_BIND_OP_MAP 0x0
#define XE_VM_BIND_OP_UNMAP 0x1
@@ -427,8 +495,8 @@ struct drm_xe_vm_bind_op {
* If this flag is clear and the IOCTL doesn't return an error, in
* practice the bind op is good and will complete.
*
- * If this flag is set and doesn't return return an error, the bind op
- * can still fail and recovery is needed. If configured, the bind op that
+ * If this flag is set and doesn't return an error, the bind op can
+ * still fail and recovery is needed. If configured, the bind op that
* caused the error will be captured in drm_xe_vm_bind_op_error_capture.
* Once the user sees the error (via a ufence +
* XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS), it should free memory
@@ -446,6 +514,19 @@ struct drm_xe_vm_bind_op {
* than differing the MAP to the page fault handler.
*/
#define XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 18)
+ /*
+ * When the NULL flag is set, the page tables are setup with a special
+ * bit which indicates writes are dropped and all reads return zero. In
+ * the future, the NULL flags will only be valid for XE_VM_BIND_OP_MAP
+ * operations, the BO handle MBZ, and the BO offset MBZ. This flag is
+ * intended to implement VK sparse bindings.
+ */
+#define XE_VM_BIND_FLAG_NULL (0x1 << 19)
+ /** @op: Operation to perform (lower 16 bits) and flags (upper 16 bits) */
+ __u32 op;
+
+ /** @mem_region: Memory region to prefetch VMA to, instance not a mask */
+ __u32 region;
/** @reserved: Reserved */
__u64 reserved[2];
@@ -468,9 +549,13 @@ struct drm_xe_vm_bind {
/** @num_binds: number of binds in this IOCTL */
__u32 num_binds;
+ /** @pad: MBZ */
+ __u32 pad;
+
union {
/** @bind: used if num_binds == 1 */
struct drm_xe_vm_bind_op bind;
+
/**
* @vector_of_binds: userptr to array of struct
* drm_xe_vm_bind_op if num_binds > 1
@@ -481,6 +566,9 @@ struct drm_xe_vm_bind {
/** @num_syncs: amount of syncs to wait on */
__u32 num_syncs;
+ /** @pad2: MBZ */
+ __u32 pad2;
+
/** @syncs: pointer to struct drm_xe_sync array */
__u64 syncs;
@@ -496,6 +584,9 @@ struct drm_xe_ext_engine_set_property {
/** @property: property to set */
__u32 property;
+ /** @pad: MBZ */
+ __u32 pad;
+
/** @value: property value */
__u64 value;
};
@@ -512,7 +603,6 @@ struct drm_xe_engine_set_property {
/** @engine_id: Engine ID */
__u32 engine_id;
- /** @property: property to set */
#define XE_ENGINE_SET_PROPERTY_PRIORITY 0
#define XE_ENGINE_SET_PROPERTY_TIMESLICE 1
#define XE_ENGINE_SET_PROPERTY_PREEMPTION_TIMEOUT 2
@@ -528,6 +618,7 @@ struct drm_xe_engine_set_property {
#define XE_ENGINE_SET_PROPERTY_ACC_TRIGGER 6
#define XE_ENGINE_SET_PROPERTY_ACC_NOTIFY 7
#define XE_ENGINE_SET_PROPERTY_ACC_GRANULARITY 8
+ /** @property: property to set */
__u32 property;
/** @value: property value */
@@ -537,9 +628,27 @@ struct drm_xe_engine_set_property {
__u64 reserved[2];
};
+/** struct drm_xe_engine_class_instance - instance of an engine class */
+struct drm_xe_engine_class_instance {
+#define DRM_XE_ENGINE_CLASS_RENDER 0
+#define DRM_XE_ENGINE_CLASS_COPY 1
+#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
+#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
+#define DRM_XE_ENGINE_CLASS_COMPUTE 4
+ /*
+ * Kernel only class (not actual hardware engine class). Used for
+ * creating ordered queues of VM bind operations.
+ */
+#define DRM_XE_ENGINE_CLASS_VM_BIND 5
+ __u16 engine_class;
+
+ __u16 engine_instance;
+ __u16 gt_id;
+};
+
struct drm_xe_engine_create {
- /** @extensions: Pointer to the first extension struct, if any */
#define XE_ENGINE_EXTENSION_SET_PROPERTY 0
+ /** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
/** @width: submission width (number BB per exec) for this engine */
@@ -577,8 +686,8 @@ struct drm_xe_engine_get_property {
/** @engine_id: Engine ID */
__u32 engine_id;
- /** @property: property to get */
#define XE_ENGINE_GET_PROPERTY_BAN 0
+ /** @property: property to get */
__u32 property;
/** @value: property value */
@@ -603,16 +712,19 @@ struct drm_xe_sync {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
- __u32 flags;
-
#define DRM_XE_SYNC_SYNCOBJ 0x0
#define DRM_XE_SYNC_TIMELINE_SYNCOBJ 0x1
#define DRM_XE_SYNC_DMA_BUF 0x2
#define DRM_XE_SYNC_USER_FENCE 0x3
#define DRM_XE_SYNC_SIGNAL 0x10
+ __u32 flags;
+
+ /** @pad: MBZ */
+ __u32 pad;
union {
__u32 handle;
+
/**
* @addr: Address of user fence. When sync passed in via exec
* IOCTL this a GPU address in the VM. When sync passed in via
@@ -644,9 +756,9 @@ struct drm_xe_exec {
__u64 syncs;
/**
- * @address: address of batch buffer if num_batch_buffer == 1 or an
- * array of batch buffer addresses
- */
+ * @address: address of batch buffer if num_batch_buffer == 1 or an
+ * array of batch buffer addresses
+ */
__u64 address;
/**
@@ -655,6 +767,9 @@ struct drm_xe_exec {
*/
__u16 num_batch_buffer;
+ /** @pad: MBZ */
+ __u16 pad[3];
+
/** @reserved: Reserved */
__u64 reserved[2];
};
@@ -665,8 +780,6 @@ struct drm_xe_mmio {
__u32 addr;
- __u32 flags;
-
#define DRM_XE_MMIO_8BIT 0x0
#define DRM_XE_MMIO_16BIT 0x1
#define DRM_XE_MMIO_32BIT 0x2
@@ -674,6 +787,7 @@ struct drm_xe_mmio {
#define DRM_XE_MMIO_BITS_MASK 0x3
#define DRM_XE_MMIO_READ 0x4
#define DRM_XE_MMIO_WRITE 0x8
+ __u32 flags;
__u64 value;
@@ -693,45 +807,57 @@ struct drm_xe_mmio {
struct drm_xe_wait_user_fence {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
+
union {
/**
* @addr: user pointer address to wait on, must qword aligned
*/
__u64 addr;
+
/**
* @vm_id: The ID of the VM which encounter an error used with
* DRM_XE_UFENCE_WAIT_VM_ERROR. Upper 32 bits must be clear.
*/
__u64 vm_id;
};
- /** @op: wait operation (type of comparison) */
+
#define DRM_XE_UFENCE_WAIT_EQ 0
#define DRM_XE_UFENCE_WAIT_NEQ 1
#define DRM_XE_UFENCE_WAIT_GT 2
#define DRM_XE_UFENCE_WAIT_GTE 3
#define DRM_XE_UFENCE_WAIT_LT 4
#define DRM_XE_UFENCE_WAIT_LTE 5
+ /** @op: wait operation (type of comparison) */
__u16 op;
- /** @flags: wait flags */
+
#define DRM_XE_UFENCE_WAIT_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */
#define DRM_XE_UFENCE_WAIT_ABSTIME (1 << 1)
#define DRM_XE_UFENCE_WAIT_VM_ERROR (1 << 2)
+ /** @flags: wait flags */
__u16 flags;
+
+ /** @pad: MBZ */
+ __u32 pad;
+
/** @value: compare value */
__u64 value;
- /** @mask: comparison mask */
+
#define DRM_XE_UFENCE_WAIT_U8 0xffu
#define DRM_XE_UFENCE_WAIT_U16 0xffffu
#define DRM_XE_UFENCE_WAIT_U32 0xffffffffu
#define DRM_XE_UFENCE_WAIT_U64 0xffffffffffffffffu
+ /** @mask: comparison mask */
__u64 mask;
+
/** @timeout: how long to wait before bailing, value in jiffies */
__s64 timeout;
+
/**
* @num_engines: number of engine instances to wait on, must be zero
* when DRM_XE_UFENCE_WAIT_SOFT_OP set
*/
__u64 num_engines;
+
/**
* @instances: user pointer to array of drm_xe_engine_class_instance to
* wait on, must be NULL when DRM_XE_UFENCE_WAIT_SOFT_OP set
@@ -749,6 +875,9 @@ struct drm_xe_vm_madvise {
/** @vm_id: The ID VM in which the VMA exists */
__u32 vm_id;
+ /** @pad: MBZ */
+ __u32 pad;
+
/** @range: Number of bytes in the VMA */
__u64 range;
@@ -789,10 +918,12 @@ struct drm_xe_vm_madvise {
#define DRM_XE_VMA_PRIORITY_HIGH 2 /* Must be elevated user */
/* Pin the VMA in memory, must be elevated user */
#define DRM_XE_VM_MADVISE_PIN 6
-
/** @property: property to set */
__u32 property;
+ /** @pad2: MBZ */
+ __u32 pad2;
+
/** @value: property value */
__u64 value;
diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
index 479ded70f29b..3c26e1ed799d 100644
--- a/tests/xe/xe_vm.c
+++ b/tests/xe/xe_vm.c
@@ -892,7 +892,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
bind_ops[i].obj_offset = 0;
bind_ops[i].range = bo_size;
bind_ops[i].addr = addr;
- bind_ops[i].gt_mask = 0x1 << eci->gt_id;
+ bind_ops[i].tile_mask = 0x1 << eci->gt_id;
bind_ops[i].op = XE_VM_BIND_OP_MAP | XE_VM_BIND_FLAG_ASYNC;
bind_ops[i].region = 0;
bind_ops[i].reserved[0] = 0;
--
2.38.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for drm-uapi/xe_drm: Sync from drm-xe-next (rev2)
2023-06-23 3:24 [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next Ashutosh Dixit
@ 2023-06-23 7:11 ` Patchwork
2023-06-23 11:16 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2023-06-23 18:03 ` [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next Kamil Konieczny
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-06-23 7:11 UTC (permalink / raw)
To: Ashutosh Dixit; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 6426 bytes --]
== Series Details ==
Series: drm-uapi/xe_drm: Sync from drm-xe-next (rev2)
URL : https://patchwork.freedesktop.org/series/119779/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13309 -> IGTPW_9243
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/index.html
Participating hosts (43 -> 41)
------------------------------
Additional (1): bat-dg1-8
Missing (3): fi-kbl-soraka fi-snb-2520m fi-pnv-d510
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_9243:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@xe_create@create-massive-size}:
- {bat-dg1-8}: NOTRUN -> [FAIL][1] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/bat-dg1-8/igt@xe_create@create-massive-size.html
New tests
---------
New tests have been introduced between CI_DRM_13309 and IGTPW_9243:
### New IGT tests (2) ###
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-d-edp-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_9243 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_mocs:
- bat-mtlp-8: [PASS][2] -> [DMESG-FAIL][3] ([i915#7059])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][4] -> [ABORT][5] ([i915#4983] / [i915#7911] / [i915#7920])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-rpls-1/igt@i915_selftest@live@requests.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/bat-rpls-1/igt@i915_selftest@live@requests.html
- bat-rpls-2: [PASS][6] -> [ABORT][7] ([i915#7913] / [i915#7982])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-rpls-2/igt@i915_selftest@live@requests.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#7828])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/bat-dg2-11/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][9] -> [FAIL][10] ([i915#7932])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- bat-dg2-11: [ABORT][11] ([i915#7913]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-dg2-11/igt@i915_selftest@live@requests.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/bat-dg2-11/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-6: [DMESG-FAIL][13] ([i915#6763]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
#### Warnings ####
* igt@i915_module_load@load:
- bat-adlp-11: [DMESG-WARN][15] ([i915#4423]) -> [ABORT][16] ([i915#4423])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-adlp-11/igt@i915_module_load@load.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/bat-adlp-11/igt@i915_module_load@load.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8513]: https://gitlab.freedesktop.org/drm/intel/issues/8513
[i915#8676]: https://gitlab.freedesktop.org/drm/intel/issues/8676
[i915#8678]: https://gitlab.freedesktop.org/drm/intel/issues/8678
[i915#8679]: https://gitlab.freedesktop.org/drm/intel/issues/8679
[i915#8698]: https://gitlab.freedesktop.org/drm/intel/issues/8698
[i915#8699]: https://gitlab.freedesktop.org/drm/intel/issues/8699
[i915#8700]: https://gitlab.freedesktop.org/drm/intel/issues/8700
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7346 -> IGTPW_9243
CI-20190529: 20190529
CI_DRM_13309: af67b02abf56a5018cd885c94d7611241052e98f @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9243: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/index.html
IGT_7346: 29302a0d57bcf10cb553f5d7ff5bb99166a19bba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/index.html
[-- Attachment #2: Type: text/html, Size: 6561 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for drm-uapi/xe_drm: Sync from drm-xe-next (rev2)
2023-06-23 3:24 [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next Ashutosh Dixit
2023-06-23 7:11 ` [igt-dev] ✓ Fi.CI.BAT: success for drm-uapi/xe_drm: Sync from drm-xe-next (rev2) Patchwork
@ 2023-06-23 11:16 ` Patchwork
2023-06-23 18:03 ` [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next Kamil Konieczny
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-06-23 11:16 UTC (permalink / raw)
To: Ashutosh Dixit; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 38092 bytes --]
== Series Details ==
Series: drm-uapi/xe_drm: Sync from drm-xe-next (rev2)
URL : https://patchwork.freedesktop.org/series/119779/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13309_full -> IGTPW_9243_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/index.html
Participating hosts (9 -> 8)
------------------------------
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_9243_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-2:
- {shard-dg2}: NOTRUN -> [TIMEOUT][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg2-12/igt@kms_content_protection@atomic-dpms@pipe-a-dp-2.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a3:
- {shard-dg2}: [PASS][2] -> [INCOMPLETE][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-1/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a3.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg2-1/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a3.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
- {shard-dg2}: [PASS][4] -> [FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-dp-4:
- {shard-dg2}: NOTRUN -> [SKIP][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg2-11/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-dp-4.html
New tests
---------
New tests have been introduced between CI_DRM_13309_full and IGTPW_9243_full:
### New IGT tests (6) ###
* igt@kms_pipe_crc_basic@read-crc@pipe-c-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-c-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-c-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_9243_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@crc32:
- shard-rkl: NOTRUN -> [SKIP][7] ([i915#6230])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-1/igt@api_intel_bb@crc32.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: NOTRUN -> [FAIL][8] ([i915#7742])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@feature_discovery@psr2:
- shard-rkl: NOTRUN -> [SKIP][9] ([i915#658])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-1/igt@feature_discovery@psr2.html
* igt@gem_ccs@block-copy-compressed:
- shard-rkl: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#4579] / [i915#5325])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-tglu: NOTRUN -> [SKIP][11] ([i915#4579] / [i915#5325])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-7/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-rkl: NOTRUN -> [SKIP][12] ([i915#6335])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-1/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_create@create-ext-set-pat:
- shard-glk: NOTRUN -> [FAIL][13] ([i915#8621])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk7/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [PASS][14] -> [FAIL][15] ([i915#6268])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: [PASS][16] -> [ABORT][17] ([i915#180])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][18] ([i915#7975] / [i915#8213])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-rkl: NOTRUN -> [SKIP][19] ([i915#4525])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][20] ([i915#2842]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: [PASS][21] -> [FAIL][22] ([i915#2842]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-6/igt@gem_exec_fair@basic-none@bcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-rkl: NOTRUN -> [SKIP][23] ([fdo#109283])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-4/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-wc-cpu:
- shard-rkl: NOTRUN -> [SKIP][24] ([i915#3281])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-1/igt@gem_exec_reloc@basic-wc-cpu.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-tglu: [PASS][25] -> [ABORT][26] ([i915#7975] / [i915#8213])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-tglu-3/igt@gem_exec_suspend@basic-s4-devices@smem.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_lmem_swapping@random-engines:
- shard-glk: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#4613]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk7/igt@gem_lmem_swapping@random-engines.html
* igt@gem_partial_pwrite_pread@reads:
- shard-rkl: NOTRUN -> [SKIP][28] ([i915#3282])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-1/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-rkl: NOTRUN -> [SKIP][29] ([i915#4270]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gen7_exec_parse@bitmasks:
- shard-rkl: NOTRUN -> [SKIP][30] ([fdo#109289])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-4/igt@gen7_exec_parse@bitmasks.html
* igt@i915_pm_dc@dc6-dpms:
- shard-rkl: NOTRUN -> [SKIP][31] ([i915#3361])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-rkl: NOTRUN -> [SKIP][32] ([i915#1937] / [i915#4579])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-rkl: [PASS][33] -> [SKIP][34] ([i915#1397]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-6/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@i2c:
- shard-glk: [PASS][35] -> [FAIL][36] ([i915#5466])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-glk8/igt@i915_pm_rpm@i2c.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk6/igt@i915_pm_rpm@i2c.html
* igt@i915_query@hwconfig_table:
- shard-rkl: NOTRUN -> [SKIP][37] ([i915#6245])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-4/igt@i915_query@hwconfig_table.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-rkl: NOTRUN -> [SKIP][38] ([fdo#109303])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@i915_query@query-topology-known-pci-ids.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][39] ([fdo#111615] / [i915#5286])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-9/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][40] ([i915#5286]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][41] ([fdo#111614] / [i915#3638]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][42] ([fdo#110723]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][43] ([i915#3886] / [i915#5354] / [i915#6095]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][44] ([i915#5354] / [i915#6095]) +6 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-4/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-yf_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#3734] / [i915#5354] / [i915#6095]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-1/igt@kms_ccs@pipe-b-ccs-on-another-bo-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-rkl: NOTRUN -> [SKIP][46] ([i915#5354]) +13 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-6/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +7 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk4/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_mtl_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][48] ([i915#5354] / [i915#6095])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-3/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_mtl_mc_ccs.html
* igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][49] ([i915#3689] / [i915#5354] / [i915#6095])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-6/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
- shard-rkl: NOTRUN -> [SKIP][50] ([i915#7828]) +3 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
* igt@kms_content_protection@atomic-dpms:
- shard-rkl: NOTRUN -> [SKIP][51] ([i915#4579] / [i915#7118])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-1/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-rkl: NOTRUN -> [SKIP][52] ([i915#3555] / [i915#4579]) +3 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-rkl: NOTRUN -> [SKIP][53] ([fdo#111825]) +5 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [PASS][54] -> [FAIL][55] ([i915#2346])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@forked-bo@pipe-b:
- shard-rkl: [PASS][56] -> [INCOMPLETE][57] ([i915#8011])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-6/igt@kms_cursor_legacy@forked-bo@pipe-b.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@kms_cursor_legacy@forked-bo@pipe-b.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][58] ([i915#3804] / [i915#4579])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dp_aux_dev:
- shard-rkl: NOTRUN -> [SKIP][59] ([i915#1257])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-with-bpc:
- shard-tglu: NOTRUN -> [SKIP][60] ([i915#3840] / [i915#4579])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-5/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][61] ([i915#2672] / [i915#4579]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#3023]) +9 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
- shard-tglu: NOTRUN -> [SKIP][63] ([fdo#109280])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-rkl: NOTRUN -> [SKIP][64] ([fdo#111825] / [i915#1825]) +15 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][65] ([fdo#110189]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
* igt@kms_panel_fitting@legacy:
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#4579] / [i915#6301])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][67] ([i915#7862]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk9/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][68] ([i915#5176]) +4 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][69] ([i915#4579] / [i915#5176]) +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#4579]) +10 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-snb1/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][71] ([fdo#109271]) +13 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-snb1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][72] ([i915#5235])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#4579] / [i915#5235])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][74] ([fdo#109271]) +146 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-tglu: NOTRUN -> [SKIP][75] ([i915#658])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-8/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][76] ([fdo#111068] / [i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-4/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr@cursor_mmap_gtt:
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#1072]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@kms_psr@cursor_mmap_gtt.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-glk: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#4579]) +14 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk5/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#3555] / [i915#4098] / [i915#4579])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-6/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_vblank@pipe-c-wait-idle:
- shard-rkl: NOTRUN -> [SKIP][80] ([i915#4070] / [i915#6768]) +3 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-1/igt@kms_vblank@pipe-c-wait-idle.html
* igt@kms_vblank@pipe-d-ts-continuation-modeset:
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#4070] / [i915#533] / [i915#6768]) +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-6/igt@kms_vblank@pipe-d-ts-continuation-modeset.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][82] ([fdo#109295] / [i915#3708])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-1/igt@prime_vgem@fence-write-hang.html
* igt@v3d/v3d_wait_bo@used-bo-1ns:
- shard-rkl: NOTRUN -> [SKIP][83] ([fdo#109315]) +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@v3d/v3d_wait_bo@used-bo-1ns.html
* igt@vc4/vc4_tiling@set-bad-flags:
- shard-rkl: NOTRUN -> [SKIP][84] ([i915#7711])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@vc4/vc4_tiling@set-bad-flags.html
#### Possible fixes ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-rkl: [ABORT][85] ([i915#7461] / [i915#8211]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-7/igt@gem_barrier_race@remote-request@rcs0.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-4/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_eio@kms:
- {shard-dg2}: [INCOMPLETE][87] ([i915#7892]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-7/igt@gem_eio@kms.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg2-7/igt@gem_eio@kms.html
* igt@gem_eio@reset-stress:
- {shard-dg1}: [FAIL][89] ([i915#5784]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg1-14/igt@gem_eio@reset-stress.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg1-16/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][91] ([i915#2842]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [FAIL][93] ([i915#2842]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [FAIL][95] ([i915#2842]) -> [PASS][96] +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-1/igt@gem_exec_fair@basic-pace@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [FAIL][97] ([i915#2842]) -> [PASS][98] +2 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-glk3/igt@gem_exec_fair@basic-pace@vcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk3/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_softpin@noreloc-s3:
- {shard-dg2}: [INCOMPLETE][99] ([i915#7886]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-7/igt@gem_softpin@noreloc-s3.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg2-1/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglu: [SKIP][101] ([i915#4281]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-tglu-5/igt@i915_pm_dc@dc9-dpms.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-tglu-4/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-dg1}: [SKIP][103] ([i915#1937] / [i915#4579]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg1-15/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- {shard-dg1}: [FAIL][105] ([i915#3591]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-dg1}: [SKIP][107] ([i915#1397]) -> [PASS][108] +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg1-19/igt@i915_pm_rpm@dpms-non-lpsp.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg1-15/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp:
- shard-rkl: [SKIP][109] ([i915#1397]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- {shard-dg2}: [SKIP][111] ([i915#1397]) -> [PASS][112] +2 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg2-11/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [FAIL][113] ([fdo#103375]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-1/igt@i915_suspend@basic-s3-without-i915.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-7/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-glk: [INCOMPLETE][115] ([i915#8680]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-glk2/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk2/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][117] ([i915#2346]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
- shard-glk: [FAIL][119] ([i915#2346]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-glk: [TIMEOUT][121] ([i915#8166]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@perf@non-zero-reason@0-rcs0:
- {shard-dg2}: [FAIL][123] ([i915#7757]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-8/igt@perf@non-zero-reason@0-rcs0.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg2-10/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@busy-double-start@vecs0:
- {shard-dg1}: [FAIL][125] ([i915#4349]) -> [PASS][126] +2 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg1-15/igt@perf_pmu@busy-double-start@vecs0.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-dg1-19/igt@perf_pmu@busy-double-start@vecs0.html
#### Warnings ####
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [FAIL][127] ([i915#4275]) -> [SKIP][128] ([fdo#109271])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl6/igt@i915_pm_dc@dc9-dpms.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-apl3/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][129] ([i915#3955]) -> [SKIP][130] ([fdo#110189] / [i915#3955]) +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4275]: https://gitlab.freedesktop.org/drm/intel/issues/4275
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5466]: https://gitlab.freedesktop.org/drm/intel/issues/5466
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5978]: https://gitlab.freedesktop.org/drm/intel/issues/5978
[i915#6032]: https://gitlab.freedesktop.org/drm/intel/issues/6032
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7356]: https://gitlab.freedesktop.org/drm/intel/issues/7356
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7757]: https://gitlab.freedesktop.org/drm/intel/issues/7757
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7862]: https://gitlab.freedesktop.org/drm/intel/issues/7862
[i915#7886]: https://gitlab.freedesktop.org/drm/intel/issues/7886
[i915#7892]: https://gitlab.freedesktop.org/drm/intel/issues/7892
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8166]: https://gitlab.freedesktop.org/drm/intel/issues/8166
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8304]: https://gitlab.freedesktop.org/drm/intel/issues/8304
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8621]: https://gitlab.freedesktop.org/drm/intel/issues/8621
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8680]: https://gitlab.freedesktop.org/drm/intel/issues/8680
[i915#8682]: https://gitlab.freedesktop.org/drm/intel/issues/8682
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7346 -> IGTPW_9243
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13309: af67b02abf56a5018cd885c94d7611241052e98f @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9243: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/index.html
IGT_7346: 29302a0d57bcf10cb553f5d7ff5bb99166a19bba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9243/index.html
[-- Attachment #2: Type: text/html, Size: 42897 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next
2023-06-23 3:24 [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next Ashutosh Dixit
2023-06-23 7:11 ` [igt-dev] ✓ Fi.CI.BAT: success for drm-uapi/xe_drm: Sync from drm-xe-next (rev2) Patchwork
2023-06-23 11:16 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
@ 2023-06-23 18:03 ` Kamil Konieczny
2023-06-23 18:24 ` Dixit, Ashutosh
2 siblings, 1 reply; 5+ messages in thread
From: Kamil Konieczny @ 2023-06-23 18:03 UTC (permalink / raw)
To: igt-dev
Hi Ashutosh,
On 2023-06-22 at 20:24:37 -0700, Ashutosh Dixit wrote:
> Our include/drm-uapi/xe_drm.h is from March. Pull in the latest xe_drm.h
> from drm-xe-next kernel branch. Generated after 'make headers_install'.
I checked xe_drm.h header and it is a little different. Am I
missing something ? There was also patch from Matthew Brost,
I will add him to Cc.
This is still better to have new header, so
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
>
> v2: Fix build break in tests/xe/xe_vm.c
>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
> include/drm-uapi/xe_drm.h | 315 +++++++++++++++++++++++++++-----------
> tests/xe/xe_vm.c | 2 +-
> 2 files changed, 224 insertions(+), 93 deletions(-)
>
> diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
> index 593b01ba5919..bcec0df6d115 100644
> --- a/include/drm-uapi/xe_drm.h
> +++ b/include/drm-uapi/xe_drm.h
> @@ -1,26 +1,6 @@
> +/* SPDX-License-Identifier: MIT */
> /*
> - * Copyright 2021 Intel Corporation. All Rights Reserved.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the
> - * "Software"), to deal in the Software without restriction, including
> - * without limitation the rights to use, copy, modify, merge, publish,
> - * distribute, sub license, and/or sell copies of the Software, and to
> - * permit persons to whom the Software is furnished to do so, subject to
> - * the following conditions:
> - *
> - * The above copyright notice and this permission notice (including the
> - * next paragraph) shall be included in all copies or substantial portions
> - * of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
> - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
> - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
> - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
> - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> - *
> + * Copyright © 2023 Intel Corporation
> */
>
> #ifndef _UAPI_XE_DRM_H_
> @@ -37,7 +17,7 @@ extern "C" {
> */
>
> /**
> - * struct i915_user_extension - Base class for defining a chain of extensions
> + * struct xe_user_extension - Base class for defining a chain of extensions
> *
> * Many interfaces need to grow over time. In most cases we can simply
> * extend the struct and have userspace pass in more data. Another option,
> @@ -55,20 +35,20 @@ extern "C" {
> *
> * .. code-block:: C
> *
> - * struct i915_user_extension ext3 {
> + * struct xe_user_extension ext3 {
> * .next_extension = 0, // end
> * .name = ...,
> * };
> - * struct i915_user_extension ext2 {
> + * struct xe_user_extension ext2 {
> * .next_extension = (uintptr_t)&ext3,
> * .name = ...,
> * };
> - * struct i915_user_extension ext1 {
> + * struct xe_user_extension ext1 {
> * .next_extension = (uintptr_t)&ext2,
> * .name = ...,
> * };
> *
> - * Typically the struct i915_user_extension would be embedded in some uAPI
> + * Typically the struct xe_user_extension would be embedded in some uAPI
> * struct, and in this case we would feed it the head of the chain(i.e ext1),
> * which would then apply all of the above extensions.
> *
> @@ -77,9 +57,10 @@ struct xe_user_extension {
> /**
> * @next_extension:
> *
> - * Pointer to the next struct i915_user_extension, or zero if the end.
> + * Pointer to the next struct xe_user_extension, or zero if the end.
> */
> __u64 next_extension;
> +
> /**
> * @name: Name of the extension.
> *
> @@ -87,11 +68,12 @@ struct xe_user_extension {
> *
> * Also note that the name space for this is not global for the whole
> * driver, but rather its scope/meaning is limited to the specific piece
> - * of uAPI which has embedded the struct i915_user_extension.
> + * of uAPI which has embedded the struct xe_user_extension.
> */
> __u32 name;
> +
> /**
> - * @flags: MBZ
> + * @pad: MBZ
> *
> * All undefined bits must be zero.
> */
> @@ -99,7 +81,7 @@ struct xe_user_extension {
> };
>
> /*
> - * i915 specific ioctls.
> + * xe specific ioctls.
> *
> * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
> * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
> @@ -125,40 +107,32 @@ struct xe_user_extension {
> #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)
> #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)
> #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
> -#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
> -#define DRM_IOCTL_XE_VM_BIND DRM_IOW( DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
> +#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
> +#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
> #define DRM_IOCTL_XE_ENGINE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_CREATE, struct drm_xe_engine_create)
> #define DRM_IOCTL_XE_ENGINE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_GET_PROPERTY, struct drm_xe_engine_get_property)
> -#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy)
> -#define DRM_IOCTL_XE_EXEC DRM_IOW( DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
> +#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy)
> +#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
> #define DRM_IOCTL_XE_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_MMIO, struct drm_xe_mmio)
> -#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property)
> +#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property)
> #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
> -#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW( DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
> -
> -struct drm_xe_engine_class_instance {
> - __u16 engine_class;
> -
> -#define DRM_XE_ENGINE_CLASS_RENDER 0
> -#define DRM_XE_ENGINE_CLASS_COPY 1
> -#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
> -#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
> -#define DRM_XE_ENGINE_CLASS_COMPUTE 4
> - /*
> - * Kernel only class (not actual hardware engine class). Used for
> - * creating ordered queues of VM bind operations.
> - */
> -#define DRM_XE_ENGINE_CLASS_VM_BIND 5
> -
> - __u16 engine_instance;
> - __u16 gt_id;
> -};
> +#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
>
> #define XE_MEM_REGION_CLASS_SYSMEM 0
> #define XE_MEM_REGION_CLASS_VRAM 1
>
> +/**
> + * struct drm_xe_query_mem_usage - describe memory regions and usage
> + *
> + * If a query is made with a struct drm_xe_device_query where .query
> + * is equal to DRM_XE_DEVICE_QUERY_MEM_USAGE, then the reply uses
> + * struct drm_xe_query_mem_usage in .data.
> + */
> struct drm_xe_query_mem_usage {
> + /** @num_params: number of memory regions returned in regions */
> __u32 num_regions;
> +
> + /** @pad: MBZ */
> __u32 pad;
>
> struct drm_xe_query_mem_region {
> @@ -173,9 +147,20 @@ struct drm_xe_query_mem_usage {
> } regions[];
> };
>
> +/**
> + * struct drm_xe_query_config - describe the device configuration
> + *
> + * If a query is made with a struct drm_xe_device_query where .query
> + * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses
> + * struct drm_xe_query_config in .data.
> + */
> struct drm_xe_query_config {
> + /** @num_params: number of parameters returned in info */
> __u32 num_params;
> +
> + /** @pad: MBZ */
> __u32 pad;
> +
> #define XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
> #define XE_QUERY_CONFIG_FLAGS 1
> #define XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0)
> @@ -184,12 +169,24 @@ struct drm_xe_query_config {
> #define XE_QUERY_CONFIG_VA_BITS 3
> #define XE_QUERY_CONFIG_GT_COUNT 4
> #define XE_QUERY_CONFIG_MEM_REGION_COUNT 5
> -#define XE_QUERY_CONFIG_NUM_PARAM XE_QUERY_CONFIG_MEM_REGION_COUNT + 1
> +#define XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY 6
> +#define XE_QUERY_CONFIG_NUM_PARAM (XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY + 1)
> + /** @info: array of elements containing the config info */
> __u64 info[];
> };
>
> +/**
> + * struct drm_xe_query_gts - describe GTs
> + *
> + * If a query is made with a struct drm_xe_device_query where .query
> + * is equal to DRM_XE_DEVICE_QUERY_GTS, then the reply uses struct
> + * drm_xe_query_gts in .data.
> + */
> struct drm_xe_query_gts {
> + /** @num_gt: number of GTs returned in gts */
> __u32 num_gt;
> +
> + /** @pad: MBZ */
> __u32 pad;
>
> /*
> @@ -212,15 +209,46 @@ struct drm_xe_query_gts {
> } gts[];
> };
>
> +/**
> + * struct drm_xe_query_topology_mask - describe the topology mask of a GT
> + *
> + * This is the hardware topology which reflects the internal physical
> + * structure of the GPU.
> + *
> + * If a query is made with a struct drm_xe_device_query where .query
> + * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses
> + * struct drm_xe_query_topology_mask in .data.
> + */
> struct drm_xe_query_topology_mask {
> /** @gt_id: GT ID the mask is associated with */
> __u16 gt_id;
>
> - /** @type: type of mask */
> - __u16 type;
> + /*
> + * To query the mask of Dual Sub Slices (DSS) available for geometry
> + * operations. For example a query response containing the following
> + * in mask:
> + * DSS_GEOMETRY ff ff ff ff 00 00 00 00
> + * means 32 DSS are available for geometry.
> + */
> #define XE_TOPO_DSS_GEOMETRY (1 << 0)
> + /*
> + * To query the mask of Dual Sub Slices (DSS) available for compute
> + * operations. For example a query response containing the following
> + * in mask:
> + * DSS_COMPUTE ff ff ff ff 00 00 00 00
> + * means 32 DSS are available for compute.
> + */
> #define XE_TOPO_DSS_COMPUTE (1 << 1)
> + /*
> + * To query the mask of Execution Units (EU) available per Dual Sub
> + * Slices (DSS). For example a query response containing the following
> + * in mask:
> + * EU_PER_DSS ff ff 00 00 00 00 00 00
> + * means each DSS has 16 EU.
> + */
> #define XE_TOPO_EU_PER_DSS (1 << 2)
> + /** @type: type of mask */
> + __u16 type;
>
> /** @num_bytes: number of bytes in requested mask */
> __u32 num_bytes;
> @@ -229,19 +257,53 @@ struct drm_xe_query_topology_mask {
> __u8 mask[];
> };
>
> +/**
> + * struct drm_xe_device_query - main structure to query device information
> + *
> + * If size is set to 0, the driver fills it with the required size for the
> + * requested type of data to query. If size is equal to the required size,
> + * the queried information is copied into data.
> + *
> + * For example the following code snippet allows retrieving and printing
> + * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
> + *
> + * .. code-block:: C
> + *
> + * struct drm_xe_engine_class_instance *hwe;
> + * struct drm_xe_device_query query = {
> + * .extensions = 0,
> + * .query = DRM_XE_DEVICE_QUERY_ENGINES,
> + * .size = 0,
> + * .data = 0,
> + * };
> + * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
> + * hwe = malloc(query.size);
> + * query.data = (uintptr_t)hwe;
> + * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
> + * int num_engines = query.size / sizeof(*hwe);
> + * for (int i = 0; i < num_engines; i++) {
> + * printf("Engine %d: %s\n", i,
> + * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER":
> + * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY":
> + * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE":
> + * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE":
> + * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE":
> + * "UNKNOWN");
> + * }
> + * free(hwe);
> + */
> struct drm_xe_device_query {
> /** @extensions: Pointer to the first extension struct, if any */
> __u64 extensions;
>
> - /** @query: The type of data to query */
> - __u32 query;
> -
> #define DRM_XE_DEVICE_QUERY_ENGINES 0
> #define DRM_XE_DEVICE_QUERY_MEM_USAGE 1
> #define DRM_XE_DEVICE_QUERY_CONFIG 2
> #define DRM_XE_DEVICE_QUERY_GTS 3
> #define DRM_XE_DEVICE_QUERY_HWCONFIG 4
> #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
> + /** @query: The type of data to query */
> + __u32 query;
>
> /** @size: Size of the queried data */
> __u32 size;
> @@ -264,12 +326,12 @@ struct drm_xe_gem_create {
> */
> __u64 size;
>
> +#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
> +#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
> /**
> * @flags: Flags, currently a mask of memory instances of where BO can
> * be placed
> */
> -#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
> -#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
> __u32 flags;
>
> /**
> @@ -290,6 +352,9 @@ struct drm_xe_gem_create {
> */
> __u32 handle;
>
> + /** @pad: MBZ */
> + __u32 pad;
> +
> /** @reserved: Reserved */
> __u64 reserved[2];
> };
> @@ -317,10 +382,13 @@ struct drm_xe_gem_mmap_offset {
> struct drm_xe_vm_bind_op_error_capture {
> /** @error: errno that occured */
> __s32 error;
> +
> /** @op: operation that encounter an error */
> __u32 op;
> +
> /** @addr: address of bind op */
> __u64 addr;
> +
> /** @size: size of bind */
> __u64 size;
> };
> @@ -330,10 +398,13 @@ struct drm_xe_ext_vm_set_property {
> /** @base: base user extension */
> struct xe_user_extension base;
>
> - /** @property: property to set */
> #define XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS 0
> + /** @property: property to set */
> __u32 property;
>
> + /** @pad: MBZ */
> + __u32 pad;
> +
> /** @value: property value */
> __u64 value;
>
> @@ -342,17 +413,16 @@ struct drm_xe_ext_vm_set_property {
> };
>
> struct drm_xe_vm_create {
> - /** @extensions: Pointer to the first extension struct, if any */
> #define XE_VM_EXTENSION_SET_PROPERTY 0
> + /** @extensions: Pointer to the first extension struct, if any */
> __u64 extensions;
>
> - /** @flags: Flags */
> - __u32 flags;
> -
> #define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0)
> #define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1)
> #define DRM_XE_VM_CREATE_ASYNC_BIND_OPS (0x1 << 2)
> #define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3)
> + /** @flags: Flags */
> + __u32 flags;
>
> /** @vm_id: Returned VM ID */
> __u32 vm_id;
> @@ -378,12 +448,16 @@ struct drm_xe_vm_bind_op {
> */
> __u32 obj;
>
> + /** @pad: MBZ */
> + __u32 pad;
> +
> union {
> /**
> * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE,
> * ignored for unbind
> */
> __u64 obj_offset;
> +
> /** @userptr: user pointer to bind on */
> __u64 userptr;
> };
> @@ -397,16 +471,10 @@ struct drm_xe_vm_bind_op {
> __u64 addr;
>
> /**
> - * @gt_mask: Mask for which GTs to create binds for, 0 == All GTs,
> + * @tile_mask: Mask for which tiles to create binds for, 0 == All tiles,
> * only applies to creating new VMAs
> */
> - __u64 gt_mask;
> -
> - /** @op: Operation to perform (lower 16 bits) and flags (upper 16 bits) */
> - __u32 op;
> -
> - /** @mem_region: Memory region to prefetch VMA to, instance not a mask */
> - __u32 region;
> + __u64 tile_mask;
>
> #define XE_VM_BIND_OP_MAP 0x0
> #define XE_VM_BIND_OP_UNMAP 0x1
> @@ -427,8 +495,8 @@ struct drm_xe_vm_bind_op {
> * If this flag is clear and the IOCTL doesn't return an error, in
> * practice the bind op is good and will complete.
> *
> - * If this flag is set and doesn't return return an error, the bind op
> - * can still fail and recovery is needed. If configured, the bind op that
> + * If this flag is set and doesn't return an error, the bind op can
> + * still fail and recovery is needed. If configured, the bind op that
> * caused the error will be captured in drm_xe_vm_bind_op_error_capture.
> * Once the user sees the error (via a ufence +
> * XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS), it should free memory
> @@ -446,6 +514,19 @@ struct drm_xe_vm_bind_op {
> * than differing the MAP to the page fault handler.
> */
> #define XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 18)
> + /*
> + * When the NULL flag is set, the page tables are setup with a special
> + * bit which indicates writes are dropped and all reads return zero. In
> + * the future, the NULL flags will only be valid for XE_VM_BIND_OP_MAP
> + * operations, the BO handle MBZ, and the BO offset MBZ. This flag is
> + * intended to implement VK sparse bindings.
> + */
> +#define XE_VM_BIND_FLAG_NULL (0x1 << 19)
> + /** @op: Operation to perform (lower 16 bits) and flags (upper 16 bits) */
> + __u32 op;
> +
> + /** @mem_region: Memory region to prefetch VMA to, instance not a mask */
> + __u32 region;
>
> /** @reserved: Reserved */
> __u64 reserved[2];
> @@ -468,9 +549,13 @@ struct drm_xe_vm_bind {
> /** @num_binds: number of binds in this IOCTL */
> __u32 num_binds;
>
> + /** @pad: MBZ */
> + __u32 pad;
> +
> union {
> /** @bind: used if num_binds == 1 */
> struct drm_xe_vm_bind_op bind;
> +
> /**
> * @vector_of_binds: userptr to array of struct
> * drm_xe_vm_bind_op if num_binds > 1
> @@ -481,6 +566,9 @@ struct drm_xe_vm_bind {
> /** @num_syncs: amount of syncs to wait on */
> __u32 num_syncs;
>
> + /** @pad2: MBZ */
> + __u32 pad2;
> +
> /** @syncs: pointer to struct drm_xe_sync array */
> __u64 syncs;
>
> @@ -496,6 +584,9 @@ struct drm_xe_ext_engine_set_property {
> /** @property: property to set */
> __u32 property;
>
> + /** @pad: MBZ */
> + __u32 pad;
> +
> /** @value: property value */
> __u64 value;
> };
> @@ -512,7 +603,6 @@ struct drm_xe_engine_set_property {
> /** @engine_id: Engine ID */
> __u32 engine_id;
>
> - /** @property: property to set */
> #define XE_ENGINE_SET_PROPERTY_PRIORITY 0
> #define XE_ENGINE_SET_PROPERTY_TIMESLICE 1
> #define XE_ENGINE_SET_PROPERTY_PREEMPTION_TIMEOUT 2
> @@ -528,6 +618,7 @@ struct drm_xe_engine_set_property {
> #define XE_ENGINE_SET_PROPERTY_ACC_TRIGGER 6
> #define XE_ENGINE_SET_PROPERTY_ACC_NOTIFY 7
> #define XE_ENGINE_SET_PROPERTY_ACC_GRANULARITY 8
> + /** @property: property to set */
> __u32 property;
>
> /** @value: property value */
> @@ -537,9 +628,27 @@ struct drm_xe_engine_set_property {
> __u64 reserved[2];
> };
>
> +/** struct drm_xe_engine_class_instance - instance of an engine class */
> +struct drm_xe_engine_class_instance {
> +#define DRM_XE_ENGINE_CLASS_RENDER 0
> +#define DRM_XE_ENGINE_CLASS_COPY 1
> +#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
> +#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
> +#define DRM_XE_ENGINE_CLASS_COMPUTE 4
> + /*
> + * Kernel only class (not actual hardware engine class). Used for
> + * creating ordered queues of VM bind operations.
> + */
> +#define DRM_XE_ENGINE_CLASS_VM_BIND 5
> + __u16 engine_class;
> +
> + __u16 engine_instance;
> + __u16 gt_id;
> +};
> +
> struct drm_xe_engine_create {
> - /** @extensions: Pointer to the first extension struct, if any */
> #define XE_ENGINE_EXTENSION_SET_PROPERTY 0
> + /** @extensions: Pointer to the first extension struct, if any */
> __u64 extensions;
>
> /** @width: submission width (number BB per exec) for this engine */
> @@ -577,8 +686,8 @@ struct drm_xe_engine_get_property {
> /** @engine_id: Engine ID */
> __u32 engine_id;
>
> - /** @property: property to get */
> #define XE_ENGINE_GET_PROPERTY_BAN 0
> + /** @property: property to get */
> __u32 property;
>
> /** @value: property value */
> @@ -603,16 +712,19 @@ struct drm_xe_sync {
> /** @extensions: Pointer to the first extension struct, if any */
> __u64 extensions;
>
> - __u32 flags;
> -
> #define DRM_XE_SYNC_SYNCOBJ 0x0
> #define DRM_XE_SYNC_TIMELINE_SYNCOBJ 0x1
> #define DRM_XE_SYNC_DMA_BUF 0x2
> #define DRM_XE_SYNC_USER_FENCE 0x3
> #define DRM_XE_SYNC_SIGNAL 0x10
> + __u32 flags;
> +
> + /** @pad: MBZ */
> + __u32 pad;
>
> union {
> __u32 handle;
> +
> /**
> * @addr: Address of user fence. When sync passed in via exec
> * IOCTL this a GPU address in the VM. When sync passed in via
> @@ -644,9 +756,9 @@ struct drm_xe_exec {
> __u64 syncs;
>
> /**
> - * @address: address of batch buffer if num_batch_buffer == 1 or an
> - * array of batch buffer addresses
> - */
> + * @address: address of batch buffer if num_batch_buffer == 1 or an
> + * array of batch buffer addresses
> + */
> __u64 address;
>
> /**
> @@ -655,6 +767,9 @@ struct drm_xe_exec {
> */
> __u16 num_batch_buffer;
>
> + /** @pad: MBZ */
> + __u16 pad[3];
> +
> /** @reserved: Reserved */
> __u64 reserved[2];
> };
> @@ -665,8 +780,6 @@ struct drm_xe_mmio {
>
> __u32 addr;
>
> - __u32 flags;
> -
> #define DRM_XE_MMIO_8BIT 0x0
> #define DRM_XE_MMIO_16BIT 0x1
> #define DRM_XE_MMIO_32BIT 0x2
> @@ -674,6 +787,7 @@ struct drm_xe_mmio {
> #define DRM_XE_MMIO_BITS_MASK 0x3
> #define DRM_XE_MMIO_READ 0x4
> #define DRM_XE_MMIO_WRITE 0x8
> + __u32 flags;
>
> __u64 value;
>
> @@ -693,45 +807,57 @@ struct drm_xe_mmio {
> struct drm_xe_wait_user_fence {
> /** @extensions: Pointer to the first extension struct, if any */
> __u64 extensions;
> +
> union {
> /**
> * @addr: user pointer address to wait on, must qword aligned
> */
> __u64 addr;
> +
> /**
> * @vm_id: The ID of the VM which encounter an error used with
> * DRM_XE_UFENCE_WAIT_VM_ERROR. Upper 32 bits must be clear.
> */
> __u64 vm_id;
> };
> - /** @op: wait operation (type of comparison) */
> +
> #define DRM_XE_UFENCE_WAIT_EQ 0
> #define DRM_XE_UFENCE_WAIT_NEQ 1
> #define DRM_XE_UFENCE_WAIT_GT 2
> #define DRM_XE_UFENCE_WAIT_GTE 3
> #define DRM_XE_UFENCE_WAIT_LT 4
> #define DRM_XE_UFENCE_WAIT_LTE 5
> + /** @op: wait operation (type of comparison) */
> __u16 op;
> - /** @flags: wait flags */
> +
> #define DRM_XE_UFENCE_WAIT_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */
> #define DRM_XE_UFENCE_WAIT_ABSTIME (1 << 1)
> #define DRM_XE_UFENCE_WAIT_VM_ERROR (1 << 2)
> + /** @flags: wait flags */
> __u16 flags;
> +
> + /** @pad: MBZ */
> + __u32 pad;
> +
> /** @value: compare value */
> __u64 value;
> - /** @mask: comparison mask */
> +
> #define DRM_XE_UFENCE_WAIT_U8 0xffu
> #define DRM_XE_UFENCE_WAIT_U16 0xffffu
> #define DRM_XE_UFENCE_WAIT_U32 0xffffffffu
> #define DRM_XE_UFENCE_WAIT_U64 0xffffffffffffffffu
> + /** @mask: comparison mask */
> __u64 mask;
> +
> /** @timeout: how long to wait before bailing, value in jiffies */
> __s64 timeout;
> +
> /**
> * @num_engines: number of engine instances to wait on, must be zero
> * when DRM_XE_UFENCE_WAIT_SOFT_OP set
> */
> __u64 num_engines;
> +
> /**
> * @instances: user pointer to array of drm_xe_engine_class_instance to
> * wait on, must be NULL when DRM_XE_UFENCE_WAIT_SOFT_OP set
> @@ -749,6 +875,9 @@ struct drm_xe_vm_madvise {
> /** @vm_id: The ID VM in which the VMA exists */
> __u32 vm_id;
>
> + /** @pad: MBZ */
> + __u32 pad;
> +
> /** @range: Number of bytes in the VMA */
> __u64 range;
>
> @@ -789,10 +918,12 @@ struct drm_xe_vm_madvise {
> #define DRM_XE_VMA_PRIORITY_HIGH 2 /* Must be elevated user */
> /* Pin the VMA in memory, must be elevated user */
> #define DRM_XE_VM_MADVISE_PIN 6
> -
> /** @property: property to set */
> __u32 property;
>
> + /** @pad2: MBZ */
> + __u32 pad2;
> +
> /** @value: property value */
> __u64 value;
>
> diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
> index 479ded70f29b..3c26e1ed799d 100644
> --- a/tests/xe/xe_vm.c
> +++ b/tests/xe/xe_vm.c
> @@ -892,7 +892,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
> bind_ops[i].obj_offset = 0;
> bind_ops[i].range = bo_size;
> bind_ops[i].addr = addr;
> - bind_ops[i].gt_mask = 0x1 << eci->gt_id;
> + bind_ops[i].tile_mask = 0x1 << eci->gt_id;
> bind_ops[i].op = XE_VM_BIND_OP_MAP | XE_VM_BIND_FLAG_ASYNC;
> bind_ops[i].region = 0;
> bind_ops[i].reserved[0] = 0;
> --
> 2.38.0
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next
2023-06-23 18:03 ` [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next Kamil Konieczny
@ 2023-06-23 18:24 ` Dixit, Ashutosh
0 siblings, 0 replies; 5+ messages in thread
From: Dixit, Ashutosh @ 2023-06-23 18:24 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev, Ashutosh Dixit, Matthew Brost
On Fri, 23 Jun 2023 11:03:33 -0700, Kamil Konieczny wrote:
>
Hi Kamil,
> On 2023-06-22 at 20:24:37 -0700, Ashutosh Dixit wrote:
> > Our include/drm-uapi/xe_drm.h is from March. Pull in the latest xe_drm.h
> > from drm-xe-next kernel branch. Generated after 'make headers_install'.
>
> I checked xe_drm.h header and it is a little different. Am I missing
> something ?
What is different? I just posted a v3 with Matt Auld's change to xe_drm.h
from yesterday. Apart from that the file is exactly the same as that in the
kernel, of course we need to do a 'make headers_install' before exposing to
userland.
> There was also patch from Matthew Brost, I will add him to Cc.
Not sure about this one either. Is this something in flight?
> This is still better to have new header, so
>
> Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Thanks, I'll wait till all these issues are addressed.
Thanks.
--
Ashutosh
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2023-06-23 3:24 [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next Ashutosh Dixit
2023-06-23 7:11 ` [igt-dev] ✓ Fi.CI.BAT: success for drm-uapi/xe_drm: Sync from drm-xe-next (rev2) Patchwork
2023-06-23 11:16 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2023-06-23 18:03 ` [igt-dev] [PATCH v2 i-g-t] drm-uapi/xe_drm: Sync from drm-xe-next Kamil Konieczny
2023-06-23 18:24 ` Dixit, Ashutosh
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