* [igt-dev] [PATCH i-g-t 0/2] Remove _v2 functions in gpu pipelines
@ 2020-05-29 10:41 Zbigniew Kempczyński
2020-05-29 10:41 ` [igt-dev] [PATCH i-g-t 1/2] lib/media_spin: localize pipeline functions Zbigniew Kempczyński
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Zbigniew Kempczyński @ 2020-05-29 10:41 UTC (permalink / raw)
To: igt-dev
Clean the code by removing libdrm version of the functions.
Due to some couplings in media_spin localize required once
in it allowing gpgpu_fill/media_fill/media_vme be cleaned.
Zbigniew Kempczyński (2):
lib/media_spin: localize pipeline functions
tests/gem_(gpgpu|media)_fill: remove the _v2 suffix
lib/gpgpu_fill.c | 304 +++--------
lib/gpgpu_fill.h | 83 +--
lib/gpu_cmds.c | 1015 +++++++----------------------------
lib/gpu_cmds.h | 165 +-----
lib/intel_batchbuffer.c | 56 +-
lib/intel_batchbuffer.h | 20 +-
lib/media_fill.c | 267 ++-------
lib/media_fill.h | 45 +-
lib/media_spin.c | 364 ++++++++++++-
tests/i915/gem_gpgpu_fill.c | 83 +--
tests/i915/gem_media_fill.c | 83 +--
11 files changed, 748 insertions(+), 1737 deletions(-)
--
2.26.0
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^ permalink raw reply [flat|nested] 8+ messages in thread* [igt-dev] [PATCH i-g-t 1/2] lib/media_spin: localize pipeline functions 2020-05-29 10:41 [igt-dev] [PATCH i-g-t 0/2] Remove _v2 functions in gpu pipelines Zbigniew Kempczyński @ 2020-05-29 10:41 ` Zbigniew Kempczyński 2020-05-29 10:41 ` [igt-dev] [PATCH i-g-t 2/2] tests/gem_(gpgpu|media)_fill: remove the _v2 suffix Zbigniew Kempczyński ` (3 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Zbigniew Kempczyński @ 2020-05-29 10:41 UTC (permalink / raw) To: igt-dev; +Cc: Chris Wilson To allow remove "_v2" suffix in functions add this not-fully-clean step and localize names. Some additional requirement is needed to fulfill its needs (passing batchbuffer from the caller side). Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- lib/media_spin.c | 364 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 363 insertions(+), 1 deletion(-) diff --git a/lib/media_spin.c b/lib/media_spin.c index 009c7806..d3d0c278 100644 --- a/lib/media_spin.c +++ b/lib/media_spin.c @@ -29,9 +29,10 @@ #include "intel_reg.h" #include "drmtest.h" #include "intel_batchbuffer.h" +#include "intel_chipset.h" +#include "gen7_media.h" #include "gen8_media.h" #include "media_spin.h" -#include "gpu_cmds.h" static const uint32_t spin_kernel[][4] = { { 0x00600001, 0x20800208, 0x008d0000, 0x00000000 }, /* mov (8)r4.0<1>:ud r0.0<8;8;1>:ud */ @@ -79,6 +80,366 @@ static const uint32_t spin_kernel[][4] = { #define xoffset 0 #define yoffset 0 +static void +gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end) +{ + int ret; + + ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer); + if (ret == 0) + ret = drm_intel_bo_mrb_exec(batch->bo, batch_end, + NULL, 0, 0, 0); + igt_assert(ret == 0); +} + +static uint32_t +gen7_fill_kernel(struct intel_batchbuffer *batch, + const uint32_t kernel[][4], size_t size) +{ + uint32_t offset; + + offset = intel_batchbuffer_copy_data(batch, kernel, size, 64); + + return offset; +} + +static uint32_t +gen7_fill_surface_state(struct intel_batchbuffer *batch, + const struct igt_buf *buf, + uint32_t format, + int is_dst) +{ + struct gen7_surface_state *ss; + uint32_t write_domain, read_domain, offset; + int ret; + + if (is_dst) { + write_domain = read_domain = I915_GEM_DOMAIN_RENDER; + } else { + write_domain = 0; + read_domain = I915_GEM_DOMAIN_SAMPLER; + } + + ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64); + offset = intel_batchbuffer_subdata_offset(batch, ss); + + ss->ss0.surface_type = SURFACE_2D; + ss->ss0.surface_format = format; + ss->ss0.render_cache_read_write = 1; + + if (buf->tiling == I915_TILING_X) + ss->ss0.tiled_mode = 2; + else if (buf->tiling == I915_TILING_Y) + ss->ss0.tiled_mode = 3; + + ss->ss1.base_addr = buf->bo->offset; + ret = drm_intel_bo_emit_reloc(batch->bo, + intel_batchbuffer_subdata_offset(batch, ss) + 4, + buf->bo, 0, + read_domain, write_domain); + igt_assert(ret == 0); + + ss->ss2.height = igt_buf_height(buf) - 1; + ss->ss2.width = igt_buf_width(buf) - 1; + + ss->ss3.pitch = buf->surface[0].stride - 1; + + ss->ss7.shader_chanel_select_r = 4; + ss->ss7.shader_chanel_select_g = 5; + ss->ss7.shader_chanel_select_b = 6; + ss->ss7.shader_chanel_select_a = 7; + + return offset; +} + +static uint32_t +gen8_fill_surface_state(struct intel_batchbuffer *batch, + const struct igt_buf *buf, + uint32_t format, + int is_dst) +{ + struct gen8_surface_state *ss; + uint32_t write_domain, read_domain, offset; + int ret; + + if (is_dst) { + write_domain = read_domain = I915_GEM_DOMAIN_RENDER; + } else { + write_domain = 0; + read_domain = I915_GEM_DOMAIN_SAMPLER; + } + + ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64); + offset = intel_batchbuffer_subdata_offset(batch, ss); + + ss->ss0.surface_type = SURFACE_2D; + ss->ss0.surface_format = format; + ss->ss0.render_cache_read_write = 1; + ss->ss0.vertical_alignment = 1; /* align 4 */ + ss->ss0.horizontal_alignment = 1; /* align 4 */ + + if (buf->tiling == I915_TILING_X) + ss->ss0.tiled_mode = 2; + else if (buf->tiling == I915_TILING_Y) + ss->ss0.tiled_mode = 3; + + ss->ss8.base_addr = buf->bo->offset; + + ret = drm_intel_bo_emit_reloc(batch->bo, + intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4, + buf->bo, 0, read_domain, write_domain); + igt_assert(ret == 0); + + ss->ss2.height = igt_buf_height(buf) - 1; + ss->ss2.width = igt_buf_width(buf) - 1; + ss->ss3.pitch = buf->surface[0].stride - 1; + + ss->ss7.shader_chanel_select_r = 4; + ss->ss7.shader_chanel_select_g = 5; + ss->ss7.shader_chanel_select_b = 6; + ss->ss7.shader_chanel_select_a = 7; + + return offset; +} + +static uint32_t +gen8_spin_curbe_buffer_data(struct intel_batchbuffer *batch, + uint32_t iters) +{ + uint32_t *curbe_buffer; + uint32_t offset; + + curbe_buffer = intel_batchbuffer_subdata_alloc(batch, 64, 64); + offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer); + *curbe_buffer = iters; + + return offset; +} + +static uint32_t +gen7_fill_binding_table(struct intel_batchbuffer *batch, + const struct igt_buf *dst) +{ + uint32_t *binding_table, offset; + + binding_table = intel_batchbuffer_subdata_alloc(batch, 32, 64); + offset = intel_batchbuffer_subdata_offset(batch, binding_table); + if (IS_GEN7(batch->devid)) + binding_table[0] = gen7_fill_surface_state(batch, dst, + SURFACEFORMAT_R8_UNORM, 1); + else + binding_table[0] = gen8_fill_surface_state(batch, dst, + SURFACEFORMAT_R8_UNORM, 1); + + return offset; +} + +static uint32_t +gen8_fill_interface_descriptor(struct intel_batchbuffer *batch, + const struct igt_buf *dst, + const uint32_t kernel[][4], + size_t size) +{ + struct gen8_interface_descriptor_data *idd; + uint32_t offset; + uint32_t binding_table_offset, kernel_offset; + + binding_table_offset = gen7_fill_binding_table(batch, dst); + kernel_offset = gen7_fill_kernel(batch, kernel, size); + + idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64); + offset = intel_batchbuffer_subdata_offset(batch, idd); + + idd->desc0.kernel_start_pointer = (kernel_offset >> 6); + + idd->desc2.single_program_flow = 1; + idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754; + + idd->desc3.sampler_count = 0; /* 0 samplers used */ + idd->desc3.sampler_state_pointer = 0; + + idd->desc4.binding_table_entry_count = 0; + idd->desc4.binding_table_pointer = (binding_table_offset >> 5); + + idd->desc5.constant_urb_entry_read_offset = 0; + idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */ + + idd->desc6.num_threads_in_tg = 1; + + return offset; +} + +static void +gen8_emit_state_base_address(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2)); + + /* general */ + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0); + + /* stateless data port */ + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); + + /* surface */ + OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY); + + /* dynamic */ + OUT_RELOC(batch->bo, + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, + 0, BASE_ADDRESS_MODIFY); + + /* indirect */ + OUT_BATCH(0); + OUT_BATCH(0); + + /* instruction */ + OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + BASE_ADDRESS_MODIFY); + + /* general state buffer size */ + OUT_BATCH(0xfffff000 | 1); + /* dynamic state buffer size */ + OUT_BATCH(1 << 12 | 1); + /* indirect object buffer size */ + OUT_BATCH(0xfffff000 | 1); + /* instruction buffer size, must set modify enable bit, otherwise it may + * result in GPU hang + */ + OUT_BATCH(1 << 12 | 1); +} + +static void +gen8_emit_vfe_state(struct intel_batchbuffer *batch, uint32_t threads, + uint32_t urb_entries, uint32_t urb_size, + uint32_t curbe_size) +{ + OUT_BATCH(GEN7_MEDIA_VFE_STATE | (9 - 2)); + + /* scratch buffer */ + OUT_BATCH(0); + OUT_BATCH(0); + + /* number of threads & urb entries */ + OUT_BATCH(threads << 16 | + urb_entries << 8); + + OUT_BATCH(0); + + /* urb entry size & curbe size */ + OUT_BATCH(urb_size << 16 | + curbe_size); + + /* scoreboard */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); +} + +static void +gen7_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer) +{ + OUT_BATCH(GEN7_MEDIA_CURBE_LOAD | (4 - 2)); + OUT_BATCH(0); + /* curbe total data length */ + OUT_BATCH(64); + /* curbe data start address, is relative to the dynamics base address */ + OUT_BATCH(curbe_buffer); +} + +static void +gen7_emit_interface_descriptor_load(struct intel_batchbuffer *batch, + uint32_t interface_descriptor) +{ + OUT_BATCH(GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2)); + OUT_BATCH(0); + /* interface descriptor data length */ + if (IS_GEN7(batch->devid)) + OUT_BATCH(sizeof(struct gen7_interface_descriptor_data)); + else + OUT_BATCH(sizeof(struct gen8_interface_descriptor_data)); + /* interface descriptor address, is relative to the dynamics base + * address + */ + OUT_BATCH(interface_descriptor); +} + +static void +gen8_emit_media_state_flush(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN8_MEDIA_STATE_FLUSH | (2 - 2)); + OUT_BATCH(0); +} + +static void +gen_emit_media_object(struct intel_batchbuffer *batch, + unsigned int xoff, unsigned int yoff) +{ + OUT_BATCH(GEN7_MEDIA_OBJECT | (8 - 2)); + + /* interface descriptor offset */ + OUT_BATCH(0); + + /* without indirect data */ + OUT_BATCH(0); + OUT_BATCH(0); + + /* scoreboard */ + OUT_BATCH(0); + OUT_BATCH(0); + + /* inline data (xoffset, yoffset) */ + OUT_BATCH(xoff); + OUT_BATCH(yoff); + if (AT_LEAST_GEN(batch->devid, 8) && !IS_CHERRYVIEW(batch->devid)) + gen8_emit_media_state_flush(batch); +} + +static void +gen9_emit_state_base_address(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (19 - 2)); + + /* general */ + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0); + + /* stateless data port */ + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); + + /* surface */ + OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY); + + /* dynamic */ + OUT_RELOC(batch->bo, + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, + 0, BASE_ADDRESS_MODIFY); + + /* indirect */ + OUT_BATCH(0); + OUT_BATCH(0); + + /* instruction */ + OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + BASE_ADDRESS_MODIFY); + + /* general state buffer size */ + OUT_BATCH(0xfffff000 | 1); + /* dynamic state buffer size */ + OUT_BATCH(1 << 12 | 1); + /* indirect object buffer size */ + OUT_BATCH(0xfffff000 | 1); + /* intruction buffer size, must set modify enable bit, otherwise it may + * result in GPU hang + */ + OUT_BATCH(1 << 12 | 1); + + /* Bindless surface state base address */ + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0); + OUT_BATCH(0xfffff000); +} + void gen8_media_spinfunc(struct intel_batchbuffer *batch, const struct igt_buf *dst, uint32_t spins) @@ -119,6 +480,7 @@ gen8_media_spinfunc(struct intel_batchbuffer *batch, intel_batchbuffer_reset(batch); } + void gen9_media_spinfunc(struct intel_batchbuffer *batch, const struct igt_buf *dst, uint32_t spins) -- 2.26.0 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/gem_(gpgpu|media)_fill: remove the _v2 suffix 2020-05-29 10:41 [igt-dev] [PATCH i-g-t 0/2] Remove _v2 functions in gpu pipelines Zbigniew Kempczyński 2020-05-29 10:41 ` [igt-dev] [PATCH i-g-t 1/2] lib/media_spin: localize pipeline functions Zbigniew Kempczyński @ 2020-05-29 10:41 ` Zbigniew Kempczyński 2020-05-29 11:07 ` [igt-dev] ✓ Fi.CI.BAT: success for Remove _v2 functions in gpu pipelines Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Zbigniew Kempczyński @ 2020-05-29 10:41 UTC (permalink / raw) To: igt-dev; +Cc: Chris Wilson Remove libdrm functions and replace them with new ones after removing _v2 suffix introduced for transition state. Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- lib/gpgpu_fill.c | 304 +++-------- lib/gpgpu_fill.h | 83 +-- lib/gpu_cmds.c | 1015 +++++++---------------------------- lib/gpu_cmds.h | 165 +----- lib/intel_batchbuffer.c | 56 +- lib/intel_batchbuffer.h | 20 +- lib/media_fill.c | 267 ++------- lib/media_fill.h | 45 +- tests/i915/gem_gpgpu_fill.c | 83 +-- tests/i915/gem_media_fill.c | 83 +-- 10 files changed, 385 insertions(+), 1736 deletions(-) diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c index 49988a36..aa2ffa8d 100644 --- a/lib/gpgpu_fill.c +++ b/lib/gpgpu_fill.c @@ -25,7 +25,6 @@ * Dominik Zeromski <dominik.zeromski@intel.com> */ -#include <intel_bufmgr.h> #include <i915_drm.h> #include "intel_reg.h" @@ -131,60 +130,11 @@ static const uint32_t gen12_gpgpu_kernel[][4] = { #define GEN7_VFE_STATE_GPGPU_MODE 1 void -gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, +gen7_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, uint8_t color) -{ - uint32_t curbe_buffer, interface_descriptor; - uint32_t batch_end; - - intel_batchbuffer_flush(batch); - - /* setup states */ - batch->ptr = &batch->buffer[BATCH_STATE_SPLIT]; - - /* - * const buffer needs to fill for every thread, but as we have just 1 - * thread per every group, so need only one curbe data. - * For each thread, just use thread group ID for buffer offset. - */ - curbe_buffer = gen7_fill_curbe_buffer_data(batch, color); - - interface_descriptor = gen7_fill_interface_descriptor(batch, dst, - gen7_gpgpu_kernel, sizeof(gen7_gpgpu_kernel)); - - igt_assert(batch->ptr < &batch->buffer[4095]); - - batch->ptr = batch->buffer; - - /* GPGPU pipeline */ - OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU); - - gen7_emit_state_base_address(batch); - gen7_emit_vfe_state(batch, THREADS, GEN7_GPGPU_URB_ENTRIES, - GPGPU_URB_SIZE, GPGPU_CURBE_SIZE, - GEN7_VFE_STATE_GPGPU_MODE); - gen7_emit_curbe_load(batch, curbe_buffer); - gen7_emit_interface_descriptor_load(batch, interface_descriptor); - gen7_emit_gpgpu_walk(batch, x, y, width, height); - - OUT_BATCH(MI_BATCH_BUFFER_END); - - batch_end = intel_batchbuffer_align(batch, 8); - igt_assert(batch_end < BATCH_STATE_SPLIT); - - gen7_render_flush(batch, batch_end); - intel_batchbuffer_reset(batch); -} - -void -gen7_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color) { struct intel_bb *ibb; uint32_t curbe_buffer, interface_descriptor; @@ -195,7 +145,7 @@ gen7_gpgpu_fillfunc_v2(int i915, intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT); /* Fill curbe buffer data */ - curbe_buffer = gen7_fill_curbe_buffer_data_v2(ibb, color); + curbe_buffer = gen7_fill_curbe_buffer_data(ibb, color); /* * const buffer needs to fill for every thread, but as we have just 1 @@ -203,22 +153,22 @@ gen7_gpgpu_fillfunc_v2(int i915, * For each thread, just use thread group ID for buffer offset. */ interface_descriptor = - gen7_fill_interface_descriptor_v2(ibb, buf, - gen7_gpgpu_kernel, - sizeof(gen7_gpgpu_kernel)); + gen7_fill_interface_descriptor(ibb, buf, + gen7_gpgpu_kernel, + sizeof(gen7_gpgpu_kernel)); intel_bb_ptr_set(ibb, 0); /* GPGPU pipeline */ intel_bb_out(ibb, GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU); - gen7_emit_state_base_address_v2(ibb); - gen7_emit_vfe_state_v2(ibb, THREADS, GEN7_GPGPU_URB_ENTRIES, + gen7_emit_state_base_address(ibb); + gen7_emit_vfe_state(ibb, THREADS, GEN7_GPGPU_URB_ENTRIES, GPGPU_URB_SIZE, GPGPU_CURBE_SIZE, GEN7_VFE_STATE_GPGPU_MODE); - gen7_emit_curbe_load_v2(ibb, curbe_buffer); - gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor); - gen7_emit_gpgpu_walk_v2(ibb, x, y, width, height); + gen7_emit_curbe_load(ibb, curbe_buffer); + gen7_emit_interface_descriptor_load(ibb, interface_descriptor); + gen7_emit_gpgpu_walk(ibb, x, y, width, height); intel_bb_out(ibb, MI_BATCH_BUFFER_END); intel_bb_ptr_align(ibb, 32); @@ -230,59 +180,11 @@ gen7_gpgpu_fillfunc_v2(int i915, } void -gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, +gen8_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, uint8_t color) -{ - uint32_t curbe_buffer, interface_descriptor; - uint32_t batch_end; - - intel_batchbuffer_flush(batch); - - /* setup states */ - batch->ptr = &batch->buffer[BATCH_STATE_SPLIT]; - - /* - * const buffer needs to fill for every thread, but as we have just 1 - * thread per every group, so need only one curbe data. - * For each thread, just use thread group ID for buffer offset. - */ - curbe_buffer = gen7_fill_curbe_buffer_data(batch, color); - - interface_descriptor = gen8_fill_interface_descriptor(batch, dst, - gen8_gpgpu_kernel, sizeof(gen8_gpgpu_kernel)); - - igt_assert(batch->ptr < &batch->buffer[4095]); - - batch->ptr = batch->buffer; - - /* GPGPU pipeline */ - OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU); - - gen8_emit_state_base_address(batch); - gen8_emit_vfe_state(batch, THREADS, GEN8_GPGPU_URB_ENTRIES, - GPGPU_URB_SIZE, GPGPU_CURBE_SIZE); - gen7_emit_curbe_load(batch, curbe_buffer); - gen7_emit_interface_descriptor_load(batch, interface_descriptor); - gen8_emit_gpgpu_walk(batch, x, y, width, height); - - OUT_BATCH(MI_BATCH_BUFFER_END); - - batch_end = intel_batchbuffer_align(batch, 8); - igt_assert(batch_end < BATCH_STATE_SPLIT); - - gen7_render_flush(batch, batch_end); - intel_batchbuffer_reset(batch); -} - -void -gen8_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color) { struct intel_bb *ibb; uint32_t curbe_buffer, interface_descriptor; @@ -297,9 +199,9 @@ gen8_gpgpu_fillfunc_v2(int i915, * thread per every group, so need only one curbe data. * For each thread, just use thread group ID for buffer offset. */ - curbe_buffer = gen7_fill_curbe_buffer_data_v2(ibb, color); + curbe_buffer = gen7_fill_curbe_buffer_data(ibb, color); - interface_descriptor = gen8_fill_interface_descriptor_v2(ibb, buf, + interface_descriptor = gen8_fill_interface_descriptor(ibb, buf, gen8_gpgpu_kernel, sizeof(gen8_gpgpu_kernel)); intel_bb_ptr_set(ibb, 0); @@ -307,14 +209,14 @@ gen8_gpgpu_fillfunc_v2(int i915, /* GPGPU pipeline */ intel_bb_out(ibb, GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU); - gen8_emit_state_base_address_v2(ibb); - gen8_emit_vfe_state_v2(ibb, THREADS, GEN8_GPGPU_URB_ENTRIES, - GPGPU_URB_SIZE, GPGPU_CURBE_SIZE); + gen8_emit_state_base_address(ibb); + gen8_emit_vfe_state(ibb, THREADS, GEN8_GPGPU_URB_ENTRIES, + GPGPU_URB_SIZE, GPGPU_CURBE_SIZE); - gen7_emit_curbe_load_v2(ibb, curbe_buffer); - gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor); + gen7_emit_curbe_load(ibb, curbe_buffer); + gen7_emit_interface_descriptor_load(ibb, interface_descriptor); - gen8_emit_gpgpu_walk_v2(ibb, x, y, width, height); + gen8_emit_gpgpu_walk(ibb, x, y, width, height); intel_bb_out(ibb, MI_BATCH_BUFFER_END); intel_bb_ptr_align(ibb, 32); @@ -326,63 +228,12 @@ gen8_gpgpu_fillfunc_v2(int i915, } static void -__gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color, const uint32_t kernel[][4], - size_t kernel_size) -{ - uint32_t curbe_buffer, interface_descriptor; - uint32_t batch_end; - - intel_batchbuffer_flush(batch); - - /* setup states */ - batch->ptr = &batch->buffer[BATCH_STATE_SPLIT]; - - /* - * const buffer needs to fill for every thread, but as we have just 1 - * thread per every group, so need only one curbe data. - * For each thread, just use thread group ID for buffer offset. - */ - curbe_buffer = gen7_fill_curbe_buffer_data(batch, color); - - interface_descriptor = gen8_fill_interface_descriptor(batch, dst, - kernel, kernel_size); - - igt_assert(batch->ptr < &batch->buffer[4095]); - - batch->ptr = batch->buffer; - - /* GPGPU pipeline */ - OUT_BATCH(GEN7_PIPELINE_SELECT | GEN9_PIPELINE_SELECTION_MASK | - PIPELINE_SELECT_GPGPU); - - gen9_emit_state_base_address(batch); - gen8_emit_vfe_state(batch, THREADS, GEN8_GPGPU_URB_ENTRIES, - GPGPU_URB_SIZE, GPGPU_CURBE_SIZE); - gen7_emit_curbe_load(batch, curbe_buffer); - gen7_emit_interface_descriptor_load(batch, interface_descriptor); - gen8_emit_gpgpu_walk(batch, x, y, width, height); - - OUT_BATCH(MI_BATCH_BUFFER_END); - - batch_end = intel_batchbuffer_align(batch, 8); - igt_assert(batch_end < BATCH_STATE_SPLIT); - - gen7_render_flush(batch, batch_end); - intel_batchbuffer_reset(batch); -} - - -static void -__gen9_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color, - const uint32_t kernel[][4], size_t kernel_size) +__gen9_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, + uint8_t color, + const uint32_t kernel[][4], size_t kernel_size) { struct intel_bb *ibb; uint32_t curbe_buffer, interface_descriptor; @@ -398,11 +249,11 @@ __gen9_gpgpu_fillfunc_v2(int i915, * For each thread, just use thread group ID for buffer offset. */ /* Fill curbe buffer data */ - curbe_buffer = gen7_fill_curbe_buffer_data_v2(ibb, color); + curbe_buffer = gen7_fill_curbe_buffer_data(ibb, color); - interface_descriptor = gen8_fill_interface_descriptor_v2(ibb, buf, - kernel, - kernel_size); + interface_descriptor = gen8_fill_interface_descriptor(ibb, buf, + kernel, + kernel_size); intel_bb_ptr_set(ibb, 0); @@ -410,15 +261,15 @@ __gen9_gpgpu_fillfunc_v2(int i915, intel_bb_out(ibb, GEN7_PIPELINE_SELECT | GEN9_PIPELINE_SELECTION_MASK | PIPELINE_SELECT_GPGPU); - gen9_emit_state_base_address_v2(ibb); + gen9_emit_state_base_address(ibb); - gen8_emit_vfe_state_v2(ibb, THREADS, GEN8_GPGPU_URB_ENTRIES, - GPGPU_URB_SIZE, GPGPU_CURBE_SIZE); + gen8_emit_vfe_state(ibb, THREADS, GEN8_GPGPU_URB_ENTRIES, + GPGPU_URB_SIZE, GPGPU_CURBE_SIZE); - gen7_emit_curbe_load_v2(ibb, curbe_buffer); - gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor); + gen7_emit_curbe_load(ibb, curbe_buffer); + gen7_emit_interface_descriptor_load(ibb, interface_descriptor); - gen8_emit_gpgpu_walk_v2(ibb, x, y, width, height); + gen8_emit_gpgpu_walk(ibb, x, y, width, height); intel_bb_out(ibb, MI_BATCH_BUFFER_END); intel_bb_ptr_align(ibb, 32); @@ -429,66 +280,35 @@ __gen9_gpgpu_fillfunc_v2(int i915, intel_bb_destroy(ibb); } -void gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, +void gen9_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, uint8_t color) { - __gen9_gpgpu_fillfunc(batch, dst, x, y, width, height, color, - gen9_gpgpu_kernel, sizeof(gen9_gpgpu_kernel)); -} - -void gen9_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color) -{ - __gen9_gpgpu_fillfunc_v2(i915, buf, x, y, width, height, color, - gen9_gpgpu_kernel, - sizeof(gen9_gpgpu_kernel)); + __gen9_gpgpu_fillfunc(i915, buf, x, y, width, height, color, + gen9_gpgpu_kernel, + sizeof(gen9_gpgpu_kernel)); } - -void gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, +void gen11_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, uint8_t color) { - __gen9_gpgpu_fillfunc(batch, dst, x, y, width, height, color, - gen11_gpgpu_kernel, sizeof(gen11_gpgpu_kernel)); + __gen9_gpgpu_fillfunc(i915, buf, x, y, width, height, color, + gen11_gpgpu_kernel, + sizeof(gen11_gpgpu_kernel)); } -void gen11_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color) -{ - __gen9_gpgpu_fillfunc_v2(i915, buf, x, y, width, height, color, - gen11_gpgpu_kernel, - sizeof(gen11_gpgpu_kernel)); -} - -void gen12_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, +void gen12_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, uint8_t color) { - __gen9_gpgpu_fillfunc(batch, dst, x, y, width, height, color, - gen12_gpgpu_kernel, sizeof(gen12_gpgpu_kernel)); -} - -void gen12_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color) -{ - __gen9_gpgpu_fillfunc_v2(i915, buf, x, y, width, height, color, - gen12_gpgpu_kernel, - sizeof(gen12_gpgpu_kernel)); + __gen9_gpgpu_fillfunc(i915, buf, x, y, width, height, color, + gen12_gpgpu_kernel, + sizeof(gen12_gpgpu_kernel)); } diff --git a/lib/gpgpu_fill.h b/lib/gpgpu_fill.h index a387732b..25abe1fa 100644 --- a/lib/gpgpu_fill.h +++ b/lib/gpgpu_fill.h @@ -27,75 +27,38 @@ #ifndef GPGPU_FILL_H #define GPGPU_FILL_H -#include "intel_batchbuffer.h" #include "intel_bufops.h" void -gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, +gen7_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, uint8_t color); void -gen7_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color); - -void -gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color); - -void -gen8_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color); - -void -gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, +gen8_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, uint8_t color); -void gen9_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color); - -void -gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color); - -void gen11_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color); +void gen9_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, + uint8_t color); -void -gen12_gpgpu_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color); +void gen11_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, + uint8_t color); -void -gen12_gpgpu_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color); +void gen12_gpgpu_fillfunc(int i915, + struct intel_buf *buf, + unsigned x, unsigned y, + unsigned width, unsigned height, + uint8_t color); #endif /* GPGPU_FILL_H */ diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c index 8c41d0f3..8c284eb1 100644 --- a/lib/gpu_cmds.c +++ b/lib/gpu_cmds.c @@ -24,773 +24,24 @@ #include "gpu_cmds.h" -void -gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end) -{ - int ret; - - ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer); - if (ret == 0) - ret = drm_intel_bo_mrb_exec(batch->bo, batch_end, - NULL, 0, 0, 0); - igt_assert(ret == 0); -} - -void -gen7_render_context_flush(struct intel_batchbuffer *batch, uint32_t batch_end) -{ - igt_assert_eq(drm_intel_bo_subdata(batch->bo, - 0, 4096, batch->buffer), - 0); - igt_assert_eq(drm_intel_gem_bo_context_exec(batch->bo, batch->ctx, - batch_end, 0), - 0); -} - -uint32_t -gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch, - uint8_t color) -{ - uint8_t *curbe_buffer; - uint32_t offset; - - curbe_buffer = intel_batchbuffer_subdata_alloc(batch, - sizeof(uint32_t) * 8, - 64); - offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer); - *curbe_buffer = color; - - return offset; -} - -uint32_t -gen11_fill_curbe_buffer_data(struct intel_bb *ibb) - -{ - uint32_t *curbe_buffer; - uint32_t offset; - - intel_bb_ptr_align(ibb, 64); - curbe_buffer = intel_bb_ptr(ibb); - offset = intel_bb_offset(ibb); - - *curbe_buffer++ = 0; - *curbe_buffer = 1; - intel_bb_ptr_add(ibb, 64); - - return offset; -} - -uint32_t -gen7_fill_surface_state(struct intel_batchbuffer *batch, - const struct igt_buf *buf, - uint32_t format, - int is_dst) -{ - struct gen7_surface_state *ss; - uint32_t write_domain, read_domain, offset; - int ret; - - if (is_dst) { - write_domain = read_domain = I915_GEM_DOMAIN_RENDER; - } else { - write_domain = 0; - read_domain = I915_GEM_DOMAIN_SAMPLER; - } - - ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64); - offset = intel_batchbuffer_subdata_offset(batch, ss); - - ss->ss0.surface_type = SURFACE_2D; - ss->ss0.surface_format = format; - ss->ss0.render_cache_read_write = 1; - - if (buf->tiling == I915_TILING_X) - ss->ss0.tiled_mode = 2; - else if (buf->tiling == I915_TILING_Y) - ss->ss0.tiled_mode = 3; - - ss->ss1.base_addr = buf->bo->offset; - ret = drm_intel_bo_emit_reloc(batch->bo, - intel_batchbuffer_subdata_offset(batch, ss) + 4, - buf->bo, 0, - read_domain, write_domain); - igt_assert(ret == 0); - - ss->ss2.height = igt_buf_height(buf) - 1; - ss->ss2.width = igt_buf_width(buf) - 1; - - ss->ss3.pitch = buf->surface[0].stride - 1; - - ss->ss7.shader_chanel_select_r = 4; - ss->ss7.shader_chanel_select_g = 5; - ss->ss7.shader_chanel_select_b = 6; - ss->ss7.shader_chanel_select_a = 7; - - return offset; -} - -uint32_t -gen7_fill_binding_table(struct intel_batchbuffer *batch, - const struct igt_buf *dst) -{ - uint32_t *binding_table, offset; - - binding_table = intel_batchbuffer_subdata_alloc(batch, 32, 64); - offset = intel_batchbuffer_subdata_offset(batch, binding_table); - if (IS_GEN7(batch->devid)) - binding_table[0] = gen7_fill_surface_state(batch, dst, - SURFACEFORMAT_R8_UNORM, 1); - else - binding_table[0] = gen8_fill_surface_state(batch, dst, - SURFACEFORMAT_R8_UNORM, 1); - - return offset; -} - -uint32_t -gen11_fill_binding_table(struct intel_bb *ibb, - const struct intel_buf *src, - const struct intel_buf *dst) -{ - uint32_t binding_table_offset; - uint32_t *binding_table; - - intel_bb_ptr_align(ibb, 64); - binding_table_offset = intel_bb_offset(ibb); - binding_table = intel_bb_ptr(ibb); - intel_bb_ptr_add(ibb, 64); - - binding_table[0] = gen11_fill_surface_state(ibb, src, - SURFACE_1D, - SURFACEFORMAT_R32G32B32A32_FLOAT, - 0, 0, 0); - binding_table[1] = gen11_fill_surface_state(ibb, dst, - SURFACE_BUFFER, - SURFACEFORMAT_RAW, - 1, 1, 1); - - return binding_table_offset; - -} - -uint32_t -gen7_fill_kernel(struct intel_batchbuffer *batch, - const uint32_t kernel[][4], - size_t size) -{ - uint32_t offset; - - offset = intel_batchbuffer_copy_data(batch, kernel, size, 64); - - return offset; -} - -uint32_t -gen7_fill_interface_descriptor(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - const uint32_t kernel[][4], - size_t size) -{ - struct gen7_interface_descriptor_data *idd; - uint32_t offset; - uint32_t binding_table_offset, kernel_offset; - - binding_table_offset = gen7_fill_binding_table(batch, dst); - kernel_offset = gen7_fill_kernel(batch, kernel, size); - - idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64); - offset = intel_batchbuffer_subdata_offset(batch, idd); - - idd->desc0.kernel_start_pointer = (kernel_offset >> 6); - - idd->desc1.single_program_flow = 1; - idd->desc1.floating_point_mode = GEN7_FLOATING_POINT_IEEE_754; - - idd->desc2.sampler_count = 0; /* 0 samplers used */ - idd->desc2.sampler_state_pointer = 0; - - idd->desc3.binding_table_entry_count = 0; - idd->desc3.binding_table_pointer = (binding_table_offset >> 5); - - idd->desc4.constant_urb_entry_read_offset = 0; - idd->desc4.constant_urb_entry_read_length = 1; /* grf 1 */ - - return offset; -} - -void -gen7_emit_state_base_address(struct intel_batchbuffer *batch) -{ - OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2)); - - /* general */ - OUT_BATCH(0); - - /* surface */ - OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, - BASE_ADDRESS_MODIFY); - - /* dynamic */ - OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, - BASE_ADDRESS_MODIFY); - - /* indirect */ - OUT_BATCH(0); - - /* instruction */ - OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, - BASE_ADDRESS_MODIFY); - - /* general/dynamic/indirect/instruction access Bound */ - OUT_BATCH(0); - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); - OUT_BATCH(0); - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); -} - -void -gen7_emit_vfe_state(struct intel_batchbuffer *batch, uint32_t threads, - uint32_t urb_entries, uint32_t urb_size, - uint32_t curbe_size, uint32_t mode) -{ - OUT_BATCH(GEN7_MEDIA_VFE_STATE | (8 - 2)); - - /* scratch buffer */ - OUT_BATCH(0); - - /* number of threads & urb entries */ - OUT_BATCH(threads << 16 | - urb_entries << 8 | - mode << 2); /* GPGPU vs media mode */ - - OUT_BATCH(0); - - /* urb entry size & curbe size */ - OUT_BATCH(urb_size << 16 | /* in 256 bits unit */ - curbe_size); /* in 256 bits unit */ - - /* scoreboard */ - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); -} - -void -gen7_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer) -{ - OUT_BATCH(GEN7_MEDIA_CURBE_LOAD | (4 - 2)); - OUT_BATCH(0); - /* curbe total data length */ - OUT_BATCH(64); - /* curbe data start address, is relative to the dynamics base address */ - OUT_BATCH(curbe_buffer); -} - -void -gen7_emit_interface_descriptor_load(struct intel_batchbuffer *batch, - uint32_t interface_descriptor) -{ - OUT_BATCH(GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2)); - OUT_BATCH(0); - /* interface descriptor data length */ - if (IS_GEN7(batch->devid)) - OUT_BATCH(sizeof(struct gen7_interface_descriptor_data)); - else - OUT_BATCH(sizeof(struct gen8_interface_descriptor_data)); - /* interface descriptor address, is relative to the dynamics base - * address - */ - OUT_BATCH(interface_descriptor); -} - -void -gen7_emit_media_objects(struct intel_batchbuffer *batch, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height) -{ - int i, j; - - for (i = 0; i < width / 16; i++) { - for (j = 0; j < height / 16; j++) { - gen_emit_media_object(batch, x + i * 16, y + j * 16); - } - } -} - -void -gen7_emit_gpgpu_walk(struct intel_batchbuffer *batch, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height) -{ - uint32_t x_dim, y_dim, tmp, right_mask; - - /* - * Simply do SIMD16 based dispatch, so every thread uses - * SIMD16 channels. - * - * Define our own thread group size, e.g 16x1 for every group, then - * will have 1 thread each group in SIMD16 dispatch. So thread - * width/height/depth are all 1. - * - * Then thread group X = width / 16 (aligned to 16) - * thread group Y = height; - */ - x_dim = (width + 15) / 16; - y_dim = height; - - tmp = width & 15; - if (tmp == 0) - right_mask = (1 << 16) - 1; - else - right_mask = (1 << tmp) - 1; - - OUT_BATCH(GEN7_GPGPU_WALKER | 9); - - /* interface descriptor offset */ - OUT_BATCH(0); - - /* SIMD size, thread w/h/d */ - OUT_BATCH(1 << 30 | /* SIMD16 */ - 0 << 16 | /* depth:1 */ - 0 << 8 | /* height:1 */ - 0); /* width:1 */ - - /* thread group X */ - OUT_BATCH(0); - OUT_BATCH(x_dim); - - /* thread group Y */ - OUT_BATCH(0); - OUT_BATCH(y_dim); - - /* thread group Z */ - OUT_BATCH(0); - OUT_BATCH(1); - - /* right mask */ - OUT_BATCH(right_mask); - - /* bottom mask, height 1, always 0xffffffff */ - OUT_BATCH(0xffffffff); -} - -uint32_t -gen8_spin_curbe_buffer_data(struct intel_batchbuffer *batch, - uint32_t iters) -{ - uint32_t *curbe_buffer; - uint32_t offset; - - curbe_buffer = intel_batchbuffer_subdata_alloc(batch, 64, 64); - offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer); - *curbe_buffer = iters; - - return offset; -} - -uint32_t -gen8_fill_surface_state(struct intel_batchbuffer *batch, - const struct igt_buf *buf, - uint32_t format, - int is_dst) -{ - struct gen8_surface_state *ss; - uint32_t write_domain, read_domain, offset; - int ret; - - if (is_dst) { - write_domain = read_domain = I915_GEM_DOMAIN_RENDER; - } else { - write_domain = 0; - read_domain = I915_GEM_DOMAIN_SAMPLER; - } - - ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64); - offset = intel_batchbuffer_subdata_offset(batch, ss); - - ss->ss0.surface_type = SURFACE_2D; - ss->ss0.surface_format = format; - ss->ss0.render_cache_read_write = 1; - ss->ss0.vertical_alignment = 1; /* align 4 */ - ss->ss0.horizontal_alignment = 1; /* align 4 */ - - if (buf->tiling == I915_TILING_X) - ss->ss0.tiled_mode = 2; - else if (buf->tiling == I915_TILING_Y) - ss->ss0.tiled_mode = 3; - - ss->ss8.base_addr = buf->bo->offset; - - ret = drm_intel_bo_emit_reloc(batch->bo, - intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4, - buf->bo, 0, read_domain, write_domain); - igt_assert(ret == 0); - - ss->ss2.height = igt_buf_height(buf) - 1; - ss->ss2.width = igt_buf_width(buf) - 1; - ss->ss3.pitch = buf->surface[0].stride - 1; - - ss->ss7.shader_chanel_select_r = 4; - ss->ss7.shader_chanel_select_g = 5; - ss->ss7.shader_chanel_select_b = 6; - ss->ss7.shader_chanel_select_a = 7; - - return offset; -} - -uint32_t -gen11_fill_surface_state(struct intel_bb *ibb, - const struct intel_buf *buf, - uint32_t surface_type, - uint32_t format, - uint32_t vertical_alignment, - uint32_t horizontal_alignment, - int is_dst) -{ - struct gen8_surface_state *ss; - uint32_t write_domain, read_domain, offset; - uint64_t address; - - if (is_dst) { - write_domain = read_domain = I915_GEM_DOMAIN_RENDER; - } else { - write_domain = 0; - read_domain = I915_GEM_DOMAIN_SAMPLER; - } - - intel_bb_ptr_align(ibb, 64); - offset = intel_bb_offset(ibb); - ss = intel_bb_ptr(ibb); - intel_bb_ptr_add(ibb, 64); - - ss->ss0.surface_type = surface_type; - ss->ss0.surface_format = format; - ss->ss0.render_cache_read_write = 1; - ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */ - ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */ - - if (buf->tiling == I915_TILING_X) - ss->ss0.tiled_mode = 2; - else if (buf->tiling == I915_TILING_Y) - ss->ss0.tiled_mode = 3; - else - ss->ss0.tiled_mode = 0; - - address = intel_bb_offset_reloc(ibb, buf->handle, - read_domain, write_domain, - offset + 4 * 8, 0x0); - - ss->ss8.base_addr = (uint32_t) address; - ss->ss9.base_addr_hi = address >> 32; - - if (is_dst) { - ss->ss1.memory_object_control = 2; - ss->ss2.height = 1; - ss->ss2.width = 95; - ss->ss3.pitch = 0; - ss->ss7.shader_chanel_select_r = 4; - ss->ss7.shader_chanel_select_g = 5; - ss->ss7.shader_chanel_select_b = 6; - ss->ss7.shader_chanel_select_a = 7; - } - else { - ss->ss1.qpitch = 4040; - ss->ss1.base_mip_level = 31; - ss->ss2.height = 9216; - ss->ss2.width = 1019; - ss->ss3.pitch = 64; - ss->ss5.mip_count = 2; - } - - return offset; -} - -uint32_t -gen8_fill_interface_descriptor(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - const uint32_t kernel[][4], - size_t size) -{ - struct gen8_interface_descriptor_data *idd; - uint32_t offset; - uint32_t binding_table_offset, kernel_offset; - - binding_table_offset = gen7_fill_binding_table(batch, dst); - kernel_offset = gen7_fill_kernel(batch, kernel, size); - - idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64); - offset = intel_batchbuffer_subdata_offset(batch, idd); - - idd->desc0.kernel_start_pointer = (kernel_offset >> 6); - - idd->desc2.single_program_flow = 1; - idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754; - - idd->desc3.sampler_count = 0; /* 0 samplers used */ - idd->desc3.sampler_state_pointer = 0; - - idd->desc4.binding_table_entry_count = 0; - idd->desc4.binding_table_pointer = (binding_table_offset >> 5); - - idd->desc5.constant_urb_entry_read_offset = 0; - idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */ - - idd->desc6.num_threads_in_tg = 1; - - return offset; -} - -static uint32_t -gen7_fill_kernel_v2(struct intel_bb *ibb, - const uint32_t kernel[][4], - size_t size); - -uint32_t -gen11_fill_interface_descriptor(struct intel_bb *ibb, - struct intel_buf *src, struct intel_buf *dst, - const uint32_t kernel[][4], - size_t size) -{ - struct gen8_interface_descriptor_data *idd; - uint32_t offset; - uint32_t binding_table_offset, kernel_offset; - - binding_table_offset = gen11_fill_binding_table(ibb, src, dst); - kernel_offset = gen7_fill_kernel_v2(ibb, kernel, size); - - intel_bb_ptr_align(ibb, 64); - idd = intel_bb_ptr(ibb); - offset = intel_bb_offset(ibb); - - idd->desc0.kernel_start_pointer = (kernel_offset >> 6); - - idd->desc2.single_program_flow = 1; - idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754; - - idd->desc3.sampler_count = 0; /* 0 samplers used */ - idd->desc3.sampler_state_pointer = 0; - - idd->desc4.binding_table_entry_count = 0; - idd->desc4.binding_table_pointer = (binding_table_offset >> 5); - - idd->desc5.constant_urb_entry_read_offset = 0; - idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */ - - idd->desc6.num_threads_in_tg = 1; - - return offset; -} - -void -gen8_emit_state_base_address(struct intel_batchbuffer *batch) -{ - OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2)); - - /* general */ - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); - OUT_BATCH(0); - - /* stateless data port */ - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); - - /* surface */ - OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY); - - /* dynamic */ - OUT_RELOC(batch->bo, - I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, - 0, BASE_ADDRESS_MODIFY); - - /* indirect */ - OUT_BATCH(0); - OUT_BATCH(0); - - /* instruction */ - OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, - BASE_ADDRESS_MODIFY); - - /* general state buffer size */ - OUT_BATCH(0xfffff000 | 1); - /* dynamic state buffer size */ - OUT_BATCH(1 << 12 | 1); - /* indirect object buffer size */ - OUT_BATCH(0xfffff000 | 1); - /* instruction buffer size, must set modify enable bit, otherwise it may - * result in GPU hang - */ - OUT_BATCH(1 << 12 | 1); -} - -void -gen8_emit_media_state_flush(struct intel_batchbuffer *batch) -{ - OUT_BATCH(GEN8_MEDIA_STATE_FLUSH | (2 - 2)); - OUT_BATCH(0); -} - -void -gen8_emit_vfe_state(struct intel_batchbuffer *batch, uint32_t threads, - uint32_t urb_entries, uint32_t urb_size, - uint32_t curbe_size) -{ - OUT_BATCH(GEN7_MEDIA_VFE_STATE | (9 - 2)); - - /* scratch buffer */ - OUT_BATCH(0); - OUT_BATCH(0); - - /* number of threads & urb entries */ - OUT_BATCH(threads << 16 | - urb_entries << 8); - - OUT_BATCH(0); - - /* urb entry size & curbe size */ - OUT_BATCH(urb_size << 16 | - curbe_size); - - /* scoreboard */ - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); -} - -void -gen8_emit_gpgpu_walk(struct intel_batchbuffer *batch, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height) -{ - uint32_t x_dim, y_dim, tmp, right_mask; - - /* - * Simply do SIMD16 based dispatch, so every thread uses - * SIMD16 channels. - * - * Define our own thread group size, e.g 16x1 for every group, then - * will have 1 thread each group in SIMD16 dispatch. So thread - * width/height/depth are all 1. - * - * Then thread group X = width / 16 (aligned to 16) - * thread group Y = height; - */ - x_dim = (width + 15) / 16; - y_dim = height; - - tmp = width & 15; - if (tmp == 0) - right_mask = (1 << 16) - 1; - else - right_mask = (1 << tmp) - 1; - - OUT_BATCH(GEN7_GPGPU_WALKER | 13); - - OUT_BATCH(0); /* kernel offset */ - OUT_BATCH(0); /* indirect data length */ - OUT_BATCH(0); /* indirect data offset */ - - /* SIMD size, thread w/h/d */ - OUT_BATCH(1 << 30 | /* SIMD16 */ - 0 << 16 | /* depth:1 */ - 0 << 8 | /* height:1 */ - 0); /* width:1 */ - - /* thread group X */ - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(x_dim); - - /* thread group Y */ - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(y_dim); - - /* thread group Z */ - OUT_BATCH(0); - OUT_BATCH(1); - - /* right mask */ - OUT_BATCH(right_mask); - - /* bottom mask, height 1, always 0xffffffff */ - OUT_BATCH(0xffffffff); -} - -void -gen_emit_media_object(struct intel_batchbuffer *batch, - unsigned int xoffset, unsigned int yoffset) -{ - OUT_BATCH(GEN7_MEDIA_OBJECT | (8 - 2)); - - /* interface descriptor offset */ - OUT_BATCH(0); - - /* without indirect data */ - OUT_BATCH(0); - OUT_BATCH(0); - - /* scoreboard */ - OUT_BATCH(0); - OUT_BATCH(0); - - /* inline data (xoffset, yoffset) */ - OUT_BATCH(xoffset); - OUT_BATCH(yoffset); - if (AT_LEAST_GEN(batch->devid, 8) && !IS_CHERRYVIEW(batch->devid)) - gen8_emit_media_state_flush(batch); -} - -void -gen9_emit_state_base_address(struct intel_batchbuffer *batch) +uint32_t +gen7_fill_curbe_buffer_data(struct intel_bb *ibb, uint8_t color) { - OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (19 - 2)); - - /* general */ - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); - OUT_BATCH(0); - - /* stateless data port */ - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); - - /* surface */ - OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY); - - /* dynamic */ - OUT_RELOC(batch->bo, - I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, - 0, BASE_ADDRESS_MODIFY); - - /* indirect */ - OUT_BATCH(0); - OUT_BATCH(0); + uint32_t *curbe_buffer; + uint32_t offset; - /* instruction */ - OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, - BASE_ADDRESS_MODIFY); + intel_bb_ptr_align(ibb, 64); + curbe_buffer = intel_bb_ptr(ibb); + offset = intel_bb_offset(ibb); - /* general state buffer size */ - OUT_BATCH(0xfffff000 | 1); - /* dynamic state buffer size */ - OUT_BATCH(1 << 12 | 1); - /* indirect object buffer size */ - OUT_BATCH(0xfffff000 | 1); - /* intruction buffer size, must set modify enable bit, otherwise it may - * result in GPU hang - */ - OUT_BATCH(1 << 12 | 1); + *curbe_buffer = color; + intel_bb_ptr_add(ibb, 32); - /* Bindless surface state base address */ - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); - OUT_BATCH(0); - OUT_BATCH(0xfffff000); + return offset; } -/* - * Here we start version of the gpgpu fill pipeline creation which is based - * on intel_bb. - */ uint32_t -gen7_fill_curbe_buffer_data_v2(struct intel_bb *ibb, uint8_t color) +gen11_fill_curbe_buffer_data(struct intel_bb *ibb) { uint32_t *curbe_buffer; uint32_t offset; @@ -799,16 +50,17 @@ gen7_fill_curbe_buffer_data_v2(struct intel_bb *ibb, uint8_t color) curbe_buffer = intel_bb_ptr(ibb); offset = intel_bb_offset(ibb); - *curbe_buffer = color; - intel_bb_ptr_add(ibb, 32); + *curbe_buffer++ = 0; + *curbe_buffer = 1; + intel_bb_ptr_add(ibb, 64); return offset; } static uint32_t -gen7_fill_kernel_v2(struct intel_bb *ibb, - const uint32_t kernel[][4], - size_t size) +gen7_fill_kernel(struct intel_bb *ibb, + const uint32_t kernel[][4], + size_t size) { uint32_t *kernel_dst; uint32_t offset; @@ -825,10 +77,10 @@ gen7_fill_kernel_v2(struct intel_bb *ibb, } static uint32_t -gen7_fill_surface_state_v2(struct intel_bb *ibb, - struct intel_buf *buf, - uint32_t format, - int is_dst) +gen7_fill_surface_state(struct intel_bb *ibb, + struct intel_buf *buf, + uint32_t format, + int is_dst) { struct gen7_surface_state *ss; uint32_t write_domain, read_domain, offset; @@ -875,10 +127,10 @@ gen7_fill_surface_state_v2(struct intel_bb *ibb, } static uint32_t -gen8_fill_surface_state_v2(struct intel_bb *ibb, - struct intel_buf *buf, - uint32_t format, - int is_dst) +gen8_fill_surface_state(struct intel_bb *ibb, + struct intel_buf *buf, + uint32_t format, + int is_dst) { struct gen8_surface_state *ss; uint32_t write_domain, read_domain, offset; @@ -927,8 +179,75 @@ gen8_fill_surface_state_v2(struct intel_bb *ibb, } static uint32_t -gen7_fill_binding_table_v2(struct intel_bb *ibb, - struct intel_buf *buf) +gen11_fill_surface_state(struct intel_bb *ibb, + const struct intel_buf *buf, + uint32_t surface_type, + uint32_t format, + uint32_t vertical_alignment, + uint32_t horizontal_alignment, + int is_dst) +{ + struct gen8_surface_state *ss; + uint32_t write_domain, read_domain, offset; + uint64_t address; + + if (is_dst) { + write_domain = read_domain = I915_GEM_DOMAIN_RENDER; + } else { + write_domain = 0; + read_domain = I915_GEM_DOMAIN_SAMPLER; + } + + intel_bb_ptr_align(ibb, 64); + offset = intel_bb_offset(ibb); + ss = intel_bb_ptr(ibb); + intel_bb_ptr_add(ibb, 64); + + ss->ss0.surface_type = surface_type; + ss->ss0.surface_format = format; + ss->ss0.render_cache_read_write = 1; + ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */ + ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */ + + if (buf->tiling == I915_TILING_X) + ss->ss0.tiled_mode = 2; + else if (buf->tiling == I915_TILING_Y) + ss->ss0.tiled_mode = 3; + else + ss->ss0.tiled_mode = 0; + + address = intel_bb_offset_reloc(ibb, buf->handle, + read_domain, write_domain, + offset + 4 * 8, 0x0); + + ss->ss8.base_addr = (uint32_t) address; + ss->ss9.base_addr_hi = address >> 32; + + if (is_dst) { + ss->ss1.memory_object_control = 2; + ss->ss2.height = 1; + ss->ss2.width = 95; + ss->ss3.pitch = 0; + ss->ss7.shader_chanel_select_r = 4; + ss->ss7.shader_chanel_select_g = 5; + ss->ss7.shader_chanel_select_b = 6; + ss->ss7.shader_chanel_select_a = 7; + } + else { + ss->ss1.qpitch = 4040; + ss->ss1.base_mip_level = 31; + ss->ss2.height = 9216; + ss->ss2.width = 1019; + ss->ss3.pitch = 64; + ss->ss5.mip_count = 2; + } + + return offset; +} + +static uint32_t +gen7_fill_binding_table(struct intel_bb *ibb, + struct intel_buf *buf) { uint32_t binding_table_offset; uint32_t *binding_table; @@ -940,28 +259,53 @@ gen7_fill_binding_table_v2(struct intel_bb *ibb, intel_bb_ptr_add(ibb, 64); if (IS_GEN7(devid)) - binding_table[0] = gen7_fill_surface_state_v2(ibb, buf, - SURFACEFORMAT_R8_UNORM, 1); + binding_table[0] = gen7_fill_surface_state(ibb, buf, + SURFACEFORMAT_R8_UNORM, 1); else - binding_table[0] = gen8_fill_surface_state_v2(ibb, buf, - SURFACEFORMAT_R8_UNORM, 1); + binding_table[0] = gen8_fill_surface_state(ibb, buf, + SURFACEFORMAT_R8_UNORM, 1); + + return binding_table_offset; +} + +static uint32_t +gen11_fill_binding_table(struct intel_bb *ibb, + const struct intel_buf *src, + const struct intel_buf *dst) +{ + uint32_t binding_table_offset; + uint32_t *binding_table; + + intel_bb_ptr_align(ibb, 64); + binding_table_offset = intel_bb_offset(ibb); + binding_table = intel_bb_ptr(ibb); + intel_bb_ptr_add(ibb, 64); + + binding_table[0] = gen11_fill_surface_state(ibb, src, + SURFACE_1D, + SURFACEFORMAT_R32G32B32A32_FLOAT, + 0, 0, 0); + binding_table[1] = gen11_fill_surface_state(ibb, dst, + SURFACE_BUFFER, + SURFACEFORMAT_RAW, + 1, 1, 1); return binding_table_offset; } uint32_t -gen7_fill_interface_descriptor_v2(struct intel_bb *ibb, - struct intel_buf *buf, - const uint32_t kernel[][4], - size_t size) +gen7_fill_interface_descriptor(struct intel_bb *ibb, + struct intel_buf *buf, + const uint32_t kernel[][4], + size_t size) { struct gen7_interface_descriptor_data *idd; uint32_t offset; uint32_t binding_table_offset, kernel_offset; - binding_table_offset = gen7_fill_binding_table_v2(ibb, buf); - kernel_offset = gen7_fill_kernel_v2(ibb, kernel, size); + binding_table_offset = gen7_fill_binding_table(ibb, buf); + kernel_offset = gen7_fill_kernel(ibb, kernel, size); intel_bb_ptr_align(ibb, 64); idd = intel_bb_ptr(ibb); @@ -987,17 +331,53 @@ gen7_fill_interface_descriptor_v2(struct intel_bb *ibb, } uint32_t -gen8_fill_interface_descriptor_v2(struct intel_bb *ibb, - struct intel_buf *buf, - const uint32_t kernel[][4], - size_t size) +gen8_fill_interface_descriptor(struct intel_bb *ibb, + struct intel_buf *buf, + const uint32_t kernel[][4], + size_t size) +{ + struct gen8_interface_descriptor_data *idd; + uint32_t offset; + uint32_t binding_table_offset, kernel_offset; + + binding_table_offset = gen7_fill_binding_table(ibb, buf); + kernel_offset = gen7_fill_kernel(ibb, kernel, size); + + intel_bb_ptr_align(ibb, 64); + idd = intel_bb_ptr(ibb); + offset = intel_bb_offset(ibb); + + idd->desc0.kernel_start_pointer = (kernel_offset >> 6); + + idd->desc2.single_program_flow = 1; + idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754; + + idd->desc3.sampler_count = 0; /* 0 samplers used */ + idd->desc3.sampler_state_pointer = 0; + + idd->desc4.binding_table_entry_count = 0; + idd->desc4.binding_table_pointer = (binding_table_offset >> 5); + + idd->desc5.constant_urb_entry_read_offset = 0; + idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */ + + idd->desc6.num_threads_in_tg = 1; + + return offset; +} + +uint32_t +gen11_fill_interface_descriptor(struct intel_bb *ibb, + struct intel_buf *src, struct intel_buf *dst, + const uint32_t kernel[][4], + size_t size) { struct gen8_interface_descriptor_data *idd; uint32_t offset; uint32_t binding_table_offset, kernel_offset; - binding_table_offset = gen7_fill_binding_table_v2(ibb, buf); - kernel_offset = gen7_fill_kernel_v2(ibb, kernel, size); + binding_table_offset = gen11_fill_binding_table(ibb, src, dst); + kernel_offset = gen7_fill_kernel(ibb, kernel, size); intel_bb_ptr_align(ibb, 64); idd = intel_bb_ptr(ibb); @@ -1023,7 +403,7 @@ gen8_fill_interface_descriptor_v2(struct intel_bb *ibb, } void -gen7_emit_state_base_address_v2(struct intel_bb *ibb) +gen7_emit_state_base_address(struct intel_bb *ibb) { intel_bb_out(ibb, GEN7_STATE_BASE_ADDRESS | (10 - 2)); @@ -1056,7 +436,7 @@ gen7_emit_state_base_address_v2(struct intel_bb *ibb) } void -gen8_emit_state_base_address_v2(struct intel_bb *ibb) +gen8_emit_state_base_address(struct intel_bb *ibb) { intel_bb_out(ibb, GEN8_STATE_BASE_ADDRESS | (16 - 2)); @@ -1101,9 +481,8 @@ gen8_emit_state_base_address_v2(struct intel_bb *ibb) intel_bb_out(ibb, 1 << 12 | 1); } - void -gen9_emit_state_base_address_v2(struct intel_bb *ibb) +gen9_emit_state_base_address(struct intel_bb *ibb) { intel_bb_out(ibb, GEN8_STATE_BASE_ADDRESS | (19 - 2)); @@ -1152,9 +531,9 @@ gen9_emit_state_base_address_v2(struct intel_bb *ibb) } void -gen7_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads, - uint32_t urb_entries, uint32_t urb_size, - uint32_t curbe_size, uint32_t mode) +gen7_emit_vfe_state(struct intel_bb *ibb, uint32_t threads, + uint32_t urb_entries, uint32_t urb_size, + uint32_t curbe_size, uint32_t mode) { intel_bb_out(ibb, GEN7_MEDIA_VFE_STATE | (8 - 2)); @@ -1179,9 +558,9 @@ gen7_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads, } void -gen8_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads, - uint32_t urb_entries, uint32_t urb_size, - uint32_t curbe_size) +gen8_emit_vfe_state(struct intel_bb *ibb, uint32_t threads, + uint32_t urb_entries, uint32_t urb_size, + uint32_t curbe_size) { intel_bb_out(ibb, GEN7_MEDIA_VFE_STATE | (9 - 2)); @@ -1204,7 +583,7 @@ gen8_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads, } void -gen7_emit_curbe_load_v2(struct intel_bb *ibb, uint32_t curbe_buffer) +gen7_emit_curbe_load(struct intel_bb *ibb, uint32_t curbe_buffer) { intel_bb_out(ibb, GEN7_MEDIA_CURBE_LOAD | (4 - 2)); intel_bb_out(ibb, 0); @@ -1215,8 +594,8 @@ gen7_emit_curbe_load_v2(struct intel_bb *ibb, uint32_t curbe_buffer) } void -gen7_emit_interface_descriptor_load_v2(struct intel_bb *ibb, - uint32_t interface_descriptor) +gen7_emit_interface_descriptor_load(struct intel_bb *ibb, + uint32_t interface_descriptor) { intel_bb_out(ibb, GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2)); intel_bb_out(ibb, 0); @@ -1232,9 +611,9 @@ gen7_emit_interface_descriptor_load_v2(struct intel_bb *ibb, } void -gen7_emit_gpgpu_walk_v2(struct intel_bb *ibb, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height) +gen7_emit_gpgpu_walk(struct intel_bb *ibb, + unsigned int x, unsigned int y, + unsigned int width, unsigned int height) { uint32_t x_dim, y_dim, tmp, right_mask; @@ -1289,9 +668,9 @@ gen7_emit_gpgpu_walk_v2(struct intel_bb *ibb, } void -gen8_emit_gpgpu_walk_v2(struct intel_bb *ibb, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height) +gen8_emit_gpgpu_walk(struct intel_bb *ibb, + unsigned int x, unsigned int y, + unsigned int width, unsigned int height) { uint32_t x_dim, y_dim, tmp, right_mask; @@ -1349,15 +728,15 @@ gen8_emit_gpgpu_walk_v2(struct intel_bb *ibb, } void -gen8_emit_media_state_flush_v2(struct intel_bb *ibb) +gen8_emit_media_state_flush(struct intel_bb *ibb) { intel_bb_out(ibb, GEN8_MEDIA_STATE_FLUSH | (2 - 2)); intel_bb_out(ibb, 0); } void -gen_emit_media_object_v2(struct intel_bb *ibb, - unsigned int xoffset, unsigned int yoffset) +gen_emit_media_object(struct intel_bb *ibb, + unsigned int xoffset, unsigned int yoffset) { intel_bb_out(ibb, GEN7_MEDIA_OBJECT | (8 - 2)); @@ -1376,17 +755,17 @@ gen_emit_media_object_v2(struct intel_bb *ibb, intel_bb_out(ibb, xoffset); intel_bb_out(ibb, yoffset); if (AT_LEAST_GEN(ibb->devid, 8) && !IS_CHERRYVIEW(ibb->devid)) - gen8_emit_media_state_flush_v2(ibb); + gen8_emit_media_state_flush(ibb); } void -gen7_emit_media_objects_v2(struct intel_bb *ibb, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height) +gen7_emit_media_objects(struct intel_bb *ibb, + unsigned int x, unsigned int y, + unsigned int width, unsigned int height) { int i, j; for (i = 0; i < width / 16; i++) for (j = 0; j < height / 16; j++) - gen_emit_media_object_v2(ibb, x + i * 16, y + j * 16); + gen_emit_media_object(ibb, x + i * 16, y + j * 16); } diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h index 64abc513..56f09b6e 100644 --- a/lib/gpu_cmds.h +++ b/lib/gpu_cmds.h @@ -25,7 +25,6 @@ #ifndef GPU_CMDS_H #define GPU_CMDS_H -#include <intel_bufmgr.h> #include <i915_drm.h> #include "media_fill.h" @@ -38,182 +37,74 @@ #include "intel_bufops.h" #include <assert.h> -void -gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end); - -void -gen7_render_context_flush(struct intel_batchbuffer *batch, uint32_t batch_end); - uint32_t -gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch, - uint8_t color); +gen7_fill_curbe_buffer_data(struct intel_bb *ibb, uint8_t color); uint32_t gen11_fill_curbe_buffer_data(struct intel_bb *ibb); uint32_t -gen7_fill_surface_state(struct intel_batchbuffer *batch, - const struct igt_buf *buf, - uint32_t format, - int is_dst); - -uint32_t -gen7_fill_binding_table(struct intel_batchbuffer *batch, - const struct igt_buf *dst); -uint32_t -gen11_fill_binding_table(struct intel_bb *ibb, - const struct intel_buf *src, - const struct intel_buf *dst); - -uint32_t -gen7_fill_kernel(struct intel_batchbuffer *batch, - const uint32_t kernel[][4], - size_t size); - -uint32_t -gen7_fill_interface_descriptor(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +gen7_fill_interface_descriptor(struct intel_bb *ibb, + struct intel_buf *buf, const uint32_t kernel[][4], size_t size); -void -gen7_emit_state_base_address(struct intel_batchbuffer *batch); - -void -gen7_emit_vfe_state(struct intel_batchbuffer *batch, uint32_t threads, - uint32_t urb_entries, uint32_t urb_size, - uint32_t curbe_size, uint32_t mode); - -void -gen7_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer); - -void -gen7_emit_interface_descriptor_load(struct intel_batchbuffer *batch, - uint32_t interface_descriptor); - -void -gen7_emit_media_objects(struct intel_batchbuffer *batch, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height); - -void -gen7_emit_gpgpu_walk(struct intel_batchbuffer *batch, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height); - -uint32_t -gen8_spin_curbe_buffer_data(struct intel_batchbuffer *batch, - uint32_t iters); - -uint32_t -gen8_fill_surface_state(struct intel_batchbuffer *batch, - const struct igt_buf *buf, - uint32_t format, - int is_dst); -uint32_t -gen11_fill_surface_state(struct intel_bb *ibb, - const struct intel_buf *buf, - uint32_t surface_type, - uint32_t format, - uint32_t vertical_alignment, - uint32_t horizontal_alignment, - int is_dst); - uint32_t -gen8_fill_interface_descriptor(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +gen8_fill_interface_descriptor(struct intel_bb *ibb, + struct intel_buf *buf, const uint32_t kernel[][4], size_t size); + uint32_t gen11_fill_interface_descriptor(struct intel_bb *ibb, struct intel_buf *src, struct intel_buf *dst, const uint32_t kernel[][4], size_t size); -void -gen8_emit_state_base_address(struct intel_batchbuffer *batch); void -gen8_emit_media_state_flush(struct intel_batchbuffer *batch); +gen7_emit_state_base_address(struct intel_bb *ibb); void -gen8_emit_vfe_state(struct intel_batchbuffer *batch, uint32_t threads, - uint32_t urb_entries, uint32_t urb_size, - uint32_t curbe_size); +gen8_emit_state_base_address(struct intel_bb *ibb); void -gen8_emit_gpgpu_walk(struct intel_batchbuffer *batch, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height); - -void -gen_emit_media_object(struct intel_batchbuffer *batch, unsigned int xoffset, - unsigned int yoffset); +gen9_emit_state_base_address(struct intel_bb *ibb); void -gen9_emit_state_base_address(struct intel_batchbuffer *batch); - - -/* No libdrm */ -uint32_t -gen7_fill_curbe_buffer_data_v2(struct intel_bb *ibb, - uint8_t color); - -uint32_t -gen7_fill_interface_descriptor_v2(struct intel_bb *ibb, - struct intel_buf *buf, - const uint32_t kernel[][4], - size_t size); - -uint32_t -gen8_fill_interface_descriptor_v2(struct intel_bb *ibb, - struct intel_buf *buf, - const uint32_t kernel[][4], - size_t size); +gen7_emit_vfe_state(struct intel_bb *ibb, uint32_t threads, + uint32_t urb_entries, uint32_t urb_size, + uint32_t curbe_size, uint32_t mode); void -gen7_emit_state_base_address_v2(struct intel_bb *ibb); - +gen8_emit_vfe_state(struct intel_bb *ibb, uint32_t threads, + uint32_t urb_entries, uint32_t urb_size, + uint32_t curbe_size); void -gen8_emit_state_base_address_v2(struct intel_bb *ibb); +gen7_emit_curbe_load(struct intel_bb *ibb, uint32_t curbe_buffer); void -gen9_emit_state_base_address_v2(struct intel_bb *ibb); +gen7_emit_interface_descriptor_load(struct intel_bb *ibb, + uint32_t interface_descriptor); void -gen7_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads, - uint32_t urb_entries, uint32_t urb_size, - uint32_t curbe_size, uint32_t mode); +gen7_emit_gpgpu_walk(struct intel_bb *ibb, + unsigned int x, unsigned int y, + unsigned int width, unsigned int height); void -gen8_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads, - uint32_t urb_entries, uint32_t urb_size, - uint32_t curbe_size); -void -gen7_emit_curbe_load_v2(struct intel_bb *ibb, uint32_t curbe_buffer); +gen8_emit_gpgpu_walk(struct intel_bb *ibb, + unsigned int x, unsigned int y, + unsigned int width, unsigned int height); void -gen7_emit_interface_descriptor_load_v2(struct intel_bb *ibb, - uint32_t interface_descriptor); +gen8_emit_media_state_flush(struct intel_bb *ibb); void -gen7_emit_gpgpu_walk_v2(struct intel_bb *ibb, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height); +gen_emit_media_object(struct intel_bb *ibb, + unsigned int xoffset, unsigned int yoffset); void -gen8_emit_gpgpu_walk_v2(struct intel_bb *ibb, +gen7_emit_media_objects(struct intel_bb *ibb, unsigned int x, unsigned int y, unsigned int width, unsigned int height); - -void -gen8_emit_media_state_flush_v2(struct intel_bb *ibb); - -void -gen_emit_media_object_v2(struct intel_bb *ibb, - unsigned int xoffset, unsigned int yoffset); - -void -gen7_emit_media_objects_v2(struct intel_bb *ibb, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height); #endif /* GPU_CMDS_H */ diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index 02c293be..49f2d0fe 100644 --- a/lib/intel_batchbuffer.c +++ b/lib/intel_batchbuffer.c @@ -1118,32 +1118,6 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid) return fill; } - -/** - * igt_get_media_fillfunc_v2: - * @devid: pci device id - * - * Returns: - * - * The platform-specific media fill function pointer for the device specified - * with @devid. Will return NULL when no media fill function is implemented. - */ -igt_fillfunc_v2_t igt_get_media_fillfunc_v2(int devid) -{ - igt_fillfunc_v2_t fill = NULL; - - if (IS_GEN12(devid)) - fill = gen12_media_fillfunc_v2; - else if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid)) - fill = gen9_media_fillfunc_v2; - else if (IS_GEN8(devid)) - fill = gen8_media_fillfunc_v2; - else if (IS_GEN7(devid)) - fill = gen7_media_fillfunc_v2; - - return fill; -} - igt_vme_func_t igt_get_media_vme_func(int devid) { igt_vme_func_t fill = NULL; @@ -1153,6 +1127,7 @@ igt_vme_func_t igt_get_media_vme_func(int devid) return fill; } + /** * igt_get_gpgpu_fillfunc: * @devid: pci device id @@ -1168,7 +1143,7 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid) if (IS_GEN7(devid)) fill = gen7_gpgpu_fillfunc; - else if (IS_BROADWELL(devid)) + else if (IS_GEN8(devid)) fill = gen8_gpgpu_fillfunc; else if (IS_GEN9(devid) || IS_GEN10(devid)) fill = gen9_gpgpu_fillfunc; @@ -1180,33 +1155,6 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid) return fill; } -/** - * igt_get_gpgpu_fillfunc_v2: - * @devid: pci device id - * - * Returns: - * - * The platform-specific gpgpu fill function pointer for the device specified - * with @devid. Will return NULL when no gpgpu fill function is implemented. - */ -igt_fillfunc_v2_t igt_get_gpgpu_fillfunc_v2(int devid) -{ - igt_fillfunc_v2_t fill = NULL; - - if (IS_GEN7(devid)) - fill = gen7_gpgpu_fillfunc_v2; - else if (IS_GEN8(devid)) - fill = gen8_gpgpu_fillfunc_v2; - else if (IS_GEN9(devid) || IS_GEN10(devid)) - fill = gen9_gpgpu_fillfunc_v2; - else if (IS_GEN11(devid)) - fill = gen11_gpgpu_fillfunc_v2; - else if (IS_GEN12(devid)) - fill = gen12_gpgpu_fillfunc_v2; - - return fill; -} - /** * igt_get_media_spinfunc: * @devid: pci device id diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index 162e7f0c..ae052c17 100644 --- a/lib/intel_batchbuffer.h +++ b/lib/intel_batchbuffer.h @@ -370,8 +370,8 @@ igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid); /** * igt_fillfunc_t: - * @batch: batchbuffer object - * @dst: destination i-g-t buffer object + * @i915: drm fd + * @buf: destination intel_buf object * @x: destination pixel x-coordination * @y: destination pixel y-coordination * @width: width of the filled rectangle @@ -385,23 +385,15 @@ igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid); * A fill function will emit a batchbuffer to the kernel which executes * the specified blit fill operation using the media/gpgpu engine. */ -typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +struct intel_buf; +typedef void (*igt_fillfunc_t)(int i915, + struct intel_buf *buf, unsigned x, unsigned y, unsigned width, unsigned height, uint8_t color); -struct intel_buf; -typedef void (*igt_fillfunc_v2_t)(int i915, - struct intel_buf *buf, - unsigned x, unsigned y, - unsigned width, unsigned height, - uint8_t color); - -igt_fillfunc_t igt_get_media_fillfunc(int devid); igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid); -igt_fillfunc_v2_t igt_get_gpgpu_fillfunc_v2(int devid); -igt_fillfunc_v2_t igt_get_media_fillfunc_v2(int devid); +igt_fillfunc_t igt_get_media_fillfunc(int devid); typedef void (*igt_vme_func_t)(int i915, uint32_t ctx, diff --git a/lib/media_fill.c b/lib/media_fill.c index 53d63b4b..c21de54b 100644 --- a/lib/media_fill.c +++ b/lib/media_fill.c @@ -145,55 +145,11 @@ static const uint32_t gen12_media_kernel[][4] = { #define GEN7_VFE_STATE_MEDIA_MODE 0 void -gen7_media_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +gen7_media_fillfunc(int i915, + struct intel_buf *buf, unsigned int x, unsigned int y, unsigned int width, unsigned int height, uint8_t color) -{ - uint32_t curbe_buffer, interface_descriptor; - uint32_t batch_end; - - intel_batchbuffer_flush(batch); - - /* setup states */ - batch->ptr = &batch->buffer[BATCH_STATE_SPLIT]; - - curbe_buffer = gen7_fill_curbe_buffer_data(batch, color); - interface_descriptor = gen7_fill_interface_descriptor(batch, dst, - gen7_media_kernel, - sizeof(gen7_media_kernel)); - igt_assert(batch->ptr < &batch->buffer[4095]); - - /* media pipeline */ - batch->ptr = batch->buffer; - OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); - gen7_emit_state_base_address(batch); - - gen7_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, - MEDIA_CURBE_SIZE, GEN7_VFE_STATE_MEDIA_MODE);; - - gen7_emit_curbe_load(batch, curbe_buffer); - - gen7_emit_interface_descriptor_load(batch, interface_descriptor); - - gen7_emit_media_objects(batch, x, y, width, height); - - OUT_BATCH(MI_BATCH_BUFFER_END); - - batch_end = intel_batchbuffer_align(batch, 8); - igt_assert(batch_end < BATCH_STATE_SPLIT); - - gen7_render_flush(batch, batch_end); - intel_batchbuffer_reset(batch); -} - -void -gen7_media_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color) { struct intel_bb *ibb; uint32_t curbe_buffer, interface_descriptor; @@ -203,24 +159,24 @@ gen7_media_fillfunc_v2(int i915, intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT); - curbe_buffer = gen7_fill_curbe_buffer_data_v2(ibb, color); - interface_descriptor = gen7_fill_interface_descriptor_v2(ibb, buf, + curbe_buffer = gen7_fill_curbe_buffer_data(ibb, color); + interface_descriptor = gen7_fill_interface_descriptor(ibb, buf, gen7_media_kernel, sizeof(gen7_media_kernel)); intel_bb_ptr_set(ibb, 0); /* media pipeline */ intel_bb_out(ibb, GEN7_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); - gen7_emit_state_base_address_v2(ibb); + gen7_emit_state_base_address(ibb); - gen7_emit_vfe_state_v2(ibb, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, - MEDIA_CURBE_SIZE, GEN7_VFE_STATE_MEDIA_MODE); + gen7_emit_vfe_state(ibb, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, + MEDIA_CURBE_SIZE, GEN7_VFE_STATE_MEDIA_MODE); - gen7_emit_curbe_load_v2(ibb, curbe_buffer); + gen7_emit_curbe_load(ibb, curbe_buffer); - gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor); + gen7_emit_interface_descriptor_load(ibb, interface_descriptor); - gen7_emit_media_objects_v2(ibb, x, y, width, height); + gen7_emit_media_objects(ibb, x, y, width, height); intel_bb_out(ibb, MI_BATCH_BUFFER_END); intel_bb_ptr_align(ibb, 32); @@ -232,55 +188,11 @@ gen7_media_fillfunc_v2(int i915, } void -gen8_media_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +gen8_media_fillfunc(int i915, + struct intel_buf *buf, unsigned int x, unsigned int y, unsigned int width, unsigned int height, uint8_t color) -{ - uint32_t curbe_buffer, interface_descriptor; - uint32_t batch_end; - - intel_batchbuffer_flush(batch); - - /* setup states */ - batch->ptr = &batch->buffer[BATCH_STATE_SPLIT]; - - curbe_buffer = gen7_fill_curbe_buffer_data(batch, color); - interface_descriptor = gen8_fill_interface_descriptor(batch, dst, - gen8_media_kernel, - sizeof(gen8_media_kernel)); - igt_assert(batch->ptr < &batch->buffer[4095]); - - /* media pipeline */ - batch->ptr = batch->buffer; - OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); - gen8_emit_state_base_address(batch); - - gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, - MEDIA_CURBE_SIZE); - - gen7_emit_curbe_load(batch, curbe_buffer); - - gen7_emit_interface_descriptor_load(batch, interface_descriptor); - - gen7_emit_media_objects(batch, x, y, width, height); - - OUT_BATCH(MI_BATCH_BUFFER_END); - - batch_end = intel_batchbuffer_align(batch, 8); - igt_assert(batch_end < BATCH_STATE_SPLIT); - - gen7_render_flush(batch, batch_end); - intel_batchbuffer_reset(batch); -} - -void -gen8_media_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color) { struct intel_bb *ibb; uint32_t curbe_buffer, interface_descriptor; @@ -290,24 +202,24 @@ gen8_media_fillfunc_v2(int i915, intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT); - curbe_buffer = gen7_fill_curbe_buffer_data_v2(ibb, color); - interface_descriptor = gen8_fill_interface_descriptor_v2(ibb, buf, + curbe_buffer = gen7_fill_curbe_buffer_data(ibb, color); + interface_descriptor = gen8_fill_interface_descriptor(ibb, buf, gen8_media_kernel, sizeof(gen8_media_kernel)); intel_bb_ptr_set(ibb, 0); /* media pipeline */ intel_bb_out(ibb, GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); - gen8_emit_state_base_address_v2(ibb); + gen8_emit_state_base_address(ibb); - gen8_emit_vfe_state_v2(ibb, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, - MEDIA_CURBE_SIZE); + gen8_emit_vfe_state(ibb, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, + MEDIA_CURBE_SIZE); - gen7_emit_curbe_load_v2(ibb, curbe_buffer); + gen7_emit_curbe_load(ibb, curbe_buffer); - gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor); + gen7_emit_interface_descriptor_load(ibb, interface_descriptor); - gen7_emit_media_objects_v2(ibb, x, y, width, height); + gen7_emit_media_objects(ibb, x, y, width, height); intel_bb_out(ibb, MI_BATCH_BUFFER_END); intel_bb_ptr_align(ibb, 32); @@ -319,81 +231,12 @@ gen8_media_fillfunc_v2(int i915, } static void -__gen9_media_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +__gen9_media_fillfunc(int i915, + struct intel_buf *buf, unsigned int x, unsigned int y, unsigned int width, unsigned int height, - uint8_t color, const uint32_t kernel[][4], - size_t kernel_size) -{ - uint32_t curbe_buffer, interface_descriptor; - uint32_t batch_end; - - intel_batchbuffer_flush(batch); - - /* setup states */ - batch->ptr = &batch->buffer[BATCH_STATE_SPLIT]; - - curbe_buffer = gen7_fill_curbe_buffer_data(batch, color); - interface_descriptor = gen8_fill_interface_descriptor(batch, dst, - kernel, kernel_size); - assert(batch->ptr < &batch->buffer[4095]); - - /* media pipeline */ - batch->ptr = batch->buffer; - OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA | - GEN9_FORCE_MEDIA_AWAKE_ENABLE | - GEN9_SAMPLER_DOP_GATE_DISABLE | - GEN9_PIPELINE_SELECTION_MASK | - GEN9_SAMPLER_DOP_GATE_MASK | - GEN9_FORCE_MEDIA_AWAKE_MASK); - gen9_emit_state_base_address(batch); - - gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, - MEDIA_CURBE_SIZE); - - gen7_emit_curbe_load(batch, curbe_buffer); - - gen7_emit_interface_descriptor_load(batch, interface_descriptor); - - gen7_emit_media_objects(batch, x, y, width, height); - - OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA | - GEN9_FORCE_MEDIA_AWAKE_DISABLE | - GEN9_SAMPLER_DOP_GATE_ENABLE | - GEN9_PIPELINE_SELECTION_MASK | - GEN9_SAMPLER_DOP_GATE_MASK | - GEN9_FORCE_MEDIA_AWAKE_MASK); - - OUT_BATCH(MI_BATCH_BUFFER_END); - - batch_end = intel_batchbuffer_align(batch, 8); - assert(batch_end < BATCH_STATE_SPLIT); - - gen7_render_flush(batch, batch_end); - intel_batchbuffer_reset(batch); -} - -void -gen9_media_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color) -{ - - __gen9_media_fillfunc(batch, dst, x, y, width, height, color, - gen8_media_kernel, sizeof(gen8_media_kernel)); - -} - -static void -__gen9_media_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color, - const uint32_t kernel[][4], size_t kernel_size) + uint8_t color, + const uint32_t kernel[][4], size_t kernel_size) { struct intel_bb *ibb; uint32_t curbe_buffer, interface_descriptor; @@ -404,10 +247,10 @@ __gen9_media_fillfunc_v2(int i915, /* setup states */ intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT); - curbe_buffer = gen7_fill_curbe_buffer_data_v2(ibb, color); - interface_descriptor = gen8_fill_interface_descriptor_v2(ibb, buf, - kernel, - kernel_size); + curbe_buffer = gen7_fill_curbe_buffer_data(ibb, color); + interface_descriptor = gen8_fill_interface_descriptor(ibb, buf, + kernel, + kernel_size); intel_bb_ptr_set(ibb, 0); /* media pipeline */ @@ -417,16 +260,16 @@ __gen9_media_fillfunc_v2(int i915, GEN9_PIPELINE_SELECTION_MASK | GEN9_SAMPLER_DOP_GATE_MASK | GEN9_FORCE_MEDIA_AWAKE_MASK); - gen9_emit_state_base_address_v2(ibb); + gen9_emit_state_base_address(ibb); - gen8_emit_vfe_state_v2(ibb, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, - MEDIA_CURBE_SIZE); + gen8_emit_vfe_state(ibb, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, + MEDIA_CURBE_SIZE); - gen7_emit_curbe_load_v2(ibb, curbe_buffer); + gen7_emit_curbe_load(ibb, curbe_buffer); - gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor); + gen7_emit_interface_descriptor_load(ibb, interface_descriptor); - gen7_emit_media_objects_v2(ibb, x, y, width, height); + gen7_emit_media_objects(ibb, x, y, width, height); intel_bb_out(ibb, GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA | GEN9_FORCE_MEDIA_AWAKE_DISABLE | @@ -445,15 +288,14 @@ __gen9_media_fillfunc_v2(int i915, } void -gen9_media_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color) +gen9_media_fillfunc(int i915, + struct intel_buf *buf, + unsigned int x, unsigned int y, + unsigned int width, unsigned int height, + uint8_t color) { - - __gen9_media_fillfunc_v2(i915, buf, x, y, width, height, color, - gen8_media_kernel, sizeof(gen8_media_kernel)); + __gen9_media_fillfunc(i915, buf, x, y, width, height, color, + gen8_media_kernel, sizeof(gen8_media_kernel)); } static void @@ -488,16 +330,16 @@ __gen11_media_vme_func(int i915, GEN9_PIPELINE_SELECTION_MASK | GEN9_SAMPLER_DOP_GATE_MASK | GEN9_FORCE_MEDIA_AWAKE_MASK); - gen9_emit_state_base_address_v2(ibb); + gen9_emit_state_base_address(ibb); - gen8_emit_vfe_state_v2(ibb, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, + gen8_emit_vfe_state(ibb, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE, MEDIA_CURBE_SIZE); - gen7_emit_curbe_load_v2(ibb, curbe_buffer); + gen7_emit_curbe_load(ibb, curbe_buffer); - gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor); + gen7_emit_interface_descriptor_load(ibb, interface_descriptor); - gen7_emit_media_objects_v2(ibb, 0, 0, width, height); + gen7_emit_media_objects(ibb, 0, 0, width, height); intel_bb_out(ibb, GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA | GEN9_FORCE_MEDIA_AWAKE_DISABLE | @@ -531,23 +373,12 @@ gen11_media_vme_func(int i915, } void -gen12_media_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +gen12_media_fillfunc(int i915, + struct intel_buf *buf, unsigned int x, unsigned int y, unsigned int width, unsigned int height, uint8_t color) { - __gen9_media_fillfunc(batch, dst, x, y, width, height, color, + __gen9_media_fillfunc(i915, buf, x, y, width, height, color, gen12_media_kernel, sizeof(gen12_media_kernel)); } - -void -gen12_media_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color) -{ - __gen9_media_fillfunc_v2(i915, buf, x, y, width, height, color, - gen12_media_kernel, sizeof(gen12_media_kernel)); -} diff --git a/lib/media_fill.h b/lib/media_fill.h index 851a9915..0d2d0db3 100644 --- a/lib/media_fill.h +++ b/lib/media_fill.h @@ -26,51 +26,29 @@ #define RENDE_MEDIA_FILL_H #include <stdint.h> -#include "intel_batchbuffer.h" #include "intel_bufops.h" void -gen8_media_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +gen7_media_fillfunc(int i915, + struct intel_buf *buf, unsigned int x, unsigned int y, unsigned int width, unsigned int height, uint8_t color); void -gen7_media_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +gen8_media_fillfunc(int i915, + struct intel_buf *buf, unsigned int x, unsigned int y, unsigned int width, unsigned int height, uint8_t color); void -gen7_media_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color); - -void -gen8_media_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color); - -void -gen9_media_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +gen9_media_fillfunc(int i915, + struct intel_buf *buf, unsigned int x, unsigned int y, unsigned int width, unsigned int height, uint8_t color); -void -gen9_media_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color); - void gen11_media_vme_func(int i915, uint32_t ctx, @@ -79,17 +57,10 @@ gen11_media_vme_func(int i915, struct intel_buf *dst); void -gen12_media_fillfunc(struct intel_batchbuffer *batch, - const struct igt_buf *dst, +gen12_media_fillfunc(int i915, + struct intel_buf *buf, unsigned int x, unsigned int y, unsigned int width, unsigned int height, uint8_t color); -void -gen12_media_fillfunc_v2(int i915, - struct intel_buf *buf, - unsigned int x, unsigned int y, - unsigned int width, unsigned int height, - uint8_t color); - #endif /* RENDE_MEDIA_FILL_H */ diff --git a/tests/i915/gem_gpgpu_fill.c b/tests/i915/gem_gpgpu_fill.c index 39917d94..e1d3a288 100644 --- a/tests/i915/gem_gpgpu_fill.c +++ b/tests/i915/gem_gpgpu_fill.c @@ -45,7 +45,6 @@ #include "drm.h" #include "i915/gem.h" #include "igt.h" -#include "intel_bufmgr.h" #include "intel_bufops.h" #define WIDTH 64 @@ -59,32 +58,9 @@ typedef struct { int drm_fd; uint32_t devid; - drm_intel_bufmgr *bufmgr; - uint8_t linear[WIDTH * HEIGHT]; struct buf_ops *bops; } data_t; -static void scratch_buf_init(data_t *data, struct igt_buf *buf, - int width, int height, int stride, uint8_t color) -{ - drm_intel_bo *bo; - int i; - - bo = drm_intel_bo_alloc(data->bufmgr, "", SIZE, 4096); - for (i = 0; i < width * height; i++) - data->linear[i] = color; - gem_write(data->drm_fd, bo->handle, 0, data->linear, - sizeof(data->linear)); - - memset(buf, 0, sizeof(*buf)); - - buf->bo = bo; - buf->surface[0].stride = stride; - buf->tiling = I915_TILING_NONE; - buf->surface[0].size = SIZE; - buf->bpp = 32; -} - static struct intel_buf * create_buf(data_t *data, int width, int height, uint8_t color) { @@ -113,20 +89,6 @@ create_buf(data_t *data, int width, int height, uint8_t color) return buf; } -static void -scratch_buf_check(data_t *data, struct igt_buf *buf, int x, int y, - uint8_t color) -{ - uint8_t val; - - gem_read(data->drm_fd, buf->bo->handle, 0, - data->linear, sizeof(data->linear)); - val = data->linear[y * WIDTH + x]; - igt_assert_f(val == color, - "Expected 0x%02x, found 0x%02x at (%d,%d)\n", - color, val, x, y); -} - static void buf_check(uint8_t *ptr, int x, int y, uint8_t color) { uint8_t val; @@ -137,7 +99,7 @@ static void buf_check(uint8_t *ptr, int x, int y, uint8_t color) color, val, x, y); } -static void no_libdrm(data_t *data, igt_fillfunc_v2_t fill) +static void gpgpu_fill(data_t *data, igt_fillfunc_t fill) { struct intel_buf *buf; uint8_t *ptr; @@ -162,54 +124,19 @@ static void no_libdrm(data_t *data, igt_fillfunc_v2_t fill) munmap(ptr, buf->size); } -static void with_libdrm(data_t *data, igt_fillfunc_t fill) -{ - struct intel_batchbuffer *batch = NULL; - struct igt_buf dst; - int i, j; - - batch = intel_batchbuffer_alloc(data->bufmgr, data->devid); - igt_assert(batch); - - scratch_buf_init(data, &dst, WIDTH, HEIGHT, STRIDE, COLOR_C4); - - for (i = 0; i < WIDTH; i++) - for (j = 0; j < HEIGHT; j++) - scratch_buf_check(data, &dst, i, j, COLOR_C4); - - fill(batch, &dst, 0, 0, WIDTH / 2, HEIGHT / 2, COLOR_4C); - - for (i = 0; i < WIDTH; i++) - for (j = 0; j < HEIGHT; j++) - if (i < WIDTH / 2 && j < HEIGHT / 2) - scratch_buf_check(data, &dst, i, j, COLOR_4C); - else - scratch_buf_check(data, &dst, i, j, COLOR_C4); - -} - igt_simple_main { data_t data = {0, }; - igt_fillfunc_t gpgpu_fill = NULL; - igt_fillfunc_v2_t gpgpu_fill_v2 = NULL; + igt_fillfunc_t fill_fn = NULL; data.drm_fd = drm_open_driver_render(DRIVER_INTEL); data.devid = intel_get_drm_devid(data.drm_fd); igt_require_gem(data.drm_fd); data.bops = buf_ops_create(data.drm_fd); - data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096); - igt_assert(data.bufmgr); - - gpgpu_fill = igt_get_gpgpu_fillfunc(data.devid); - gpgpu_fill_v2 = igt_get_gpgpu_fillfunc_v2(data.devid); + fill_fn = igt_get_gpgpu_fillfunc(data.devid); - igt_require_f(gpgpu_fill || gpgpu_fill_v2, - "no gpgpu-fill function\n"); + igt_require_f(fill_fn, "no gpgpu-fill function\n"); - if (gpgpu_fill_v2) - no_libdrm(&data, gpgpu_fill_v2); - else - with_libdrm(&data, gpgpu_fill); + gpgpu_fill(&data, fill_fn); } diff --git a/tests/i915/gem_media_fill.c b/tests/i915/gem_media_fill.c index 7c975577..934a9402 100644 --- a/tests/i915/gem_media_fill.c +++ b/tests/i915/gem_media_fill.c @@ -45,7 +45,6 @@ #include "drm.h" #include "i915/gem.h" #include "igt.h" -#include "intel_bufmgr.h" IGT_TEST_DESCRIPTION("Basic test for the media_fill() function, a very simple" " workload for the Media pipeline."); @@ -61,32 +60,9 @@ IGT_TEST_DESCRIPTION("Basic test for the media_fill() function, a very simple" typedef struct { int drm_fd; uint32_t devid; - drm_intel_bufmgr *bufmgr; - uint8_t linear[WIDTH * HEIGHT]; struct buf_ops *bops; } data_t; -static void scratch_buf_init(data_t *data, struct igt_buf *buf, - int width, int height, int stride, uint8_t color) -{ - drm_intel_bo *bo; - int i; - - bo = drm_intel_bo_alloc(data->bufmgr, "", SIZE, 4096); - for (i = 0; i < width * height; i++) - data->linear[i] = color; - gem_write(data->drm_fd, bo->handle, 0, data->linear, - sizeof(data->linear)); - - memset(buf, 0, sizeof(*buf)); - - buf->bo = bo; - buf->surface[0].stride = stride; - buf->tiling = I915_TILING_NONE; - buf->surface[0].size = SIZE; - buf->bpp = 32; -} - static struct intel_buf * create_buf(data_t *data, int width, int height, uint8_t color) { @@ -115,20 +91,6 @@ create_buf(data_t *data, int width, int height, uint8_t color) return buf; } -static void -scratch_buf_check(data_t *data, struct igt_buf *buf, int x, int y, - uint8_t color) -{ - uint8_t val; - - gem_read(data->drm_fd, buf->bo->handle, 0, - data->linear, sizeof(data->linear)); - val = data->linear[y * WIDTH + x]; - igt_assert_f(val == color, - "Expected 0x%02x, found 0x%02x at (%d,%d)\n", - color, val, x, y); -} - static void buf_check(uint8_t *ptr, int x, int y, uint8_t color) { uint8_t val; @@ -139,7 +101,7 @@ static void buf_check(uint8_t *ptr, int x, int y, uint8_t color) color, val, x, y); } -static void no_libdrm(data_t *data, igt_fillfunc_v2_t fill) +static void media_fill(data_t *data, igt_fillfunc_t fill) { struct intel_buf *buf; uint8_t *ptr; @@ -164,37 +126,10 @@ static void no_libdrm(data_t *data, igt_fillfunc_v2_t fill) munmap(ptr, buf->size); } -static void with_libdrm(data_t *data, igt_fillfunc_t fill) -{ - struct intel_batchbuffer *batch = NULL; - struct igt_buf dst; - int i, j; - - batch = intel_batchbuffer_alloc(data->bufmgr, data->devid); - igt_assert(batch); - - scratch_buf_init(data, &dst, WIDTH, HEIGHT, STRIDE, COLOR_C4); - - for (i = 0; i < WIDTH; i++) - for (j = 0; j < HEIGHT; j++) - scratch_buf_check(data, &dst, i, j, COLOR_C4); - - fill(batch, &dst, 0, 0, WIDTH / 2, HEIGHT / 2, COLOR_4C); - - for (i = 0; i < WIDTH; i++) - for (j = 0; j < HEIGHT; j++) - if (i < WIDTH / 2 && j < HEIGHT / 2) - scratch_buf_check(data, &dst, i, j, COLOR_4C); - else - scratch_buf_check(data, &dst, i, j, COLOR_C4); - -} - igt_simple_main { data_t data = {0, }; - igt_fillfunc_t media_fill = NULL; - igt_fillfunc_v2_t media_fill_v2 = NULL; + igt_fillfunc_t fill_fn = NULL; data.drm_fd = drm_open_driver_render(DRIVER_INTEL); igt_require_gem(data.drm_fd); @@ -202,17 +137,9 @@ igt_simple_main data.devid = intel_get_drm_devid(data.drm_fd); data.bops = buf_ops_create(data.drm_fd); - data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096); - igt_assert(data.bufmgr); - - media_fill = igt_get_media_fillfunc(data.devid); - media_fill_v2 = igt_get_media_fillfunc_v2(data.devid); + fill_fn = igt_get_media_fillfunc(data.devid); - igt_require_f(media_fill || media_fill_v2, - "no media-fill function\n"); + igt_require_f(fill_fn, "no media-fill function\n"); - if (media_fill_v2) - no_libdrm(&data, media_fill_v2); - else - with_libdrm(&data, media_fill); + media_fill(&data, fill_fn); } -- 2.26.0 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Remove _v2 functions in gpu pipelines 2020-05-29 10:41 [igt-dev] [PATCH i-g-t 0/2] Remove _v2 functions in gpu pipelines Zbigniew Kempczyński 2020-05-29 10:41 ` [igt-dev] [PATCH i-g-t 1/2] lib/media_spin: localize pipeline functions Zbigniew Kempczyński 2020-05-29 10:41 ` [igt-dev] [PATCH i-g-t 2/2] tests/gem_(gpgpu|media)_fill: remove the _v2 suffix Zbigniew Kempczyński @ 2020-05-29 11:07 ` Patchwork 2020-05-29 12:07 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 2020-05-29 13:24 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2020-05-29 11:07 UTC (permalink / raw) To: Zbigniew Kempczyński; +Cc: igt-dev == Series Details == Series: Remove _v2 functions in gpu pipelines URL : https://patchwork.freedesktop.org/series/77782/ State : success == Summary == CI Bug Log - changes from CI_DRM_8552 -> IGTPW_4623 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html Changes ------- No changes found Participating hosts (50 -> 42) ------------------------------ Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5683 -> IGTPW_4623 CI-20190529: 20190529 CI_DRM_8552: cd4a9b47339259e3a98601fff14438f17fd2d7dc @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_4623: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html IGT_5683: 757b6e72d546fd2dbc3801a73796d67b0854021b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Remove _v2 functions in gpu pipelines 2020-05-29 10:41 [igt-dev] [PATCH i-g-t 0/2] Remove _v2 functions in gpu pipelines Zbigniew Kempczyński ` (2 preceding siblings ...) 2020-05-29 11:07 ` [igt-dev] ✓ Fi.CI.BAT: success for Remove _v2 functions in gpu pipelines Patchwork @ 2020-05-29 12:07 ` Patchwork 2020-05-29 12:36 ` Zbigniew Kempczyński 2020-05-29 13:24 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork 4 siblings, 1 reply; 8+ messages in thread From: Patchwork @ 2020-05-29 12:07 UTC (permalink / raw) To: Zbigniew Kempczyński; +Cc: igt-dev == Series Details == Series: Remove _v2 functions in gpu pipelines URL : https://patchwork.freedesktop.org/series/77782/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8552_full -> IGTPW_4623_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_4623_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_4623_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_4623_full: ### IGT changes ### #### Possible regressions #### * igt@gem_exec_reloc@basic-gtt-cpu-active: - shard-glk: [PASS][1] -> [TIMEOUT][2] +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk7/igt@gem_exec_reloc@basic-gtt-cpu-active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk2/igt@gem_exec_reloc@basic-gtt-cpu-active.html Known issues ------------ Here are the changes found in IGTPW_4623_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen: - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#54] / [i915#93] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html * igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-hsw: [PASS][11] -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-apl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html #### Possible fixes #### * igt@gem_ctx_persistence@engines-mixed-process@rcs0: - shard-apl: [FAIL][19] ([i915#1528]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl8/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html * igt@gem_exec_whisper@basic-fds-forked-all: - shard-hsw: [INCOMPLETE][21] ([i915#61]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@gem_exec_whisper@basic-fds-forked-all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw2/igt@gem_exec_whisper@basic-fds-forked-all.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-tglb: [SKIP][23] ([i915#1904]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb8/igt@i915_pm_dc@dc3co-vpb-simulation.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb6/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_dc@dc5-psr: - shard-iclb: [FAIL][25] ([i915#1899]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb1/igt@i915_pm_dc@dc5-psr.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb2/igt@i915_pm_dc@dc5-psr.html * igt@i915_suspend@sysfs-reader: - shard-apl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl4/igt@i915_suspend@sysfs-reader.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@i915_suspend@sysfs-reader.html * igt@kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [FAIL][29] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk5/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen: - shard-glk: [TIMEOUT][31] ([i915#1958]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk4/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [DMESG-FAIL][33] ([i915#1926]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled: - shard-kbl: [FAIL][35] ([i915#177] / [i915#52] / [i915#54] / [i915#93] / [i915#95]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl6/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled: - shard-apl: [FAIL][37] ([i915#52] / [i915#54] / [i915#95]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-snb: [DMESG-WARN][39] ([i915#42]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-snb5/igt@kms_fbcon_fbt@fbc-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-snb2/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render: - shard-snb: [SKIP][41] ([fdo#109271]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-snb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html * igt@kms_hdmi_inject@inject-audio: - shard-tglb: [SKIP][43] ([i915#433]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb8/igt@kms_hdmi_inject@inject-audio.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb8/igt@kms_hdmi_inject@inject-audio.html * igt@kms_panel_fitting@atomic-fastset: - shard-iclb: [FAIL][45] ([i915#83]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb3/igt@kms_panel_fitting@atomic-fastset.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb8/igt@kms_panel_fitting@atomic-fastset.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [DMESG-WARN][47] ([i915#180] / [i915#95]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_cursor@pipe-a-viewport-size-64: - shard-kbl: [FAIL][49] ([i915#1559] / [i915#93] / [i915#95]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl1/igt@kms_plane_cursor@pipe-a-viewport-size-64.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html - shard-apl: [FAIL][51] ([i915#1559] / [i915#95]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [INCOMPLETE][55] ([i915#155]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html * {igt@perf@blocking-parameterized}: - shard-iclb: [FAIL][57] ([i915#1542]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb1/igt@perf@blocking-parameterized.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb6/igt@perf@blocking-parameterized.html - shard-hsw: [FAIL][59] ([i915#1542]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@perf@blocking-parameterized.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw4/igt@perf@blocking-parameterized.html #### Warnings #### * igt@i915_pm_dc@dc6-dpms: - shard-glk: [TIMEOUT][61] ([i915#1958]) -> [SKIP][62] ([fdo#109271]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk4/igt@i915_pm_dc@dc6-dpms.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk5/igt@i915_pm_dc@dc6-dpms.html - shard-tglb: [FAIL][63] ([i915#454]) -> [SKIP][64] ([i915#468]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb5/igt@i915_pm_dc@dc6-dpms.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][65] ([i915#468]) -> [FAIL][66] ([i915#454]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb2/igt@i915_pm_dc@dc6-psr.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb1/igt@i915_pm_dc@dc6-psr.html * igt@kms_content_protection@atomic: - shard-apl: [TIMEOUT][67] ([i915#1319] / [i915#1635]) -> [FAIL][68] ([fdo#110321] / [fdo#110336]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_content_protection@atomic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl6/igt@kms_content_protection@atomic.html * igt@kms_content_protection@lic: - shard-kbl: [FAIL][69] ([fdo#110321] / [i915#93] / [i915#95]) -> [TIMEOUT][70] ([i915#1319]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl2/igt@kms_content_protection@lic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl7/igt@kms_content_protection@lic.html * igt@kms_content_protection@srm: - shard-apl: [FAIL][71] ([fdo#110321]) -> [TIMEOUT][72] ([i915#1319] / [i915#1635]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl4/igt@kms_content_protection@srm.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl4/igt@kms_content_protection@srm.html * igt@kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [DMESG-FAIL][73] ([i915#1925]) -> [DMESG-FAIL][74] ([i915#1925] / [i915#1926]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk4/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1559]: https://gitlab.freedesktop.org/drm/intel/issues/1559 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1904]: https://gitlab.freedesktop.org/drm/intel/issues/1904 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#83]: https://gitlab.freedesktop.org/drm/intel/issues/83 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 8) ------------------------------ Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5683 -> IGTPW_4623 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_8552: cd4a9b47339259e3a98601fff14438f17fd2d7dc @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_4623: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html IGT_5683: 757b6e72d546fd2dbc3801a73796d67b0854021b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] ✗ Fi.CI.IGT: failure for Remove _v2 functions in gpu pipelines 2020-05-29 12:07 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork @ 2020-05-29 12:36 ` Zbigniew Kempczyński 2020-05-29 13:26 ` Vudum, Lakshminarayana 0 siblings, 1 reply; 8+ messages in thread From: Zbigniew Kempczyński @ 2020-05-29 12:36 UTC (permalink / raw) To: igt-dev; +Cc: Vudum, Lakshminarayana On Fri, May 29, 2020 at 12:07:15PM +0000, Patchwork wrote: > == Series Details == > > Series: Remove _v2 functions in gpu pipelines > URL : https://patchwork.freedesktop.org/series/77782/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8552_full -> IGTPW_4623_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with IGTPW_4623_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in IGTPW_4623_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in IGTPW_4623_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@gem_exec_reloc@basic-gtt-cpu-active: > - shard-glk: [PASS][1] -> [TIMEOUT][2] +5 similar issues > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk7/igt@gem_exec_reloc@basic-gtt-cpu-active.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk2/igt@gem_exec_reloc@basic-gtt-cpu-active.html Those tests were not touched by the code I've changed. -- Zbigniew > > > Known issues > ------------ > > Here are the changes found in IGTPW_4623_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_workarounds@suspend-resume-fd: > - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html > > * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen: > - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#54] / [i915#93] / [i915#95]) +1 similar issue > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html > > * igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen: > - shard-apl: [PASS][7] -> [FAIL][8] ([i915#54]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html > - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#54]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html > > * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: > - shard-hsw: [PASS][11] -> [SKIP][12] ([fdo#109271]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html > > * igt@kms_fbcon_fbt@fbc-suspend: > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html > > * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-apl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265] / [i915#95]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > * igt@kms_psr@psr2_cursor_blt: > - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html > > > #### Possible fixes #### > > * igt@gem_ctx_persistence@engines-mixed-process@rcs0: > - shard-apl: [FAIL][19] ([i915#1528]) -> [PASS][20] > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl8/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html > > * igt@gem_exec_whisper@basic-fds-forked-all: > - shard-hsw: [INCOMPLETE][21] ([i915#61]) -> [PASS][22] +1 similar issue > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@gem_exec_whisper@basic-fds-forked-all.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw2/igt@gem_exec_whisper@basic-fds-forked-all.html > > * igt@i915_pm_dc@dc3co-vpb-simulation: > - shard-tglb: [SKIP][23] ([i915#1904]) -> [PASS][24] > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb8/igt@i915_pm_dc@dc3co-vpb-simulation.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb6/igt@i915_pm_dc@dc3co-vpb-simulation.html > > * igt@i915_pm_dc@dc5-psr: > - shard-iclb: [FAIL][25] ([i915#1899]) -> [PASS][26] > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb1/igt@i915_pm_dc@dc5-psr.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb2/igt@i915_pm_dc@dc5-psr.html > > * igt@i915_suspend@sysfs-reader: > - shard-apl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +3 similar issues > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl4/igt@i915_suspend@sysfs-reader.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@i915_suspend@sysfs-reader.html > > * igt@kms_big_fb@x-tiled-64bpp-rotate-0: > - shard-glk: [FAIL][29] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][30] > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk5/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html > > * igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen: > - shard-glk: [TIMEOUT][31] ([i915#1958]) -> [PASS][32] > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk4/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html > > * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: > - shard-hsw: [DMESG-FAIL][33] ([i915#1926]) -> [PASS][34] > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html > > * igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled: > - shard-kbl: [FAIL][35] ([i915#177] / [i915#52] / [i915#54] / [i915#93] / [i915#95]) -> [PASS][36] +1 similar issue > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl6/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html > > * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled: > - shard-apl: [FAIL][37] ([i915#52] / [i915#54] / [i915#95]) -> [PASS][38] +1 similar issue > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html > > * igt@kms_fbcon_fbt@fbc-suspend: > - shard-snb: [DMESG-WARN][39] ([i915#42]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-snb5/igt@kms_fbcon_fbt@fbc-suspend.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-snb2/igt@kms_fbcon_fbt@fbc-suspend.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render: > - shard-snb: [SKIP][41] ([fdo#109271]) -> [PASS][42] +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-snb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html > > * igt@kms_hdmi_inject@inject-audio: > - shard-tglb: [SKIP][43] ([i915#433]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb8/igt@kms_hdmi_inject@inject-audio.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb8/igt@kms_hdmi_inject@inject-audio.html > > * igt@kms_panel_fitting@atomic-fastset: > - shard-iclb: [FAIL][45] ([i915#83]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb3/igt@kms_panel_fitting@atomic-fastset.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb8/igt@kms_panel_fitting@atomic-fastset.html > > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: > - shard-apl: [DMESG-WARN][47] ([i915#180] / [i915#95]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > > * igt@kms_plane_cursor@pipe-a-viewport-size-64: > - shard-kbl: [FAIL][49] ([i915#1559] / [i915#93] / [i915#95]) -> [PASS][50] +1 similar issue > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl1/igt@kms_plane_cursor@pipe-a-viewport-size-64.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html > - shard-apl: [FAIL][51] ([i915#1559] / [i915#95]) -> [PASS][52] +1 similar issue > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html > > * igt@kms_psr@psr2_sprite_plane_move: > - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +2 similar issues > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html > > * igt@kms_vblank@pipe-b-ts-continuation-suspend: > - shard-kbl: [INCOMPLETE][55] ([i915#155]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html > > * {igt@perf@blocking-parameterized}: > - shard-iclb: [FAIL][57] ([i915#1542]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb1/igt@perf@blocking-parameterized.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb6/igt@perf@blocking-parameterized.html > - shard-hsw: [FAIL][59] ([i915#1542]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@perf@blocking-parameterized.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw4/igt@perf@blocking-parameterized.html > > > #### Warnings #### > > * igt@i915_pm_dc@dc6-dpms: > - shard-glk: [TIMEOUT][61] ([i915#1958]) -> [SKIP][62] ([fdo#109271]) +1 similar issue > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk4/igt@i915_pm_dc@dc6-dpms.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk5/igt@i915_pm_dc@dc6-dpms.html > - shard-tglb: [FAIL][63] ([i915#454]) -> [SKIP][64] ([i915#468]) > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb5/igt@i915_pm_dc@dc6-dpms.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html > > * igt@i915_pm_dc@dc6-psr: > - shard-tglb: [SKIP][65] ([i915#468]) -> [FAIL][66] ([i915#454]) > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb2/igt@i915_pm_dc@dc6-psr.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb1/igt@i915_pm_dc@dc6-psr.html > > * igt@kms_content_protection@atomic: > - shard-apl: [TIMEOUT][67] ([i915#1319] / [i915#1635]) -> [FAIL][68] ([fdo#110321] / [fdo#110336]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_content_protection@atomic.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl6/igt@kms_content_protection@atomic.html > > * igt@kms_content_protection@lic: > - shard-kbl: [FAIL][69] ([fdo#110321] / [i915#93] / [i915#95]) -> [TIMEOUT][70] ([i915#1319]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl2/igt@kms_content_protection@lic.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl7/igt@kms_content_protection@lic.html > > * igt@kms_content_protection@srm: > - shard-apl: [FAIL][71] ([fdo#110321]) -> [TIMEOUT][72] ([i915#1319] / [i915#1635]) > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl4/igt@kms_content_protection@srm.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl4/igt@kms_content_protection@srm.html > > * igt@kms_cursor_legacy@cursora-vs-flipb-toggle: > - shard-glk: [DMESG-FAIL][73] ([i915#1925]) -> [DMESG-FAIL][74] ([i915#1925] / [i915#1926]) +1 similar issue > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk4/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 > [i915#1559]: https://gitlab.freedesktop.org/drm/intel/issues/1559 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 > [i915#1904]: https://gitlab.freedesktop.org/drm/intel/issues/1904 > [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 > [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42 > [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 > [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 > [i915#83]: https://gitlab.freedesktop.org/drm/intel/issues/83 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 8) > ------------------------------ > > Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7 > > > Build changes > ------------- > > * CI: CI-20190529 -> None > * IGT: IGT_5683 -> IGTPW_4623 > * Piglit: piglit_4509 -> None > > CI-20190529: 20190529 > CI_DRM_8552: cd4a9b47339259e3a98601fff14438f17fd2d7dc @ git://anongit.freedesktop.org/gfx-ci/linux > IGTPW_4623: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html > IGT_5683: 757b6e72d546fd2dbc3801a73796d67b0854021b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] ✗ Fi.CI.IGT: failure for Remove _v2 functions in gpu pipelines 2020-05-29 12:36 ` Zbigniew Kempczyński @ 2020-05-29 13:26 ` Vudum, Lakshminarayana 0 siblings, 0 replies; 8+ messages in thread From: Vudum, Lakshminarayana @ 2020-05-29 13:26 UTC (permalink / raw) To: Kempczynski, Zbigniew, igt-dev@lists.freedesktop.org I have addressed the issue. -----Original Message----- From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com> Sent: Friday, May 29, 2020 3:36 PM To: igt-dev@lists.freedesktop.org Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com> Subject: Re: ✗ Fi.CI.IGT: failure for Remove _v2 functions in gpu pipelines On Fri, May 29, 2020 at 12:07:15PM +0000, Patchwork wrote: > == Series Details == > > Series: Remove _v2 functions in gpu pipelines > URL : https://patchwork.freedesktop.org/series/77782/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8552_full -> IGTPW_4623_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with IGTPW_4623_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in IGTPW_4623_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in IGTPW_4623_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@gem_exec_reloc@basic-gtt-cpu-active: > - shard-glk: [PASS][1] -> [TIMEOUT][2] +5 similar issues > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk7/igt@gem_exec_reloc@basic-gtt-cpu-active.html > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk2/igt@gem > _exec_reloc@basic-gtt-cpu-active.html Those tests were not touched by the code I've changed. -- Zbigniew > > > Known issues > ------------ > > Here are the changes found in IGTPW_4623_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_workarounds@suspend-resume-fd: > - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html > [4]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@gem > _workarounds@suspend-resume-fd.html > > * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen: > - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#54] / [i915#93] / [i915#95]) +1 similar issue > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html > [6]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@kms > _cursor_crc@pipe-a-cursor-64x64-onscreen.html > > * igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen: > - shard-apl: [PASS][7] -> [FAIL][8] ([i915#54]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html > - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#54]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html > [10]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl7/igt@kms > _cursor_crc@pipe-c-cursor-64x64-onscreen.html > > * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: > - shard-hsw: [PASS][11] -> [SKIP][12] ([fdo#109271]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html > [12]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw8/igt@kms > _cursor_legacy@2x-long-flip-vs-cursor-legacy.html > > * igt@kms_fbcon_fbt@fbc-suspend: > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html > [14]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl6/igt@kms > _fbcon_fbt@fbc-suspend.html > > * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-apl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265] / [i915#95]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [16]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl3/igt@kms > _plane_alpha_blend@pipe-a-coverage-7efc.html > > * igt@kms_psr@psr2_cursor_blt: > - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html > [18]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb7/igt@km > s_psr@psr2_cursor_blt.html > > > #### Possible fixes #### > > * igt@gem_ctx_persistence@engines-mixed-process@rcs0: > - shard-apl: [FAIL][19] ([i915#1528]) -> [PASS][20] > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl8/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html > [20]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@gem > _ctx_persistence@engines-mixed-process@rcs0.html > > * igt@gem_exec_whisper@basic-fds-forked-all: > - shard-hsw: [INCOMPLETE][21] ([i915#61]) -> [PASS][22] +1 similar issue > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@gem_exec_whisper@basic-fds-forked-all.html > [22]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw2/igt@gem > _exec_whisper@basic-fds-forked-all.html > > * igt@i915_pm_dc@dc3co-vpb-simulation: > - shard-tglb: [SKIP][23] ([i915#1904]) -> [PASS][24] > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb8/igt@i915_pm_dc@dc3co-vpb-simulation.html > [24]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb6/igt@i9 > 15_pm_dc@dc3co-vpb-simulation.html > > * igt@i915_pm_dc@dc5-psr: > - shard-iclb: [FAIL][25] ([i915#1899]) -> [PASS][26] > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb1/igt@i915_pm_dc@dc5-psr.html > [26]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb2/igt@i9 > 15_pm_dc@dc5-psr.html > > * igt@i915_suspend@sysfs-reader: > - shard-apl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +3 similar issues > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl4/igt@i915_suspend@sysfs-reader.html > [28]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@i91 > 5_suspend@sysfs-reader.html > > * igt@kms_big_fb@x-tiled-64bpp-rotate-0: > - shard-glk: [FAIL][29] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][30] > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html > [30]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk5/igt@kms > _big_fb@x-tiled-64bpp-rotate-0.html > > * igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen: > - shard-glk: [TIMEOUT][31] ([i915#1958]) -> [PASS][32] > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk4/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html > [32]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk8/igt@kms > _cursor_crc@pipe-a-cursor-64x21-onscreen.html > > * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: > - shard-hsw: [DMESG-FAIL][33] ([i915#1926]) -> [PASS][34] > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html > [34]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw4/igt@kms > _cursor_legacy@2x-long-cursor-vs-flip-legacy.html > > * igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled: > - shard-kbl: [FAIL][35] ([i915#177] / [i915#52] / [i915#54] / [i915#93] / [i915#95]) -> [PASS][36] +1 similar issue > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl6/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html > [36]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@kms > _draw_crc@draw-method-xrgb8888-blt-untiled.html > > * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled: > - shard-apl: [FAIL][37] ([i915#52] / [i915#54] / [i915#95]) -> [PASS][38] +1 similar issue > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html > [38]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl1/igt@kms > _draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html > > * igt@kms_fbcon_fbt@fbc-suspend: > - shard-snb: [DMESG-WARN][39] ([i915#42]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-snb5/igt@kms_fbcon_fbt@fbc-suspend.html > [40]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-snb2/igt@kms > _fbcon_fbt@fbc-suspend.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render: > - shard-snb: [SKIP][41] ([fdo#109271]) -> [PASS][42] +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html > [42]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-snb6/igt@kms > _frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html > > * igt@kms_hdmi_inject@inject-audio: > - shard-tglb: [SKIP][43] ([i915#433]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb8/igt@kms_hdmi_inject@inject-audio.html > [44]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb8/igt@km > s_hdmi_inject@inject-audio.html > > * igt@kms_panel_fitting@atomic-fastset: > - shard-iclb: [FAIL][45] ([i915#83]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb3/igt@kms_panel_fitting@atomic-fastset.html > [46]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb8/igt@km > s_panel_fitting@atomic-fastset.html > > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: > - shard-apl: [DMESG-WARN][47] ([i915#180] / [i915#95]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > [48]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl1/igt@kms > _plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > > * igt@kms_plane_cursor@pipe-a-viewport-size-64: > - shard-kbl: [FAIL][49] ([i915#1559] / [i915#93] / [i915#95]) -> [PASS][50] +1 similar issue > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl1/igt@kms_plane_cursor@pipe-a-viewport-size-64.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html > - shard-apl: [FAIL][51] ([i915#1559] / [i915#95]) -> [PASS][52] +1 similar issue > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html > [52]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@kms > _plane_cursor@pipe-a-viewport-size-64.html > > * igt@kms_psr@psr2_sprite_plane_move: > - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +2 similar issues > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html > [54]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb2/igt@km > s_psr@psr2_sprite_plane_move.html > > * igt@kms_vblank@pipe-b-ts-continuation-suspend: > - shard-kbl: [INCOMPLETE][55] ([i915#155]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html > [56]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl4/igt@kms > _vblank@pipe-b-ts-continuation-suspend.html > > * {igt@perf@blocking-parameterized}: > - shard-iclb: [FAIL][57] ([i915#1542]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb1/igt@perf@blocking-parameterized.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb6/igt@perf@blocking-parameterized.html > - shard-hsw: [FAIL][59] ([i915#1542]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@perf@blocking-parameterized.html > [60]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw4/igt@per > f@blocking-parameterized.html > > > #### Warnings #### > > * igt@i915_pm_dc@dc6-dpms: > - shard-glk: [TIMEOUT][61] ([i915#1958]) -> [SKIP][62] ([fdo#109271]) +1 similar issue > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk4/igt@i915_pm_dc@dc6-dpms.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk5/igt@i915_pm_dc@dc6-dpms.html > - shard-tglb: [FAIL][63] ([i915#454]) -> [SKIP][64] ([i915#468]) > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb5/igt@i915_pm_dc@dc6-dpms.html > [64]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb2/igt@i9 > 15_pm_dc@dc6-dpms.html > > * igt@i915_pm_dc@dc6-psr: > - shard-tglb: [SKIP][65] ([i915#468]) -> [FAIL][66] ([i915#454]) > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb2/igt@i915_pm_dc@dc6-psr.html > [66]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb1/igt@i9 > 15_pm_dc@dc6-psr.html > > * igt@kms_content_protection@atomic: > - shard-apl: [TIMEOUT][67] ([i915#1319] / [i915#1635]) -> [FAIL][68] ([fdo#110321] / [fdo#110336]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_content_protection@atomic.html > [68]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl6/igt@kms > _content_protection@atomic.html > > * igt@kms_content_protection@lic: > - shard-kbl: [FAIL][69] ([fdo#110321] / [i915#93] / [i915#95]) -> [TIMEOUT][70] ([i915#1319]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl2/igt@kms_content_protection@lic.html > [70]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl7/igt@kms > _content_protection@lic.html > > * igt@kms_content_protection@srm: > - shard-apl: [FAIL][71] ([fdo#110321]) -> [TIMEOUT][72] ([i915#1319] / [i915#1635]) > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl4/igt@kms_content_protection@srm.html > [72]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl4/igt@kms > _content_protection@srm.html > > * igt@kms_cursor_legacy@cursora-vs-flipb-toggle: > - shard-glk: [DMESG-FAIL][73] ([i915#1925]) -> [DMESG-FAIL][74] ([i915#1925] / [i915#1926]) +1 similar issue > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html > [74]: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk4/igt@kms > _cursor_legacy@cursora-vs-flipb-toggle.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 > [i915#1559]: https://gitlab.freedesktop.org/drm/intel/issues/1559 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 > [i915#1904]: https://gitlab.freedesktop.org/drm/intel/issues/1904 > [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 > [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42 > [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 > [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 > [i915#83]: https://gitlab.freedesktop.org/drm/intel/issues/83 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 8) > ------------------------------ > > Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7 > > > Build changes > ------------- > > * CI: CI-20190529 -> None > * IGT: IGT_5683 -> IGTPW_4623 > * Piglit: piglit_4509 -> None > > CI-20190529: 20190529 > CI_DRM_8552: cd4a9b47339259e3a98601fff14438f17fd2d7dc @ git://anongit.freedesktop.org/gfx-ci/linux > IGTPW_4623: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html > IGT_5683: 757b6e72d546fd2dbc3801a73796d67b0854021b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Remove _v2 functions in gpu pipelines 2020-05-29 10:41 [igt-dev] [PATCH i-g-t 0/2] Remove _v2 functions in gpu pipelines Zbigniew Kempczyński ` (3 preceding siblings ...) 2020-05-29 12:07 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork @ 2020-05-29 13:24 ` Patchwork 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2020-05-29 13:24 UTC (permalink / raw) To: Zbigniew Kempczyński; +Cc: igt-dev == Series Details == Series: Remove _v2 functions in gpu pipelines URL : https://patchwork.freedesktop.org/series/77782/ State : success == Summary == CI Bug Log - changes from CI_DRM_8552_full -> IGTPW_4623_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html Known issues ------------ Here are the changes found in IGTPW_4623_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_reloc@basic-gtt-cpu-active: - shard-glk: [PASS][1] -> [TIMEOUT][2] ([i915#1958]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk7/igt@gem_exec_reloc@basic-gtt-cpu-active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk2/igt@gem_exec_reloc@basic-gtt-cpu-active.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen: - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#54] / [i915#93] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html * igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-hsw: [PASS][11] -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-apl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html #### Possible fixes #### * igt@gem_ctx_persistence@engines-mixed-process@rcs0: - shard-apl: [FAIL][19] ([i915#1528]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl8/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html * igt@gem_exec_whisper@basic-fds-forked-all: - shard-hsw: [INCOMPLETE][21] ([i915#61]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@gem_exec_whisper@basic-fds-forked-all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw2/igt@gem_exec_whisper@basic-fds-forked-all.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-tglb: [SKIP][23] ([i915#1904]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb8/igt@i915_pm_dc@dc3co-vpb-simulation.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb6/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_dc@dc5-psr: - shard-iclb: [FAIL][25] ([i915#1899]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb1/igt@i915_pm_dc@dc5-psr.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb2/igt@i915_pm_dc@dc5-psr.html * igt@i915_suspend@sysfs-reader: - shard-apl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl4/igt@i915_suspend@sysfs-reader.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@i915_suspend@sysfs-reader.html * igt@kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [FAIL][29] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk5/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen: - shard-glk: [TIMEOUT][31] ([i915#1958]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk4/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [DMESG-FAIL][33] ([i915#1926]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled: - shard-kbl: [FAIL][35] ([i915#177] / [i915#52] / [i915#54] / [i915#93] / [i915#95]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl6/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl1/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled: - shard-apl: [FAIL][37] ([i915#52] / [i915#54] / [i915#95]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-snb: [DMESG-WARN][39] ([i915#42]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-snb5/igt@kms_fbcon_fbt@fbc-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-snb2/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render: - shard-snb: [SKIP][41] ([fdo#109271]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-snb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html * igt@kms_hdmi_inject@inject-audio: - shard-tglb: [SKIP][43] ([i915#433]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb8/igt@kms_hdmi_inject@inject-audio.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb8/igt@kms_hdmi_inject@inject-audio.html * igt@kms_panel_fitting@atomic-fastset: - shard-iclb: [FAIL][45] ([i915#83]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb3/igt@kms_panel_fitting@atomic-fastset.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb8/igt@kms_panel_fitting@atomic-fastset.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [DMESG-WARN][47] ([i915#180] / [i915#95]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_cursor@pipe-a-viewport-size-64: - shard-kbl: [FAIL][49] ([i915#1559] / [i915#93] / [i915#95]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl1/igt@kms_plane_cursor@pipe-a-viewport-size-64.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html - shard-apl: [FAIL][51] ([i915#1559] / [i915#95]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [INCOMPLETE][55] ([i915#155]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html * {igt@perf@blocking-parameterized}: - shard-iclb: [FAIL][57] ([i915#1542]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-iclb1/igt@perf@blocking-parameterized.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-iclb6/igt@perf@blocking-parameterized.html - shard-hsw: [FAIL][59] ([i915#1542]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-hsw8/igt@perf@blocking-parameterized.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-hsw4/igt@perf@blocking-parameterized.html #### Warnings #### * igt@i915_pm_dc@dc6-dpms: - shard-glk: [TIMEOUT][61] ([i915#1958]) -> [SKIP][62] ([fdo#109271]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk4/igt@i915_pm_dc@dc6-dpms.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk5/igt@i915_pm_dc@dc6-dpms.html - shard-tglb: [FAIL][63] ([i915#454]) -> [SKIP][64] ([i915#468]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb5/igt@i915_pm_dc@dc6-dpms.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][65] ([i915#468]) -> [FAIL][66] ([i915#454]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-tglb2/igt@i915_pm_dc@dc6-psr.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-tglb1/igt@i915_pm_dc@dc6-psr.html * igt@kms_content_protection@atomic: - shard-apl: [TIMEOUT][67] ([i915#1319] / [i915#1635]) -> [FAIL][68] ([fdo#110321] / [fdo#110336]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl1/igt@kms_content_protection@atomic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl6/igt@kms_content_protection@atomic.html * igt@kms_content_protection@lic: - shard-kbl: [FAIL][69] ([fdo#110321] / [i915#93] / [i915#95]) -> [TIMEOUT][70] ([i915#1319]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-kbl2/igt@kms_content_protection@lic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-kbl7/igt@kms_content_protection@lic.html * igt@kms_content_protection@srm: - shard-apl: [FAIL][71] ([fdo#110321]) -> [TIMEOUT][72] ([i915#1319] / [i915#1635]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-apl4/igt@kms_content_protection@srm.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-apl4/igt@kms_content_protection@srm.html * igt@kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [DMESG-FAIL][73] ([i915#1925]) -> [DMESG-FAIL][74] ([i915#1925] / [i915#1926]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8552/shard-glk2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/shard-glk4/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1559]: https://gitlab.freedesktop.org/drm/intel/issues/1559 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1904]: https://gitlab.freedesktop.org/drm/intel/issues/1904 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#83]: https://gitlab.freedesktop.org/drm/intel/issues/83 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 8) ------------------------------ Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5683 -> IGTPW_4623 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_8552: cd4a9b47339259e3a98601fff14438f17fd2d7dc @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_4623: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html IGT_5683: 757b6e72d546fd2dbc3801a73796d67b0854021b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4623/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-05-29 13:26 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-05-29 10:41 [igt-dev] [PATCH i-g-t 0/2] Remove _v2 functions in gpu pipelines Zbigniew Kempczyński 2020-05-29 10:41 ` [igt-dev] [PATCH i-g-t 1/2] lib/media_spin: localize pipeline functions Zbigniew Kempczyński 2020-05-29 10:41 ` [igt-dev] [PATCH i-g-t 2/2] tests/gem_(gpgpu|media)_fill: remove the _v2 suffix Zbigniew Kempczyński 2020-05-29 11:07 ` [igt-dev] ✓ Fi.CI.BAT: success for Remove _v2 functions in gpu pipelines Patchwork 2020-05-29 12:07 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 2020-05-29 12:36 ` Zbigniew Kempczyński 2020-05-29 13:26 ` Vudum, Lakshminarayana 2020-05-29 13:24 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
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