* [igt-dev] [PATCH v4 0/2] RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure
@ 2023-12-06 14:44 Bommu Krishnaiah
2023-12-06 14:44 ` [igt-dev] [PATCH v4 1/2] " Bommu Krishnaiah
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Bommu Krishnaiah @ 2023-12-06 14:44 UTC (permalink / raw)
To: igt-dev; +Cc: Bommu Krishnaiah
remove the num_engines/instances members from drm_xe_wait_user_fence structure
and add a exec_queue_id member
invalid-exec_queue-wait subtest to excess behaviour when exec_queue reset happen
about test
Skipping the GPU mapping(vm_bind) for object, so that exec_queue
reset will happen and xe_wait_ufence will end return EIO not ETIME
v3: fixed build failures
I am able to see exec_queue reset was happened and xe_wait_user_fence_ioctl returned EIO
test result
root@DUT7075PVC:/home/gta# LD_LIBRARY_PATH=/home/gta/ ./xe_waitfence --r invalid-exec_queue-wait
IGT-Version: 1.28-g3c0162fc4 (x86_64) (Linux: 6.6.0-rc3-xe x86_64)
Opened device: /dev/dri/card0
Starting subtest: invalid-exec_queue-wait
Subtest invalid-exec_queue-wait: SUCCESS (0.993s)
dmesg logs
[ 807.680378] [IGT] xe_waitfence: executing
[ 807.699796] [drm:drm_stub_open [drm]]
[ 807.704536] xe 0000:51:00.0: [drm:drm_open_helper [drm]] comm="xe_waitfence", pid=2952, minor=0
[ 807.715155] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, DRM_IOCTL_VERSION
[ 807.727328] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, DRM_IOCTL_VERSION
[ 807.739580] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_DEVICE_QUERY
[ 807.751518] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_DEVICE_QUERY
[ 807.763550] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_DEVICE_QUERY
[ 807.775525] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_DEVICE_QUERY
[ 807.787556] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_DEVICE_QUERY
[ 807.799494] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_DEVICE_QUERY
[ 807.811531] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_DEVICE_QUERY
[ 807.823476] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_DEVICE_QUERY
[ 807.835577] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, DRM_IOCTL_VERSION
[ 807.847921] [IGT] xe_waitfence: starting subtest invalid-exec_queue-wait
[ 807.855528] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_VM_CREATE
[ 807.891346] xe 0000:51:00.0: [drm:xe_reg_sr_apply_mmio [xe]] GT0: Applying GT save-restore MMIOs
[ 807.901602] xe 0000:51:00.0: [drm:xe_reg_sr_apply_mmio [xe]] GT0: REG[0x9424] = 0x7ffffffc
-----------------
-----------------
[ 808.560967] xe REG[0x4500-0x45ff]: deny rw access
[ 808.566292] xe REG[0x1e3a8-0x1e3af]: allow read access
[ 808.572161] xe 0000:51:00.0: [drm:xe_reg_sr_apply_mmio [xe]] GT0: Applying ccs3 save-restore MMIOs
[ 808.582462] xe 0000:51:00.0: [drm:xe_reg_sr_apply_mmio [xe]] GT0: REG[0x260c4] = 0x3f7e0104
[ 808.592096] xe 0000:51:00.0: [drm:xe_reg_sr_apply_whitelist [xe]] Whitelisting ccs3 registers
[ 808.601962] xe REG[0x4400-0x45ff]: deny rw access
[ 808.607281] xe REG[0x4500-0x45ff]: deny rw access
[ 808.612608] xe REG[0x263a8-0x263af]: allow read access
[ 808.618477] xe 0000:51:00.0: [drm] GT0: resumed
[ 808.626283] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_EXEC_QUEUE_CREATE
[ 808.638765] krishna xe_exec_queue_create_ioctl
[ 808.645592] krishna args->exec_queue_id = 1
[ 808.650328] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_GEM_CREATE
[ 808.662621] xe 0000:51:00.0: [drm:xe_migrate_clear [xe]] Pass 0, size: 262144
[ 808.672889] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_GEM_MMAP_OFFSET
[ 808.685733] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_EXEC
[ 808.696900] krishna args->exec_queue_id = 1
[ 808.702700] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_WAIT_USER_FENCE
[ 808.704620] xe 0000:51:00.0: [drm:pf_queue_work_func [xe]]
ASID: 1048575
VFID: 0
PDATA: 0x00a3
Faulted Address: 0x00000000001a0000
FaultType: 0
AccessType: 0
FaultLevel: 4
EngineClass: 3
EngineInstance: 0
[ 808.750685] xe 0000:51:00.0: [drm:pf_queue_work_func [xe]] Fault response: Unsuccessful -22
[ 808.760519] xe 0000:51:00.0: [drm:xe_guc_exec_queue_memory_cat_error_handler [xe]] Engine memory cat error: guc_id=2
[ 808.773237] xe 0000:51:00.0: [drm] exec gueue reset detected
[ 808.773965] xe 0000:51:00.0: [drm] Timedout job: seqno=4294967169, guc_id=2, flags=0x8
[ 808.779632] xe 0000:51:00.0: [drm:xe_wait_user_fence_ioctl [xe]] Ioctl argument check failed at drivers/gpu/drm/xe/xe_wait_user_fence.c:174: err < 0
[ 808.789655] xe 0000:51:00.0: [drm] Xe device coredump has been created
[ 808.803796] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence", pid=2952, ret=-5
[ 808.811133] xe 0000:51:00.0: [drm] Check your /sys/class/drm/card0/device/devcoredump/data
[ 808.811220] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, XE_EXEC_QUEUE_DESTROY
[ 808.823605] xe 0000:51:00.0: [drm] Engine reset: guc_id=2
[ 808.829862] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
[ 808.843312] xe 0000:51:00.0: [drm:guc_exec_queue_timedout_job [xe]] Timedout signaled job: seqno=4294967169, guc_id=2, flags=0x9
[ 808.848707] [IGT] xe_waitfence: finished subtest invalid-exec_queue-wait, SUCCESS
[ 808.882255] xe 0000:51:00.0: [drm:drm_ioctl [drm]] comm="xe_waitfence" pid=2952, dev=0xe200, auth=1, DRM_IOCTL_VERSION
[ 808.894404] xe 0000:51:00.0: [drm:drm_file_free.part.0 [drm]] comm="xe_waitfence", pid=2952, dev=0xe200, open_count=1
[ 808.907374] xe 0000:51:00.0: [drm:drm_lastclose [drm]]
[ 808.913594] xe 0000:51:00.0: [drm:drm_lastclose [drm]] driver lastclose completed
Need validate below tests
xe_exec_balancer.c
xe_exec_compute_mode.c
xe_exec_fault_mode.c
xe_exec_reset.c
xe_exec_threads.c
xe_waitfence.c
Bommu Krishnaiah (2):
drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence
structure
drm-uapi/xe: kill xe_wait_user_fence_ioctl when exec_queue reset
happen
include/drm-uapi/xe_drm.h | 16 ++--
lib/xe/xe_ioctl.c | 42 +--------
lib/xe/xe_ioctl.h | 6 +-
tests/intel/xe_evict.c | 4 +-
tests/intel/xe_exec_balancer.c | 12 +--
tests/intel/xe_exec_compute_mode.c | 12 +--
tests/intel/xe_exec_fault_mode.c | 14 +--
tests/intel/xe_exec_reset.c | 6 +-
tests/intel/xe_exec_threads.c | 12 +--
tests/intel/xe_waitfence.c | 141 ++++++++++++++++++++++-------
10 files changed, 150 insertions(+), 115 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [igt-dev] [PATCH v4 1/2] drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure 2023-12-06 14:44 [igt-dev] [PATCH v4 0/2] RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure Bommu Krishnaiah @ 2023-12-06 14:44 ` Bommu Krishnaiah 2023-12-06 17:04 ` Rodrigo Vivi 2023-12-06 14:44 ` [igt-dev] [PATCH v4 1/1] drm-uapi/xe: kill xe_wait_user_fence_ioctl when exec_queue reset happen Bommu Krishnaiah ` (4 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Bommu Krishnaiah @ 2023-12-06 14:44 UTC (permalink / raw) To: igt-dev; +Cc: Bommu Krishnaiah, Rodrigo Vivi remove the num_engines/instances members from drm_xe_wait_user_fence structure and add a exec_queue_id member Right now this is only checking if the engine list is sane and nothing else. In the end every operation with this IOCTL is a soft check. So, let's formalize that and only use this IOCTL to wait on the fence. exec_queue_id member will help to user space to get proper error code from kernel while in exec_queue reset Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Francois Dugast <francois.dugast@intel.com> --- include/drm-uapi/xe_drm.h | 16 ++---- lib/xe/xe_ioctl.c | 42 +------------- lib/xe/xe_ioctl.h | 6 +- tests/intel/xe_evict.c | 4 +- tests/intel/xe_exec_balancer.c | 12 ++-- tests/intel/xe_exec_compute_mode.c | 12 ++-- tests/intel/xe_exec_fault_mode.c | 14 ++--- tests/intel/xe_exec_reset.c | 6 +- tests/intel/xe_exec_threads.c | 12 ++-- tests/intel/xe_waitfence.c | 88 ++++++++++++++---------------- 10 files changed, 82 insertions(+), 130 deletions(-) diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index 590f7b7af..ceaca3991 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -1024,8 +1024,7 @@ struct drm_xe_wait_user_fence { /** @op: wait operation (type of comparison) */ __u16 op; -#define DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */ -#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 1) +#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) /** @flags: wait flags */ __u16 flags; @@ -1059,16 +1058,13 @@ struct drm_xe_wait_user_fence { __s64 timeout; /** - * @num_engines: number of engine instances to wait on, must be zero - * when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set + * @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl + * exec_queue_id is help to find exec_queue reset status */ - __u64 num_engines; + __u32 exec_queue_id; - /** - * @instances: user pointer to array of drm_xe_engine_class_instance to - * wait on, must be NULL when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set - */ - __u64 instances; + /** @reserved: Reserved */ + __u32 pad2; /** @reserved: Reserved */ __u64 reserved[2]; diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c index c91bf25c4..87e2db5b4 100644 --- a/lib/xe/xe_ioctl.c +++ b/lib/xe/xe_ioctl.c @@ -458,18 +458,16 @@ void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr) } int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t timeout) + uint32_t exec_queue, int64_t timeout) { struct drm_xe_wait_user_fence wait = { .addr = to_user_pointer(addr), .op = DRM_XE_UFENCE_WAIT_OP_EQ, - .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP : 0, + .flags = 0, .value = value, .mask = DRM_XE_UFENCE_WAIT_MASK_U64, .timeout = timeout, - .num_engines = eci ? 1 :0, - .instances = eci ? to_user_pointer(eci) : 0, + .exec_queue_id = exec_queue, }; igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0); @@ -477,40 +475,6 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, return wait.timeout; } -/** - * xe_wait_ufence_abstime: - * @fd: xe device fd - * @addr: address of value to compare - * @value: expected value (equal) in @address - * @eci: engine class instance - * @timeout: absolute time when wait expire - * - * Function compares @value with memory pointed by @addr until they are equal. - * - * Returns elapsed time in nanoseconds if user fence was signalled. - */ -int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t timeout) -{ - struct drm_xe_wait_user_fence wait = { - .addr = to_user_pointer(addr), - .op = DRM_XE_UFENCE_WAIT_OP_EQ, - .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP | DRM_XE_UFENCE_WAIT_FLAG_ABSTIME : 0, - .value = value, - .mask = DRM_XE_UFENCE_WAIT_MASK_U64, - .timeout = timeout, - .num_engines = eci ? 1 : 0, - .instances = eci ? to_user_pointer(eci) : 0, - }; - struct timespec ts; - - igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0); - igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); - - return ts.tv_sec * 1e9 + ts.tv_nsec; -} - void xe_force_gt_reset(int fd, int gt) { char reset_string[128]; diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h index 32b34b15a..186544a34 100644 --- a/lib/xe/xe_ioctl.h +++ b/lib/xe/xe_ioctl.h @@ -89,11 +89,9 @@ void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr, struct drm_xe_sync *sync, uint32_t num_syncs); void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr); int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t timeout); + uint32_t exec_queue,int64_t timeout); int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t timeout); + uint32_t exec_queue, int64_t timeout); void xe_force_gt_reset(int fd, int gt); #endif /* XE_IOCTL_H */ diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c index 89dc46fae..12fbaf586 100644 --- a/tests/intel/xe_evict.c +++ b/tests/intel/xe_evict.c @@ -317,7 +317,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, } #define TWENTY_SEC MS_TO_NS(20000) xe_wait_ufence(fd, &data[i].vm_sync, USER_FENCE_VALUE, - NULL, TWENTY_SEC); + 0, TWENTY_SEC); } sync[0].addr = addr + (char *)&data[i].exec_sync - (char *)data; @@ -352,7 +352,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, data = xe_bo_map(fd, __bo, ALIGN(sizeof(*data) * n_execs, 0x1000)); xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, - NULL, TWENTY_SEC); + exec_queues[i], TWENTY_SEC); igt_assert_eq(data[i].data, 0xc0ffee); } munmap(data, ALIGN(sizeof(*data) * n_execs, 0x1000)); diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c index 79ff65e89..0a02c6767 100644 --- a/tests/intel/xe_exec_balancer.c +++ b/tests/intel/xe_exec_balancer.c @@ -483,7 +483,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, bo_size, sync, 1); #define ONE_SEC MS_TO_NS(1000) - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); data[0].vm_sync = 0; for (i = 0; i < n_execs; i++) { @@ -514,7 +514,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, if (flags & REBIND && i + 1 != n_execs) { xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, - NULL, ONE_SEC); + exec_queues[e], ONE_SEC); xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, NULL, 0); @@ -529,7 +529,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, addr, bo_size, sync, 1); xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, - NULL, ONE_SEC); + 0, ONE_SEC); data[0].vm_sync = 0; } @@ -542,7 +542,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, * an invalidate. */ xe_wait_ufence(fd, &data[i].exec_sync, - USER_FENCE_VALUE, NULL, ONE_SEC); + USER_FENCE_VALUE, exec_queues[e], ONE_SEC); igt_assert_eq(data[i].data, 0xc0ffee); } else if (i * 2 != n_execs) { /* @@ -571,7 +571,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, j = flags & INVALIDATE && n_execs ? n_execs - 1 : 0; for (i = j; i < n_execs; i++) - xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, NULL, + xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, exec_queues[i], ONE_SEC); /* Wait for all execs to complete */ @@ -580,7 +580,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, sync[0].addr = to_user_pointer(&data[0].vm_sync); xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); for (i = (flags & INVALIDATE && n_execs) ? n_execs - 1 : 0; i < n_execs; i++) diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c index 7d3004d65..e8497a520 100644 --- a/tests/intel/xe_exec_compute_mode.c +++ b/tests/intel/xe_exec_compute_mode.c @@ -171,7 +171,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, fence_timeout = igt_run_in_simulation() ? HUNDRED_SEC : ONE_SEC; - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, fence_timeout); data[0].vm_sync = 0; @@ -198,7 +198,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, if (flags & REBIND && i + 1 != n_execs) { xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, - NULL, fence_timeout); + exec_queues[e], fence_timeout); xe_vm_unbind_async(fd, vm, bind_exec_queues[e], 0, addr, bo_size, NULL, 0); @@ -214,7 +214,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, addr, bo_size, sync, 1); xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, - NULL, fence_timeout); + 0, fence_timeout); data[0].vm_sync = 0; } @@ -227,7 +227,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, * an invalidate. */ xe_wait_ufence(fd, &data[i].exec_sync, - USER_FENCE_VALUE, NULL, + USER_FENCE_VALUE, exec_queues[e], fence_timeout); igt_assert_eq(data[i].data, 0xc0ffee); } else if (i * 2 != n_execs) { @@ -257,7 +257,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, j = flags & INVALIDATE ? n_execs - 1 : 0; for (i = j; i < n_execs; i++) - xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, NULL, + xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, exec_queues[i], fence_timeout); /* Wait for all execs to complete */ @@ -267,7 +267,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, sync[0].addr = to_user_pointer(&data[0].vm_sync); xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, bo_size, sync, 1); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, fence_timeout); for (i = j; i < n_execs; i++) diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c index ee7cbb604..27921f47a 100644 --- a/tests/intel/xe_exec_fault_mode.c +++ b/tests/intel/xe_exec_fault_mode.c @@ -195,14 +195,14 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, } #define ONE_SEC MS_TO_NS(1000) - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); data[0].vm_sync = 0; if (flags & PREFETCH) { /* Should move to system memory */ xe_vm_prefetch_async(fd, vm, bind_exec_queues[0], 0, addr, bo_size, sync, 1, 0); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); data[0].vm_sync = 0; } @@ -230,7 +230,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, if (flags & REBIND && i + 1 != n_execs) { xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, - NULL, ONE_SEC); + exec_queues[e], ONE_SEC); xe_vm_unbind_async(fd, vm, bind_exec_queues[e], 0, addr, bo_size, NULL, 0); @@ -246,7 +246,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, addr, bo_size, sync, 1); xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, - NULL, ONE_SEC); + 0, ONE_SEC); data[0].vm_sync = 0; } @@ -259,7 +259,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, * an invalidate. */ xe_wait_ufence(fd, &data[i].exec_sync, - USER_FENCE_VALUE, NULL, ONE_SEC); + USER_FENCE_VALUE, exec_queues[e], ONE_SEC); igt_assert_eq(data[i].data, 0xc0ffee); } else if (i * 2 != n_execs) { /* @@ -290,13 +290,13 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, j = flags & INVALIDATE ? n_execs - 1 : 0; for (i = j; i < n_execs; i++) xe_wait_ufence(fd, &data[i].exec_sync, - USER_FENCE_VALUE, NULL, ONE_SEC); + USER_FENCE_VALUE, exec_queues[i], ONE_SEC); } sync[0].addr = to_user_pointer(&data[0].vm_sync); xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, bo_size, sync, 1); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); if (!(flags & INVALID_FAULT)) { for (i = j; i < n_execs; i++) diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c index edfd27fe0..e133706ee 100644 --- a/tests/intel/xe_exec_reset.c +++ b/tests/intel/xe_exec_reset.c @@ -564,7 +564,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); #define THREE_SEC MS_TO_NS(3000) - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, THREE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, THREE_SEC); data[0].vm_sync = 0; for (i = 0; i < n_execs; i++) { @@ -618,11 +618,11 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, for (i = 1; i < n_execs; i++) xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, - NULL, THREE_SEC); + exec_queues[i], THREE_SEC); sync[0].addr = to_user_pointer(&data[0].vm_sync); xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, THREE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, THREE_SEC); for (i = 1; i < n_execs; i++) igt_assert_eq(data[i].data, 0xc0ffee); diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c index fcb926698..f8450a844 100644 --- a/tests/intel/xe_exec_threads.c +++ b/tests/intel/xe_exec_threads.c @@ -331,7 +331,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, fence_timeout = igt_run_in_simulation() ? THIRTY_SEC : THREE_SEC; - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, fence_timeout); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, fence_timeout); data[0].vm_sync = 0; for (i = 0; i < n_execs; i++) { @@ -359,7 +359,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, for (j = i - 0x20; j <= i; ++j) xe_wait_ufence(fd, &data[j].exec_sync, USER_FENCE_VALUE, - NULL, fence_timeout); + exec_queues[e], fence_timeout); xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, NULL, 0); @@ -374,7 +374,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, addr, bo_size, sync, 1); xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, - NULL, fence_timeout); + 0, fence_timeout); data[0].vm_sync = 0; } @@ -389,7 +389,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, for (j = i == 0x20 ? 0 : i - 0x1f; j <= i; ++j) xe_wait_ufence(fd, &data[j].exec_sync, USER_FENCE_VALUE, - NULL, fence_timeout); + exec_queues[e], fence_timeout); igt_assert_eq(data[i].data, 0xc0ffee); } else if (i * 2 != n_execs) { /* @@ -421,7 +421,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, j = flags & INVALIDATE ? (flags & RACE ? n_execs / 2 + 1 : n_execs - 1) : 0; for (i = j; i < n_execs; i++) - xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, NULL, + xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, exec_queues[i], fence_timeout); /* Wait for all execs to complete */ @@ -430,7 +430,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, sync[0].addr = to_user_pointer(&data[0].vm_sync); xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, fence_timeout); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, fence_timeout); for (i = j; i < n_execs; i++) igt_assert_eq(data[i].data, 0xc0ffee); diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c index 3be987954..0bd7e5dce 100644 --- a/tests/intel/xe_waitfence.c +++ b/tests/intel/xe_waitfence.c @@ -37,22 +37,51 @@ static void do_bind(int fd, uint32_t vm, uint32_t bo, uint64_t offset, } static int64_t wait_with_eci_abstime(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t timeout) + uint32_t exec_queue, int64_t timeout) { struct drm_xe_wait_user_fence wait = { .addr = to_user_pointer(addr), .op = DRM_XE_UFENCE_WAIT_OP_EQ, - .flags = !eci ? 0 : DRM_XE_UFENCE_WAIT_FLAG_ABSTIME, + .flags = !exec_queue ? 0 : DRM_XE_UFENCE_WAIT_FLAG_ABSTIME, .value = value, .mask = DRM_XE_UFENCE_WAIT_MASK_U64, .timeout = timeout, - .num_engines = eci ? 1 : 0, - .instances = eci ? to_user_pointer(eci) : 0, + .exec_queue_id = exec_queue, + }; + struct timespec ts; + + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0); + igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); + + return ts.tv_sec * 1e9 + ts.tv_nsec; +} + +/** + * xe_wait_ufence_abstime: + * @fd: xe device fd + * @addr: address of value to compare + * @value: expected value (equal) in @address + * @exec_queue: exec_queue id + * @timeout: absolute time when wait expire + * + * Function compares @value with memory pointed by @addr until they are equal. + * + * Returns elapsed time in nanoseconds if user fence was signalled. + */ +int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, + uint32_t exec_queue, int64_t timeout) +{ + struct drm_xe_wait_user_fence wait = { + .addr = to_user_pointer(addr), + .op = DRM_XE_UFENCE_WAIT_OP_EQ, + .flags = !exec_queue ? DRM_XE_UFENCE_WAIT_FLAG_ABSTIME : 0, + .value = value, + .mask = DRM_XE_UFENCE_WAIT_MASK_U64, + .timeout = timeout, + .exec_queue_id = exec_queue, }; struct timespec ts; - igt_assert(eci); igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0); igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); @@ -82,7 +111,6 @@ enum waittype { static void waitfence(int fd, enum waittype wt) { - struct drm_xe_engine *engine = NULL; struct timespec ts; int64_t current, signalled; uint32_t bo_1; @@ -111,15 +139,15 @@ waitfence(int fd, enum waittype wt) do_bind(fd, vm, bo_7, 0, 0xeffff0000, 0x10000, 7); if (wt == RELTIME) { - timeout = xe_wait_ufence(fd, &wait_fence, 7, NULL, MS_TO_NS(10)); + timeout = xe_wait_ufence(fd, &wait_fence, 7, 0, MS_TO_NS(10)); igt_debug("wait type: RELTIME - timeout: %ld, timeout left: %ld\n", MS_TO_NS(10), timeout); } else if (wt == ENGINE) { - engine = xe_engine(fd, 1); + uint32_t exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); clock_gettime(CLOCK_MONOTONIC, &ts); current = ts.tv_sec * 1e9 + ts.tv_nsec; timeout = current + MS_TO_NS(10); - signalled = wait_with_eci_abstime(fd, &wait_fence, 7, &engine->instance, timeout); + signalled = wait_with_eci_abstime(fd, &wait_fence, 7, exec_queue, timeout); igt_debug("wait type: ENGINE ABSTIME - timeout: %" PRId64 ", signalled: %" PRId64 ", elapsed: %" PRId64 "\n", @@ -128,7 +156,7 @@ waitfence(int fd, enum waittype wt) clock_gettime(CLOCK_MONOTONIC, &ts); current = ts.tv_sec * 1e9 + ts.tv_nsec; timeout = current + MS_TO_NS(10); - signalled = xe_wait_ufence_abstime(fd, &wait_fence, 7, NULL, timeout); + signalled = xe_wait_ufence_abstime(fd, &wait_fence, 7, 0, timeout); igt_debug("wait type: ABSTIME - timeout: %" PRId64 ", signalled: %" PRId64 ", elapsed: %" PRId64 "\n", @@ -149,9 +177,6 @@ waitfence(int fd, enum waittype wt) * * SUBTEST: invalid-ops * Description: Check query with invalid ops returns expected error code - * - * SUBTEST: invalid-engine - * Description: Check query with invalid engine info returns expected error code */ static void @@ -166,8 +191,7 @@ invalid_flag(int fd) .value = 1, .mask = DRM_XE_UFENCE_WAIT_MASK_U64, .timeout = -1, - .num_engines = 0, - .instances = 0, + .exec_queue_id = 0, }; uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); @@ -191,8 +215,7 @@ invalid_ops(int fd) .value = 1, .mask = DRM_XE_UFENCE_WAIT_MASK_U64, .timeout = 1, - .num_engines = 0, - .instances = 0, + .exec_queue_id = 0, }; uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); @@ -204,32 +227,6 @@ invalid_ops(int fd) do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EINVAL); } -static void -invalid_engine(int fd) -{ - uint32_t bo; - - struct drm_xe_wait_user_fence wait = { - .addr = to_user_pointer(&wait_fence), - .op = DRM_XE_UFENCE_WAIT_OP_EQ, - .flags = 0, - .value = 1, - .mask = DRM_XE_UFENCE_WAIT_MASK_U64, - .timeout = -1, - .num_engines = 1, - .instances = 0, - }; - - uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); - - bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); - - do_bind(fd, vm, bo, 0, 0x200000, 0x40000, 1); - - do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EFAULT); -} - - igt_main { int fd; @@ -252,9 +249,6 @@ igt_main igt_subtest("invalid-ops") invalid_ops(fd); - igt_subtest("invalid-engine") - invalid_engine(fd); - igt_fixture drm_close_driver(fd); } -- 2.25.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 1/2] drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure 2023-12-06 14:44 ` [igt-dev] [PATCH v4 1/2] " Bommu Krishnaiah @ 2023-12-06 17:04 ` Rodrigo Vivi 2023-12-06 17:23 ` Bommu, Krishnaiah 0 siblings, 1 reply; 12+ messages in thread From: Rodrigo Vivi @ 2023-12-06 17:04 UTC (permalink / raw) To: Bommu Krishnaiah; +Cc: igt-dev On Wed, Dec 06, 2023 at 08:14:50PM +0530, Bommu Krishnaiah wrote: > remove the num_engines/instances members from drm_xe_wait_user_fence structure > and add a exec_queue_id member > > Right now this is only checking if the engine list is sane and nothing > else. In the end every operation with this IOCTL is a soft check. > So, let's formalize that and only use this IOCTL to wait on the fence. > > exec_queue_id member will help to user space to get proper error code > from kernel while in exec_queue reset > > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Francois Dugast <francois.dugast@intel.com> > --- > include/drm-uapi/xe_drm.h | 16 ++---- Since you are touching the header file it would be good if you could add a mention to the commit message of which kernel patch you were when you aligned this header. Something like xe_drm.h aligns with kernel commit ("drm/xe/uapi: Return correct error code for xe_wait_user_fence_ioctl") (no need to add the commit hash since it is still volatile in drm-xe-next) Also ensure that you do not copy the header directly, but always make it from the kernel and then copy the 'built' one. make headers_install INSTALL_HDR_PATH=/tmp/blah cp /tmp/blah/include/drm/xe_drm.h ./include/drm-uapi/xe_drm.h > lib/xe/xe_ioctl.c | 42 +------------- > lib/xe/xe_ioctl.h | 6 +- > tests/intel/xe_evict.c | 4 +- > tests/intel/xe_exec_balancer.c | 12 ++-- > tests/intel/xe_exec_compute_mode.c | 12 ++-- > tests/intel/xe_exec_fault_mode.c | 14 ++--- > tests/intel/xe_exec_reset.c | 6 +- > tests/intel/xe_exec_threads.c | 12 ++-- > tests/intel/xe_waitfence.c | 88 ++++++++++++++---------------- > 10 files changed, 82 insertions(+), 130 deletions(-) > > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h > index 590f7b7af..ceaca3991 100644 > --- a/include/drm-uapi/xe_drm.h > +++ b/include/drm-uapi/xe_drm.h > @@ -1024,8 +1024,7 @@ struct drm_xe_wait_user_fence { > /** @op: wait operation (type of comparison) */ > __u16 op; > > -#define DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */ > -#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 1) > +#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) > /** @flags: wait flags */ > __u16 flags; > > @@ -1059,16 +1058,13 @@ struct drm_xe_wait_user_fence { > __s64 timeout; > > /** > - * @num_engines: number of engine instances to wait on, must be zero > - * when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set > + * @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl > + * exec_queue_id is help to find exec_queue reset status > */ > - __u64 num_engines; > + __u32 exec_queue_id; > > - /** > - * @instances: user pointer to array of drm_xe_engine_class_instance to > - * wait on, must be NULL when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set > - */ > - __u64 instances; > + /** @reserved: Reserved */ please fix the alignments and pad doc as Francois already pointed out and then when that is finalized, import the result here as mentioned above. > + __u32 pad2; > > /** @reserved: Reserved */ > __u64 reserved[2]; > diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c > index c91bf25c4..87e2db5b4 100644 > --- a/lib/xe/xe_ioctl.c > +++ b/lib/xe/xe_ioctl.c > @@ -458,18 +458,16 @@ void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr) > } > > int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, > - struct drm_xe_engine_class_instance *eci, > - int64_t timeout) > + uint32_t exec_queue, int64_t timeout) > { > struct drm_xe_wait_user_fence wait = { > .addr = to_user_pointer(addr), > .op = DRM_XE_UFENCE_WAIT_OP_EQ, > - .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP : 0, > + .flags = 0, > .value = value, > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > .timeout = timeout, > - .num_engines = eci ? 1 :0, > - .instances = eci ? to_user_pointer(eci) : 0, > + .exec_queue_id = exec_queue, > }; > > igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0); > @@ -477,40 +475,6 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, > return wait.timeout; > } > > -/** > - * xe_wait_ufence_abstime: > - * @fd: xe device fd > - * @addr: address of value to compare > - * @value: expected value (equal) in @address > - * @eci: engine class instance > - * @timeout: absolute time when wait expire > - * > - * Function compares @value with memory pointed by @addr until they are equal. > - * > - * Returns elapsed time in nanoseconds if user fence was signalled. > - */ > -int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, > - struct drm_xe_engine_class_instance *eci, > - int64_t timeout) > -{ > - struct drm_xe_wait_user_fence wait = { > - .addr = to_user_pointer(addr), > - .op = DRM_XE_UFENCE_WAIT_OP_EQ, > - .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP | DRM_XE_UFENCE_WAIT_FLAG_ABSTIME : 0, > - .value = value, > - .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > - .timeout = timeout, > - .num_engines = eci ? 1 : 0, > - .instances = eci ? to_user_pointer(eci) : 0, > - }; > - struct timespec ts; > - > - igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0); > - igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); > - > - return ts.tv_sec * 1e9 + ts.tv_nsec; > -} Well, I believe it would be better this movement in a separated patch. > - > void xe_force_gt_reset(int fd, int gt) > { > char reset_string[128]; > diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h > index 32b34b15a..186544a34 100644 > --- a/lib/xe/xe_ioctl.h > +++ b/lib/xe/xe_ioctl.h > @@ -89,11 +89,9 @@ void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr, > struct drm_xe_sync *sync, uint32_t num_syncs); > void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr); > int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, > - struct drm_xe_engine_class_instance *eci, > - int64_t timeout); > + uint32_t exec_queue,int64_t timeout); > int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, > - struct drm_xe_engine_class_instance *eci, > - int64_t timeout); > + uint32_t exec_queue, int64_t timeout); > void xe_force_gt_reset(int fd, int gt); > > #endif /* XE_IOCTL_H */ > diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c > index 89dc46fae..12fbaf586 100644 > --- a/tests/intel/xe_evict.c > +++ b/tests/intel/xe_evict.c > @@ -317,7 +317,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, > } > #define TWENTY_SEC MS_TO_NS(20000) > xe_wait_ufence(fd, &data[i].vm_sync, USER_FENCE_VALUE, > - NULL, TWENTY_SEC); > + 0, TWENTY_SEC); > } > sync[0].addr = addr + (char *)&data[i].exec_sync - > (char *)data; > @@ -352,7 +352,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, > data = xe_bo_map(fd, __bo, > ALIGN(sizeof(*data) * n_execs, 0x1000)); > xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, > - NULL, TWENTY_SEC); > + exec_queues[i], TWENTY_SEC); > igt_assert_eq(data[i].data, 0xc0ffee); > } > munmap(data, ALIGN(sizeof(*data) * n_execs, 0x1000)); > diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c > index 79ff65e89..0a02c6767 100644 > --- a/tests/intel/xe_exec_balancer.c > +++ b/tests/intel/xe_exec_balancer.c > @@ -483,7 +483,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > bo_size, sync, 1); > > #define ONE_SEC MS_TO_NS(1000) > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); > data[0].vm_sync = 0; > > for (i = 0; i < n_execs; i++) { > @@ -514,7 +514,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > > if (flags & REBIND && i + 1 != n_execs) { > xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, > - NULL, ONE_SEC); > + exec_queues[e], ONE_SEC); > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, NULL, > 0); > > @@ -529,7 +529,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > addr, bo_size, sync, > 1); > xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, > - NULL, ONE_SEC); > + 0, ONE_SEC); > data[0].vm_sync = 0; > } > > @@ -542,7 +542,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > * an invalidate. > */ > xe_wait_ufence(fd, &data[i].exec_sync, > - USER_FENCE_VALUE, NULL, ONE_SEC); > + USER_FENCE_VALUE, exec_queues[e], ONE_SEC); > igt_assert_eq(data[i].data, 0xc0ffee); > } else if (i * 2 != n_execs) { > /* > @@ -571,7 +571,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > > j = flags & INVALIDATE && n_execs ? n_execs - 1 : 0; > for (i = j; i < n_execs; i++) > - xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, NULL, > + xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, exec_queues[i], > ONE_SEC); > > /* Wait for all execs to complete */ > @@ -580,7 +580,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); > > for (i = (flags & INVALIDATE && n_execs) ? n_execs - 1 : 0; > i < n_execs; i++) > diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c > index 7d3004d65..e8497a520 100644 > --- a/tests/intel/xe_exec_compute_mode.c > +++ b/tests/intel/xe_exec_compute_mode.c > @@ -171,7 +171,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > fence_timeout = igt_run_in_simulation() ? HUNDRED_SEC : ONE_SEC; > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > fence_timeout); > data[0].vm_sync = 0; > > @@ -198,7 +198,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > if (flags & REBIND && i + 1 != n_execs) { > xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, > - NULL, fence_timeout); > + exec_queues[e], fence_timeout); > xe_vm_unbind_async(fd, vm, bind_exec_queues[e], 0, > addr, bo_size, NULL, 0); > > @@ -214,7 +214,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > addr, bo_size, sync, > 1); > xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, > - NULL, fence_timeout); > + 0, fence_timeout); > data[0].vm_sync = 0; > } > > @@ -227,7 +227,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > * an invalidate. > */ > xe_wait_ufence(fd, &data[i].exec_sync, > - USER_FENCE_VALUE, NULL, > + USER_FENCE_VALUE, exec_queues[e], > fence_timeout); > igt_assert_eq(data[i].data, 0xc0ffee); > } else if (i * 2 != n_execs) { > @@ -257,7 +257,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > j = flags & INVALIDATE ? n_execs - 1 : 0; > for (i = j; i < n_execs; i++) > - xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, NULL, > + xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, exec_queues[i], > fence_timeout); > > /* Wait for all execs to complete */ > @@ -267,7 +267,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > sync[0].addr = to_user_pointer(&data[0].vm_sync); > xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, bo_size, > sync, 1); > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > fence_timeout); > > for (i = j; i < n_execs; i++) > diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c > index ee7cbb604..27921f47a 100644 > --- a/tests/intel/xe_exec_fault_mode.c > +++ b/tests/intel/xe_exec_fault_mode.c > @@ -195,14 +195,14 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > } > > #define ONE_SEC MS_TO_NS(1000) > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); > data[0].vm_sync = 0; > > if (flags & PREFETCH) { > /* Should move to system memory */ > xe_vm_prefetch_async(fd, vm, bind_exec_queues[0], 0, addr, > bo_size, sync, 1, 0); > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > ONE_SEC); > data[0].vm_sync = 0; > } > @@ -230,7 +230,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > if (flags & REBIND && i + 1 != n_execs) { > xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, > - NULL, ONE_SEC); > + exec_queues[e], ONE_SEC); > xe_vm_unbind_async(fd, vm, bind_exec_queues[e], 0, > addr, bo_size, NULL, 0); > > @@ -246,7 +246,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > addr, bo_size, sync, > 1); > xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, > - NULL, ONE_SEC); > + 0, ONE_SEC); > data[0].vm_sync = 0; > } > > @@ -259,7 +259,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > * an invalidate. > */ > xe_wait_ufence(fd, &data[i].exec_sync, > - USER_FENCE_VALUE, NULL, ONE_SEC); > + USER_FENCE_VALUE, exec_queues[e], ONE_SEC); > igt_assert_eq(data[i].data, 0xc0ffee); > } else if (i * 2 != n_execs) { > /* > @@ -290,13 +290,13 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > j = flags & INVALIDATE ? n_execs - 1 : 0; > for (i = j; i < n_execs; i++) > xe_wait_ufence(fd, &data[i].exec_sync, > - USER_FENCE_VALUE, NULL, ONE_SEC); > + USER_FENCE_VALUE, exec_queues[i], ONE_SEC); > } > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, bo_size, > sync, 1); just to confirm... we don't need to get the bind_exec_queues there right?! > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); > > if (!(flags & INVALID_FAULT)) { > for (i = j; i < n_execs; i++) > diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c > index edfd27fe0..e133706ee 100644 > --- a/tests/intel/xe_exec_reset.c > +++ b/tests/intel/xe_exec_reset.c > @@ -564,7 +564,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); > > #define THREE_SEC MS_TO_NS(3000) > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, THREE_SEC); > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, THREE_SEC); > data[0].vm_sync = 0; > > for (i = 0; i < n_execs; i++) { > @@ -618,11 +618,11 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > > for (i = 1; i < n_execs; i++) > xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, > - NULL, THREE_SEC); > + exec_queues[i], THREE_SEC); > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, THREE_SEC); > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, THREE_SEC); why do you pick '0' here and 'exec_queue' in other places in this same code? > > for (i = 1; i < n_execs; i++) > igt_assert_eq(data[i].data, 0xc0ffee); > diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c > index fcb926698..f8450a844 100644 > --- a/tests/intel/xe_exec_threads.c > +++ b/tests/intel/xe_exec_threads.c > @@ -331,7 +331,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > > fence_timeout = igt_run_in_simulation() ? THIRTY_SEC : THREE_SEC; > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, fence_timeout); > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, fence_timeout); > data[0].vm_sync = 0; > > for (i = 0; i < n_execs; i++) { > @@ -359,7 +359,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > for (j = i - 0x20; j <= i; ++j) > xe_wait_ufence(fd, &data[j].exec_sync, > USER_FENCE_VALUE, > - NULL, fence_timeout); > + exec_queues[e], fence_timeout); > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, > NULL, 0); > > @@ -374,7 +374,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > addr, bo_size, sync, > 1); > xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, > - NULL, fence_timeout); > + 0, fence_timeout); > data[0].vm_sync = 0; > } > > @@ -389,7 +389,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > for (j = i == 0x20 ? 0 : i - 0x1f; j <= i; ++j) > xe_wait_ufence(fd, &data[j].exec_sync, > USER_FENCE_VALUE, > - NULL, fence_timeout); > + exec_queues[e], fence_timeout); > igt_assert_eq(data[i].data, 0xc0ffee); > } else if (i * 2 != n_execs) { > /* > @@ -421,7 +421,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > j = flags & INVALIDATE ? > (flags & RACE ? n_execs / 2 + 1 : n_execs - 1) : 0; > for (i = j; i < n_execs; i++) > - xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, NULL, > + xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, exec_queues[i], > fence_timeout); > > /* Wait for all execs to complete */ > @@ -430,7 +430,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, fence_timeout); > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, fence_timeout); > > for (i = j; i < n_execs; i++) > igt_assert_eq(data[i].data, 0xc0ffee); > diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c > index 3be987954..0bd7e5dce 100644 > --- a/tests/intel/xe_waitfence.c > +++ b/tests/intel/xe_waitfence.c > @@ -37,22 +37,51 @@ static void do_bind(int fd, uint32_t vm, uint32_t bo, uint64_t offset, > } > > static int64_t wait_with_eci_abstime(int fd, uint64_t *addr, uint64_t value, > - struct drm_xe_engine_class_instance *eci, > - int64_t timeout) > + uint32_t exec_queue, int64_t timeout) > { > struct drm_xe_wait_user_fence wait = { > .addr = to_user_pointer(addr), > .op = DRM_XE_UFENCE_WAIT_OP_EQ, > - .flags = !eci ? 0 : DRM_XE_UFENCE_WAIT_FLAG_ABSTIME, > + .flags = !exec_queue ? 0 : DRM_XE_UFENCE_WAIT_FLAG_ABSTIME, > .value = value, > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > .timeout = timeout, > - .num_engines = eci ? 1 : 0, > - .instances = eci ? to_user_pointer(eci) : 0, > + .exec_queue_id = exec_queue, > + }; > + struct timespec ts; > + > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0); > + igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); > + > + return ts.tv_sec * 1e9 + ts.tv_nsec; > +} > + > +/** > + * xe_wait_ufence_abstime: > + * @fd: xe device fd > + * @addr: address of value to compare > + * @value: expected value (equal) in @address > + * @exec_queue: exec_queue id > + * @timeout: absolute time when wait expire > + * > + * Function compares @value with memory pointed by @addr until they are equal. > + * > + * Returns elapsed time in nanoseconds if user fence was signalled. > + */ > +int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, > + uint32_t exec_queue, int64_t timeout) > +{ > + struct drm_xe_wait_user_fence wait = { > + .addr = to_user_pointer(addr), > + .op = DRM_XE_UFENCE_WAIT_OP_EQ, > + .flags = !exec_queue ? DRM_XE_UFENCE_WAIT_FLAG_ABSTIME : 0, > + .value = value, > + .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > + .timeout = timeout, > + .exec_queue_id = exec_queue, > }; > struct timespec ts; > > - igt_assert(eci); > igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0); > igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); > > @@ -82,7 +111,6 @@ enum waittype { > static void > waitfence(int fd, enum waittype wt) > { > - struct drm_xe_engine *engine = NULL; > struct timespec ts; > int64_t current, signalled; > uint32_t bo_1; > @@ -111,15 +139,15 @@ waitfence(int fd, enum waittype wt) > do_bind(fd, vm, bo_7, 0, 0xeffff0000, 0x10000, 7); > > if (wt == RELTIME) { > - timeout = xe_wait_ufence(fd, &wait_fence, 7, NULL, MS_TO_NS(10)); > + timeout = xe_wait_ufence(fd, &wait_fence, 7, 0, MS_TO_NS(10)); > igt_debug("wait type: RELTIME - timeout: %ld, timeout left: %ld\n", > MS_TO_NS(10), timeout); > } else if (wt == ENGINE) { > - engine = xe_engine(fd, 1); > + uint32_t exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); > clock_gettime(CLOCK_MONOTONIC, &ts); > current = ts.tv_sec * 1e9 + ts.tv_nsec; > timeout = current + MS_TO_NS(10); > - signalled = wait_with_eci_abstime(fd, &wait_fence, 7, &engine->instance, timeout); > + signalled = wait_with_eci_abstime(fd, &wait_fence, 7, exec_queue, timeout); > igt_debug("wait type: ENGINE ABSTIME - timeout: %" PRId64 > ", signalled: %" PRId64 > ", elapsed: %" PRId64 "\n", > @@ -128,7 +156,7 @@ waitfence(int fd, enum waittype wt) > clock_gettime(CLOCK_MONOTONIC, &ts); > current = ts.tv_sec * 1e9 + ts.tv_nsec; > timeout = current + MS_TO_NS(10); > - signalled = xe_wait_ufence_abstime(fd, &wait_fence, 7, NULL, timeout); > + signalled = xe_wait_ufence_abstime(fd, &wait_fence, 7, 0, timeout); > igt_debug("wait type: ABSTIME - timeout: %" PRId64 > ", signalled: %" PRId64 > ", elapsed: %" PRId64 "\n", > @@ -149,9 +177,6 @@ waitfence(int fd, enum waittype wt) > * > * SUBTEST: invalid-ops > * Description: Check query with invalid ops returns expected error code > - * > - * SUBTEST: invalid-engine > - * Description: Check query with invalid engine info returns expected error code > */ > > static void > @@ -166,8 +191,7 @@ invalid_flag(int fd) > .value = 1, > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > .timeout = -1, > - .num_engines = 0, > - .instances = 0, > + .exec_queue_id = 0, > }; > > uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); > @@ -191,8 +215,7 @@ invalid_ops(int fd) > .value = 1, > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > .timeout = 1, > - .num_engines = 0, > - .instances = 0, > + .exec_queue_id = 0, > }; > > uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); > @@ -204,32 +227,6 @@ invalid_ops(int fd) > do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EINVAL); > } > > -static void > -invalid_engine(int fd) > -{ > - uint32_t bo; > - > - struct drm_xe_wait_user_fence wait = { > - .addr = to_user_pointer(&wait_fence), > - .op = DRM_XE_UFENCE_WAIT_OP_EQ, > - .flags = 0, > - .value = 1, > - .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > - .timeout = -1, > - .num_engines = 1, > - .instances = 0, > - }; > - > - uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); > - > - bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); > - > - do_bind(fd, vm, bo, 0, 0x200000, 0x40000, 1); > - > - do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EFAULT); > -} > - why are you removing this? should be in a separate patch as well > - > igt_main > { > int fd; > @@ -252,9 +249,6 @@ igt_main > igt_subtest("invalid-ops") > invalid_ops(fd); > > - igt_subtest("invalid-engine") > - invalid_engine(fd); > - > igt_fixture > drm_close_driver(fd); > } > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 1/2] drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure 2023-12-06 17:04 ` Rodrigo Vivi @ 2023-12-06 17:23 ` Bommu, Krishnaiah 2023-12-06 17:36 ` Rodrigo Vivi 0 siblings, 1 reply; 12+ messages in thread From: Bommu, Krishnaiah @ 2023-12-06 17:23 UTC (permalink / raw) To: Vivi, Rodrigo; +Cc: igt-dev@lists.freedesktop.org > -----Original Message----- > From: Vivi, Rodrigo <rodrigo.vivi@intel.com> > Sent: Wednesday, December 6, 2023 10:34 PM > To: Bommu, Krishnaiah <krishnaiah.bommu@intel.com> > Cc: igt-dev@lists.freedesktop.org > Subject: Re: [igt-dev] [PATCH v4 1/2] drm-uapi/xe: add exec_queue_id > member to drm_xe_wait_user_fence structure > > On Wed, Dec 06, 2023 at 08:14:50PM +0530, Bommu Krishnaiah wrote: > > remove the num_engines/instances members from > drm_xe_wait_user_fence > > structure and add a exec_queue_id member > > > > Right now this is only checking if the engine list is sane and nothing > > else. In the end every operation with this IOCTL is a soft check. > > So, let's formalize that and only use this IOCTL to wait on the fence. > > > > exec_queue_id member will help to user space to get proper error code > > from kernel while in exec_queue reset > > > > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: Francois Dugast <francois.dugast@intel.com> > > --- > > include/drm-uapi/xe_drm.h | 16 ++---- > > Since you are touching the header file it would be good if you could add a > mention to the commit message of which kernel patch you were when you > aligned this header. > > Something like xe_drm.h aligns with kernel commit ("drm/xe/uapi: Return > correct error code for xe_wait_user_fence_ioctl") > > (no need to add the commit hash since it is still volatile in drm-xe-next) > > Also ensure that you do not copy the header directly, but always make it > from the kernel and then copy the 'built' one. > > make headers_install INSTALL_HDR_PATH=/tmp/blah cp > /tmp/blah/include/drm/xe_drm.h ./include/drm-uapi/xe_drm.h I will update in next version > > > > lib/xe/xe_ioctl.c | 42 +------------- > > lib/xe/xe_ioctl.h | 6 +- > > tests/intel/xe_evict.c | 4 +- > > tests/intel/xe_exec_balancer.c | 12 ++-- > > tests/intel/xe_exec_compute_mode.c | 12 ++-- > > tests/intel/xe_exec_fault_mode.c | 14 ++--- > > tests/intel/xe_exec_reset.c | 6 +- > > tests/intel/xe_exec_threads.c | 12 ++-- > > tests/intel/xe_waitfence.c | 88 ++++++++++++++---------------- > > 10 files changed, 82 insertions(+), 130 deletions(-) > > > > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h > > index 590f7b7af..ceaca3991 100644 > > --- a/include/drm-uapi/xe_drm.h > > +++ b/include/drm-uapi/xe_drm.h > > @@ -1024,8 +1024,7 @@ struct drm_xe_wait_user_fence { > > /** @op: wait operation (type of comparison) */ > > __u16 op; > > > > -#define DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP (1 << 0) /* e.g. Wait > on VM bind */ > > -#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 1) > > +#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) > > /** @flags: wait flags */ > > __u16 flags; > > > > @@ -1059,16 +1058,13 @@ struct drm_xe_wait_user_fence { > > __s64 timeout; > > > > /** > > - * @num_engines: number of engine instances to wait on, must be > zero > > - * when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set > > + * @exec_queue_id: exec_queue_id returned from > xe_exec_queue_create_ioctl > > + * exec_queue_id is help to find exec_queue reset status > > */ > > - __u64 num_engines; > > + __u32 exec_queue_id; > > > > - /** > > - * @instances: user pointer to array of > drm_xe_engine_class_instance to > > - * wait on, must be NULL when > DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set > > - */ > > - __u64 instances; > > + /** @reserved: Reserved */ > > please fix the alignments and pad doc as Francois already pointed out and > then when that is finalized, import the result here as mentioned above. I will update in next version > > > + __u32 pad2; > > > > /** @reserved: Reserved */ > > __u64 reserved[2]; > > diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c index > > c91bf25c4..87e2db5b4 100644 > > --- a/lib/xe/xe_ioctl.c > > +++ b/lib/xe/xe_ioctl.c > > @@ -458,18 +458,16 @@ void xe_exec_wait(int fd, uint32_t exec_queue, > > uint64_t addr) } > > > > int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, > > - struct drm_xe_engine_class_instance *eci, > > - int64_t timeout) > > + uint32_t exec_queue, int64_t timeout) > > { > > struct drm_xe_wait_user_fence wait = { > > .addr = to_user_pointer(addr), > > .op = DRM_XE_UFENCE_WAIT_OP_EQ, > > - .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP : 0, > > + .flags = 0, > > .value = value, > > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > .timeout = timeout, > > - .num_engines = eci ? 1 :0, > > - .instances = eci ? to_user_pointer(eci) : 0, > > + .exec_queue_id = exec_queue, > > }; > > > > igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, > &wait), > > 0); @@ -477,40 +475,6 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, > uint64_t value, > > return wait.timeout; > > } > > > > -/** > > - * xe_wait_ufence_abstime: > > - * @fd: xe device fd > > - * @addr: address of value to compare > > - * @value: expected value (equal) in @address > > - * @eci: engine class instance > > - * @timeout: absolute time when wait expire > > - * > > - * Function compares @value with memory pointed by @addr until they > are equal. > > - * > > - * Returns elapsed time in nanoseconds if user fence was signalled. > > - */ > > -int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, > > - struct drm_xe_engine_class_instance *eci, > > - int64_t timeout) > > -{ > > - struct drm_xe_wait_user_fence wait = { > > - .addr = to_user_pointer(addr), > > - .op = DRM_XE_UFENCE_WAIT_OP_EQ, > > - .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP | > DRM_XE_UFENCE_WAIT_FLAG_ABSTIME : 0, > > - .value = value, > > - .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > - .timeout = timeout, > > - .num_engines = eci ? 1 : 0, > > - .instances = eci ? to_user_pointer(eci) : 0, > > - }; > > - struct timespec ts; > > - > > - igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, > &wait), 0); > > - igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); > > - > > - return ts.tv_sec * 1e9 + ts.tv_nsec; > > -} > > Well, I believe it would be better this movement in a separated patch. ok > > > - > > void xe_force_gt_reset(int fd, int gt) { > > char reset_string[128]; > > diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h index > > 32b34b15a..186544a34 100644 > > --- a/lib/xe/xe_ioctl.h > > +++ b/lib/xe/xe_ioctl.h > > @@ -89,11 +89,9 @@ void xe_exec_sync(int fd, uint32_t exec_queue, > uint64_t addr, > > struct drm_xe_sync *sync, uint32_t num_syncs); void > > xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr); int64_t > > xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, > > - struct drm_xe_engine_class_instance *eci, > > - int64_t timeout); > > + uint32_t exec_queue,int64_t timeout); > > int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, > > - struct drm_xe_engine_class_instance *eci, > > - int64_t timeout); > > + uint32_t exec_queue, int64_t timeout); > > void xe_force_gt_reset(int fd, int gt); > > > > #endif /* XE_IOCTL_H */ > > diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c index > > 89dc46fae..12fbaf586 100644 > > --- a/tests/intel/xe_evict.c > > +++ b/tests/intel/xe_evict.c > > @@ -317,7 +317,7 @@ test_evict_cm(int fd, struct > drm_xe_engine_class_instance *eci, > > } > > #define TWENTY_SEC MS_TO_NS(20000) > > xe_wait_ufence(fd, &data[i].vm_sync, > USER_FENCE_VALUE, > > - NULL, TWENTY_SEC); > > + 0, TWENTY_SEC); > > } > > sync[0].addr = addr + (char *)&data[i].exec_sync - > > (char *)data; > > @@ -352,7 +352,7 @@ test_evict_cm(int fd, struct > drm_xe_engine_class_instance *eci, > > data = xe_bo_map(fd, __bo, > > ALIGN(sizeof(*data) * n_execs, 0x1000)); > > xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, > > - NULL, TWENTY_SEC); > > + exec_queues[i], TWENTY_SEC); > > igt_assert_eq(data[i].data, 0xc0ffee); > > } > > munmap(data, ALIGN(sizeof(*data) * n_execs, 0x1000)); diff --git > > a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c > > index 79ff65e89..0a02c6767 100644 > > --- a/tests/intel/xe_exec_balancer.c > > +++ b/tests/intel/xe_exec_balancer.c > > @@ -483,7 +483,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, > int n_execs, > > bo_size, sync, 1); > > > > #define ONE_SEC MS_TO_NS(1000) > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > ONE_SEC); > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > ONE_SEC); > > data[0].vm_sync = 0; > > > > for (i = 0; i < n_execs; i++) { > > @@ -514,7 +514,7 @@ test_cm(int fd, int gt, int class, int > > n_exec_queues, int n_execs, > > > > if (flags & REBIND && i + 1 != n_execs) { > > xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, > > - NULL, ONE_SEC); > > + exec_queues[e], ONE_SEC); > > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, > NULL, > > 0); > > > > @@ -529,7 +529,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, > int n_execs, > > addr, bo_size, sync, > > 1); > > xe_wait_ufence(fd, &data[0].vm_sync, > USER_FENCE_VALUE, > > - NULL, ONE_SEC); > > + 0, ONE_SEC); > > data[0].vm_sync = 0; > > } > > > > @@ -542,7 +542,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, > int n_execs, > > * an invalidate. > > */ > > xe_wait_ufence(fd, &data[i].exec_sync, > > - USER_FENCE_VALUE, NULL, > ONE_SEC); > > + USER_FENCE_VALUE, > exec_queues[e], ONE_SEC); > > igt_assert_eq(data[i].data, 0xc0ffee); > > } else if (i * 2 != n_execs) { > > /* > > @@ -571,7 +571,7 @@ test_cm(int fd, int gt, int class, int > > n_exec_queues, int n_execs, > > > > j = flags & INVALIDATE && n_execs ? n_execs - 1 : 0; > > for (i = j; i < n_execs; i++) > > - xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, NULL, > > + xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, > > +exec_queues[i], > > ONE_SEC); > > > > /* Wait for all execs to complete */ @@ -580,7 +580,7 @@ > test_cm(int > > fd, int gt, int class, int n_exec_queues, int n_execs, > > > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > ONE_SEC); > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > ONE_SEC); > > > > for (i = (flags & INVALIDATE && n_execs) ? n_execs - 1 : 0; > > i < n_execs; i++) > > diff --git a/tests/intel/xe_exec_compute_mode.c > > b/tests/intel/xe_exec_compute_mode.c > > index 7d3004d65..e8497a520 100644 > > --- a/tests/intel/xe_exec_compute_mode.c > > +++ b/tests/intel/xe_exec_compute_mode.c > > @@ -171,7 +171,7 @@ test_exec(int fd, struct > > drm_xe_engine_class_instance *eci, > > > > fence_timeout = igt_run_in_simulation() ? HUNDRED_SEC : > ONE_SEC; > > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > fence_timeout); > > data[0].vm_sync = 0; > > > > @@ -198,7 +198,7 @@ test_exec(int fd, struct > > drm_xe_engine_class_instance *eci, > > > > if (flags & REBIND && i + 1 != n_execs) { > > xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, > > - NULL, fence_timeout); > > + exec_queues[e], fence_timeout); > > xe_vm_unbind_async(fd, vm, bind_exec_queues[e], > 0, > > addr, bo_size, NULL, 0); > > > > @@ -214,7 +214,7 @@ test_exec(int fd, struct > drm_xe_engine_class_instance *eci, > > addr, bo_size, sync, > > 1); > > xe_wait_ufence(fd, &data[0].vm_sync, > USER_FENCE_VALUE, > > - NULL, fence_timeout); > > + 0, fence_timeout); > > data[0].vm_sync = 0; > > } > > > > @@ -227,7 +227,7 @@ test_exec(int fd, struct > drm_xe_engine_class_instance *eci, > > * an invalidate. > > */ > > xe_wait_ufence(fd, &data[i].exec_sync, > > - USER_FENCE_VALUE, NULL, > > + USER_FENCE_VALUE, > exec_queues[e], > > fence_timeout); > > igt_assert_eq(data[i].data, 0xc0ffee); > > } else if (i * 2 != n_execs) { > > @@ -257,7 +257,7 @@ test_exec(int fd, struct > > drm_xe_engine_class_instance *eci, > > > > j = flags & INVALIDATE ? n_execs - 1 : 0; > > for (i = j; i < n_execs; i++) > > - xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, NULL, > > + xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, > > +exec_queues[i], > > fence_timeout); > > > > /* Wait for all execs to complete */ @@ -267,7 +267,7 @@ > > test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > > xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, > bo_size, > > sync, 1); > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > fence_timeout); > > > > for (i = j; i < n_execs; i++) > > diff --git a/tests/intel/xe_exec_fault_mode.c > > b/tests/intel/xe_exec_fault_mode.c > > index ee7cbb604..27921f47a 100644 > > --- a/tests/intel/xe_exec_fault_mode.c > > +++ b/tests/intel/xe_exec_fault_mode.c > > @@ -195,14 +195,14 @@ test_exec(int fd, struct > drm_xe_engine_class_instance *eci, > > } > > > > #define ONE_SEC MS_TO_NS(1000) > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > ONE_SEC); > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > ONE_SEC); > > data[0].vm_sync = 0; > > > > if (flags & PREFETCH) { > > /* Should move to system memory */ > > xe_vm_prefetch_async(fd, vm, bind_exec_queues[0], 0, > addr, > > bo_size, sync, 1, 0); > > - xe_wait_ufence(fd, &data[0].vm_sync, > USER_FENCE_VALUE, NULL, > > + xe_wait_ufence(fd, &data[0].vm_sync, > USER_FENCE_VALUE, 0, > > ONE_SEC); > > data[0].vm_sync = 0; > > } > > @@ -230,7 +230,7 @@ test_exec(int fd, struct > > drm_xe_engine_class_instance *eci, > > > > if (flags & REBIND && i + 1 != n_execs) { > > xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, > > - NULL, ONE_SEC); > > + exec_queues[e], ONE_SEC); > > xe_vm_unbind_async(fd, vm, bind_exec_queues[e], > 0, > > addr, bo_size, NULL, 0); > > > > @@ -246,7 +246,7 @@ test_exec(int fd, struct > drm_xe_engine_class_instance *eci, > > addr, bo_size, sync, > > 1); > > xe_wait_ufence(fd, &data[0].vm_sync, > USER_FENCE_VALUE, > > - NULL, ONE_SEC); > > + 0, ONE_SEC); > > data[0].vm_sync = 0; > > } > > > > @@ -259,7 +259,7 @@ test_exec(int fd, struct > drm_xe_engine_class_instance *eci, > > * an invalidate. > > */ > > xe_wait_ufence(fd, &data[i].exec_sync, > > - USER_FENCE_VALUE, NULL, > ONE_SEC); > > + USER_FENCE_VALUE, > exec_queues[e], ONE_SEC); > > igt_assert_eq(data[i].data, 0xc0ffee); > > } else if (i * 2 != n_execs) { > > /* > > @@ -290,13 +290,13 @@ test_exec(int fd, struct > drm_xe_engine_class_instance *eci, > > j = flags & INVALIDATE ? n_execs - 1 : 0; > > for (i = j; i < n_execs; i++) > > xe_wait_ufence(fd, &data[i].exec_sync, > > - USER_FENCE_VALUE, NULL, ONE_SEC); > > + USER_FENCE_VALUE, exec_queues[i], > ONE_SEC); > > } > > > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > > xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, > bo_size, > > sync, 1); > > just to confirm... we don't need to get the bind_exec_queues there right?! Here I can use the bind_exec_queues for vm_bind instead of '0' below > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > ONE_SEC); > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > ONE_SEC); > > > > if (!(flags & INVALID_FAULT)) { > > for (i = j; i < n_execs; i++) > > diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c > > index edfd27fe0..e133706ee 100644 > > --- a/tests/intel/xe_exec_reset.c > > +++ b/tests/intel/xe_exec_reset.c > > @@ -564,7 +564,7 @@ test_compute_mode(int fd, struct > drm_xe_engine_class_instance *eci, > > xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); > > > > #define THREE_SEC MS_TO_NS(3000) > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > THREE_SEC); > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > +THREE_SEC); > > data[0].vm_sync = 0; > > > > for (i = 0; i < n_execs; i++) { > > @@ -618,11 +618,11 @@ test_compute_mode(int fd, struct > > drm_xe_engine_class_instance *eci, > > > > for (i = 1; i < n_execs; i++) > > xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, > > - NULL, THREE_SEC); > > + exec_queues[i], THREE_SEC); > > > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > THREE_SEC); > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > +THREE_SEC); > > why do you pick '0' here and 'exec_queue' in other places in this same code? For vm_bind we didn't have any exec_queue, because of this I used "0" > > > > > for (i = 1; i < n_execs; i++) > > igt_assert_eq(data[i].data, 0xc0ffee); diff --git > > a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c index > > fcb926698..f8450a844 100644 > > --- a/tests/intel/xe_exec_threads.c > > +++ b/tests/intel/xe_exec_threads.c > > @@ -331,7 +331,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t > > addr, uint64_t userptr, > > > > fence_timeout = igt_run_in_simulation() ? THIRTY_SEC : THREE_SEC; > > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > fence_timeout); > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > +fence_timeout); > > data[0].vm_sync = 0; > > > > for (i = 0; i < n_execs; i++) { > > @@ -359,7 +359,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t > addr, uint64_t userptr, > > for (j = i - 0x20; j <= i; ++j) > > xe_wait_ufence(fd, &data[j].exec_sync, > > USER_FENCE_VALUE, > > - NULL, fence_timeout); > > + exec_queues[e], fence_timeout); > > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, > > NULL, 0); > > > > @@ -374,7 +374,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t > addr, uint64_t userptr, > > addr, bo_size, sync, > > 1); > > xe_wait_ufence(fd, &data[0].vm_sync, > USER_FENCE_VALUE, > > - NULL, fence_timeout); > > + 0, fence_timeout); > > data[0].vm_sync = 0; > > } > > > > @@ -389,7 +389,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t > addr, uint64_t userptr, > > for (j = i == 0x20 ? 0 : i - 0x1f; j <= i; ++j) > > xe_wait_ufence(fd, > &data[j].exec_sync, > > USER_FENCE_VALUE, > > - NULL, fence_timeout); > > + exec_queues[e], > fence_timeout); > > igt_assert_eq(data[i].data, 0xc0ffee); > > } else if (i * 2 != n_execs) { > > /* > > @@ -421,7 +421,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t > addr, uint64_t userptr, > > j = flags & INVALIDATE ? > > (flags & RACE ? n_execs / 2 + 1 : n_execs - 1) : 0; > > for (i = j; i < n_execs; i++) > > - xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, NULL, > > + xe_wait_ufence(fd, &data[i].exec_sync, > USER_FENCE_VALUE, > > +exec_queues[i], > > fence_timeout); > > > > /* Wait for all execs to complete */ @@ -430,7 +430,7 @@ > > test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t > > userptr, > > > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > fence_timeout); > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > +fence_timeout); > > > > for (i = j; i < n_execs; i++) > > igt_assert_eq(data[i].data, 0xc0ffee); diff --git > > a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c index > > 3be987954..0bd7e5dce 100644 > > --- a/tests/intel/xe_waitfence.c > > +++ b/tests/intel/xe_waitfence.c > > @@ -37,22 +37,51 @@ static void do_bind(int fd, uint32_t vm, uint32_t > > bo, uint64_t offset, } > > > > static int64_t wait_with_eci_abstime(int fd, uint64_t *addr, uint64_t value, > > - struct drm_xe_engine_class_instance *eci, > > - int64_t timeout) > > + uint32_t exec_queue, int64_t timeout) > > { > > struct drm_xe_wait_user_fence wait = { > > .addr = to_user_pointer(addr), > > .op = DRM_XE_UFENCE_WAIT_OP_EQ, > > - .flags = !eci ? 0 : DRM_XE_UFENCE_WAIT_FLAG_ABSTIME, > > + .flags = !exec_queue ? 0 : > DRM_XE_UFENCE_WAIT_FLAG_ABSTIME, > > .value = value, > > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > .timeout = timeout, > > - .num_engines = eci ? 1 : 0, > > - .instances = eci ? to_user_pointer(eci) : 0, > > + .exec_queue_id = exec_queue, > > + }; > > + struct timespec ts; > > + > > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, > &wait), 0); > > + igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); > > + > > + return ts.tv_sec * 1e9 + ts.tv_nsec; } > > + > > +/** > > + * xe_wait_ufence_abstime: > > + * @fd: xe device fd > > + * @addr: address of value to compare > > + * @value: expected value (equal) in @address > > + * @exec_queue: exec_queue id > > + * @timeout: absolute time when wait expire > > + * > > + * Function compares @value with memory pointed by @addr until they > are equal. > > + * > > + * Returns elapsed time in nanoseconds if user fence was signalled. > > + */ > > +int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, > > + uint32_t exec_queue, int64_t timeout) { > > + struct drm_xe_wait_user_fence wait = { > > + .addr = to_user_pointer(addr), > > + .op = DRM_XE_UFENCE_WAIT_OP_EQ, > > + .flags = !exec_queue ? > DRM_XE_UFENCE_WAIT_FLAG_ABSTIME : 0, > > + .value = value, > > + .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > + .timeout = timeout, > > + .exec_queue_id = exec_queue, > > }; > > struct timespec ts; > > > > - igt_assert(eci); > > igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, > &wait), 0); > > igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); > > > > @@ -82,7 +111,6 @@ enum waittype { > > static void > > waitfence(int fd, enum waittype wt) > > { > > - struct drm_xe_engine *engine = NULL; > > struct timespec ts; > > int64_t current, signalled; > > uint32_t bo_1; > > @@ -111,15 +139,15 @@ waitfence(int fd, enum waittype wt) > > do_bind(fd, vm, bo_7, 0, 0xeffff0000, 0x10000, 7); > > > > if (wt == RELTIME) { > > - timeout = xe_wait_ufence(fd, &wait_fence, 7, NULL, > MS_TO_NS(10)); > > + timeout = xe_wait_ufence(fd, &wait_fence, 7, 0, > MS_TO_NS(10)); > > igt_debug("wait type: RELTIME - timeout: %ld, timeout left: > %ld\n", > > MS_TO_NS(10), timeout); > > } else if (wt == ENGINE) { > > - engine = xe_engine(fd, 1); > > + uint32_t exec_queue = xe_exec_queue_create_class(fd, > vm, > > +DRM_XE_ENGINE_CLASS_COPY); > > clock_gettime(CLOCK_MONOTONIC, &ts); > > current = ts.tv_sec * 1e9 + ts.tv_nsec; > > timeout = current + MS_TO_NS(10); > > - signalled = wait_with_eci_abstime(fd, &wait_fence, 7, > &engine->instance, timeout); > > + signalled = wait_with_eci_abstime(fd, &wait_fence, 7, > exec_queue, > > +timeout); > > igt_debug("wait type: ENGINE ABSTIME - timeout: %" PRId64 > > ", signalled: %" PRId64 > > ", elapsed: %" PRId64 "\n", > > @@ -128,7 +156,7 @@ waitfence(int fd, enum waittype wt) > > clock_gettime(CLOCK_MONOTONIC, &ts); > > current = ts.tv_sec * 1e9 + ts.tv_nsec; > > timeout = current + MS_TO_NS(10); > > - signalled = xe_wait_ufence_abstime(fd, &wait_fence, 7, > NULL, timeout); > > + signalled = xe_wait_ufence_abstime(fd, &wait_fence, 7, 0, > timeout); > > igt_debug("wait type: ABSTIME - timeout: %" PRId64 > > ", signalled: %" PRId64 > > ", elapsed: %" PRId64 "\n", > > @@ -149,9 +177,6 @@ waitfence(int fd, enum waittype wt) > > * > > * SUBTEST: invalid-ops > > * Description: Check query with invalid ops returns expected error > > code > > - * > > - * SUBTEST: invalid-engine > > - * Description: Check query with invalid engine info returns expected error > code > > */ > > > > static void > > @@ -166,8 +191,7 @@ invalid_flag(int fd) > > .value = 1, > > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > .timeout = -1, > > - .num_engines = 0, > > - .instances = 0, > > + .exec_queue_id = 0, > > }; > > > > uint32_t vm = xe_vm_create(fd, > DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, > > 0); @@ -191,8 +215,7 @@ invalid_ops(int fd) > > .value = 1, > > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > .timeout = 1, > > - .num_engines = 0, > > - .instances = 0, > > + .exec_queue_id = 0, > > }; > > > > uint32_t vm = xe_vm_create(fd, > DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, > > 0); @@ -204,32 +227,6 @@ invalid_ops(int fd) > > do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, > EINVAL); } > > > > -static void > > -invalid_engine(int fd) > > -{ > > - uint32_t bo; > > - > > - struct drm_xe_wait_user_fence wait = { > > - .addr = to_user_pointer(&wait_fence), > > - .op = DRM_XE_UFENCE_WAIT_OP_EQ, > > - .flags = 0, > > - .value = 1, > > - .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > - .timeout = -1, > > - .num_engines = 1, > > - .instances = 0, > > - }; > > - > > - uint32_t vm = xe_vm_create(fd, > DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); > > - > > - bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); > > - > > - do_bind(fd, vm, bo, 0, 0x200000, 0x40000, 1); > > - > > - do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, > EFAULT); > > -} > > - > > why are you removing this? > should be in a separate patch as well > I will keep this for now and remove later Krishna > > - > > igt_main > > { > > int fd; > > @@ -252,9 +249,6 @@ igt_main > > igt_subtest("invalid-ops") > > invalid_ops(fd); > > > > - igt_subtest("invalid-engine") > > - invalid_engine(fd); > > - > > igt_fixture > > drm_close_driver(fd); > > } > > -- > > 2.25.1 > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 1/2] drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure 2023-12-06 17:23 ` Bommu, Krishnaiah @ 2023-12-06 17:36 ` Rodrigo Vivi 0 siblings, 0 replies; 12+ messages in thread From: Rodrigo Vivi @ 2023-12-06 17:36 UTC (permalink / raw) To: Bommu, Krishnaiah; +Cc: igt-dev@lists.freedesktop.org On Wed, Dec 06, 2023 at 05:23:43PM +0000, Bommu, Krishnaiah wrote: > > > > -----Original Message----- > > From: Vivi, Rodrigo <rodrigo.vivi@intel.com> > > Sent: Wednesday, December 6, 2023 10:34 PM > > To: Bommu, Krishnaiah <krishnaiah.bommu@intel.com> > > Cc: igt-dev@lists.freedesktop.org > > Subject: Re: [igt-dev] [PATCH v4 1/2] drm-uapi/xe: add exec_queue_id > > member to drm_xe_wait_user_fence structure > > > > On Wed, Dec 06, 2023 at 08:14:50PM +0530, Bommu Krishnaiah wrote: > > > remove the num_engines/instances members from > > drm_xe_wait_user_fence > > > structure and add a exec_queue_id member > > > > > > Right now this is only checking if the engine list is sane and nothing > > > else. In the end every operation with this IOCTL is a soft check. > > > So, let's formalize that and only use this IOCTL to wait on the fence. > > > > > > exec_queue_id member will help to user space to get proper error code > > > from kernel while in exec_queue reset > > > > > > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Cc: Francois Dugast <francois.dugast@intel.com> > > > --- > > > include/drm-uapi/xe_drm.h | 16 ++---- > > > > Since you are touching the header file it would be good if you could add a > > mention to the commit message of which kernel patch you were when you > > aligned this header. > > > > Something like xe_drm.h aligns with kernel commit ("drm/xe/uapi: Return > > correct error code for xe_wait_user_fence_ioctl") > > > > (no need to add the commit hash since it is still volatile in drm-xe-next) > > > > Also ensure that you do not copy the header directly, but always make it > > from the kernel and then copy the 'built' one. > > > > make headers_install INSTALL_HDR_PATH=/tmp/blah cp > > /tmp/blah/include/drm/xe_drm.h ./include/drm-uapi/xe_drm.h > > I will update in next version > > > > > > > > lib/xe/xe_ioctl.c | 42 +------------- > > > lib/xe/xe_ioctl.h | 6 +- > > > tests/intel/xe_evict.c | 4 +- > > > tests/intel/xe_exec_balancer.c | 12 ++-- > > > tests/intel/xe_exec_compute_mode.c | 12 ++-- > > > tests/intel/xe_exec_fault_mode.c | 14 ++--- > > > tests/intel/xe_exec_reset.c | 6 +- > > > tests/intel/xe_exec_threads.c | 12 ++-- > > > tests/intel/xe_waitfence.c | 88 ++++++++++++++---------------- > > > 10 files changed, 82 insertions(+), 130 deletions(-) > > > > > > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h > > > index 590f7b7af..ceaca3991 100644 > > > --- a/include/drm-uapi/xe_drm.h > > > +++ b/include/drm-uapi/xe_drm.h > > > @@ -1024,8 +1024,7 @@ struct drm_xe_wait_user_fence { > > > /** @op: wait operation (type of comparison) */ > > > __u16 op; > > > > > > -#define DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP (1 << 0) /* e.g. Wait > > on VM bind */ > > > -#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 1) > > > +#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) > > > /** @flags: wait flags */ > > > __u16 flags; > > > > > > @@ -1059,16 +1058,13 @@ struct drm_xe_wait_user_fence { > > > __s64 timeout; > > > > > > /** > > > - * @num_engines: number of engine instances to wait on, must be > > zero > > > - * when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set > > > + * @exec_queue_id: exec_queue_id returned from > > xe_exec_queue_create_ioctl > > > + * exec_queue_id is help to find exec_queue reset status > > > */ > > > - __u64 num_engines; > > > + __u32 exec_queue_id; > > > > > > - /** > > > - * @instances: user pointer to array of > > drm_xe_engine_class_instance to > > > - * wait on, must be NULL when > > DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set > > > - */ > > > - __u64 instances; > > > + /** @reserved: Reserved */ > > > > please fix the alignments and pad doc as Francois already pointed out and > > then when that is finalized, import the result here as mentioned above. > > I will update in next version > > > > > > + __u32 pad2; > > > > > > /** @reserved: Reserved */ > > > __u64 reserved[2]; > > > diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c index > > > c91bf25c4..87e2db5b4 100644 > > > --- a/lib/xe/xe_ioctl.c > > > +++ b/lib/xe/xe_ioctl.c > > > @@ -458,18 +458,16 @@ void xe_exec_wait(int fd, uint32_t exec_queue, > > > uint64_t addr) } > > > > > > int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, > > > - struct drm_xe_engine_class_instance *eci, > > > - int64_t timeout) > > > + uint32_t exec_queue, int64_t timeout) > > > { > > > struct drm_xe_wait_user_fence wait = { > > > .addr = to_user_pointer(addr), > > > .op = DRM_XE_UFENCE_WAIT_OP_EQ, > > > - .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP : 0, > > > + .flags = 0, > > > .value = value, > > > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > > .timeout = timeout, > > > - .num_engines = eci ? 1 :0, > > > - .instances = eci ? to_user_pointer(eci) : 0, > > > + .exec_queue_id = exec_queue, > > > }; > > > > > > igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, > > &wait), > > > 0); @@ -477,40 +475,6 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, > > uint64_t value, > > > return wait.timeout; > > > } > > > > > > -/** > > > - * xe_wait_ufence_abstime: > > > - * @fd: xe device fd > > > - * @addr: address of value to compare > > > - * @value: expected value (equal) in @address > > > - * @eci: engine class instance > > > - * @timeout: absolute time when wait expire > > > - * > > > - * Function compares @value with memory pointed by @addr until they > > are equal. > > > - * > > > - * Returns elapsed time in nanoseconds if user fence was signalled. > > > - */ > > > -int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, > > > - struct drm_xe_engine_class_instance *eci, > > > - int64_t timeout) > > > -{ > > > - struct drm_xe_wait_user_fence wait = { > > > - .addr = to_user_pointer(addr), > > > - .op = DRM_XE_UFENCE_WAIT_OP_EQ, > > > - .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP | > > DRM_XE_UFENCE_WAIT_FLAG_ABSTIME : 0, > > > - .value = value, > > > - .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > > - .timeout = timeout, > > > - .num_engines = eci ? 1 : 0, > > > - .instances = eci ? to_user_pointer(eci) : 0, > > > - }; > > > - struct timespec ts; > > > - > > > - igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, > > &wait), 0); > > > - igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); > > > - > > > - return ts.tv_sec * 1e9 + ts.tv_nsec; > > > -} > > > > Well, I believe it would be better this movement in a separated patch. > ok > > > > > - > > > void xe_force_gt_reset(int fd, int gt) { > > > char reset_string[128]; > > > diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h index > > > 32b34b15a..186544a34 100644 > > > --- a/lib/xe/xe_ioctl.h > > > +++ b/lib/xe/xe_ioctl.h > > > @@ -89,11 +89,9 @@ void xe_exec_sync(int fd, uint32_t exec_queue, > > uint64_t addr, > > > struct drm_xe_sync *sync, uint32_t num_syncs); void > > > xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr); int64_t > > > xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, > > > - struct drm_xe_engine_class_instance *eci, > > > - int64_t timeout); > > > + uint32_t exec_queue,int64_t timeout); > > > int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, > > > - struct drm_xe_engine_class_instance *eci, > > > - int64_t timeout); > > > + uint32_t exec_queue, int64_t timeout); > > > void xe_force_gt_reset(int fd, int gt); > > > > > > #endif /* XE_IOCTL_H */ > > > diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c index > > > 89dc46fae..12fbaf586 100644 > > > --- a/tests/intel/xe_evict.c > > > +++ b/tests/intel/xe_evict.c > > > @@ -317,7 +317,7 @@ test_evict_cm(int fd, struct > > drm_xe_engine_class_instance *eci, > > > } > > > #define TWENTY_SEC MS_TO_NS(20000) > > > xe_wait_ufence(fd, &data[i].vm_sync, > > USER_FENCE_VALUE, > > > - NULL, TWENTY_SEC); > > > + 0, TWENTY_SEC); > > > } > > > sync[0].addr = addr + (char *)&data[i].exec_sync - > > > (char *)data; > > > @@ -352,7 +352,7 @@ test_evict_cm(int fd, struct > > drm_xe_engine_class_instance *eci, > > > data = xe_bo_map(fd, __bo, > > > ALIGN(sizeof(*data) * n_execs, 0x1000)); > > > xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, > > > - NULL, TWENTY_SEC); > > > + exec_queues[i], TWENTY_SEC); > > > igt_assert_eq(data[i].data, 0xc0ffee); > > > } > > > munmap(data, ALIGN(sizeof(*data) * n_execs, 0x1000)); diff --git > > > a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c > > > index 79ff65e89..0a02c6767 100644 > > > --- a/tests/intel/xe_exec_balancer.c > > > +++ b/tests/intel/xe_exec_balancer.c > > > @@ -483,7 +483,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, > > int n_execs, > > > bo_size, sync, 1); > > > > > > #define ONE_SEC MS_TO_NS(1000) > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > ONE_SEC); > > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > ONE_SEC); > > > data[0].vm_sync = 0; > > > > > > for (i = 0; i < n_execs; i++) { > > > @@ -514,7 +514,7 @@ test_cm(int fd, int gt, int class, int > > > n_exec_queues, int n_execs, > > > > > > if (flags & REBIND && i + 1 != n_execs) { > > > xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, > > > - NULL, ONE_SEC); > > > + exec_queues[e], ONE_SEC); > > > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, > > NULL, > > > 0); > > > > > > @@ -529,7 +529,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, > > int n_execs, > > > addr, bo_size, sync, > > > 1); > > > xe_wait_ufence(fd, &data[0].vm_sync, > > USER_FENCE_VALUE, > > > - NULL, ONE_SEC); > > > + 0, ONE_SEC); > > > data[0].vm_sync = 0; > > > } > > > > > > @@ -542,7 +542,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, > > int n_execs, > > > * an invalidate. > > > */ > > > xe_wait_ufence(fd, &data[i].exec_sync, > > > - USER_FENCE_VALUE, NULL, > > ONE_SEC); > > > + USER_FENCE_VALUE, > > exec_queues[e], ONE_SEC); > > > igt_assert_eq(data[i].data, 0xc0ffee); > > > } else if (i * 2 != n_execs) { > > > /* > > > @@ -571,7 +571,7 @@ test_cm(int fd, int gt, int class, int > > > n_exec_queues, int n_execs, > > > > > > j = flags & INVALIDATE && n_execs ? n_execs - 1 : 0; > > > for (i = j; i < n_execs; i++) > > > - xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, NULL, > > > + xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, > > > +exec_queues[i], > > > ONE_SEC); > > > > > > /* Wait for all execs to complete */ @@ -580,7 +580,7 @@ > > test_cm(int > > > fd, int gt, int class, int n_exec_queues, int n_execs, > > > > > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > > > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > ONE_SEC); > > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > ONE_SEC); > > > > > > for (i = (flags & INVALIDATE && n_execs) ? n_execs - 1 : 0; > > > i < n_execs; i++) > > > diff --git a/tests/intel/xe_exec_compute_mode.c > > > b/tests/intel/xe_exec_compute_mode.c > > > index 7d3004d65..e8497a520 100644 > > > --- a/tests/intel/xe_exec_compute_mode.c > > > +++ b/tests/intel/xe_exec_compute_mode.c > > > @@ -171,7 +171,7 @@ test_exec(int fd, struct > > > drm_xe_engine_class_instance *eci, > > > > > > fence_timeout = igt_run_in_simulation() ? HUNDRED_SEC : > > ONE_SEC; > > > > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > > fence_timeout); > > > data[0].vm_sync = 0; > > > > > > @@ -198,7 +198,7 @@ test_exec(int fd, struct > > > drm_xe_engine_class_instance *eci, > > > > > > if (flags & REBIND && i + 1 != n_execs) { > > > xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, > > > - NULL, fence_timeout); > > > + exec_queues[e], fence_timeout); > > > xe_vm_unbind_async(fd, vm, bind_exec_queues[e], > > 0, > > > addr, bo_size, NULL, 0); > > > > > > @@ -214,7 +214,7 @@ test_exec(int fd, struct > > drm_xe_engine_class_instance *eci, > > > addr, bo_size, sync, > > > 1); > > > xe_wait_ufence(fd, &data[0].vm_sync, > > USER_FENCE_VALUE, > > > - NULL, fence_timeout); > > > + 0, fence_timeout); > > > data[0].vm_sync = 0; > > > } > > > > > > @@ -227,7 +227,7 @@ test_exec(int fd, struct > > drm_xe_engine_class_instance *eci, > > > * an invalidate. > > > */ > > > xe_wait_ufence(fd, &data[i].exec_sync, > > > - USER_FENCE_VALUE, NULL, > > > + USER_FENCE_VALUE, > > exec_queues[e], > > > fence_timeout); > > > igt_assert_eq(data[i].data, 0xc0ffee); > > > } else if (i * 2 != n_execs) { > > > @@ -257,7 +257,7 @@ test_exec(int fd, struct > > > drm_xe_engine_class_instance *eci, > > > > > > j = flags & INVALIDATE ? n_execs - 1 : 0; > > > for (i = j; i < n_execs; i++) > > > - xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, NULL, > > > + xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, > > > +exec_queues[i], > > > fence_timeout); > > > > > > /* Wait for all execs to complete */ @@ -267,7 +267,7 @@ > > > test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > > > xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, > > bo_size, > > > sync, 1); > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > > fence_timeout); > > > > > > for (i = j; i < n_execs; i++) > > > diff --git a/tests/intel/xe_exec_fault_mode.c > > > b/tests/intel/xe_exec_fault_mode.c > > > index ee7cbb604..27921f47a 100644 > > > --- a/tests/intel/xe_exec_fault_mode.c > > > +++ b/tests/intel/xe_exec_fault_mode.c > > > @@ -195,14 +195,14 @@ test_exec(int fd, struct > > drm_xe_engine_class_instance *eci, > > > } > > > > > > #define ONE_SEC MS_TO_NS(1000) > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > ONE_SEC); > > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > ONE_SEC); > > > data[0].vm_sync = 0; > > > > > > if (flags & PREFETCH) { > > > /* Should move to system memory */ > > > xe_vm_prefetch_async(fd, vm, bind_exec_queues[0], 0, > > addr, > > > bo_size, sync, 1, 0); > > > - xe_wait_ufence(fd, &data[0].vm_sync, > > USER_FENCE_VALUE, NULL, > > > + xe_wait_ufence(fd, &data[0].vm_sync, > > USER_FENCE_VALUE, 0, > > > ONE_SEC); > > > data[0].vm_sync = 0; > > > } > > > @@ -230,7 +230,7 @@ test_exec(int fd, struct > > > drm_xe_engine_class_instance *eci, > > > > > > if (flags & REBIND && i + 1 != n_execs) { > > > xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, > > > - NULL, ONE_SEC); > > > + exec_queues[e], ONE_SEC); > > > xe_vm_unbind_async(fd, vm, bind_exec_queues[e], > > 0, > > > addr, bo_size, NULL, 0); > > > > > > @@ -246,7 +246,7 @@ test_exec(int fd, struct > > drm_xe_engine_class_instance *eci, > > > addr, bo_size, sync, > > > 1); > > > xe_wait_ufence(fd, &data[0].vm_sync, > > USER_FENCE_VALUE, > > > - NULL, ONE_SEC); > > > + 0, ONE_SEC); > > > data[0].vm_sync = 0; > > > } > > > > > > @@ -259,7 +259,7 @@ test_exec(int fd, struct > > drm_xe_engine_class_instance *eci, > > > * an invalidate. > > > */ > > > xe_wait_ufence(fd, &data[i].exec_sync, > > > - USER_FENCE_VALUE, NULL, > > ONE_SEC); > > > + USER_FENCE_VALUE, > > exec_queues[e], ONE_SEC); > > > igt_assert_eq(data[i].data, 0xc0ffee); > > > } else if (i * 2 != n_execs) { > > > /* > > > @@ -290,13 +290,13 @@ test_exec(int fd, struct > > drm_xe_engine_class_instance *eci, > > > j = flags & INVALIDATE ? n_execs - 1 : 0; > > > for (i = j; i < n_execs; i++) > > > xe_wait_ufence(fd, &data[i].exec_sync, > > > - USER_FENCE_VALUE, NULL, ONE_SEC); > > > + USER_FENCE_VALUE, exec_queues[i], > > ONE_SEC); > > > } > > > > > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > > > xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, > > bo_size, > > > sync, 1); > > > > just to confirm... we don't need to get the bind_exec_queues there right?! > Here I can use the bind_exec_queues for vm_bind instead of '0' below > > > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > ONE_SEC); > > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > ONE_SEC); > > > > > > if (!(flags & INVALID_FAULT)) { > > > for (i = j; i < n_execs; i++) > > > diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c > > > index edfd27fe0..e133706ee 100644 > > > --- a/tests/intel/xe_exec_reset.c > > > +++ b/tests/intel/xe_exec_reset.c > > > @@ -564,7 +564,7 @@ test_compute_mode(int fd, struct > > drm_xe_engine_class_instance *eci, > > > xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); > > > > > > #define THREE_SEC MS_TO_NS(3000) > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > THREE_SEC); > > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > > +THREE_SEC); > > > data[0].vm_sync = 0; > > > > > > for (i = 0; i < n_execs; i++) { > > > @@ -618,11 +618,11 @@ test_compute_mode(int fd, struct > > > drm_xe_engine_class_instance *eci, > > > > > > for (i = 1; i < n_execs; i++) > > > xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, > > > - NULL, THREE_SEC); > > > + exec_queues[i], THREE_SEC); > > > > > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > > > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > THREE_SEC); > > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > > +THREE_SEC); > > > > why do you pick '0' here and 'exec_queue' in other places in this same code? > For vm_bind we didn't have any exec_queue, because of this I used "0" But isn't 0 a valid exec_queue_id number? > > > > > > > > for (i = 1; i < n_execs; i++) > > > igt_assert_eq(data[i].data, 0xc0ffee); diff --git > > > a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c index > > > fcb926698..f8450a844 100644 > > > --- a/tests/intel/xe_exec_threads.c > > > +++ b/tests/intel/xe_exec_threads.c > > > @@ -331,7 +331,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t > > > addr, uint64_t userptr, > > > > > > fence_timeout = igt_run_in_simulation() ? THIRTY_SEC : THREE_SEC; > > > > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > fence_timeout); > > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > > +fence_timeout); > > > data[0].vm_sync = 0; > > > > > > for (i = 0; i < n_execs; i++) { > > > @@ -359,7 +359,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t > > addr, uint64_t userptr, > > > for (j = i - 0x20; j <= i; ++j) > > > xe_wait_ufence(fd, &data[j].exec_sync, > > > USER_FENCE_VALUE, > > > - NULL, fence_timeout); > > > + exec_queues[e], fence_timeout); > > > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, > > > NULL, 0); > > > > > > @@ -374,7 +374,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t > > addr, uint64_t userptr, > > > addr, bo_size, sync, > > > 1); > > > xe_wait_ufence(fd, &data[0].vm_sync, > > USER_FENCE_VALUE, > > > - NULL, fence_timeout); > > > + 0, fence_timeout); > > > data[0].vm_sync = 0; > > > } > > > > > > @@ -389,7 +389,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t > > addr, uint64_t userptr, > > > for (j = i == 0x20 ? 0 : i - 0x1f; j <= i; ++j) > > > xe_wait_ufence(fd, > > &data[j].exec_sync, > > > USER_FENCE_VALUE, > > > - NULL, fence_timeout); > > > + exec_queues[e], > > fence_timeout); > > > igt_assert_eq(data[i].data, 0xc0ffee); > > > } else if (i * 2 != n_execs) { > > > /* > > > @@ -421,7 +421,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t > > addr, uint64_t userptr, > > > j = flags & INVALIDATE ? > > > (flags & RACE ? n_execs / 2 + 1 : n_execs - 1) : 0; > > > for (i = j; i < n_execs; i++) > > > - xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, NULL, > > > + xe_wait_ufence(fd, &data[i].exec_sync, > > USER_FENCE_VALUE, > > > +exec_queues[i], > > > fence_timeout); > > > > > > /* Wait for all execs to complete */ @@ -430,7 +430,7 @@ > > > test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t > > > userptr, > > > > > > sync[0].addr = to_user_pointer(&data[0].vm_sync); > > > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > > > - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, > > fence_timeout); > > > + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, > > > +fence_timeout); > > > > > > for (i = j; i < n_execs; i++) > > > igt_assert_eq(data[i].data, 0xc0ffee); diff --git > > > a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c index > > > 3be987954..0bd7e5dce 100644 > > > --- a/tests/intel/xe_waitfence.c > > > +++ b/tests/intel/xe_waitfence.c > > > @@ -37,22 +37,51 @@ static void do_bind(int fd, uint32_t vm, uint32_t > > > bo, uint64_t offset, } > > > > > > static int64_t wait_with_eci_abstime(int fd, uint64_t *addr, uint64_t value, > > > - struct drm_xe_engine_class_instance *eci, > > > - int64_t timeout) > > > + uint32_t exec_queue, int64_t timeout) > > > { > > > struct drm_xe_wait_user_fence wait = { > > > .addr = to_user_pointer(addr), > > > .op = DRM_XE_UFENCE_WAIT_OP_EQ, > > > - .flags = !eci ? 0 : DRM_XE_UFENCE_WAIT_FLAG_ABSTIME, > > > + .flags = !exec_queue ? 0 : > > DRM_XE_UFENCE_WAIT_FLAG_ABSTIME, > > > .value = value, > > > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > > .timeout = timeout, > > > - .num_engines = eci ? 1 : 0, > > > - .instances = eci ? to_user_pointer(eci) : 0, > > > + .exec_queue_id = exec_queue, > > > + }; > > > + struct timespec ts; > > > + > > > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, > > &wait), 0); > > > + igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); > > > + > > > + return ts.tv_sec * 1e9 + ts.tv_nsec; } > > > + > > > +/** > > > + * xe_wait_ufence_abstime: > > > + * @fd: xe device fd > > > + * @addr: address of value to compare > > > + * @value: expected value (equal) in @address > > > + * @exec_queue: exec_queue id > > > + * @timeout: absolute time when wait expire > > > + * > > > + * Function compares @value with memory pointed by @addr until they > > are equal. > > > + * > > > + * Returns elapsed time in nanoseconds if user fence was signalled. > > > + */ > > > +int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, > > > + uint32_t exec_queue, int64_t timeout) { > > > + struct drm_xe_wait_user_fence wait = { > > > + .addr = to_user_pointer(addr), > > > + .op = DRM_XE_UFENCE_WAIT_OP_EQ, > > > + .flags = !exec_queue ? > > DRM_XE_UFENCE_WAIT_FLAG_ABSTIME : 0, > > > + .value = value, > > > + .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > > + .timeout = timeout, > > > + .exec_queue_id = exec_queue, > > > }; > > > struct timespec ts; > > > > > > - igt_assert(eci); > > > igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, > > &wait), 0); > > > igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); > > > > > > @@ -82,7 +111,6 @@ enum waittype { > > > static void > > > waitfence(int fd, enum waittype wt) > > > { > > > - struct drm_xe_engine *engine = NULL; > > > struct timespec ts; > > > int64_t current, signalled; > > > uint32_t bo_1; > > > @@ -111,15 +139,15 @@ waitfence(int fd, enum waittype wt) > > > do_bind(fd, vm, bo_7, 0, 0xeffff0000, 0x10000, 7); > > > > > > if (wt == RELTIME) { > > > - timeout = xe_wait_ufence(fd, &wait_fence, 7, NULL, > > MS_TO_NS(10)); > > > + timeout = xe_wait_ufence(fd, &wait_fence, 7, 0, > > MS_TO_NS(10)); > > > igt_debug("wait type: RELTIME - timeout: %ld, timeout left: > > %ld\n", > > > MS_TO_NS(10), timeout); > > > } else if (wt == ENGINE) { > > > - engine = xe_engine(fd, 1); > > > + uint32_t exec_queue = xe_exec_queue_create_class(fd, > > vm, > > > +DRM_XE_ENGINE_CLASS_COPY); > > > clock_gettime(CLOCK_MONOTONIC, &ts); > > > current = ts.tv_sec * 1e9 + ts.tv_nsec; > > > timeout = current + MS_TO_NS(10); > > > - signalled = wait_with_eci_abstime(fd, &wait_fence, 7, > > &engine->instance, timeout); > > > + signalled = wait_with_eci_abstime(fd, &wait_fence, 7, > > exec_queue, > > > +timeout); > > > igt_debug("wait type: ENGINE ABSTIME - timeout: %" PRId64 > > > ", signalled: %" PRId64 > > > ", elapsed: %" PRId64 "\n", > > > @@ -128,7 +156,7 @@ waitfence(int fd, enum waittype wt) > > > clock_gettime(CLOCK_MONOTONIC, &ts); > > > current = ts.tv_sec * 1e9 + ts.tv_nsec; > > > timeout = current + MS_TO_NS(10); > > > - signalled = xe_wait_ufence_abstime(fd, &wait_fence, 7, > > NULL, timeout); > > > + signalled = xe_wait_ufence_abstime(fd, &wait_fence, 7, 0, > > timeout); > > > igt_debug("wait type: ABSTIME - timeout: %" PRId64 > > > ", signalled: %" PRId64 > > > ", elapsed: %" PRId64 "\n", > > > @@ -149,9 +177,6 @@ waitfence(int fd, enum waittype wt) > > > * > > > * SUBTEST: invalid-ops > > > * Description: Check query with invalid ops returns expected error > > > code > > > - * > > > - * SUBTEST: invalid-engine > > > - * Description: Check query with invalid engine info returns expected error > > code > > > */ > > > > > > static void > > > @@ -166,8 +191,7 @@ invalid_flag(int fd) > > > .value = 1, > > > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > > .timeout = -1, > > > - .num_engines = 0, > > > - .instances = 0, > > > + .exec_queue_id = 0, > > > }; > > > > > > uint32_t vm = xe_vm_create(fd, > > DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, > > > 0); @@ -191,8 +215,7 @@ invalid_ops(int fd) > > > .value = 1, > > > .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > > .timeout = 1, > > > - .num_engines = 0, > > > - .instances = 0, > > > + .exec_queue_id = 0, > > > }; > > > > > > uint32_t vm = xe_vm_create(fd, > > DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, > > > 0); @@ -204,32 +227,6 @@ invalid_ops(int fd) > > > do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, > > EINVAL); } > > > > > > -static void > > > -invalid_engine(int fd) > > > -{ > > > - uint32_t bo; > > > - > > > - struct drm_xe_wait_user_fence wait = { > > > - .addr = to_user_pointer(&wait_fence), > > > - .op = DRM_XE_UFENCE_WAIT_OP_EQ, > > > - .flags = 0, > > > - .value = 1, > > > - .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > > > - .timeout = -1, > > > - .num_engines = 1, > > > - .instances = 0, > > > - }; > > > - > > > - uint32_t vm = xe_vm_create(fd, > > DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); > > > - > > > - bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); > > > - > > > - do_bind(fd, vm, bo, 0, 0x200000, 0x40000, 1); > > > - > > > - do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, > > EFAULT); > > > -} > > > - > > > > why are you removing this? > > should be in a separate patch as well > > > I will keep this for now and remove later > Krishna > > > - > > > igt_main > > > { > > > int fd; > > > @@ -252,9 +249,6 @@ igt_main > > > igt_subtest("invalid-ops") > > > invalid_ops(fd); > > > > > > - igt_subtest("invalid-engine") > > > - invalid_engine(fd); > > > - > > > igt_fixture > > > drm_close_driver(fd); > > > } > > > -- > > > 2.25.1 > > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] [PATCH v4 1/1] drm-uapi/xe: kill xe_wait_user_fence_ioctl when exec_queue reset happen 2023-12-06 14:44 [igt-dev] [PATCH v4 0/2] RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure Bommu Krishnaiah 2023-12-06 14:44 ` [igt-dev] [PATCH v4 1/2] " Bommu Krishnaiah @ 2023-12-06 14:44 ` Bommu Krishnaiah 2023-12-06 17:06 ` Rodrigo Vivi 2023-12-06 14:44 ` [igt-dev] [PATCH v4 2/2] " Bommu Krishnaiah ` (3 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Bommu Krishnaiah @ 2023-12-06 14:44 UTC (permalink / raw) To: igt-dev; +Cc: Bommu Krishnaiah, Rodrigo Vivi Skipping the GPU mapping(vm_bind) for object, so that exec_queue reset will happen and xe_wait_ufence will end return EIO not ETIME Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Francois Dugast <francois.dugast@intel.com> --- tests/intel/xe_waitfence.c | 83 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c index 0bd7e5dce..b5bf0d5b6 100644 --- a/tests/intel/xe_waitfence.c +++ b/tests/intel/xe_waitfence.c @@ -177,6 +177,9 @@ waitfence(int fd, enum waittype wt) * * SUBTEST: invalid-ops * Description: Check query with invalid ops returns expected error code + * + * SUBTEST: invalid-exec_queue-wait + * Description: Check xe_wait_ufence will return expected error code while exec_queue reset happen */ static void @@ -227,6 +230,83 @@ invalid_ops(int fd) do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EINVAL); } +static void +invalid_exec_queue_wait(int fd) +{ + uint32_t bo, b; + uint64_t batch_offset; + uint64_t batch_addr; + uint64_t sdi_offset; + uint64_t sdi_addr; + uint64_t addr = 0x1a0000; + + struct { + uint32_t batch[16]; + uint64_t pad; + uint64_t vm_sync; + uint64_t exec_sync; + uint32_t data; + } *data; + +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull + struct drm_xe_sync sync[1] = { + { .flags = DRM_XE_SYNC_TYPE_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL, + .timeline_value = USER_FENCE_VALUE }, + }; + + struct drm_xe_exec exec = { + .num_batch_buffer = 1, + .num_syncs = 1, + .syncs = to_user_pointer(sync), + }; + + uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + uint32_t exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); + struct drm_xe_wait_user_fence wait = { + .op = DRM_XE_UFENCE_WAIT_OP_EQ, + .flags = 0, + .value = 0xc0ffee, + .mask = DRM_XE_UFENCE_WAIT_MASK_U64, + .timeout = -1, + .exec_queue_id = exec_queue, + }; + + bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); + data = xe_bo_map(fd, bo, 0x40000); + + batch_offset = (char *)&data[0].batch - (char *)data; + batch_addr = addr + batch_offset; + sdi_offset = (char *)&data[0].data - (char *)data; + sdi_addr = addr + sdi_offset; + + b = 0; + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4; + data[0].batch[b++] = sdi_addr; + data[0].batch[b++] = sdi_addr >> 32; + data[0].batch[b++] = 0xc0ffee; + data[0].batch[b++] = MI_BATCH_BUFFER_END; + igt_assert(b <= ARRAY_SIZE(data[0].batch)); + + wait.addr = to_user_pointer(&data[0].exec_sync); + exec.exec_queue_id = exec_queue; + exec.address = batch_addr; + + xe_exec(fd, &exec); + + /** + * Skipping the GPU mapping(vm_bind) for object, so that exec_queue + * reset will happen and xe_wait_ufence will end return EIO not ETIME + */ + do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EIO); + + xe_exec_queue_destroy(fd, exec_queue); + + if (bo) { + munmap(data, 0x40000); + gem_close(fd, bo); + } +} + igt_main { int fd; @@ -249,6 +329,9 @@ igt_main igt_subtest("invalid-ops") invalid_ops(fd); + igt_subtest("invalid-exec_queue-wait") + invalid_exec_queue_wait(fd); + igt_fixture drm_close_driver(fd); } -- 2.25.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 1/1] drm-uapi/xe: kill xe_wait_user_fence_ioctl when exec_queue reset happen 2023-12-06 14:44 ` [igt-dev] [PATCH v4 1/1] drm-uapi/xe: kill xe_wait_user_fence_ioctl when exec_queue reset happen Bommu Krishnaiah @ 2023-12-06 17:06 ` Rodrigo Vivi 0 siblings, 0 replies; 12+ messages in thread From: Rodrigo Vivi @ 2023-12-06 17:06 UTC (permalink / raw) To: Bommu Krishnaiah; +Cc: igt-dev On Wed, Dec 06, 2023 at 08:14:51PM +0530, Bommu Krishnaiah wrote: > Skipping the GPU mapping(vm_bind) for object, so that exec_queue > reset will happen and xe_wait_ufence will end return EIO not ETIME > > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Francois Dugast <francois.dugast@intel.com> > --- > tests/intel/xe_waitfence.c | 83 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 83 insertions(+) > > diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c > index 0bd7e5dce..b5bf0d5b6 100644 > --- a/tests/intel/xe_waitfence.c > +++ b/tests/intel/xe_waitfence.c > @@ -177,6 +177,9 @@ waitfence(int fd, enum waittype wt) > * > * SUBTEST: invalid-ops > * Description: Check query with invalid ops returns expected error code > + * > + * SUBTEST: invalid-exec_queue-wait > + * Description: Check xe_wait_ufence will return expected error code while exec_queue reset happen > */ > > static void > @@ -227,6 +230,83 @@ invalid_ops(int fd) > do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EINVAL); > } > > +static void > +invalid_exec_queue_wait(int fd) > +{ > + uint32_t bo, b; > + uint64_t batch_offset; > + uint64_t batch_addr; > + uint64_t sdi_offset; > + uint64_t sdi_addr; > + uint64_t addr = 0x1a0000; > + > + struct { > + uint32_t batch[16]; > + uint64_t pad; > + uint64_t vm_sync; > + uint64_t exec_sync; > + uint32_t data; > + } *data; > + > +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull > + struct drm_xe_sync sync[1] = { > + { .flags = DRM_XE_SYNC_TYPE_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL, > + .timeline_value = USER_FENCE_VALUE }, > + }; > + > + struct drm_xe_exec exec = { > + .num_batch_buffer = 1, > + .num_syncs = 1, > + .syncs = to_user_pointer(sync), > + }; > + > + uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); > + uint32_t exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); > + struct drm_xe_wait_user_fence wait = { > + .op = DRM_XE_UFENCE_WAIT_OP_EQ, > + .flags = 0, > + .value = 0xc0ffee, > + .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > + .timeout = -1, > + .exec_queue_id = exec_queue, this doesn't exist without the patch 2, so this shouldn't be the first patch in the series. Also, the patch is not doing what the subject tells, so I'm really confused here. > + }; > + > + bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); > + data = xe_bo_map(fd, bo, 0x40000); > + > + batch_offset = (char *)&data[0].batch - (char *)data; > + batch_addr = addr + batch_offset; > + sdi_offset = (char *)&data[0].data - (char *)data; > + sdi_addr = addr + sdi_offset; > + > + b = 0; > + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4; > + data[0].batch[b++] = sdi_addr; > + data[0].batch[b++] = sdi_addr >> 32; > + data[0].batch[b++] = 0xc0ffee; > + data[0].batch[b++] = MI_BATCH_BUFFER_END; > + igt_assert(b <= ARRAY_SIZE(data[0].batch)); > + > + wait.addr = to_user_pointer(&data[0].exec_sync); > + exec.exec_queue_id = exec_queue; > + exec.address = batch_addr; > + > + xe_exec(fd, &exec); > + > + /** > + * Skipping the GPU mapping(vm_bind) for object, so that exec_queue > + * reset will happen and xe_wait_ufence will end return EIO not ETIME > + */ > + do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EIO); > + > + xe_exec_queue_destroy(fd, exec_queue); > + > + if (bo) { > + munmap(data, 0x40000); > + gem_close(fd, bo); > + } > +} > + > igt_main > { > int fd; > @@ -249,6 +329,9 @@ igt_main > igt_subtest("invalid-ops") > invalid_ops(fd); > > + igt_subtest("invalid-exec_queue-wait") > + invalid_exec_queue_wait(fd); > + > igt_fixture > drm_close_driver(fd); > } > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] [PATCH v4 2/2] drm-uapi/xe: kill xe_wait_user_fence_ioctl when exec_queue reset happen 2023-12-06 14:44 [igt-dev] [PATCH v4 0/2] RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure Bommu Krishnaiah 2023-12-06 14:44 ` [igt-dev] [PATCH v4 1/2] " Bommu Krishnaiah 2023-12-06 14:44 ` [igt-dev] [PATCH v4 1/1] drm-uapi/xe: kill xe_wait_user_fence_ioctl when exec_queue reset happen Bommu Krishnaiah @ 2023-12-06 14:44 ` Bommu Krishnaiah 2023-12-06 17:08 ` Rodrigo Vivi 2023-12-06 17:25 ` [igt-dev] ✓ Fi.CI.BAT: success for RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure (rev4) Patchwork ` (2 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Bommu Krishnaiah @ 2023-12-06 14:44 UTC (permalink / raw) To: igt-dev; +Cc: Bommu Krishnaiah, Rodrigo Vivi Skipping the GPU mapping(vm_bind) for object, so that exec_queue reset will happen and xe_wait_ufence will end return EIO not ETIME Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Francois Dugast <francois.dugast@intel.com> --- tests/intel/xe_waitfence.c | 83 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c index 0bd7e5dce..b5bf0d5b6 100644 --- a/tests/intel/xe_waitfence.c +++ b/tests/intel/xe_waitfence.c @@ -177,6 +177,9 @@ waitfence(int fd, enum waittype wt) * * SUBTEST: invalid-ops * Description: Check query with invalid ops returns expected error code + * + * SUBTEST: invalid-exec_queue-wait + * Description: Check xe_wait_ufence will return expected error code while exec_queue reset happen */ static void @@ -227,6 +230,83 @@ invalid_ops(int fd) do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EINVAL); } +static void +invalid_exec_queue_wait(int fd) +{ + uint32_t bo, b; + uint64_t batch_offset; + uint64_t batch_addr; + uint64_t sdi_offset; + uint64_t sdi_addr; + uint64_t addr = 0x1a0000; + + struct { + uint32_t batch[16]; + uint64_t pad; + uint64_t vm_sync; + uint64_t exec_sync; + uint32_t data; + } *data; + +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull + struct drm_xe_sync sync[1] = { + { .flags = DRM_XE_SYNC_TYPE_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL, + .timeline_value = USER_FENCE_VALUE }, + }; + + struct drm_xe_exec exec = { + .num_batch_buffer = 1, + .num_syncs = 1, + .syncs = to_user_pointer(sync), + }; + + uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + uint32_t exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); + struct drm_xe_wait_user_fence wait = { + .op = DRM_XE_UFENCE_WAIT_OP_EQ, + .flags = 0, + .value = 0xc0ffee, + .mask = DRM_XE_UFENCE_WAIT_MASK_U64, + .timeout = -1, + .exec_queue_id = exec_queue, + }; + + bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); + data = xe_bo_map(fd, bo, 0x40000); + + batch_offset = (char *)&data[0].batch - (char *)data; + batch_addr = addr + batch_offset; + sdi_offset = (char *)&data[0].data - (char *)data; + sdi_addr = addr + sdi_offset; + + b = 0; + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4; + data[0].batch[b++] = sdi_addr; + data[0].batch[b++] = sdi_addr >> 32; + data[0].batch[b++] = 0xc0ffee; + data[0].batch[b++] = MI_BATCH_BUFFER_END; + igt_assert(b <= ARRAY_SIZE(data[0].batch)); + + wait.addr = to_user_pointer(&data[0].exec_sync); + exec.exec_queue_id = exec_queue; + exec.address = batch_addr; + + xe_exec(fd, &exec); + + /** + * Skipping the GPU mapping(vm_bind) for object, so that exec_queue + * reset will happen and xe_wait_ufence will end return EIO not ETIME + */ + do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EIO); + + xe_exec_queue_destroy(fd, exec_queue); + + if (bo) { + munmap(data, 0x40000); + gem_close(fd, bo); + } +} + igt_main { int fd; @@ -249,6 +329,9 @@ igt_main igt_subtest("invalid-ops") invalid_ops(fd); + igt_subtest("invalid-exec_queue-wait") + invalid_exec_queue_wait(fd); + igt_fixture drm_close_driver(fd); } -- 2.25.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 2/2] drm-uapi/xe: kill xe_wait_user_fence_ioctl when exec_queue reset happen 2023-12-06 14:44 ` [igt-dev] [PATCH v4 2/2] " Bommu Krishnaiah @ 2023-12-06 17:08 ` Rodrigo Vivi 0 siblings, 0 replies; 12+ messages in thread From: Rodrigo Vivi @ 2023-12-06 17:08 UTC (permalink / raw) To: Bommu Krishnaiah; +Cc: igt-dev On Wed, Dec 06, 2023 at 08:14:52PM +0530, Bommu Krishnaiah wrote: > Skipping the GPU mapping(vm_bind) for object, so that exec_queue > reset will happen and xe_wait_ufence will end return EIO not ETIME oh, now I saw that this is really the second patch in the series and that number in the subject was wrong... Anyway, I see the test below adding a new check, not 'killing' or 'skipping' anything. > > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Francois Dugast <francois.dugast@intel.com> > --- > tests/intel/xe_waitfence.c | 83 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 83 insertions(+) > > diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c > index 0bd7e5dce..b5bf0d5b6 100644 > --- a/tests/intel/xe_waitfence.c > +++ b/tests/intel/xe_waitfence.c > @@ -177,6 +177,9 @@ waitfence(int fd, enum waittype wt) > * > * SUBTEST: invalid-ops > * Description: Check query with invalid ops returns expected error code > + * > + * SUBTEST: invalid-exec_queue-wait > + * Description: Check xe_wait_ufence will return expected error code while exec_queue reset happen > */ > > static void > @@ -227,6 +230,83 @@ invalid_ops(int fd) > do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EINVAL); > } > > +static void > +invalid_exec_queue_wait(int fd) > +{ > + uint32_t bo, b; > + uint64_t batch_offset; > + uint64_t batch_addr; > + uint64_t sdi_offset; > + uint64_t sdi_addr; > + uint64_t addr = 0x1a0000; > + > + struct { > + uint32_t batch[16]; > + uint64_t pad; > + uint64_t vm_sync; > + uint64_t exec_sync; > + uint32_t data; > + } *data; > + > +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull > + struct drm_xe_sync sync[1] = { > + { .flags = DRM_XE_SYNC_TYPE_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL, > + .timeline_value = USER_FENCE_VALUE }, > + }; > + > + struct drm_xe_exec exec = { > + .num_batch_buffer = 1, > + .num_syncs = 1, > + .syncs = to_user_pointer(sync), > + }; > + > + uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); > + uint32_t exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); > + struct drm_xe_wait_user_fence wait = { > + .op = DRM_XE_UFENCE_WAIT_OP_EQ, > + .flags = 0, > + .value = 0xc0ffee, > + .mask = DRM_XE_UFENCE_WAIT_MASK_U64, > + .timeout = -1, > + .exec_queue_id = exec_queue, > + }; > + > + bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); > + data = xe_bo_map(fd, bo, 0x40000); > + > + batch_offset = (char *)&data[0].batch - (char *)data; > + batch_addr = addr + batch_offset; > + sdi_offset = (char *)&data[0].data - (char *)data; > + sdi_addr = addr + sdi_offset; > + > + b = 0; > + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4; > + data[0].batch[b++] = sdi_addr; > + data[0].batch[b++] = sdi_addr >> 32; > + data[0].batch[b++] = 0xc0ffee; > + data[0].batch[b++] = MI_BATCH_BUFFER_END; > + igt_assert(b <= ARRAY_SIZE(data[0].batch)); > + > + wait.addr = to_user_pointer(&data[0].exec_sync); > + exec.exec_queue_id = exec_queue; > + exec.address = batch_addr; > + > + xe_exec(fd, &exec); > + > + /** > + * Skipping the GPU mapping(vm_bind) for object, so that exec_queue > + * reset will happen and xe_wait_ufence will end return EIO not ETIME > + */ > + do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EIO); > + > + xe_exec_queue_destroy(fd, exec_queue); > + > + if (bo) { > + munmap(data, 0x40000); > + gem_close(fd, bo); > + } > +} > + > igt_main > { > int fd; > @@ -249,6 +329,9 @@ igt_main > igt_subtest("invalid-ops") > invalid_ops(fd); > > + igt_subtest("invalid-exec_queue-wait") > + invalid_exec_queue_wait(fd); > + > igt_fixture > drm_close_driver(fd); > } > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure (rev4) 2023-12-06 14:44 [igt-dev] [PATCH v4 0/2] RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure Bommu Krishnaiah ` (2 preceding siblings ...) 2023-12-06 14:44 ` [igt-dev] [PATCH v4 2/2] " Bommu Krishnaiah @ 2023-12-06 17:25 ` Patchwork 2023-12-06 19:09 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 2023-12-06 19:20 ` [igt-dev] ✗ CI.xeBAT: " Patchwork 5 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2023-12-06 17:25 UTC (permalink / raw) To: Bommu, Krishnaiah; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 6878 bytes --] == Series Details == Series: RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure (rev4) URL : https://patchwork.freedesktop.org/series/127364/ State : success == Summary == CI Bug Log - changes from CI_DRM_13988 -> IGTPW_10354 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/index.html Participating hosts (37 -> 37) ------------------------------ Additional (1): bat-dg1-5 Missing (1): fi-snb-2520m Known issues ------------ Here are the changes found in IGTPW_10354 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@core_hotunplug@unbind-rebind: - bat-dg1-5: NOTRUN -> [ABORT][1] ([i915#8213]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@core_hotunplug@unbind-rebind.html * igt@gem_mmap@basic: - bat-dg1-5: NOTRUN -> [SKIP][2] ([i915#4083]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@gem_mmap@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][3] ([i915#4077]) +2 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@gem_tiled_fence_blits@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#4079]) +1 other test skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@i915_pm_rps@basic-api.html * igt@kms_addfb_basic@basic-x-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][6] ([i915#4212]) +7 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#4215]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#4103] / [i915#4213]) +1 other test skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-dg1-5: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#3840]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@kms_dsc@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-5: NOTRUN -> [SKIP][10] ([fdo#109285]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_hdmi_inject@inject-audio: - bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#433]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@kms_hdmi_inject@inject-audio.html * igt@kms_pm_backlight@basic-brightness: - bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#5354]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@kms_pm_backlight@basic-brightness.html * igt@kms_psr@psr_primary_mmap_gtt: - bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#9673] / [i915#9732]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@kms_psr@psr_primary_mmap_gtt.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#3555]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-read: - bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#3708]) +3 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@prime_vgem@basic-fence-read.html * igt@prime_vgem@basic-gtt: - bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#3708] / [i915#4077]) +1 other test skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-dg1-5/igt@prime_vgem@basic-gtt.html #### Warnings #### * igt@kms_pipe_crc_basic@nonblocking-crc: - bat-mtlp-6: [SKIP][17] -> [SKIP][18] ([i915#9792]) +3 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/bat-mtlp-6/igt@kms_pipe_crc_basic@nonblocking-crc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-mtlp-6/igt@kms_pipe_crc_basic@nonblocking-crc.html * igt@prime_vgem@basic-fence-flip: - bat-mtlp-6: [SKIP][19] ([i915#3708]) -> [SKIP][20] ([i915#3708] / [i915#9792]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213 [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673 [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732 [i915#9792]: https://gitlab.freedesktop.org/drm/intel/issues/9792 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7625 -> IGTPW_10354 CI-20190529: 20190529 CI_DRM_13988: 6ae23377ae459d8506ecdd2f538bfee2f52652f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_10354: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/index.html IGT_7625: f40c67d84e142095ac6215be154e1f3710f26cba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Testlist changes ---------------- +igt@xe_waitfence@invalid-exec_queue-wait -igt@xe_waitfence@invalid-engine == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/index.html [-- Attachment #2: Type: text/html, Size: 8333 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure (rev4) 2023-12-06 14:44 [igt-dev] [PATCH v4 0/2] RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure Bommu Krishnaiah ` (3 preceding siblings ...) 2023-12-06 17:25 ` [igt-dev] ✓ Fi.CI.BAT: success for RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure (rev4) Patchwork @ 2023-12-06 19:09 ` Patchwork 2023-12-06 19:20 ` [igt-dev] ✗ CI.xeBAT: " Patchwork 5 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2023-12-06 19:09 UTC (permalink / raw) To: Bommu, Krishnaiah; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 100305 bytes --] == Series Details == Series: RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure (rev4) URL : https://patchwork.freedesktop.org/series/127364/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13988_full -> IGTPW_10354_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_10354_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_10354_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/index.html Participating hosts (8 -> 9) ------------------------------ Additional (1): shard-snb-0 Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_10354_full: ### IGT changes ### #### Possible regressions #### * igt@gem_lmem_swapping@basic@lmem0: - shard-dg1: NOTRUN -> [ABORT][1] +6 other tests abort [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@gem_lmem_swapping@basic@lmem0.html * igt@i915_module_load@reload-with-fault-injection: - shard-rkl: NOTRUN -> [ABORT][2] +3 other tests abort [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html - shard-tglu: NOTRUN -> [ABORT][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-9/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_selftest@live@gt_pm: - shard-glk: [PASS][4] -> [DMESG-FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-glk9/igt@i915_selftest@live@gt_pm.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-glk4/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@perf@engine_cs: - shard-dg2: NOTRUN -> [ABORT][6] +9 other tests abort [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@i915_selftest@perf@engine_cs.html * igt@kms_content_protection@uevent: - shard-snb: NOTRUN -> [INCOMPLETE][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb7/igt@kms_content_protection@uevent.html * igt@kms_dirtyfb@psr-dirtyfb-ioctl: - shard-dg2: NOTRUN -> [SKIP][8] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-7/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html * igt@kms_pm_backlight@fade-with-suspend: - shard-tglu: NOTRUN -> [SKIP][9] +2 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-8/igt@kms_pm_backlight@fade-with-suspend.html Known issues ------------ Here are the changes found in IGTPW_10354_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@object-reloc-purge-cache: - shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8411]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@api_intel_bb@object-reloc-purge-cache.html - shard-rkl: NOTRUN -> [SKIP][11] ([i915#8411]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@api_intel_bb@object-reloc-purge-cache.html * igt@core_hotunplug@unbind-rebind: - shard-dg2: NOTRUN -> [ABORT][12] ([i915#8213]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-2/igt@core_hotunplug@unbind-rebind.html - shard-dg1: NOTRUN -> [ABORT][13] ([i915#8213]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-17/igt@core_hotunplug@unbind-rebind.html * igt@debugfs_test@basic-hwmon: - shard-mtlp: NOTRUN -> [SKIP][14] ([i915#9318]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@debugfs_test@basic-hwmon.html - shard-rkl: NOTRUN -> [SKIP][15] ([i915#9318]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@debugfs_test@basic-hwmon.html - shard-tglu: NOTRUN -> [SKIP][16] ([i915#9318]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-8/igt@debugfs_test@basic-hwmon.html * igt@device_reset@unbind-cold-reset-rebind: - shard-rkl: NOTRUN -> [SKIP][17] ([i915#7701]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@device_reset@unbind-cold-reset-rebind.html - shard-dg1: NOTRUN -> [SKIP][18] ([i915#7701]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-16/igt@device_reset@unbind-cold-reset-rebind.html - shard-tglu: NOTRUN -> [SKIP][19] ([i915#7701]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-2/igt@device_reset@unbind-cold-reset-rebind.html - shard-mtlp: NOTRUN -> [SKIP][20] ([i915#7701]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@device_reset@unbind-cold-reset-rebind.html - shard-dg2: NOTRUN -> [SKIP][21] ([i915#7701]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-5/igt@device_reset@unbind-cold-reset-rebind.html * igt@drm_fdinfo@all-busy-idle-check-all: - shard-mtlp: NOTRUN -> [SKIP][22] ([i915#8414]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@drm_fdinfo@all-busy-idle-check-all.html * igt@drm_fdinfo@idle@rcs0: - shard-rkl: NOTRUN -> [FAIL][23] ([i915#7742]) +1 other test fail [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@drm_fdinfo@idle@rcs0.html * igt@drm_fdinfo@most-busy-check-all@bcs0: - shard-dg2: NOTRUN -> [SKIP][24] ([i915#8414]) +10 other tests skip [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@drm_fdinfo@most-busy-check-all@bcs0.html - shard-dg1: NOTRUN -> [SKIP][25] ([i915#8414]) +4 other tests skip [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@drm_fdinfo@most-busy-check-all@bcs0.html * igt@gem_busy@semaphore: - shard-dg2: NOTRUN -> [SKIP][26] ([i915#3936]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@gem_busy@semaphore.html - shard-dg1: NOTRUN -> [SKIP][27] ([i915#3936]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@gem_busy@semaphore.html - shard-mtlp: NOTRUN -> [SKIP][28] ([i915#3936]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@gem_busy@semaphore.html * igt@gem_ccs@block-multicopy-compressed: - shard-rkl: NOTRUN -> [SKIP][29] ([i915#9323]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@gem_ccs@block-multicopy-compressed.html - shard-tglu: NOTRUN -> [SKIP][30] ([i915#9323]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-2/igt@gem_ccs@block-multicopy-compressed.html - shard-mtlp: NOTRUN -> [SKIP][31] ([i915#9323]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@gem_ccs@block-multicopy-compressed.html * igt@gem_ccs@ctrl-surf-copy: - shard-mtlp: NOTRUN -> [SKIP][32] ([i915#3555]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@gem_ccs@ctrl-surf-copy.html * igt@gem_ccs@suspend-resume: - shard-dg1: NOTRUN -> [SKIP][33] ([i915#9323]) +1 other test skip [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-17/igt@gem_ccs@suspend-resume.html * igt@gem_create@create-ext-set-pat: - shard-dg2: NOTRUN -> [SKIP][34] ([i915#8562]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-2/igt@gem_create@create-ext-set-pat.html - shard-rkl: NOTRUN -> [SKIP][35] ([i915#8562]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@gem_create@create-ext-set-pat.html - shard-dg1: NOTRUN -> [SKIP][36] ([i915#8562]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@gem_create@create-ext-set-pat.html - shard-tglu: NOTRUN -> [SKIP][37] ([i915#8562]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-9/igt@gem_create@create-ext-set-pat.html * igt@gem_ctx_persistence@engines-cleanup: - shard-snb: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#1099]) +2 other tests skip [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb2/igt@gem_ctx_persistence@engines-cleanup.html * igt@gem_ctx_persistence@heartbeat-many: - shard-mtlp: NOTRUN -> [SKIP][39] ([i915#8555]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@gem_ctx_persistence@heartbeat-many.html * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0: - shard-dg2: NOTRUN -> [SKIP][40] ([i915#5882]) +9 other tests skip [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html * igt@gem_eio@hibernate: - shard-dg2: NOTRUN -> [ABORT][41] ([i915#7975] / [i915#8213]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-2/igt@gem_eio@hibernate.html * igt@gem_eio@reset-stress: - shard-dg2: NOTRUN -> [FAIL][42] ([i915#5784]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@gem_eio@reset-stress.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][43] ([i915#8898]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb6/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@bonded-sync: - shard-mtlp: NOTRUN -> [SKIP][44] ([i915#4771]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-1/igt@gem_exec_balancer@bonded-sync.html * igt@gem_exec_balancer@parallel-balancer: - shard-rkl: NOTRUN -> [SKIP][45] ([i915#4525]) +3 other tests skip [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@gem_exec_balancer@parallel-balancer.html * igt@gem_exec_balancer@sliced: - shard-dg2: NOTRUN -> [SKIP][46] ([i915#4812]) +1 other test skip [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@gem_exec_balancer@sliced.html * igt@gem_exec_capture@many-4k-incremental: - shard-mtlp: NOTRUN -> [FAIL][47] ([i915#9606]) +1 other test fail [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@gem_exec_capture@many-4k-incremental.html * igt@gem_exec_fair@basic-none: - shard-mtlp: NOTRUN -> [SKIP][48] ([i915#4473] / [i915#4771]) +1 other test skip [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@gem_exec_fair@basic-none.html * igt@gem_exec_fair@basic-none-share: - shard-dg2: NOTRUN -> [SKIP][49] ([i915#3539] / [i915#4852]) +8 other tests skip [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@gem_exec_fair@basic-none-share.html * igt@gem_exec_fair@basic-none@bcs0: - shard-rkl: NOTRUN -> [FAIL][50] ([i915#2842]) +2 other tests fail [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@gem_exec_fair@basic-none@bcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-tglu: NOTRUN -> [FAIL][51] ([i915#2842]) +9 other tests fail [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-8/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglu: [PASS][52] -> [FAIL][53] ([i915#2842]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-tglu-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-5/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_fair@basic-sync: - shard-dg1: NOTRUN -> [SKIP][54] ([i915#3539]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@gem_exec_fair@basic-sync.html * igt@gem_exec_fence@submit67: - shard-mtlp: NOTRUN -> [SKIP][55] ([i915#4812]) +4 other tests skip [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@gem_exec_fence@submit67.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-rkl: NOTRUN -> [SKIP][56] ([fdo#109313]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html * igt@gem_exec_flush@basic-batch-kernel-default-wb: - shard-dg1: NOTRUN -> [SKIP][57] ([i915#3539] / [i915#4852]) +8 other tests skip [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@gem_exec_flush@basic-batch-kernel-default-wb.html * igt@gem_exec_gttfill@multigpu-basic: - shard-dg2: NOTRUN -> [SKIP][58] ([i915#7697]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@gem_exec_gttfill@multigpu-basic.html - shard-dg1: NOTRUN -> [SKIP][59] ([i915#7697]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-15/igt@gem_exec_gttfill@multigpu-basic.html * igt@gem_exec_params@rsvd2-dirt: - shard-dg2: NOTRUN -> [SKIP][60] ([fdo#109283] / [i915#5107]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@gem_exec_params@rsvd2-dirt.html - shard-rkl: NOTRUN -> [SKIP][61] ([fdo#109283]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@gem_exec_params@rsvd2-dirt.html * igt@gem_exec_reloc@basic-active: - shard-dg2: NOTRUN -> [SKIP][62] ([i915#3281]) +10 other tests skip [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@gem_exec_reloc@basic-active.html - shard-rkl: NOTRUN -> [SKIP][63] ([i915#3281]) +10 other tests skip [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@gem_exec_reloc@basic-active.html * igt@gem_exec_reloc@basic-gtt-wc: - shard-mtlp: NOTRUN -> [SKIP][64] ([i915#3281]) +10 other tests skip [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@gem_exec_reloc@basic-gtt-wc.html * igt@gem_exec_reloc@basic-write-read-noreloc: - shard-dg1: NOTRUN -> [SKIP][65] ([i915#3281]) +16 other tests skip [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-14/igt@gem_exec_reloc@basic-write-read-noreloc.html * igt@gem_exec_schedule@deep@rcs0: - shard-mtlp: NOTRUN -> [SKIP][66] ([i915#4537]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@gem_exec_schedule@deep@rcs0.html * igt@gem_exec_schedule@preempt-queue-contexts-chain: - shard-mtlp: NOTRUN -> [SKIP][67] ([i915#4537] / [i915#4812]) +1 other test skip [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@gem_exec_schedule@preempt-queue-contexts-chain.html * igt@gem_exec_schedule@reorder-wide: - shard-dg2: NOTRUN -> [SKIP][68] ([i915#4537] / [i915#4812]) +1 other test skip [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@gem_exec_schedule@reorder-wide.html - shard-dg1: NOTRUN -> [SKIP][69] ([i915#4812]) +5 other tests skip [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@gem_exec_schedule@reorder-wide.html * igt@gem_fenced_exec_thrash@no-spare-fences-busy: - shard-dg1: NOTRUN -> [SKIP][70] ([i915#4860]) +2 other tests skip [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible: - shard-dg2: NOTRUN -> [SKIP][71] ([i915#4860]) +2 other tests skip [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html * igt@gem_fenced_exec_thrash@too-many-fences: - shard-mtlp: NOTRUN -> [SKIP][72] ([i915#4860]) +2 other tests skip [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@gem_fenced_exec_thrash@too-many-fences.html * igt@gem_lmem_swapping@heavy-random: - shard-glk: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#4613]) +2 other tests skip [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-glk4/igt@gem_lmem_swapping@heavy-random.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-mtlp: NOTRUN -> [SKIP][74] ([i915#4613]) +2 other tests skip [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-1/igt@gem_lmem_swapping@heavy-verify-multi.html * igt@gem_lmem_swapping@parallel-random-verify-ccs: - shard-rkl: NOTRUN -> [SKIP][75] ([i915#4613]) +2 other tests skip [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@gem_lmem_swapping@parallel-random-verify-ccs.html * igt@gem_lmem_swapping@verify-random-ccs: - shard-tglu: NOTRUN -> [SKIP][76] ([i915#4613]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-10/igt@gem_lmem_swapping@verify-random-ccs.html * igt@gem_media_fill@media-fill: - shard-mtlp: NOTRUN -> [SKIP][77] ([i915#8289]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@gem_media_fill@media-fill.html * igt@gem_mmap@short-mmap: - shard-mtlp: NOTRUN -> [SKIP][78] ([i915#4083]) +3 other tests skip [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@gem_mmap@short-mmap.html * igt@gem_mmap_gtt@hang-busy: - shard-mtlp: NOTRUN -> [SKIP][79] ([i915#4077]) +11 other tests skip [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@gem_mmap_gtt@hang-busy.html * igt@gem_mmap_wc@write-cpu-read-wc-unflushed: - shard-dg1: NOTRUN -> [SKIP][80] ([i915#4083]) +8 other tests skip [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html * igt@gem_mmap_wc@write-prefaulted: - shard-dg2: NOTRUN -> [SKIP][81] ([i915#4083]) +11 other tests skip [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@gem_mmap_wc@write-prefaulted.html * igt@gem_partial_pwrite_pread@write-display: - shard-mtlp: NOTRUN -> [SKIP][82] ([i915#3282]) +4 other tests skip [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@gem_partial_pwrite_pread@write-display.html * igt@gem_partial_pwrite_pread@writes-after-reads-uncached: - shard-rkl: NOTRUN -> [SKIP][83] ([i915#3282]) +5 other tests skip [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html * igt@gem_pread@exhaustion: - shard-dg1: NOTRUN -> [SKIP][84] ([i915#3282]) +9 other tests skip [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-15/igt@gem_pread@exhaustion.html - shard-snb: NOTRUN -> [WARN][85] ([i915#2658]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb2/igt@gem_pread@exhaustion.html - shard-tglu: NOTRUN -> [WARN][86] ([i915#2658]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-3/igt@gem_pread@exhaustion.html * igt@gem_pwrite@basic-random: - shard-dg2: NOTRUN -> [SKIP][87] ([i915#3282]) +10 other tests skip [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-7/igt@gem_pwrite@basic-random.html * igt@gem_pxp@create-regular-context-1: - shard-mtlp: NOTRUN -> [SKIP][88] ([i915#4270]) +4 other tests skip [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@gem_pxp@create-regular-context-1.html * igt@gem_pxp@reject-modify-context-protection-off-2: - shard-dg2: NOTRUN -> [SKIP][89] ([i915#4270]) +2 other tests skip [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-7/igt@gem_pxp@reject-modify-context-protection-off-2.html * igt@gem_pxp@reject-modify-context-protection-off-3: - shard-snb: NOTRUN -> [SKIP][90] ([fdo#109271]) +276 other tests skip [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb5/igt@gem_pxp@reject-modify-context-protection-off-3.html - shard-dg1: NOTRUN -> [SKIP][91] ([i915#4270]) +2 other tests skip [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@gem_pxp@reject-modify-context-protection-off-3.html - shard-tglu: NOTRUN -> [SKIP][92] ([i915#4270]) +2 other tests skip [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-7/igt@gem_pxp@reject-modify-context-protection-off-3.html * igt@gem_pxp@reject-modify-context-protection-on: - shard-rkl: NOTRUN -> [SKIP][93] ([i915#4270]) +3 other tests skip [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@gem_pxp@reject-modify-context-protection-on.html * igt@gem_render_copy@y-tiled-ccs-to-linear: - shard-dg2: NOTRUN -> [SKIP][94] ([i915#5190]) +16 other tests skip [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-2/igt@gem_render_copy@y-tiled-ccs-to-linear.html * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs: - shard-mtlp: NOTRUN -> [SKIP][95] ([i915#8428]) +7 other tests skip [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html * igt@gem_render_tiled_blits@basic: - shard-dg1: NOTRUN -> [SKIP][96] ([i915#4079]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-15/igt@gem_render_tiled_blits@basic.html - shard-dg2: NOTRUN -> [SKIP][97] ([i915#4079]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@gem_render_tiled_blits@basic.html * igt@gem_softpin@evict-snoop-interruptible: - shard-dg2: NOTRUN -> [SKIP][98] ([i915#4885]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@gem_softpin@evict-snoop-interruptible.html - shard-rkl: NOTRUN -> [SKIP][99] ([fdo#109312]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@gem_softpin@evict-snoop-interruptible.html - shard-dg1: NOTRUN -> [SKIP][100] ([i915#4885]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-14/igt@gem_softpin@evict-snoop-interruptible.html - shard-tglu: NOTRUN -> [SKIP][101] ([fdo#109312]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-9/igt@gem_softpin@evict-snoop-interruptible.html - shard-mtlp: NOTRUN -> [SKIP][102] ([i915#4885]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@gem_softpin@evict-snoop-interruptible.html * igt@gem_tiled_partial_pwrite_pread@writes: - shard-dg2: NOTRUN -> [SKIP][103] ([i915#4077]) +17 other tests skip [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@gem_tiled_partial_pwrite_pread@writes.html * igt@gem_tiled_partial_pwrite_pread@writes-after-reads: - shard-dg1: NOTRUN -> [SKIP][104] ([i915#4077]) +21 other tests skip [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-17/igt@gem_tiled_partial_pwrite_pread@writes-after-reads.html * igt@gem_tiled_pread_pwrite: - shard-mtlp: NOTRUN -> [SKIP][105] ([i915#4079]) +2 other tests skip [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@gem_tiled_pread_pwrite.html * igt@gem_userptr_blits@create-destroy-unsync: - shard-dg2: NOTRUN -> [SKIP][106] ([i915#3297]) +3 other tests skip [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@gem_userptr_blits@create-destroy-unsync.html - shard-dg1: NOTRUN -> [SKIP][107] ([i915#3297]) +3 other tests skip [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@gem_userptr_blits@create-destroy-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-dg2: NOTRUN -> [SKIP][108] ([i915#3297] / [i915#4880]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html - shard-dg1: NOTRUN -> [SKIP][109] ([i915#3297] / [i915#4880]) [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html * igt@gem_userptr_blits@unsync-overlap: - shard-mtlp: NOTRUN -> [SKIP][110] ([i915#3297]) +6 other tests skip [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@gem_userptr_blits@unsync-overlap.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-rkl: NOTRUN -> [SKIP][111] ([i915#3297]) +2 other tests skip [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-3/igt@gem_userptr_blits@unsync-unmap-cycles.html - shard-tglu: NOTRUN -> [SKIP][112] ([i915#3297]) +2 other tests skip [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-9/igt@gem_userptr_blits@unsync-unmap-cycles.html * igt@gen3_render_linear_blits: - shard-rkl: NOTRUN -> [SKIP][113] ([fdo#109289]) +2 other tests skip [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@gen3_render_linear_blits.html * igt@gen7_exec_parse@batch-without-end: - shard-dg1: NOTRUN -> [SKIP][114] ([fdo#109289]) +4 other tests skip [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-14/igt@gen7_exec_parse@batch-without-end.html * igt@gen7_exec_parse@bitmasks: - shard-dg2: NOTRUN -> [SKIP][115] ([fdo#109289]) +5 other tests skip [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@gen7_exec_parse@bitmasks.html * igt@gen9_exec_parse@allowed-all: - shard-mtlp: NOTRUN -> [SKIP][116] ([i915#2856]) +5 other tests skip [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@gen9_exec_parse@allowed-all.html * igt@gen9_exec_parse@bb-chained: - shard-rkl: NOTRUN -> [SKIP][117] ([i915#2527]) +3 other tests skip [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@gen9_exec_parse@bb-chained.html * igt@gen9_exec_parse@bb-oversize: - shard-dg1: NOTRUN -> [SKIP][118] ([i915#2527]) +5 other tests skip [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@gen9_exec_parse@bb-oversize.html * igt@gen9_exec_parse@bb-start-far: - shard-dg2: NOTRUN -> [SKIP][119] ([i915#2856]) +6 other tests skip [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-2/igt@gen9_exec_parse@bb-start-far.html * igt@gen9_exec_parse@bb-start-param: - shard-tglu: NOTRUN -> [SKIP][120] ([i915#2527] / [i915#2856]) +2 other tests skip [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-5/igt@gen9_exec_parse@bb-start-param.html * igt@i915_fb_tiling: - shard-mtlp: NOTRUN -> [SKIP][121] ([i915#4881]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@i915_fb_tiling.html * igt@i915_module_load@reload-with-fault-injection: - shard-glk: NOTRUN -> [ABORT][122] ([i915#8668]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-glk3/igt@i915_module_load@reload-with-fault-injection.html - shard-mtlp: NOTRUN -> [ABORT][123] ([i915#8668]) [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_module_load@resize-bar: - shard-rkl: NOTRUN -> [SKIP][124] ([i915#6412]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@i915_module_load@resize-bar.html - shard-tglu: NOTRUN -> [SKIP][125] ([i915#6412]) [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-8/igt@i915_module_load@resize-bar.html - shard-mtlp: NOTRUN -> [SKIP][126] ([i915#6412]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@i915_module_load@resize-bar.html * igt@i915_pipe_stress@stress-xrgb8888-ytiled: - shard-mtlp: NOTRUN -> [SKIP][127] ([i915#8436]) [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html * igt@i915_pm_freq_api@freq-suspend: - shard-rkl: NOTRUN -> [SKIP][128] ([i915#8399]) +1 other test skip [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-1/igt@i915_pm_freq_api@freq-suspend.html * igt@i915_pm_rps@min-max-config-idle: - shard-dg2: NOTRUN -> [SKIP][129] ([i915#6621]) [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@i915_pm_rps@min-max-config-idle.html - shard-dg1: NOTRUN -> [SKIP][130] ([i915#6621]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@i915_pm_rps@min-max-config-idle.html * igt@i915_pm_rps@thresholds@gt0: - shard-mtlp: NOTRUN -> [SKIP][131] ([i915#8925]) [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@i915_pm_rps@thresholds@gt0.html * igt@i915_pm_rps@thresholds@gt1: - shard-mtlp: NOTRUN -> [SKIP][132] ([i915#3555] / [i915#8925]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@i915_pm_rps@thresholds@gt1.html * igt@i915_pm_rps@waitboost: - shard-mtlp: NOTRUN -> [FAIL][133] ([i915#8346]) [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-1/igt@i915_pm_rps@waitboost.html * igt@i915_query@query-topology-unsupported: - shard-rkl: NOTRUN -> [SKIP][134] ([fdo#109302]) [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@i915_query@query-topology-unsupported.html - shard-tglu: NOTRUN -> [SKIP][135] ([fdo#109302]) [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-4/igt@i915_query@query-topology-unsupported.html - shard-mtlp: NOTRUN -> [SKIP][136] ([fdo#109302]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@i915_query@query-topology-unsupported.html * igt@intel_hwmon@hwmon-write: - shard-rkl: NOTRUN -> [SKIP][137] ([i915#7707]) +1 other test skip [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@intel_hwmon@hwmon-write.html - shard-tglu: NOTRUN -> [SKIP][138] ([i915#7707]) +1 other test skip [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-7/igt@intel_hwmon@hwmon-write.html - shard-mtlp: NOTRUN -> [SKIP][139] ([i915#7707]) +1 other test skip [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@intel_hwmon@hwmon-write.html * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling: - shard-dg2: NOTRUN -> [SKIP][140] ([i915#4212]) +1 other test skip [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - shard-mtlp: NOTRUN -> [SKIP][141] ([i915#4212]) +3 other tests skip [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - shard-dg1: NOTRUN -> [SKIP][142] ([i915#4215]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_addfb_basic@bo-too-small-due-to-tiling: - shard-dg1: NOTRUN -> [SKIP][143] ([i915#4212]) +1 other test skip [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs: - shard-dg1: NOTRUN -> [SKIP][144] ([i915#8709]) +7 other tests skip [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-16/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs.html * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs: - shard-dg2: NOTRUN -> [SKIP][145] ([i915#8709]) +11 other tests skip [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html * igt@kms_async_flips@invalid-async-flip: - shard-dg2: NOTRUN -> [SKIP][146] ([i915#6228]) [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_async_flips@invalid-async-flip.html * igt@kms_big_fb@4-tiled-16bpp-rotate-90: - shard-mtlp: NOTRUN -> [SKIP][147] ([fdo#111614]) +4 other tests skip [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html * igt@kms_big_fb@4-tiled-32bpp-rotate-90: - shard-tglu: NOTRUN -> [SKIP][148] ([fdo#111615] / [i915#5286]) +6 other tests skip [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-6/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html * igt@kms_big_fb@4-tiled-64bpp-rotate-270: - shard-dg2: NOTRUN -> [SKIP][149] ([fdo#111614]) +2 other tests skip [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html * igt@kms_big_fb@4-tiled-addfb: - shard-rkl: NOTRUN -> [SKIP][150] ([i915#5286]) +7 other tests skip [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_big_fb@4-tiled-addfb.html - shard-dg1: NOTRUN -> [SKIP][151] ([i915#5286]) [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-14/igt@kms_big_fb@4-tiled-addfb.html - shard-tglu: NOTRUN -> [SKIP][152] ([i915#5286]) [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-9/igt@kms_big_fb@4-tiled-addfb.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-dg1: NOTRUN -> [SKIP][153] ([i915#4538] / [i915#5286]) +6 other tests skip [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-13/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@linear-32bpp-rotate-90: - shard-tglu: NOTRUN -> [SKIP][154] ([fdo#111614]) [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-5/igt@kms_big_fb@linear-32bpp-rotate-90.html * igt@kms_big_fb@x-tiled-32bpp-rotate-270: - shard-rkl: NOTRUN -> [SKIP][155] ([fdo#111614] / [i915#3638]) +1 other test skip [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html * igt@kms_big_fb@y-tiled-32bpp-rotate-180: - shard-mtlp: NOTRUN -> [SKIP][156] ([fdo#111615]) +11 other tests skip [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html * igt@kms_big_fb@y-tiled-64bpp-rotate-90: - shard-dg1: NOTRUN -> [SKIP][157] ([i915#3638]) +3 other tests skip [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-tglu: [PASS][158] -> [FAIL][159] ([i915#3743]) [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-tglu-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html * igt@kms_big_fb@yf-tiled-16bpp-rotate-270: - shard-rkl: NOTRUN -> [SKIP][160] ([fdo#110723]) +5 other tests skip [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html - shard-tglu: NOTRUN -> [SKIP][161] ([fdo#111615]) +2 other tests skip [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-0: - shard-dg2: NOTRUN -> [SKIP][162] ([i915#4538] / [i915#5190]) +4 other tests skip [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html * igt@kms_big_fb@yf-tiled-addfb: - shard-mtlp: NOTRUN -> [SKIP][163] ([i915#6187]) +4 other tests skip [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@kms_big_fb@yf-tiled-addfb.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0: - shard-dg1: NOTRUN -> [SKIP][164] ([i915#4538]) +5 other tests skip [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html * igt@kms_big_joiner@2x-modeset: - shard-dg1: NOTRUN -> [SKIP][165] ([i915#2705]) +1 other test skip [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_big_joiner@2x-modeset.html * igt@kms_big_joiner@basic: - shard-dg2: NOTRUN -> [SKIP][166] ([i915#2705]) [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_big_joiner@basic.html * igt@kms_big_joiner@invalid-modeset: - shard-mtlp: NOTRUN -> [SKIP][167] ([i915#2705]) [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@kms_big_joiner@invalid-modeset.html * igt@kms_ccs@pipe-a-bad-pixel-format-yf-tiled-ccs: - shard-tglu: NOTRUN -> [SKIP][168] ([i915#5354] / [i915#6095]) +44 other tests skip [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-9/igt@kms_ccs@pipe-a-bad-pixel-format-yf-tiled-ccs.html * igt@kms_ccs@pipe-a-bad-rotation-90-y-tiled-gen12-mc-ccs: - shard-dg1: NOTRUN -> [SKIP][169] ([i915#5354] / [i915#6095]) +69 other tests skip [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@kms_ccs@pipe-a-bad-rotation-90-y-tiled-gen12-mc-ccs.html * igt@kms_ccs@pipe-b-bad-rotation-90-y-tiled-gen12-mc-ccs: - shard-dg2: NOTRUN -> [SKIP][170] ([i915#5354]) +104 other tests skip [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_ccs@pipe-b-bad-rotation-90-y-tiled-gen12-mc-ccs.html * igt@kms_ccs@pipe-b-crc-primary-basic-yf-tiled-ccs: - shard-rkl: NOTRUN -> [SKIP][171] ([i915#5354] / [i915#6095]) +32 other tests skip [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@kms_ccs@pipe-b-crc-primary-basic-yf-tiled-ccs.html * igt@kms_ccs@pipe-d-ccs-on-another-bo-yf-tiled-ccs: - shard-mtlp: NOTRUN -> [SKIP][172] ([i915#5354] / [i915#6095]) +58 other tests skip [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@kms_ccs@pipe-d-ccs-on-another-bo-yf-tiled-ccs.html * igt@kms_ccs@pipe-d-random-ccs-data-4-tiled-mtl-rc-ccs-cc: - shard-rkl: NOTRUN -> [SKIP][173] ([i915#5354]) +30 other tests skip [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_ccs@pipe-d-random-ccs-data-4-tiled-mtl-rc-ccs-cc.html * igt@kms_cdclk@plane-scaling@pipe-d-dp-4: - shard-dg2: NOTRUN -> [SKIP][174] ([i915#4087]) +3 other tests skip [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@kms_cdclk@plane-scaling@pipe-d-dp-4.html * igt@kms_chamelium_color@ctm-0-50: - shard-dg1: NOTRUN -> [SKIP][175] ([fdo#111827]) +2 other tests skip [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-15/igt@kms_chamelium_color@ctm-0-50.html * igt@kms_chamelium_color@ctm-max: - shard-mtlp: NOTRUN -> [SKIP][176] ([fdo#111827]) +2 other tests skip [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@kms_chamelium_color@ctm-max.html * igt@kms_chamelium_color@gamma: - shard-tglu: NOTRUN -> [SKIP][177] ([fdo#111827]) +1 other test skip [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-8/igt@kms_chamelium_color@gamma.html - shard-dg2: NOTRUN -> [SKIP][178] ([fdo#111827]) +1 other test skip [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@kms_chamelium_color@gamma.html - shard-rkl: NOTRUN -> [SKIP][179] ([fdo#111827]) [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_chamelium_color@gamma.html * igt@kms_chamelium_edid@dp-edid-change-during-suspend: - shard-tglu: NOTRUN -> [SKIP][180] ([i915#7828]) +4 other tests skip [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-2/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html * igt@kms_chamelium_edid@dp-mode-timings: - shard-mtlp: NOTRUN -> [SKIP][181] ([i915#7828]) +11 other tests skip [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@kms_chamelium_edid@dp-mode-timings.html * igt@kms_chamelium_frames@dp-crc-fast: - shard-dg2: NOTRUN -> [SKIP][182] ([i915#7828]) +14 other tests skip [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-5/igt@kms_chamelium_frames@dp-crc-fast.html * igt@kms_chamelium_hpd@dp-hpd: - shard-rkl: NOTRUN -> [SKIP][183] ([i915#7828]) +6 other tests skip [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-1/igt@kms_chamelium_hpd@dp-hpd.html - shard-dg1: NOTRUN -> [SKIP][184] ([i915#7828]) +12 other tests skip [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-15/igt@kms_chamelium_hpd@dp-hpd.html * igt@kms_content_protection@atomic-dpms: - shard-tglu: NOTRUN -> [SKIP][185] ([i915#6944] / [i915#7116] / [i915#7118]) +1 other test skip [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-2/igt@kms_content_protection@atomic-dpms.html - shard-dg2: NOTRUN -> [SKIP][186] ([i915#7118]) [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-7/igt@kms_content_protection@atomic-dpms.html - shard-dg1: NOTRUN -> [SKIP][187] ([i915#7116]) [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-16/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@atomic@pipe-a-dp-4: - shard-dg2: NOTRUN -> [TIMEOUT][188] ([i915#7173]) [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@kms_content_protection@atomic@pipe-a-dp-4.html * igt@kms_content_protection@content-type-change: - shard-mtlp: NOTRUN -> [SKIP][189] ([i915#9424]) [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@kms_content_protection@content-type-change.html * igt@kms_content_protection@dp-mst-lic-type-1: - shard-dg2: NOTRUN -> [SKIP][190] ([i915#3299]) +2 other tests skip [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-5/igt@kms_content_protection@dp-mst-lic-type-1.html * igt@kms_content_protection@dp-mst-type-1: - shard-rkl: NOTRUN -> [SKIP][191] ([i915#3116]) +2 other tests skip [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@kms_content_protection@dp-mst-type-1.html - shard-dg1: NOTRUN -> [SKIP][192] ([i915#3299]) +2 other tests skip [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@kms_content_protection@dp-mst-type-1.html - shard-tglu: NOTRUN -> [SKIP][193] ([i915#3116] / [i915#3299]) +1 other test skip [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-8/igt@kms_content_protection@dp-mst-type-1.html - shard-mtlp: NOTRUN -> [SKIP][194] ([i915#3299]) +2 other tests skip [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@kms_content_protection@dp-mst-type-1.html * igt@kms_content_protection@mei-interface: - shard-rkl: NOTRUN -> [SKIP][195] ([i915#9424]) [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@kms_content_protection@mei-interface.html * igt@kms_content_protection@uevent: - shard-mtlp: NOTRUN -> [SKIP][196] ([i915#6944]) +1 other test skip [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@kms_content_protection@uevent.html - shard-rkl: NOTRUN -> [SKIP][197] ([i915#7118]) +1 other test skip [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@cursor-offscreen-512x170: - shard-tglu: NOTRUN -> [SKIP][198] ([fdo#109279] / [i915#3359]) [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-3/igt@kms_cursor_crc@cursor-offscreen-512x170.html - shard-rkl: NOTRUN -> [SKIP][199] ([fdo#109279] / [i915#3359]) [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@kms_cursor_crc@cursor-offscreen-512x170.html * igt@kms_cursor_crc@cursor-onscreen-32x10: - shard-mtlp: NOTRUN -> [SKIP][200] ([i915#3555] / [i915#8814]) +7 other tests skip [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-1/igt@kms_cursor_crc@cursor-onscreen-32x10.html * igt@kms_cursor_crc@cursor-onscreen-512x512: - shard-tglu: NOTRUN -> [SKIP][201] ([i915#3359]) +1 other test skip [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-5/igt@kms_cursor_crc@cursor-onscreen-512x512.html - shard-mtlp: NOTRUN -> [SKIP][202] ([i915#3359]) +3 other tests skip [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-1/igt@kms_cursor_crc@cursor-onscreen-512x512.html - shard-rkl: NOTRUN -> [SKIP][203] ([i915#3359]) [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@kms_cursor_crc@cursor-onscreen-512x512.html * igt@kms_cursor_crc@cursor-random-512x512: - shard-dg2: NOTRUN -> [SKIP][204] ([i915#3359]) +2 other tests skip [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-7/igt@kms_cursor_crc@cursor-random-512x512.html * igt@kms_cursor_crc@cursor-sliding-512x512: - shard-dg1: NOTRUN -> [SKIP][205] ([i915#3359]) +2 other tests skip [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-14/igt@kms_cursor_crc@cursor-sliding-512x512.html * igt@kms_cursor_legacy@cursora-vs-flipb-atomic: - shard-mtlp: NOTRUN -> [SKIP][206] ([i915#9809]) +5 other tests skip [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic: - shard-dg2: NOTRUN -> [SKIP][207] ([fdo#109274] / [i915#5354]) +7 other tests skip [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html - shard-tglu: NOTRUN -> [SKIP][208] ([fdo#109274]) +1 other test skip [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle: - shard-tglu: NOTRUN -> [SKIP][209] ([i915#4103]) [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-9/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html - shard-dg2: NOTRUN -> [SKIP][210] ([i915#4103] / [i915#4213]) [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html - shard-rkl: NOTRUN -> [SKIP][211] ([i915#4103]) [211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html - shard-dg1: NOTRUN -> [SKIP][212] ([i915#4103] / [i915#4213]) +1 other test skip [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][213] ([i915#9723]) +1 other test skip [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html * igt@kms_dirtyfb@psr-dirtyfb-ioctl: - shard-dg1: NOTRUN -> [SKIP][214] ([i915#9723]) [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-16/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html * igt@kms_display_modes@extended-mode-basic: - shard-dg2: NOTRUN -> [SKIP][215] ([i915#3555]) +6 other tests skip [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@kms_display_modes@extended-mode-basic.html * igt@kms_dp_aux_dev: - shard-dg1: NOTRUN -> [SKIP][216] ([i915#1257]) [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@kms_dp_aux_dev.html * igt@kms_draw_crc@draw-method-mmap-wc: - shard-dg2: NOTRUN -> [SKIP][217] ([i915#8812]) [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@kms_draw_crc@draw-method-mmap-wc.html - shard-dg1: NOTRUN -> [SKIP][218] ([i915#8812]) [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@kms_draw_crc@draw-method-mmap-wc.html * igt@kms_dsc@dsc-basic: - shard-rkl: NOTRUN -> [SKIP][219] ([i915#3555] / [i915#3840]) +1 other test skip [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@kms_dsc@dsc-basic.html - shard-mtlp: NOTRUN -> [SKIP][220] ([i915#3555] / [i915#3840] / [i915#9159]) [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@kms_dsc@dsc-basic.html * igt@kms_dsc@dsc-with-bpc: - shard-tglu: NOTRUN -> [SKIP][221] ([i915#3555] / [i915#3840]) +1 other test skip [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-8/igt@kms_dsc@dsc-with-bpc.html - shard-mtlp: NOTRUN -> [SKIP][222] ([i915#3555] / [i915#3840]) [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@kms_dsc@dsc-with-bpc.html - shard-dg2: NOTRUN -> [SKIP][223] ([i915#3555] / [i915#3840]) [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@kms_dsc@dsc-with-bpc.html - shard-dg1: NOTRUN -> [SKIP][224] ([i915#3555] / [i915#3840]) [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@kms_dsc@dsc-with-bpc.html * igt@kms_dsc@dsc-with-output-formats-with-bpc: - shard-dg2: NOTRUN -> [SKIP][225] ([i915#3840] / [i915#9053]) [225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_dsc@dsc-with-output-formats-with-bpc.html - shard-rkl: NOTRUN -> [SKIP][226] ([i915#3840] / [i915#9053]) [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html - shard-dg1: NOTRUN -> [SKIP][227] ([i915#3840] / [i915#9053]) [227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_dsc@dsc-with-output-formats-with-bpc.html * igt@kms_feature_discovery@display-4x: - shard-rkl: NOTRUN -> [SKIP][228] ([i915#1839]) [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@kms_feature_discovery@display-4x.html - shard-dg1: NOTRUN -> [SKIP][229] ([i915#1839]) [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_feature_discovery@display-4x.html - shard-tglu: NOTRUN -> [SKIP][230] ([i915#1839]) [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-6/igt@kms_feature_discovery@display-4x.html - shard-mtlp: NOTRUN -> [SKIP][231] ([i915#1839]) [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@kms_feature_discovery@display-4x.html - shard-dg2: NOTRUN -> [SKIP][232] ([i915#1839]) [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_feature_discovery@display-4x.html * igt@kms_feature_discovery@dp-mst: - shard-mtlp: NOTRUN -> [SKIP][233] ([i915#9337]) [233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@kms_feature_discovery@dp-mst.html * igt@kms_feature_discovery@psr2: - shard-dg1: NOTRUN -> [SKIP][234] ([i915#658]) [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-17/igt@kms_feature_discovery@psr2.html * igt@kms_fence_pin_leak: - shard-dg1: NOTRUN -> [SKIP][235] ([i915#4881]) [235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@kms_fence_pin_leak.html * igt@kms_flip@2x-flip-vs-fences: - shard-dg1: NOTRUN -> [SKIP][236] ([i915#8381]) [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-13/igt@kms_flip@2x-flip-vs-fences.html - shard-dg2: NOTRUN -> [SKIP][237] ([i915#8381]) [237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-2/igt@kms_flip@2x-flip-vs-fences.html * igt@kms_flip@2x-flip-vs-fences-interruptible: - shard-mtlp: NOTRUN -> [SKIP][238] ([i915#8381]) [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@kms_flip@2x-flip-vs-fences-interruptible.html * igt@kms_flip@2x-flip-vs-rmfb-interruptible: - shard-dg2: NOTRUN -> [SKIP][239] ([fdo#109274] / [fdo#111767]) [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html * igt@kms_flip@2x-flip-vs-suspend: - shard-mtlp: NOTRUN -> [SKIP][240] ([i915#3637]) +10 other tests skip [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@kms_flip@2x-flip-vs-suspend.html * igt@kms_flip@2x-nonexisting-fb-interruptible: - shard-tglu: NOTRUN -> [SKIP][241] ([fdo#109274] / [i915#3637]) +6 other tests skip [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-7/igt@kms_flip@2x-nonexisting-fb-interruptible.html * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset: - shard-dg2: NOTRUN -> [SKIP][242] ([fdo#109274]) +10 other tests skip [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-5/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode: - shard-dg1: NOTRUN -> [SKIP][243] ([i915#2587] / [i915#2672]) +3 other tests skip [243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][244] ([i915#3555] / [i915#8810]) +2 other tests skip [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode: - shard-dg2: NOTRUN -> [SKIP][245] ([i915#2672]) +4 other tests skip [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][246] ([i915#8810]) +1 other test skip [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][247] ([i915#2672]) +4 other tests skip [247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode: - shard-rkl: NOTRUN -> [SKIP][248] ([i915#2672]) +3 other tests skip [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html - shard-tglu: NOTRUN -> [SKIP][249] ([i915#2587] / [i915#2672]) +2 other tests skip [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][250] ([i915#2672] / [i915#3555]) +1 other test skip [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode.html * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt: - shard-mtlp: NOTRUN -> [SKIP][251] ([i915#8708]) +10 other tests skip [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-dg2: NOTRUN -> [FAIL][252] ([i915#6880]) +1 other test fail [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt: - shard-snb: [PASS][253] -> [SKIP][254] ([fdo#109271]) +10 other tests skip [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt.html [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt: - shard-dg1: NOTRUN -> [SKIP][255] ([fdo#111825]) +58 other tests skip [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc: - shard-dg1: NOTRUN -> [SKIP][256] ([i915#8708]) +35 other tests skip [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite: - shard-tglu: NOTRUN -> [SKIP][257] ([fdo#109280]) +39 other tests skip [257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move: - shard-tglu: NOTRUN -> [SKIP][258] ([fdo#110189]) +18 other tests skip [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt: - shard-rkl: NOTRUN -> [SKIP][259] ([fdo#111825]) +14 other tests skip [259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu: - shard-mtlp: NOTRUN -> [SKIP][260] ([i915#1825]) +49 other tests skip [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt: - shard-rkl: NOTRUN -> [SKIP][261] ([fdo#111825] / [i915#1825]) +51 other tests skip [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc: - shard-rkl: NOTRUN -> [SKIP][262] ([i915#3023]) +24 other tests skip [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@plane-fbc-rte: - shard-mtlp: NOTRUN -> [SKIP][263] ([i915#9653]) [263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@kms_frontbuffer_tracking@plane-fbc-rte.html - shard-dg2: NOTRUN -> [SKIP][264] ([i915#9653]) [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@kms_frontbuffer_tracking@plane-fbc-rte.html - shard-rkl: NOTRUN -> [SKIP][265] ([i915#9653]) [265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@kms_frontbuffer_tracking@plane-fbc-rte.html - shard-dg1: NOTRUN -> [SKIP][266] ([i915#9653]) [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@kms_frontbuffer_tracking@plane-fbc-rte.html - shard-tglu: NOTRUN -> [SKIP][267] ([i915#9653]) [267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-8/igt@kms_frontbuffer_tracking@plane-fbc-rte.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff: - shard-dg2: NOTRUN -> [SKIP][268] ([i915#3458]) +18 other tests skip [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt: - shard-dg2: NOTRUN -> [SKIP][269] ([i915#8708]) +31 other tests skip [269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite: - shard-dg1: NOTRUN -> [SKIP][270] ([i915#3458]) +22 other tests skip [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html * igt@kms_hdmi_inject@inject-audio: - shard-dg1: NOTRUN -> [SKIP][271] ([i915#433]) [271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_hdmi_inject@inject-audio.html * igt@kms_hdr@invalid-hdr: - shard-dg2: NOTRUN -> [SKIP][272] ([i915#3555] / [i915#8228]) [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-2/igt@kms_hdr@invalid-hdr.html - shard-dg1: NOTRUN -> [SKIP][273] ([i915#3555] / [i915#8228]) [273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-13/igt@kms_hdr@invalid-hdr.html * igt@kms_hdr@static-toggle: - shard-rkl: NOTRUN -> [SKIP][274] ([i915#3555] / [i915#8228]) [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_hdr@static-toggle.html * igt@kms_invalid_mode@clock-too-high@pipe-a-edp-1: - shard-mtlp: NOTRUN -> [SKIP][275] ([i915#9457]) +3 other tests skip [275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@kms_invalid_mode@clock-too-high@pipe-a-edp-1.html * igt@kms_multipipe_modeset@basic-max-pipe-crc-check: - shard-dg2: NOTRUN -> [SKIP][276] ([i915#4816]) [276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html * igt@kms_panel_fitting@legacy: - shard-dg2: NOTRUN -> [SKIP][277] ([i915#6301]) [277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@kms_panel_fitting@legacy.html - shard-dg1: NOTRUN -> [SKIP][278] ([i915#6301]) [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-12/igt@kms_panel_fitting@legacy.html * igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c: - shard-tglu: NOTRUN -> [SKIP][279] ([fdo#109289]) [279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-2/igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c.html * igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1: - shard-glk: NOTRUN -> [FAIL][280] ([i915#4573]) +1 other test fail [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-glk1/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1.html * igt@kms_plane_lowres@tiling-yf: - shard-rkl: NOTRUN -> [SKIP][281] ([i915#3555]) +5 other tests skip [281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-3/igt@kms_plane_lowres@tiling-yf.html - shard-mtlp: NOTRUN -> [SKIP][282] ([i915#3555] / [i915#8821]) [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@kms_plane_lowres@tiling-yf.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-dp-4: - shard-dg2: NOTRUN -> [SKIP][283] ([i915#9423]) +7 other tests skip [283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-dp-4.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][284] ([i915#9423]) +3 other tests skip [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-1: - shard-glk: NOTRUN -> [SKIP][285] ([fdo#109271]) +234 other tests skip [285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-glk2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-1.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-4: - shard-dg1: NOTRUN -> [SKIP][286] ([i915#9423]) +7 other tests skip [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-4.html * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-edp-1: - shard-mtlp: NOTRUN -> [SKIP][287] ([i915#5176]) +3 other tests skip [287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-edp-1.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][288] ([i915#5235]) +3 other tests skip [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-edp-1: - shard-mtlp: NOTRUN -> [SKIP][289] ([i915#5235]) +2 other tests skip [289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-edp-1.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-edp-1: - shard-mtlp: NOTRUN -> [SKIP][290] ([i915#3555] / [i915#5235]) [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-edp-1.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-3: - shard-dg1: NOTRUN -> [SKIP][291] ([i915#5235]) +11 other tests skip [291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-13/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-3.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][292] ([i915#5235]) +11 other tests skip [292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html * igt@kms_pm_backlight@basic-brightness: - shard-dg1: NOTRUN -> [SKIP][293] ([i915#5354]) +2 other tests skip [293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@kms_pm_backlight@basic-brightness.html * igt@kms_pm_dc@dc3co-vpb-simulation: - shard-rkl: NOTRUN -> [SKIP][294] ([i915#9685]) [294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@kms_pm_dc@dc3co-vpb-simulation.html * igt@kms_pm_dc@dc6-dpms: - shard-rkl: NOTRUN -> [SKIP][295] ([i915#3361]) [295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-1/igt@kms_pm_dc@dc6-dpms.html * igt@kms_pm_lpsp@screens-disabled: - shard-mtlp: NOTRUN -> [SKIP][296] ([i915#8430]) [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@kms_pm_lpsp@screens-disabled.html * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp: - shard-rkl: [PASS][297] -> [SKIP][298] ([i915#9519]) [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-rkl-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html [298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait: - shard-dg1: NOTRUN -> [SKIP][299] ([i915#9519]) [299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-15/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html * igt@kms_pm_rpm@modeset-non-lpsp: - shard-mtlp: NOTRUN -> [SKIP][300] ([i915#9519]) +1 other test skip [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@kms_pm_rpm@modeset-non-lpsp.html * igt@kms_pm_rpm@modeset-non-lpsp-stress: - shard-rkl: NOTRUN -> [SKIP][301] ([i915#9519]) [301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html * igt@kms_pm_rpm@modeset-pc8-residency-stress: - shard-mtlp: NOTRUN -> [SKIP][302] ([fdo#109293]) [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@kms_pm_rpm@modeset-pc8-residency-stress.html * igt@kms_prime@basic-crc-hybrid: - shard-dg2: NOTRUN -> [SKIP][303] ([i915#6524] / [i915#6805]) [303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-1/igt@kms_prime@basic-crc-hybrid.html - shard-dg1: NOTRUN -> [SKIP][304] ([i915#6524]) [304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-13/igt@kms_prime@basic-crc-hybrid.html * igt@kms_psr2_sf@cursor-plane-update-sf: - shard-rkl: NOTRUN -> [SKIP][305] ([fdo#111068] / [i915#9683]) +4 other tests skip [305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_psr2_sf@cursor-plane-update-sf.html * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf: - shard-rkl: NOTRUN -> [SKIP][306] ([i915#9683]) [306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf: - shard-dg2: NOTRUN -> [SKIP][307] ([i915#9683]) +2 other tests skip [307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html - shard-dg1: NOTRUN -> [SKIP][308] ([i915#9683]) [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: - shard-tglu: NOTRUN -> [SKIP][309] ([fdo#111068] / [i915#9683]) +3 other tests skip [309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area: - shard-dg1: NOTRUN -> [SKIP][310] ([fdo#111068] / [i915#9683]) +1 other test skip [310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-17/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-mtlp: NOTRUN -> [SKIP][311] ([i915#4348]) [311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@kms_psr2_su@page_flip-xrgb8888.html - shard-tglu: NOTRUN -> [SKIP][312] ([fdo#109642] / [fdo#111068] / [i915#9683]) +1 other test skip [312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-4/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: - shard-dg1: NOTRUN -> [SKIP][313] ([i915#9685]) [313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-16/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html - shard-dg2: NOTRUN -> [SKIP][314] ([i915#9685]) [314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html * igt@kms_rotation_crc@bad-pixel-format: - shard-dg2: NOTRUN -> [SKIP][315] ([i915#4235]) [315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-2/igt@kms_rotation_crc@bad-pixel-format.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90: - shard-mtlp: NOTRUN -> [SKIP][316] ([i915#4235]) +5 other tests skip [316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html - shard-rkl: NOTRUN -> [INCOMPLETE][317] ([i915#8875] / [i915#9569]) [317]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270: - shard-dg2: NOTRUN -> [SKIP][318] ([i915#4235] / [i915#5190]) [318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html - shard-dg1: NOTRUN -> [SKIP][319] ([fdo#111615] / [i915#5289]) [319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html * igt@kms_scaling_modes@scaling-mode-full-aspect: - shard-tglu: NOTRUN -> [SKIP][320] ([i915#3555]) +7 other tests skip [320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-4/igt@kms_scaling_modes@scaling-mode-full-aspect.html * igt@kms_setmode@basic-clone-single-crtc: - shard-mtlp: NOTRUN -> [SKIP][321] ([i915#3555] / [i915#8809]) [321]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html * igt@kms_setmode@basic@pipe-a-vga-1-pipe-b-hdmi-a-1: - shard-snb: NOTRUN -> [FAIL][322] ([i915#5465]) +3 other tests fail [322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb7/igt@kms_setmode@basic@pipe-a-vga-1-pipe-b-hdmi-a-1.html * igt@kms_setmode@clone-exclusive-crtc: - shard-dg1: NOTRUN -> [SKIP][323] ([i915#3555]) +7 other tests skip [323]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@kms_setmode@clone-exclusive-crtc.html * igt@kms_setmode@invalid-clone-exclusive-crtc: - shard-mtlp: NOTRUN -> [SKIP][324] ([i915#3555] / [i915#8823]) [324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@kms_setmode@invalid-clone-exclusive-crtc.html * igt@kms_tiled_display@basic-test-pattern: - shard-rkl: NOTRUN -> [SKIP][325] ([i915#8623]) [325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-2/igt@kms_tiled_display@basic-test-pattern.html * igt@kms_tv_load_detect@load-detect: - shard-dg2: NOTRUN -> [SKIP][326] ([fdo#109309]) [326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_tv_load_detect@load-detect.html * igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1: - shard-rkl: NOTRUN -> [FAIL][327] ([i915#9196]) [327]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html * igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1: - shard-snb: [PASS][328] -> [FAIL][329] ([i915#9196]) [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-snb2/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html [329]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb6/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html * igt@kms_vrr@flip-dpms: - shard-mtlp: NOTRUN -> [SKIP][330] ([i915#3555] / [i915#8808]) [330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@kms_vrr@flip-dpms.html * igt@kms_writeback@writeback-check-output: - shard-dg1: NOTRUN -> [SKIP][331] ([i915#2437]) [331]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@kms_writeback@writeback-check-output.html * igt@kms_writeback@writeback-check-output-xrgb2101010: - shard-mtlp: NOTRUN -> [SKIP][332] ([i915#2437] / [i915#9412]) [332]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@kms_writeback@writeback-check-output-xrgb2101010.html * igt@kms_writeback@writeback-invalid-parameters: - shard-dg2: NOTRUN -> [SKIP][333] ([i915#2437]) [333]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@kms_writeback@writeback-invalid-parameters.html - shard-rkl: NOTRUN -> [SKIP][334] ([i915#2437]) [334]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-1/igt@kms_writeback@writeback-invalid-parameters.html * igt@kms_writeback@writeback-pixel-formats: - shard-mtlp: NOTRUN -> [SKIP][335] ([i915#2437]) [335]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@kms_writeback@writeback-pixel-formats.html * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-mtlp: NOTRUN -> [SKIP][336] ([fdo#109289]) +6 other tests skip [336]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@perf@gen8-unprivileged-single-ctx-counters.html * igt@perf@non-zero-reason@0-rcs0: - shard-dg2: NOTRUN -> [FAIL][337] ([i915#7484]) [337]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html * igt@perf_pmu@busy-double-start@rcs0: - shard-mtlp: [PASS][338] -> [FAIL][339] ([i915#4349]) [338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-mtlp-2/igt@perf_pmu@busy-double-start@rcs0.html [339]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-8/igt@perf_pmu@busy-double-start@rcs0.html * igt@perf_pmu@event-wait@rcs0: - shard-dg2: NOTRUN -> [SKIP][340] ([fdo#112283]) [340]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@perf_pmu@event-wait@rcs0.html * igt@perf_pmu@rc6-all-gts: - shard-rkl: NOTRUN -> [SKIP][341] ([i915#8516]) [341]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-1/igt@perf_pmu@rc6-all-gts.html * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem: - shard-dg2: NOTRUN -> [INCOMPLETE][342] ([i915#5493]) [342]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-7/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html * igt@prime_udl: - shard-tglu: NOTRUN -> [SKIP][343] ([fdo#109291]) [343]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-6/igt@prime_udl.html - shard-mtlp: NOTRUN -> [SKIP][344] ([fdo#109291]) [344]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@prime_udl.html - shard-dg2: NOTRUN -> [SKIP][345] ([fdo#109291]) [345]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@prime_udl.html - shard-rkl: NOTRUN -> [SKIP][346] ([fdo#109291]) [346]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@prime_udl.html - shard-dg1: NOTRUN -> [SKIP][347] ([fdo#109291]) [347]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-19/igt@prime_udl.html * igt@prime_vgem@basic-fence-flip: - shard-dg1: NOTRUN -> [SKIP][348] ([i915#3708]) +1 other test skip [348]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-15/igt@prime_vgem@basic-fence-flip.html - shard-dg2: NOTRUN -> [SKIP][349] ([i915#3708]) [349]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-6/igt@prime_vgem@basic-fence-flip.html * igt@prime_vgem@basic-fence-read: - shard-dg2: NOTRUN -> [SKIP][350] ([i915#3291] / [i915#3708]) [350]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-2/igt@prime_vgem@basic-fence-read.html * igt@prime_vgem@coherency-gtt: - shard-dg1: NOTRUN -> [SKIP][351] ([i915#3708] / [i915#4077]) [351]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-16/igt@prime_vgem@coherency-gtt.html * igt@prime_vgem@fence-flip-hang: - shard-mtlp: NOTRUN -> [SKIP][352] ([i915#3708]) [352]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-2/igt@prime_vgem@fence-flip-hang.html * igt@syncobj_wait@invalid-wait-zero-handles: - shard-mtlp: NOTRUN -> [FAIL][353] ([i915#9779]) [353]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-3/igt@syncobj_wait@invalid-wait-zero-handles.html * igt@tools_test@sysfs_l3_parity: - shard-dg1: NOTRUN -> [SKIP][354] ([fdo#109307] / [i915#4818]) [354]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@tools_test@sysfs_l3_parity.html * igt@v3d/v3d_job_submission@array-job-submission: - shard-dg2: NOTRUN -> [SKIP][355] ([i915#2575]) +10 other tests skip [355]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-7/igt@v3d/v3d_job_submission@array-job-submission.html * igt@v3d/v3d_submit_cl@bad-extension: - shard-dg1: NOTRUN -> [SKIP][356] ([i915#2575]) +14 other tests skip [356]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-15/igt@v3d/v3d_submit_cl@bad-extension.html * igt@v3d/v3d_submit_cl@bad-multisync-pad: - shard-tglu: NOTRUN -> [SKIP][357] ([fdo#109315] / [i915#2575]) +10 other tests skip [357]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-8/igt@v3d/v3d_submit_cl@bad-multisync-pad.html * igt@v3d/v3d_submit_csd@bad-multisync-extension: - shard-rkl: NOTRUN -> [SKIP][358] ([fdo#109315]) +12 other tests skip [358]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-4/igt@v3d/v3d_submit_csd@bad-multisync-extension.html * igt@v3d/v3d_submit_csd@bad-pad: - shard-mtlp: NOTRUN -> [SKIP][359] ([i915#2575]) +16 other tests skip [359]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-5/igt@v3d/v3d_submit_csd@bad-pad.html * igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done: - shard-tglu: NOTRUN -> [SKIP][360] ([i915#2575]) +8 other tests skip [360]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-7/igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done.html * igt@vc4/vc4_perfmon@create-two-perfmon: - shard-rkl: NOTRUN -> [SKIP][361] ([i915#7711]) +11 other tests skip [361]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@vc4/vc4_perfmon@create-two-perfmon.html * igt@vc4/vc4_perfmon@get-values-invalid-pointer: - shard-mtlp: NOTRUN -> [SKIP][362] ([i915#7711]) +12 other tests skip [362]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-mtlp-1/igt@vc4/vc4_perfmon@get-values-invalid-pointer.html * igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained: - shard-dg2: NOTRUN -> [SKIP][363] ([i915#7711]) +7 other tests skip [363]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-5/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html * igt@vc4/vc4_wait_bo@unused-bo-0ns: - shard-dg1: NOTRUN -> [SKIP][364] ([i915#7711]) +9 other tests skip [364]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-15/igt@vc4/vc4_wait_bo@unused-bo-0ns.html #### Possible fixes #### * igt@gem_exec_fair@basic-deadline: - shard-rkl: [FAIL][365] ([i915#2846]) -> [PASS][366] [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-rkl-7/igt@gem_exec_fair@basic-deadline.html [366]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-5/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_whisper@basic-fds-priority-all: - shard-rkl: [INCOMPLETE][367] -> [PASS][368] [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-rkl-4/igt@gem_exec_whisper@basic-fds-priority-all.html [368]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-1/igt@gem_exec_whisper@basic-fds-priority-all.html * igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0: - shard-dg1: [FAIL][369] ([i915#3591]) -> [PASS][370] +1 other test pass [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html [370]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-snb: [SKIP][371] ([fdo#109271] / [fdo#111767]) -> [PASS][372] [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-snb5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html [372]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb7/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [FAIL][373] ([i915#2346]) -> [PASS][374] [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [374]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite: - shard-snb: [SKIP][375] ([fdo#109271]) -> [PASS][376] +2 other tests pass [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html [376]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html * igt@kms_pm_rpm@dpms-lpsp: - shard-dg2: [SKIP][377] ([i915#9519]) -> [PASS][378] +1 other test pass [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-dg2-2/igt@kms_pm_rpm@dpms-lpsp.html [378]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-dg2-10/igt@kms_pm_rpm@dpms-lpsp.html * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait: - shard-rkl: [SKIP][379] ([i915#9519]) -> [PASS][380] [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html [380]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-7/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html * igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1: - shard-tglu: [FAIL][381] ([i915#9196]) -> [PASS][382] [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-tglu-10/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html [382]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html #### Warnings #### * igt@i915_module_load@reload-no-display: - shard-snb: [INCOMPLETE][383] ([i915#4528]) -> [ABORT][384] ([i915#8668]) [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-snb4/igt@i915_module_load@reload-no-display.html [384]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-snb4/igt@i915_module_load@reload-no-display.html * igt@i915_suspend@basic-s3-without-i915: - shard-tglu: [INCOMPLETE][385] -> [INCOMPLETE][386] ([i915#7443]) [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-tglu-5/igt@i915_suspend@basic-s3-without-i915.html [386]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-tglu-8/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_fbcon_fbt@psr-suspend: - shard-rkl: [SKIP][387] ([i915#3955]) -> [SKIP][388] ([fdo#110189] / [i915#3955]) +1 other test skip [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13988/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html [388]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293 [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023 [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816 [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 [i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465 [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187 [i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228 [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805 [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880 [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173 [i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443 [i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484 [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697 [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701 [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975 [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213 [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228 [i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289 [i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346 [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381 [i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399 [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411 [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414 [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428 [i915#8430]: https://gitlab.freedesktop.org/drm/intel/issues/8430 [i915#8436]: https://gitlab.freedesktop.org/drm/intel/issues/8436 [i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516 [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555 [i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562 [i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708 [i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709 [i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808 [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809 [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810 [i915#8812]: https: == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/index.html [-- Attachment #2: Type: text/html, Size: 124721 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] ✗ CI.xeBAT: failure for RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure (rev4) 2023-12-06 14:44 [igt-dev] [PATCH v4 0/2] RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure Bommu Krishnaiah ` (4 preceding siblings ...) 2023-12-06 19:09 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork @ 2023-12-06 19:20 ` Patchwork 5 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2023-12-06 19:20 UTC (permalink / raw) To: Bommu, Krishnaiah; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 7018 bytes --] == Series Details == Series: RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure (rev4) URL : https://patchwork.freedesktop.org/series/127364/ State : failure == Summary == CI Bug Log - changes from XEIGT_7625_BAT -> XEIGTPW_10354_BAT ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with XEIGTPW_10354_BAT absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in XEIGTPW_10354_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (4 -> 4) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in XEIGTPW_10354_BAT: ### IGT changes ### #### Possible regressions #### * igt@xe_evict@evict-beng-mixed-threads-small-multi-vm: - bat-pvc-2: [PASS][1] -> [TIMEOUT][2] +2 other tests timeout [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-pvc-2/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-pvc-2/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html - bat-dg2-oem2: [PASS][3] -> [TIMEOUT][4] +2 other tests timeout [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-dg2-oem2/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-dg2-oem2/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html * igt@xe_evict@evict-mixed-threads-small: - bat-atsm-2: [PASS][5] -> [TIMEOUT][6] +2 other tests timeout [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-atsm-2/igt@xe_evict@evict-mixed-threads-small.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-atsm-2/igt@xe_evict@evict-mixed-threads-small.html * igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate: - bat-pvc-2: [PASS][7] -> [FAIL][8] +25 other tests fail [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-pvc-2/igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate.html [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-pvc-2/igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate.html * igt@xe_exec_compute_mode@twice-preempt-fence-early: - bat-adlp-7: [PASS][9] -> [FAIL][10] +17 other tests fail [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-adlp-7/igt@xe_exec_compute_mode@twice-preempt-fence-early.html [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-adlp-7/igt@xe_exec_compute_mode@twice-preempt-fence-early.html * igt@xe_exec_compute_mode@twice-userptr-invalidate: - bat-atsm-2: [PASS][11] -> [FAIL][12] +30 other tests fail [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-atsm-2/igt@xe_exec_compute_mode@twice-userptr-invalidate.html [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-atsm-2/igt@xe_exec_compute_mode@twice-userptr-invalidate.html * igt@xe_live_ktest@dmabuf: - bat-pvc-2: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-pvc-2/igt@xe_live_ktest@dmabuf.html [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-pvc-2/igt@xe_live_ktest@dmabuf.html * igt@xe_waitfence@engine: - bat-dg2-oem2: [PASS][15] -> [FAIL][16] +29 other tests fail [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-dg2-oem2/igt@xe_waitfence@engine.html [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-dg2-oem2/igt@xe_waitfence@engine.html #### Warnings #### * igt@xe_evict@evict-beng-small-cm: - bat-pvc-2: [DMESG-FAIL][17] ([Intel XE#482]) -> [FAIL][18] +3 other tests fail [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-pvc-2/igt@xe_evict@evict-beng-small-cm.html [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-pvc-2/igt@xe_evict@evict-beng-small-cm.html Known issues ------------ Here are the changes found in XEIGTPW_10354_BAT that come from known issues: ### IGT changes ### #### Issues hit #### * igt@xe_create@create-execqueues-noleak: - bat-adlp-7: [PASS][19] -> [FAIL][20] ([Intel XE#524]) [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-adlp-7/igt@xe_create@create-execqueues-noleak.html [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-adlp-7/igt@xe_create@create-execqueues-noleak.html * igt@xe_exec_reset@cm-close-fd-no-exec: - bat-pvc-2: [PASS][21] -> [FAIL][22] ([Intel XE#818]) [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-pvc-2/igt@xe_exec_reset@cm-close-fd-no-exec.html [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-pvc-2/igt@xe_exec_reset@cm-close-fd-no-exec.html - bat-adlp-7: [PASS][23] -> [FAIL][24] ([Intel XE#818]) [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-adlp-7/igt@xe_exec_reset@cm-close-fd-no-exec.html [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-adlp-7/igt@xe_exec_reset@cm-close-fd-no-exec.html - bat-dg2-oem2: [PASS][25] -> [FAIL][26] ([Intel XE#818]) [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-dg2-oem2/igt@xe_exec_reset@cm-close-fd-no-exec.html [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-dg2-oem2/igt@xe_exec_reset@cm-close-fd-no-exec.html #### Possible fixes #### * igt@kms_flip@basic-flip-vs-wf_vblank: - bat-adlp-7: [FAIL][27] ([Intel XE#480]) -> [PASS][28] +2 other tests pass [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7625/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank.html [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank.html [Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480 [Intel XE#482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/482 [Intel XE#524]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/524 [Intel XE#818]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/818 Build changes ------------- * IGT: IGT_7625 -> IGTPW_10354 * Linux: xe-554-9d76164e08c68a3d5d081ff7b07c15a2cadf741a -> xe-555-42c08951a31c679822795d72ada017e004d89102 IGTPW_10354: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10354/index.html IGT_7625: f40c67d84e142095ac6215be154e1f3710f26cba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-554-9d76164e08c68a3d5d081ff7b07c15a2cadf741a: 9d76164e08c68a3d5d081ff7b07c15a2cadf741a xe-555-42c08951a31c679822795d72ada017e004d89102: 42c08951a31c679822795d72ada017e004d89102 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10354/index.html [-- Attachment #2: Type: text/html, Size: 8085 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-12-06 19:20 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-12-06 14:44 [igt-dev] [PATCH v4 0/2] RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure Bommu Krishnaiah 2023-12-06 14:44 ` [igt-dev] [PATCH v4 1/2] " Bommu Krishnaiah 2023-12-06 17:04 ` Rodrigo Vivi 2023-12-06 17:23 ` Bommu, Krishnaiah 2023-12-06 17:36 ` Rodrigo Vivi 2023-12-06 14:44 ` [igt-dev] [PATCH v4 1/1] drm-uapi/xe: kill xe_wait_user_fence_ioctl when exec_queue reset happen Bommu Krishnaiah 2023-12-06 17:06 ` Rodrigo Vivi 2023-12-06 14:44 ` [igt-dev] [PATCH v4 2/2] " Bommu Krishnaiah 2023-12-06 17:08 ` Rodrigo Vivi 2023-12-06 17:25 ` [igt-dev] ✓ Fi.CI.BAT: success for RFC: drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure (rev4) Patchwork 2023-12-06 19:09 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 2023-12-06 19:20 ` [igt-dev] ✗ CI.xeBAT: " Patchwork
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