* [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners
@ 2024-07-25 18:45 Matthew Brost
2024-07-25 20:40 ` ✓ CI.xeBAT: success for tests/intel/xe_vm: Add test for 64k page corners (rev3) Patchwork
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Matthew Brost @ 2024-07-25 18:45 UTC (permalink / raw)
To: igt-dev; +Cc: zbigniew.kempczynski
Add sections which splits 64k pages in 4k pages or splits compact 64k in
64k pages.
v2:
- Use SZ_* (Zbigniew)
- Remove clock block (Zbigniew)
- Update commit message / comments
v3:
- Send correct version
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
tests/intel/xe_vm.c | 125 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
index a4f6c7a0b4..f41c6aca53 100644
--- a/tests/intel/xe_vm.c
+++ b/tests/intel/xe_vm.c
@@ -366,6 +366,125 @@ static void userptr_invalid(int fd)
xe_vm_destroy(fd, vm);
}
+/**
+ * SUBTEST: compact-64k-pages
+ * Description:
+ * Take corner cases related to compact and 64k pages
+ * Functionality: bind
+ * Test category: functionality test
+ */
+static void compact_64k_pages(int fd, struct drm_xe_engine_class_instance *eci)
+{
+ size_t page_size = xe_get_default_alignment(fd);
+ uint64_t addr0 = 0x10000000ull, addr1;
+ uint32_t vm;
+ uint32_t bo0, bo1;
+ uint32_t exec_queue;
+ void *ptr0, *ptr1;
+ struct drm_xe_sync sync[2] = {
+ { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
+ .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
+ .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
+ };
+ struct {
+ uint32_t batch[16];
+ uint64_t pad;
+ uint32_t data;
+ } *data = NULL;
+ struct drm_xe_exec exec = {
+ .num_batch_buffer = 1,
+ .num_syncs = 2,
+ .syncs = to_user_pointer(sync),
+ };
+ uint64_t batch_offset;
+ uint64_t batch_addr;
+ uint64_t sdi_offset;
+ uint64_t sdi_addr;
+ int b = 0;
+
+ vm = xe_vm_create(fd, 0, 0);
+ exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
+
+ bo0 = xe_bo_create(fd, vm, SZ_8M,
+ vram_if_possible(fd, eci->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+ ptr0 = xe_bo_map(fd, bo0, SZ_8M);
+
+ bo1 = xe_bo_create(fd, vm, SZ_8M / 2,
+ vram_if_possible(fd, eci->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+ ptr1 = xe_bo_map(fd, bo1, SZ_8M / 2);
+
+ sync[0].handle = syncobj_create(fd, 0);
+ if (page_size == SZ_4K) {
+ /* Setup mapping to split a 64k PTE in cache */
+ xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_64K, 0, 0);
+
+ addr1 = addr0 + (SZ_64K / 2);
+ xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_64K / 2,
+ sync, 1);
+ } else if (page_size == SZ_64K) {
+ addr0 += page_size;
+
+ /* Setup mapping to split compact 64k pages */
+ xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_8M, 0, 0);
+
+ addr1 = addr0 + (SZ_8M / 4);
+ xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_8M / 2,
+ sync, 1);
+ }
+ igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+ /* Verify 1st and 2nd mappings working */
+ batch_offset = (char *)&data[0].batch - (char *)data;
+ batch_addr = addr0 + batch_offset;
+ sdi_offset = (char *)&data[0].data - (char *)data;
+ sdi_addr = addr0 + sdi_offset;
+ data = ptr0;
+
+ data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+ data[0].batch[b++] = sdi_addr;
+ data[0].batch[b++] = sdi_addr >> 32;
+ data[0].batch[b++] = 0xc0ffee;
+
+ sdi_addr = addr1 + sdi_offset;
+ data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+ data[0].batch[b++] = sdi_addr;
+ data[0].batch[b++] = sdi_addr >> 32;
+ data[0].batch[b++] = 0xc0ffee;
+
+ data[0].batch[b++] = MI_BATCH_BUFFER_END;
+ igt_assert(b <= ARRAY_SIZE(data[0].batch));
+
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].handle = syncobj_create(fd, 0);
+ exec.exec_queue_id = exec_queue;
+ exec.address = batch_addr;
+ xe_exec(fd, &exec);
+
+ igt_assert(syncobj_wait(fd, &sync[1].handle, 1, INT64_MAX, 0,
+ NULL));
+ igt_assert_eq(data[0].data, 0xc0ffee);
+ data = ptr1;
+ igt_assert_eq(data[0].data, 0xc0ffee);
+
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+ syncobj_reset(fd, &sync[0].handle, 1);
+ xe_vm_unbind_all_async(fd, vm, 0, bo0, 0, 0);
+ xe_vm_unbind_all_async(fd, vm, 0, bo1, sync, 1);
+ igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+ xe_exec_queue_destroy(fd, exec_queue);
+ syncobj_destroy(fd, sync[0].handle);
+ syncobj_destroy(fd, sync[1].handle);
+ munmap(ptr0, SZ_8M);
+ munmap(ptr1, SZ_8M / 2);
+ gem_close(fd, bo0);
+ gem_close(fd, bo1);
+ xe_vm_destroy(fd, vm);
+}
+
/**
* SUBTEST: shared-%s-page
* Description: Test shared arg[1] page
@@ -1973,6 +2092,12 @@ igt_main
igt_subtest("bind-flag-invalid")
bind_flag_invalid(fd);
+ igt_subtest("compact-64k-pages")
+ xe_for_each_engine(fd, hwe) {
+ compact_64k_pages(fd, hwe);
+ break;
+ }
+
igt_subtest("shared-pte-page")
xe_for_each_engine(fd, hwe)
shared_pte_page(fd, hwe, 4,
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ CI.xeBAT: success for tests/intel/xe_vm: Add test for 64k page corners (rev3)
2024-07-25 18:45 [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners Matthew Brost
@ 2024-07-25 20:40 ` Patchwork
2024-07-25 20:49 ` ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2024-07-25 20:40 UTC (permalink / raw)
To: Matthew Brost; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 1079 bytes --]
== Series Details ==
Series: tests/intel/xe_vm: Add test for 64k page corners (rev3)
URL : https://patchwork.freedesktop.org/series/136299/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7937_BAT -> XEIGTPW_11467_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_7937 -> IGTPW_11467
* Linux: xe-1664-724a2a53988a57709d7f9dcd5c58dd5737d45cb2 -> xe-1667-9f8e597a1c39d7e316f9479e6f627c15dbc58e1d
IGTPW_11467: 11467
IGT_7937: eba69333dfe8c295d053997367e395d7bde2b4b4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-1664-724a2a53988a57709d7f9dcd5c58dd5737d45cb2: 724a2a53988a57709d7f9dcd5c58dd5737d45cb2
xe-1667-9f8e597a1c39d7e316f9479e6f627c15dbc58e1d: 9f8e597a1c39d7e316f9479e6f627c15dbc58e1d
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/index.html
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^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for tests/intel/xe_vm: Add test for 64k page corners (rev3)
2024-07-25 18:45 [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners Matthew Brost
2024-07-25 20:40 ` ✓ CI.xeBAT: success for tests/intel/xe_vm: Add test for 64k page corners (rev3) Patchwork
@ 2024-07-25 20:49 ` Patchwork
2024-07-26 4:20 ` ✗ CI.xeFULL: " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2024-07-25 20:49 UTC (permalink / raw)
To: Matthew Brost; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 2787 bytes --]
== Series Details ==
Series: tests/intel/xe_vm: Add test for 64k page corners (rev3)
URL : https://patchwork.freedesktop.org/series/136299/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15132 -> IGTPW_11467
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_11467 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_11467, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11467/index.html
Participating hosts (41 -> 39)
------------------------------
Additional (1): fi-cfl-8109u
Missing (3): bat-arls-2 fi-snb-2520m fi-bsw-n3050
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_11467:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@slpc:
- bat-arls-5: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15132/bat-arls-5/igt@i915_selftest@live@slpc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11467/bat-arls-5/igt@i915_selftest@live@slpc.html
Known issues
------------
Here are the changes found in IGTPW_11467 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11467/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11467/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html
* igt@kms_pm_backlight@basic-brightness:
- fi-cfl-8109u: NOTRUN -> [SKIP][5] +11 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11467/fi-cfl-8109u/igt@kms_pm_backlight@basic-brightness.html
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7937 -> IGTPW_11467
CI-20190529: 20190529
CI_DRM_15132: 9f8e597a1c39d7e316f9479e6f627c15dbc58e1d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_11467: 11467
IGT_7937: eba69333dfe8c295d053997367e395d7bde2b4b4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11467/index.html
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^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ CI.xeFULL: failure for tests/intel/xe_vm: Add test for 64k page corners (rev3)
2024-07-25 18:45 [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners Matthew Brost
2024-07-25 20:40 ` ✓ CI.xeBAT: success for tests/intel/xe_vm: Add test for 64k page corners (rev3) Patchwork
2024-07-25 20:49 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2024-07-26 4:20 ` Patchwork
2024-07-26 9:04 ` [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners Zbigniew Kempczyński
2024-07-26 17:03 ` Kamil Konieczny
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2024-07-26 4:20 UTC (permalink / raw)
To: Matthew Brost; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 50793 bytes --]
== Series Details ==
Series: tests/intel/xe_vm: Add test for 64k page corners (rev3)
URL : https://patchwork.freedesktop.org/series/136299/
State : failure
== Summary ==
CI Bug Log - changes from XEIGT_7937_full -> XEIGTPW_11467_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with XEIGTPW_11467_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in XEIGTPW_11467_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (3 -> 3)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in XEIGTPW_11467_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pm_rpm@legacy-planes-dpms@plane-68:
- shard-dg2-set2: [PASS][1] -> [INCOMPLETE][2] +3 other tests incomplete
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_pm_rpm@legacy-planes-dpms@plane-68.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_pm_rpm@legacy-planes-dpms@plane-68.html
* igt@xe_exec_basic@many-bindexecqueue-rebind:
- shard-lnl: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-3/igt@xe_exec_basic@many-bindexecqueue-rebind.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-3/igt@xe_exec_basic@many-bindexecqueue-rebind.html
New tests
---------
New tests have been introduced between XEIGT_7937_full and XEIGTPW_11467_full:
### New IGT tests (1) ###
* igt@xe_vm@compact-64k-pages:
- Statuses : 2 pass(s)
- Exec time: [0.00, 0.01] s
Known issues
------------
Here are the changes found in XEIGTPW_11467_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-lnl: [PASS][5] -> [FAIL][6] ([Intel XE#1659])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][7] ([Intel XE#1201] / [Intel XE#316])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-436/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
- shard-lnl: NOTRUN -> [SKIP][8] ([Intel XE#1407])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-2/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-lnl: NOTRUN -> [SKIP][9] ([Intel XE#1477])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-6/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-lnl: NOTRUN -> [SKIP][10] ([Intel XE#1124]) +3 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-8/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][11] ([Intel XE#1124] / [Intel XE#1201]) +1 other test skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-435/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][12] ([Intel XE#1399]) +3 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-3/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][13] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][14] ([Intel XE#1201] / [Intel XE#787]) +6 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_chamelium_color@ctm-blue-to-red:
- shard-lnl: NOTRUN -> [SKIP][15] ([Intel XE#306])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-1/igt@kms_chamelium_color@ctm-blue-to-red.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-dg2-set2: NOTRUN -> [SKIP][16] ([Intel XE#1201] / [Intel XE#373])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-466/igt@kms_chamelium_frames@hdmi-frame-dump.html
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#373]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-3/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-lnl: NOTRUN -> [SKIP][18] ([Intel XE#1413])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-8/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-lnl: NOTRUN -> [SKIP][19] ([Intel XE#1424])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-8/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-lnl: NOTRUN -> [SKIP][20] ([Intel XE#309])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-lnl: NOTRUN -> [SKIP][21] ([Intel XE#323])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@torture-bo@pipe-b:
- shard-dg2-set2: [PASS][22] -> [DMESG-WARN][23] ([Intel XE#877]) +1 other test dmesg-warn
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-434/igt@kms_cursor_legacy@torture-bo@pipe-b.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-464/igt@kms_cursor_legacy@torture-bo@pipe-b.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-lnl: NOTRUN -> [SKIP][24] ([Intel XE#1401] / [Intel XE#1745])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][25] ([Intel XE#1401])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling:
- shard-lnl: NOTRUN -> [SKIP][26] ([Intel XE#1397] / [Intel XE#1745])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][27] ([Intel XE#1397])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][28] ([Intel XE#656]) +8 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-rgb565-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][29] ([Intel XE#1201] / [Intel XE#651]) +2 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw:
- shard-lnl: NOTRUN -> [SKIP][30] ([Intel XE#651]) +3 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
- shard-dg2-set2: NOTRUN -> [SKIP][31] ([Intel XE#1201] / [Intel XE#653]) +4 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6:
- shard-dg2-set2: [PASS][32] -> [FAIL][33] ([Intel XE#361])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-463/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#498]) +3 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-4/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-a-edp-1.html
* igt@kms_pm_backlight@fade:
- shard-lnl: [PASS][35] -> [SKIP][36] ([Intel XE#870])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-1/igt@kms_pm_backlight@fade.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-3/igt@kms_pm_backlight@fade.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][37] ([Intel XE#1201] / [Intel XE#1489]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-lnl: NOTRUN -> [SKIP][38] ([Intel XE#1128])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-8/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@pr-sprite-blt:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#1406])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-5/igt@kms_psr@pr-sprite-blt.html
* igt@kms_psr@psr-sprite-plane-onoff:
- shard-dg2-set2: NOTRUN -> [SKIP][40] ([Intel XE#929]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_psr@psr-sprite-plane-onoff.html
* igt@kms_psr@psr2-cursor-blt@edp-1:
- shard-lnl: [PASS][41] -> [FAIL][42] ([Intel XE#1649]) +1 other test fail
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-8/igt@kms_psr@psr2-cursor-blt@edp-1.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-4/igt@kms_psr@psr2-cursor-blt@edp-1.html
* igt@xe_compute@ccs-mode-compute-kernel:
- shard-dg2-set2: NOTRUN -> [FAIL][43] ([Intel XE#1050])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-435/igt@xe_compute@ccs-mode-compute-kernel.html
- shard-lnl: NOTRUN -> [SKIP][44] ([Intel XE#1447])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-4/igt@xe_compute@ccs-mode-compute-kernel.html
* igt@xe_evict@evict-beng-cm-threads-large:
- shard-dg2-set2: [PASS][45] -> [INCOMPLETE][46] ([Intel XE#1195] / [Intel XE#1473] / [Intel XE#392]) +1 other test incomplete
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@xe_evict@evict-beng-cm-threads-large.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@xe_evict@evict-beng-cm-threads-large.html
* igt@xe_evict@evict-beng-cm-threads-small-multi-vm:
- shard-lnl: NOTRUN -> [SKIP][47] ([Intel XE#688]) +3 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-1/igt@xe_evict@evict-beng-cm-threads-small-multi-vm.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-dg2-set2: [PASS][48] -> [TIMEOUT][49] ([Intel XE#1473] / [Intel XE#402])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-466/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_evict@evict-threads-large:
- shard-dg2-set2: [PASS][50] -> [TIMEOUT][51] ([Intel XE#1473] / [Intel XE#392])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-435/igt@xe_evict@evict-threads-large.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@xe_evict@evict-threads-large.html
* igt@xe_exec_basic@multigpu-no-exec-userptr:
- shard-lnl: NOTRUN -> [SKIP][52] ([Intel XE#1392]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-4/igt@xe_exec_basic@multigpu-no-exec-userptr.html
* igt@xe_exec_fault_mode@many-execqueues-userptr-rebind-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][53] ([Intel XE#1201] / [Intel XE#288])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@xe_exec_fault_mode@many-execqueues-userptr-rebind-imm.html
* igt@xe_live_ktest@xe_dma_buf:
- shard-dg2-set2: [PASS][54] -> [SKIP][55] ([Intel XE#1192] / [Intel XE#1201])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@xe_live_ktest@xe_dma_buf.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-463/igt@xe_live_ktest@xe_dma_buf.html
* igt@xe_module_load@many-reload:
- shard-dg2-set2: [PASS][56] -> [FAIL][57] ([Intel XE#2136])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@xe_module_load@many-reload.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@xe_module_load@many-reload.html
* igt@xe_pm@s3-vm-bind-userptr:
- shard-dg2-set2: [PASS][58] -> [DMESG-WARN][59] ([Intel XE#1551] / [Intel XE#569])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@xe_pm@s3-vm-bind-userptr.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@xe_pm@s3-vm-bind-userptr.html
* igt@xe_pm@s4-exec-after:
- shard-lnl: [PASS][60] -> [ABORT][61] ([Intel XE#1358] / [Intel XE#1607])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-7/igt@xe_pm@s4-exec-after.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-2/igt@xe_pm@s4-exec-after.html
* igt@xe_pm@s4-multiple-execs:
- shard-dg2-set2: [PASS][62] -> [DMESG-WARN][63] ([Intel XE#2019]) +1 other test dmesg-warn
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-466/igt@xe_pm@s4-multiple-execs.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-463/igt@xe_pm@s4-multiple-execs.html
* igt@xe_pm@s4-vm-bind-userptr:
- shard-dg2-set2: [PASS][64] -> [DMESG-WARN][65] ([Intel XE#2280])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-464/igt@xe_pm@s4-vm-bind-userptr.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-466/igt@xe_pm@s4-vm-bind-userptr.html
#### Possible fixes ####
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear:
- shard-lnl: [FAIL][66] ([Intel XE#911]) -> [PASS][67] +3 other tests pass
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1:
- shard-lnl: [FAIL][68] ([Intel XE#1426]) -> [PASS][69] +3 other tests pass
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-dg2-set2: [DMESG-WARN][70] -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-434/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-lnl: [FAIL][72] ([Intel XE#1659]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_plane@plane-position-covered:
- shard-lnl: [DMESG-WARN][74] ([Intel XE#324]) -> [PASS][75] +3 other tests pass
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-5/igt@kms_plane@plane-position-covered.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-1/igt@kms_plane@plane-position-covered.html
* igt@kms_pm_backlight@bad-brightness:
- shard-lnl: [SKIP][76] ([Intel XE#870]) -> [PASS][77] +1 other test pass
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-5/igt@kms_pm_backlight@bad-brightness.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-7/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-dg2-set2: [FAIL][78] ([Intel XE#771] / [Intel XE#899]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-464/igt@kms_universal_plane@cursor-fb-leak.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-435/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-6:
- shard-dg2-set2: [FAIL][80] ([Intel XE#899]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-464/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-6.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-435/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-6.html
* igt@xe_pm@s2idle-d3hot-basic-exec:
- shard-dg2-set2: [INCOMPLETE][82] ([Intel XE#1195] / [Intel XE#1358]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-436/igt@xe_pm@s2idle-d3hot-basic-exec.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-463/igt@xe_pm@s2idle-d3hot-basic-exec.html
* igt@xe_pm@s3-d3hot-basic-exec:
- shard-dg2-set2: [DMESG-WARN][84] ([Intel XE#1551] / [Intel XE#569]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@xe_pm@s3-d3hot-basic-exec.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-464/igt@xe_pm@s3-d3hot-basic-exec.html
* igt@xe_pm@s4-mocs:
- shard-dg2-set2: [DMESG-WARN][86] ([Intel XE#2280]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-466/igt@xe_pm@s4-mocs.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-466/igt@xe_pm@s4-mocs.html
* igt@xe_pm@s4-vm-bind-unbind-all:
- shard-lnl: [ABORT][88] ([Intel XE#1794]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-5/igt@xe_pm@s4-vm-bind-unbind-all.html
#### Warnings ####
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-dg2-set2: [SKIP][90] ([Intel XE#316]) -> [SKIP][91] ([Intel XE#1201] / [Intel XE#316]) +3 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-434/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-dg2-set2: [SKIP][92] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][93] ([Intel XE#316])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@kms_big_fb@linear-16bpp-rotate-270.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-dg2-set2: [SKIP][94] ([Intel XE#1201] / [Intel XE#610]) -> [SKIP][95] ([Intel XE#610])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-dg2-set2: [SKIP][96] ([Intel XE#1124]) -> [SKIP][97] ([Intel XE#1124] / [Intel XE#1201]) +9 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-464/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-dg2-set2: [SKIP][98] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][99] ([Intel XE#1124]) +4 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_bw@linear-tiling-1-displays-1920x1080p:
- shard-dg2-set2: [SKIP][100] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][101] ([Intel XE#367]) +2 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-435/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-2-displays-1920x1080p:
- shard-dg2-set2: [SKIP][102] ([Intel XE#367]) -> [SKIP][103] ([Intel XE#1201] / [Intel XE#367]) +1 other test skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-464/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6:
- shard-dg2-set2: [SKIP][104] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][105] ([Intel XE#787]) +41 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-436/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html
* igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
- shard-dg2-set2: [SKIP][106] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][107] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +15 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-435/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs:
- shard-dg2-set2: [SKIP][108] ([Intel XE#1252]) -> [SKIP][109] ([Intel XE#1201] / [Intel XE#1252]) +2 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-435/igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: [SKIP][110] ([Intel XE#787]) -> [SKIP][111] ([Intel XE#1201] / [Intel XE#787]) +55 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-6.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-466/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
- shard-dg2-set2: [SKIP][112] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][113] ([Intel XE#455] / [Intel XE#787]) +11 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
- shard-dg2-set2: [SKIP][114] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][115] ([Intel XE#373]) +3 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
- shard-dg2-set2: [SKIP][116] ([Intel XE#373]) -> [SKIP][117] ([Intel XE#1201] / [Intel XE#373]) +9 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg2-set2: [SKIP][118] ([Intel XE#307]) -> [SKIP][119] ([Intel XE#1201] / [Intel XE#307]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_content_protection@dp-mst-type-0.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2-set2: [SKIP][120] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][121] ([Intel XE#308])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-434/igt@kms_cursor_crc@cursor-onscreen-512x170.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg2-set2: [SKIP][122] ([Intel XE#308]) -> [SKIP][123] ([Intel XE#1201] / [Intel XE#308])
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_cursor_crc@cursor-sliding-512x512.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-435/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2-set2: [SKIP][124] ([Intel XE#323]) -> [SKIP][125] ([Intel XE#1201] / [Intel XE#323])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-436/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2-set2: [SKIP][126] ([Intel XE#455]) -> [SKIP][127] ([Intel XE#1201] / [Intel XE#455]) +10 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_dsc@dsc-with-bpc-formats.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-434/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg2-set2: [SKIP][128] ([Intel XE#1137] / [Intel XE#1201]) -> [SKIP][129] ([Intel XE#1137])
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@kms_feature_discovery@dp-mst.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_feature_discovery@dp-mst.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][130] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][131] ([Intel XE#651]) +14 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
- shard-dg2-set2: [SKIP][132] ([Intel XE#651]) -> [SKIP][133] ([Intel XE#1201] / [Intel XE#651]) +24 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
- shard-dg2-set2: [SKIP][134] ([Intel XE#653]) -> [SKIP][135] ([Intel XE#1201] / [Intel XE#653]) +26 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][136] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][137] ([Intel XE#653]) +14 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2-set2: [SKIP][138] ([Intel XE#658]) -> [SKIP][139] ([Intel XE#1201] / [Intel XE#658])
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_hdmi_inject@inject-audio:
- shard-dg2-set2: [SKIP][140] ([Intel XE#1201] / [Intel XE#417]) -> [SKIP][141] ([Intel XE#417])
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-434/igt@kms_hdmi_inject@inject-audio.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_plane@plane-position-hole:
- shard-lnl: [DMESG-WARN][142] ([Intel XE#324]) -> [DMESG-FAIL][143] ([Intel XE#324])
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-lnl-3/igt@kms_plane@plane-position-hole.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-lnl-5/igt@kms_plane@plane-position-hole.html
* igt@kms_plane_multiple@tiling-y:
- shard-dg2-set2: [SKIP][144] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][145] ([Intel XE#455]) +11 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-435/igt@kms_plane_multiple@tiling-y.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_plane_multiple@tiling-y.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
- shard-dg2-set2: [SKIP][146] ([Intel XE#2318] / [Intel XE#455]) -> [SKIP][147] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455])
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-463/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6:
- shard-dg2-set2: [SKIP][148] ([Intel XE#2318]) -> [SKIP][149] ([Intel XE#1201] / [Intel XE#2318]) +2 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-463/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2-set2: [SKIP][150] ([Intel XE#1122]) -> [SKIP][151] ([Intel XE#1122] / [Intel XE#1201]) +1 other test skip
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_pm_dc@dc3co-vpb-simulation.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg2-set2: [SKIP][152] ([Intel XE#908]) -> [SKIP][153] ([Intel XE#1201] / [Intel XE#908])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_pm_dc@dc6-dpms.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-464/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg2-set2: [SKIP][154] ([Intel XE#1129]) -> [SKIP][155] ([Intel XE#1129] / [Intel XE#1201])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_pm_dc@dc6-psr.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@kms_pm_dc@dc6-psr.html
* igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-fully-sf:
- shard-dg2-set2: [SKIP][156] ([Intel XE#1489]) -> [SKIP][157] ([Intel XE#1201] / [Intel XE#1489]) +2 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-fully-sf.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-434/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-dg2-set2: [SKIP][158] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][159] ([Intel XE#1489])
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-464/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr@fbc-pr-sprite-plane-onoff:
- shard-dg2-set2: [SKIP][160] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][161] ([Intel XE#929]) +5 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-435/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
* igt@kms_psr@fbc-psr2-primary-render:
- shard-dg2-set2: [SKIP][162] ([Intel XE#929]) -> [SKIP][163] ([Intel XE#1201] / [Intel XE#929]) +10 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_psr@fbc-psr2-primary-render.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-433/igt@kms_psr@fbc-psr2-primary-render.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-dg2-set2: [SKIP][164] ([Intel XE#1127] / [Intel XE#1201]) -> [SKIP][165] ([Intel XE#1127])
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2-set2: [SKIP][166] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][167] ([Intel XE#327])
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2-set2: [SKIP][168] ([Intel XE#327]) -> [SKIP][169] ([Intel XE#1201] / [Intel XE#327]) +1 other test skip
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-466/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2-set2: [FAIL][170] ([Intel XE#1729]) -> [SKIP][171] ([Intel XE#1201] / [Intel XE#362])
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-436/igt@kms_tiled_display@basic-test-pattern.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: [SKIP][172] ([Intel XE#1500]) -> [SKIP][173] ([Intel XE#1201] / [Intel XE#1500])
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vblank@ts-continuation-suspend:
- shard-dg2-set2: [DMESG-WARN][174] ([Intel XE#2019]) -> [DMESG-WARN][175] ([Intel XE#2019] / [Intel XE#2226]) +1 other test dmesg-warn
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_vblank@ts-continuation-suspend.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-466/igt@kms_vblank@ts-continuation-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-dg2-set2: [SKIP][176] ([Intel XE#756]) -> [SKIP][177] ([Intel XE#1201] / [Intel XE#756])
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@kms_writeback@writeback-check-output.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-466/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2-set2: [SKIP][178] ([Intel XE#1201] / [Intel XE#756]) -> [SKIP][179] ([Intel XE#756])
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-463/igt@kms_writeback@writeback-check-output-xrgb2101010.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute:
- shard-dg2-set2: [SKIP][180] ([Intel XE#1201] / [Intel XE#1280] / [Intel XE#455]) -> [SKIP][181] ([Intel XE#1280] / [Intel XE#455]) +3 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-464/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html
* igt@xe_copy_basic@mem-set-linear-0x3fff:
- shard-dg2-set2: [SKIP][182] ([Intel XE#1126]) -> [SKIP][183] ([Intel XE#1126] / [Intel XE#1201]) +1 other test skip
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@xe_copy_basic@mem-set-linear-0x3fff.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-436/igt@xe_copy_basic@mem-set-linear-0x3fff.html
* igt@xe_evict@evict-beng-mixed-threads-large:
- shard-dg2-set2: [INCOMPLETE][184] ([Intel XE#1473] / [Intel XE#392]) -> [INCOMPLETE][185] ([Intel XE#1195] / [Intel XE#1473] / [Intel XE#392])
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@xe_evict@evict-beng-mixed-threads-large.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-434/igt@xe_evict@evict-beng-mixed-threads-large.html
* igt@xe_exec_fault_mode@many-execqueues-basic-prefetch:
- shard-dg2-set2: [SKIP][186] ([Intel XE#288]) -> [SKIP][187] ([Intel XE#1201] / [Intel XE#288]) +21 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@xe_exec_fault_mode@many-execqueues-basic-prefetch.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-463/igt@xe_exec_fault_mode@many-execqueues-basic-prefetch.html
* igt@xe_exec_fault_mode@once-userptr-invalidate-race-imm:
- shard-dg2-set2: [SKIP][188] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][189] ([Intel XE#288]) +14 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-463/igt@xe_exec_fault_mode@once-userptr-invalidate-race-imm.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@xe_exec_fault_mode@once-userptr-invalidate-race-imm.html
* igt@xe_module_load@force-load:
- shard-dg2-set2: [SKIP][190] ([Intel XE#1201] / [Intel XE#378]) -> [SKIP][191] ([Intel XE#378])
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-433/igt@xe_module_load@force-load.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@xe_module_load@force-load.html
* igt@xe_pm@d3cold-mmap-vram:
- shard-dg2-set2: [SKIP][192] ([Intel XE#366]) -> [SKIP][193] ([Intel XE#1201] / [Intel XE#366])
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-432/igt@xe_pm@d3cold-mmap-vram.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-466/igt@xe_pm@d3cold-mmap-vram.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-dg2-set2: [DMESG-WARN][194] ([Intel XE#1162] / [Intel XE#1941]) -> [DMESG-WARN][195] ([Intel XE#1162])
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-435/igt@xe_pm@s3-vm-bind-unbind-all.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-435/igt@xe_pm@s3-vm-bind-unbind-all.html
* igt@xe_query@multigpu-query-invalid-size:
- shard-dg2-set2: [SKIP][196] ([Intel XE#1201] / [Intel XE#944]) -> [SKIP][197] ([Intel XE#944])
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7937/shard-dg2-434/igt@xe_query@multigpu-query-invalid-size.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/shard-dg2-432/igt@xe_query@multigpu-query-invalid-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1050
[Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
[Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
[Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
[Intel XE#1162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1162
[Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
[Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
[Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
[Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252
[Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
[Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1413
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
[Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
[Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
[Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1551]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1551
[Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
[Intel XE#1649]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1649
[Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#1941]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1941
[Intel XE#2019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2019
[Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2207]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2207
[Intel XE#2226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2226
[Intel XE#2280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2280
[Intel XE#2318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2318
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
[Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
[Intel XE#361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/361
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/392
[Intel XE#402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/402
[Intel XE#417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/417
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498
[Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
[Intel XE#771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/771
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
[Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
[Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
[Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_7937 -> IGTPW_11467
* Linux: xe-1664-724a2a53988a57709d7f9dcd5c58dd5737d45cb2 -> xe-1667-9f8e597a1c39d7e316f9479e6f627c15dbc58e1d
IGTPW_11467: 11467
IGT_7937: eba69333dfe8c295d053997367e395d7bde2b4b4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-1664-724a2a53988a57709d7f9dcd5c58dd5737d45cb2: 724a2a53988a57709d7f9dcd5c58dd5737d45cb2
xe-1667-9f8e597a1c39d7e316f9479e6f627c15dbc58e1d: 9f8e597a1c39d7e316f9479e6f627c15dbc58e1d
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11467/index.html
[-- Attachment #2: Type: text/html, Size: 65473 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners
2024-07-25 18:45 [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners Matthew Brost
` (2 preceding siblings ...)
2024-07-26 4:20 ` ✗ CI.xeFULL: " Patchwork
@ 2024-07-26 9:04 ` Zbigniew Kempczyński
2024-07-26 12:16 ` Matthew Brost
2024-07-26 17:03 ` Kamil Konieczny
4 siblings, 1 reply; 9+ messages in thread
From: Zbigniew Kempczyński @ 2024-07-26 9:04 UTC (permalink / raw)
To: Matthew Brost; +Cc: igt-dev
On Thu, Jul 25, 2024 at 11:45:38AM -0700, Matthew Brost wrote:
> Add sections which splits 64k pages in 4k pages or splits compact 64k in
> 64k pages.
>
> v2:
> - Use SZ_* (Zbigniew)
> - Remove clock block (Zbigniew)
> - Update commit message / comments
> v3:
> - Send correct version
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> tests/intel/xe_vm.c | 125 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 125 insertions(+)
>
> diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
> index a4f6c7a0b4..f41c6aca53 100644
> --- a/tests/intel/xe_vm.c
> +++ b/tests/intel/xe_vm.c
> @@ -366,6 +366,125 @@ static void userptr_invalid(int fd)
> xe_vm_destroy(fd, vm);
> }
>
> +/**
> + * SUBTEST: compact-64k-pages
> + * Description:
> + * Take corner cases related to compact and 64k pages
> + * Functionality: bind
> + * Test category: functionality test
> + */
> +static void compact_64k_pages(int fd, struct drm_xe_engine_class_instance *eci)
> +{
> + size_t page_size = xe_get_default_alignment(fd);
> + uint64_t addr0 = 0x10000000ull, addr1;
> + uint32_t vm;
> + uint32_t bo0, bo1;
> + uint32_t exec_queue;
> + void *ptr0, *ptr1;
> + struct drm_xe_sync sync[2] = {
> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> + .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> + .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> + };
> + struct {
> + uint32_t batch[16];
> + uint64_t pad;
> + uint32_t data;
> + } *data = NULL;
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 2,
> + .syncs = to_user_pointer(sync),
> + };
> + uint64_t batch_offset;
> + uint64_t batch_addr;
> + uint64_t sdi_offset;
> + uint64_t sdi_addr;
> + int b = 0;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
> +
> + bo0 = xe_bo_create(fd, vm, SZ_8M,
> + vram_if_possible(fd, eci->gt_id),
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + ptr0 = xe_bo_map(fd, bo0, SZ_8M);
> +
> + bo1 = xe_bo_create(fd, vm, SZ_8M / 2,
> + vram_if_possible(fd, eci->gt_id),
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + ptr1 = xe_bo_map(fd, bo1, SZ_8M / 2);
> +
> + sync[0].handle = syncobj_create(fd, 0);
> + if (page_size == SZ_4K) {
> + /* Setup mapping to split a 64k PTE in cache */
> + xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_64K, 0, 0);
> +
> + addr1 = addr0 + (SZ_64K / 2);
> + xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_64K / 2,
> + sync, 1);
> + } else if (page_size == SZ_64K) {
> + addr0 += page_size;
> +
> + /* Setup mapping to split compact 64k pages */
> + xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_8M, 0, 0);
> +
> + addr1 = addr0 + (SZ_8M / 4);
> + xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_8M / 2,
> + sync, 1);
> + }
> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + /* Verify 1st and 2nd mappings working */
> + batch_offset = (char *)&data[0].batch - (char *)data;
> + batch_addr = addr0 + batch_offset;
> + sdi_offset = (char *)&data[0].data - (char *)data;
> + sdi_addr = addr0 + sdi_offset;
> + data = ptr0;
> +
> + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> + data[0].batch[b++] = sdi_addr;
> + data[0].batch[b++] = sdi_addr >> 32;
> + data[0].batch[b++] = 0xc0ffee;
> +
> + sdi_addr = addr1 + sdi_offset;
> + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> + data[0].batch[b++] = sdi_addr;
> + data[0].batch[b++] = sdi_addr >> 32;
> + data[0].batch[b++] = 0xc0ffee;
> +
> + data[0].batch[b++] = MI_BATCH_BUFFER_END;
> + igt_assert(b <= ARRAY_SIZE(data[0].batch));
> +
> + sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> + sync[1].handle = syncobj_create(fd, 0);
> + exec.exec_queue_id = exec_queue;
> + exec.address = batch_addr;
> + xe_exec(fd, &exec);
> +
> + igt_assert(syncobj_wait(fd, &sync[1].handle, 1, INT64_MAX, 0,
> + NULL));
This will fit in same line ase syncobj_wait() below.
> + igt_assert_eq(data[0].data, 0xc0ffee);
> + data = ptr1;
> + igt_assert_eq(data[0].data, 0xc0ffee);
> +
> + sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + syncobj_reset(fd, &sync[0].handle, 1);
> + xe_vm_unbind_all_async(fd, vm, 0, bo0, 0, 0);
> + xe_vm_unbind_all_async(fd, vm, 0, bo1, sync, 1);
> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + xe_exec_queue_destroy(fd, exec_queue);
> + syncobj_destroy(fd, sync[0].handle);
> + syncobj_destroy(fd, sync[1].handle);
> + munmap(ptr0, SZ_8M);
> + munmap(ptr1, SZ_8M / 2);
> + gem_close(fd, bo0);
> + gem_close(fd, bo1);
> + xe_vm_destroy(fd, vm);
> +}
> +
> /**
> * SUBTEST: shared-%s-page
> * Description: Test shared arg[1] page
> @@ -1973,6 +2092,12 @@ igt_main
> igt_subtest("bind-flag-invalid")
> bind_flag_invalid(fd);
>
> + igt_subtest("compact-64k-pages")
> + xe_for_each_engine(fd, hwe) {
> + compact_64k_pages(fd, hwe);
> + break;
> + }
> +
> igt_subtest("shared-pte-page")
> xe_for_each_engine(fd, hwe)
> shared_pte_page(fd, hwe, 4,
> --
> 2.34.1
>
Regardless addressing nit above:
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
--
Zbigniew
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners
2024-07-26 9:04 ` [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners Zbigniew Kempczyński
@ 2024-07-26 12:16 ` Matthew Brost
2024-07-26 19:13 ` Zbigniew Kempczyński
0 siblings, 1 reply; 9+ messages in thread
From: Matthew Brost @ 2024-07-26 12:16 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Fri, Jul 26, 2024 at 11:04:25AM +0200, Zbigniew Kempczyński wrote:
> On Thu, Jul 25, 2024 at 11:45:38AM -0700, Matthew Brost wrote:
> > Add sections which splits 64k pages in 4k pages or splits compact 64k in
> > 64k pages.
> >
> > v2:
> > - Use SZ_* (Zbigniew)
> > - Remove clock block (Zbigniew)
> > - Update commit message / comments
> > v3:
> > - Send correct version
> >
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > tests/intel/xe_vm.c | 125 ++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 125 insertions(+)
> >
> > diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
> > index a4f6c7a0b4..f41c6aca53 100644
> > --- a/tests/intel/xe_vm.c
> > +++ b/tests/intel/xe_vm.c
> > @@ -366,6 +366,125 @@ static void userptr_invalid(int fd)
> > xe_vm_destroy(fd, vm);
> > }
> >
> > +/**
> > + * SUBTEST: compact-64k-pages
> > + * Description:
> > + * Take corner cases related to compact and 64k pages
> > + * Functionality: bind
> > + * Test category: functionality test
> > + */
> > +static void compact_64k_pages(int fd, struct drm_xe_engine_class_instance *eci)
> > +{
> > + size_t page_size = xe_get_default_alignment(fd);
> > + uint64_t addr0 = 0x10000000ull, addr1;
> > + uint32_t vm;
> > + uint32_t bo0, bo1;
> > + uint32_t exec_queue;
> > + void *ptr0, *ptr1;
> > + struct drm_xe_sync sync[2] = {
> > + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> > + .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> > + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> > + .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> > + };
> > + struct {
> > + uint32_t batch[16];
> > + uint64_t pad;
> > + uint32_t data;
> > + } *data = NULL;
> > + struct drm_xe_exec exec = {
> > + .num_batch_buffer = 1,
> > + .num_syncs = 2,
> > + .syncs = to_user_pointer(sync),
> > + };
> > + uint64_t batch_offset;
> > + uint64_t batch_addr;
> > + uint64_t sdi_offset;
> > + uint64_t sdi_addr;
> > + int b = 0;
> > +
> > + vm = xe_vm_create(fd, 0, 0);
> > + exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
> > +
> > + bo0 = xe_bo_create(fd, vm, SZ_8M,
> > + vram_if_possible(fd, eci->gt_id),
> > + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> > + ptr0 = xe_bo_map(fd, bo0, SZ_8M);
> > +
> > + bo1 = xe_bo_create(fd, vm, SZ_8M / 2,
> > + vram_if_possible(fd, eci->gt_id),
> > + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> > + ptr1 = xe_bo_map(fd, bo1, SZ_8M / 2);
> > +
> > + sync[0].handle = syncobj_create(fd, 0);
> > + if (page_size == SZ_4K) {
> > + /* Setup mapping to split a 64k PTE in cache */
> > + xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_64K, 0, 0);
> > +
> > + addr1 = addr0 + (SZ_64K / 2);
> > + xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_64K / 2,
> > + sync, 1);
> > + } else if (page_size == SZ_64K) {
> > + addr0 += page_size;
> > +
> > + /* Setup mapping to split compact 64k pages */
> > + xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_8M, 0, 0);
> > +
> > + addr1 = addr0 + (SZ_8M / 4);
> > + xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_8M / 2,
> > + sync, 1);
> > + }
> > + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> > +
> > + /* Verify 1st and 2nd mappings working */
> > + batch_offset = (char *)&data[0].batch - (char *)data;
> > + batch_addr = addr0 + batch_offset;
> > + sdi_offset = (char *)&data[0].data - (char *)data;
> > + sdi_addr = addr0 + sdi_offset;
> > + data = ptr0;
> > +
> > + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> > + data[0].batch[b++] = sdi_addr;
> > + data[0].batch[b++] = sdi_addr >> 32;
> > + data[0].batch[b++] = 0xc0ffee;
> > +
> > + sdi_addr = addr1 + sdi_offset;
> > + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> > + data[0].batch[b++] = sdi_addr;
> > + data[0].batch[b++] = sdi_addr >> 32;
> > + data[0].batch[b++] = 0xc0ffee;
> > +
> > + data[0].batch[b++] = MI_BATCH_BUFFER_END;
> > + igt_assert(b <= ARRAY_SIZE(data[0].batch));
> > +
> > + sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> > + sync[1].handle = syncobj_create(fd, 0);
> > + exec.exec_queue_id = exec_queue;
> > + exec.address = batch_addr;
> > + xe_exec(fd, &exec);
> > +
> > + igt_assert(syncobj_wait(fd, &sync[1].handle, 1, INT64_MAX, 0,
> > + NULL));
>
> This will fit in same line ase syncobj_wait() below.
>
No, you need to wait here the exec to signal before checking the data
and unbinding.
> > + igt_assert_eq(data[0].data, 0xc0ffee);
> > + data = ptr1;
> > + igt_assert_eq(data[0].data, 0xc0ffee);
> > +
> > + sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> > + syncobj_reset(fd, &sync[0].handle, 1);
> > + xe_vm_unbind_all_async(fd, vm, 0, bo0, 0, 0);
> > + xe_vm_unbind_all_async(fd, vm, 0, bo1, sync, 1);
> > + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
This waits on the unbinds.
> > +
> > + xe_exec_queue_destroy(fd, exec_queue);
> > + syncobj_destroy(fd, sync[0].handle);
> > + syncobj_destroy(fd, sync[1].handle);
> > + munmap(ptr0, SZ_8M);
> > + munmap(ptr1, SZ_8M / 2);
> > + gem_close(fd, bo0);
> > + gem_close(fd, bo1);
> > + xe_vm_destroy(fd, vm);
> > +}
> > +
> > /**
> > * SUBTEST: shared-%s-page
> > * Description: Test shared arg[1] page
> > @@ -1973,6 +2092,12 @@ igt_main
> > igt_subtest("bind-flag-invalid")
> > bind_flag_invalid(fd);
> >
> > + igt_subtest("compact-64k-pages")
> > + xe_for_each_engine(fd, hwe) {
> > + compact_64k_pages(fd, hwe);
> > + break;
> > + }
> > +
> > igt_subtest("shared-pte-page")
> > xe_for_each_engine(fd, hwe)
> > shared_pte_page(fd, hwe, 4,
> > --
> > 2.34.1
> >
>
> Regardless addressing nit above:
>
> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>
Thanks.
Matt
> --
> Zbigniew
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners
2024-07-25 18:45 [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners Matthew Brost
` (3 preceding siblings ...)
2024-07-26 9:04 ` [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners Zbigniew Kempczyński
@ 2024-07-26 17:03 ` Kamil Konieczny
2024-07-26 17:39 ` Matthew Brost
4 siblings, 1 reply; 9+ messages in thread
From: Kamil Konieczny @ 2024-07-26 17:03 UTC (permalink / raw)
To: igt-dev; +Cc: Matthew Brost, zbigniew.kempczynski
Hi Matthew,
On 2024-07-25 at 11:45:38 -0700, Matthew Brost wrote:
> Add sections which splits 64k pages in 4k pages or splits compact 64k in
Should this be s/splits compact 64k/compact 4k/ ?
Regards,
Kamil
> 64k pages.
>
> v2:
> - Use SZ_* (Zbigniew)
> - Remove clock block (Zbigniew)
> - Update commit message / comments
> v3:
> - Send correct version
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> tests/intel/xe_vm.c | 125 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 125 insertions(+)
>
> diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
> index a4f6c7a0b4..f41c6aca53 100644
> --- a/tests/intel/xe_vm.c
> +++ b/tests/intel/xe_vm.c
> @@ -366,6 +366,125 @@ static void userptr_invalid(int fd)
> xe_vm_destroy(fd, vm);
> }
>
> +/**
> + * SUBTEST: compact-64k-pages
> + * Description:
> + * Take corner cases related to compact and 64k pages
> + * Functionality: bind
> + * Test category: functionality test
> + */
> +static void compact_64k_pages(int fd, struct drm_xe_engine_class_instance *eci)
> +{
> + size_t page_size = xe_get_default_alignment(fd);
> + uint64_t addr0 = 0x10000000ull, addr1;
> + uint32_t vm;
> + uint32_t bo0, bo1;
> + uint32_t exec_queue;
> + void *ptr0, *ptr1;
> + struct drm_xe_sync sync[2] = {
> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> + .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> + .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> + };
> + struct {
> + uint32_t batch[16];
> + uint64_t pad;
> + uint32_t data;
> + } *data = NULL;
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 2,
> + .syncs = to_user_pointer(sync),
> + };
> + uint64_t batch_offset;
> + uint64_t batch_addr;
> + uint64_t sdi_offset;
> + uint64_t sdi_addr;
> + int b = 0;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
> +
> + bo0 = xe_bo_create(fd, vm, SZ_8M,
> + vram_if_possible(fd, eci->gt_id),
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + ptr0 = xe_bo_map(fd, bo0, SZ_8M);
> +
> + bo1 = xe_bo_create(fd, vm, SZ_8M / 2,
> + vram_if_possible(fd, eci->gt_id),
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + ptr1 = xe_bo_map(fd, bo1, SZ_8M / 2);
> +
> + sync[0].handle = syncobj_create(fd, 0);
> + if (page_size == SZ_4K) {
> + /* Setup mapping to split a 64k PTE in cache */
> + xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_64K, 0, 0);
> +
> + addr1 = addr0 + (SZ_64K / 2);
> + xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_64K / 2,
> + sync, 1);
> + } else if (page_size == SZ_64K) {
> + addr0 += page_size;
> +
> + /* Setup mapping to split compact 64k pages */
> + xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_8M, 0, 0);
> +
> + addr1 = addr0 + (SZ_8M / 4);
> + xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_8M / 2,
> + sync, 1);
> + }
> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + /* Verify 1st and 2nd mappings working */
> + batch_offset = (char *)&data[0].batch - (char *)data;
> + batch_addr = addr0 + batch_offset;
> + sdi_offset = (char *)&data[0].data - (char *)data;
> + sdi_addr = addr0 + sdi_offset;
> + data = ptr0;
> +
> + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> + data[0].batch[b++] = sdi_addr;
> + data[0].batch[b++] = sdi_addr >> 32;
> + data[0].batch[b++] = 0xc0ffee;
> +
> + sdi_addr = addr1 + sdi_offset;
> + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> + data[0].batch[b++] = sdi_addr;
> + data[0].batch[b++] = sdi_addr >> 32;
> + data[0].batch[b++] = 0xc0ffee;
> +
> + data[0].batch[b++] = MI_BATCH_BUFFER_END;
> + igt_assert(b <= ARRAY_SIZE(data[0].batch));
> +
> + sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> + sync[1].handle = syncobj_create(fd, 0);
> + exec.exec_queue_id = exec_queue;
> + exec.address = batch_addr;
> + xe_exec(fd, &exec);
> +
> + igt_assert(syncobj_wait(fd, &sync[1].handle, 1, INT64_MAX, 0,
> + NULL));
> + igt_assert_eq(data[0].data, 0xc0ffee);
> + data = ptr1;
> + igt_assert_eq(data[0].data, 0xc0ffee);
> +
> + sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + syncobj_reset(fd, &sync[0].handle, 1);
> + xe_vm_unbind_all_async(fd, vm, 0, bo0, 0, 0);
> + xe_vm_unbind_all_async(fd, vm, 0, bo1, sync, 1);
> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> + xe_exec_queue_destroy(fd, exec_queue);
> + syncobj_destroy(fd, sync[0].handle);
> + syncobj_destroy(fd, sync[1].handle);
> + munmap(ptr0, SZ_8M);
> + munmap(ptr1, SZ_8M / 2);
> + gem_close(fd, bo0);
> + gem_close(fd, bo1);
> + xe_vm_destroy(fd, vm);
> +}
> +
> /**
> * SUBTEST: shared-%s-page
> * Description: Test shared arg[1] page
> @@ -1973,6 +2092,12 @@ igt_main
> igt_subtest("bind-flag-invalid")
> bind_flag_invalid(fd);
>
> + igt_subtest("compact-64k-pages")
> + xe_for_each_engine(fd, hwe) {
> + compact_64k_pages(fd, hwe);
> + break;
> + }
> +
> igt_subtest("shared-pte-page")
> xe_for_each_engine(fd, hwe)
> shared_pte_page(fd, hwe, 4,
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners
2024-07-26 17:03 ` Kamil Konieczny
@ 2024-07-26 17:39 ` Matthew Brost
0 siblings, 0 replies; 9+ messages in thread
From: Matthew Brost @ 2024-07-26 17:39 UTC (permalink / raw)
To: Kamil Konieczny; +Cc: igt-dev, zbigniew.kempczynski
On Fri, Jul 26, 2024 at 07:03:03PM +0200, Kamil Konieczny wrote:
> Hi Matthew,
> On 2024-07-25 at 11:45:38 -0700, Matthew Brost wrote:
> > Add sections which splits 64k pages in 4k pages or splits compact 64k in
>
> Should this be s/splits compact 64k/compact 4k/ ?
No. A compact 64k page != 64k pages. Also compact 4k pages is not a thing.
Matt
>
> Regards,
> Kamil
>
> > 64k pages.
> >
> > v2:
> > - Use SZ_* (Zbigniew)
> > - Remove clock block (Zbigniew)
> > - Update commit message / comments
> > v3:
> > - Send correct version
> >
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > tests/intel/xe_vm.c | 125 ++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 125 insertions(+)
> >
> > diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
> > index a4f6c7a0b4..f41c6aca53 100644
> > --- a/tests/intel/xe_vm.c
> > +++ b/tests/intel/xe_vm.c
> > @@ -366,6 +366,125 @@ static void userptr_invalid(int fd)
> > xe_vm_destroy(fd, vm);
> > }
> >
> > +/**
> > + * SUBTEST: compact-64k-pages
> > + * Description:
> > + * Take corner cases related to compact and 64k pages
> > + * Functionality: bind
> > + * Test category: functionality test
> > + */
> > +static void compact_64k_pages(int fd, struct drm_xe_engine_class_instance *eci)
> > +{
> > + size_t page_size = xe_get_default_alignment(fd);
> > + uint64_t addr0 = 0x10000000ull, addr1;
> > + uint32_t vm;
> > + uint32_t bo0, bo1;
> > + uint32_t exec_queue;
> > + void *ptr0, *ptr1;
> > + struct drm_xe_sync sync[2] = {
> > + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> > + .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> > + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> > + .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> > + };
> > + struct {
> > + uint32_t batch[16];
> > + uint64_t pad;
> > + uint32_t data;
> > + } *data = NULL;
> > + struct drm_xe_exec exec = {
> > + .num_batch_buffer = 1,
> > + .num_syncs = 2,
> > + .syncs = to_user_pointer(sync),
> > + };
> > + uint64_t batch_offset;
> > + uint64_t batch_addr;
> > + uint64_t sdi_offset;
> > + uint64_t sdi_addr;
> > + int b = 0;
> > +
> > + vm = xe_vm_create(fd, 0, 0);
> > + exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
> > +
> > + bo0 = xe_bo_create(fd, vm, SZ_8M,
> > + vram_if_possible(fd, eci->gt_id),
> > + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> > + ptr0 = xe_bo_map(fd, bo0, SZ_8M);
> > +
> > + bo1 = xe_bo_create(fd, vm, SZ_8M / 2,
> > + vram_if_possible(fd, eci->gt_id),
> > + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> > + ptr1 = xe_bo_map(fd, bo1, SZ_8M / 2);
> > +
> > + sync[0].handle = syncobj_create(fd, 0);
> > + if (page_size == SZ_4K) {
> > + /* Setup mapping to split a 64k PTE in cache */
> > + xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_64K, 0, 0);
> > +
> > + addr1 = addr0 + (SZ_64K / 2);
> > + xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_64K / 2,
> > + sync, 1);
> > + } else if (page_size == SZ_64K) {
> > + addr0 += page_size;
> > +
> > + /* Setup mapping to split compact 64k pages */
> > + xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_8M, 0, 0);
> > +
> > + addr1 = addr0 + (SZ_8M / 4);
> > + xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_8M / 2,
> > + sync, 1);
> > + }
> > + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> > +
> > + /* Verify 1st and 2nd mappings working */
> > + batch_offset = (char *)&data[0].batch - (char *)data;
> > + batch_addr = addr0 + batch_offset;
> > + sdi_offset = (char *)&data[0].data - (char *)data;
> > + sdi_addr = addr0 + sdi_offset;
> > + data = ptr0;
> > +
> > + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> > + data[0].batch[b++] = sdi_addr;
> > + data[0].batch[b++] = sdi_addr >> 32;
> > + data[0].batch[b++] = 0xc0ffee;
> > +
> > + sdi_addr = addr1 + sdi_offset;
> > + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> > + data[0].batch[b++] = sdi_addr;
> > + data[0].batch[b++] = sdi_addr >> 32;
> > + data[0].batch[b++] = 0xc0ffee;
> > +
> > + data[0].batch[b++] = MI_BATCH_BUFFER_END;
> > + igt_assert(b <= ARRAY_SIZE(data[0].batch));
> > +
> > + sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> > + sync[1].handle = syncobj_create(fd, 0);
> > + exec.exec_queue_id = exec_queue;
> > + exec.address = batch_addr;
> > + xe_exec(fd, &exec);
> > +
> > + igt_assert(syncobj_wait(fd, &sync[1].handle, 1, INT64_MAX, 0,
> > + NULL));
> > + igt_assert_eq(data[0].data, 0xc0ffee);
> > + data = ptr1;
> > + igt_assert_eq(data[0].data, 0xc0ffee);
> > +
> > + sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> > + syncobj_reset(fd, &sync[0].handle, 1);
> > + xe_vm_unbind_all_async(fd, vm, 0, bo0, 0, 0);
> > + xe_vm_unbind_all_async(fd, vm, 0, bo1, sync, 1);
> > + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> > +
> > + xe_exec_queue_destroy(fd, exec_queue);
> > + syncobj_destroy(fd, sync[0].handle);
> > + syncobj_destroy(fd, sync[1].handle);
> > + munmap(ptr0, SZ_8M);
> > + munmap(ptr1, SZ_8M / 2);
> > + gem_close(fd, bo0);
> > + gem_close(fd, bo1);
> > + xe_vm_destroy(fd, vm);
> > +}
> > +
> > /**
> > * SUBTEST: shared-%s-page
> > * Description: Test shared arg[1] page
> > @@ -1973,6 +2092,12 @@ igt_main
> > igt_subtest("bind-flag-invalid")
> > bind_flag_invalid(fd);
> >
> > + igt_subtest("compact-64k-pages")
> > + xe_for_each_engine(fd, hwe) {
> > + compact_64k_pages(fd, hwe);
> > + break;
> > + }
> > +
> > igt_subtest("shared-pte-page")
> > xe_for_each_engine(fd, hwe)
> > shared_pte_page(fd, hwe, 4,
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners
2024-07-26 12:16 ` Matthew Brost
@ 2024-07-26 19:13 ` Zbigniew Kempczyński
0 siblings, 0 replies; 9+ messages in thread
From: Zbigniew Kempczyński @ 2024-07-26 19:13 UTC (permalink / raw)
To: Matthew Brost; +Cc: igt-dev
On Fri, Jul 26, 2024 at 12:16:59PM +0000, Matthew Brost wrote:
> On Fri, Jul 26, 2024 at 11:04:25AM +0200, Zbigniew Kempczyński wrote:
> > On Thu, Jul 25, 2024 at 11:45:38AM -0700, Matthew Brost wrote:
> > > Add sections which splits 64k pages in 4k pages or splits compact 64k in
> > > 64k pages.
> > >
> > > v2:
> > > - Use SZ_* (Zbigniew)
> > > - Remove clock block (Zbigniew)
> > > - Update commit message / comments
> > > v3:
> > > - Send correct version
> > >
> > > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > ---
> > > tests/intel/xe_vm.c | 125 ++++++++++++++++++++++++++++++++++++++++++++
> > > 1 file changed, 125 insertions(+)
> > >
> > > diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
> > > index a4f6c7a0b4..f41c6aca53 100644
> > > --- a/tests/intel/xe_vm.c
> > > +++ b/tests/intel/xe_vm.c
> > > @@ -366,6 +366,125 @@ static void userptr_invalid(int fd)
> > > xe_vm_destroy(fd, vm);
> > > }
> > >
> > > +/**
> > > + * SUBTEST: compact-64k-pages
> > > + * Description:
> > > + * Take corner cases related to compact and 64k pages
> > > + * Functionality: bind
> > > + * Test category: functionality test
> > > + */
> > > +static void compact_64k_pages(int fd, struct drm_xe_engine_class_instance *eci)
> > > +{
> > > + size_t page_size = xe_get_default_alignment(fd);
> > > + uint64_t addr0 = 0x10000000ull, addr1;
> > > + uint32_t vm;
> > > + uint32_t bo0, bo1;
> > > + uint32_t exec_queue;
> > > + void *ptr0, *ptr1;
> > > + struct drm_xe_sync sync[2] = {
> > > + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> > > + .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> > > + { .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
> > > + .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> > > + };
> > > + struct {
> > > + uint32_t batch[16];
> > > + uint64_t pad;
> > > + uint32_t data;
> > > + } *data = NULL;
> > > + struct drm_xe_exec exec = {
> > > + .num_batch_buffer = 1,
> > > + .num_syncs = 2,
> > > + .syncs = to_user_pointer(sync),
> > > + };
> > > + uint64_t batch_offset;
> > > + uint64_t batch_addr;
> > > + uint64_t sdi_offset;
> > > + uint64_t sdi_addr;
> > > + int b = 0;
> > > +
> > > + vm = xe_vm_create(fd, 0, 0);
> > > + exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
> > > +
> > > + bo0 = xe_bo_create(fd, vm, SZ_8M,
> > > + vram_if_possible(fd, eci->gt_id),
> > > + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> > > + ptr0 = xe_bo_map(fd, bo0, SZ_8M);
> > > +
> > > + bo1 = xe_bo_create(fd, vm, SZ_8M / 2,
> > > + vram_if_possible(fd, eci->gt_id),
> > > + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> > > + ptr1 = xe_bo_map(fd, bo1, SZ_8M / 2);
> > > +
> > > + sync[0].handle = syncobj_create(fd, 0);
> > > + if (page_size == SZ_4K) {
> > > + /* Setup mapping to split a 64k PTE in cache */
> > > + xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_64K, 0, 0);
> > > +
> > > + addr1 = addr0 + (SZ_64K / 2);
> > > + xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_64K / 2,
> > > + sync, 1);
> > > + } else if (page_size == SZ_64K) {
> > > + addr0 += page_size;
> > > +
> > > + /* Setup mapping to split compact 64k pages */
> > > + xe_vm_bind_async(fd, vm, 0, bo0, 0, addr0, SZ_8M, 0, 0);
> > > +
> > > + addr1 = addr0 + (SZ_8M / 4);
> > > + xe_vm_bind_async(fd, vm, 0, bo1, 0, addr1, SZ_8M / 2,
> > > + sync, 1);
> > > + }
> > > + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
> > > +
> > > + /* Verify 1st and 2nd mappings working */
> > > + batch_offset = (char *)&data[0].batch - (char *)data;
> > > + batch_addr = addr0 + batch_offset;
> > > + sdi_offset = (char *)&data[0].data - (char *)data;
> > > + sdi_addr = addr0 + sdi_offset;
> > > + data = ptr0;
> > > +
> > > + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> > > + data[0].batch[b++] = sdi_addr;
> > > + data[0].batch[b++] = sdi_addr >> 32;
> > > + data[0].batch[b++] = 0xc0ffee;
> > > +
> > > + sdi_addr = addr1 + sdi_offset;
> > > + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> > > + data[0].batch[b++] = sdi_addr;
> > > + data[0].batch[b++] = sdi_addr >> 32;
> > > + data[0].batch[b++] = 0xc0ffee;
> > > +
> > > + data[0].batch[b++] = MI_BATCH_BUFFER_END;
> > > + igt_assert(b <= ARRAY_SIZE(data[0].batch));
> > > +
> > > + sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> > > + sync[1].handle = syncobj_create(fd, 0);
> > > + exec.exec_queue_id = exec_queue;
> > > + exec.address = batch_addr;
> > > + xe_exec(fd, &exec);
> > > +
> > > + igt_assert(syncobj_wait(fd, &sync[1].handle, 1, INT64_MAX, 0,
> > > + NULL));
> >
> > This will fit in same line ase syncobj_wait() below.
> >
>
> No, you need to wait here the exec to signal before checking the data
> and unbinding.
I meant code style, not functionality (NULL may be in same line).
igt_assert(syncobj_wait(fd, &sync[1].handle, 1, INT64_MAX, 0, NULL));
--
Zbigniew
>
>
> > > + igt_assert_eq(data[0].data, 0xc0ffee);
> > > + data = ptr1;
> > > + igt_assert_eq(data[0].data, 0xc0ffee);
> > > +
> > > + sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> > > + syncobj_reset(fd, &sync[0].handle, 1);
> > > + xe_vm_unbind_all_async(fd, vm, 0, bo0, 0, 0);
> > > + xe_vm_unbind_all_async(fd, vm, 0, bo1, sync, 1);
> > > + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
>
> This waits on the unbinds.
>
> > > +
> > > + xe_exec_queue_destroy(fd, exec_queue);
> > > + syncobj_destroy(fd, sync[0].handle);
> > > + syncobj_destroy(fd, sync[1].handle);
> > > + munmap(ptr0, SZ_8M);
> > > + munmap(ptr1, SZ_8M / 2);
> > > + gem_close(fd, bo0);
> > > + gem_close(fd, bo1);
> > > + xe_vm_destroy(fd, vm);
> > > +}
> > > +
> > > /**
> > > * SUBTEST: shared-%s-page
> > > * Description: Test shared arg[1] page
> > > @@ -1973,6 +2092,12 @@ igt_main
> > > igt_subtest("bind-flag-invalid")
> > > bind_flag_invalid(fd);
> > >
> > > + igt_subtest("compact-64k-pages")
> > > + xe_for_each_engine(fd, hwe) {
> > > + compact_64k_pages(fd, hwe);
> > > + break;
> > > + }
> > > +
> > > igt_subtest("shared-pte-page")
> > > xe_for_each_engine(fd, hwe)
> > > shared_pte_page(fd, hwe, 4,
> > > --
> > > 2.34.1
> > >
> >
> > Regardless addressing nit above:
> >
> > Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> >
>
> Thanks.
>
> Matt
>
> > --
> > Zbigniew
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-07-26 19:14 UTC | newest]
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2024-07-25 18:45 [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners Matthew Brost
2024-07-25 20:40 ` ✓ CI.xeBAT: success for tests/intel/xe_vm: Add test for 64k page corners (rev3) Patchwork
2024-07-25 20:49 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-07-26 4:20 ` ✗ CI.xeFULL: " Patchwork
2024-07-26 9:04 ` [PATCH v3] tests/intel/xe_vm: Add test for 64k page corners Zbigniew Kempczyński
2024-07-26 12:16 ` Matthew Brost
2024-07-26 19:13 ` Zbigniew Kempczyński
2024-07-26 17:03 ` Kamil Konieczny
2024-07-26 17:39 ` Matthew Brost
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