* [PATCH i-g-t 1/2] lib: Add u32 variants of igt_assert_{lt,lte}
@ 2024-07-29 22:02 Matt Roper
2024-07-29 22:02 ` [PATCH i-g-t 2/2] tests/intel: Apply igt.cocci transforms Matt Roper
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Matt Roper @ 2024-07-29 22:02 UTC (permalink / raw)
To: igt-dev; +Cc: matthew.d.roper
igt.cocci assumes that u32 variants of the comparison assertions exist,
so add the two that were missing.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
lib/igt_core.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/lib/igt_core.h b/lib/igt_core.h
index 084d94da7..82f474c5f 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -915,6 +915,15 @@ void igt_describe_f(const char *fmt, ...);
*/
#define igt_assert_lte(n1, n2) igt_assert_cmpint(n1, <=, >, n2)
+/**
+ * igt_assert_lte_u32:
+ * @n1: first integer
+ * @n2: second integer
+ *
+ * Like igt_assert_lte(), but for uint32_t.
+ */
+#define igt_assert_lte_u32(n1, n2) igt_assert_cmpuint(n1, <=, >, n2)
+
/**
* igt_assert_lte_u64:
* @n1: first integer
@@ -954,6 +963,15 @@ void igt_describe_f(const char *fmt, ...);
*/
#define igt_assert_lt(n1, n2) igt_assert_cmpint(n1, <, >=, n2)
+/**
+ * igt_assert_lt_u32:
+ * @n1: first integer
+ * @n2: second integer
+ *
+ * Like igt_assert_lt(), but for uint32_t.
+ */
+#define igt_assert_lt_u32(n1, n2) igt_assert_cmpuint(n1, <, >=, n2)
+
/**
* igt_assert_lt_u64:
* @n1: first integer
--
2.45.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH i-g-t 2/2] tests/intel: Apply igt.cocci transforms 2024-07-29 22:02 [PATCH i-g-t 1/2] lib: Add u32 variants of igt_assert_{lt,lte} Matt Roper @ 2024-07-29 22:02 ` Matt Roper 2024-07-31 12:25 ` [i-g-t,2/2] " Vivekanandan, Balasubramani 2024-08-01 21:46 ` [PATCH i-g-t 2/2] " Dixit, Ashutosh 2024-07-29 22:43 ` ✓ CI.xeBAT: success for series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} Patchwork ` (3 subsequent siblings) 4 siblings, 2 replies; 12+ messages in thread From: Matt Roper @ 2024-07-29 22:02 UTC (permalink / raw) To: igt-dev; +Cc: matthew.d.roper A number of Intel tests are using checks like "igt_assert(x < y)" rather than using the dedicated comparison assertions that print the actual values on assertion failure. Run the Intel test directory through Coccinelle to apply these conversions and also apply some other general coding style cleanup: spatch --in-place --sp-file lib/igt.cocci tests/intel Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- tests/intel/api_intel_allocator.c | 12 ++--- tests/intel/api_intel_bb.c | 18 +++---- tests/intel/drm_fdinfo.c | 8 +-- tests/intel/gem_blits.c | 16 +++--- tests/intel/gem_ccs.c | 4 +- tests/intel/gem_close_race.c | 2 +- tests/intel/gem_concurrent_all.c | 8 +-- tests/intel/gem_create.c | 2 +- tests/intel/gem_ctx_create.c | 8 +-- tests/intel/gem_ctx_exec.c | 4 +- tests/intel/gem_ctx_persistence.c | 12 +++-- tests/intel/gem_eio.c | 8 +-- tests/intel/gem_exec_alignment.c | 6 ++- tests/intel/gem_exec_big.c | 4 +- tests/intel/gem_exec_capture.c | 8 +-- tests/intel/gem_exec_fair.c | 32 +++++++----- tests/intel/gem_exec_fence.c | 2 +- tests/intel/gem_exec_gttfill.c | 4 +- tests/intel/gem_exec_nop.c | 2 +- tests/intel/gem_exec_reloc.c | 4 +- tests/intel/gem_gtt_speed.c | 2 +- tests/intel/gem_linear_blits.c | 6 +-- tests/intel/gem_pread.c | 5 +- tests/intel/gem_pwrite.c | 5 +- tests/intel/gem_pxp.c | 16 +++--- tests/intel/gem_reset_stats.c | 8 +-- tests/intel/gem_softpin.c | 8 ++- tests/intel/gem_tiled_blits.c | 6 +-- tests/intel/gem_tiled_fence_blits.c | 4 +- tests/intel/gem_userptr_blits.c | 4 +- tests/intel/gem_wait.c | 8 +-- tests/intel/gem_watchdog.c | 2 +- tests/intel/i915_hangman.c | 2 +- tests/intel/i915_module_load.c | 6 +-- tests/intel/i915_pm_freq_api.c | 50 +++++++++--------- tests/intel/i915_pm_rc6_residency.c | 4 +- tests/intel/i915_pm_rps.c | 11 ++-- tests/intel/i915_query.c | 12 ++--- tests/intel/kms_big_fb.c | 2 +- tests/intel/kms_busy.c | 2 +- tests/intel/kms_ccs.c | 2 +- tests/intel/kms_cdclk.c | 5 +- tests/intel/kms_dsc_helper.c | 4 +- tests/intel/kms_fbcon_fbt.c | 3 +- tests/intel/kms_pm_dc.c | 9 ++-- tests/intel/kms_pm_rpm.c | 2 +- tests/intel/kms_psr.c | 18 +++---- tests/intel/perf.c | 34 ++++++------ tests/intel/perf_pmu.c | 37 +++++++------ tests/intel/xe_ccs.c | 4 +- tests/intel/xe_debugfs.c | 2 +- tests/intel/xe_dma_buf_sync.c | 2 +- tests/intel/xe_evict.c | 4 +- tests/intel/xe_exec_balancer.c | 7 +-- tests/intel/xe_exec_basic.c | 4 +- tests/intel/xe_exec_compute_mode.c | 9 ++-- tests/intel/xe_exec_fault_mode.c | 5 +- tests/intel/xe_exec_reset.c | 8 +-- tests/intel/xe_exec_store.c | 2 +- tests/intel/xe_exec_threads.c | 11 ++-- tests/intel/xe_gt_freq.c | 80 ++++++++++++++--------------- tests/intel/xe_intel_bb.c | 16 +++--- tests/intel/xe_oa.c | 26 +++++----- tests/intel/xe_pat.c | 2 +- tests/intel/xe_peer2peer.c | 2 +- tests/intel/xe_pm.c | 16 +++--- tests/intel/xe_pm_residency.c | 4 +- tests/intel/xe_query.c | 12 ++--- tests/intel/xe_vm.c | 6 +-- 69 files changed, 335 insertions(+), 328 deletions(-) diff --git a/tests/intel/api_intel_allocator.c b/tests/intel/api_intel_allocator.c index 9218be3b9..15ba4828c 100644 --- a/tests/intel/api_intel_allocator.c +++ b/tests/intel/api_intel_allocator.c @@ -705,7 +705,7 @@ static void execbuf_with_allocator(int fd) gem_close(fd, object[i].handle); } - igt_assert(copied == magic); + igt_assert_eq_u32(copied, magic); igt_assert(intel_allocator_close(ahnd) == true); } @@ -776,13 +776,13 @@ static void gem_pool(int i915) bb[0] = single_exec_from_pool(i915, ahnd, 4096); gem_sync(i915, bb[0]); bb[1] = single_exec_from_pool(i915, ahnd, 4096); - igt_assert(bb[0] == bb[1]); + igt_assert_eq_u32(bb[0], bb[1]); bb[2] = single_exec_from_pool(i915, ahnd, 8192); gem_sync(i915, bb[2]); bb[3] = single_exec_from_pool(i915, ahnd, 8192); - igt_assert(bb[2] == bb[3]); - igt_assert(bb[0] != bb[2]); + igt_assert_eq_u32(bb[2], bb[3]); + igt_assert_neq_u32(bb[0], bb[2]); spin = igt_spin_new(i915, .ahnd = ahnd, @@ -792,8 +792,8 @@ static void gem_pool(int i915) bb[2] = single_exec_from_pool(i915, ahnd, 8192); bb[3] = single_exec_from_pool(i915, ahnd, 8192); igt_spin_free(i915, spin); - igt_assert(bb[0] != bb[1]); - igt_assert(bb[2] != bb[3]); + igt_assert_neq_u32(bb[0], bb[1]); + igt_assert_neq_u32(bb[2], bb[3]); put_ahnd(ahnd); diff --git a/tests/intel/api_intel_bb.c b/tests/intel/api_intel_bb.c index 6cb5d4f9e..db039dc3b 100644 --- a/tests/intel/api_intel_bb.c +++ b/tests/intel/api_intel_bb.c @@ -1024,11 +1024,11 @@ static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling) /* We'll fail on src <-> final compare so just warn */ if (tiling == I915_TILING_NONE) { - if (compare_bufs(&src, &dst, false) > 0) - igt_warn("none->none blit failed!"); + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, + "none->none blit failed!"); } else { - if (compare_bufs(&src, &dst, false) == 0) - igt_warn("none->tiled blit failed!"); + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, + "none->tiled blit failed!"); } fails = compare_bufs(&src, &final, true); @@ -1367,11 +1367,11 @@ static int render(struct buf_ops *bops, uint32_t tiling, bool do_reloc, /* We'll fail on src <-> final compare so just warn */ if (tiling == I915_TILING_NONE) { - if (compare_bufs(&src, &dst, false) > 0) - igt_warn("%s: none->none failed!\n", __func__); + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, + "%s: none->none failed!\n", __func__); } else { - if (compare_bufs(&src, &dst, false) == 0) - igt_warn("%s: none->tiled failed!\n", __func__); + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, + "%s: none->tiled failed!\n", __func__); } fails = compare_bufs(&src, &final, true); @@ -1535,7 +1535,7 @@ static void test_crc32(int i915, const intel_ctx_t *ctx, put_offset(ahnd, data); gem_close(i915, data); - igt_assert(cpu_crc == gpu_crc); + igt_assert_eq_u32(cpu_crc, gpu_crc); } put_ahnd(ahnd); diff --git a/tests/intel/drm_fdinfo.c b/tests/intel/drm_fdinfo.c index a790f9255..160dc3d0a 100644 --- a/tests/intel/drm_fdinfo.c +++ b/tests/intel/drm_fdinfo.c @@ -275,7 +275,7 @@ static void log_busy(unsigned int num_engines, uint64_t *val) int len; len = snprintf(p, rem, "%u=%" PRIu64 "\n", i, val[i]); - igt_assert(len > 0); + igt_assert_lt(0, len); rem -= len; p += len; } @@ -805,7 +805,7 @@ static size_t read_fdinfo(char *buf, const size_t sz, int at, const char *name) buf[count - 1] = 0; close(fd); - return count > 0 ? count : 0; + return max(count, 0); } /* @@ -855,7 +855,7 @@ test_memory(int i915, struct gem_memory_region *mr, unsigned int flags) gem_quiescent_gpu(i915); ret = __igt_parse_drm_fdinfo(dir, buf, &info, NULL, 0, NULL, 0); - igt_assert(ret > 0); + igt_assert_lt(0, ret); igt_require(info.num_regions); memcpy(&prev_info, &info, sizeof(info)); memcpy(&base_info, &info, sizeof(info)); @@ -905,7 +905,7 @@ test_memory(int i915, struct gem_memory_region *mr, unsigned int flags) ret = __igt_parse_drm_fdinfo(dir, buf, &info, NULL, 0, region_map, ARRAY_SIZE(region_map)); - igt_assert(ret > 0); + igt_assert_lt(0, ret); igt_assert(info.num_regions); read_fdinfo(fdinfo_buf, sizeof(fdinfo_buf), dir, buf); diff --git a/tests/intel/gem_blits.c b/tests/intel/gem_blits.c index 5ca81fbfe..b2af48ef1 100644 --- a/tests/intel/gem_blits.c +++ b/tests/intel/gem_blits.c @@ -267,7 +267,7 @@ static void buffer_set_tiling(const struct device *device, batch[i++] = obj[1].offset >> 32; if ((tiling | buffer->tiling) >= T_YMAJOR) { - igt_assert(device->gen >= 6); + igt_assert_lte(6, device->gen); batch[i++] = MI_FLUSH_DW_CMD | 2; batch[i++] = 0; batch[i++] = 0; @@ -415,7 +415,7 @@ static bool blit_to_linear(const struct device *device, batch[i++] = obj[1].offset >> 32; if (buffer->tiling >= T_YMAJOR) { - igt_assert(device->gen >= 6); + igt_assert_lte(6, device->gen); batch[i++] = MI_FLUSH_DW_CMD | 2; batch[i++] = 0; batch[i++] = 0; @@ -542,11 +542,9 @@ static bool buffer_check(const struct device *device, continue; for (int x = 0; x < buffer->width; x++) { - if (row[x] != model[x] && num_errors++ < 5) { - igt_warn("buffer handle=%d mismatch at (%d, %d): expected %08x, found %08x\n", - buffer->handle, - x, y, model[x], row[x]); - } + igt_warn_on_f(row[x] != model[x] && num_errors++ < 5, + "buffer handle=%d mismatch at (%d, %d): expected %08x, found %08x\n", + buffer->handle, x, y, model[x], row[x]); } } @@ -664,7 +662,7 @@ blit(const struct device *device, height = dst->height - dst_y; if (dst->caching) { - igt_assert(device->gen >= 3); + igt_assert_lte(3, device->gen); igt_assert(device->llc || !src->caching); } @@ -764,7 +762,7 @@ blit(const struct device *device, batch[i++] = obj[1].offset >> 32; if ((src->tiling | dst->tiling) >= T_YMAJOR) { - igt_assert(device->gen >= 6); + igt_assert_lte(6, device->gen); batch[i++] = MI_FLUSH_DW_CMD | 2; batch[i++] = 0; batch[i++] = 0; diff --git a/tests/intel/gem_ccs.c b/tests/intel/gem_ccs.c index 6ced67d7a..07aa6d322 100644 --- a/tests/intel/gem_ccs.c +++ b/tests/intel/gem_ccs.c @@ -175,7 +175,7 @@ static void surf_copy(int i915, gem_sync(i915, blt.dst.handle); WRITE_PNG(i915, run_id, "corrupted", &blt.dst, dst->x2, dst->y2, bpp); result = memcmp(src->ptr, dst->ptr, src->size); - igt_assert(result != 0); + igt_assert_neq(result, 0); /* retrieve back ccs */ memcpy(ccsmap, ccscopy, ccssize); @@ -601,7 +601,7 @@ static int opt_handler(int opt, int opt_index, void *data) case 'f': param.compression_format = atoi(optarg); igt_debug("Compression format: %d\n", param.compression_format); - igt_assert((param.compression_format & ~0x1f) == 0); + igt_assert_eq((param.compression_format & ~0x1f), 0); break; case 'p': param.write_png = true; diff --git a/tests/intel/gem_close_race.c b/tests/intel/gem_close_race.c index 9edcf13eb..c68e2fa73 100644 --- a/tests/intel/gem_close_race.c +++ b/tests/intel/gem_close_race.c @@ -307,7 +307,7 @@ static void multigpu_threads(int timeout, unsigned int flags, int gpu_count) struct drm_gem_open name; int fd = __drm_open_driver_another(gpu, DRIVER_INTEL); - igt_assert(fd > 0); + igt_assert_lt(0, fd); igt_fork(child, size) thread(fd, name, timeout, flags); diff --git a/tests/intel/gem_concurrent_all.c b/tests/intel/gem_concurrent_all.c index dbb7622d3..acc6a230d 100644 --- a/tests/intel/gem_concurrent_all.c +++ b/tests/intel/gem_concurrent_all.c @@ -306,7 +306,7 @@ userptr_create_bo(const struct buffers *b) igt_assert(ptr != (void *)-1); userptr.user_ptr = to_user_pointer(ptr); - do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr)); + do_ioctl(fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr); buf = intel_buf_create_using_handle_and_size(b->bops, userptr.handle, b->width, b->height, 32, 0, I915_TILING_NONE, 0, @@ -497,7 +497,7 @@ vgem_create_bo(const struct buffers *b) struct dmabuf *dmabuf; uint32_t handle; - igt_assert(vgem_drv != -1); + igt_assert_neq(vgem_drv, -1); vgem.width = b->width; vgem.height = b->height; @@ -915,7 +915,7 @@ static void buffers_create(struct buffers *b) igt_assert(b->bops); buffers_destroy(b); - igt_assert(b->count == 0); + igt_assert_eq(b->count, 0); b->count = count; ahnd = alloc_open(); @@ -941,7 +941,7 @@ static void __buffers_create(struct buffers *b) { b->bops = buf_ops_create(fd); igt_assert(b->bops); - igt_assert(b->num_buffers > 0); + igt_assert_lt(0, b->num_buffers); igt_assert(b->mode); igt_assert(b->mode->create_bo); diff --git a/tests/intel/gem_create.c b/tests/intel/gem_create.c index 26cd6e32e..ca39a8b64 100644 --- a/tests/intel/gem_create.c +++ b/tests/intel/gem_create.c @@ -637,7 +637,7 @@ static void create_ext_set_pat(int fd) * This means that we are on a Meteor Lake and the PAT * index is already supported by the running i915 */ - igt_assert(ret == 0); + igt_assert_eq(ret, 0); /* * {set|get}_caching ioctl should fail for objects created with set_pat diff --git a/tests/intel/gem_ctx_create.c b/tests/intel/gem_ctx_create.c index 6afb10a7b..0332ecbb9 100644 --- a/tests/intel/gem_ctx_create.c +++ b/tests/intel/gem_ctx_create.c @@ -297,18 +297,14 @@ static void xchg_u32(void *array, unsigned i, unsigned j) { uint32_t *a = array, tmp; - tmp = a[i]; - a[i] = a[j]; - a[j] = tmp; + igt_swap(a[i], a[j]); } static void xchg_ptr(void *array, unsigned i, unsigned j) { void **a = array, *tmp; - tmp = a[i]; - a[i] = a[j]; - a[j] = tmp; + igt_swap(a[i], a[j]); } static unsigned __context_size(int fd) diff --git a/tests/intel/gem_ctx_exec.c b/tests/intel/gem_ctx_exec.c index f3e252d10..a45a7e378 100644 --- a/tests/intel/gem_ctx_exec.c +++ b/tests/intel/gem_ctx_exec.c @@ -346,7 +346,7 @@ static void nohangcheck_hostile(int i915) IGT_SPIN_FENCE_OUT)); new = fill_ring(i915, &spin->execbuf); - igt_assert(new != -1); + igt_assert_neq(new, -1); spin->out_fence = -1; if (fence < 0) { @@ -362,7 +362,7 @@ static void nohangcheck_hostile(int i915) } } intel_ctx_destroy(i915, ctx); - igt_assert(fence != -1); + igt_assert_neq(fence, -1); err = 0; if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */ diff --git a/tests/intel/gem_ctx_persistence.c b/tests/intel/gem_ctx_persistence.c index 90c1e0112..8d4a874d4 100644 --- a/tests/intel/gem_ctx_persistence.c +++ b/tests/intel/gem_ctx_persistence.c @@ -1093,10 +1093,12 @@ static void test_processes(int i915) /* Wait until we are told to die */ pid = getpid(); - write(p[i].sv[0], &pid, sizeof(pid)); + igt_assert_eq(write(p[i].sv[0], &pid, sizeof(pid)), + sizeof(pid)); pid = 0; - read(p[i].sv[0], &pid, sizeof(pid)); + igt_assert_eq(read(p[i].sv[0], &pid, sizeof(pid)), + sizeof(pid)); igt_assert(pid == getpid()); } } @@ -1109,8 +1111,10 @@ static void test_processes(int i915) igt_assert_eq(sync_fence_wait(fence, 0), -ETIME); /* Kill *this* process */ - read(p[i].sv[1], &pid, sizeof(pid)); - write(p[i].sv[1], &pid, sizeof(pid)); + igt_assert_eq(read(p[i].sv[1], &pid, sizeof(pid)), + sizeof(pid)); + igt_assert_eq(write(p[i].sv[1], &pid, sizeof(pid)), + sizeof(pid)); /* * A little bit of slack required for the signal to terminate diff --git a/tests/intel/gem_eio.c b/tests/intel/gem_eio.c index dc6178d63..b65b914fa 100644 --- a/tests/intel/gem_eio.c +++ b/tests/intel/gem_eio.c @@ -627,7 +627,7 @@ static void test_inflight(int fd, unsigned int wait) for (unsigned int n = 0; n < max; n++) { gem_execbuf_wr(fd, &execbuf); fence[n] = execbuf.rsvd2 >> 32; - igt_assert(fence[n] != -1); + igt_assert_neq(fence[n], -1); } igt_debugfs_dump(fd, "i915_engine_info"); @@ -687,7 +687,7 @@ static void test_inflight_suspend(int fd) for (unsigned int n = 0; n < max; n++) { gem_execbuf_wr(fd, &execbuf); fence[n] = execbuf.rsvd2 >> 32; - igt_assert(fence[n] != -1); + igt_assert_neq(fence[n], -1); } igt_set_autoresume_delay(30); @@ -774,7 +774,7 @@ static void test_inflight_contexts(int fd, unsigned int wait) if (__gem_execbuf_wr(fd, &execbuf)) break; /* small shared ring */ fence[n] = execbuf.rsvd2 >> 32; - igt_assert(fence[n] != -1); + igt_assert_neq(fence[n], -1); count++; } @@ -885,7 +885,7 @@ static void test_inflight_internal(int fd, unsigned int wait) gem_execbuf_wr(fd, &execbuf); fences[nfence] = execbuf.rsvd2 >> 32; - igt_assert(fences[nfence] != -1); + igt_assert_neq(fences[nfence], -1); nfence++; } diff --git a/tests/intel/gem_exec_alignment.c b/tests/intel/gem_exec_alignment.c index 7b51b7af0..6a9905d95 100644 --- a/tests/intel/gem_exec_alignment.c +++ b/tests/intel/gem_exec_alignment.c @@ -302,7 +302,8 @@ static void prio_inversion(int i915, unsigned int flags) naughty_child(i915, link[1], obj.handle, flags); igt_debug("Waiting for naughty client\n"); - read(link[0], &elapsed, sizeof(elapsed)); + igt_assert_eq(read(link[0], &elapsed, sizeof(elapsed)), + sizeof(elapsed)); igt_debug("Ready...\n"); usleep(250 * 1000); /* let the naughty execbuf begin */ igt_debug("Go!\n"); @@ -331,7 +332,8 @@ static void prio_inversion(int i915, unsigned int flags) igt_waitchildren(); gem_close(i915, obj.handle); - read(link[0], &naughty, sizeof(naughty)); + igt_assert_eq(read(link[0], &naughty, sizeof(naughty)), + sizeof(naughty)); igt_info("Naughty client took %'"PRIu64"ns\n", naughty); igt_assert(elapsed < naughty / 2); diff --git a/tests/intel/gem_exec_big.c b/tests/intel/gem_exec_big.c index 7bd91c2a0..86849f322 100644 --- a/tests/intel/gem_exec_big.c +++ b/tests/intel/gem_exec_big.c @@ -143,9 +143,7 @@ static void xchg_reloc(void *array, unsigned i, unsigned j) struct drm_i915_gem_relocation_entry *b = &reloc[j]; struct drm_i915_gem_relocation_entry tmp; - tmp = *a; - *a = *b; - *b = tmp; + igt_swap(*a, *b); } static void execN(int fd, uint32_t handle, uint64_t batch_size, unsigned flags, char *ptr) diff --git a/tests/intel/gem_exec_capture.c b/tests/intel/gem_exec_capture.c index 720ff796d..2340ad495 100644 --- a/tests/intel/gem_exec_capture.c +++ b/tests/intel/gem_exec_capture.c @@ -406,7 +406,7 @@ static void __capture1(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx, gem_execbuf_wr(fd, &execbuf); fence_out = execbuf.rsvd2 >> 32; - igt_assert(fence_out >= 0); + igt_assert_lte(0, fence_out); /* Wait for the request to start */ while (READ_ONCE(*seqno) != 0xc0ffee) @@ -792,11 +792,11 @@ static void prioinv(int fd, int dir, const intel_ctx_t *ctx, &fence_out, REGION_SMEM, true)); put_ahnd(ahnd); - write(link[1], &fd, sizeof(fd)); /* wake the parent up */ + igt_assert_eq(write(link[1], &fd, sizeof(fd)), sizeof(fd)); /* wake the parent up */ wait_to_die(fence_out); - write(link[1], &fd, sizeof(fd)); /* wake the parent up */ + igt_assert_eq(write(link[1], &fd, sizeof(fd)), sizeof(fd)); /* wake the parent up */ } - read(link[0], &dummy, sizeof(dummy)); + igt_assert_eq(read(link[0], &dummy, sizeof(dummy)), sizeof(dummy)); igt_require_f(poll(&(struct pollfd){link[0], POLLIN}, 1, 500) == 0, "Capture completed too quickly! Will not block\n"); diff --git a/tests/intel/gem_exec_fair.c b/tests/intel/gem_exec_fair.c index 2f7ef3800..19df66921 100644 --- a/tests/intel/gem_exec_fair.c +++ b/tests/intel/gem_exec_fair.c @@ -579,10 +579,12 @@ static void fair_child(int i915, const intel_ctx_t *ctx, /* Synchronize with other children/parent upon construction */ if (sv != -1) - write(sv, &p_fence, sizeof(p_fence)); + igt_assert_eq(write(sv, &p_fence, sizeof(p_fence)), + sizeof(p_fence)); if (rv != -1) - read(rv, &p_fence, sizeof(p_fence)); - igt_assert(p_fence == -1); + igt_assert_eq(read(rv, &p_fence, sizeof(p_fence)), + sizeof(p_fence)); + igt_assert_eq(p_fence, -1); aux_flags = 0; if (intel_gen(intel_get_drm_devid(i915)) < 8) @@ -850,9 +852,11 @@ static void fairness(int i915, const intel_ctx_cfg_t *cfg, { int sync; for (int child = 0; child < nchild; child++) - read(lnk.child[0], &sync, sizeof(sync)); + igt_assert_eq(read(lnk.child[0], &sync, sizeof(sync)), + sizeof(sync)); for (int child = 0; child < nchild; child++) - write(lnk.parent[1], &sync, sizeof(sync)); + igt_assert_eq(write(lnk.parent[1], &sync, sizeof(sync)), + sizeof(sync)); } while (nfences--) @@ -1028,9 +1032,9 @@ static void deadline_child(int i915, if (!(flags & DL_PRIO)) execbuf.flags |= I915_EXEC_FENCE_IN; - write(sv, &prev, sizeof(int)); - read(rv, &prev, sizeof(int)); - igt_assert(prev == -1); + igt_assert_eq(write(sv, &prev, sizeof(int)), sizeof(int)); + igt_assert_eq(read(rv, &prev, sizeof(int)), sizeof(int)); + igt_assert_eq(prev, -1); prev = execbuf.rsvd2; next = execbuf.rsvd2 >> 32; @@ -1044,7 +1048,8 @@ static void deadline_child(int i915, gem_execbuf_wr(i915, &execbuf); close(execbuf.rsvd2); - write(sv, &fence.handle, sizeof(uint32_t)); + igt_assert_eq(write(sv, &fence.handle, sizeof(uint32_t)), + sizeof(uint32_t)); prev = next; next = execbuf.rsvd2 >> 32; @@ -1187,10 +1192,12 @@ static void deadline(int i915, const intel_ctx_cfg_t *cfg, } for (int i = 0; i < num_children; i++) - read(link[i].child[0], &over, sizeof(int)); + igt_assert_eq(read(link[i].child[0], &over, sizeof(int)), + sizeof(int)); igt_info("Testing %d children, with %'dns\n", num_children, child_ns); for (int i = 0; i < num_children; i++) - write(link[i].parent[1], &over, sizeof(int)); + igt_assert_eq(write(link[i].parent[1], &over, sizeof(int)), + sizeof(int)); over = 0; missed = 0; @@ -1207,7 +1214,8 @@ static void deadline(int i915, const intel_ctx_cfg_t *cfg, sw_sync_timeline_inc(timeline, 1); for (int i = 0; i < num_children; i++) { - read(link[i].child[0], &fences[i].handle, sizeof(uint32_t)); + igt_assert_eq(read(link[i].child[0], &fences[i].handle, sizeof(uint32_t)), + sizeof(uint32_t)); fences[i].flags = I915_EXEC_FENCE_WAIT; } diff --git a/tests/intel/gem_exec_fence.c b/tests/intel/gem_exec_fence.c index a313c31f2..7f39c73d7 100644 --- a/tests/intel/gem_exec_fence.c +++ b/tests/intel/gem_exec_fence.c @@ -366,7 +366,7 @@ static void test_fence_busy_all(int fd, const intel_ctx_t *ctx, unsigned flags) execbuf.rsvd2 = -1; gem_execbuf_wr(fd, &execbuf); fence = execbuf.rsvd2 >> 32; - igt_assert(fence != -1); + igt_assert_neq(fence, -1); if (all < 0) { all = fence; diff --git a/tests/intel/gem_exec_gttfill.c b/tests/intel/gem_exec_gttfill.c index 096681740..ff600e0ca 100644 --- a/tests/intel/gem_exec_gttfill.c +++ b/tests/intel/gem_exec_gttfill.c @@ -66,9 +66,7 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) struct batch *batches = array; struct batch tmp; - tmp = batches[i]; - batches[i] = batches[j]; - batches[j] = tmp; + igt_swap(batches[i], batches[j]); } static void submit(int fd, uint64_t ahnd, unsigned int gen, diff --git a/tests/intel/gem_exec_nop.c b/tests/intel/gem_exec_nop.c index fb37cb511..1b20cc870 100644 --- a/tests/intel/gem_exec_nop.c +++ b/tests/intel/gem_exec_nop.c @@ -415,7 +415,7 @@ stable_nop_on_ring(int fd, uint32_t handle, const intel_ctx_t *ctx, igt_stats_t s; double n; - igt_assert(reps >= 5); + igt_assert_lte(5, reps); igt_stats_init_with_size(&s, reps); s.is_float = true; diff --git a/tests/intel/gem_exec_reloc.c b/tests/intel/gem_exec_reloc.c index d8013ccfc..44c09c3e2 100644 --- a/tests/intel/gem_exec_reloc.c +++ b/tests/intel/gem_exec_reloc.c @@ -1343,7 +1343,7 @@ static void concurrent_child(int i915, const intel_ctx_t *ctx, x += idx * CONCURRENT; do { - read(in, batch, sizeof(*batch)); + igt_assert_eq(read(in, batch, sizeof(*batch)), sizeof(*batch)); if (!*batch) break; @@ -1359,7 +1359,7 @@ static void concurrent_child(int i915, const intel_ctx_t *ctx, } } - write(out, &err, sizeof(err)); + igt_assert_eq(write(out, &err, sizeof(err)), sizeof(err)); count++; } while (err == 0); diff --git a/tests/intel/gem_gtt_speed.c b/tests/intel/gem_gtt_speed.c index 996e54af0..0f4e174d2 100644 --- a/tests/intel/gem_gtt_speed.c +++ b/tests/intel/gem_gtt_speed.c @@ -70,7 +70,7 @@ static void streaming_load(void *src, int len) { __m128i tmp, *s = src; - igt_assert((len & 15) == 0); + igt_assert_eq((len & 15), 0); igt_assert((((uintptr_t)src) & 15) == 0); while (len >= 16) { diff --git a/tests/intel/gem_linear_blits.c b/tests/intel/gem_linear_blits.c index 2eeec5b6a..b6c0b13ac 100644 --- a/tests/intel/gem_linear_blits.c +++ b/tests/intel/gem_linear_blits.c @@ -212,9 +212,9 @@ check_bo(int fd, uint32_t handle, uint32_t val) num_errors = 0; for (i = 0; i < WIDTH*HEIGHT; i++) { - if (linear[i] != val && num_errors++ < 32) - igt_warn("[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", - i * 4, val, linear[i], val ^ linear[i]); + igt_warn_on_f(linear[i] != val && num_errors++ < 32, + "[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", + i * 4, val, linear[i], val ^ linear[i]); val++; } igt_assert_eq(num_errors, 0); diff --git a/tests/intel/gem_pread.c b/tests/intel/gem_pread.c index e5e662361..70a38e75c 100644 --- a/tests/intel/gem_pread.c +++ b/tests/intel/gem_pread.c @@ -151,7 +151,7 @@ static void write_value(const char *path, int value) fd = open(path, O_WRONLY); if (fd != -1) { - write(fd, buf, len); + igt_assert_eq(write(fd, buf, len), len); close(fd); } } @@ -223,8 +223,7 @@ static void test_exhaustion(int i915) count++; } igt_assert(count); - if (t.err) - igt_warn("err:%d after %lu threads\n", t.err, count); + igt_warn_on_f(t.err, "err:%d after %lu threads\n", t.err, count); /* Service the fault; releasing the stuck ioctls */ memset(©, 0, sizeof(copy)); diff --git a/tests/intel/gem_pwrite.c b/tests/intel/gem_pwrite.c index 025684a33..05a47b7b1 100644 --- a/tests/intel/gem_pwrite.c +++ b/tests/intel/gem_pwrite.c @@ -425,7 +425,7 @@ static void write_value(const char *path, int value) fd = open(path, O_WRONLY); if (fd != -1) { - write(fd, buf, len); + igt_assert_eq(write(fd, buf, len), len); close(fd); } } @@ -497,8 +497,7 @@ static void test_exhaustion(int i915) count++; } igt_assert(count); - if (t.err) - igt_warn("err:%d after %lu threads\n", t.err, count); + igt_warn_on_f(t.err, "err:%d after %lu threads\n", t.err, count); /* Service the fault; releasing the stuck ioctls */ memset(©, 0, sizeof(copy)); diff --git a/tests/intel/gem_pxp.c b/tests/intel/gem_pxp.c index 6be19318a..e2c12df17 100644 --- a/tests/intel/gem_pxp.c +++ b/tests/intel/gem_pxp.c @@ -811,7 +811,7 @@ static void test_pxp_dmabuffshare_refcnt(int i915) for (n = 0; n < (TSTSURF_SIZE/4); ++n) if (encrypted[0][n] == encrypted[1][n]) ++num_matches; - igt_assert(num_matches == (TSTSURF_SIZE/4)); + igt_assert_eq(num_matches, (TSTSURF_SIZE / 4)); } @@ -988,7 +988,7 @@ static void test_pxp_stale_ctx_execution(int i915) */ prepare_exec_assets(i915, &data, true, false); ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); - igt_assert(ret == 0); + igt_assert_eq(ret, 0); trigger_pxp_debugfs_forced_teardown(i915); @@ -1008,7 +1008,7 @@ static void test_pxp_stale_buf_execution(int i915) /* Use pxp buffers with pxp context for testing for invalidation of protected buffers. */ prepare_exec_assets(i915, &data, true, true); ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); - igt_assert(ret == 0); + igt_assert_eq(ret, 0); trigger_pxp_debugfs_forced_teardown(i915); @@ -1055,7 +1055,7 @@ static void test_pxp_stale_buf_optout_execution(int i915) * the intent of the subtest) to ensure ARB session is alive. */ ret = create_ctx_with_params(i915, true, true, true, false, &tmpctx); - igt_assert(ret == 0); + igt_assert_eq(ret, 0); /* * Use a normal context for testing opt-out behavior @@ -1063,7 +1063,7 @@ static void test_pxp_stale_buf_optout_execution(int i915) */ prepare_exec_assets(i915, &data, false, true); ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); - igt_assert(ret == 0); + igt_assert_eq(ret, 0); trigger_pxp_debugfs_forced_teardown(i915); @@ -1088,7 +1088,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat */ prepare_exec_assets(i915, &data[0], true, false); ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf); - igt_assert(ret == 0); + igt_assert_eq(ret, 0); /* * For asset data[1]: Use pxp buffers with pxp context for testing for invalidation @@ -1096,7 +1096,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat */ prepare_exec_assets(i915, &data[1], true, true); ret = gem_execbuf_flush_store_dw(i915, data[1].ibb, data[1].ctx, data[1].fencebuf); - igt_assert(ret == 0); + igt_assert_eq(ret, 0); /* * For asset data[2]: Use a normal context for testing opt-out behavior @@ -1104,7 +1104,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat */ prepare_exec_assets(i915, &data[2], false, true); ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf); - igt_assert(ret == 0); + igt_assert_eq(ret, 0); /* Do an S3 suspend resume cycle which also causes the pxp teardown event */ trigger_powermgt_suspend_cycle(i915, pm); diff --git a/tests/intel/gem_reset_stats.c b/tests/intel/gem_reset_stats.c index 91bec96c0..8c74ce28c 100644 --- a/tests/intel/gem_reset_stats.c +++ b/tests/intel/gem_reset_stats.c @@ -315,7 +315,7 @@ static int noop(int fd, uint32_t ctx, const struct intel_execution_ring *e) memset(&exec, 0, sizeof(exec)); exec.handle = gem_create(fd, 4096); - igt_assert((int)exec.handle > 0); + igt_assert_lt(0, (int)exec.handle); gem_write(fd, exec.handle, 0, &bbe, sizeof(bbe)); memset(&eb, 0, sizeof(eb)); @@ -457,7 +457,7 @@ static void test_rs(const struct intel_execution_ring *e, if (i == hang_index) inject_hang(fd[i], 0, e, ASYNC); else - igt_assert(noop(fd[i], 0, e) > 0); + igt_assert_lt(0, noop(fd[i], 0, e)); } sync_gpu(); @@ -524,7 +524,7 @@ static void test_rs_ctx(const struct intel_execution_ring *e, if (i == hang_index && j == hang_context) inject_hang(fd[i], ctx[i][j], e, ASYNC); else - igt_assert(noop(fd[i], ctx[i][j], e) > 0); + igt_assert_lt(0, noop(fd[i], ctx[i][j], e)); } } sync_gpu(); @@ -876,7 +876,7 @@ static void _check_param_ctx(const int fd, const int ctx, const cap_t cap) igt_assert_eq(_test_params(fd, ctx, 0, 0), 0); if (cap != root) { - igt_assert(get_reset_count(fd, ctx) == 0); + igt_assert_eq(get_reset_count(fd, ctx), 0); } } diff --git a/tests/intel/gem_softpin.c b/tests/intel/gem_softpin.c index b7c1b34e1..c542bf741 100644 --- a/tests/intel/gem_softpin.c +++ b/tests/intel/gem_softpin.c @@ -793,7 +793,7 @@ static void __reserve(uint64_t ahnd, int i915, bool pinned, unsigned int flags; int i; - igt_assert(num_obj > 1); + igt_assert_lt(1, num_obj); flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS; if (pinned) @@ -843,7 +843,7 @@ static void __exec_using_allocator(uint64_t ahnd, int i915, int num_obj, uint64_t sz = 4096; int i; - igt_assert(num_obj > 10); + igt_assert_lt(10, num_obj); flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS; if (pinned) @@ -969,9 +969,7 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) struct batch *batches = array; struct batch tmp; - tmp = batches[i]; - batches[i] = batches[j]; - batches[j] = tmp; + igt_swap(batches[i], batches[j]); } static void submit(int fd, unsigned int gen, diff --git a/tests/intel/gem_tiled_blits.c b/tests/intel/gem_tiled_blits.c index 6fcc8616e..d8e80ca60 100644 --- a/tests/intel/gem_tiled_blits.c +++ b/tests/intel/gem_tiled_blits.c @@ -129,9 +129,9 @@ check_bo(struct intel_buf *buf, uint32_t val, struct intel_bb *ibb) linear = intel_buf_cpu_map(linear_buf, 0); num_errors = 0; for (i = 0; i < width * height; i++) { - if (linear[i] != val && num_errors++ < 32) - igt_warn("[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", - i * 4, val, linear[i], val ^ linear[i]); + igt_warn_on_f(linear[i] != val && num_errors++ < 32, + "[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", + i * 4, val, linear[i], val ^ linear[i]); val++; } igt_assert_eq(num_errors, 0); diff --git a/tests/intel/gem_tiled_fence_blits.c b/tests/intel/gem_tiled_fence_blits.c index 5e5bc6939..f5a3d9311 100644 --- a/tests/intel/gem_tiled_fence_blits.c +++ b/tests/intel/gem_tiled_fence_blits.c @@ -158,9 +158,7 @@ static void xchg_u32(void *array, unsigned i, unsigned j) { uint32_t tmp, *base = array; - tmp = base[i]; - base[i] = base[j]; - base[j] = tmp; + igt_swap(base[i], base[j]); } static void run_test(int fd, int count, uint64_t end) diff --git a/tests/intel/gem_userptr_blits.c b/tests/intel/gem_userptr_blits.c index 807c209e8..67283c182 100644 --- a/tests/intel/gem_userptr_blits.c +++ b/tests/intel/gem_userptr_blits.c @@ -814,7 +814,7 @@ static void test_nohangcheck_hostile(int i915) IGT_SPIN_FENCE_OUT)); new = fill_ring(i915, &spin->execbuf); - igt_assert(new != -1); + igt_assert_neq(new, -1); spin->out_fence = -1; if (fence < 0) { @@ -831,7 +831,7 @@ static void test_nohangcheck_hostile(int i915) } intel_ctx_destroy(i915, ctx); put_ahnd(ahnd); - igt_assert(fence != -1); + igt_assert_neq(fence, -1); if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */ igt_debugfs_dump(i915, "i915_engine_info"); diff --git a/tests/intel/gem_wait.c b/tests/intel/gem_wait.c index 7a353a11e..9265d1d7a 100644 --- a/tests/intel/gem_wait.c +++ b/tests/intel/gem_wait.c @@ -167,9 +167,11 @@ static void basic(int fd, const intel_ctx_t *ctx, unsigned engine, igt_seconds_elapsed(&tv) < timeout) ; - if ((flags & HANG) == 0 && !timespec_isset(&spin->last_signal)) - igt_warn("spinner not terminated, expired? %d!\n", - poll(&(struct pollfd){ spin->timerfd, POLLIN }, 1, 0)); + igt_warn_on_f((flags & HANG) == 0 && !timespec_isset(&spin->last_signal), + "spinner not terminated, expired? %d!\n", poll(&(struct pollfd){ + spin->timerfd, + POLLIN, + }, 1, 0)); igt_assert_eq(__gem_wait(fd, &wait), 0); } else { diff --git a/tests/intel/gem_watchdog.c b/tests/intel/gem_watchdog.c index 3d2fd68a8..1edde8b3c 100644 --- a/tests/intel/gem_watchdog.c +++ b/tests/intel/gem_watchdog.c @@ -500,7 +500,7 @@ far_delay(int i915, unsigned long delay, unsigned int target, batch[1] = batch[0]; batch[1].flags &= ~EXEC_OBJECT_WRITE; batch[0].handle = handle; - assert(batch[0].flags & EXEC_OBJECT_WRITE); + igt_assert(batch[0].flags & EXEC_OBJECT_WRITE); gem_execbuf_wr(i915, &execbuf); gem_close(i915, obj.handle); diff --git a/tests/intel/i915_hangman.c b/tests/intel/i915_hangman.c index f100118b6..a556eec53 100644 --- a/tests/intel/i915_hangman.c +++ b/tests/intel/i915_hangman.c @@ -470,7 +470,7 @@ static void test_hang_detector(const intel_ctx_t *ctx, igt_stop_hang_detector(); /* Did it work? */ - igt_assert(hang_count == 1); + igt_assert_eq(hang_count, 1); check_alive(); } diff --git a/tests/intel/i915_module_load.c b/tests/intel/i915_module_load.c index e3e4470df..cd1ee6d10 100644 --- a/tests/intel/i915_module_load.c +++ b/tests/intel/i915_module_load.c @@ -230,7 +230,7 @@ inject_fault(const char *module_name, const char *opt, int fault) char buf[1024]; int dir; - igt_assert(fault > 0); + igt_assert_lt(0, fault); snprintf(buf, sizeof(buf), "%s=%d", opt, fault); if (igt_kmod_load(module_name, buf)) { @@ -343,8 +343,8 @@ static uint32_t driver_load_with_lmem_bar_size(uint32_t lmem_bar_size, bool che char *tmp; tmp = __igt_params_get(i915, "lmem_bar_size"); - if (!tmp) - igt_skip("lmem_bar_size modparam not supported on this kernel. Skipping the test.\n"); + igt_skip_on_f(!tmp, + "lmem_bar_size modparam not supported on this kernel. Skipping the test.\n"); free(tmp); } diff --git a/tests/intel/i915_pm_freq_api.c b/tests/intel/i915_pm_freq_api.c index 2a3da6f4a..f2106cd3e 100644 --- a/tests/intel/i915_pm_freq_api.c +++ b/tests/intel/i915_pm_freq_api.c @@ -61,34 +61,34 @@ static void test_freq_basic_api(int dirfd, int gt) igt_debug("GT: %d, RPn: %d, RPe: %d, RP0: %d\n", gt, rpn, rpe, rp0); /* Set min/max to RPn, RP0 for baseline behavior */ - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0) > 0); + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0)); /* * Negative bound tests * RPn is the floor * RP0 is the ceiling */ - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn - 1) < 0); - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0 + 1) < 0); - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn - 1) < 0); - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0 + 1) < 0); + igt_assert_lt(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn - 1), 0); + igt_assert_lt(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0 + 1), 0); + igt_assert_lt(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn - 1), 0); + igt_assert_lt(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0 + 1), 0); /* Assert min requests are respected from rp0 to rpn */ - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0) > 0); - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rp0); - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpe) > 0); - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpe); - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn); + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0)); + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rp0); + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpe)); + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rpe); + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rpn); /* Assert max requests are respected from rpn to rp0 */ - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn); - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpe) > 0); - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpe); - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0) > 0); - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rp0); + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rpn); + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpe)); + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rpe); + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0)); + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rp0); } @@ -100,8 +100,8 @@ static void test_reset(int i915, int dirfd, int gt, int count) for (int i = 0; i < count; i++) { igt_debug("Running cycle: %d", i); - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); usleep(ACT_FREQ_LATENCY_US); req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ); if (req_freq) @@ -124,8 +124,8 @@ static void test_suspend(int i915, int dirfd, int gt) uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ); uint32_t req_freq; - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); usleep(ACT_FREQ_LATENCY_US); req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ); if (req_freq) @@ -149,8 +149,10 @@ static void restore_sysfs_freq(int sig) /* Restore frequencies */ for_each_sysfs_gt_dirfd(i915, dirfd, gt) { igt_pm_ignore_slpc_efficient_freq(i915, dirfd, false); - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, stash_max[gt]) > 0); - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, stash_min[gt]) > 0); + igt_assert_lt(0, + set_freq(dirfd, RPS_MAX_FREQ_MHZ, stash_max[gt])); + igt_assert_lt(0, + set_freq(dirfd, RPS_MIN_FREQ_MHZ, stash_min[gt])); } free(stash_min); free(stash_max); diff --git a/tests/intel/i915_pm_rc6_residency.c b/tests/intel/i915_pm_rc6_residency.c index ebc0c235c..7942d46d3 100644 --- a/tests/intel/i915_pm_rc6_residency.c +++ b/tests/intel/i915_pm_rc6_residency.c @@ -250,7 +250,7 @@ static char *get_drpc(int i915, int gt_id) int gt_dir; gt_dir = igt_debugfs_gt_dir(i915, gt_id); - igt_assert(gt_dir != -1); + igt_assert_neq(gt_dir, -1); return igt_sysfs_get(gt_dir, "drpc"); } @@ -307,7 +307,7 @@ static int open_pmu(int i915, uint64_t config) fd = perf_i915_open(i915, config); igt_skip_on(fd < 0 && errno == ENODEV); - igt_assert(fd >= 0); + igt_assert_lte(0, fd); return fd; } diff --git a/tests/intel/i915_pm_rps.c b/tests/intel/i915_pm_rps.c index 99b83f315..3b7da197d 100644 --- a/tests/intel/i915_pm_rps.c +++ b/tests/intel/i915_pm_rps.c @@ -322,7 +322,8 @@ static void load_helper_run(enum load load) spin[high_load] = __igt_spin_new(drm_fd, .ahnd = ahnd); if (lh.signal && high_load != prev_load) { - write(lh.link, &lh.signal, sizeof(lh.signal)); + igt_assert_eq(write(lh.link, &lh.signal, sizeof(lh.signal)), + sizeof(lh.signal)); lh.signal = false; } prev_load = high_load; @@ -690,9 +691,9 @@ static uint64_t __fence_order(int i915, obj->flags = flags1; gem_execbuf(i915, eb); - read(fd, before, sizeof(before)); + igt_assert_eq(read(fd, before, sizeof(before)), sizeof(before)); gem_sync(i915, obj->handle); - read(fd, after, sizeof(after)); + igt_assert_eq(read(fd, after, sizeof(after)), sizeof(after)); close(fd); after[0] -= before[0]; @@ -796,9 +797,9 @@ static uint64_t __engine_order(int i915, gem_execbuf(i915, eb); } - read(fd, before, sizeof(before)); + igt_assert_eq(read(fd, before, sizeof(before)), sizeof(before)); gem_sync(i915, obj->handle); - read(fd, after, sizeof(after)); + igt_assert_eq(read(fd, after, sizeof(after)), sizeof(after)); close(fd); after[0] -= before[0]; diff --git a/tests/intel/i915_query.c b/tests/intel/i915_query.c index f886297ed..4d706d62b 100644 --- a/tests/intel/i915_query.c +++ b/tests/intel/i915_query.c @@ -491,7 +491,7 @@ test_query_topology_matches_eu_total(int fd) free(topo_info); - igt_assert(n_eus_topology == n_eus); + igt_assert_eq(n_eus_topology, n_eus); } /* @@ -1380,7 +1380,7 @@ static void query_parse_and_validate_hwconfig_table(int i915) i915_query_items(i915, &item, 1); igt_assert(item.length == table_size); igt_info("Table size = %d bytes\n", table_size); - igt_assert(table_size > 0); + igt_assert_lt(0, table_size); /* HWConfig table is a list of KLV sets */ max_words = table_size / sizeof(uint32_t); @@ -1391,21 +1391,21 @@ static void query_parse_and_validate_hwconfig_table(int i915) igt_assert(data[i] < __INTEL_HWCONFIG_KEY_LIMIT); len = data[i + 1]; - igt_assert(len > 0); - igt_assert((i + 2 + len) <= max_words); + igt_assert_lt(0, len); + igt_assert_lte((i + 2 + len), max_words); igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]); value = data[i + 2]; switch (data[i]) { case INTEL_HWCONFIG_MEMORY_TYPE: - igt_assert(len == 1); + igt_assert_eq(len, 1); igt_assert(value < __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT); igt_info("%s\n", hwconfig_memtypes[value]); break; case INTEL_HWCONFIG_CACHE_TYPES: - igt_assert(len == 1); + igt_assert_eq(len, 1); if (!value) igt_info("-\n"); diff --git a/tests/intel/kms_big_fb.c b/tests/intel/kms_big_fb.c index 605813f7f..b808b4a02 100644 --- a/tests/intel/kms_big_fb.c +++ b/tests/intel/kms_big_fb.c @@ -307,7 +307,7 @@ static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width, igt_remove_fb(data->drm_fd, &col_fb); } - igt_assert(drmIoctl(data->drm_fd, DRM_IOCTL_MODE_ADDFB2, &f) == 0); + do_ioctl(data->drm_fd, DRM_IOCTL_MODE_ADDFB2, &f); newfb->fb_id = f.fb_id; } diff --git a/tests/intel/kms_busy.c b/tests/intel/kms_busy.c index db45e286e..5917b888f 100644 --- a/tests/intel/kms_busy.c +++ b/tests/intel/kms_busy.c @@ -388,7 +388,7 @@ static void gpu_engines_init_timeouts(int fd, int max_engines, *num_engines = 0; for_each_physical_engine(fd, e) { - igt_assert(*num_engines < max_engines); + igt_assert_lt(*num_engines, max_engines); props[*num_engines].engine = *e; props[*num_engines].preempt_timeout = 0; diff --git a/tests/intel/kms_ccs.c b/tests/intel/kms_ccs.c index c91370a9a..f262b271c 100644 --- a/tests/intel/kms_ccs.c +++ b/tests/intel/kms_ccs.c @@ -348,7 +348,7 @@ static void check_ccs_cc_plane(int drm_fd, igt_fb_t *fb, int plane, const float (uint8_t)(cc_color[1] * 0xff) << 8 | (uint8_t)(cc_color[2] * 0xff); - igt_assert(native_color == cc_p[4].d); + igt_assert_eq_u32(native_color, cc_p[4].d); igt_assert(gem_munmap(map, fb->size) == 0); }; diff --git a/tests/intel/kms_cdclk.c b/tests/intel/kms_cdclk.c index 7baf7d98e..6fe6e6c3f 100644 --- a/tests/intel/kms_cdclk.c +++ b/tests/intel/kms_cdclk.c @@ -236,9 +236,8 @@ static void test_mode_transition(data_t *data, enum pipe pipe, igt_output_t *out mode_hi = get_highres_mode(output); igt_require(mode_hi != NULL); - if (mode_hi->hdisplay == mode_lo->hdisplay && - mode_hi->vdisplay == mode_lo->vdisplay) - igt_skip("Highest and lowest mode resolutions are same; no transition\n"); + igt_skip_on_f(mode_hi->hdisplay == mode_lo->hdisplay && mode_hi->vdisplay == mode_lo->vdisplay, + "Highest and lowest mode resolutions are same; no transition\n"); primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); diff --git a/tests/intel/kms_dsc_helper.c b/tests/intel/kms_dsc_helper.c index 58057aca3..0de09b8e9 100644 --- a/tests/intel/kms_dsc_helper.c +++ b/tests/intel/kms_dsc_helper.c @@ -35,7 +35,7 @@ void save_force_dsc_en(int drmfd, igt_output_t *output) igt_is_force_dsc_enabled(drmfd, output->name); force_dsc_restore_fd = igt_get_dsc_debugfs_fd(drmfd, output->name); - igt_assert(force_dsc_restore_fd >= 0); + igt_assert_lte(0, force_dsc_restore_fd); } void restore_force_dsc_en(void) @@ -163,7 +163,7 @@ void save_force_dsc_fractional_bpp_en(int drmfd, igt_output_t *output) igt_is_force_dsc_fractional_bpp_enabled(drmfd, output->name); force_dsc_fractional_bpp_restore_fd = igt_get_dsc_fractional_bpp_debugfs_fd(drmfd, output->name); - igt_assert(force_dsc_fractional_bpp_restore_fd >= 0); + igt_assert_lte(0, force_dsc_fractional_bpp_restore_fd); } void restore_force_dsc_fractional_bpp_en(void) diff --git a/tests/intel/kms_fbcon_fbt.c b/tests/intel/kms_fbcon_fbt.c index 71e42f19c..edf6f8d4e 100644 --- a/tests/intel/kms_fbcon_fbt.c +++ b/tests/intel/kms_fbcon_fbt.c @@ -317,8 +317,7 @@ static void fbc_skips_on_fbcon(int debugfs_fd) for (i = 0; skip == false && i < ARRAY_SIZE(reasons); i++) skip = strstr(buf, reasons[i]); - if (skip) - igt_skip("fbcon modeset is not compatible with FBC\n"); + igt_skip_on_f(skip, "fbcon modeset is not compatible with FBC\n"); } static void psr_skips_on_fbcon(int debugfs_fd) diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c index e1318bfa6..1aef1e02d 100644 --- a/tests/intel/kms_pm_dc.c +++ b/tests/intel/kms_pm_dc.c @@ -230,11 +230,10 @@ static uint32_t get_dc_counter(char *dc_data) long ret; char *s = strchr(dc_data, ':'); - assert(s); + igt_assert(s); s++; ret = strtol(s, &e, 10); - assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) && - e > s && *e == '\n' && ret >= 0); + igt_assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) && e > s && *e == '\n' && ret >= 0); return ret; } @@ -611,8 +610,8 @@ static void test_deep_pkgc_state(data_t *data) } /* Skip the test if no VRR capable output is found */ - if (!vrr_supported) - igt_skip("No VRR capable output found, skipping the test.\n"); + igt_skip_on_f(!vrr_supported, + "No VRR capable output found, skipping the test.\n"); igt_display_reset(display); diff --git a/tests/intel/kms_pm_rpm.c b/tests/intel/kms_pm_rpm.c index 66c68b902..5af3e81bc 100644 --- a/tests/intel/kms_pm_rpm.c +++ b/tests/intel/kms_pm_rpm.c @@ -1527,7 +1527,7 @@ static void pm_test_tiling(void) gem_set_tiling(drm_fd, handles[j], tiling_modes[i], stride); gem_get_tiling(drm_fd, handles[j], &ti, &sw); - igt_assert(tiling_modes[i] == ti); + igt_assert_eq_u32(tiling_modes[i], ti); } enable_one_screen_and_wait(&ms_data); diff --git a/tests/intel/kms_psr.c b/tests/intel/kms_psr.c index f3caa9ecc..cf0ce4bb8 100644 --- a/tests/intel/kms_psr.c +++ b/tests/intel/kms_psr.c @@ -499,27 +499,27 @@ static void fill_render(data_t *data, const struct igt_fb *fb, static bool psr_wait_entry_if_enabled(data_t *data) { - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", - data->op_psr_mode); + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), + "enable_psr modparam doesn't allow psr mode %d\n", + data->op_psr_mode); return psr_wait_entry(data->debugfs_fd, data->op_psr_mode, data->output); } static bool psr_wait_update_if_enabled(data_t *data) { - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", - data->op_psr_mode); + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), + "enable_psr modparam doesn't allow psr mode %d\n", + data->op_psr_mode); return psr_wait_update(data->debugfs_fd, data->op_psr_mode, data->output); } static bool psr_enable_if_enabled(data_t *data) { - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", - data->op_psr_mode); + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), + "enable_psr modparam doesn't allow psr mode %d\n", + data->op_psr_mode); return psr_enable(data->drm_fd, data->debugfs_fd, data->op_psr_mode, data->output); } diff --git a/tests/intel/perf.c b/tests/intel/perf.c index 95b17f522..c5a103c94 100644 --- a/tests/intel/perf.c +++ b/tests/intel/perf.c @@ -493,12 +493,12 @@ __perf_open(int fd, struct drm_i915_perf_open_param *param, bool prevent_pm) ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param); - igt_assert(ret >= 0); + igt_assert_lte(0, ret); errno = 0; if (prevent_pm) { pm_fd = open("/dev/cpu_dma_latency", O_RDWR); - igt_assert(pm_fd >= 0); + igt_assert_lte(0, pm_fd); igt_assert_eq(write(pm_fd, &pm_value, sizeof(pm_value)), sizeof(pm_value)); } @@ -625,7 +625,7 @@ elapsed_delta(uint64_t t1, uint64_t t0, uint32_t width) { uint32_t max_bits = sizeof(t1) * 8; - igt_assert(width <= max_bits); + igt_assert_lte_u32(width, max_bits); if (t1 < t0 && width != max_bits) return ((1ULL << width) - t0) + t1; @@ -2128,7 +2128,7 @@ test_oa_exponents(const struct intel_execution_engine2 *e) /* igt_debug(" > read %i bytes\n", ret); */ /* We should never have no data. */ - igt_assert(ret > 0); + igt_assert_lt(0, ret); for (int offset = 0; offset < ret && n_timer_reports < NUM_TIMER_REPORTS; @@ -2472,7 +2472,7 @@ test_blocking(uint64_t requested_oa_period, errno == EINTR) ; - igt_assert(ret > 0); + igt_assert_lt(0, ret); /* For Haswell reports don't contain a well defined reason * field we so assume all reports to be 'periodic'. For gen8+ @@ -2526,12 +2526,12 @@ test_blocking(uint64_t requested_oa_period, /* With completely broken blocking (but also not returning an error) we * could end up with an open loop, */ - igt_assert(n <= (max_iterations + n_extra_iterations)); + igt_assert_lte(n, (max_iterations + n_extra_iterations)); /* Make sure the driver is reporting new samples with a reasonably * low latency... */ - igt_assert(n > (min_iterations + n_extra_iterations)); + igt_assert_lt((min_iterations + n_extra_iterations), n); if (!set_kernel_hrtimer) igt_assert(kernel_ns <= (test_duration_ns / 100ull)); @@ -2728,12 +2728,12 @@ test_polling(uint64_t requested_oa_period, /* With completely broken blocking while polling (but still somehow * reporting a POLLIN event) we could end up with an open loop. */ - igt_assert(n <= (max_iterations + n_extra_iterations)); + igt_assert_lte(n, (max_iterations + n_extra_iterations)); /* Make sure the driver is reporting new samples with a reasonably * low latency... */ - igt_assert(n > (min_iterations + n_extra_iterations)); + igt_assert_lt((min_iterations + n_extra_iterations), n); if (!set_kernel_hrtimer) igt_assert(kernel_ns <= (test_duration_ns / 100ull)); @@ -2821,7 +2821,7 @@ num_valid_reports_captured(struct drm_i915_perf_open_param *param, errno == EINTR) ; - igt_assert(ret > 0); + igt_assert_lt(0, ret); for (int offset = 0; offset < ret; offset += header->size) { header = (void *)(buf + offset); @@ -3343,7 +3343,7 @@ test_short_reads(void) ret = read(stream_fd, header, page_size); - igt_assert(ret > 0); + igt_assert_lt(0, ret); } while (header->type == DRM_I915_PERF_RECORD_OA_REPORT_LOST); igt_assert_eq(ret, record_size); @@ -5001,7 +5001,7 @@ static int i915_perf_add_config(int fd, struct drm_i915_perf_oa_config *config) int config_id = __i915_perf_add_config(fd, config); igt_debug("config_id=%i\n", config_id); - igt_assert(config_id > 0); + igt_assert_lt(0, config_id); return config_id; } @@ -5339,7 +5339,7 @@ test_whitelisted_registers_userspace_config(void) /* Create a new config */ ret = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, &config); - igt_assert(ret > 0); /* Config 0 should be used by the kernel */ + igt_assert_lt(0, ret); /* Config 0 should be used by the kernel */ config_id = ret; i915_perf_remove_config(drm_fd, config_id); @@ -5360,7 +5360,7 @@ read_i915_module_ref(void) if (strncmp(line, "i915 ", 5) == 0) { unsigned long mem; int ret = sscanf(line + 5, "%lu %u", &mem, &ref_count); - igt_assert(ret == 2); + igt_assert_eq(ret, 2); goto done; } } @@ -5381,7 +5381,7 @@ static int perf_sysfs_open(int i915) for_each_sysfs_gt_dirfd(i915, dirfd, gt) break; - igt_assert(dirfd != -1); + igt_assert_neq(dirfd, -1); return dirfd; } @@ -5784,7 +5784,7 @@ test_group_exclusive_stream(const intel_ctx_t *ctx, bool exponent) grp->perf_fd = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m); - igt_assert(grp->perf_fd >= 0); + igt_assert_lte(0, grp->perf_fd); igt_debug("opened OA buffer with c:i %d:%d\n", ci->engine_class, ci->engine_instance); } @@ -5826,7 +5826,7 @@ test_group_exclusive_stream(const intel_ctx_t *ctx, bool exponent) param.num_properties = ARRAY_SIZE(properties) / 2 - 1; errno = 0; err = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m); - igt_assert(err < 0); + igt_assert_lt(err, 0); igt_assert(errno == EBUSY || errno == ENODEV); igt_debug("try OA ci unit with c:i %d:%d\n", ci->engine_class, ci->engine_instance); diff --git a/tests/intel/perf_pmu.c b/tests/intel/perf_pmu.c index e3f51d0c7..bfa2d501a 100644 --- a/tests/intel/perf_pmu.c +++ b/tests/intel/perf_pmu.c @@ -200,7 +200,7 @@ static char *get_drpc(int i915, int gt_id) int gt_dir; gt_dir = igt_debugfs_gt_dir(i915, gt_id); - igt_assert(gt_dir != -1); + igt_assert_neq(gt_dir, -1); return igt_sysfs_get(gt_dir, "drpc"); } @@ -210,7 +210,7 @@ static int open_pmu(int i915, uint64_t config) fd = perf_i915_open(i915, config); igt_skip_on(fd < 0 && errno == ENODEV); - igt_assert(fd >= 0); + igt_assert_lte(0, fd); return fd; } @@ -221,7 +221,7 @@ static int open_group(int i915, uint64_t config, int group) fd = perf_i915_open_group(i915, config, group); igt_skip_on(fd < 0 && errno == ENODEV); - igt_assert(fd >= 0); + igt_assert_lte(0, fd); return fd; } @@ -527,7 +527,7 @@ static void log_busy(unsigned int num_engines, uint64_t *val) int len; len = snprintf(p, rem, "%u=%" PRIu64 "\n", i, val[i]); - igt_assert(len > 0); + igt_assert_lt(0, len); rem -= len; p += len; } @@ -950,7 +950,7 @@ __sema_busy(int gem_fd, uint64_t ahnd, int pmu, const intel_ctx_t *ctx, int timeout = 3; /* Time spent being busy includes time waiting on semaphores */ - igt_assert(busy_pct >= sema_pct); + igt_assert_lte(sema_pct, busy_pct); gem_quiescent_gpu(gem_fd); @@ -1359,7 +1359,7 @@ static void open_invalid(int i915) int fd; fd = perf_i915_open(i915, -1ULL); - igt_assert(fd < 0); + igt_assert_lt(fd, 0); } static bool cpu0_hotplug_support(void) @@ -1415,7 +1415,7 @@ static void cpu_hotplug(int gem_fd) cpu), sizeof(name)); cpufd = open(name, O_WRONLY); if (cpufd == -1) { - igt_assert(cpu > 0); + igt_assert_lt(0, cpu); /* * Signal parent that we cycled through all * CPUs and we are done. @@ -1534,7 +1534,7 @@ test_interrupts(int gem_fd) close(old_fd); } - igt_assert(fence_fd >= 0); + igt_assert_lte(0, fence_fd); } /* Wait for idle state. */ @@ -1755,9 +1755,9 @@ test_frequency(int gem_fd, unsigned int gt) */ __igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq); __igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz", &read_value); - if (read_value != min_freq) - igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n", - min_freq, read_value); + igt_warn_on_f(read_value != min_freq, + "Unable to restore min frequency to saved value [%u MHz], now %u MHz\n", + min_freq, read_value); close(fd[0]); close(fd[1]); put_ahnd(ahnd); @@ -1880,7 +1880,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) continue; if (gt_ == gt) { - igt_assert(test_idx == -1); + igt_assert_eq(test_idx, -1); test_idx = pmus; } @@ -1890,7 +1890,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) igt_skip_on(fd[pmus] < 0 && errno == ENODEV); pmus++; } - igt_assert(test_idx >= 0); + igt_assert_lte(0, test_idx); if (flags & TEST_RUNTIME_PM) { drmModeRes *res; @@ -1981,7 +1981,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) continue; fw[gt_] = open_forcewake_handle(gem_fd, gt_); - igt_assert(fw[gt_] >= 0); + igt_assert_lte(0, fw[gt_]); } usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */ @@ -2206,7 +2206,8 @@ accuracy(int gem_fd, const intel_ctx_t *ctx, 100 * expected, target_busy_pct, avg, sqrt(var / n)); - write(link[1], &expected, sizeof(expected)); + igt_assert_eq(write(link[1], &expected, sizeof(expected)), + sizeof(expected)); } igt_spin_free(gem_fd, spin); @@ -2216,12 +2217,14 @@ accuracy(int gem_fd, const intel_ctx_t *ctx, fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance)); /* Let the child run. */ - read(link[0], &expected, sizeof(expected)); + igt_assert_eq(read(link[0], &expected, sizeof(expected)), + sizeof(expected)); assert_within(100.0 * expected, target_busy_pct, 5); /* Collect engine busyness for an interesting part of child runtime. */ val[0] = __pmu_read_single(fd, &ts[0]); - read(link[0], &expected, sizeof(expected)); + igt_assert_eq(read(link[0], &expected, sizeof(expected)), + sizeof(expected)); val[1] = __pmu_read_single(fd, &ts[1]); close(fd); diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c index beccfcb1a..a55ee5abd 100644 --- a/tests/intel/xe_ccs.c +++ b/tests/intel/xe_ccs.c @@ -212,7 +212,7 @@ static void surf_copy(int xe, WRITE_PNG(xe, run_id, "corrupted", &blt.dst, dst->x2, dst->y2, bpp); result = memcmp(src->ptr, dst->ptr, src->size); if (blt_platform_has_flat_ccs_enabled(xe)) - igt_assert(result != 0); + igt_assert_neq(result, 0); /* In case of suspend_resume, buffer object would become * uncompressed in xe2+ dgfx, and therefore retrieve the @@ -696,7 +696,7 @@ static int opt_handler(int opt, int opt_index, void *data) case 'f': param.compression_format = atoi(optarg); igt_debug("Compression format: %d\n", param.compression_format); - igt_assert((param.compression_format & ~0x1f) == 0); + igt_assert_eq((param.compression_format & ~0x1f), 0); break; case 'p': param.write_png = true; diff --git a/tests/intel/xe_debugfs.c b/tests/intel/xe_debugfs.c index a7d56a0be..a7c567c45 100644 --- a/tests/intel/xe_debugfs.c +++ b/tests/intel/xe_debugfs.c @@ -222,7 +222,7 @@ test_forcewake(int fd) { int handle = igt_debugfs_open(fd, "forcewake_all", O_WRONLY); - igt_assert(handle != -1); + igt_assert_neq(handle, -1); close(handle); } diff --git a/tests/intel/xe_dma_buf_sync.c b/tests/intel/xe_dma_buf_sync.c index f0d3f0d54..7af80dd2f 100644 --- a/tests/intel/xe_dma_buf_sync.c +++ b/tests/intel/xe_dma_buf_sync.c @@ -108,7 +108,7 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, } *data [MAX_N_BO]; int i; - igt_assert(n_bo <= MAX_N_BO); + igt_assert_lte(n_bo, MAX_N_BO); for (i = 0; i < N_FD; ++i) { fd[i] = drm_open_driver(DRIVER_XE); diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c index eebdbc84b..f0c66c49e 100644 --- a/tests/intel/xe_evict.c +++ b/tests/intel/xe_evict.c @@ -57,7 +57,7 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci, } *data; int i, b; - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); bo = calloc(n_execs / 2, sizeof(*bo)); igt_assert(bo); @@ -237,7 +237,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, } *data; int i, b; - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); bo = calloc(n_execs / 2, sizeof(*bo)); igt_assert(bo); diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c index a6dbd748b..73f69e7b0 100644 --- a/tests/intel/xe_exec_balancer.c +++ b/tests/intel/xe_exec_balancer.c @@ -190,7 +190,7 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs, struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; int i, j, b, num_placements = 0; - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); xe_for_each_engine(fd, hwe) { if (hwe->engine_class != class || hwe->gt_id != gt) @@ -410,7 +410,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, int i, j, b, num_placements = 0; int map_fd = -1; - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); xe_for_each_engine(fd, hwe) { if (hwe->engine_class != class || hwe->gt_id != gt) @@ -534,7 +534,8 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, if (flags & RACE) { map_fd = open("/tmp", O_TMPFILE | O_RDWR, 0x666); - write(map_fd, data, bo_size); + igt_assert_eq(write(map_fd, data, bo_size), + bo_size); data = mmap((void *)MAP_ADDRESS, bo_size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, map_fd, 0); diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c index 0fd1ae062..dfbd68d1d 100644 --- a/tests/intel/xe_exec_basic.c +++ b/tests/intel/xe_exec_basic.c @@ -122,8 +122,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, } *data; int i, b; - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); - igt_assert(n_vm <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); + igt_assert_lte(n_vm, MAX_N_EXEC_QUEUES); for (i = 0; i < n_vm; ++i) vm[i] = xe_vm_create(fd, 0, 0); diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c index 389de7ca4..b92feee2c 100644 --- a/tests/intel/xe_exec_compute_mode.c +++ b/tests/intel/xe_exec_compute_mode.c @@ -115,7 +115,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, int map_fd = -1; int64_t fence_timeout; - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); bo_size = sizeof(*data) * n_execs; @@ -243,7 +243,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, if (flags & RACE) { map_fd = open("/tmp", O_TMPFILE | O_RDWR, 0x666); - write(map_fd, data, bo_size); + igt_assert_eq(write(map_fd, data, bo_size), + bo_size); data = mmap((void *)MAP_ADDRESS, bo_size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, map_fd, 0); @@ -457,7 +458,7 @@ static void lr_mode_workload(int fd) ts_1 = spin->timestamp; sleep(1); ts_2 = spin->timestamp; - igt_assert(ts_1 != ts_2); + igt_assert_neq_u32(ts_1, ts_2); xe_spin_end(spin); xe_wait_ufence(fd, &spin->exec_sync, USER_FENCE_VALUE, 0, ONE_SEC); @@ -466,7 +467,7 @@ static void lr_mode_workload(int fd) ts_1 = spin->timestamp; sleep(1); ts_2 = spin->timestamp; - igt_assert(ts_1 == ts_2); + igt_assert_eq_u32(ts_1, ts_2); sync.addr = to_user_pointer(&vm_sync); xe_vm_unbind_async(fd, vm, 0, 0, spin_addr, bo_size, &sync, 1); diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c index b022f97d3..56bad2b75 100644 --- a/tests/intel/xe_exec_fault_mode.c +++ b/tests/intel/xe_exec_fault_mode.c @@ -140,7 +140,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, int i, j, b; int map_fd = -1; - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); if (flags & ENABLE_SCRATCH) vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE | @@ -291,7 +291,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, if (flags & RACE) { map_fd = open("/tmp", O_TMPFILE | O_RDWR, 0x666); - write(map_fd, data, bo_size); + igt_assert_eq(write(map_fd, data, bo_size), + bo_size); data = mmap((void *)MAP_ADDRESS, bo_size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, map_fd, 0); diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c index dcb22f275..72f2133e5 100644 --- a/tests/intel/xe_exec_reset.c +++ b/tests/intel/xe_exec_reset.c @@ -155,7 +155,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; int i, j, b, num_placements = 0, bad_batches = 1; - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); if (flags & CLOSE_FD) fd = drm_open_driver(DRIVER_XE); @@ -326,7 +326,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, struct xe_spin_opts spin_opts = { .preempt = false }; int i, b; - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); if (flags & CLOSE_FD) fd = drm_open_driver(DRIVER_XE); @@ -475,7 +475,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, struct xe_spin_opts spin_opts = { .preempt = false }; int i, b; - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); if (flags & CLOSE_FD) fd = drm_open_driver(DRIVER_XE); @@ -704,7 +704,7 @@ gt_reset(int fd, int n_threads, int n_sec) for (i = 0; i < n_threads; i++) pthread_join(threads[i].thread, NULL); - printf("number of resets %d\n", num_reset); + igt_info("number of resets %d\n", num_reset); free(threads); } diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c index c872c22d5..5c1dd0a01 100644 --- a/tests/intel/xe_exec_store.c +++ b/tests/intel/xe_exec_store.c @@ -249,7 +249,7 @@ static void store_cachelines(int fd, struct drm_xe_engine_class_instance *eci, object_index = n % (count - 1); ptr[n] = bo_map[object_index] + delta / 4; - igt_assert(*ptr[n] == value[n]); + igt_assert_eq_u32(*ptr[n], value[n]); } for (i = 0; i < count; i++) { diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c index e7a0a7cd0..6e53d3cf8 100644 --- a/tests/intel/xe_exec_threads.c +++ b/tests/intel/xe_exec_threads.c @@ -70,7 +70,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr, int i, j, b, num_placements = 0; bool owns_vm = false, owns_fd = false; - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); if (flags & FD) { fd = drm_reopen_driver(fd); @@ -88,7 +88,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr, eci[num_placements++] = *hwe; } - igt_assert(num_placements > 1); + igt_assert_lt(1, num_placements); bo_size = sizeof(*data) * n_execs; bo_size = xe_bb_size(fd, bo_size); @@ -272,7 +272,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, int map_fd = -1; bool owns_vm = false, owns_fd = false; - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); if (flags & FD) { fd = drm_reopen_driver(fd); @@ -396,7 +396,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, if (flags & RACE) { map_fd = open("/tmp", O_TMPFILE | O_RDWR, 0x666); - write(map_fd, data, bo_size); + igt_assert_eq(write(map_fd, data, bo_size), + bo_size); data = mmap(from_user_pointer(userptr), bo_size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, @@ -476,7 +477,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, int i, j, b, hang_exec_queue = n_exec_queues / 2; bool owns_vm = false, owns_fd = false; - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); if (flags & FD) { fd = drm_reopen_driver(fd); diff --git a/tests/intel/xe_gt_freq.c b/tests/intel/xe_gt_freq.c index 93ebb5ed0..365c9b9e6 100644 --- a/tests/intel/xe_gt_freq.c +++ b/tests/intel/xe_gt_freq.c @@ -41,7 +41,7 @@ static int set_freq(int fd, int gt_id, const char *freq_name, uint32_t freq) snprintf(freq_attr, sizeof(freq_attr), "freq0/%s_freq", freq_name); gt_fd = xe_sysfs_gt_open(fd, gt_id); - igt_assert(gt_fd >= 0); + igt_assert_lte(0, gt_fd); while (ret == -EAGAIN) ret = igt_sysfs_printf(gt_fd, freq_attr, "%u", freq); @@ -59,7 +59,7 @@ static uint32_t get_freq(int fd, int gt_id, const char *freq_name) snprintf(freq_attr, sizeof(freq_attr), "freq0/%s_freq", freq_name); gt_fd = xe_sysfs_gt_open(fd, gt_id); - igt_assert(gt_fd >= 0); + igt_assert_lte(0, gt_fd); while (err == -EAGAIN) err = igt_sysfs_scanf(gt_fd, freq_attr, "%u", &freq); @@ -84,7 +84,7 @@ static uint32_t get_throttle(int fd, int gt_id, const char *throttle_file) snprintf(throttle_attr, sizeof(throttle_attr), "freq0/throttle/%s", throttle_file); gt_fd = xe_sysfs_gt_open(fd, gt_id); - igt_assert(gt_fd >= 0); + igt_assert_lte(0, gt_fd); igt_sysfs_scanf(gt_fd, throttle_attr, "%u", &val); @@ -134,26 +134,26 @@ static void test_freq_basic_api(int fd, int gt_id) * RPn is the floor * RP0 is the ceiling */ - igt_assert(set_freq(fd, gt_id, "min", rpn - 1) < 0); - igt_assert(set_freq(fd, gt_id, "min", rp0 + 1) < 0); - igt_assert(set_freq(fd, gt_id, "max", rpn - 1) < 0); - igt_assert(set_freq(fd, gt_id, "max", rp0 + 1) < 0); + igt_assert_lt(set_freq(fd, gt_id, "min", rpn - 1), 0); + igt_assert_lt(set_freq(fd, gt_id, "min", rp0 + 1), 0); + igt_assert_lt(set_freq(fd, gt_id, "max", rpn - 1), 0); + igt_assert_lt(set_freq(fd, gt_id, "max", rp0 + 1), 0); /* Assert min requests are respected from rp0 to rpn */ - igt_assert(set_freq(fd, gt_id, "min", rp0) > 0); - igt_assert(get_freq(fd, gt_id, "min") == rp0); - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); - igt_assert(get_freq(fd, gt_id, "min") == rpe(fd, gt_id)); - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); - igt_assert(get_freq(fd, gt_id, "min") == rpn); + igt_assert_lt(0, set_freq(fd, gt_id, "min", rp0)); + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rp0); + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpe(fd, gt_id)); + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpn); /* Assert max requests are respected from rpn to rp0 */ - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); - igt_assert(get_freq(fd, gt_id, "max") == rpn); - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); - igt_assert(get_freq(fd, gt_id, "max") == rpe(fd, gt_id)); - igt_assert(set_freq(fd, gt_id, "max", rp0) > 0); - igt_assert(get_freq(fd, gt_id, "max") == rp0); + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpn); + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpe(fd, gt_id)); + igt_assert_lt(0, set_freq(fd, gt_id, "max", rp0)); + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rp0); } /** @@ -176,10 +176,10 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle) * Then we check if hardware is actually operating at the desired freq * And let's do this for all the 3 known Render Performance (RP) values. */ - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); usleep(ACT_FREQ_LATENCY_US); - igt_assert(get_freq(fd, gt_id, "cur") == rpn); + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpn); if (gt_idle) { /* Wait for GT to go in C6 as previous get_freq wakes up GT*/ @@ -187,31 +187,31 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle) "GT %d should be in C6\n", gt_id); igt_assert(get_freq(fd, gt_id, "act") == 0); } else { - igt_assert(get_freq(fd, gt_id, "act") == rpn); + igt_assert_eq_u32(get_freq(fd, gt_id, "act"), rpn); } - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); usleep(ACT_FREQ_LATENCY_US); - igt_assert(get_freq(fd, gt_id, "cur") == rpe(fd, gt_id)); + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpe(fd, gt_id)); if (gt_idle) { igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10), "GT %d should be in C6\n", gt_id); igt_assert(get_freq(fd, gt_id, "act") == 0); } else { - igt_assert(get_freq(fd, gt_id, "act") == rpe(fd, gt_id)); + igt_assert_eq_u32(get_freq(fd, gt_id, "act"), rpe(fd, gt_id)); } - igt_assert(set_freq(fd, gt_id, "min", rp0) > 0); - igt_assert(set_freq(fd, gt_id, "max", rp0) > 0); + igt_assert_lt(0, set_freq(fd, gt_id, "min", rp0)); + igt_assert_lt(0, set_freq(fd, gt_id, "max", rp0)); usleep(ACT_FREQ_LATENCY_US); /* * It is unlikely that PCODE will *always* respect any request above RPe * So for this level let's only check if GuC PC is doing its job * and respecting our request, by propagating it to the hardware. */ - igt_assert(get_freq(fd, gt_id, "cur") == rp0); + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rp0); if (gt_idle) { igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10), @@ -236,8 +236,8 @@ static void test_freq_range(int fd, int gt_id, bool gt_idle) igt_debug("Starting testing range request\n"); - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); usleep(ACT_FREQ_LATENCY_US); cur = get_freq(fd, gt_id, "cur"); igt_assert(rpn <= cur && cur <= rpe(fd, gt_id)); @@ -267,12 +267,12 @@ static void test_freq_low_max(int fd, int gt_id) * When max request < min request, max is ignored and min works like * a fixed one. Let's assert this assumption */ - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); usleep(ACT_FREQ_LATENCY_US); /* Refresh value of rpe, pcode could have adjusted it */ - igt_assert(get_freq(fd, gt_id, "cur") == rpe(fd, gt_id)); + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpe(fd, gt_id)); } /** @@ -284,16 +284,16 @@ static void test_suspend(int fd, int gt_id) { uint32_t rpn = get_freq(fd, gt_id, "rpn"); - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); usleep(ACT_FREQ_LATENCY_US); - igt_assert(get_freq(fd, gt_id, "cur") == rpn); + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpn); igt_system_suspend_autoresume(SUSPEND_STATE_S3, SUSPEND_TEST_NONE); - igt_assert(get_freq(fd, gt_id, "min") == rpn); - igt_assert(get_freq(fd, gt_id, "max") == rpn); + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpn); + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpn); } /** diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c index 647fd64e7..845052bf2 100644 --- a/tests/intel/xe_intel_bb.c +++ b/tests/intel/xe_intel_bb.c @@ -674,11 +674,11 @@ static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling) /* We'll fail on src <-> final compare so just warn */ if (tiling == I915_TILING_NONE) { - if (compare_bufs(&src, &dst, false) > 0) - igt_warn("none->none blit failed!"); + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, + "none->none blit failed!"); } else { - if (compare_bufs(&src, &dst, false) == 0) - igt_warn("none->tiled blit failed!"); + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, + "none->tiled blit failed!"); } fails = compare_bufs(&src, &final, true); @@ -925,11 +925,11 @@ static int render(struct buf_ops *bops, uint32_t tiling, /* We'll fail on src <-> final compare so just warn */ if (tiling == I915_TILING_NONE) { - if (compare_bufs(&src, &dst, false) > 0) - igt_warn("%s: none->none failed!\n", __func__); + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, + "%s: none->none failed!\n", __func__); } else { - if (compare_bufs(&src, &dst, false) == 0) - igt_warn("%s: none->tiled failed!\n", __func__); + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, + "%s: none->tiled failed!\n", __func__); } fails = compare_bufs(&src, &final, true); diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c index ff2218300..e26ebceb9 100644 --- a/tests/intel/xe_oa.c +++ b/tests/intel/xe_oa.c @@ -492,12 +492,12 @@ __perf_open(int fd, struct intel_xe_oa_open_prop *param, bool prevent_pm) ret = intel_xe_perf_ioctl(fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, param); - igt_assert(ret >= 0); + igt_assert_lte(0, ret); errno = 0; if (prevent_pm) { pm_fd = open("/dev/cpu_dma_latency", O_RDWR); - igt_assert(pm_fd >= 0); + igt_assert_lte(0, pm_fd); igt_assert_eq(write(pm_fd, &pm_value, sizeof(pm_value)), sizeof(pm_value)); } @@ -568,7 +568,7 @@ elapsed_delta(uint64_t t1, uint64_t t0, uint32_t width) { uint32_t max_bits = sizeof(t1) * 8; - igt_assert(width <= max_bits); + igt_assert_lte_u32(width, max_bits); if (t1 < t0 && width != max_bits) return ((1ULL << width) - t0) + t1; @@ -1710,7 +1710,7 @@ static void test_oa_exponents(const struct drm_xe_engine_class_instance *hwe) /* igt_debug(" > read %i bytes\n", ret); */ /* We should never have no data. */ - igt_assert(ret > 0); + igt_assert_lt(0, ret); for (int offset = 0; offset < ret && n_timer_reports < NUM_TIMER_REPORTS; @@ -1933,7 +1933,7 @@ static void test_blocking(uint64_t requested_oa_period, while ((ret = read(perf_fd, buf, sizeof(buf))) < 0 && (errno == EINTR || errno == EIO)) ; - igt_assert(ret > 0); + igt_assert_lt(0, ret); for (int offset = 0; offset < ret; offset += format_size) { uint32_t *report = (void *)(buf + offset); @@ -1972,12 +1972,12 @@ static void test_blocking(uint64_t requested_oa_period, /* With completely broken blocking (but also not returning an error) we * could end up with an open loop, */ - igt_assert(n <= (max_iterations + n_extra_iterations)); + igt_assert_lte(n, (max_iterations + n_extra_iterations)); /* Make sure the driver is reporting new samples with a reasonably * low latency... */ - igt_assert(n > (min_iterations + n_extra_iterations)); + igt_assert_lt((min_iterations + n_extra_iterations), n); if (!set_kernel_hrtimer) igt_assert(kernel_ns <= (test_duration_ns / 100ull)); @@ -2163,12 +2163,12 @@ static void test_polling(uint64_t requested_oa_period, /* With completely broken blocking while polling (but still somehow * reporting a POLLIN event) we could end up with an open loop. */ - igt_assert(n <= (max_iterations + n_extra_iterations)); + igt_assert_lte(n, (max_iterations + n_extra_iterations)); /* Make sure the driver is reporting new samples with a reasonably * low latency... */ - igt_assert(n > (min_iterations + n_extra_iterations)); + igt_assert_lt((min_iterations + n_extra_iterations), n); if (!set_kernel_hrtimer) igt_assert(kernel_ns <= (test_duration_ns / 100ull)); @@ -2260,7 +2260,7 @@ num_valid_reports_captured(struct intel_xe_oa_open_prop *param, (errno == EINTR || errno == EIO)) ; - igt_assert(ret > 0); + igt_assert_lt(0, ret); for (int offset = 0; offset < ret; offset += format_size) { uint32_t *report = (void *)(buf + offset); @@ -3473,7 +3473,7 @@ static int xe_oa_add_config(int fd, struct drm_xe_oa_config *config) int config_id = __xe_oa_add_config(fd, config); igt_debug("config_id=%i\n", config_id); - igt_assert(config_id > 0); + igt_assert_lt(0, config_id); return config_id; } @@ -3769,7 +3769,7 @@ test_whitelisted_registers_userspace_config(void) /* Create a new config */ ret = intel_xe_perf_ioctl(drm_fd, DRM_XE_OBSERVATION_OP_ADD_CONFIG, &config); - igt_assert(ret > 0); /* Config 0 should be used by the kernel */ + igt_assert_lt(0, ret); /* Config 0 should be used by the kernel */ config_id = ret; xe_oa_remove_config(drm_fd, config_id); @@ -4195,7 +4195,7 @@ test_oa_unit_exclusive_stream(bool exponent) properties[11] = exec_q[i]; errno = 0; err = intel_xe_perf_ioctl(drm_fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, ¶m); - igt_assert(err < 0); + igt_assert_lt(err, 0); igt_assert(errno == EBUSY || errno == ENODEV); poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); } diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c index 82155f1d5..153d9ce1d 100644 --- a/tests/intel/xe_pat.c +++ b/tests/intel/xe_pat.c @@ -808,7 +808,7 @@ static void display_vs_wb_transient(int fd) /* c0 -> c6 might flush caches */ fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY); - igt_assert(fw_handle >= 0); + igt_assert_lte(0, fw_handle); render_copy(ibb, &src, diff --git a/tests/intel/xe_peer2peer.c b/tests/intel/xe_peer2peer.c index 6ff4774bb..2a941abe6 100644 --- a/tests/intel/xe_peer2peer.c +++ b/tests/intel/xe_peer2peer.c @@ -279,7 +279,7 @@ static char *region_name(int xe, uint32_t region) r = snprintf(name, len, "%s", xe_region_name(region)); - igt_assert(r > 0); + igt_assert_lt(0, r); return name; } diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c index 8b115e2f6..eee89428c 100644 --- a/tests/intel/xe_pm.c +++ b/tests/intel/xe_pm.c @@ -94,7 +94,7 @@ static uint64_t get_vram_d3cold_threshold(int sysfs) igt_require_f(!faccessat(sysfs, path, R_OK, 0), "vram_d3cold_threshold is not present\n"); ret = igt_sysfs_scanf(sysfs, path, "%lu", &threshold); - igt_assert(ret > 0); + igt_assert_lt(0, ret); return threshold; } @@ -111,7 +111,7 @@ static void set_vram_d3cold_threshold(int sysfs, uint64_t threshold) else igt_warn("vram_d3cold_threshold is not present\n"); - igt_assert(ret > 0); + igt_assert_lt(0, ret); } static void vram_d3cold_threshold_restore(int sig) @@ -305,8 +305,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci, bool check_rpm = (d_state == IGT_ACPI_D3Hot || d_state == IGT_ACPI_D3Cold); - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); - igt_assert(n_execs > 0); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); + igt_assert_lt(0, n_execs); if (check_rpm) { igt_assert(in_d3(device, d_state)); @@ -507,7 +507,7 @@ static void test_vram_d3cold_threshold(device_t device, int sysfs_fd) * Therefore open and close fw handle to wake the device. */ fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); - igt_assert(fw_handle >= 0); + igt_assert_lte(0, fw_handle); active = igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE; close(fw_handle); igt_assert(active); @@ -557,7 +557,7 @@ static void test_mmap(device_t device, uint32_t placement, uint32_t flags, fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); - igt_assert(fw_handle >= 0); + igt_assert_lte(0, fw_handle); igt_assert(igt_pm_get_runtime_active_time(device.pci_xe) > active_time); @@ -600,7 +600,7 @@ static void test_mmap(device_t device, uint32_t placement, uint32_t flags, /* Runtime resume and check the pattern */ fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); - igt_assert(fw_handle >= 0); + igt_assert_lte(0, fw_handle); igt_assert(igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE); for (i = 0; i < bo_size / sizeof(*map); i++) igt_assert(map[i] == MAGIC_2); @@ -651,7 +651,7 @@ static void test_mocs_suspend_resume(device_t device, enum igt_suspend_state s_s active_time = igt_pm_get_runtime_active_time(device.pci_xe); fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); - igt_assert(fw_handle >= 0); + igt_assert_lte(0, fw_handle); igt_assert(igt_pm_get_runtime_active_time(device.pci_xe) > active_time); diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c index 51735d887..1d3ce0762 100644 --- a/tests/intel/xe_pm_residency.c +++ b/tests/intel/xe_pm_residency.c @@ -182,7 +182,7 @@ static unsigned long read_idle_residency(int fd, int gt) int gt_fd; gt_fd = xe_sysfs_gt_open(fd, gt); - igt_assert(gt_fd >= 0); + igt_assert_lte(0, gt_fd); igt_assert(igt_sysfs_scanf(gt_fd, "gtidle/idle_residency_ms", "%lu", &residency) == 1); close(gt_fd); @@ -280,7 +280,7 @@ static void toggle_gt_c6(int fd, int n) do { fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY); - igt_assert(fw_handle >= 0); + igt_assert_lte(0, fw_handle); /* check if all gts are in C0 after forcewake is acquired */ xe_for_each_gt(fd, gt) igt_assert_f(!xe_is_gt_in_c6(fd, gt), diff --git a/tests/intel/xe_query.c b/tests/intel/xe_query.c index c13613e0a..c6d88b258 100644 --- a/tests/intel/xe_query.c +++ b/tests/intel/xe_query.c @@ -198,7 +198,7 @@ test_query_engines(int fd) hwe->gt_id); } - igt_assert(i > 0); + igt_assert_lt(0, i); } /** @@ -464,15 +464,15 @@ test_query_gt_topology_l3_bank_mask(int fd) igt_info(" count: %d\n", count); if (intel_get_device_info(dev_id)->graphics_ver < 20) { - igt_assert(count > 0); + igt_assert_lt(0, count); } if (IS_METEORLAKE(dev_id)) - igt_assert((count % 2) == 0); + igt_assert_eq((count % 2), 0); else if (IS_PONTEVECCHIO(dev_id)) - igt_assert((count % 4) == 0); + igt_assert_eq((count % 4), 0); else if (IS_DG2(dev_id)) - igt_assert((count % 8) == 0); + igt_assert_eq((count % 8), 0); } query.size -= sz; @@ -786,7 +786,7 @@ __engine_cycles(int fd, struct drm_xe_engine_class_instance *hwe) if (!((i + 1) % NUM_SNAPSHOTS)) { igt_debug("clock %s\n", clock[index].name); igt_debug("usable %d\n", usable); - igt_assert(usable > 2); + igt_assert_lt(2, usable); usable = 0; } } diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c index a4f6c7a0b..f20a1f474 100644 --- a/tests/intel/xe_vm.c +++ b/tests/intel/xe_vm.c @@ -408,7 +408,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo, int n_exec_queues = n_bo, n_execs = n_bo; int i, b; - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); bo = malloc(sizeof(*bo) * n_bo); igt_assert(bo); @@ -778,7 +778,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs, } *data; int i, b; - igt_assert(n_execs <= BIND_ARRAY_MAX_N_EXEC); + igt_assert_lte(n_execs, BIND_ARRAY_MAX_N_EXEC); vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data) * n_execs; @@ -974,7 +974,7 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci, base_addr -= xe_get_default_alignment(fd); } - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); vm = xe_vm_create(fd, 0, 0); if (flags & LARGE_BIND_FLAG_USERPTR) { -- 2.45.2 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [i-g-t,2/2] tests/intel: Apply igt.cocci transforms 2024-07-29 22:02 ` [PATCH i-g-t 2/2] tests/intel: Apply igt.cocci transforms Matt Roper @ 2024-07-31 12:25 ` Vivekanandan, Balasubramani 2024-07-31 16:26 ` Matt Roper 2024-08-01 21:46 ` [PATCH i-g-t 2/2] " Dixit, Ashutosh 1 sibling, 1 reply; 12+ messages in thread From: Vivekanandan, Balasubramani @ 2024-07-31 12:25 UTC (permalink / raw) To: Matt Roper, igt-dev On 29.07.2024 15:02, Matt Roper wrote: > A number of Intel tests are using checks like "igt_assert(x < y)" rather > than using the dedicated comparison assertions that print the actual > values on assertion failure. Run the Intel test directory through > Coccinelle to apply these conversions and also apply some other general > coding style cleanup: > > spatch --in-place --sp-file lib/igt.cocci tests/intel There are some places in the code, where still igt_assert is retained like these lines from file gem_ctx_create.c ``` shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); igt_assert(shared != MAP_FAILED); ``` Are these unspotted by Coccinelle? Regards, Bala > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > tests/intel/api_intel_allocator.c | 12 ++--- > tests/intel/api_intel_bb.c | 18 +++---- > tests/intel/drm_fdinfo.c | 8 +-- > tests/intel/gem_blits.c | 16 +++--- > tests/intel/gem_ccs.c | 4 +- > tests/intel/gem_close_race.c | 2 +- > tests/intel/gem_concurrent_all.c | 8 +-- > tests/intel/gem_create.c | 2 +- > tests/intel/gem_ctx_create.c | 8 +-- > tests/intel/gem_ctx_exec.c | 4 +- > tests/intel/gem_ctx_persistence.c | 12 +++-- > tests/intel/gem_eio.c | 8 +-- > tests/intel/gem_exec_alignment.c | 6 ++- > tests/intel/gem_exec_big.c | 4 +- > tests/intel/gem_exec_capture.c | 8 +-- > tests/intel/gem_exec_fair.c | 32 +++++++----- > tests/intel/gem_exec_fence.c | 2 +- > tests/intel/gem_exec_gttfill.c | 4 +- > tests/intel/gem_exec_nop.c | 2 +- > tests/intel/gem_exec_reloc.c | 4 +- > tests/intel/gem_gtt_speed.c | 2 +- > tests/intel/gem_linear_blits.c | 6 +-- > tests/intel/gem_pread.c | 5 +- > tests/intel/gem_pwrite.c | 5 +- > tests/intel/gem_pxp.c | 16 +++--- > tests/intel/gem_reset_stats.c | 8 +-- > tests/intel/gem_softpin.c | 8 ++- > tests/intel/gem_tiled_blits.c | 6 +-- > tests/intel/gem_tiled_fence_blits.c | 4 +- > tests/intel/gem_userptr_blits.c | 4 +- > tests/intel/gem_wait.c | 8 +-- > tests/intel/gem_watchdog.c | 2 +- > tests/intel/i915_hangman.c | 2 +- > tests/intel/i915_module_load.c | 6 +-- > tests/intel/i915_pm_freq_api.c | 50 +++++++++--------- > tests/intel/i915_pm_rc6_residency.c | 4 +- > tests/intel/i915_pm_rps.c | 11 ++-- > tests/intel/i915_query.c | 12 ++--- > tests/intel/kms_big_fb.c | 2 +- > tests/intel/kms_busy.c | 2 +- > tests/intel/kms_ccs.c | 2 +- > tests/intel/kms_cdclk.c | 5 +- > tests/intel/kms_dsc_helper.c | 4 +- > tests/intel/kms_fbcon_fbt.c | 3 +- > tests/intel/kms_pm_dc.c | 9 ++-- > tests/intel/kms_pm_rpm.c | 2 +- > tests/intel/kms_psr.c | 18 +++---- > tests/intel/perf.c | 34 ++++++------ > tests/intel/perf_pmu.c | 37 +++++++------ > tests/intel/xe_ccs.c | 4 +- > tests/intel/xe_debugfs.c | 2 +- > tests/intel/xe_dma_buf_sync.c | 2 +- > tests/intel/xe_evict.c | 4 +- > tests/intel/xe_exec_balancer.c | 7 +-- > tests/intel/xe_exec_basic.c | 4 +- > tests/intel/xe_exec_compute_mode.c | 9 ++-- > tests/intel/xe_exec_fault_mode.c | 5 +- > tests/intel/xe_exec_reset.c | 8 +-- > tests/intel/xe_exec_store.c | 2 +- > tests/intel/xe_exec_threads.c | 11 ++-- > tests/intel/xe_gt_freq.c | 80 ++++++++++++++--------------- > tests/intel/xe_intel_bb.c | 16 +++--- > tests/intel/xe_oa.c | 26 +++++----- > tests/intel/xe_pat.c | 2 +- > tests/intel/xe_peer2peer.c | 2 +- > tests/intel/xe_pm.c | 16 +++--- > tests/intel/xe_pm_residency.c | 4 +- > tests/intel/xe_query.c | 12 ++--- > tests/intel/xe_vm.c | 6 +-- > 69 files changed, 335 insertions(+), 328 deletions(-) > > diff --git a/tests/intel/api_intel_allocator.c b/tests/intel/api_intel_allocator.c > index 9218be3b9..15ba4828c 100644 > --- a/tests/intel/api_intel_allocator.c > +++ b/tests/intel/api_intel_allocator.c > @@ -705,7 +705,7 @@ static void execbuf_with_allocator(int fd) > gem_close(fd, object[i].handle); > } > > - igt_assert(copied == magic); > + igt_assert_eq_u32(copied, magic); > igt_assert(intel_allocator_close(ahnd) == true); > } > > @@ -776,13 +776,13 @@ static void gem_pool(int i915) > bb[0] = single_exec_from_pool(i915, ahnd, 4096); > gem_sync(i915, bb[0]); > bb[1] = single_exec_from_pool(i915, ahnd, 4096); > - igt_assert(bb[0] == bb[1]); > + igt_assert_eq_u32(bb[0], bb[1]); > > bb[2] = single_exec_from_pool(i915, ahnd, 8192); > gem_sync(i915, bb[2]); > bb[3] = single_exec_from_pool(i915, ahnd, 8192); > - igt_assert(bb[2] == bb[3]); > - igt_assert(bb[0] != bb[2]); > + igt_assert_eq_u32(bb[2], bb[3]); > + igt_assert_neq_u32(bb[0], bb[2]); > > spin = igt_spin_new(i915, > .ahnd = ahnd, > @@ -792,8 +792,8 @@ static void gem_pool(int i915) > bb[2] = single_exec_from_pool(i915, ahnd, 8192); > bb[3] = single_exec_from_pool(i915, ahnd, 8192); > igt_spin_free(i915, spin); > - igt_assert(bb[0] != bb[1]); > - igt_assert(bb[2] != bb[3]); > + igt_assert_neq_u32(bb[0], bb[1]); > + igt_assert_neq_u32(bb[2], bb[3]); > > put_ahnd(ahnd); > > diff --git a/tests/intel/api_intel_bb.c b/tests/intel/api_intel_bb.c > index 6cb5d4f9e..db039dc3b 100644 > --- a/tests/intel/api_intel_bb.c > +++ b/tests/intel/api_intel_bb.c > @@ -1024,11 +1024,11 @@ static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling) > > /* We'll fail on src <-> final compare so just warn */ > if (tiling == I915_TILING_NONE) { > - if (compare_bufs(&src, &dst, false) > 0) > - igt_warn("none->none blit failed!"); > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > + "none->none blit failed!"); > } else { > - if (compare_bufs(&src, &dst, false) == 0) > - igt_warn("none->tiled blit failed!"); > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > + "none->tiled blit failed!"); > } > > fails = compare_bufs(&src, &final, true); > @@ -1367,11 +1367,11 @@ static int render(struct buf_ops *bops, uint32_t tiling, bool do_reloc, > > /* We'll fail on src <-> final compare so just warn */ > if (tiling == I915_TILING_NONE) { > - if (compare_bufs(&src, &dst, false) > 0) > - igt_warn("%s: none->none failed!\n", __func__); > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > + "%s: none->none failed!\n", __func__); > } else { > - if (compare_bufs(&src, &dst, false) == 0) > - igt_warn("%s: none->tiled failed!\n", __func__); > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > + "%s: none->tiled failed!\n", __func__); > } > > fails = compare_bufs(&src, &final, true); > @@ -1535,7 +1535,7 @@ static void test_crc32(int i915, const intel_ctx_t *ctx, > > put_offset(ahnd, data); > gem_close(i915, data); > - igt_assert(cpu_crc == gpu_crc); > + igt_assert_eq_u32(cpu_crc, gpu_crc); > } > > put_ahnd(ahnd); > diff --git a/tests/intel/drm_fdinfo.c b/tests/intel/drm_fdinfo.c > index a790f9255..160dc3d0a 100644 > --- a/tests/intel/drm_fdinfo.c > +++ b/tests/intel/drm_fdinfo.c > @@ -275,7 +275,7 @@ static void log_busy(unsigned int num_engines, uint64_t *val) > int len; > > len = snprintf(p, rem, "%u=%" PRIu64 "\n", i, val[i]); > - igt_assert(len > 0); > + igt_assert_lt(0, len); > rem -= len; > p += len; > } > @@ -805,7 +805,7 @@ static size_t read_fdinfo(char *buf, const size_t sz, int at, const char *name) > buf[count - 1] = 0; > close(fd); > > - return count > 0 ? count : 0; > + return max(count, 0); > } > > /* > @@ -855,7 +855,7 @@ test_memory(int i915, struct gem_memory_region *mr, unsigned int flags) > > gem_quiescent_gpu(i915); > ret = __igt_parse_drm_fdinfo(dir, buf, &info, NULL, 0, NULL, 0); > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > igt_require(info.num_regions); > memcpy(&prev_info, &info, sizeof(info)); > memcpy(&base_info, &info, sizeof(info)); > @@ -905,7 +905,7 @@ test_memory(int i915, struct gem_memory_region *mr, unsigned int flags) > ret = __igt_parse_drm_fdinfo(dir, buf, &info, > NULL, 0, > region_map, ARRAY_SIZE(region_map)); > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > igt_assert(info.num_regions); > > read_fdinfo(fdinfo_buf, sizeof(fdinfo_buf), dir, buf); > diff --git a/tests/intel/gem_blits.c b/tests/intel/gem_blits.c > index 5ca81fbfe..b2af48ef1 100644 > --- a/tests/intel/gem_blits.c > +++ b/tests/intel/gem_blits.c > @@ -267,7 +267,7 @@ static void buffer_set_tiling(const struct device *device, > batch[i++] = obj[1].offset >> 32; > > if ((tiling | buffer->tiling) >= T_YMAJOR) { > - igt_assert(device->gen >= 6); > + igt_assert_lte(6, device->gen); > batch[i++] = MI_FLUSH_DW_CMD | 2; > batch[i++] = 0; > batch[i++] = 0; > @@ -415,7 +415,7 @@ static bool blit_to_linear(const struct device *device, > batch[i++] = obj[1].offset >> 32; > > if (buffer->tiling >= T_YMAJOR) { > - igt_assert(device->gen >= 6); > + igt_assert_lte(6, device->gen); > batch[i++] = MI_FLUSH_DW_CMD | 2; > batch[i++] = 0; > batch[i++] = 0; > @@ -542,11 +542,9 @@ static bool buffer_check(const struct device *device, > continue; > > for (int x = 0; x < buffer->width; x++) { > - if (row[x] != model[x] && num_errors++ < 5) { > - igt_warn("buffer handle=%d mismatch at (%d, %d): expected %08x, found %08x\n", > - buffer->handle, > - x, y, model[x], row[x]); > - } > + igt_warn_on_f(row[x] != model[x] && num_errors++ < 5, > + "buffer handle=%d mismatch at (%d, %d): expected %08x, found %08x\n", > + buffer->handle, x, y, model[x], row[x]); > } > } > > @@ -664,7 +662,7 @@ blit(const struct device *device, > height = dst->height - dst_y; > > if (dst->caching) { > - igt_assert(device->gen >= 3); > + igt_assert_lte(3, device->gen); > igt_assert(device->llc || !src->caching); > } > > @@ -764,7 +762,7 @@ blit(const struct device *device, > batch[i++] = obj[1].offset >> 32; > > if ((src->tiling | dst->tiling) >= T_YMAJOR) { > - igt_assert(device->gen >= 6); > + igt_assert_lte(6, device->gen); > batch[i++] = MI_FLUSH_DW_CMD | 2; > batch[i++] = 0; > batch[i++] = 0; > diff --git a/tests/intel/gem_ccs.c b/tests/intel/gem_ccs.c > index 6ced67d7a..07aa6d322 100644 > --- a/tests/intel/gem_ccs.c > +++ b/tests/intel/gem_ccs.c > @@ -175,7 +175,7 @@ static void surf_copy(int i915, > gem_sync(i915, blt.dst.handle); > WRITE_PNG(i915, run_id, "corrupted", &blt.dst, dst->x2, dst->y2, bpp); > result = memcmp(src->ptr, dst->ptr, src->size); > - igt_assert(result != 0); > + igt_assert_neq(result, 0); > > /* retrieve back ccs */ > memcpy(ccsmap, ccscopy, ccssize); > @@ -601,7 +601,7 @@ static int opt_handler(int opt, int opt_index, void *data) > case 'f': > param.compression_format = atoi(optarg); > igt_debug("Compression format: %d\n", param.compression_format); > - igt_assert((param.compression_format & ~0x1f) == 0); > + igt_assert_eq((param.compression_format & ~0x1f), 0); > break; > case 'p': > param.write_png = true; > diff --git a/tests/intel/gem_close_race.c b/tests/intel/gem_close_race.c > index 9edcf13eb..c68e2fa73 100644 > --- a/tests/intel/gem_close_race.c > +++ b/tests/intel/gem_close_race.c > @@ -307,7 +307,7 @@ static void multigpu_threads(int timeout, unsigned int flags, int gpu_count) > struct drm_gem_open name; > int fd = __drm_open_driver_another(gpu, DRIVER_INTEL); > > - igt_assert(fd > 0); > + igt_assert_lt(0, fd); > > igt_fork(child, size) > thread(fd, name, timeout, flags); > diff --git a/tests/intel/gem_concurrent_all.c b/tests/intel/gem_concurrent_all.c > index dbb7622d3..acc6a230d 100644 > --- a/tests/intel/gem_concurrent_all.c > +++ b/tests/intel/gem_concurrent_all.c > @@ -306,7 +306,7 @@ userptr_create_bo(const struct buffers *b) > igt_assert(ptr != (void *)-1); > userptr.user_ptr = to_user_pointer(ptr); > > - do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr)); > + do_ioctl(fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr); > buf = intel_buf_create_using_handle_and_size(b->bops, userptr.handle, > b->width, b->height, 32, 0, > I915_TILING_NONE, 0, > @@ -497,7 +497,7 @@ vgem_create_bo(const struct buffers *b) > struct dmabuf *dmabuf; > uint32_t handle; > > - igt_assert(vgem_drv != -1); > + igt_assert_neq(vgem_drv, -1); > > vgem.width = b->width; > vgem.height = b->height; > @@ -915,7 +915,7 @@ static void buffers_create(struct buffers *b) > igt_assert(b->bops); > > buffers_destroy(b); > - igt_assert(b->count == 0); > + igt_assert_eq(b->count, 0); > b->count = count; > > ahnd = alloc_open(); > @@ -941,7 +941,7 @@ static void __buffers_create(struct buffers *b) > { > b->bops = buf_ops_create(fd); > igt_assert(b->bops); > - igt_assert(b->num_buffers > 0); > + igt_assert_lt(0, b->num_buffers); > igt_assert(b->mode); > igt_assert(b->mode->create_bo); > > diff --git a/tests/intel/gem_create.c b/tests/intel/gem_create.c > index 26cd6e32e..ca39a8b64 100644 > --- a/tests/intel/gem_create.c > +++ b/tests/intel/gem_create.c > @@ -637,7 +637,7 @@ static void create_ext_set_pat(int fd) > * This means that we are on a Meteor Lake and the PAT > * index is already supported by the running i915 > */ > - igt_assert(ret == 0); > + igt_assert_eq(ret, 0); > > /* > * {set|get}_caching ioctl should fail for objects created with set_pat > diff --git a/tests/intel/gem_ctx_create.c b/tests/intel/gem_ctx_create.c > index 6afb10a7b..0332ecbb9 100644 > --- a/tests/intel/gem_ctx_create.c > +++ b/tests/intel/gem_ctx_create.c > @@ -297,18 +297,14 @@ static void xchg_u32(void *array, unsigned i, unsigned j) > { > uint32_t *a = array, tmp; > > - tmp = a[i]; > - a[i] = a[j]; > - a[j] = tmp; > + igt_swap(a[i], a[j]); > } > > static void xchg_ptr(void *array, unsigned i, unsigned j) > { > void **a = array, *tmp; > > - tmp = a[i]; > - a[i] = a[j]; > - a[j] = tmp; > + igt_swap(a[i], a[j]); > } > > static unsigned __context_size(int fd) > diff --git a/tests/intel/gem_ctx_exec.c b/tests/intel/gem_ctx_exec.c > index f3e252d10..a45a7e378 100644 > --- a/tests/intel/gem_ctx_exec.c > +++ b/tests/intel/gem_ctx_exec.c > @@ -346,7 +346,7 @@ static void nohangcheck_hostile(int i915) > IGT_SPIN_FENCE_OUT)); > > new = fill_ring(i915, &spin->execbuf); > - igt_assert(new != -1); > + igt_assert_neq(new, -1); > spin->out_fence = -1; > > if (fence < 0) { > @@ -362,7 +362,7 @@ static void nohangcheck_hostile(int i915) > } > } > intel_ctx_destroy(i915, ctx); > - igt_assert(fence != -1); > + igt_assert_neq(fence, -1); > > err = 0; > if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */ > diff --git a/tests/intel/gem_ctx_persistence.c b/tests/intel/gem_ctx_persistence.c > index 90c1e0112..8d4a874d4 100644 > --- a/tests/intel/gem_ctx_persistence.c > +++ b/tests/intel/gem_ctx_persistence.c > @@ -1093,10 +1093,12 @@ static void test_processes(int i915) > > /* Wait until we are told to die */ > pid = getpid(); > - write(p[i].sv[0], &pid, sizeof(pid)); > + igt_assert_eq(write(p[i].sv[0], &pid, sizeof(pid)), > + sizeof(pid)); > > pid = 0; > - read(p[i].sv[0], &pid, sizeof(pid)); > + igt_assert_eq(read(p[i].sv[0], &pid, sizeof(pid)), > + sizeof(pid)); > igt_assert(pid == getpid()); > } > } > @@ -1109,8 +1111,10 @@ static void test_processes(int i915) > igt_assert_eq(sync_fence_wait(fence, 0), -ETIME); > > /* Kill *this* process */ > - read(p[i].sv[1], &pid, sizeof(pid)); > - write(p[i].sv[1], &pid, sizeof(pid)); > + igt_assert_eq(read(p[i].sv[1], &pid, sizeof(pid)), > + sizeof(pid)); > + igt_assert_eq(write(p[i].sv[1], &pid, sizeof(pid)), > + sizeof(pid)); > > /* > * A little bit of slack required for the signal to terminate > diff --git a/tests/intel/gem_eio.c b/tests/intel/gem_eio.c > index dc6178d63..b65b914fa 100644 > --- a/tests/intel/gem_eio.c > +++ b/tests/intel/gem_eio.c > @@ -627,7 +627,7 @@ static void test_inflight(int fd, unsigned int wait) > for (unsigned int n = 0; n < max; n++) { > gem_execbuf_wr(fd, &execbuf); > fence[n] = execbuf.rsvd2 >> 32; > - igt_assert(fence[n] != -1); > + igt_assert_neq(fence[n], -1); > } > > igt_debugfs_dump(fd, "i915_engine_info"); > @@ -687,7 +687,7 @@ static void test_inflight_suspend(int fd) > for (unsigned int n = 0; n < max; n++) { > gem_execbuf_wr(fd, &execbuf); > fence[n] = execbuf.rsvd2 >> 32; > - igt_assert(fence[n] != -1); > + igt_assert_neq(fence[n], -1); > } > > igt_set_autoresume_delay(30); > @@ -774,7 +774,7 @@ static void test_inflight_contexts(int fd, unsigned int wait) > if (__gem_execbuf_wr(fd, &execbuf)) > break; /* small shared ring */ > fence[n] = execbuf.rsvd2 >> 32; > - igt_assert(fence[n] != -1); > + igt_assert_neq(fence[n], -1); > count++; > } > > @@ -885,7 +885,7 @@ static void test_inflight_internal(int fd, unsigned int wait) > gem_execbuf_wr(fd, &execbuf); > > fences[nfence] = execbuf.rsvd2 >> 32; > - igt_assert(fences[nfence] != -1); > + igt_assert_neq(fences[nfence], -1); > nfence++; > } > > diff --git a/tests/intel/gem_exec_alignment.c b/tests/intel/gem_exec_alignment.c > index 7b51b7af0..6a9905d95 100644 > --- a/tests/intel/gem_exec_alignment.c > +++ b/tests/intel/gem_exec_alignment.c > @@ -302,7 +302,8 @@ static void prio_inversion(int i915, unsigned int flags) > naughty_child(i915, link[1], obj.handle, flags); > > igt_debug("Waiting for naughty client\n"); > - read(link[0], &elapsed, sizeof(elapsed)); > + igt_assert_eq(read(link[0], &elapsed, sizeof(elapsed)), > + sizeof(elapsed)); > igt_debug("Ready...\n"); > usleep(250 * 1000); /* let the naughty execbuf begin */ > igt_debug("Go!\n"); > @@ -331,7 +332,8 @@ static void prio_inversion(int i915, unsigned int flags) > igt_waitchildren(); > gem_close(i915, obj.handle); > > - read(link[0], &naughty, sizeof(naughty)); > + igt_assert_eq(read(link[0], &naughty, sizeof(naughty)), > + sizeof(naughty)); > igt_info("Naughty client took %'"PRIu64"ns\n", naughty); > > igt_assert(elapsed < naughty / 2); > diff --git a/tests/intel/gem_exec_big.c b/tests/intel/gem_exec_big.c > index 7bd91c2a0..86849f322 100644 > --- a/tests/intel/gem_exec_big.c > +++ b/tests/intel/gem_exec_big.c > @@ -143,9 +143,7 @@ static void xchg_reloc(void *array, unsigned i, unsigned j) > struct drm_i915_gem_relocation_entry *b = &reloc[j]; > struct drm_i915_gem_relocation_entry tmp; > > - tmp = *a; > - *a = *b; > - *b = tmp; > + igt_swap(*a, *b); > } > > static void execN(int fd, uint32_t handle, uint64_t batch_size, unsigned flags, char *ptr) > diff --git a/tests/intel/gem_exec_capture.c b/tests/intel/gem_exec_capture.c > index 720ff796d..2340ad495 100644 > --- a/tests/intel/gem_exec_capture.c > +++ b/tests/intel/gem_exec_capture.c > @@ -406,7 +406,7 @@ static void __capture1(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx, > gem_execbuf_wr(fd, &execbuf); > > fence_out = execbuf.rsvd2 >> 32; > - igt_assert(fence_out >= 0); > + igt_assert_lte(0, fence_out); > > /* Wait for the request to start */ > while (READ_ONCE(*seqno) != 0xc0ffee) > @@ -792,11 +792,11 @@ static void prioinv(int fd, int dir, const intel_ctx_t *ctx, > &fence_out, REGION_SMEM, true)); > put_ahnd(ahnd); > > - write(link[1], &fd, sizeof(fd)); /* wake the parent up */ > + igt_assert_eq(write(link[1], &fd, sizeof(fd)), sizeof(fd)); /* wake the parent up */ > wait_to_die(fence_out); > - write(link[1], &fd, sizeof(fd)); /* wake the parent up */ > + igt_assert_eq(write(link[1], &fd, sizeof(fd)), sizeof(fd)); /* wake the parent up */ > } > - read(link[0], &dummy, sizeof(dummy)); > + igt_assert_eq(read(link[0], &dummy, sizeof(dummy)), sizeof(dummy)); > igt_require_f(poll(&(struct pollfd){link[0], POLLIN}, 1, 500) == 0, > "Capture completed too quickly! Will not block\n"); > > diff --git a/tests/intel/gem_exec_fair.c b/tests/intel/gem_exec_fair.c > index 2f7ef3800..19df66921 100644 > --- a/tests/intel/gem_exec_fair.c > +++ b/tests/intel/gem_exec_fair.c > @@ -579,10 +579,12 @@ static void fair_child(int i915, const intel_ctx_t *ctx, > > /* Synchronize with other children/parent upon construction */ > if (sv != -1) > - write(sv, &p_fence, sizeof(p_fence)); > + igt_assert_eq(write(sv, &p_fence, sizeof(p_fence)), > + sizeof(p_fence)); > if (rv != -1) > - read(rv, &p_fence, sizeof(p_fence)); > - igt_assert(p_fence == -1); > + igt_assert_eq(read(rv, &p_fence, sizeof(p_fence)), > + sizeof(p_fence)); > + igt_assert_eq(p_fence, -1); > > aux_flags = 0; > if (intel_gen(intel_get_drm_devid(i915)) < 8) > @@ -850,9 +852,11 @@ static void fairness(int i915, const intel_ctx_cfg_t *cfg, > { > int sync; > for (int child = 0; child < nchild; child++) > - read(lnk.child[0], &sync, sizeof(sync)); > + igt_assert_eq(read(lnk.child[0], &sync, sizeof(sync)), > + sizeof(sync)); > for (int child = 0; child < nchild; child++) > - write(lnk.parent[1], &sync, sizeof(sync)); > + igt_assert_eq(write(lnk.parent[1], &sync, sizeof(sync)), > + sizeof(sync)); > } > > while (nfences--) > @@ -1028,9 +1032,9 @@ static void deadline_child(int i915, > if (!(flags & DL_PRIO)) > execbuf.flags |= I915_EXEC_FENCE_IN; > > - write(sv, &prev, sizeof(int)); > - read(rv, &prev, sizeof(int)); > - igt_assert(prev == -1); > + igt_assert_eq(write(sv, &prev, sizeof(int)), sizeof(int)); > + igt_assert_eq(read(rv, &prev, sizeof(int)), sizeof(int)); > + igt_assert_eq(prev, -1); > > prev = execbuf.rsvd2; > next = execbuf.rsvd2 >> 32; > @@ -1044,7 +1048,8 @@ static void deadline_child(int i915, > gem_execbuf_wr(i915, &execbuf); > close(execbuf.rsvd2); > > - write(sv, &fence.handle, sizeof(uint32_t)); > + igt_assert_eq(write(sv, &fence.handle, sizeof(uint32_t)), > + sizeof(uint32_t)); > > prev = next; > next = execbuf.rsvd2 >> 32; > @@ -1187,10 +1192,12 @@ static void deadline(int i915, const intel_ctx_cfg_t *cfg, > } > > for (int i = 0; i < num_children; i++) > - read(link[i].child[0], &over, sizeof(int)); > + igt_assert_eq(read(link[i].child[0], &over, sizeof(int)), > + sizeof(int)); > igt_info("Testing %d children, with %'dns\n", num_children, child_ns); > for (int i = 0; i < num_children; i++) > - write(link[i].parent[1], &over, sizeof(int)); > + igt_assert_eq(write(link[i].parent[1], &over, sizeof(int)), > + sizeof(int)); > > over = 0; > missed = 0; > @@ -1207,7 +1214,8 @@ static void deadline(int i915, const intel_ctx_cfg_t *cfg, > > sw_sync_timeline_inc(timeline, 1); > for (int i = 0; i < num_children; i++) { > - read(link[i].child[0], &fences[i].handle, sizeof(uint32_t)); > + igt_assert_eq(read(link[i].child[0], &fences[i].handle, sizeof(uint32_t)), > + sizeof(uint32_t)); > fences[i].flags = I915_EXEC_FENCE_WAIT; > } > > diff --git a/tests/intel/gem_exec_fence.c b/tests/intel/gem_exec_fence.c > index a313c31f2..7f39c73d7 100644 > --- a/tests/intel/gem_exec_fence.c > +++ b/tests/intel/gem_exec_fence.c > @@ -366,7 +366,7 @@ static void test_fence_busy_all(int fd, const intel_ctx_t *ctx, unsigned flags) > execbuf.rsvd2 = -1; > gem_execbuf_wr(fd, &execbuf); > fence = execbuf.rsvd2 >> 32; > - igt_assert(fence != -1); > + igt_assert_neq(fence, -1); > > if (all < 0) { > all = fence; > diff --git a/tests/intel/gem_exec_gttfill.c b/tests/intel/gem_exec_gttfill.c > index 096681740..ff600e0ca 100644 > --- a/tests/intel/gem_exec_gttfill.c > +++ b/tests/intel/gem_exec_gttfill.c > @@ -66,9 +66,7 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) > struct batch *batches = array; > struct batch tmp; > > - tmp = batches[i]; > - batches[i] = batches[j]; > - batches[j] = tmp; > + igt_swap(batches[i], batches[j]); > } > > static void submit(int fd, uint64_t ahnd, unsigned int gen, > diff --git a/tests/intel/gem_exec_nop.c b/tests/intel/gem_exec_nop.c > index fb37cb511..1b20cc870 100644 > --- a/tests/intel/gem_exec_nop.c > +++ b/tests/intel/gem_exec_nop.c > @@ -415,7 +415,7 @@ stable_nop_on_ring(int fd, uint32_t handle, const intel_ctx_t *ctx, > igt_stats_t s; > double n; > > - igt_assert(reps >= 5); > + igt_assert_lte(5, reps); > > igt_stats_init_with_size(&s, reps); > s.is_float = true; > diff --git a/tests/intel/gem_exec_reloc.c b/tests/intel/gem_exec_reloc.c > index d8013ccfc..44c09c3e2 100644 > --- a/tests/intel/gem_exec_reloc.c > +++ b/tests/intel/gem_exec_reloc.c > @@ -1343,7 +1343,7 @@ static void concurrent_child(int i915, const intel_ctx_t *ctx, > x += idx * CONCURRENT; > > do { > - read(in, batch, sizeof(*batch)); > + igt_assert_eq(read(in, batch, sizeof(*batch)), sizeof(*batch)); > if (!*batch) > break; > > @@ -1359,7 +1359,7 @@ static void concurrent_child(int i915, const intel_ctx_t *ctx, > } > } > > - write(out, &err, sizeof(err)); > + igt_assert_eq(write(out, &err, sizeof(err)), sizeof(err)); > count++; > } while (err == 0); > > diff --git a/tests/intel/gem_gtt_speed.c b/tests/intel/gem_gtt_speed.c > index 996e54af0..0f4e174d2 100644 > --- a/tests/intel/gem_gtt_speed.c > +++ b/tests/intel/gem_gtt_speed.c > @@ -70,7 +70,7 @@ static void streaming_load(void *src, int len) > { > __m128i tmp, *s = src; > > - igt_assert((len & 15) == 0); > + igt_assert_eq((len & 15), 0); > igt_assert((((uintptr_t)src) & 15) == 0); > > while (len >= 16) { > diff --git a/tests/intel/gem_linear_blits.c b/tests/intel/gem_linear_blits.c > index 2eeec5b6a..b6c0b13ac 100644 > --- a/tests/intel/gem_linear_blits.c > +++ b/tests/intel/gem_linear_blits.c > @@ -212,9 +212,9 @@ check_bo(int fd, uint32_t handle, uint32_t val) > > num_errors = 0; > for (i = 0; i < WIDTH*HEIGHT; i++) { > - if (linear[i] != val && num_errors++ < 32) > - igt_warn("[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > - i * 4, val, linear[i], val ^ linear[i]); > + igt_warn_on_f(linear[i] != val && num_errors++ < 32, > + "[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > + i * 4, val, linear[i], val ^ linear[i]); > val++; > } > igt_assert_eq(num_errors, 0); > diff --git a/tests/intel/gem_pread.c b/tests/intel/gem_pread.c > index e5e662361..70a38e75c 100644 > --- a/tests/intel/gem_pread.c > +++ b/tests/intel/gem_pread.c > @@ -151,7 +151,7 @@ static void write_value(const char *path, int value) > > fd = open(path, O_WRONLY); > if (fd != -1) { > - write(fd, buf, len); > + igt_assert_eq(write(fd, buf, len), len); > close(fd); > } > } > @@ -223,8 +223,7 @@ static void test_exhaustion(int i915) > count++; > } > igt_assert(count); > - if (t.err) > - igt_warn("err:%d after %lu threads\n", t.err, count); > + igt_warn_on_f(t.err, "err:%d after %lu threads\n", t.err, count); > > /* Service the fault; releasing the stuck ioctls */ > memset(©, 0, sizeof(copy)); > diff --git a/tests/intel/gem_pwrite.c b/tests/intel/gem_pwrite.c > index 025684a33..05a47b7b1 100644 > --- a/tests/intel/gem_pwrite.c > +++ b/tests/intel/gem_pwrite.c > @@ -425,7 +425,7 @@ static void write_value(const char *path, int value) > > fd = open(path, O_WRONLY); > if (fd != -1) { > - write(fd, buf, len); > + igt_assert_eq(write(fd, buf, len), len); > close(fd); > } > } > @@ -497,8 +497,7 @@ static void test_exhaustion(int i915) > count++; > } > igt_assert(count); > - if (t.err) > - igt_warn("err:%d after %lu threads\n", t.err, count); > + igt_warn_on_f(t.err, "err:%d after %lu threads\n", t.err, count); > > /* Service the fault; releasing the stuck ioctls */ > memset(©, 0, sizeof(copy)); > diff --git a/tests/intel/gem_pxp.c b/tests/intel/gem_pxp.c > index 6be19318a..e2c12df17 100644 > --- a/tests/intel/gem_pxp.c > +++ b/tests/intel/gem_pxp.c > @@ -811,7 +811,7 @@ static void test_pxp_dmabuffshare_refcnt(int i915) > for (n = 0; n < (TSTSURF_SIZE/4); ++n) > if (encrypted[0][n] == encrypted[1][n]) > ++num_matches; > - igt_assert(num_matches == (TSTSURF_SIZE/4)); > + igt_assert_eq(num_matches, (TSTSURF_SIZE / 4)); > } > > > @@ -988,7 +988,7 @@ static void test_pxp_stale_ctx_execution(int i915) > */ > prepare_exec_assets(i915, &data, true, false); > ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); > - igt_assert(ret == 0); > + igt_assert_eq(ret, 0); > > trigger_pxp_debugfs_forced_teardown(i915); > > @@ -1008,7 +1008,7 @@ static void test_pxp_stale_buf_execution(int i915) > /* Use pxp buffers with pxp context for testing for invalidation of protected buffers. */ > prepare_exec_assets(i915, &data, true, true); > ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); > - igt_assert(ret == 0); > + igt_assert_eq(ret, 0); > > trigger_pxp_debugfs_forced_teardown(i915); > > @@ -1055,7 +1055,7 @@ static void test_pxp_stale_buf_optout_execution(int i915) > * the intent of the subtest) to ensure ARB session is alive. > */ > ret = create_ctx_with_params(i915, true, true, true, false, &tmpctx); > - igt_assert(ret == 0); > + igt_assert_eq(ret, 0); > > /* > * Use a normal context for testing opt-out behavior > @@ -1063,7 +1063,7 @@ static void test_pxp_stale_buf_optout_execution(int i915) > */ > prepare_exec_assets(i915, &data, false, true); > ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); > - igt_assert(ret == 0); > + igt_assert_eq(ret, 0); > > trigger_pxp_debugfs_forced_teardown(i915); > > @@ -1088,7 +1088,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat > */ > prepare_exec_assets(i915, &data[0], true, false); > ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf); > - igt_assert(ret == 0); > + igt_assert_eq(ret, 0); > > /* > * For asset data[1]: Use pxp buffers with pxp context for testing for invalidation > @@ -1096,7 +1096,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat > */ > prepare_exec_assets(i915, &data[1], true, true); > ret = gem_execbuf_flush_store_dw(i915, data[1].ibb, data[1].ctx, data[1].fencebuf); > - igt_assert(ret == 0); > + igt_assert_eq(ret, 0); > > /* > * For asset data[2]: Use a normal context for testing opt-out behavior > @@ -1104,7 +1104,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat > */ > prepare_exec_assets(i915, &data[2], false, true); > ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf); > - igt_assert(ret == 0); > + igt_assert_eq(ret, 0); > > /* Do an S3 suspend resume cycle which also causes the pxp teardown event */ > trigger_powermgt_suspend_cycle(i915, pm); > diff --git a/tests/intel/gem_reset_stats.c b/tests/intel/gem_reset_stats.c > index 91bec96c0..8c74ce28c 100644 > --- a/tests/intel/gem_reset_stats.c > +++ b/tests/intel/gem_reset_stats.c > @@ -315,7 +315,7 @@ static int noop(int fd, uint32_t ctx, const struct intel_execution_ring *e) > > memset(&exec, 0, sizeof(exec)); > exec.handle = gem_create(fd, 4096); > - igt_assert((int)exec.handle > 0); > + igt_assert_lt(0, (int)exec.handle); > gem_write(fd, exec.handle, 0, &bbe, sizeof(bbe)); > > memset(&eb, 0, sizeof(eb)); > @@ -457,7 +457,7 @@ static void test_rs(const struct intel_execution_ring *e, > if (i == hang_index) > inject_hang(fd[i], 0, e, ASYNC); > else > - igt_assert(noop(fd[i], 0, e) > 0); > + igt_assert_lt(0, noop(fd[i], 0, e)); > } > sync_gpu(); > > @@ -524,7 +524,7 @@ static void test_rs_ctx(const struct intel_execution_ring *e, > if (i == hang_index && j == hang_context) > inject_hang(fd[i], ctx[i][j], e, ASYNC); > else > - igt_assert(noop(fd[i], ctx[i][j], e) > 0); > + igt_assert_lt(0, noop(fd[i], ctx[i][j], e)); > } > } > sync_gpu(); > @@ -876,7 +876,7 @@ static void _check_param_ctx(const int fd, const int ctx, const cap_t cap) > igt_assert_eq(_test_params(fd, ctx, 0, 0), 0); > > if (cap != root) { > - igt_assert(get_reset_count(fd, ctx) == 0); > + igt_assert_eq(get_reset_count(fd, ctx), 0); > } > } > > diff --git a/tests/intel/gem_softpin.c b/tests/intel/gem_softpin.c > index b7c1b34e1..c542bf741 100644 > --- a/tests/intel/gem_softpin.c > +++ b/tests/intel/gem_softpin.c > @@ -793,7 +793,7 @@ static void __reserve(uint64_t ahnd, int i915, bool pinned, > unsigned int flags; > int i; > > - igt_assert(num_obj > 1); > + igt_assert_lt(1, num_obj); > > flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > if (pinned) > @@ -843,7 +843,7 @@ static void __exec_using_allocator(uint64_t ahnd, int i915, int num_obj, > uint64_t sz = 4096; > int i; > > - igt_assert(num_obj > 10); > + igt_assert_lt(10, num_obj); > > flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > if (pinned) > @@ -969,9 +969,7 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) > struct batch *batches = array; > struct batch tmp; > > - tmp = batches[i]; > - batches[i] = batches[j]; > - batches[j] = tmp; > + igt_swap(batches[i], batches[j]); > } > > static void submit(int fd, unsigned int gen, > diff --git a/tests/intel/gem_tiled_blits.c b/tests/intel/gem_tiled_blits.c > index 6fcc8616e..d8e80ca60 100644 > --- a/tests/intel/gem_tiled_blits.c > +++ b/tests/intel/gem_tiled_blits.c > @@ -129,9 +129,9 @@ check_bo(struct intel_buf *buf, uint32_t val, struct intel_bb *ibb) > linear = intel_buf_cpu_map(linear_buf, 0); > num_errors = 0; > for (i = 0; i < width * height; i++) { > - if (linear[i] != val && num_errors++ < 32) > - igt_warn("[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > - i * 4, val, linear[i], val ^ linear[i]); > + igt_warn_on_f(linear[i] != val && num_errors++ < 32, > + "[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > + i * 4, val, linear[i], val ^ linear[i]); > val++; > } > igt_assert_eq(num_errors, 0); > diff --git a/tests/intel/gem_tiled_fence_blits.c b/tests/intel/gem_tiled_fence_blits.c > index 5e5bc6939..f5a3d9311 100644 > --- a/tests/intel/gem_tiled_fence_blits.c > +++ b/tests/intel/gem_tiled_fence_blits.c > @@ -158,9 +158,7 @@ static void xchg_u32(void *array, unsigned i, unsigned j) > { > uint32_t tmp, *base = array; > > - tmp = base[i]; > - base[i] = base[j]; > - base[j] = tmp; > + igt_swap(base[i], base[j]); > } > > static void run_test(int fd, int count, uint64_t end) > diff --git a/tests/intel/gem_userptr_blits.c b/tests/intel/gem_userptr_blits.c > index 807c209e8..67283c182 100644 > --- a/tests/intel/gem_userptr_blits.c > +++ b/tests/intel/gem_userptr_blits.c > @@ -814,7 +814,7 @@ static void test_nohangcheck_hostile(int i915) > IGT_SPIN_FENCE_OUT)); > > new = fill_ring(i915, &spin->execbuf); > - igt_assert(new != -1); > + igt_assert_neq(new, -1); > spin->out_fence = -1; > > if (fence < 0) { > @@ -831,7 +831,7 @@ static void test_nohangcheck_hostile(int i915) > } > intel_ctx_destroy(i915, ctx); > put_ahnd(ahnd); > - igt_assert(fence != -1); > + igt_assert_neq(fence, -1); > > if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */ > igt_debugfs_dump(i915, "i915_engine_info"); > diff --git a/tests/intel/gem_wait.c b/tests/intel/gem_wait.c > index 7a353a11e..9265d1d7a 100644 > --- a/tests/intel/gem_wait.c > +++ b/tests/intel/gem_wait.c > @@ -167,9 +167,11 @@ static void basic(int fd, const intel_ctx_t *ctx, unsigned engine, > igt_seconds_elapsed(&tv) < timeout) > ; > > - if ((flags & HANG) == 0 && !timespec_isset(&spin->last_signal)) > - igt_warn("spinner not terminated, expired? %d!\n", > - poll(&(struct pollfd){ spin->timerfd, POLLIN }, 1, 0)); > + igt_warn_on_f((flags & HANG) == 0 && !timespec_isset(&spin->last_signal), > + "spinner not terminated, expired? %d!\n", poll(&(struct pollfd){ > + spin->timerfd, > + POLLIN, > + }, 1, 0)); > > igt_assert_eq(__gem_wait(fd, &wait), 0); > } else { > diff --git a/tests/intel/gem_watchdog.c b/tests/intel/gem_watchdog.c > index 3d2fd68a8..1edde8b3c 100644 > --- a/tests/intel/gem_watchdog.c > +++ b/tests/intel/gem_watchdog.c > @@ -500,7 +500,7 @@ far_delay(int i915, unsigned long delay, unsigned int target, > batch[1] = batch[0]; > batch[1].flags &= ~EXEC_OBJECT_WRITE; > batch[0].handle = handle; > - assert(batch[0].flags & EXEC_OBJECT_WRITE); > + igt_assert(batch[0].flags & EXEC_OBJECT_WRITE); > gem_execbuf_wr(i915, &execbuf); > > gem_close(i915, obj.handle); > diff --git a/tests/intel/i915_hangman.c b/tests/intel/i915_hangman.c > index f100118b6..a556eec53 100644 > --- a/tests/intel/i915_hangman.c > +++ b/tests/intel/i915_hangman.c > @@ -470,7 +470,7 @@ static void test_hang_detector(const intel_ctx_t *ctx, > igt_stop_hang_detector(); > > /* Did it work? */ > - igt_assert(hang_count == 1); > + igt_assert_eq(hang_count, 1); > > check_alive(); > } > diff --git a/tests/intel/i915_module_load.c b/tests/intel/i915_module_load.c > index e3e4470df..cd1ee6d10 100644 > --- a/tests/intel/i915_module_load.c > +++ b/tests/intel/i915_module_load.c > @@ -230,7 +230,7 @@ inject_fault(const char *module_name, const char *opt, int fault) > char buf[1024]; > int dir; > > - igt_assert(fault > 0); > + igt_assert_lt(0, fault); > snprintf(buf, sizeof(buf), "%s=%d", opt, fault); > > if (igt_kmod_load(module_name, buf)) { > @@ -343,8 +343,8 @@ static uint32_t driver_load_with_lmem_bar_size(uint32_t lmem_bar_size, bool che > char *tmp; > > tmp = __igt_params_get(i915, "lmem_bar_size"); > - if (!tmp) > - igt_skip("lmem_bar_size modparam not supported on this kernel. Skipping the test.\n"); > + igt_skip_on_f(!tmp, > + "lmem_bar_size modparam not supported on this kernel. Skipping the test.\n"); > free(tmp); > } > > diff --git a/tests/intel/i915_pm_freq_api.c b/tests/intel/i915_pm_freq_api.c > index 2a3da6f4a..f2106cd3e 100644 > --- a/tests/intel/i915_pm_freq_api.c > +++ b/tests/intel/i915_pm_freq_api.c > @@ -61,34 +61,34 @@ static void test_freq_basic_api(int dirfd, int gt) > igt_debug("GT: %d, RPn: %d, RPe: %d, RP0: %d\n", gt, rpn, rpe, rp0); > > /* Set min/max to RPn, RP0 for baseline behavior */ > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0) > 0); > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0)); > > /* > * Negative bound tests > * RPn is the floor > * RP0 is the ceiling > */ > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn - 1) < 0); > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0 + 1) < 0); > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn - 1) < 0); > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0 + 1) < 0); > + igt_assert_lt(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn - 1), 0); > + igt_assert_lt(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0 + 1), 0); > + igt_assert_lt(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn - 1), 0); > + igt_assert_lt(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0 + 1), 0); > > /* Assert min requests are respected from rp0 to rpn */ > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0) > 0); > - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rp0); > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpe) > 0); > - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpe); > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn); > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0)); > + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rp0); > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpe)); > + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rpe); > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rpn); > > /* Assert max requests are respected from rpn to rp0 */ > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); > - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn); > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpe) > 0); > - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpe); > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0) > 0); > - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rp0); > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); > + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rpn); > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpe)); > + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rpe); > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0)); > + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rp0); > > } > > @@ -100,8 +100,8 @@ static void test_reset(int i915, int dirfd, int gt, int count) > > for (int i = 0; i < count; i++) { > igt_debug("Running cycle: %d", i); > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); > usleep(ACT_FREQ_LATENCY_US); > req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ); > if (req_freq) > @@ -124,8 +124,8 @@ static void test_suspend(int i915, int dirfd, int gt) > uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ); > uint32_t req_freq; > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); > usleep(ACT_FREQ_LATENCY_US); > req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ); > if (req_freq) > @@ -149,8 +149,10 @@ static void restore_sysfs_freq(int sig) > /* Restore frequencies */ > for_each_sysfs_gt_dirfd(i915, dirfd, gt) { > igt_pm_ignore_slpc_efficient_freq(i915, dirfd, false); > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, stash_max[gt]) > 0); > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, stash_min[gt]) > 0); > + igt_assert_lt(0, > + set_freq(dirfd, RPS_MAX_FREQ_MHZ, stash_max[gt])); > + igt_assert_lt(0, > + set_freq(dirfd, RPS_MIN_FREQ_MHZ, stash_min[gt])); > } > free(stash_min); > free(stash_max); > diff --git a/tests/intel/i915_pm_rc6_residency.c b/tests/intel/i915_pm_rc6_residency.c > index ebc0c235c..7942d46d3 100644 > --- a/tests/intel/i915_pm_rc6_residency.c > +++ b/tests/intel/i915_pm_rc6_residency.c > @@ -250,7 +250,7 @@ static char *get_drpc(int i915, int gt_id) > int gt_dir; > > gt_dir = igt_debugfs_gt_dir(i915, gt_id); > - igt_assert(gt_dir != -1); > + igt_assert_neq(gt_dir, -1); > return igt_sysfs_get(gt_dir, "drpc"); > } > > @@ -307,7 +307,7 @@ static int open_pmu(int i915, uint64_t config) > > fd = perf_i915_open(i915, config); > igt_skip_on(fd < 0 && errno == ENODEV); > - igt_assert(fd >= 0); > + igt_assert_lte(0, fd); > > return fd; > } > diff --git a/tests/intel/i915_pm_rps.c b/tests/intel/i915_pm_rps.c > index 99b83f315..3b7da197d 100644 > --- a/tests/intel/i915_pm_rps.c > +++ b/tests/intel/i915_pm_rps.c > @@ -322,7 +322,8 @@ static void load_helper_run(enum load load) > spin[high_load] = __igt_spin_new(drm_fd, .ahnd = ahnd); > > if (lh.signal && high_load != prev_load) { > - write(lh.link, &lh.signal, sizeof(lh.signal)); > + igt_assert_eq(write(lh.link, &lh.signal, sizeof(lh.signal)), > + sizeof(lh.signal)); > lh.signal = false; > } > prev_load = high_load; > @@ -690,9 +691,9 @@ static uint64_t __fence_order(int i915, > obj->flags = flags1; > gem_execbuf(i915, eb); > > - read(fd, before, sizeof(before)); > + igt_assert_eq(read(fd, before, sizeof(before)), sizeof(before)); > gem_sync(i915, obj->handle); > - read(fd, after, sizeof(after)); > + igt_assert_eq(read(fd, after, sizeof(after)), sizeof(after)); > close(fd); > > after[0] -= before[0]; > @@ -796,9 +797,9 @@ static uint64_t __engine_order(int i915, > gem_execbuf(i915, eb); > } > > - read(fd, before, sizeof(before)); > + igt_assert_eq(read(fd, before, sizeof(before)), sizeof(before)); > gem_sync(i915, obj->handle); > - read(fd, after, sizeof(after)); > + igt_assert_eq(read(fd, after, sizeof(after)), sizeof(after)); > close(fd); > > after[0] -= before[0]; > diff --git a/tests/intel/i915_query.c b/tests/intel/i915_query.c > index f886297ed..4d706d62b 100644 > --- a/tests/intel/i915_query.c > +++ b/tests/intel/i915_query.c > @@ -491,7 +491,7 @@ test_query_topology_matches_eu_total(int fd) > > free(topo_info); > > - igt_assert(n_eus_topology == n_eus); > + igt_assert_eq(n_eus_topology, n_eus); > } > > /* > @@ -1380,7 +1380,7 @@ static void query_parse_and_validate_hwconfig_table(int i915) > i915_query_items(i915, &item, 1); > igt_assert(item.length == table_size); > igt_info("Table size = %d bytes\n", table_size); > - igt_assert(table_size > 0); > + igt_assert_lt(0, table_size); > > /* HWConfig table is a list of KLV sets */ > max_words = table_size / sizeof(uint32_t); > @@ -1391,21 +1391,21 @@ static void query_parse_and_validate_hwconfig_table(int i915) > igt_assert(data[i] < __INTEL_HWCONFIG_KEY_LIMIT); > > len = data[i + 1]; > - igt_assert(len > 0); > - igt_assert((i + 2 + len) <= max_words); > + igt_assert_lt(0, len); > + igt_assert_lte((i + 2 + len), max_words); > > igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]); > > value = data[i + 2]; > switch (data[i]) { > case INTEL_HWCONFIG_MEMORY_TYPE: > - igt_assert(len == 1); > + igt_assert_eq(len, 1); > igt_assert(value < __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT); > igt_info("%s\n", hwconfig_memtypes[value]); > break; > > case INTEL_HWCONFIG_CACHE_TYPES: > - igt_assert(len == 1); > + igt_assert_eq(len, 1); > > if (!value) > igt_info("-\n"); > diff --git a/tests/intel/kms_big_fb.c b/tests/intel/kms_big_fb.c > index 605813f7f..b808b4a02 100644 > --- a/tests/intel/kms_big_fb.c > +++ b/tests/intel/kms_big_fb.c > @@ -307,7 +307,7 @@ static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width, > igt_remove_fb(data->drm_fd, &col_fb); > } > > - igt_assert(drmIoctl(data->drm_fd, DRM_IOCTL_MODE_ADDFB2, &f) == 0); > + do_ioctl(data->drm_fd, DRM_IOCTL_MODE_ADDFB2, &f); > newfb->fb_id = f.fb_id; > } > > diff --git a/tests/intel/kms_busy.c b/tests/intel/kms_busy.c > index db45e286e..5917b888f 100644 > --- a/tests/intel/kms_busy.c > +++ b/tests/intel/kms_busy.c > @@ -388,7 +388,7 @@ static void gpu_engines_init_timeouts(int fd, int max_engines, > > *num_engines = 0; > for_each_physical_engine(fd, e) { > - igt_assert(*num_engines < max_engines); > + igt_assert_lt(*num_engines, max_engines); > > props[*num_engines].engine = *e; > props[*num_engines].preempt_timeout = 0; > diff --git a/tests/intel/kms_ccs.c b/tests/intel/kms_ccs.c > index c91370a9a..f262b271c 100644 > --- a/tests/intel/kms_ccs.c > +++ b/tests/intel/kms_ccs.c > @@ -348,7 +348,7 @@ static void check_ccs_cc_plane(int drm_fd, igt_fb_t *fb, int plane, const float > (uint8_t)(cc_color[1] * 0xff) << 8 | > (uint8_t)(cc_color[2] * 0xff); > > - igt_assert(native_color == cc_p[4].d); > + igt_assert_eq_u32(native_color, cc_p[4].d); > > igt_assert(gem_munmap(map, fb->size) == 0); > }; > diff --git a/tests/intel/kms_cdclk.c b/tests/intel/kms_cdclk.c > index 7baf7d98e..6fe6e6c3f 100644 > --- a/tests/intel/kms_cdclk.c > +++ b/tests/intel/kms_cdclk.c > @@ -236,9 +236,8 @@ static void test_mode_transition(data_t *data, enum pipe pipe, igt_output_t *out > mode_hi = get_highres_mode(output); > igt_require(mode_hi != NULL); > > - if (mode_hi->hdisplay == mode_lo->hdisplay && > - mode_hi->vdisplay == mode_lo->vdisplay) > - igt_skip("Highest and lowest mode resolutions are same; no transition\n"); > + igt_skip_on_f(mode_hi->hdisplay == mode_lo->hdisplay && mode_hi->vdisplay == mode_lo->vdisplay, > + "Highest and lowest mode resolutions are same; no transition\n"); > > primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); > > diff --git a/tests/intel/kms_dsc_helper.c b/tests/intel/kms_dsc_helper.c > index 58057aca3..0de09b8e9 100644 > --- a/tests/intel/kms_dsc_helper.c > +++ b/tests/intel/kms_dsc_helper.c > @@ -35,7 +35,7 @@ void save_force_dsc_en(int drmfd, igt_output_t *output) > igt_is_force_dsc_enabled(drmfd, output->name); > force_dsc_restore_fd = > igt_get_dsc_debugfs_fd(drmfd, output->name); > - igt_assert(force_dsc_restore_fd >= 0); > + igt_assert_lte(0, force_dsc_restore_fd); > } > > void restore_force_dsc_en(void) > @@ -163,7 +163,7 @@ void save_force_dsc_fractional_bpp_en(int drmfd, igt_output_t *output) > igt_is_force_dsc_fractional_bpp_enabled(drmfd, output->name); > force_dsc_fractional_bpp_restore_fd = > igt_get_dsc_fractional_bpp_debugfs_fd(drmfd, output->name); > - igt_assert(force_dsc_fractional_bpp_restore_fd >= 0); > + igt_assert_lte(0, force_dsc_fractional_bpp_restore_fd); > } > > void restore_force_dsc_fractional_bpp_en(void) > diff --git a/tests/intel/kms_fbcon_fbt.c b/tests/intel/kms_fbcon_fbt.c > index 71e42f19c..edf6f8d4e 100644 > --- a/tests/intel/kms_fbcon_fbt.c > +++ b/tests/intel/kms_fbcon_fbt.c > @@ -317,8 +317,7 @@ static void fbc_skips_on_fbcon(int debugfs_fd) > for (i = 0; skip == false && i < ARRAY_SIZE(reasons); i++) > skip = strstr(buf, reasons[i]); > > - if (skip) > - igt_skip("fbcon modeset is not compatible with FBC\n"); > + igt_skip_on_f(skip, "fbcon modeset is not compatible with FBC\n"); > } > > static void psr_skips_on_fbcon(int debugfs_fd) > diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c > index e1318bfa6..1aef1e02d 100644 > --- a/tests/intel/kms_pm_dc.c > +++ b/tests/intel/kms_pm_dc.c > @@ -230,11 +230,10 @@ static uint32_t get_dc_counter(char *dc_data) > long ret; > char *s = strchr(dc_data, ':'); > > - assert(s); > + igt_assert(s); > s++; > ret = strtol(s, &e, 10); > - assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) && > - e > s && *e == '\n' && ret >= 0); > + igt_assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) && e > s && *e == '\n' && ret >= 0); > return ret; > } > > @@ -611,8 +610,8 @@ static void test_deep_pkgc_state(data_t *data) > } > > /* Skip the test if no VRR capable output is found */ > - if (!vrr_supported) > - igt_skip("No VRR capable output found, skipping the test.\n"); > + igt_skip_on_f(!vrr_supported, > + "No VRR capable output found, skipping the test.\n"); > > igt_display_reset(display); > > diff --git a/tests/intel/kms_pm_rpm.c b/tests/intel/kms_pm_rpm.c > index 66c68b902..5af3e81bc 100644 > --- a/tests/intel/kms_pm_rpm.c > +++ b/tests/intel/kms_pm_rpm.c > @@ -1527,7 +1527,7 @@ static void pm_test_tiling(void) > gem_set_tiling(drm_fd, handles[j], > tiling_modes[i], stride); > gem_get_tiling(drm_fd, handles[j], &ti, &sw); > - igt_assert(tiling_modes[i] == ti); > + igt_assert_eq_u32(tiling_modes[i], ti); > } > > enable_one_screen_and_wait(&ms_data); > diff --git a/tests/intel/kms_psr.c b/tests/intel/kms_psr.c > index f3caa9ecc..cf0ce4bb8 100644 > --- a/tests/intel/kms_psr.c > +++ b/tests/intel/kms_psr.c > @@ -499,27 +499,27 @@ static void fill_render(data_t *data, const struct igt_fb *fb, > > static bool psr_wait_entry_if_enabled(data_t *data) > { > - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) > - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", > - data->op_psr_mode); > + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), > + "enable_psr modparam doesn't allow psr mode %d\n", > + data->op_psr_mode); > > return psr_wait_entry(data->debugfs_fd, data->op_psr_mode, data->output); > } > > static bool psr_wait_update_if_enabled(data_t *data) > { > - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) > - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", > - data->op_psr_mode); > + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), > + "enable_psr modparam doesn't allow psr mode %d\n", > + data->op_psr_mode); > > return psr_wait_update(data->debugfs_fd, data->op_psr_mode, data->output); > } > > static bool psr_enable_if_enabled(data_t *data) > { > - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) > - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", > - data->op_psr_mode); > + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), > + "enable_psr modparam doesn't allow psr mode %d\n", > + data->op_psr_mode); > > return psr_enable(data->drm_fd, data->debugfs_fd, data->op_psr_mode, data->output); > } > diff --git a/tests/intel/perf.c b/tests/intel/perf.c > index 95b17f522..c5a103c94 100644 > --- a/tests/intel/perf.c > +++ b/tests/intel/perf.c > @@ -493,12 +493,12 @@ __perf_open(int fd, struct drm_i915_perf_open_param *param, bool prevent_pm) > > ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param); > > - igt_assert(ret >= 0); > + igt_assert_lte(0, ret); > errno = 0; > > if (prevent_pm) { > pm_fd = open("/dev/cpu_dma_latency", O_RDWR); > - igt_assert(pm_fd >= 0); > + igt_assert_lte(0, pm_fd); > > igt_assert_eq(write(pm_fd, &pm_value, sizeof(pm_value)), sizeof(pm_value)); > } > @@ -625,7 +625,7 @@ elapsed_delta(uint64_t t1, uint64_t t0, uint32_t width) > { > uint32_t max_bits = sizeof(t1) * 8; > > - igt_assert(width <= max_bits); > + igt_assert_lte_u32(width, max_bits); > > if (t1 < t0 && width != max_bits) > return ((1ULL << width) - t0) + t1; > @@ -2128,7 +2128,7 @@ test_oa_exponents(const struct intel_execution_engine2 *e) > /* igt_debug(" > read %i bytes\n", ret); */ > > /* We should never have no data. */ > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > > for (int offset = 0; > offset < ret && n_timer_reports < NUM_TIMER_REPORTS; > @@ -2472,7 +2472,7 @@ test_blocking(uint64_t requested_oa_period, > errno == EINTR) > ; > > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > > /* For Haswell reports don't contain a well defined reason > * field we so assume all reports to be 'periodic'. For gen8+ > @@ -2526,12 +2526,12 @@ test_blocking(uint64_t requested_oa_period, > /* With completely broken blocking (but also not returning an error) we > * could end up with an open loop, > */ > - igt_assert(n <= (max_iterations + n_extra_iterations)); > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > /* Make sure the driver is reporting new samples with a reasonably > * low latency... > */ > - igt_assert(n > (min_iterations + n_extra_iterations)); > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > if (!set_kernel_hrtimer) > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > @@ -2728,12 +2728,12 @@ test_polling(uint64_t requested_oa_period, > /* With completely broken blocking while polling (but still somehow > * reporting a POLLIN event) we could end up with an open loop. > */ > - igt_assert(n <= (max_iterations + n_extra_iterations)); > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > /* Make sure the driver is reporting new samples with a reasonably > * low latency... > */ > - igt_assert(n > (min_iterations + n_extra_iterations)); > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > if (!set_kernel_hrtimer) > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > @@ -2821,7 +2821,7 @@ num_valid_reports_captured(struct drm_i915_perf_open_param *param, > errno == EINTR) > ; > > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > > for (int offset = 0; offset < ret; offset += header->size) { > header = (void *)(buf + offset); > @@ -3343,7 +3343,7 @@ test_short_reads(void) > ret = read(stream_fd, > header, > page_size); > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > } while (header->type == DRM_I915_PERF_RECORD_OA_REPORT_LOST); > > igt_assert_eq(ret, record_size); > @@ -5001,7 +5001,7 @@ static int i915_perf_add_config(int fd, struct drm_i915_perf_oa_config *config) > int config_id = __i915_perf_add_config(fd, config); > > igt_debug("config_id=%i\n", config_id); > - igt_assert(config_id > 0); > + igt_assert_lt(0, config_id); > > return config_id; > } > @@ -5339,7 +5339,7 @@ test_whitelisted_registers_userspace_config(void) > > /* Create a new config */ > ret = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, &config); > - igt_assert(ret > 0); /* Config 0 should be used by the kernel */ > + igt_assert_lt(0, ret); /* Config 0 should be used by the kernel */ > config_id = ret; > > i915_perf_remove_config(drm_fd, config_id); > @@ -5360,7 +5360,7 @@ read_i915_module_ref(void) > if (strncmp(line, "i915 ", 5) == 0) { > unsigned long mem; > int ret = sscanf(line + 5, "%lu %u", &mem, &ref_count); > - igt_assert(ret == 2); > + igt_assert_eq(ret, 2); > goto done; > } > } > @@ -5381,7 +5381,7 @@ static int perf_sysfs_open(int i915) > for_each_sysfs_gt_dirfd(i915, dirfd, gt) > break; > > - igt_assert(dirfd != -1); > + igt_assert_neq(dirfd, -1); > > return dirfd; > } > @@ -5784,7 +5784,7 @@ test_group_exclusive_stream(const intel_ctx_t *ctx, bool exponent) > grp->perf_fd = igt_ioctl(drm_fd, > DRM_IOCTL_I915_PERF_OPEN, > ¶m); > - igt_assert(grp->perf_fd >= 0); > + igt_assert_lte(0, grp->perf_fd); > igt_debug("opened OA buffer with c:i %d:%d\n", > ci->engine_class, ci->engine_instance); > } > @@ -5826,7 +5826,7 @@ test_group_exclusive_stream(const intel_ctx_t *ctx, bool exponent) > param.num_properties = ARRAY_SIZE(properties) / 2 - 1; > errno = 0; > err = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m); > - igt_assert(err < 0); > + igt_assert_lt(err, 0); > igt_assert(errno == EBUSY || errno == ENODEV); > igt_debug("try OA ci unit with c:i %d:%d\n", > ci->engine_class, ci->engine_instance); > diff --git a/tests/intel/perf_pmu.c b/tests/intel/perf_pmu.c > index e3f51d0c7..bfa2d501a 100644 > --- a/tests/intel/perf_pmu.c > +++ b/tests/intel/perf_pmu.c > @@ -200,7 +200,7 @@ static char *get_drpc(int i915, int gt_id) > int gt_dir; > > gt_dir = igt_debugfs_gt_dir(i915, gt_id); > - igt_assert(gt_dir != -1); > + igt_assert_neq(gt_dir, -1); > return igt_sysfs_get(gt_dir, "drpc"); > } > > @@ -210,7 +210,7 @@ static int open_pmu(int i915, uint64_t config) > > fd = perf_i915_open(i915, config); > igt_skip_on(fd < 0 && errno == ENODEV); > - igt_assert(fd >= 0); > + igt_assert_lte(0, fd); > > return fd; > } > @@ -221,7 +221,7 @@ static int open_group(int i915, uint64_t config, int group) > > fd = perf_i915_open_group(i915, config, group); > igt_skip_on(fd < 0 && errno == ENODEV); > - igt_assert(fd >= 0); > + igt_assert_lte(0, fd); > > return fd; > } > @@ -527,7 +527,7 @@ static void log_busy(unsigned int num_engines, uint64_t *val) > int len; > > len = snprintf(p, rem, "%u=%" PRIu64 "\n", i, val[i]); > - igt_assert(len > 0); > + igt_assert_lt(0, len); > rem -= len; > p += len; > } > @@ -950,7 +950,7 @@ __sema_busy(int gem_fd, uint64_t ahnd, int pmu, const intel_ctx_t *ctx, > int timeout = 3; > > /* Time spent being busy includes time waiting on semaphores */ > - igt_assert(busy_pct >= sema_pct); > + igt_assert_lte(sema_pct, busy_pct); > > gem_quiescent_gpu(gem_fd); > > @@ -1359,7 +1359,7 @@ static void open_invalid(int i915) > int fd; > > fd = perf_i915_open(i915, -1ULL); > - igt_assert(fd < 0); > + igt_assert_lt(fd, 0); > } > > static bool cpu0_hotplug_support(void) > @@ -1415,7 +1415,7 @@ static void cpu_hotplug(int gem_fd) > cpu), sizeof(name)); > cpufd = open(name, O_WRONLY); > if (cpufd == -1) { > - igt_assert(cpu > 0); > + igt_assert_lt(0, cpu); > /* > * Signal parent that we cycled through all > * CPUs and we are done. > @@ -1534,7 +1534,7 @@ test_interrupts(int gem_fd) > close(old_fd); > } > > - igt_assert(fence_fd >= 0); > + igt_assert_lte(0, fence_fd); > } > > /* Wait for idle state. */ > @@ -1755,9 +1755,9 @@ test_frequency(int gem_fd, unsigned int gt) > */ > __igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq); > __igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz", &read_value); > - if (read_value != min_freq) > - igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n", > - min_freq, read_value); > + igt_warn_on_f(read_value != min_freq, > + "Unable to restore min frequency to saved value [%u MHz], now %u MHz\n", > + min_freq, read_value); > close(fd[0]); > close(fd[1]); > put_ahnd(ahnd); > @@ -1880,7 +1880,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) > continue; > > if (gt_ == gt) { > - igt_assert(test_idx == -1); > + igt_assert_eq(test_idx, -1); > test_idx = pmus; > } > > @@ -1890,7 +1890,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) > igt_skip_on(fd[pmus] < 0 && errno == ENODEV); > pmus++; > } > - igt_assert(test_idx >= 0); > + igt_assert_lte(0, test_idx); > > if (flags & TEST_RUNTIME_PM) { > drmModeRes *res; > @@ -1981,7 +1981,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) > continue; > > fw[gt_] = open_forcewake_handle(gem_fd, gt_); > - igt_assert(fw[gt_] >= 0); > + igt_assert_lte(0, fw[gt_]); > } > > usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */ > @@ -2206,7 +2206,8 @@ accuracy(int gem_fd, const intel_ctx_t *ctx, > 100 * expected, target_busy_pct, > avg, sqrt(var / n)); > > - write(link[1], &expected, sizeof(expected)); > + igt_assert_eq(write(link[1], &expected, sizeof(expected)), > + sizeof(expected)); > } > > igt_spin_free(gem_fd, spin); > @@ -2216,12 +2217,14 @@ accuracy(int gem_fd, const intel_ctx_t *ctx, > fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance)); > > /* Let the child run. */ > - read(link[0], &expected, sizeof(expected)); > + igt_assert_eq(read(link[0], &expected, sizeof(expected)), > + sizeof(expected)); > assert_within(100.0 * expected, target_busy_pct, 5); > > /* Collect engine busyness for an interesting part of child runtime. */ > val[0] = __pmu_read_single(fd, &ts[0]); > - read(link[0], &expected, sizeof(expected)); > + igt_assert_eq(read(link[0], &expected, sizeof(expected)), > + sizeof(expected)); > val[1] = __pmu_read_single(fd, &ts[1]); > close(fd); > > diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c > index beccfcb1a..a55ee5abd 100644 > --- a/tests/intel/xe_ccs.c > +++ b/tests/intel/xe_ccs.c > @@ -212,7 +212,7 @@ static void surf_copy(int xe, > WRITE_PNG(xe, run_id, "corrupted", &blt.dst, dst->x2, dst->y2, bpp); > result = memcmp(src->ptr, dst->ptr, src->size); > if (blt_platform_has_flat_ccs_enabled(xe)) > - igt_assert(result != 0); > + igt_assert_neq(result, 0); > > /* In case of suspend_resume, buffer object would become > * uncompressed in xe2+ dgfx, and therefore retrieve the > @@ -696,7 +696,7 @@ static int opt_handler(int opt, int opt_index, void *data) > case 'f': > param.compression_format = atoi(optarg); > igt_debug("Compression format: %d\n", param.compression_format); > - igt_assert((param.compression_format & ~0x1f) == 0); > + igt_assert_eq((param.compression_format & ~0x1f), 0); > break; > case 'p': > param.write_png = true; > diff --git a/tests/intel/xe_debugfs.c b/tests/intel/xe_debugfs.c > index a7d56a0be..a7c567c45 100644 > --- a/tests/intel/xe_debugfs.c > +++ b/tests/intel/xe_debugfs.c > @@ -222,7 +222,7 @@ test_forcewake(int fd) > { > int handle = igt_debugfs_open(fd, "forcewake_all", O_WRONLY); > > - igt_assert(handle != -1); > + igt_assert_neq(handle, -1); > close(handle); > } > > diff --git a/tests/intel/xe_dma_buf_sync.c b/tests/intel/xe_dma_buf_sync.c > index f0d3f0d54..7af80dd2f 100644 > --- a/tests/intel/xe_dma_buf_sync.c > +++ b/tests/intel/xe_dma_buf_sync.c > @@ -108,7 +108,7 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, > } *data [MAX_N_BO]; > int i; > > - igt_assert(n_bo <= MAX_N_BO); > + igt_assert_lte(n_bo, MAX_N_BO); > > for (i = 0; i < N_FD; ++i) { > fd[i] = drm_open_driver(DRIVER_XE); > diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c > index eebdbc84b..f0c66c49e 100644 > --- a/tests/intel/xe_evict.c > +++ b/tests/intel/xe_evict.c > @@ -57,7 +57,7 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci, > } *data; > int i, b; > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > bo = calloc(n_execs / 2, sizeof(*bo)); > igt_assert(bo); > @@ -237,7 +237,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, > } *data; > int i, b; > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > bo = calloc(n_execs / 2, sizeof(*bo)); > igt_assert(bo); > diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c > index a6dbd748b..73f69e7b0 100644 > --- a/tests/intel/xe_exec_balancer.c > +++ b/tests/intel/xe_exec_balancer.c > @@ -190,7 +190,7 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs, > struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; > int i, j, b, num_placements = 0; > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > xe_for_each_engine(fd, hwe) { > if (hwe->engine_class != class || hwe->gt_id != gt) > @@ -410,7 +410,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > int i, j, b, num_placements = 0; > int map_fd = -1; > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > xe_for_each_engine(fd, hwe) { > if (hwe->engine_class != class || hwe->gt_id != gt) > @@ -534,7 +534,8 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > if (flags & RACE) { > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > 0x666); > - write(map_fd, data, bo_size); > + igt_assert_eq(write(map_fd, data, bo_size), > + bo_size); > data = mmap((void *)MAP_ADDRESS, bo_size, > PROT_READ | PROT_WRITE, MAP_SHARED | > MAP_FIXED, map_fd, 0); > diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c > index 0fd1ae062..dfbd68d1d 100644 > --- a/tests/intel/xe_exec_basic.c > +++ b/tests/intel/xe_exec_basic.c > @@ -122,8 +122,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > } *data; > int i, b; > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > - igt_assert(n_vm <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_vm, MAX_N_EXEC_QUEUES); > > for (i = 0; i < n_vm; ++i) > vm[i] = xe_vm_create(fd, 0, 0); > diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c > index 389de7ca4..b92feee2c 100644 > --- a/tests/intel/xe_exec_compute_mode.c > +++ b/tests/intel/xe_exec_compute_mode.c > @@ -115,7 +115,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > int map_fd = -1; > int64_t fence_timeout; > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); > bo_size = sizeof(*data) * n_execs; > @@ -243,7 +243,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > if (flags & RACE) { > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > 0x666); > - write(map_fd, data, bo_size); > + igt_assert_eq(write(map_fd, data, bo_size), > + bo_size); > data = mmap((void *)MAP_ADDRESS, bo_size, > PROT_READ | PROT_WRITE, MAP_SHARED | > MAP_FIXED, map_fd, 0); > @@ -457,7 +458,7 @@ static void lr_mode_workload(int fd) > ts_1 = spin->timestamp; > sleep(1); > ts_2 = spin->timestamp; > - igt_assert(ts_1 != ts_2); > + igt_assert_neq_u32(ts_1, ts_2); > > xe_spin_end(spin); > xe_wait_ufence(fd, &spin->exec_sync, USER_FENCE_VALUE, 0, ONE_SEC); > @@ -466,7 +467,7 @@ static void lr_mode_workload(int fd) > ts_1 = spin->timestamp; > sleep(1); > ts_2 = spin->timestamp; > - igt_assert(ts_1 == ts_2); > + igt_assert_eq_u32(ts_1, ts_2); > > sync.addr = to_user_pointer(&vm_sync); > xe_vm_unbind_async(fd, vm, 0, 0, spin_addr, bo_size, &sync, 1); > diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c > index b022f97d3..56bad2b75 100644 > --- a/tests/intel/xe_exec_fault_mode.c > +++ b/tests/intel/xe_exec_fault_mode.c > @@ -140,7 +140,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > int i, j, b; > int map_fd = -1; > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > if (flags & ENABLE_SCRATCH) > vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE | > @@ -291,7 +291,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > if (flags & RACE) { > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > 0x666); > - write(map_fd, data, bo_size); > + igt_assert_eq(write(map_fd, data, bo_size), > + bo_size); > data = mmap((void *)MAP_ADDRESS, bo_size, > PROT_READ | PROT_WRITE, MAP_SHARED | > MAP_FIXED, map_fd, 0); > diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c > index dcb22f275..72f2133e5 100644 > --- a/tests/intel/xe_exec_reset.c > +++ b/tests/intel/xe_exec_reset.c > @@ -155,7 +155,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, > struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; > int i, j, b, num_placements = 0, bad_batches = 1; > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > if (flags & CLOSE_FD) > fd = drm_open_driver(DRIVER_XE); > @@ -326,7 +326,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, > struct xe_spin_opts spin_opts = { .preempt = false }; > int i, b; > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > if (flags & CLOSE_FD) > fd = drm_open_driver(DRIVER_XE); > @@ -475,7 +475,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > struct xe_spin_opts spin_opts = { .preempt = false }; > int i, b; > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > if (flags & CLOSE_FD) > fd = drm_open_driver(DRIVER_XE); > @@ -704,7 +704,7 @@ gt_reset(int fd, int n_threads, int n_sec) > for (i = 0; i < n_threads; i++) > pthread_join(threads[i].thread, NULL); > > - printf("number of resets %d\n", num_reset); > + igt_info("number of resets %d\n", num_reset); > > free(threads); > } > diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c > index c872c22d5..5c1dd0a01 100644 > --- a/tests/intel/xe_exec_store.c > +++ b/tests/intel/xe_exec_store.c > @@ -249,7 +249,7 @@ static void store_cachelines(int fd, struct drm_xe_engine_class_instance *eci, > object_index = n % (count - 1); > ptr[n] = bo_map[object_index] + delta / 4; > > - igt_assert(*ptr[n] == value[n]); > + igt_assert_eq_u32(*ptr[n], value[n]); > } > > for (i = 0; i < count; i++) { > diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c > index e7a0a7cd0..6e53d3cf8 100644 > --- a/tests/intel/xe_exec_threads.c > +++ b/tests/intel/xe_exec_threads.c > @@ -70,7 +70,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr, > int i, j, b, num_placements = 0; > bool owns_vm = false, owns_fd = false; > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > if (flags & FD) { > fd = drm_reopen_driver(fd); > @@ -88,7 +88,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr, > > eci[num_placements++] = *hwe; > } > - igt_assert(num_placements > 1); > + igt_assert_lt(1, num_placements); > > bo_size = sizeof(*data) * n_execs; > bo_size = xe_bb_size(fd, bo_size); > @@ -272,7 +272,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > int map_fd = -1; > bool owns_vm = false, owns_fd = false; > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > if (flags & FD) { > fd = drm_reopen_driver(fd); > @@ -396,7 +396,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > if (flags & RACE) { > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > 0x666); > - write(map_fd, data, bo_size); > + igt_assert_eq(write(map_fd, data, bo_size), > + bo_size); > data = mmap(from_user_pointer(userptr), bo_size, > PROT_READ | PROT_WRITE, > MAP_SHARED | MAP_FIXED, > @@ -476,7 +477,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > int i, j, b, hang_exec_queue = n_exec_queues / 2; > bool owns_vm = false, owns_fd = false; > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > if (flags & FD) { > fd = drm_reopen_driver(fd); > diff --git a/tests/intel/xe_gt_freq.c b/tests/intel/xe_gt_freq.c > index 93ebb5ed0..365c9b9e6 100644 > --- a/tests/intel/xe_gt_freq.c > +++ b/tests/intel/xe_gt_freq.c > @@ -41,7 +41,7 @@ static int set_freq(int fd, int gt_id, const char *freq_name, uint32_t freq) > > snprintf(freq_attr, sizeof(freq_attr), "freq0/%s_freq", freq_name); > gt_fd = xe_sysfs_gt_open(fd, gt_id); > - igt_assert(gt_fd >= 0); > + igt_assert_lte(0, gt_fd); > > while (ret == -EAGAIN) > ret = igt_sysfs_printf(gt_fd, freq_attr, "%u", freq); > @@ -59,7 +59,7 @@ static uint32_t get_freq(int fd, int gt_id, const char *freq_name) > > snprintf(freq_attr, sizeof(freq_attr), "freq0/%s_freq", freq_name); > gt_fd = xe_sysfs_gt_open(fd, gt_id); > - igt_assert(gt_fd >= 0); > + igt_assert_lte(0, gt_fd); > > while (err == -EAGAIN) > err = igt_sysfs_scanf(gt_fd, freq_attr, "%u", &freq); > @@ -84,7 +84,7 @@ static uint32_t get_throttle(int fd, int gt_id, const char *throttle_file) > snprintf(throttle_attr, sizeof(throttle_attr), > "freq0/throttle/%s", throttle_file); > gt_fd = xe_sysfs_gt_open(fd, gt_id); > - igt_assert(gt_fd >= 0); > + igt_assert_lte(0, gt_fd); > > igt_sysfs_scanf(gt_fd, throttle_attr, "%u", &val); > > @@ -134,26 +134,26 @@ static void test_freq_basic_api(int fd, int gt_id) > * RPn is the floor > * RP0 is the ceiling > */ > - igt_assert(set_freq(fd, gt_id, "min", rpn - 1) < 0); > - igt_assert(set_freq(fd, gt_id, "min", rp0 + 1) < 0); > - igt_assert(set_freq(fd, gt_id, "max", rpn - 1) < 0); > - igt_assert(set_freq(fd, gt_id, "max", rp0 + 1) < 0); > + igt_assert_lt(set_freq(fd, gt_id, "min", rpn - 1), 0); > + igt_assert_lt(set_freq(fd, gt_id, "min", rp0 + 1), 0); > + igt_assert_lt(set_freq(fd, gt_id, "max", rpn - 1), 0); > + igt_assert_lt(set_freq(fd, gt_id, "max", rp0 + 1), 0); > > /* Assert min requests are respected from rp0 to rpn */ > - igt_assert(set_freq(fd, gt_id, "min", rp0) > 0); > - igt_assert(get_freq(fd, gt_id, "min") == rp0); > - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); > - igt_assert(get_freq(fd, gt_id, "min") == rpe(fd, gt_id)); > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > - igt_assert(get_freq(fd, gt_id, "min") == rpn); > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rp0)); > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rp0); > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpe(fd, gt_id)); > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpn); > > /* Assert max requests are respected from rpn to rp0 */ > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > - igt_assert(get_freq(fd, gt_id, "max") == rpn); > - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); > - igt_assert(get_freq(fd, gt_id, "max") == rpe(fd, gt_id)); > - igt_assert(set_freq(fd, gt_id, "max", rp0) > 0); > - igt_assert(get_freq(fd, gt_id, "max") == rp0); > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpn); > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpe(fd, gt_id)); > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rp0)); > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rp0); > } > > /** > @@ -176,10 +176,10 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle) > * Then we check if hardware is actually operating at the desired freq > * And let's do this for all the 3 known Render Performance (RP) values. > */ > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > usleep(ACT_FREQ_LATENCY_US); > - igt_assert(get_freq(fd, gt_id, "cur") == rpn); > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpn); > > if (gt_idle) { > /* Wait for GT to go in C6 as previous get_freq wakes up GT*/ > @@ -187,31 +187,31 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle) > "GT %d should be in C6\n", gt_id); > igt_assert(get_freq(fd, gt_id, "act") == 0); > } else { > - igt_assert(get_freq(fd, gt_id, "act") == rpn); > + igt_assert_eq_u32(get_freq(fd, gt_id, "act"), rpn); > } > > - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); > - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); > usleep(ACT_FREQ_LATENCY_US); > - igt_assert(get_freq(fd, gt_id, "cur") == rpe(fd, gt_id)); > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpe(fd, gt_id)); > > if (gt_idle) { > igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10), > "GT %d should be in C6\n", gt_id); > igt_assert(get_freq(fd, gt_id, "act") == 0); > } else { > - igt_assert(get_freq(fd, gt_id, "act") == rpe(fd, gt_id)); > + igt_assert_eq_u32(get_freq(fd, gt_id, "act"), rpe(fd, gt_id)); > } > > - igt_assert(set_freq(fd, gt_id, "min", rp0) > 0); > - igt_assert(set_freq(fd, gt_id, "max", rp0) > 0); > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rp0)); > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rp0)); > usleep(ACT_FREQ_LATENCY_US); > /* > * It is unlikely that PCODE will *always* respect any request above RPe > * So for this level let's only check if GuC PC is doing its job > * and respecting our request, by propagating it to the hardware. > */ > - igt_assert(get_freq(fd, gt_id, "cur") == rp0); > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rp0); > > if (gt_idle) { > igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10), > @@ -236,8 +236,8 @@ static void test_freq_range(int fd, int gt_id, bool gt_idle) > > igt_debug("Starting testing range request\n"); > > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); > usleep(ACT_FREQ_LATENCY_US); > cur = get_freq(fd, gt_id, "cur"); > igt_assert(rpn <= cur && cur <= rpe(fd, gt_id)); > @@ -267,12 +267,12 @@ static void test_freq_low_max(int fd, int gt_id) > * When max request < min request, max is ignored and min works like > * a fixed one. Let's assert this assumption > */ > - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > usleep(ACT_FREQ_LATENCY_US); > > /* Refresh value of rpe, pcode could have adjusted it */ > - igt_assert(get_freq(fd, gt_id, "cur") == rpe(fd, gt_id)); > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpe(fd, gt_id)); > } > > /** > @@ -284,16 +284,16 @@ static void test_suspend(int fd, int gt_id) > { > uint32_t rpn = get_freq(fd, gt_id, "rpn"); > > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > usleep(ACT_FREQ_LATENCY_US); > - igt_assert(get_freq(fd, gt_id, "cur") == rpn); > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpn); > > igt_system_suspend_autoresume(SUSPEND_STATE_S3, > SUSPEND_TEST_NONE); > > - igt_assert(get_freq(fd, gt_id, "min") == rpn); > - igt_assert(get_freq(fd, gt_id, "max") == rpn); > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpn); > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpn); > } > > /** > diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c > index 647fd64e7..845052bf2 100644 > --- a/tests/intel/xe_intel_bb.c > +++ b/tests/intel/xe_intel_bb.c > @@ -674,11 +674,11 @@ static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling) > > /* We'll fail on src <-> final compare so just warn */ > if (tiling == I915_TILING_NONE) { > - if (compare_bufs(&src, &dst, false) > 0) > - igt_warn("none->none blit failed!"); > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > + "none->none blit failed!"); > } else { > - if (compare_bufs(&src, &dst, false) == 0) > - igt_warn("none->tiled blit failed!"); > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > + "none->tiled blit failed!"); > } > > fails = compare_bufs(&src, &final, true); > @@ -925,11 +925,11 @@ static int render(struct buf_ops *bops, uint32_t tiling, > > /* We'll fail on src <-> final compare so just warn */ > if (tiling == I915_TILING_NONE) { > - if (compare_bufs(&src, &dst, false) > 0) > - igt_warn("%s: none->none failed!\n", __func__); > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > + "%s: none->none failed!\n", __func__); > } else { > - if (compare_bufs(&src, &dst, false) == 0) > - igt_warn("%s: none->tiled failed!\n", __func__); > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > + "%s: none->tiled failed!\n", __func__); > } > > fails = compare_bufs(&src, &final, true); > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c > index ff2218300..e26ebceb9 100644 > --- a/tests/intel/xe_oa.c > +++ b/tests/intel/xe_oa.c > @@ -492,12 +492,12 @@ __perf_open(int fd, struct intel_xe_oa_open_prop *param, bool prevent_pm) > > ret = intel_xe_perf_ioctl(fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, param); > > - igt_assert(ret >= 0); > + igt_assert_lte(0, ret); > errno = 0; > > if (prevent_pm) { > pm_fd = open("/dev/cpu_dma_latency", O_RDWR); > - igt_assert(pm_fd >= 0); > + igt_assert_lte(0, pm_fd); > > igt_assert_eq(write(pm_fd, &pm_value, sizeof(pm_value)), sizeof(pm_value)); > } > @@ -568,7 +568,7 @@ elapsed_delta(uint64_t t1, uint64_t t0, uint32_t width) > { > uint32_t max_bits = sizeof(t1) * 8; > > - igt_assert(width <= max_bits); > + igt_assert_lte_u32(width, max_bits); > > if (t1 < t0 && width != max_bits) > return ((1ULL << width) - t0) + t1; > @@ -1710,7 +1710,7 @@ static void test_oa_exponents(const struct drm_xe_engine_class_instance *hwe) > > /* igt_debug(" > read %i bytes\n", ret); */ > /* We should never have no data. */ > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > > for (int offset = 0; > offset < ret && n_timer_reports < NUM_TIMER_REPORTS; > @@ -1933,7 +1933,7 @@ static void test_blocking(uint64_t requested_oa_period, > while ((ret = read(perf_fd, buf, sizeof(buf))) < 0 && > (errno == EINTR || errno == EIO)) > ; > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > > for (int offset = 0; offset < ret; offset += format_size) { > uint32_t *report = (void *)(buf + offset); > @@ -1972,12 +1972,12 @@ static void test_blocking(uint64_t requested_oa_period, > /* With completely broken blocking (but also not returning an error) we > * could end up with an open loop, > */ > - igt_assert(n <= (max_iterations + n_extra_iterations)); > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > /* Make sure the driver is reporting new samples with a reasonably > * low latency... > */ > - igt_assert(n > (min_iterations + n_extra_iterations)); > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > if (!set_kernel_hrtimer) > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > @@ -2163,12 +2163,12 @@ static void test_polling(uint64_t requested_oa_period, > /* With completely broken blocking while polling (but still somehow > * reporting a POLLIN event) we could end up with an open loop. > */ > - igt_assert(n <= (max_iterations + n_extra_iterations)); > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > /* Make sure the driver is reporting new samples with a reasonably > * low latency... > */ > - igt_assert(n > (min_iterations + n_extra_iterations)); > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > if (!set_kernel_hrtimer) > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > @@ -2260,7 +2260,7 @@ num_valid_reports_captured(struct intel_xe_oa_open_prop *param, > (errno == EINTR || errno == EIO)) > ; > > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > > for (int offset = 0; offset < ret; offset += format_size) { > uint32_t *report = (void *)(buf + offset); > @@ -3473,7 +3473,7 @@ static int xe_oa_add_config(int fd, struct drm_xe_oa_config *config) > int config_id = __xe_oa_add_config(fd, config); > > igt_debug("config_id=%i\n", config_id); > - igt_assert(config_id > 0); > + igt_assert_lt(0, config_id); > > return config_id; > } > @@ -3769,7 +3769,7 @@ test_whitelisted_registers_userspace_config(void) > > /* Create a new config */ > ret = intel_xe_perf_ioctl(drm_fd, DRM_XE_OBSERVATION_OP_ADD_CONFIG, &config); > - igt_assert(ret > 0); /* Config 0 should be used by the kernel */ > + igt_assert_lt(0, ret); /* Config 0 should be used by the kernel */ > config_id = ret; > > xe_oa_remove_config(drm_fd, config_id); > @@ -4195,7 +4195,7 @@ test_oa_unit_exclusive_stream(bool exponent) > properties[11] = exec_q[i]; > errno = 0; > err = intel_xe_perf_ioctl(drm_fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, ¶m); > - igt_assert(err < 0); > + igt_assert_lt(err, 0); > igt_assert(errno == EBUSY || errno == ENODEV); > poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); > } > diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c > index 82155f1d5..153d9ce1d 100644 > --- a/tests/intel/xe_pat.c > +++ b/tests/intel/xe_pat.c > @@ -808,7 +808,7 @@ static void display_vs_wb_transient(int fd) > > /* c0 -> c6 might flush caches */ > fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY); > - igt_assert(fw_handle >= 0); > + igt_assert_lte(0, fw_handle); > > render_copy(ibb, > &src, > diff --git a/tests/intel/xe_peer2peer.c b/tests/intel/xe_peer2peer.c > index 6ff4774bb..2a941abe6 100644 > --- a/tests/intel/xe_peer2peer.c > +++ b/tests/intel/xe_peer2peer.c > @@ -279,7 +279,7 @@ static char *region_name(int xe, uint32_t region) > r = snprintf(name, len, "%s", > xe_region_name(region)); > > - igt_assert(r > 0); > + igt_assert_lt(0, r); > > return name; > } > diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c > index 8b115e2f6..eee89428c 100644 > --- a/tests/intel/xe_pm.c > +++ b/tests/intel/xe_pm.c > @@ -94,7 +94,7 @@ static uint64_t get_vram_d3cold_threshold(int sysfs) > igt_require_f(!faccessat(sysfs, path, R_OK, 0), "vram_d3cold_threshold is not present\n"); > > ret = igt_sysfs_scanf(sysfs, path, "%lu", &threshold); > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > > return threshold; > } > @@ -111,7 +111,7 @@ static void set_vram_d3cold_threshold(int sysfs, uint64_t threshold) > else > igt_warn("vram_d3cold_threshold is not present\n"); > > - igt_assert(ret > 0); > + igt_assert_lt(0, ret); > } > > static void vram_d3cold_threshold_restore(int sig) > @@ -305,8 +305,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci, > bool check_rpm = (d_state == IGT_ACPI_D3Hot || > d_state == IGT_ACPI_D3Cold); > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > - igt_assert(n_execs > 0); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > + igt_assert_lt(0, n_execs); > > if (check_rpm) { > igt_assert(in_d3(device, d_state)); > @@ -507,7 +507,7 @@ static void test_vram_d3cold_threshold(device_t device, int sysfs_fd) > * Therefore open and close fw handle to wake the device. > */ > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > - igt_assert(fw_handle >= 0); > + igt_assert_lte(0, fw_handle); > active = igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE; > close(fw_handle); > igt_assert(active); > @@ -557,7 +557,7 @@ static void test_mmap(device_t device, uint32_t placement, uint32_t flags, > > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > > - igt_assert(fw_handle >= 0); > + igt_assert_lte(0, fw_handle); > igt_assert(igt_pm_get_runtime_active_time(device.pci_xe) > > active_time); > > @@ -600,7 +600,7 @@ static void test_mmap(device_t device, uint32_t placement, uint32_t flags, > > /* Runtime resume and check the pattern */ > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > - igt_assert(fw_handle >= 0); > + igt_assert_lte(0, fw_handle); > igt_assert(igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE); > for (i = 0; i < bo_size / sizeof(*map); i++) > igt_assert(map[i] == MAGIC_2); > @@ -651,7 +651,7 @@ static void test_mocs_suspend_resume(device_t device, enum igt_suspend_state s_s > active_time = igt_pm_get_runtime_active_time(device.pci_xe); > > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > - igt_assert(fw_handle >= 0); > + igt_assert_lte(0, fw_handle); > igt_assert(igt_pm_get_runtime_active_time(device.pci_xe) > > active_time); > > diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c > index 51735d887..1d3ce0762 100644 > --- a/tests/intel/xe_pm_residency.c > +++ b/tests/intel/xe_pm_residency.c > @@ -182,7 +182,7 @@ static unsigned long read_idle_residency(int fd, int gt) > int gt_fd; > > gt_fd = xe_sysfs_gt_open(fd, gt); > - igt_assert(gt_fd >= 0); > + igt_assert_lte(0, gt_fd); > igt_assert(igt_sysfs_scanf(gt_fd, "gtidle/idle_residency_ms", "%lu", &residency) == 1); > close(gt_fd); > > @@ -280,7 +280,7 @@ static void toggle_gt_c6(int fd, int n) > > do { > fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY); > - igt_assert(fw_handle >= 0); > + igt_assert_lte(0, fw_handle); > /* check if all gts are in C0 after forcewake is acquired */ > xe_for_each_gt(fd, gt) > igt_assert_f(!xe_is_gt_in_c6(fd, gt), > diff --git a/tests/intel/xe_query.c b/tests/intel/xe_query.c > index c13613e0a..c6d88b258 100644 > --- a/tests/intel/xe_query.c > +++ b/tests/intel/xe_query.c > @@ -198,7 +198,7 @@ test_query_engines(int fd) > hwe->gt_id); > } > > - igt_assert(i > 0); > + igt_assert_lt(0, i); > } > > /** > @@ -464,15 +464,15 @@ test_query_gt_topology_l3_bank_mask(int fd) > > igt_info(" count: %d\n", count); > if (intel_get_device_info(dev_id)->graphics_ver < 20) { > - igt_assert(count > 0); > + igt_assert_lt(0, count); > } > > if (IS_METEORLAKE(dev_id)) > - igt_assert((count % 2) == 0); > + igt_assert_eq((count % 2), 0); > else if (IS_PONTEVECCHIO(dev_id)) > - igt_assert((count % 4) == 0); > + igt_assert_eq((count % 4), 0); > else if (IS_DG2(dev_id)) > - igt_assert((count % 8) == 0); > + igt_assert_eq((count % 8), 0); > } > > query.size -= sz; > @@ -786,7 +786,7 @@ __engine_cycles(int fd, struct drm_xe_engine_class_instance *hwe) > if (!((i + 1) % NUM_SNAPSHOTS)) { > igt_debug("clock %s\n", clock[index].name); > igt_debug("usable %d\n", usable); > - igt_assert(usable > 2); > + igt_assert_lt(2, usable); > usable = 0; > } > } > diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c > index a4f6c7a0b..f20a1f474 100644 > --- a/tests/intel/xe_vm.c > +++ b/tests/intel/xe_vm.c > @@ -408,7 +408,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo, > int n_exec_queues = n_bo, n_execs = n_bo; > int i, b; > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > bo = malloc(sizeof(*bo) * n_bo); > igt_assert(bo); > @@ -778,7 +778,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs, > } *data; > int i, b; > > - igt_assert(n_execs <= BIND_ARRAY_MAX_N_EXEC); > + igt_assert_lte(n_execs, BIND_ARRAY_MAX_N_EXEC); > > vm = xe_vm_create(fd, 0, 0); > bo_size = sizeof(*data) * n_execs; > @@ -974,7 +974,7 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci, > base_addr -= xe_get_default_alignment(fd); > } > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > vm = xe_vm_create(fd, 0, 0); > > if (flags & LARGE_BIND_FLAG_USERPTR) { ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [i-g-t,2/2] tests/intel: Apply igt.cocci transforms 2024-07-31 12:25 ` [i-g-t,2/2] " Vivekanandan, Balasubramani @ 2024-07-31 16:26 ` Matt Roper 2024-08-01 10:19 ` Vivekanandan, Balasubramani 0 siblings, 1 reply; 12+ messages in thread From: Matt Roper @ 2024-07-31 16:26 UTC (permalink / raw) To: Vivekanandan, Balasubramani; +Cc: igt-dev On Wed, Jul 31, 2024 at 05:55:48PM +0530, Vivekanandan, Balasubramani wrote: > On 29.07.2024 15:02, Matt Roper wrote: > > A number of Intel tests are using checks like "igt_assert(x < y)" rather > > than using the dedicated comparison assertions that print the actual > > values on assertion failure. Run the Intel test directory through > > Coccinelle to apply these conversions and also apply some other general > > coding style cleanup: > > > > spatch --in-place --sp-file lib/igt.cocci tests/intel > > There are some places in the code, where still igt_assert is retained > like these lines from file gem_ctx_create.c > > ``` > shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > igt_assert(shared != MAP_FAILED); > ``` > > Are these unspotted by Coccinelle? Yeah, it looks like the comparison transform rules we have today only apply to various integer types: @@ typedef uint32_t; uint32_t E1, E2; int E3, E4; @@ ( - igt_assert(E1 == E2); + igt_assert_eq_u32(E1, E2); | - igt_assert(E1 != E2); + igt_assert_neq_u32(E1, E2); | mmap returns a pointer, so it isn't transformed by the current rules. We could always extend the rules in the future to cover pointers as well, although some cases like this specific example aren't terribly important (since if we trip that assertion we do know the exact value of 'shared' already. The integer comparisons are the ones where we get the most benefit from being able to see the two sides of the comparison after a failure. Matt > > Regards, > Bala > > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > --- > > tests/intel/api_intel_allocator.c | 12 ++--- > > tests/intel/api_intel_bb.c | 18 +++---- > > tests/intel/drm_fdinfo.c | 8 +-- > > tests/intel/gem_blits.c | 16 +++--- > > tests/intel/gem_ccs.c | 4 +- > > tests/intel/gem_close_race.c | 2 +- > > tests/intel/gem_concurrent_all.c | 8 +-- > > tests/intel/gem_create.c | 2 +- > > tests/intel/gem_ctx_create.c | 8 +-- > > tests/intel/gem_ctx_exec.c | 4 +- > > tests/intel/gem_ctx_persistence.c | 12 +++-- > > tests/intel/gem_eio.c | 8 +-- > > tests/intel/gem_exec_alignment.c | 6 ++- > > tests/intel/gem_exec_big.c | 4 +- > > tests/intel/gem_exec_capture.c | 8 +-- > > tests/intel/gem_exec_fair.c | 32 +++++++----- > > tests/intel/gem_exec_fence.c | 2 +- > > tests/intel/gem_exec_gttfill.c | 4 +- > > tests/intel/gem_exec_nop.c | 2 +- > > tests/intel/gem_exec_reloc.c | 4 +- > > tests/intel/gem_gtt_speed.c | 2 +- > > tests/intel/gem_linear_blits.c | 6 +-- > > tests/intel/gem_pread.c | 5 +- > > tests/intel/gem_pwrite.c | 5 +- > > tests/intel/gem_pxp.c | 16 +++--- > > tests/intel/gem_reset_stats.c | 8 +-- > > tests/intel/gem_softpin.c | 8 ++- > > tests/intel/gem_tiled_blits.c | 6 +-- > > tests/intel/gem_tiled_fence_blits.c | 4 +- > > tests/intel/gem_userptr_blits.c | 4 +- > > tests/intel/gem_wait.c | 8 +-- > > tests/intel/gem_watchdog.c | 2 +- > > tests/intel/i915_hangman.c | 2 +- > > tests/intel/i915_module_load.c | 6 +-- > > tests/intel/i915_pm_freq_api.c | 50 +++++++++--------- > > tests/intel/i915_pm_rc6_residency.c | 4 +- > > tests/intel/i915_pm_rps.c | 11 ++-- > > tests/intel/i915_query.c | 12 ++--- > > tests/intel/kms_big_fb.c | 2 +- > > tests/intel/kms_busy.c | 2 +- > > tests/intel/kms_ccs.c | 2 +- > > tests/intel/kms_cdclk.c | 5 +- > > tests/intel/kms_dsc_helper.c | 4 +- > > tests/intel/kms_fbcon_fbt.c | 3 +- > > tests/intel/kms_pm_dc.c | 9 ++-- > > tests/intel/kms_pm_rpm.c | 2 +- > > tests/intel/kms_psr.c | 18 +++---- > > tests/intel/perf.c | 34 ++++++------ > > tests/intel/perf_pmu.c | 37 +++++++------ > > tests/intel/xe_ccs.c | 4 +- > > tests/intel/xe_debugfs.c | 2 +- > > tests/intel/xe_dma_buf_sync.c | 2 +- > > tests/intel/xe_evict.c | 4 +- > > tests/intel/xe_exec_balancer.c | 7 +-- > > tests/intel/xe_exec_basic.c | 4 +- > > tests/intel/xe_exec_compute_mode.c | 9 ++-- > > tests/intel/xe_exec_fault_mode.c | 5 +- > > tests/intel/xe_exec_reset.c | 8 +-- > > tests/intel/xe_exec_store.c | 2 +- > > tests/intel/xe_exec_threads.c | 11 ++-- > > tests/intel/xe_gt_freq.c | 80 ++++++++++++++--------------- > > tests/intel/xe_intel_bb.c | 16 +++--- > > tests/intel/xe_oa.c | 26 +++++----- > > tests/intel/xe_pat.c | 2 +- > > tests/intel/xe_peer2peer.c | 2 +- > > tests/intel/xe_pm.c | 16 +++--- > > tests/intel/xe_pm_residency.c | 4 +- > > tests/intel/xe_query.c | 12 ++--- > > tests/intel/xe_vm.c | 6 +-- > > 69 files changed, 335 insertions(+), 328 deletions(-) > > > > diff --git a/tests/intel/api_intel_allocator.c b/tests/intel/api_intel_allocator.c > > index 9218be3b9..15ba4828c 100644 > > --- a/tests/intel/api_intel_allocator.c > > +++ b/tests/intel/api_intel_allocator.c > > @@ -705,7 +705,7 @@ static void execbuf_with_allocator(int fd) > > gem_close(fd, object[i].handle); > > } > > > > - igt_assert(copied == magic); > > + igt_assert_eq_u32(copied, magic); > > igt_assert(intel_allocator_close(ahnd) == true); > > } > > > > @@ -776,13 +776,13 @@ static void gem_pool(int i915) > > bb[0] = single_exec_from_pool(i915, ahnd, 4096); > > gem_sync(i915, bb[0]); > > bb[1] = single_exec_from_pool(i915, ahnd, 4096); > > - igt_assert(bb[0] == bb[1]); > > + igt_assert_eq_u32(bb[0], bb[1]); > > > > bb[2] = single_exec_from_pool(i915, ahnd, 8192); > > gem_sync(i915, bb[2]); > > bb[3] = single_exec_from_pool(i915, ahnd, 8192); > > - igt_assert(bb[2] == bb[3]); > > - igt_assert(bb[0] != bb[2]); > > + igt_assert_eq_u32(bb[2], bb[3]); > > + igt_assert_neq_u32(bb[0], bb[2]); > > > > spin = igt_spin_new(i915, > > .ahnd = ahnd, > > @@ -792,8 +792,8 @@ static void gem_pool(int i915) > > bb[2] = single_exec_from_pool(i915, ahnd, 8192); > > bb[3] = single_exec_from_pool(i915, ahnd, 8192); > > igt_spin_free(i915, spin); > > - igt_assert(bb[0] != bb[1]); > > - igt_assert(bb[2] != bb[3]); > > + igt_assert_neq_u32(bb[0], bb[1]); > > + igt_assert_neq_u32(bb[2], bb[3]); > > > > put_ahnd(ahnd); > > > > diff --git a/tests/intel/api_intel_bb.c b/tests/intel/api_intel_bb.c > > index 6cb5d4f9e..db039dc3b 100644 > > --- a/tests/intel/api_intel_bb.c > > +++ b/tests/intel/api_intel_bb.c > > @@ -1024,11 +1024,11 @@ static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling) > > > > /* We'll fail on src <-> final compare so just warn */ > > if (tiling == I915_TILING_NONE) { > > - if (compare_bufs(&src, &dst, false) > 0) > > - igt_warn("none->none blit failed!"); > > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > > + "none->none blit failed!"); > > } else { > > - if (compare_bufs(&src, &dst, false) == 0) > > - igt_warn("none->tiled blit failed!"); > > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > > + "none->tiled blit failed!"); > > } > > > > fails = compare_bufs(&src, &final, true); > > @@ -1367,11 +1367,11 @@ static int render(struct buf_ops *bops, uint32_t tiling, bool do_reloc, > > > > /* We'll fail on src <-> final compare so just warn */ > > if (tiling == I915_TILING_NONE) { > > - if (compare_bufs(&src, &dst, false) > 0) > > - igt_warn("%s: none->none failed!\n", __func__); > > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > > + "%s: none->none failed!\n", __func__); > > } else { > > - if (compare_bufs(&src, &dst, false) == 0) > > - igt_warn("%s: none->tiled failed!\n", __func__); > > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > > + "%s: none->tiled failed!\n", __func__); > > } > > > > fails = compare_bufs(&src, &final, true); > > @@ -1535,7 +1535,7 @@ static void test_crc32(int i915, const intel_ctx_t *ctx, > > > > put_offset(ahnd, data); > > gem_close(i915, data); > > - igt_assert(cpu_crc == gpu_crc); > > + igt_assert_eq_u32(cpu_crc, gpu_crc); > > } > > > > put_ahnd(ahnd); > > diff --git a/tests/intel/drm_fdinfo.c b/tests/intel/drm_fdinfo.c > > index a790f9255..160dc3d0a 100644 > > --- a/tests/intel/drm_fdinfo.c > > +++ b/tests/intel/drm_fdinfo.c > > @@ -275,7 +275,7 @@ static void log_busy(unsigned int num_engines, uint64_t *val) > > int len; > > > > len = snprintf(p, rem, "%u=%" PRIu64 "\n", i, val[i]); > > - igt_assert(len > 0); > > + igt_assert_lt(0, len); > > rem -= len; > > p += len; > > } > > @@ -805,7 +805,7 @@ static size_t read_fdinfo(char *buf, const size_t sz, int at, const char *name) > > buf[count - 1] = 0; > > close(fd); > > > > - return count > 0 ? count : 0; > > + return max(count, 0); > > } > > > > /* > > @@ -855,7 +855,7 @@ test_memory(int i915, struct gem_memory_region *mr, unsigned int flags) > > > > gem_quiescent_gpu(i915); > > ret = __igt_parse_drm_fdinfo(dir, buf, &info, NULL, 0, NULL, 0); > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > igt_require(info.num_regions); > > memcpy(&prev_info, &info, sizeof(info)); > > memcpy(&base_info, &info, sizeof(info)); > > @@ -905,7 +905,7 @@ test_memory(int i915, struct gem_memory_region *mr, unsigned int flags) > > ret = __igt_parse_drm_fdinfo(dir, buf, &info, > > NULL, 0, > > region_map, ARRAY_SIZE(region_map)); > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > igt_assert(info.num_regions); > > > > read_fdinfo(fdinfo_buf, sizeof(fdinfo_buf), dir, buf); > > diff --git a/tests/intel/gem_blits.c b/tests/intel/gem_blits.c > > index 5ca81fbfe..b2af48ef1 100644 > > --- a/tests/intel/gem_blits.c > > +++ b/tests/intel/gem_blits.c > > @@ -267,7 +267,7 @@ static void buffer_set_tiling(const struct device *device, > > batch[i++] = obj[1].offset >> 32; > > > > if ((tiling | buffer->tiling) >= T_YMAJOR) { > > - igt_assert(device->gen >= 6); > > + igt_assert_lte(6, device->gen); > > batch[i++] = MI_FLUSH_DW_CMD | 2; > > batch[i++] = 0; > > batch[i++] = 0; > > @@ -415,7 +415,7 @@ static bool blit_to_linear(const struct device *device, > > batch[i++] = obj[1].offset >> 32; > > > > if (buffer->tiling >= T_YMAJOR) { > > - igt_assert(device->gen >= 6); > > + igt_assert_lte(6, device->gen); > > batch[i++] = MI_FLUSH_DW_CMD | 2; > > batch[i++] = 0; > > batch[i++] = 0; > > @@ -542,11 +542,9 @@ static bool buffer_check(const struct device *device, > > continue; > > > > for (int x = 0; x < buffer->width; x++) { > > - if (row[x] != model[x] && num_errors++ < 5) { > > - igt_warn("buffer handle=%d mismatch at (%d, %d): expected %08x, found %08x\n", > > - buffer->handle, > > - x, y, model[x], row[x]); > > - } > > + igt_warn_on_f(row[x] != model[x] && num_errors++ < 5, > > + "buffer handle=%d mismatch at (%d, %d): expected %08x, found %08x\n", > > + buffer->handle, x, y, model[x], row[x]); > > } > > } > > > > @@ -664,7 +662,7 @@ blit(const struct device *device, > > height = dst->height - dst_y; > > > > if (dst->caching) { > > - igt_assert(device->gen >= 3); > > + igt_assert_lte(3, device->gen); > > igt_assert(device->llc || !src->caching); > > } > > > > @@ -764,7 +762,7 @@ blit(const struct device *device, > > batch[i++] = obj[1].offset >> 32; > > > > if ((src->tiling | dst->tiling) >= T_YMAJOR) { > > - igt_assert(device->gen >= 6); > > + igt_assert_lte(6, device->gen); > > batch[i++] = MI_FLUSH_DW_CMD | 2; > > batch[i++] = 0; > > batch[i++] = 0; > > diff --git a/tests/intel/gem_ccs.c b/tests/intel/gem_ccs.c > > index 6ced67d7a..07aa6d322 100644 > > --- a/tests/intel/gem_ccs.c > > +++ b/tests/intel/gem_ccs.c > > @@ -175,7 +175,7 @@ static void surf_copy(int i915, > > gem_sync(i915, blt.dst.handle); > > WRITE_PNG(i915, run_id, "corrupted", &blt.dst, dst->x2, dst->y2, bpp); > > result = memcmp(src->ptr, dst->ptr, src->size); > > - igt_assert(result != 0); > > + igt_assert_neq(result, 0); > > > > /* retrieve back ccs */ > > memcpy(ccsmap, ccscopy, ccssize); > > @@ -601,7 +601,7 @@ static int opt_handler(int opt, int opt_index, void *data) > > case 'f': > > param.compression_format = atoi(optarg); > > igt_debug("Compression format: %d\n", param.compression_format); > > - igt_assert((param.compression_format & ~0x1f) == 0); > > + igt_assert_eq((param.compression_format & ~0x1f), 0); > > break; > > case 'p': > > param.write_png = true; > > diff --git a/tests/intel/gem_close_race.c b/tests/intel/gem_close_race.c > > index 9edcf13eb..c68e2fa73 100644 > > --- a/tests/intel/gem_close_race.c > > +++ b/tests/intel/gem_close_race.c > > @@ -307,7 +307,7 @@ static void multigpu_threads(int timeout, unsigned int flags, int gpu_count) > > struct drm_gem_open name; > > int fd = __drm_open_driver_another(gpu, DRIVER_INTEL); > > > > - igt_assert(fd > 0); > > + igt_assert_lt(0, fd); > > > > igt_fork(child, size) > > thread(fd, name, timeout, flags); > > diff --git a/tests/intel/gem_concurrent_all.c b/tests/intel/gem_concurrent_all.c > > index dbb7622d3..acc6a230d 100644 > > --- a/tests/intel/gem_concurrent_all.c > > +++ b/tests/intel/gem_concurrent_all.c > > @@ -306,7 +306,7 @@ userptr_create_bo(const struct buffers *b) > > igt_assert(ptr != (void *)-1); > > userptr.user_ptr = to_user_pointer(ptr); > > > > - do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr)); > > + do_ioctl(fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr); > > buf = intel_buf_create_using_handle_and_size(b->bops, userptr.handle, > > b->width, b->height, 32, 0, > > I915_TILING_NONE, 0, > > @@ -497,7 +497,7 @@ vgem_create_bo(const struct buffers *b) > > struct dmabuf *dmabuf; > > uint32_t handle; > > > > - igt_assert(vgem_drv != -1); > > + igt_assert_neq(vgem_drv, -1); > > > > vgem.width = b->width; > > vgem.height = b->height; > > @@ -915,7 +915,7 @@ static void buffers_create(struct buffers *b) > > igt_assert(b->bops); > > > > buffers_destroy(b); > > - igt_assert(b->count == 0); > > + igt_assert_eq(b->count, 0); > > b->count = count; > > > > ahnd = alloc_open(); > > @@ -941,7 +941,7 @@ static void __buffers_create(struct buffers *b) > > { > > b->bops = buf_ops_create(fd); > > igt_assert(b->bops); > > - igt_assert(b->num_buffers > 0); > > + igt_assert_lt(0, b->num_buffers); > > igt_assert(b->mode); > > igt_assert(b->mode->create_bo); > > > > diff --git a/tests/intel/gem_create.c b/tests/intel/gem_create.c > > index 26cd6e32e..ca39a8b64 100644 > > --- a/tests/intel/gem_create.c > > +++ b/tests/intel/gem_create.c > > @@ -637,7 +637,7 @@ static void create_ext_set_pat(int fd) > > * This means that we are on a Meteor Lake and the PAT > > * index is already supported by the running i915 > > */ > > - igt_assert(ret == 0); > > + igt_assert_eq(ret, 0); > > > > /* > > * {set|get}_caching ioctl should fail for objects created with set_pat > > diff --git a/tests/intel/gem_ctx_create.c b/tests/intel/gem_ctx_create.c > > index 6afb10a7b..0332ecbb9 100644 > > --- a/tests/intel/gem_ctx_create.c > > +++ b/tests/intel/gem_ctx_create.c > > @@ -297,18 +297,14 @@ static void xchg_u32(void *array, unsigned i, unsigned j) > > { > > uint32_t *a = array, tmp; > > > > - tmp = a[i]; > > - a[i] = a[j]; > > - a[j] = tmp; > > + igt_swap(a[i], a[j]); > > } > > > > static void xchg_ptr(void *array, unsigned i, unsigned j) > > { > > void **a = array, *tmp; > > > > - tmp = a[i]; > > - a[i] = a[j]; > > - a[j] = tmp; > > + igt_swap(a[i], a[j]); > > } > > > > static unsigned __context_size(int fd) > > diff --git a/tests/intel/gem_ctx_exec.c b/tests/intel/gem_ctx_exec.c > > index f3e252d10..a45a7e378 100644 > > --- a/tests/intel/gem_ctx_exec.c > > +++ b/tests/intel/gem_ctx_exec.c > > @@ -346,7 +346,7 @@ static void nohangcheck_hostile(int i915) > > IGT_SPIN_FENCE_OUT)); > > > > new = fill_ring(i915, &spin->execbuf); > > - igt_assert(new != -1); > > + igt_assert_neq(new, -1); > > spin->out_fence = -1; > > > > if (fence < 0) { > > @@ -362,7 +362,7 @@ static void nohangcheck_hostile(int i915) > > } > > } > > intel_ctx_destroy(i915, ctx); > > - igt_assert(fence != -1); > > + igt_assert_neq(fence, -1); > > > > err = 0; > > if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */ > > diff --git a/tests/intel/gem_ctx_persistence.c b/tests/intel/gem_ctx_persistence.c > > index 90c1e0112..8d4a874d4 100644 > > --- a/tests/intel/gem_ctx_persistence.c > > +++ b/tests/intel/gem_ctx_persistence.c > > @@ -1093,10 +1093,12 @@ static void test_processes(int i915) > > > > /* Wait until we are told to die */ > > pid = getpid(); > > - write(p[i].sv[0], &pid, sizeof(pid)); > > + igt_assert_eq(write(p[i].sv[0], &pid, sizeof(pid)), > > + sizeof(pid)); > > > > pid = 0; > > - read(p[i].sv[0], &pid, sizeof(pid)); > > + igt_assert_eq(read(p[i].sv[0], &pid, sizeof(pid)), > > + sizeof(pid)); > > igt_assert(pid == getpid()); > > } > > } > > @@ -1109,8 +1111,10 @@ static void test_processes(int i915) > > igt_assert_eq(sync_fence_wait(fence, 0), -ETIME); > > > > /* Kill *this* process */ > > - read(p[i].sv[1], &pid, sizeof(pid)); > > - write(p[i].sv[1], &pid, sizeof(pid)); > > + igt_assert_eq(read(p[i].sv[1], &pid, sizeof(pid)), > > + sizeof(pid)); > > + igt_assert_eq(write(p[i].sv[1], &pid, sizeof(pid)), > > + sizeof(pid)); > > > > /* > > * A little bit of slack required for the signal to terminate > > diff --git a/tests/intel/gem_eio.c b/tests/intel/gem_eio.c > > index dc6178d63..b65b914fa 100644 > > --- a/tests/intel/gem_eio.c > > +++ b/tests/intel/gem_eio.c > > @@ -627,7 +627,7 @@ static void test_inflight(int fd, unsigned int wait) > > for (unsigned int n = 0; n < max; n++) { > > gem_execbuf_wr(fd, &execbuf); > > fence[n] = execbuf.rsvd2 >> 32; > > - igt_assert(fence[n] != -1); > > + igt_assert_neq(fence[n], -1); > > } > > > > igt_debugfs_dump(fd, "i915_engine_info"); > > @@ -687,7 +687,7 @@ static void test_inflight_suspend(int fd) > > for (unsigned int n = 0; n < max; n++) { > > gem_execbuf_wr(fd, &execbuf); > > fence[n] = execbuf.rsvd2 >> 32; > > - igt_assert(fence[n] != -1); > > + igt_assert_neq(fence[n], -1); > > } > > > > igt_set_autoresume_delay(30); > > @@ -774,7 +774,7 @@ static void test_inflight_contexts(int fd, unsigned int wait) > > if (__gem_execbuf_wr(fd, &execbuf)) > > break; /* small shared ring */ > > fence[n] = execbuf.rsvd2 >> 32; > > - igt_assert(fence[n] != -1); > > + igt_assert_neq(fence[n], -1); > > count++; > > } > > > > @@ -885,7 +885,7 @@ static void test_inflight_internal(int fd, unsigned int wait) > > gem_execbuf_wr(fd, &execbuf); > > > > fences[nfence] = execbuf.rsvd2 >> 32; > > - igt_assert(fences[nfence] != -1); > > + igt_assert_neq(fences[nfence], -1); > > nfence++; > > } > > > > diff --git a/tests/intel/gem_exec_alignment.c b/tests/intel/gem_exec_alignment.c > > index 7b51b7af0..6a9905d95 100644 > > --- a/tests/intel/gem_exec_alignment.c > > +++ b/tests/intel/gem_exec_alignment.c > > @@ -302,7 +302,8 @@ static void prio_inversion(int i915, unsigned int flags) > > naughty_child(i915, link[1], obj.handle, flags); > > > > igt_debug("Waiting for naughty client\n"); > > - read(link[0], &elapsed, sizeof(elapsed)); > > + igt_assert_eq(read(link[0], &elapsed, sizeof(elapsed)), > > + sizeof(elapsed)); > > igt_debug("Ready...\n"); > > usleep(250 * 1000); /* let the naughty execbuf begin */ > > igt_debug("Go!\n"); > > @@ -331,7 +332,8 @@ static void prio_inversion(int i915, unsigned int flags) > > igt_waitchildren(); > > gem_close(i915, obj.handle); > > > > - read(link[0], &naughty, sizeof(naughty)); > > + igt_assert_eq(read(link[0], &naughty, sizeof(naughty)), > > + sizeof(naughty)); > > igt_info("Naughty client took %'"PRIu64"ns\n", naughty); > > > > igt_assert(elapsed < naughty / 2); > > diff --git a/tests/intel/gem_exec_big.c b/tests/intel/gem_exec_big.c > > index 7bd91c2a0..86849f322 100644 > > --- a/tests/intel/gem_exec_big.c > > +++ b/tests/intel/gem_exec_big.c > > @@ -143,9 +143,7 @@ static void xchg_reloc(void *array, unsigned i, unsigned j) > > struct drm_i915_gem_relocation_entry *b = &reloc[j]; > > struct drm_i915_gem_relocation_entry tmp; > > > > - tmp = *a; > > - *a = *b; > > - *b = tmp; > > + igt_swap(*a, *b); > > } > > > > static void execN(int fd, uint32_t handle, uint64_t batch_size, unsigned flags, char *ptr) > > diff --git a/tests/intel/gem_exec_capture.c b/tests/intel/gem_exec_capture.c > > index 720ff796d..2340ad495 100644 > > --- a/tests/intel/gem_exec_capture.c > > +++ b/tests/intel/gem_exec_capture.c > > @@ -406,7 +406,7 @@ static void __capture1(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx, > > gem_execbuf_wr(fd, &execbuf); > > > > fence_out = execbuf.rsvd2 >> 32; > > - igt_assert(fence_out >= 0); > > + igt_assert_lte(0, fence_out); > > > > /* Wait for the request to start */ > > while (READ_ONCE(*seqno) != 0xc0ffee) > > @@ -792,11 +792,11 @@ static void prioinv(int fd, int dir, const intel_ctx_t *ctx, > > &fence_out, REGION_SMEM, true)); > > put_ahnd(ahnd); > > > > - write(link[1], &fd, sizeof(fd)); /* wake the parent up */ > > + igt_assert_eq(write(link[1], &fd, sizeof(fd)), sizeof(fd)); /* wake the parent up */ > > wait_to_die(fence_out); > > - write(link[1], &fd, sizeof(fd)); /* wake the parent up */ > > + igt_assert_eq(write(link[1], &fd, sizeof(fd)), sizeof(fd)); /* wake the parent up */ > > } > > - read(link[0], &dummy, sizeof(dummy)); > > + igt_assert_eq(read(link[0], &dummy, sizeof(dummy)), sizeof(dummy)); > > igt_require_f(poll(&(struct pollfd){link[0], POLLIN}, 1, 500) == 0, > > "Capture completed too quickly! Will not block\n"); > > > > diff --git a/tests/intel/gem_exec_fair.c b/tests/intel/gem_exec_fair.c > > index 2f7ef3800..19df66921 100644 > > --- a/tests/intel/gem_exec_fair.c > > +++ b/tests/intel/gem_exec_fair.c > > @@ -579,10 +579,12 @@ static void fair_child(int i915, const intel_ctx_t *ctx, > > > > /* Synchronize with other children/parent upon construction */ > > if (sv != -1) > > - write(sv, &p_fence, sizeof(p_fence)); > > + igt_assert_eq(write(sv, &p_fence, sizeof(p_fence)), > > + sizeof(p_fence)); > > if (rv != -1) > > - read(rv, &p_fence, sizeof(p_fence)); > > - igt_assert(p_fence == -1); > > + igt_assert_eq(read(rv, &p_fence, sizeof(p_fence)), > > + sizeof(p_fence)); > > + igt_assert_eq(p_fence, -1); > > > > aux_flags = 0; > > if (intel_gen(intel_get_drm_devid(i915)) < 8) > > @@ -850,9 +852,11 @@ static void fairness(int i915, const intel_ctx_cfg_t *cfg, > > { > > int sync; > > for (int child = 0; child < nchild; child++) > > - read(lnk.child[0], &sync, sizeof(sync)); > > + igt_assert_eq(read(lnk.child[0], &sync, sizeof(sync)), > > + sizeof(sync)); > > for (int child = 0; child < nchild; child++) > > - write(lnk.parent[1], &sync, sizeof(sync)); > > + igt_assert_eq(write(lnk.parent[1], &sync, sizeof(sync)), > > + sizeof(sync)); > > } > > > > while (nfences--) > > @@ -1028,9 +1032,9 @@ static void deadline_child(int i915, > > if (!(flags & DL_PRIO)) > > execbuf.flags |= I915_EXEC_FENCE_IN; > > > > - write(sv, &prev, sizeof(int)); > > - read(rv, &prev, sizeof(int)); > > - igt_assert(prev == -1); > > + igt_assert_eq(write(sv, &prev, sizeof(int)), sizeof(int)); > > + igt_assert_eq(read(rv, &prev, sizeof(int)), sizeof(int)); > > + igt_assert_eq(prev, -1); > > > > prev = execbuf.rsvd2; > > next = execbuf.rsvd2 >> 32; > > @@ -1044,7 +1048,8 @@ static void deadline_child(int i915, > > gem_execbuf_wr(i915, &execbuf); > > close(execbuf.rsvd2); > > > > - write(sv, &fence.handle, sizeof(uint32_t)); > > + igt_assert_eq(write(sv, &fence.handle, sizeof(uint32_t)), > > + sizeof(uint32_t)); > > > > prev = next; > > next = execbuf.rsvd2 >> 32; > > @@ -1187,10 +1192,12 @@ static void deadline(int i915, const intel_ctx_cfg_t *cfg, > > } > > > > for (int i = 0; i < num_children; i++) > > - read(link[i].child[0], &over, sizeof(int)); > > + igt_assert_eq(read(link[i].child[0], &over, sizeof(int)), > > + sizeof(int)); > > igt_info("Testing %d children, with %'dns\n", num_children, child_ns); > > for (int i = 0; i < num_children; i++) > > - write(link[i].parent[1], &over, sizeof(int)); > > + igt_assert_eq(write(link[i].parent[1], &over, sizeof(int)), > > + sizeof(int)); > > > > over = 0; > > missed = 0; > > @@ -1207,7 +1214,8 @@ static void deadline(int i915, const intel_ctx_cfg_t *cfg, > > > > sw_sync_timeline_inc(timeline, 1); > > for (int i = 0; i < num_children; i++) { > > - read(link[i].child[0], &fences[i].handle, sizeof(uint32_t)); > > + igt_assert_eq(read(link[i].child[0], &fences[i].handle, sizeof(uint32_t)), > > + sizeof(uint32_t)); > > fences[i].flags = I915_EXEC_FENCE_WAIT; > > } > > > > diff --git a/tests/intel/gem_exec_fence.c b/tests/intel/gem_exec_fence.c > > index a313c31f2..7f39c73d7 100644 > > --- a/tests/intel/gem_exec_fence.c > > +++ b/tests/intel/gem_exec_fence.c > > @@ -366,7 +366,7 @@ static void test_fence_busy_all(int fd, const intel_ctx_t *ctx, unsigned flags) > > execbuf.rsvd2 = -1; > > gem_execbuf_wr(fd, &execbuf); > > fence = execbuf.rsvd2 >> 32; > > - igt_assert(fence != -1); > > + igt_assert_neq(fence, -1); > > > > if (all < 0) { > > all = fence; > > diff --git a/tests/intel/gem_exec_gttfill.c b/tests/intel/gem_exec_gttfill.c > > index 096681740..ff600e0ca 100644 > > --- a/tests/intel/gem_exec_gttfill.c > > +++ b/tests/intel/gem_exec_gttfill.c > > @@ -66,9 +66,7 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) > > struct batch *batches = array; > > struct batch tmp; > > > > - tmp = batches[i]; > > - batches[i] = batches[j]; > > - batches[j] = tmp; > > + igt_swap(batches[i], batches[j]); > > } > > > > static void submit(int fd, uint64_t ahnd, unsigned int gen, > > diff --git a/tests/intel/gem_exec_nop.c b/tests/intel/gem_exec_nop.c > > index fb37cb511..1b20cc870 100644 > > --- a/tests/intel/gem_exec_nop.c > > +++ b/tests/intel/gem_exec_nop.c > > @@ -415,7 +415,7 @@ stable_nop_on_ring(int fd, uint32_t handle, const intel_ctx_t *ctx, > > igt_stats_t s; > > double n; > > > > - igt_assert(reps >= 5); > > + igt_assert_lte(5, reps); > > > > igt_stats_init_with_size(&s, reps); > > s.is_float = true; > > diff --git a/tests/intel/gem_exec_reloc.c b/tests/intel/gem_exec_reloc.c > > index d8013ccfc..44c09c3e2 100644 > > --- a/tests/intel/gem_exec_reloc.c > > +++ b/tests/intel/gem_exec_reloc.c > > @@ -1343,7 +1343,7 @@ static void concurrent_child(int i915, const intel_ctx_t *ctx, > > x += idx * CONCURRENT; > > > > do { > > - read(in, batch, sizeof(*batch)); > > + igt_assert_eq(read(in, batch, sizeof(*batch)), sizeof(*batch)); > > if (!*batch) > > break; > > > > @@ -1359,7 +1359,7 @@ static void concurrent_child(int i915, const intel_ctx_t *ctx, > > } > > } > > > > - write(out, &err, sizeof(err)); > > + igt_assert_eq(write(out, &err, sizeof(err)), sizeof(err)); > > count++; > > } while (err == 0); > > > > diff --git a/tests/intel/gem_gtt_speed.c b/tests/intel/gem_gtt_speed.c > > index 996e54af0..0f4e174d2 100644 > > --- a/tests/intel/gem_gtt_speed.c > > +++ b/tests/intel/gem_gtt_speed.c > > @@ -70,7 +70,7 @@ static void streaming_load(void *src, int len) > > { > > __m128i tmp, *s = src; > > > > - igt_assert((len & 15) == 0); > > + igt_assert_eq((len & 15), 0); > > igt_assert((((uintptr_t)src) & 15) == 0); > > > > while (len >= 16) { > > diff --git a/tests/intel/gem_linear_blits.c b/tests/intel/gem_linear_blits.c > > index 2eeec5b6a..b6c0b13ac 100644 > > --- a/tests/intel/gem_linear_blits.c > > +++ b/tests/intel/gem_linear_blits.c > > @@ -212,9 +212,9 @@ check_bo(int fd, uint32_t handle, uint32_t val) > > > > num_errors = 0; > > for (i = 0; i < WIDTH*HEIGHT; i++) { > > - if (linear[i] != val && num_errors++ < 32) > > - igt_warn("[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > > - i * 4, val, linear[i], val ^ linear[i]); > > + igt_warn_on_f(linear[i] != val && num_errors++ < 32, > > + "[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > > + i * 4, val, linear[i], val ^ linear[i]); > > val++; > > } > > igt_assert_eq(num_errors, 0); > > diff --git a/tests/intel/gem_pread.c b/tests/intel/gem_pread.c > > index e5e662361..70a38e75c 100644 > > --- a/tests/intel/gem_pread.c > > +++ b/tests/intel/gem_pread.c > > @@ -151,7 +151,7 @@ static void write_value(const char *path, int value) > > > > fd = open(path, O_WRONLY); > > if (fd != -1) { > > - write(fd, buf, len); > > + igt_assert_eq(write(fd, buf, len), len); > > close(fd); > > } > > } > > @@ -223,8 +223,7 @@ static void test_exhaustion(int i915) > > count++; > > } > > igt_assert(count); > > - if (t.err) > > - igt_warn("err:%d after %lu threads\n", t.err, count); > > + igt_warn_on_f(t.err, "err:%d after %lu threads\n", t.err, count); > > > > /* Service the fault; releasing the stuck ioctls */ > > memset(©, 0, sizeof(copy)); > > diff --git a/tests/intel/gem_pwrite.c b/tests/intel/gem_pwrite.c > > index 025684a33..05a47b7b1 100644 > > --- a/tests/intel/gem_pwrite.c > > +++ b/tests/intel/gem_pwrite.c > > @@ -425,7 +425,7 @@ static void write_value(const char *path, int value) > > > > fd = open(path, O_WRONLY); > > if (fd != -1) { > > - write(fd, buf, len); > > + igt_assert_eq(write(fd, buf, len), len); > > close(fd); > > } > > } > > @@ -497,8 +497,7 @@ static void test_exhaustion(int i915) > > count++; > > } > > igt_assert(count); > > - if (t.err) > > - igt_warn("err:%d after %lu threads\n", t.err, count); > > + igt_warn_on_f(t.err, "err:%d after %lu threads\n", t.err, count); > > > > /* Service the fault; releasing the stuck ioctls */ > > memset(©, 0, sizeof(copy)); > > diff --git a/tests/intel/gem_pxp.c b/tests/intel/gem_pxp.c > > index 6be19318a..e2c12df17 100644 > > --- a/tests/intel/gem_pxp.c > > +++ b/tests/intel/gem_pxp.c > > @@ -811,7 +811,7 @@ static void test_pxp_dmabuffshare_refcnt(int i915) > > for (n = 0; n < (TSTSURF_SIZE/4); ++n) > > if (encrypted[0][n] == encrypted[1][n]) > > ++num_matches; > > - igt_assert(num_matches == (TSTSURF_SIZE/4)); > > + igt_assert_eq(num_matches, (TSTSURF_SIZE / 4)); > > } > > > > > > @@ -988,7 +988,7 @@ static void test_pxp_stale_ctx_execution(int i915) > > */ > > prepare_exec_assets(i915, &data, true, false); > > ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); > > - igt_assert(ret == 0); > > + igt_assert_eq(ret, 0); > > > > trigger_pxp_debugfs_forced_teardown(i915); > > > > @@ -1008,7 +1008,7 @@ static void test_pxp_stale_buf_execution(int i915) > > /* Use pxp buffers with pxp context for testing for invalidation of protected buffers. */ > > prepare_exec_assets(i915, &data, true, true); > > ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); > > - igt_assert(ret == 0); > > + igt_assert_eq(ret, 0); > > > > trigger_pxp_debugfs_forced_teardown(i915); > > > > @@ -1055,7 +1055,7 @@ static void test_pxp_stale_buf_optout_execution(int i915) > > * the intent of the subtest) to ensure ARB session is alive. > > */ > > ret = create_ctx_with_params(i915, true, true, true, false, &tmpctx); > > - igt_assert(ret == 0); > > + igt_assert_eq(ret, 0); > > > > /* > > * Use a normal context for testing opt-out behavior > > @@ -1063,7 +1063,7 @@ static void test_pxp_stale_buf_optout_execution(int i915) > > */ > > prepare_exec_assets(i915, &data, false, true); > > ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); > > - igt_assert(ret == 0); > > + igt_assert_eq(ret, 0); > > > > trigger_pxp_debugfs_forced_teardown(i915); > > > > @@ -1088,7 +1088,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat > > */ > > prepare_exec_assets(i915, &data[0], true, false); > > ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf); > > - igt_assert(ret == 0); > > + igt_assert_eq(ret, 0); > > > > /* > > * For asset data[1]: Use pxp buffers with pxp context for testing for invalidation > > @@ -1096,7 +1096,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat > > */ > > prepare_exec_assets(i915, &data[1], true, true); > > ret = gem_execbuf_flush_store_dw(i915, data[1].ibb, data[1].ctx, data[1].fencebuf); > > - igt_assert(ret == 0); > > + igt_assert_eq(ret, 0); > > > > /* > > * For asset data[2]: Use a normal context for testing opt-out behavior > > @@ -1104,7 +1104,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat > > */ > > prepare_exec_assets(i915, &data[2], false, true); > > ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf); > > - igt_assert(ret == 0); > > + igt_assert_eq(ret, 0); > > > > /* Do an S3 suspend resume cycle which also causes the pxp teardown event */ > > trigger_powermgt_suspend_cycle(i915, pm); > > diff --git a/tests/intel/gem_reset_stats.c b/tests/intel/gem_reset_stats.c > > index 91bec96c0..8c74ce28c 100644 > > --- a/tests/intel/gem_reset_stats.c > > +++ b/tests/intel/gem_reset_stats.c > > @@ -315,7 +315,7 @@ static int noop(int fd, uint32_t ctx, const struct intel_execution_ring *e) > > > > memset(&exec, 0, sizeof(exec)); > > exec.handle = gem_create(fd, 4096); > > - igt_assert((int)exec.handle > 0); > > + igt_assert_lt(0, (int)exec.handle); > > gem_write(fd, exec.handle, 0, &bbe, sizeof(bbe)); > > > > memset(&eb, 0, sizeof(eb)); > > @@ -457,7 +457,7 @@ static void test_rs(const struct intel_execution_ring *e, > > if (i == hang_index) > > inject_hang(fd[i], 0, e, ASYNC); > > else > > - igt_assert(noop(fd[i], 0, e) > 0); > > + igt_assert_lt(0, noop(fd[i], 0, e)); > > } > > sync_gpu(); > > > > @@ -524,7 +524,7 @@ static void test_rs_ctx(const struct intel_execution_ring *e, > > if (i == hang_index && j == hang_context) > > inject_hang(fd[i], ctx[i][j], e, ASYNC); > > else > > - igt_assert(noop(fd[i], ctx[i][j], e) > 0); > > + igt_assert_lt(0, noop(fd[i], ctx[i][j], e)); > > } > > } > > sync_gpu(); > > @@ -876,7 +876,7 @@ static void _check_param_ctx(const int fd, const int ctx, const cap_t cap) > > igt_assert_eq(_test_params(fd, ctx, 0, 0), 0); > > > > if (cap != root) { > > - igt_assert(get_reset_count(fd, ctx) == 0); > > + igt_assert_eq(get_reset_count(fd, ctx), 0); > > } > > } > > > > diff --git a/tests/intel/gem_softpin.c b/tests/intel/gem_softpin.c > > index b7c1b34e1..c542bf741 100644 > > --- a/tests/intel/gem_softpin.c > > +++ b/tests/intel/gem_softpin.c > > @@ -793,7 +793,7 @@ static void __reserve(uint64_t ahnd, int i915, bool pinned, > > unsigned int flags; > > int i; > > > > - igt_assert(num_obj > 1); > > + igt_assert_lt(1, num_obj); > > > > flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > if (pinned) > > @@ -843,7 +843,7 @@ static void __exec_using_allocator(uint64_t ahnd, int i915, int num_obj, > > uint64_t sz = 4096; > > int i; > > > > - igt_assert(num_obj > 10); > > + igt_assert_lt(10, num_obj); > > > > flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > if (pinned) > > @@ -969,9 +969,7 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) > > struct batch *batches = array; > > struct batch tmp; > > > > - tmp = batches[i]; > > - batches[i] = batches[j]; > > - batches[j] = tmp; > > + igt_swap(batches[i], batches[j]); > > } > > > > static void submit(int fd, unsigned int gen, > > diff --git a/tests/intel/gem_tiled_blits.c b/tests/intel/gem_tiled_blits.c > > index 6fcc8616e..d8e80ca60 100644 > > --- a/tests/intel/gem_tiled_blits.c > > +++ b/tests/intel/gem_tiled_blits.c > > @@ -129,9 +129,9 @@ check_bo(struct intel_buf *buf, uint32_t val, struct intel_bb *ibb) > > linear = intel_buf_cpu_map(linear_buf, 0); > > num_errors = 0; > > for (i = 0; i < width * height; i++) { > > - if (linear[i] != val && num_errors++ < 32) > > - igt_warn("[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > > - i * 4, val, linear[i], val ^ linear[i]); > > + igt_warn_on_f(linear[i] != val && num_errors++ < 32, > > + "[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > > + i * 4, val, linear[i], val ^ linear[i]); > > val++; > > } > > igt_assert_eq(num_errors, 0); > > diff --git a/tests/intel/gem_tiled_fence_blits.c b/tests/intel/gem_tiled_fence_blits.c > > index 5e5bc6939..f5a3d9311 100644 > > --- a/tests/intel/gem_tiled_fence_blits.c > > +++ b/tests/intel/gem_tiled_fence_blits.c > > @@ -158,9 +158,7 @@ static void xchg_u32(void *array, unsigned i, unsigned j) > > { > > uint32_t tmp, *base = array; > > > > - tmp = base[i]; > > - base[i] = base[j]; > > - base[j] = tmp; > > + igt_swap(base[i], base[j]); > > } > > > > static void run_test(int fd, int count, uint64_t end) > > diff --git a/tests/intel/gem_userptr_blits.c b/tests/intel/gem_userptr_blits.c > > index 807c209e8..67283c182 100644 > > --- a/tests/intel/gem_userptr_blits.c > > +++ b/tests/intel/gem_userptr_blits.c > > @@ -814,7 +814,7 @@ static void test_nohangcheck_hostile(int i915) > > IGT_SPIN_FENCE_OUT)); > > > > new = fill_ring(i915, &spin->execbuf); > > - igt_assert(new != -1); > > + igt_assert_neq(new, -1); > > spin->out_fence = -1; > > > > if (fence < 0) { > > @@ -831,7 +831,7 @@ static void test_nohangcheck_hostile(int i915) > > } > > intel_ctx_destroy(i915, ctx); > > put_ahnd(ahnd); > > - igt_assert(fence != -1); > > + igt_assert_neq(fence, -1); > > > > if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */ > > igt_debugfs_dump(i915, "i915_engine_info"); > > diff --git a/tests/intel/gem_wait.c b/tests/intel/gem_wait.c > > index 7a353a11e..9265d1d7a 100644 > > --- a/tests/intel/gem_wait.c > > +++ b/tests/intel/gem_wait.c > > @@ -167,9 +167,11 @@ static void basic(int fd, const intel_ctx_t *ctx, unsigned engine, > > igt_seconds_elapsed(&tv) < timeout) > > ; > > > > - if ((flags & HANG) == 0 && !timespec_isset(&spin->last_signal)) > > - igt_warn("spinner not terminated, expired? %d!\n", > > - poll(&(struct pollfd){ spin->timerfd, POLLIN }, 1, 0)); > > + igt_warn_on_f((flags & HANG) == 0 && !timespec_isset(&spin->last_signal), > > + "spinner not terminated, expired? %d!\n", poll(&(struct pollfd){ > > + spin->timerfd, > > + POLLIN, > > + }, 1, 0)); > > > > igt_assert_eq(__gem_wait(fd, &wait), 0); > > } else { > > diff --git a/tests/intel/gem_watchdog.c b/tests/intel/gem_watchdog.c > > index 3d2fd68a8..1edde8b3c 100644 > > --- a/tests/intel/gem_watchdog.c > > +++ b/tests/intel/gem_watchdog.c > > @@ -500,7 +500,7 @@ far_delay(int i915, unsigned long delay, unsigned int target, > > batch[1] = batch[0]; > > batch[1].flags &= ~EXEC_OBJECT_WRITE; > > batch[0].handle = handle; > > - assert(batch[0].flags & EXEC_OBJECT_WRITE); > > + igt_assert(batch[0].flags & EXEC_OBJECT_WRITE); > > gem_execbuf_wr(i915, &execbuf); > > > > gem_close(i915, obj.handle); > > diff --git a/tests/intel/i915_hangman.c b/tests/intel/i915_hangman.c > > index f100118b6..a556eec53 100644 > > --- a/tests/intel/i915_hangman.c > > +++ b/tests/intel/i915_hangman.c > > @@ -470,7 +470,7 @@ static void test_hang_detector(const intel_ctx_t *ctx, > > igt_stop_hang_detector(); > > > > /* Did it work? */ > > - igt_assert(hang_count == 1); > > + igt_assert_eq(hang_count, 1); > > > > check_alive(); > > } > > diff --git a/tests/intel/i915_module_load.c b/tests/intel/i915_module_load.c > > index e3e4470df..cd1ee6d10 100644 > > --- a/tests/intel/i915_module_load.c > > +++ b/tests/intel/i915_module_load.c > > @@ -230,7 +230,7 @@ inject_fault(const char *module_name, const char *opt, int fault) > > char buf[1024]; > > int dir; > > > > - igt_assert(fault > 0); > > + igt_assert_lt(0, fault); > > snprintf(buf, sizeof(buf), "%s=%d", opt, fault); > > > > if (igt_kmod_load(module_name, buf)) { > > @@ -343,8 +343,8 @@ static uint32_t driver_load_with_lmem_bar_size(uint32_t lmem_bar_size, bool che > > char *tmp; > > > > tmp = __igt_params_get(i915, "lmem_bar_size"); > > - if (!tmp) > > - igt_skip("lmem_bar_size modparam not supported on this kernel. Skipping the test.\n"); > > + igt_skip_on_f(!tmp, > > + "lmem_bar_size modparam not supported on this kernel. Skipping the test.\n"); > > free(tmp); > > } > > > > diff --git a/tests/intel/i915_pm_freq_api.c b/tests/intel/i915_pm_freq_api.c > > index 2a3da6f4a..f2106cd3e 100644 > > --- a/tests/intel/i915_pm_freq_api.c > > +++ b/tests/intel/i915_pm_freq_api.c > > @@ -61,34 +61,34 @@ static void test_freq_basic_api(int dirfd, int gt) > > igt_debug("GT: %d, RPn: %d, RPe: %d, RP0: %d\n", gt, rpn, rpe, rp0); > > > > /* Set min/max to RPn, RP0 for baseline behavior */ > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0) > 0); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0)); > > > > /* > > * Negative bound tests > > * RPn is the floor > > * RP0 is the ceiling > > */ > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn - 1) < 0); > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0 + 1) < 0); > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn - 1) < 0); > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0 + 1) < 0); > > + igt_assert_lt(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn - 1), 0); > > + igt_assert_lt(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0 + 1), 0); > > + igt_assert_lt(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn - 1), 0); > > + igt_assert_lt(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0 + 1), 0); > > > > /* Assert min requests are respected from rp0 to rpn */ > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0) > 0); > > - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rp0); > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpe) > 0); > > - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpe); > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > > - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0)); > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rp0); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpe)); > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rpe); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rpn); > > > > /* Assert max requests are respected from rpn to rp0 */ > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); > > - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn); > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpe) > 0); > > - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpe); > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0) > 0); > > - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rp0); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rpn); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpe)); > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rpe); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0)); > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rp0); > > > > } > > > > @@ -100,8 +100,8 @@ static void test_reset(int i915, int dirfd, int gt, int count) > > > > for (int i = 0; i < count; i++) { > > igt_debug("Running cycle: %d", i); > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); > > usleep(ACT_FREQ_LATENCY_US); > > req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ); > > if (req_freq) > > @@ -124,8 +124,8 @@ static void test_suspend(int i915, int dirfd, int gt) > > uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ); > > uint32_t req_freq; > > > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); > > usleep(ACT_FREQ_LATENCY_US); > > req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ); > > if (req_freq) > > @@ -149,8 +149,10 @@ static void restore_sysfs_freq(int sig) > > /* Restore frequencies */ > > for_each_sysfs_gt_dirfd(i915, dirfd, gt) { > > igt_pm_ignore_slpc_efficient_freq(i915, dirfd, false); > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, stash_max[gt]) > 0); > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, stash_min[gt]) > 0); > > + igt_assert_lt(0, > > + set_freq(dirfd, RPS_MAX_FREQ_MHZ, stash_max[gt])); > > + igt_assert_lt(0, > > + set_freq(dirfd, RPS_MIN_FREQ_MHZ, stash_min[gt])); > > } > > free(stash_min); > > free(stash_max); > > diff --git a/tests/intel/i915_pm_rc6_residency.c b/tests/intel/i915_pm_rc6_residency.c > > index ebc0c235c..7942d46d3 100644 > > --- a/tests/intel/i915_pm_rc6_residency.c > > +++ b/tests/intel/i915_pm_rc6_residency.c > > @@ -250,7 +250,7 @@ static char *get_drpc(int i915, int gt_id) > > int gt_dir; > > > > gt_dir = igt_debugfs_gt_dir(i915, gt_id); > > - igt_assert(gt_dir != -1); > > + igt_assert_neq(gt_dir, -1); > > return igt_sysfs_get(gt_dir, "drpc"); > > } > > > > @@ -307,7 +307,7 @@ static int open_pmu(int i915, uint64_t config) > > > > fd = perf_i915_open(i915, config); > > igt_skip_on(fd < 0 && errno == ENODEV); > > - igt_assert(fd >= 0); > > + igt_assert_lte(0, fd); > > > > return fd; > > } > > diff --git a/tests/intel/i915_pm_rps.c b/tests/intel/i915_pm_rps.c > > index 99b83f315..3b7da197d 100644 > > --- a/tests/intel/i915_pm_rps.c > > +++ b/tests/intel/i915_pm_rps.c > > @@ -322,7 +322,8 @@ static void load_helper_run(enum load load) > > spin[high_load] = __igt_spin_new(drm_fd, .ahnd = ahnd); > > > > if (lh.signal && high_load != prev_load) { > > - write(lh.link, &lh.signal, sizeof(lh.signal)); > > + igt_assert_eq(write(lh.link, &lh.signal, sizeof(lh.signal)), > > + sizeof(lh.signal)); > > lh.signal = false; > > } > > prev_load = high_load; > > @@ -690,9 +691,9 @@ static uint64_t __fence_order(int i915, > > obj->flags = flags1; > > gem_execbuf(i915, eb); > > > > - read(fd, before, sizeof(before)); > > + igt_assert_eq(read(fd, before, sizeof(before)), sizeof(before)); > > gem_sync(i915, obj->handle); > > - read(fd, after, sizeof(after)); > > + igt_assert_eq(read(fd, after, sizeof(after)), sizeof(after)); > > close(fd); > > > > after[0] -= before[0]; > > @@ -796,9 +797,9 @@ static uint64_t __engine_order(int i915, > > gem_execbuf(i915, eb); > > } > > > > - read(fd, before, sizeof(before)); > > + igt_assert_eq(read(fd, before, sizeof(before)), sizeof(before)); > > gem_sync(i915, obj->handle); > > - read(fd, after, sizeof(after)); > > + igt_assert_eq(read(fd, after, sizeof(after)), sizeof(after)); > > close(fd); > > > > after[0] -= before[0]; > > diff --git a/tests/intel/i915_query.c b/tests/intel/i915_query.c > > index f886297ed..4d706d62b 100644 > > --- a/tests/intel/i915_query.c > > +++ b/tests/intel/i915_query.c > > @@ -491,7 +491,7 @@ test_query_topology_matches_eu_total(int fd) > > > > free(topo_info); > > > > - igt_assert(n_eus_topology == n_eus); > > + igt_assert_eq(n_eus_topology, n_eus); > > } > > > > /* > > @@ -1380,7 +1380,7 @@ static void query_parse_and_validate_hwconfig_table(int i915) > > i915_query_items(i915, &item, 1); > > igt_assert(item.length == table_size); > > igt_info("Table size = %d bytes\n", table_size); > > - igt_assert(table_size > 0); > > + igt_assert_lt(0, table_size); > > > > /* HWConfig table is a list of KLV sets */ > > max_words = table_size / sizeof(uint32_t); > > @@ -1391,21 +1391,21 @@ static void query_parse_and_validate_hwconfig_table(int i915) > > igt_assert(data[i] < __INTEL_HWCONFIG_KEY_LIMIT); > > > > len = data[i + 1]; > > - igt_assert(len > 0); > > - igt_assert((i + 2 + len) <= max_words); > > + igt_assert_lt(0, len); > > + igt_assert_lte((i + 2 + len), max_words); > > > > igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]); > > > > value = data[i + 2]; > > switch (data[i]) { > > case INTEL_HWCONFIG_MEMORY_TYPE: > > - igt_assert(len == 1); > > + igt_assert_eq(len, 1); > > igt_assert(value < __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT); > > igt_info("%s\n", hwconfig_memtypes[value]); > > break; > > > > case INTEL_HWCONFIG_CACHE_TYPES: > > - igt_assert(len == 1); > > + igt_assert_eq(len, 1); > > > > if (!value) > > igt_info("-\n"); > > diff --git a/tests/intel/kms_big_fb.c b/tests/intel/kms_big_fb.c > > index 605813f7f..b808b4a02 100644 > > --- a/tests/intel/kms_big_fb.c > > +++ b/tests/intel/kms_big_fb.c > > @@ -307,7 +307,7 @@ static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width, > > igt_remove_fb(data->drm_fd, &col_fb); > > } > > > > - igt_assert(drmIoctl(data->drm_fd, DRM_IOCTL_MODE_ADDFB2, &f) == 0); > > + do_ioctl(data->drm_fd, DRM_IOCTL_MODE_ADDFB2, &f); > > newfb->fb_id = f.fb_id; > > } > > > > diff --git a/tests/intel/kms_busy.c b/tests/intel/kms_busy.c > > index db45e286e..5917b888f 100644 > > --- a/tests/intel/kms_busy.c > > +++ b/tests/intel/kms_busy.c > > @@ -388,7 +388,7 @@ static void gpu_engines_init_timeouts(int fd, int max_engines, > > > > *num_engines = 0; > > for_each_physical_engine(fd, e) { > > - igt_assert(*num_engines < max_engines); > > + igt_assert_lt(*num_engines, max_engines); > > > > props[*num_engines].engine = *e; > > props[*num_engines].preempt_timeout = 0; > > diff --git a/tests/intel/kms_ccs.c b/tests/intel/kms_ccs.c > > index c91370a9a..f262b271c 100644 > > --- a/tests/intel/kms_ccs.c > > +++ b/tests/intel/kms_ccs.c > > @@ -348,7 +348,7 @@ static void check_ccs_cc_plane(int drm_fd, igt_fb_t *fb, int plane, const float > > (uint8_t)(cc_color[1] * 0xff) << 8 | > > (uint8_t)(cc_color[2] * 0xff); > > > > - igt_assert(native_color == cc_p[4].d); > > + igt_assert_eq_u32(native_color, cc_p[4].d); > > > > igt_assert(gem_munmap(map, fb->size) == 0); > > }; > > diff --git a/tests/intel/kms_cdclk.c b/tests/intel/kms_cdclk.c > > index 7baf7d98e..6fe6e6c3f 100644 > > --- a/tests/intel/kms_cdclk.c > > +++ b/tests/intel/kms_cdclk.c > > @@ -236,9 +236,8 @@ static void test_mode_transition(data_t *data, enum pipe pipe, igt_output_t *out > > mode_hi = get_highres_mode(output); > > igt_require(mode_hi != NULL); > > > > - if (mode_hi->hdisplay == mode_lo->hdisplay && > > - mode_hi->vdisplay == mode_lo->vdisplay) > > - igt_skip("Highest and lowest mode resolutions are same; no transition\n"); > > + igt_skip_on_f(mode_hi->hdisplay == mode_lo->hdisplay && mode_hi->vdisplay == mode_lo->vdisplay, > > + "Highest and lowest mode resolutions are same; no transition\n"); > > > > primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); > > > > diff --git a/tests/intel/kms_dsc_helper.c b/tests/intel/kms_dsc_helper.c > > index 58057aca3..0de09b8e9 100644 > > --- a/tests/intel/kms_dsc_helper.c > > +++ b/tests/intel/kms_dsc_helper.c > > @@ -35,7 +35,7 @@ void save_force_dsc_en(int drmfd, igt_output_t *output) > > igt_is_force_dsc_enabled(drmfd, output->name); > > force_dsc_restore_fd = > > igt_get_dsc_debugfs_fd(drmfd, output->name); > > - igt_assert(force_dsc_restore_fd >= 0); > > + igt_assert_lte(0, force_dsc_restore_fd); > > } > > > > void restore_force_dsc_en(void) > > @@ -163,7 +163,7 @@ void save_force_dsc_fractional_bpp_en(int drmfd, igt_output_t *output) > > igt_is_force_dsc_fractional_bpp_enabled(drmfd, output->name); > > force_dsc_fractional_bpp_restore_fd = > > igt_get_dsc_fractional_bpp_debugfs_fd(drmfd, output->name); > > - igt_assert(force_dsc_fractional_bpp_restore_fd >= 0); > > + igt_assert_lte(0, force_dsc_fractional_bpp_restore_fd); > > } > > > > void restore_force_dsc_fractional_bpp_en(void) > > diff --git a/tests/intel/kms_fbcon_fbt.c b/tests/intel/kms_fbcon_fbt.c > > index 71e42f19c..edf6f8d4e 100644 > > --- a/tests/intel/kms_fbcon_fbt.c > > +++ b/tests/intel/kms_fbcon_fbt.c > > @@ -317,8 +317,7 @@ static void fbc_skips_on_fbcon(int debugfs_fd) > > for (i = 0; skip == false && i < ARRAY_SIZE(reasons); i++) > > skip = strstr(buf, reasons[i]); > > > > - if (skip) > > - igt_skip("fbcon modeset is not compatible with FBC\n"); > > + igt_skip_on_f(skip, "fbcon modeset is not compatible with FBC\n"); > > } > > > > static void psr_skips_on_fbcon(int debugfs_fd) > > diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c > > index e1318bfa6..1aef1e02d 100644 > > --- a/tests/intel/kms_pm_dc.c > > +++ b/tests/intel/kms_pm_dc.c > > @@ -230,11 +230,10 @@ static uint32_t get_dc_counter(char *dc_data) > > long ret; > > char *s = strchr(dc_data, ':'); > > > > - assert(s); > > + igt_assert(s); > > s++; > > ret = strtol(s, &e, 10); > > - assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) && > > - e > s && *e == '\n' && ret >= 0); > > + igt_assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) && e > s && *e == '\n' && ret >= 0); > > return ret; > > } > > > > @@ -611,8 +610,8 @@ static void test_deep_pkgc_state(data_t *data) > > } > > > > /* Skip the test if no VRR capable output is found */ > > - if (!vrr_supported) > > - igt_skip("No VRR capable output found, skipping the test.\n"); > > + igt_skip_on_f(!vrr_supported, > > + "No VRR capable output found, skipping the test.\n"); > > > > igt_display_reset(display); > > > > diff --git a/tests/intel/kms_pm_rpm.c b/tests/intel/kms_pm_rpm.c > > index 66c68b902..5af3e81bc 100644 > > --- a/tests/intel/kms_pm_rpm.c > > +++ b/tests/intel/kms_pm_rpm.c > > @@ -1527,7 +1527,7 @@ static void pm_test_tiling(void) > > gem_set_tiling(drm_fd, handles[j], > > tiling_modes[i], stride); > > gem_get_tiling(drm_fd, handles[j], &ti, &sw); > > - igt_assert(tiling_modes[i] == ti); > > + igt_assert_eq_u32(tiling_modes[i], ti); > > } > > > > enable_one_screen_and_wait(&ms_data); > > diff --git a/tests/intel/kms_psr.c b/tests/intel/kms_psr.c > > index f3caa9ecc..cf0ce4bb8 100644 > > --- a/tests/intel/kms_psr.c > > +++ b/tests/intel/kms_psr.c > > @@ -499,27 +499,27 @@ static void fill_render(data_t *data, const struct igt_fb *fb, > > > > static bool psr_wait_entry_if_enabled(data_t *data) > > { > > - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) > > - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", > > - data->op_psr_mode); > > + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), > > + "enable_psr modparam doesn't allow psr mode %d\n", > > + data->op_psr_mode); > > > > return psr_wait_entry(data->debugfs_fd, data->op_psr_mode, data->output); > > } > > > > static bool psr_wait_update_if_enabled(data_t *data) > > { > > - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) > > - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", > > - data->op_psr_mode); > > + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), > > + "enable_psr modparam doesn't allow psr mode %d\n", > > + data->op_psr_mode); > > > > return psr_wait_update(data->debugfs_fd, data->op_psr_mode, data->output); > > } > > > > static bool psr_enable_if_enabled(data_t *data) > > { > > - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) > > - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", > > - data->op_psr_mode); > > + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), > > + "enable_psr modparam doesn't allow psr mode %d\n", > > + data->op_psr_mode); > > > > return psr_enable(data->drm_fd, data->debugfs_fd, data->op_psr_mode, data->output); > > } > > diff --git a/tests/intel/perf.c b/tests/intel/perf.c > > index 95b17f522..c5a103c94 100644 > > --- a/tests/intel/perf.c > > +++ b/tests/intel/perf.c > > @@ -493,12 +493,12 @@ __perf_open(int fd, struct drm_i915_perf_open_param *param, bool prevent_pm) > > > > ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param); > > > > - igt_assert(ret >= 0); > > + igt_assert_lte(0, ret); > > errno = 0; > > > > if (prevent_pm) { > > pm_fd = open("/dev/cpu_dma_latency", O_RDWR); > > - igt_assert(pm_fd >= 0); > > + igt_assert_lte(0, pm_fd); > > > > igt_assert_eq(write(pm_fd, &pm_value, sizeof(pm_value)), sizeof(pm_value)); > > } > > @@ -625,7 +625,7 @@ elapsed_delta(uint64_t t1, uint64_t t0, uint32_t width) > > { > > uint32_t max_bits = sizeof(t1) * 8; > > > > - igt_assert(width <= max_bits); > > + igt_assert_lte_u32(width, max_bits); > > > > if (t1 < t0 && width != max_bits) > > return ((1ULL << width) - t0) + t1; > > @@ -2128,7 +2128,7 @@ test_oa_exponents(const struct intel_execution_engine2 *e) > > /* igt_debug(" > read %i bytes\n", ret); */ > > > > /* We should never have no data. */ > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > > > for (int offset = 0; > > offset < ret && n_timer_reports < NUM_TIMER_REPORTS; > > @@ -2472,7 +2472,7 @@ test_blocking(uint64_t requested_oa_period, > > errno == EINTR) > > ; > > > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > > > /* For Haswell reports don't contain a well defined reason > > * field we so assume all reports to be 'periodic'. For gen8+ > > @@ -2526,12 +2526,12 @@ test_blocking(uint64_t requested_oa_period, > > /* With completely broken blocking (but also not returning an error) we > > * could end up with an open loop, > > */ > > - igt_assert(n <= (max_iterations + n_extra_iterations)); > > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > > > /* Make sure the driver is reporting new samples with a reasonably > > * low latency... > > */ > > - igt_assert(n > (min_iterations + n_extra_iterations)); > > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > > > if (!set_kernel_hrtimer) > > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > > @@ -2728,12 +2728,12 @@ test_polling(uint64_t requested_oa_period, > > /* With completely broken blocking while polling (but still somehow > > * reporting a POLLIN event) we could end up with an open loop. > > */ > > - igt_assert(n <= (max_iterations + n_extra_iterations)); > > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > > > /* Make sure the driver is reporting new samples with a reasonably > > * low latency... > > */ > > - igt_assert(n > (min_iterations + n_extra_iterations)); > > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > > > if (!set_kernel_hrtimer) > > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > > @@ -2821,7 +2821,7 @@ num_valid_reports_captured(struct drm_i915_perf_open_param *param, > > errno == EINTR) > > ; > > > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > > > for (int offset = 0; offset < ret; offset += header->size) { > > header = (void *)(buf + offset); > > @@ -3343,7 +3343,7 @@ test_short_reads(void) > > ret = read(stream_fd, > > header, > > page_size); > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > } while (header->type == DRM_I915_PERF_RECORD_OA_REPORT_LOST); > > > > igt_assert_eq(ret, record_size); > > @@ -5001,7 +5001,7 @@ static int i915_perf_add_config(int fd, struct drm_i915_perf_oa_config *config) > > int config_id = __i915_perf_add_config(fd, config); > > > > igt_debug("config_id=%i\n", config_id); > > - igt_assert(config_id > 0); > > + igt_assert_lt(0, config_id); > > > > return config_id; > > } > > @@ -5339,7 +5339,7 @@ test_whitelisted_registers_userspace_config(void) > > > > /* Create a new config */ > > ret = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, &config); > > - igt_assert(ret > 0); /* Config 0 should be used by the kernel */ > > + igt_assert_lt(0, ret); /* Config 0 should be used by the kernel */ > > config_id = ret; > > > > i915_perf_remove_config(drm_fd, config_id); > > @@ -5360,7 +5360,7 @@ read_i915_module_ref(void) > > if (strncmp(line, "i915 ", 5) == 0) { > > unsigned long mem; > > int ret = sscanf(line + 5, "%lu %u", &mem, &ref_count); > > - igt_assert(ret == 2); > > + igt_assert_eq(ret, 2); > > goto done; > > } > > } > > @@ -5381,7 +5381,7 @@ static int perf_sysfs_open(int i915) > > for_each_sysfs_gt_dirfd(i915, dirfd, gt) > > break; > > > > - igt_assert(dirfd != -1); > > + igt_assert_neq(dirfd, -1); > > > > return dirfd; > > } > > @@ -5784,7 +5784,7 @@ test_group_exclusive_stream(const intel_ctx_t *ctx, bool exponent) > > grp->perf_fd = igt_ioctl(drm_fd, > > DRM_IOCTL_I915_PERF_OPEN, > > ¶m); > > - igt_assert(grp->perf_fd >= 0); > > + igt_assert_lte(0, grp->perf_fd); > > igt_debug("opened OA buffer with c:i %d:%d\n", > > ci->engine_class, ci->engine_instance); > > } > > @@ -5826,7 +5826,7 @@ test_group_exclusive_stream(const intel_ctx_t *ctx, bool exponent) > > param.num_properties = ARRAY_SIZE(properties) / 2 - 1; > > errno = 0; > > err = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m); > > - igt_assert(err < 0); > > + igt_assert_lt(err, 0); > > igt_assert(errno == EBUSY || errno == ENODEV); > > igt_debug("try OA ci unit with c:i %d:%d\n", > > ci->engine_class, ci->engine_instance); > > diff --git a/tests/intel/perf_pmu.c b/tests/intel/perf_pmu.c > > index e3f51d0c7..bfa2d501a 100644 > > --- a/tests/intel/perf_pmu.c > > +++ b/tests/intel/perf_pmu.c > > @@ -200,7 +200,7 @@ static char *get_drpc(int i915, int gt_id) > > int gt_dir; > > > > gt_dir = igt_debugfs_gt_dir(i915, gt_id); > > - igt_assert(gt_dir != -1); > > + igt_assert_neq(gt_dir, -1); > > return igt_sysfs_get(gt_dir, "drpc"); > > } > > > > @@ -210,7 +210,7 @@ static int open_pmu(int i915, uint64_t config) > > > > fd = perf_i915_open(i915, config); > > igt_skip_on(fd < 0 && errno == ENODEV); > > - igt_assert(fd >= 0); > > + igt_assert_lte(0, fd); > > > > return fd; > > } > > @@ -221,7 +221,7 @@ static int open_group(int i915, uint64_t config, int group) > > > > fd = perf_i915_open_group(i915, config, group); > > igt_skip_on(fd < 0 && errno == ENODEV); > > - igt_assert(fd >= 0); > > + igt_assert_lte(0, fd); > > > > return fd; > > } > > @@ -527,7 +527,7 @@ static void log_busy(unsigned int num_engines, uint64_t *val) > > int len; > > > > len = snprintf(p, rem, "%u=%" PRIu64 "\n", i, val[i]); > > - igt_assert(len > 0); > > + igt_assert_lt(0, len); > > rem -= len; > > p += len; > > } > > @@ -950,7 +950,7 @@ __sema_busy(int gem_fd, uint64_t ahnd, int pmu, const intel_ctx_t *ctx, > > int timeout = 3; > > > > /* Time spent being busy includes time waiting on semaphores */ > > - igt_assert(busy_pct >= sema_pct); > > + igt_assert_lte(sema_pct, busy_pct); > > > > gem_quiescent_gpu(gem_fd); > > > > @@ -1359,7 +1359,7 @@ static void open_invalid(int i915) > > int fd; > > > > fd = perf_i915_open(i915, -1ULL); > > - igt_assert(fd < 0); > > + igt_assert_lt(fd, 0); > > } > > > > static bool cpu0_hotplug_support(void) > > @@ -1415,7 +1415,7 @@ static void cpu_hotplug(int gem_fd) > > cpu), sizeof(name)); > > cpufd = open(name, O_WRONLY); > > if (cpufd == -1) { > > - igt_assert(cpu > 0); > > + igt_assert_lt(0, cpu); > > /* > > * Signal parent that we cycled through all > > * CPUs and we are done. > > @@ -1534,7 +1534,7 @@ test_interrupts(int gem_fd) > > close(old_fd); > > } > > > > - igt_assert(fence_fd >= 0); > > + igt_assert_lte(0, fence_fd); > > } > > > > /* Wait for idle state. */ > > @@ -1755,9 +1755,9 @@ test_frequency(int gem_fd, unsigned int gt) > > */ > > __igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq); > > __igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz", &read_value); > > - if (read_value != min_freq) > > - igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n", > > - min_freq, read_value); > > + igt_warn_on_f(read_value != min_freq, > > + "Unable to restore min frequency to saved value [%u MHz], now %u MHz\n", > > + min_freq, read_value); > > close(fd[0]); > > close(fd[1]); > > put_ahnd(ahnd); > > @@ -1880,7 +1880,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) > > continue; > > > > if (gt_ == gt) { > > - igt_assert(test_idx == -1); > > + igt_assert_eq(test_idx, -1); > > test_idx = pmus; > > } > > > > @@ -1890,7 +1890,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) > > igt_skip_on(fd[pmus] < 0 && errno == ENODEV); > > pmus++; > > } > > - igt_assert(test_idx >= 0); > > + igt_assert_lte(0, test_idx); > > > > if (flags & TEST_RUNTIME_PM) { > > drmModeRes *res; > > @@ -1981,7 +1981,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) > > continue; > > > > fw[gt_] = open_forcewake_handle(gem_fd, gt_); > > - igt_assert(fw[gt_] >= 0); > > + igt_assert_lte(0, fw[gt_]); > > } > > > > usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */ > > @@ -2206,7 +2206,8 @@ accuracy(int gem_fd, const intel_ctx_t *ctx, > > 100 * expected, target_busy_pct, > > avg, sqrt(var / n)); > > > > - write(link[1], &expected, sizeof(expected)); > > + igt_assert_eq(write(link[1], &expected, sizeof(expected)), > > + sizeof(expected)); > > } > > > > igt_spin_free(gem_fd, spin); > > @@ -2216,12 +2217,14 @@ accuracy(int gem_fd, const intel_ctx_t *ctx, > > fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance)); > > > > /* Let the child run. */ > > - read(link[0], &expected, sizeof(expected)); > > + igt_assert_eq(read(link[0], &expected, sizeof(expected)), > > + sizeof(expected)); > > assert_within(100.0 * expected, target_busy_pct, 5); > > > > /* Collect engine busyness for an interesting part of child runtime. */ > > val[0] = __pmu_read_single(fd, &ts[0]); > > - read(link[0], &expected, sizeof(expected)); > > + igt_assert_eq(read(link[0], &expected, sizeof(expected)), > > + sizeof(expected)); > > val[1] = __pmu_read_single(fd, &ts[1]); > > close(fd); > > > > diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c > > index beccfcb1a..a55ee5abd 100644 > > --- a/tests/intel/xe_ccs.c > > +++ b/tests/intel/xe_ccs.c > > @@ -212,7 +212,7 @@ static void surf_copy(int xe, > > WRITE_PNG(xe, run_id, "corrupted", &blt.dst, dst->x2, dst->y2, bpp); > > result = memcmp(src->ptr, dst->ptr, src->size); > > if (blt_platform_has_flat_ccs_enabled(xe)) > > - igt_assert(result != 0); > > + igt_assert_neq(result, 0); > > > > /* In case of suspend_resume, buffer object would become > > * uncompressed in xe2+ dgfx, and therefore retrieve the > > @@ -696,7 +696,7 @@ static int opt_handler(int opt, int opt_index, void *data) > > case 'f': > > param.compression_format = atoi(optarg); > > igt_debug("Compression format: %d\n", param.compression_format); > > - igt_assert((param.compression_format & ~0x1f) == 0); > > + igt_assert_eq((param.compression_format & ~0x1f), 0); > > break; > > case 'p': > > param.write_png = true; > > diff --git a/tests/intel/xe_debugfs.c b/tests/intel/xe_debugfs.c > > index a7d56a0be..a7c567c45 100644 > > --- a/tests/intel/xe_debugfs.c > > +++ b/tests/intel/xe_debugfs.c > > @@ -222,7 +222,7 @@ test_forcewake(int fd) > > { > > int handle = igt_debugfs_open(fd, "forcewake_all", O_WRONLY); > > > > - igt_assert(handle != -1); > > + igt_assert_neq(handle, -1); > > close(handle); > > } > > > > diff --git a/tests/intel/xe_dma_buf_sync.c b/tests/intel/xe_dma_buf_sync.c > > index f0d3f0d54..7af80dd2f 100644 > > --- a/tests/intel/xe_dma_buf_sync.c > > +++ b/tests/intel/xe_dma_buf_sync.c > > @@ -108,7 +108,7 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, > > } *data [MAX_N_BO]; > > int i; > > > > - igt_assert(n_bo <= MAX_N_BO); > > + igt_assert_lte(n_bo, MAX_N_BO); > > > > for (i = 0; i < N_FD; ++i) { > > fd[i] = drm_open_driver(DRIVER_XE); > > diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c > > index eebdbc84b..f0c66c49e 100644 > > --- a/tests/intel/xe_evict.c > > +++ b/tests/intel/xe_evict.c > > @@ -57,7 +57,7 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci, > > } *data; > > int i, b; > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > bo = calloc(n_execs / 2, sizeof(*bo)); > > igt_assert(bo); > > @@ -237,7 +237,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, > > } *data; > > int i, b; > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > bo = calloc(n_execs / 2, sizeof(*bo)); > > igt_assert(bo); > > diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c > > index a6dbd748b..73f69e7b0 100644 > > --- a/tests/intel/xe_exec_balancer.c > > +++ b/tests/intel/xe_exec_balancer.c > > @@ -190,7 +190,7 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs, > > struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; > > int i, j, b, num_placements = 0; > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > xe_for_each_engine(fd, hwe) { > > if (hwe->engine_class != class || hwe->gt_id != gt) > > @@ -410,7 +410,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > > int i, j, b, num_placements = 0; > > int map_fd = -1; > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > xe_for_each_engine(fd, hwe) { > > if (hwe->engine_class != class || hwe->gt_id != gt) > > @@ -534,7 +534,8 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > > if (flags & RACE) { > > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > > 0x666); > > - write(map_fd, data, bo_size); > > + igt_assert_eq(write(map_fd, data, bo_size), > > + bo_size); > > data = mmap((void *)MAP_ADDRESS, bo_size, > > PROT_READ | PROT_WRITE, MAP_SHARED | > > MAP_FIXED, map_fd, 0); > > diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c > > index 0fd1ae062..dfbd68d1d 100644 > > --- a/tests/intel/xe_exec_basic.c > > +++ b/tests/intel/xe_exec_basic.c > > @@ -122,8 +122,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > } *data; > > int i, b; > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > - igt_assert(n_vm <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_vm, MAX_N_EXEC_QUEUES); > > > > for (i = 0; i < n_vm; ++i) > > vm[i] = xe_vm_create(fd, 0, 0); > > diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c > > index 389de7ca4..b92feee2c 100644 > > --- a/tests/intel/xe_exec_compute_mode.c > > +++ b/tests/intel/xe_exec_compute_mode.c > > @@ -115,7 +115,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > int map_fd = -1; > > int64_t fence_timeout; > > > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > > > vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); > > bo_size = sizeof(*data) * n_execs; > > @@ -243,7 +243,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > if (flags & RACE) { > > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > > 0x666); > > - write(map_fd, data, bo_size); > > + igt_assert_eq(write(map_fd, data, bo_size), > > + bo_size); > > data = mmap((void *)MAP_ADDRESS, bo_size, > > PROT_READ | PROT_WRITE, MAP_SHARED | > > MAP_FIXED, map_fd, 0); > > @@ -457,7 +458,7 @@ static void lr_mode_workload(int fd) > > ts_1 = spin->timestamp; > > sleep(1); > > ts_2 = spin->timestamp; > > - igt_assert(ts_1 != ts_2); > > + igt_assert_neq_u32(ts_1, ts_2); > > > > xe_spin_end(spin); > > xe_wait_ufence(fd, &spin->exec_sync, USER_FENCE_VALUE, 0, ONE_SEC); > > @@ -466,7 +467,7 @@ static void lr_mode_workload(int fd) > > ts_1 = spin->timestamp; > > sleep(1); > > ts_2 = spin->timestamp; > > - igt_assert(ts_1 == ts_2); > > + igt_assert_eq_u32(ts_1, ts_2); > > > > sync.addr = to_user_pointer(&vm_sync); > > xe_vm_unbind_async(fd, vm, 0, 0, spin_addr, bo_size, &sync, 1); > > diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c > > index b022f97d3..56bad2b75 100644 > > --- a/tests/intel/xe_exec_fault_mode.c > > +++ b/tests/intel/xe_exec_fault_mode.c > > @@ -140,7 +140,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > int i, j, b; > > int map_fd = -1; > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > if (flags & ENABLE_SCRATCH) > > vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE | > > @@ -291,7 +291,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > if (flags & RACE) { > > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > > 0x666); > > - write(map_fd, data, bo_size); > > + igt_assert_eq(write(map_fd, data, bo_size), > > + bo_size); > > data = mmap((void *)MAP_ADDRESS, bo_size, > > PROT_READ | PROT_WRITE, MAP_SHARED | > > MAP_FIXED, map_fd, 0); > > diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c > > index dcb22f275..72f2133e5 100644 > > --- a/tests/intel/xe_exec_reset.c > > +++ b/tests/intel/xe_exec_reset.c > > @@ -155,7 +155,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, > > struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; > > int i, j, b, num_placements = 0, bad_batches = 1; > > > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > > > if (flags & CLOSE_FD) > > fd = drm_open_driver(DRIVER_XE); > > @@ -326,7 +326,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, > > struct xe_spin_opts spin_opts = { .preempt = false }; > > int i, b; > > > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > > > if (flags & CLOSE_FD) > > fd = drm_open_driver(DRIVER_XE); > > @@ -475,7 +475,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > > struct xe_spin_opts spin_opts = { .preempt = false }; > > int i, b; > > > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > > > if (flags & CLOSE_FD) > > fd = drm_open_driver(DRIVER_XE); > > @@ -704,7 +704,7 @@ gt_reset(int fd, int n_threads, int n_sec) > > for (i = 0; i < n_threads; i++) > > pthread_join(threads[i].thread, NULL); > > > > - printf("number of resets %d\n", num_reset); > > + igt_info("number of resets %d\n", num_reset); > > > > free(threads); > > } > > diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c > > index c872c22d5..5c1dd0a01 100644 > > --- a/tests/intel/xe_exec_store.c > > +++ b/tests/intel/xe_exec_store.c > > @@ -249,7 +249,7 @@ static void store_cachelines(int fd, struct drm_xe_engine_class_instance *eci, > > object_index = n % (count - 1); > > ptr[n] = bo_map[object_index] + delta / 4; > > > > - igt_assert(*ptr[n] == value[n]); > > + igt_assert_eq_u32(*ptr[n], value[n]); > > } > > > > for (i = 0; i < count; i++) { > > diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c > > index e7a0a7cd0..6e53d3cf8 100644 > > --- a/tests/intel/xe_exec_threads.c > > +++ b/tests/intel/xe_exec_threads.c > > @@ -70,7 +70,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr, > > int i, j, b, num_placements = 0; > > bool owns_vm = false, owns_fd = false; > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > if (flags & FD) { > > fd = drm_reopen_driver(fd); > > @@ -88,7 +88,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr, > > > > eci[num_placements++] = *hwe; > > } > > - igt_assert(num_placements > 1); > > + igt_assert_lt(1, num_placements); > > > > bo_size = sizeof(*data) * n_execs; > > bo_size = xe_bb_size(fd, bo_size); > > @@ -272,7 +272,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > > int map_fd = -1; > > bool owns_vm = false, owns_fd = false; > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > if (flags & FD) { > > fd = drm_reopen_driver(fd); > > @@ -396,7 +396,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > > if (flags & RACE) { > > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > > 0x666); > > - write(map_fd, data, bo_size); > > + igt_assert_eq(write(map_fd, data, bo_size), > > + bo_size); > > data = mmap(from_user_pointer(userptr), bo_size, > > PROT_READ | PROT_WRITE, > > MAP_SHARED | MAP_FIXED, > > @@ -476,7 +477,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > > int i, j, b, hang_exec_queue = n_exec_queues / 2; > > bool owns_vm = false, owns_fd = false; > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > if (flags & FD) { > > fd = drm_reopen_driver(fd); > > diff --git a/tests/intel/xe_gt_freq.c b/tests/intel/xe_gt_freq.c > > index 93ebb5ed0..365c9b9e6 100644 > > --- a/tests/intel/xe_gt_freq.c > > +++ b/tests/intel/xe_gt_freq.c > > @@ -41,7 +41,7 @@ static int set_freq(int fd, int gt_id, const char *freq_name, uint32_t freq) > > > > snprintf(freq_attr, sizeof(freq_attr), "freq0/%s_freq", freq_name); > > gt_fd = xe_sysfs_gt_open(fd, gt_id); > > - igt_assert(gt_fd >= 0); > > + igt_assert_lte(0, gt_fd); > > > > while (ret == -EAGAIN) > > ret = igt_sysfs_printf(gt_fd, freq_attr, "%u", freq); > > @@ -59,7 +59,7 @@ static uint32_t get_freq(int fd, int gt_id, const char *freq_name) > > > > snprintf(freq_attr, sizeof(freq_attr), "freq0/%s_freq", freq_name); > > gt_fd = xe_sysfs_gt_open(fd, gt_id); > > - igt_assert(gt_fd >= 0); > > + igt_assert_lte(0, gt_fd); > > > > while (err == -EAGAIN) > > err = igt_sysfs_scanf(gt_fd, freq_attr, "%u", &freq); > > @@ -84,7 +84,7 @@ static uint32_t get_throttle(int fd, int gt_id, const char *throttle_file) > > snprintf(throttle_attr, sizeof(throttle_attr), > > "freq0/throttle/%s", throttle_file); > > gt_fd = xe_sysfs_gt_open(fd, gt_id); > > - igt_assert(gt_fd >= 0); > > + igt_assert_lte(0, gt_fd); > > > > igt_sysfs_scanf(gt_fd, throttle_attr, "%u", &val); > > > > @@ -134,26 +134,26 @@ static void test_freq_basic_api(int fd, int gt_id) > > * RPn is the floor > > * RP0 is the ceiling > > */ > > - igt_assert(set_freq(fd, gt_id, "min", rpn - 1) < 0); > > - igt_assert(set_freq(fd, gt_id, "min", rp0 + 1) < 0); > > - igt_assert(set_freq(fd, gt_id, "max", rpn - 1) < 0); > > - igt_assert(set_freq(fd, gt_id, "max", rp0 + 1) < 0); > > + igt_assert_lt(set_freq(fd, gt_id, "min", rpn - 1), 0); > > + igt_assert_lt(set_freq(fd, gt_id, "min", rp0 + 1), 0); > > + igt_assert_lt(set_freq(fd, gt_id, "max", rpn - 1), 0); > > + igt_assert_lt(set_freq(fd, gt_id, "max", rp0 + 1), 0); > > > > /* Assert min requests are respected from rp0 to rpn */ > > - igt_assert(set_freq(fd, gt_id, "min", rp0) > 0); > > - igt_assert(get_freq(fd, gt_id, "min") == rp0); > > - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); > > - igt_assert(get_freq(fd, gt_id, "min") == rpe(fd, gt_id)); > > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > > - igt_assert(get_freq(fd, gt_id, "min") == rpn); > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rp0)); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rp0); > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpe(fd, gt_id)); > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpn); > > > > /* Assert max requests are respected from rpn to rp0 */ > > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > > - igt_assert(get_freq(fd, gt_id, "max") == rpn); > > - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); > > - igt_assert(get_freq(fd, gt_id, "max") == rpe(fd, gt_id)); > > - igt_assert(set_freq(fd, gt_id, "max", rp0) > 0); > > - igt_assert(get_freq(fd, gt_id, "max") == rp0); > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpn); > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpe(fd, gt_id)); > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rp0)); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rp0); > > } > > > > /** > > @@ -176,10 +176,10 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle) > > * Then we check if hardware is actually operating at the desired freq > > * And let's do this for all the 3 known Render Performance (RP) values. > > */ > > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > > usleep(ACT_FREQ_LATENCY_US); > > - igt_assert(get_freq(fd, gt_id, "cur") == rpn); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpn); > > > > if (gt_idle) { > > /* Wait for GT to go in C6 as previous get_freq wakes up GT*/ > > @@ -187,31 +187,31 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle) > > "GT %d should be in C6\n", gt_id); > > igt_assert(get_freq(fd, gt_id, "act") == 0); > > } else { > > - igt_assert(get_freq(fd, gt_id, "act") == rpn); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "act"), rpn); > > } > > > > - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); > > - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); > > usleep(ACT_FREQ_LATENCY_US); > > - igt_assert(get_freq(fd, gt_id, "cur") == rpe(fd, gt_id)); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpe(fd, gt_id)); > > > > if (gt_idle) { > > igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10), > > "GT %d should be in C6\n", gt_id); > > igt_assert(get_freq(fd, gt_id, "act") == 0); > > } else { > > - igt_assert(get_freq(fd, gt_id, "act") == rpe(fd, gt_id)); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "act"), rpe(fd, gt_id)); > > } > > > > - igt_assert(set_freq(fd, gt_id, "min", rp0) > 0); > > - igt_assert(set_freq(fd, gt_id, "max", rp0) > 0); > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rp0)); > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rp0)); > > usleep(ACT_FREQ_LATENCY_US); > > /* > > * It is unlikely that PCODE will *always* respect any request above RPe > > * So for this level let's only check if GuC PC is doing its job > > * and respecting our request, by propagating it to the hardware. > > */ > > - igt_assert(get_freq(fd, gt_id, "cur") == rp0); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rp0); > > > > if (gt_idle) { > > igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10), > > @@ -236,8 +236,8 @@ static void test_freq_range(int fd, int gt_id, bool gt_idle) > > > > igt_debug("Starting testing range request\n"); > > > > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > > - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); > > usleep(ACT_FREQ_LATENCY_US); > > cur = get_freq(fd, gt_id, "cur"); > > igt_assert(rpn <= cur && cur <= rpe(fd, gt_id)); > > @@ -267,12 +267,12 @@ static void test_freq_low_max(int fd, int gt_id) > > * When max request < min request, max is ignored and min works like > > * a fixed one. Let's assert this assumption > > */ > > - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); > > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > > usleep(ACT_FREQ_LATENCY_US); > > > > /* Refresh value of rpe, pcode could have adjusted it */ > > - igt_assert(get_freq(fd, gt_id, "cur") == rpe(fd, gt_id)); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpe(fd, gt_id)); > > } > > > > /** > > @@ -284,16 +284,16 @@ static void test_suspend(int fd, int gt_id) > > { > > uint32_t rpn = get_freq(fd, gt_id, "rpn"); > > > > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > > usleep(ACT_FREQ_LATENCY_US); > > - igt_assert(get_freq(fd, gt_id, "cur") == rpn); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpn); > > > > igt_system_suspend_autoresume(SUSPEND_STATE_S3, > > SUSPEND_TEST_NONE); > > > > - igt_assert(get_freq(fd, gt_id, "min") == rpn); > > - igt_assert(get_freq(fd, gt_id, "max") == rpn); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpn); > > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpn); > > } > > > > /** > > diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c > > index 647fd64e7..845052bf2 100644 > > --- a/tests/intel/xe_intel_bb.c > > +++ b/tests/intel/xe_intel_bb.c > > @@ -674,11 +674,11 @@ static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling) > > > > /* We'll fail on src <-> final compare so just warn */ > > if (tiling == I915_TILING_NONE) { > > - if (compare_bufs(&src, &dst, false) > 0) > > - igt_warn("none->none blit failed!"); > > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > > + "none->none blit failed!"); > > } else { > > - if (compare_bufs(&src, &dst, false) == 0) > > - igt_warn("none->tiled blit failed!"); > > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > > + "none->tiled blit failed!"); > > } > > > > fails = compare_bufs(&src, &final, true); > > @@ -925,11 +925,11 @@ static int render(struct buf_ops *bops, uint32_t tiling, > > > > /* We'll fail on src <-> final compare so just warn */ > > if (tiling == I915_TILING_NONE) { > > - if (compare_bufs(&src, &dst, false) > 0) > > - igt_warn("%s: none->none failed!\n", __func__); > > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > > + "%s: none->none failed!\n", __func__); > > } else { > > - if (compare_bufs(&src, &dst, false) == 0) > > - igt_warn("%s: none->tiled failed!\n", __func__); > > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > > + "%s: none->tiled failed!\n", __func__); > > } > > > > fails = compare_bufs(&src, &final, true); > > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c > > index ff2218300..e26ebceb9 100644 > > --- a/tests/intel/xe_oa.c > > +++ b/tests/intel/xe_oa.c > > @@ -492,12 +492,12 @@ __perf_open(int fd, struct intel_xe_oa_open_prop *param, bool prevent_pm) > > > > ret = intel_xe_perf_ioctl(fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, param); > > > > - igt_assert(ret >= 0); > > + igt_assert_lte(0, ret); > > errno = 0; > > > > if (prevent_pm) { > > pm_fd = open("/dev/cpu_dma_latency", O_RDWR); > > - igt_assert(pm_fd >= 0); > > + igt_assert_lte(0, pm_fd); > > > > igt_assert_eq(write(pm_fd, &pm_value, sizeof(pm_value)), sizeof(pm_value)); > > } > > @@ -568,7 +568,7 @@ elapsed_delta(uint64_t t1, uint64_t t0, uint32_t width) > > { > > uint32_t max_bits = sizeof(t1) * 8; > > > > - igt_assert(width <= max_bits); > > + igt_assert_lte_u32(width, max_bits); > > > > if (t1 < t0 && width != max_bits) > > return ((1ULL << width) - t0) + t1; > > @@ -1710,7 +1710,7 @@ static void test_oa_exponents(const struct drm_xe_engine_class_instance *hwe) > > > > /* igt_debug(" > read %i bytes\n", ret); */ > > /* We should never have no data. */ > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > > > for (int offset = 0; > > offset < ret && n_timer_reports < NUM_TIMER_REPORTS; > > @@ -1933,7 +1933,7 @@ static void test_blocking(uint64_t requested_oa_period, > > while ((ret = read(perf_fd, buf, sizeof(buf))) < 0 && > > (errno == EINTR || errno == EIO)) > > ; > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > > > for (int offset = 0; offset < ret; offset += format_size) { > > uint32_t *report = (void *)(buf + offset); > > @@ -1972,12 +1972,12 @@ static void test_blocking(uint64_t requested_oa_period, > > /* With completely broken blocking (but also not returning an error) we > > * could end up with an open loop, > > */ > > - igt_assert(n <= (max_iterations + n_extra_iterations)); > > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > > > /* Make sure the driver is reporting new samples with a reasonably > > * low latency... > > */ > > - igt_assert(n > (min_iterations + n_extra_iterations)); > > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > > > if (!set_kernel_hrtimer) > > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > > @@ -2163,12 +2163,12 @@ static void test_polling(uint64_t requested_oa_period, > > /* With completely broken blocking while polling (but still somehow > > * reporting a POLLIN event) we could end up with an open loop. > > */ > > - igt_assert(n <= (max_iterations + n_extra_iterations)); > > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > > > /* Make sure the driver is reporting new samples with a reasonably > > * low latency... > > */ > > - igt_assert(n > (min_iterations + n_extra_iterations)); > > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > > > if (!set_kernel_hrtimer) > > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > > @@ -2260,7 +2260,7 @@ num_valid_reports_captured(struct intel_xe_oa_open_prop *param, > > (errno == EINTR || errno == EIO)) > > ; > > > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > > > for (int offset = 0; offset < ret; offset += format_size) { > > uint32_t *report = (void *)(buf + offset); > > @@ -3473,7 +3473,7 @@ static int xe_oa_add_config(int fd, struct drm_xe_oa_config *config) > > int config_id = __xe_oa_add_config(fd, config); > > > > igt_debug("config_id=%i\n", config_id); > > - igt_assert(config_id > 0); > > + igt_assert_lt(0, config_id); > > > > return config_id; > > } > > @@ -3769,7 +3769,7 @@ test_whitelisted_registers_userspace_config(void) > > > > /* Create a new config */ > > ret = intel_xe_perf_ioctl(drm_fd, DRM_XE_OBSERVATION_OP_ADD_CONFIG, &config); > > - igt_assert(ret > 0); /* Config 0 should be used by the kernel */ > > + igt_assert_lt(0, ret); /* Config 0 should be used by the kernel */ > > config_id = ret; > > > > xe_oa_remove_config(drm_fd, config_id); > > @@ -4195,7 +4195,7 @@ test_oa_unit_exclusive_stream(bool exponent) > > properties[11] = exec_q[i]; > > errno = 0; > > err = intel_xe_perf_ioctl(drm_fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, ¶m); > > - igt_assert(err < 0); > > + igt_assert_lt(err, 0); > > igt_assert(errno == EBUSY || errno == ENODEV); > > poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); > > } > > diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c > > index 82155f1d5..153d9ce1d 100644 > > --- a/tests/intel/xe_pat.c > > +++ b/tests/intel/xe_pat.c > > @@ -808,7 +808,7 @@ static void display_vs_wb_transient(int fd) > > > > /* c0 -> c6 might flush caches */ > > fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY); > > - igt_assert(fw_handle >= 0); > > + igt_assert_lte(0, fw_handle); > > > > render_copy(ibb, > > &src, > > diff --git a/tests/intel/xe_peer2peer.c b/tests/intel/xe_peer2peer.c > > index 6ff4774bb..2a941abe6 100644 > > --- a/tests/intel/xe_peer2peer.c > > +++ b/tests/intel/xe_peer2peer.c > > @@ -279,7 +279,7 @@ static char *region_name(int xe, uint32_t region) > > r = snprintf(name, len, "%s", > > xe_region_name(region)); > > > > - igt_assert(r > 0); > > + igt_assert_lt(0, r); > > > > return name; > > } > > diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c > > index 8b115e2f6..eee89428c 100644 > > --- a/tests/intel/xe_pm.c > > +++ b/tests/intel/xe_pm.c > > @@ -94,7 +94,7 @@ static uint64_t get_vram_d3cold_threshold(int sysfs) > > igt_require_f(!faccessat(sysfs, path, R_OK, 0), "vram_d3cold_threshold is not present\n"); > > > > ret = igt_sysfs_scanf(sysfs, path, "%lu", &threshold); > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > > > return threshold; > > } > > @@ -111,7 +111,7 @@ static void set_vram_d3cold_threshold(int sysfs, uint64_t threshold) > > else > > igt_warn("vram_d3cold_threshold is not present\n"); > > > > - igt_assert(ret > 0); > > + igt_assert_lt(0, ret); > > } > > > > static void vram_d3cold_threshold_restore(int sig) > > @@ -305,8 +305,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci, > > bool check_rpm = (d_state == IGT_ACPI_D3Hot || > > d_state == IGT_ACPI_D3Cold); > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > - igt_assert(n_execs > 0); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > + igt_assert_lt(0, n_execs); > > > > if (check_rpm) { > > igt_assert(in_d3(device, d_state)); > > @@ -507,7 +507,7 @@ static void test_vram_d3cold_threshold(device_t device, int sysfs_fd) > > * Therefore open and close fw handle to wake the device. > > */ > > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > > - igt_assert(fw_handle >= 0); > > + igt_assert_lte(0, fw_handle); > > active = igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE; > > close(fw_handle); > > igt_assert(active); > > @@ -557,7 +557,7 @@ static void test_mmap(device_t device, uint32_t placement, uint32_t flags, > > > > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > > > > - igt_assert(fw_handle >= 0); > > + igt_assert_lte(0, fw_handle); > > igt_assert(igt_pm_get_runtime_active_time(device.pci_xe) > > > active_time); > > > > @@ -600,7 +600,7 @@ static void test_mmap(device_t device, uint32_t placement, uint32_t flags, > > > > /* Runtime resume and check the pattern */ > > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > > - igt_assert(fw_handle >= 0); > > + igt_assert_lte(0, fw_handle); > > igt_assert(igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE); > > for (i = 0; i < bo_size / sizeof(*map); i++) > > igt_assert(map[i] == MAGIC_2); > > @@ -651,7 +651,7 @@ static void test_mocs_suspend_resume(device_t device, enum igt_suspend_state s_s > > active_time = igt_pm_get_runtime_active_time(device.pci_xe); > > > > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > > - igt_assert(fw_handle >= 0); > > + igt_assert_lte(0, fw_handle); > > igt_assert(igt_pm_get_runtime_active_time(device.pci_xe) > > > active_time); > > > > diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c > > index 51735d887..1d3ce0762 100644 > > --- a/tests/intel/xe_pm_residency.c > > +++ b/tests/intel/xe_pm_residency.c > > @@ -182,7 +182,7 @@ static unsigned long read_idle_residency(int fd, int gt) > > int gt_fd; > > > > gt_fd = xe_sysfs_gt_open(fd, gt); > > - igt_assert(gt_fd >= 0); > > + igt_assert_lte(0, gt_fd); > > igt_assert(igt_sysfs_scanf(gt_fd, "gtidle/idle_residency_ms", "%lu", &residency) == 1); > > close(gt_fd); > > > > @@ -280,7 +280,7 @@ static void toggle_gt_c6(int fd, int n) > > > > do { > > fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY); > > - igt_assert(fw_handle >= 0); > > + igt_assert_lte(0, fw_handle); > > /* check if all gts are in C0 after forcewake is acquired */ > > xe_for_each_gt(fd, gt) > > igt_assert_f(!xe_is_gt_in_c6(fd, gt), > > diff --git a/tests/intel/xe_query.c b/tests/intel/xe_query.c > > index c13613e0a..c6d88b258 100644 > > --- a/tests/intel/xe_query.c > > +++ b/tests/intel/xe_query.c > > @@ -198,7 +198,7 @@ test_query_engines(int fd) > > hwe->gt_id); > > } > > > > - igt_assert(i > 0); > > + igt_assert_lt(0, i); > > } > > > > /** > > @@ -464,15 +464,15 @@ test_query_gt_topology_l3_bank_mask(int fd) > > > > igt_info(" count: %d\n", count); > > if (intel_get_device_info(dev_id)->graphics_ver < 20) { > > - igt_assert(count > 0); > > + igt_assert_lt(0, count); > > } > > > > if (IS_METEORLAKE(dev_id)) > > - igt_assert((count % 2) == 0); > > + igt_assert_eq((count % 2), 0); > > else if (IS_PONTEVECCHIO(dev_id)) > > - igt_assert((count % 4) == 0); > > + igt_assert_eq((count % 4), 0); > > else if (IS_DG2(dev_id)) > > - igt_assert((count % 8) == 0); > > + igt_assert_eq((count % 8), 0); > > } > > > > query.size -= sz; > > @@ -786,7 +786,7 @@ __engine_cycles(int fd, struct drm_xe_engine_class_instance *hwe) > > if (!((i + 1) % NUM_SNAPSHOTS)) { > > igt_debug("clock %s\n", clock[index].name); > > igt_debug("usable %d\n", usable); > > - igt_assert(usable > 2); > > + igt_assert_lt(2, usable); > > usable = 0; > > } > > } > > diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c > > index a4f6c7a0b..f20a1f474 100644 > > --- a/tests/intel/xe_vm.c > > +++ b/tests/intel/xe_vm.c > > @@ -408,7 +408,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo, > > int n_exec_queues = n_bo, n_execs = n_bo; > > int i, b; > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > bo = malloc(sizeof(*bo) * n_bo); > > igt_assert(bo); > > @@ -778,7 +778,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs, > > } *data; > > int i, b; > > > > - igt_assert(n_execs <= BIND_ARRAY_MAX_N_EXEC); > > + igt_assert_lte(n_execs, BIND_ARRAY_MAX_N_EXEC); > > > > vm = xe_vm_create(fd, 0, 0); > > bo_size = sizeof(*data) * n_execs; > > @@ -974,7 +974,7 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci, > > base_addr -= xe_get_default_alignment(fd); > > } > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > vm = xe_vm_create(fd, 0, 0); > > > > if (flags & LARGE_BIND_FLAG_USERPTR) { -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [i-g-t,2/2] tests/intel: Apply igt.cocci transforms 2024-07-31 16:26 ` Matt Roper @ 2024-08-01 10:19 ` Vivekanandan, Balasubramani 0 siblings, 0 replies; 12+ messages in thread From: Vivekanandan, Balasubramani @ 2024-08-01 10:19 UTC (permalink / raw) To: Matt Roper; +Cc: igt-dev On 31.07.2024 09:26, Matt Roper wrote: > On Wed, Jul 31, 2024 at 05:55:48PM +0530, Vivekanandan, Balasubramani wrote: > > On 29.07.2024 15:02, Matt Roper wrote: > > > A number of Intel tests are using checks like "igt_assert(x < y)" rather > > > than using the dedicated comparison assertions that print the actual > > > values on assertion failure. Run the Intel test directory through > > > Coccinelle to apply these conversions and also apply some other general > > > coding style cleanup: > > > > > > spatch --in-place --sp-file lib/igt.cocci tests/intel > > > > There are some places in the code, where still igt_assert is retained > > like these lines from file gem_ctx_create.c > > > > ``` > > shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > > igt_assert(shared != MAP_FAILED); > > ``` > > > > Are these unspotted by Coccinelle? > > Yeah, it looks like the comparison transform rules we have today only > apply to various integer types: > > @@ > typedef uint32_t; > uint32_t E1, E2; > int E3, E4; > @@ > ( > - igt_assert(E1 == E2); > + igt_assert_eq_u32(E1, E2); > | > - igt_assert(E1 != E2); > + igt_assert_neq_u32(E1, E2); > | > > mmap returns a pointer, so it isn't transformed by the current rules. > We could always extend the rules in the future to cover pointers as > well, although some cases like this specific example aren't terribly > important (since if we trip that assertion we do know the exact value of > 'shared' already. The integer comparisons are the ones where we get the > most benefit from being able to see the two sides of the comparison > after a failure. > > > Matt Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Regards, Bala > > > > > Regards, > > Bala > > > > > > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > > --- > > > tests/intel/api_intel_allocator.c | 12 ++--- > > > tests/intel/api_intel_bb.c | 18 +++---- > > > tests/intel/drm_fdinfo.c | 8 +-- > > > tests/intel/gem_blits.c | 16 +++--- > > > tests/intel/gem_ccs.c | 4 +- > > > tests/intel/gem_close_race.c | 2 +- > > > tests/intel/gem_concurrent_all.c | 8 +-- > > > tests/intel/gem_create.c | 2 +- > > > tests/intel/gem_ctx_create.c | 8 +-- > > > tests/intel/gem_ctx_exec.c | 4 +- > > > tests/intel/gem_ctx_persistence.c | 12 +++-- > > > tests/intel/gem_eio.c | 8 +-- > > > tests/intel/gem_exec_alignment.c | 6 ++- > > > tests/intel/gem_exec_big.c | 4 +- > > > tests/intel/gem_exec_capture.c | 8 +-- > > > tests/intel/gem_exec_fair.c | 32 +++++++----- > > > tests/intel/gem_exec_fence.c | 2 +- > > > tests/intel/gem_exec_gttfill.c | 4 +- > > > tests/intel/gem_exec_nop.c | 2 +- > > > tests/intel/gem_exec_reloc.c | 4 +- > > > tests/intel/gem_gtt_speed.c | 2 +- > > > tests/intel/gem_linear_blits.c | 6 +-- > > > tests/intel/gem_pread.c | 5 +- > > > tests/intel/gem_pwrite.c | 5 +- > > > tests/intel/gem_pxp.c | 16 +++--- > > > tests/intel/gem_reset_stats.c | 8 +-- > > > tests/intel/gem_softpin.c | 8 ++- > > > tests/intel/gem_tiled_blits.c | 6 +-- > > > tests/intel/gem_tiled_fence_blits.c | 4 +- > > > tests/intel/gem_userptr_blits.c | 4 +- > > > tests/intel/gem_wait.c | 8 +-- > > > tests/intel/gem_watchdog.c | 2 +- > > > tests/intel/i915_hangman.c | 2 +- > > > tests/intel/i915_module_load.c | 6 +-- > > > tests/intel/i915_pm_freq_api.c | 50 +++++++++--------- > > > tests/intel/i915_pm_rc6_residency.c | 4 +- > > > tests/intel/i915_pm_rps.c | 11 ++-- > > > tests/intel/i915_query.c | 12 ++--- > > > tests/intel/kms_big_fb.c | 2 +- > > > tests/intel/kms_busy.c | 2 +- > > > tests/intel/kms_ccs.c | 2 +- > > > tests/intel/kms_cdclk.c | 5 +- > > > tests/intel/kms_dsc_helper.c | 4 +- > > > tests/intel/kms_fbcon_fbt.c | 3 +- > > > tests/intel/kms_pm_dc.c | 9 ++-- > > > tests/intel/kms_pm_rpm.c | 2 +- > > > tests/intel/kms_psr.c | 18 +++---- > > > tests/intel/perf.c | 34 ++++++------ > > > tests/intel/perf_pmu.c | 37 +++++++------ > > > tests/intel/xe_ccs.c | 4 +- > > > tests/intel/xe_debugfs.c | 2 +- > > > tests/intel/xe_dma_buf_sync.c | 2 +- > > > tests/intel/xe_evict.c | 4 +- > > > tests/intel/xe_exec_balancer.c | 7 +-- > > > tests/intel/xe_exec_basic.c | 4 +- > > > tests/intel/xe_exec_compute_mode.c | 9 ++-- > > > tests/intel/xe_exec_fault_mode.c | 5 +- > > > tests/intel/xe_exec_reset.c | 8 +-- > > > tests/intel/xe_exec_store.c | 2 +- > > > tests/intel/xe_exec_threads.c | 11 ++-- > > > tests/intel/xe_gt_freq.c | 80 ++++++++++++++--------------- > > > tests/intel/xe_intel_bb.c | 16 +++--- > > > tests/intel/xe_oa.c | 26 +++++----- > > > tests/intel/xe_pat.c | 2 +- > > > tests/intel/xe_peer2peer.c | 2 +- > > > tests/intel/xe_pm.c | 16 +++--- > > > tests/intel/xe_pm_residency.c | 4 +- > > > tests/intel/xe_query.c | 12 ++--- > > > tests/intel/xe_vm.c | 6 +-- > > > 69 files changed, 335 insertions(+), 328 deletions(-) > > > > > > diff --git a/tests/intel/api_intel_allocator.c b/tests/intel/api_intel_allocator.c > > > index 9218be3b9..15ba4828c 100644 > > > --- a/tests/intel/api_intel_allocator.c > > > +++ b/tests/intel/api_intel_allocator.c > > > @@ -705,7 +705,7 @@ static void execbuf_with_allocator(int fd) > > > gem_close(fd, object[i].handle); > > > } > > > > > > - igt_assert(copied == magic); > > > + igt_assert_eq_u32(copied, magic); > > > igt_assert(intel_allocator_close(ahnd) == true); > > > } > > > > > > @@ -776,13 +776,13 @@ static void gem_pool(int i915) > > > bb[0] = single_exec_from_pool(i915, ahnd, 4096); > > > gem_sync(i915, bb[0]); > > > bb[1] = single_exec_from_pool(i915, ahnd, 4096); > > > - igt_assert(bb[0] == bb[1]); > > > + igt_assert_eq_u32(bb[0], bb[1]); > > > > > > bb[2] = single_exec_from_pool(i915, ahnd, 8192); > > > gem_sync(i915, bb[2]); > > > bb[3] = single_exec_from_pool(i915, ahnd, 8192); > > > - igt_assert(bb[2] == bb[3]); > > > - igt_assert(bb[0] != bb[2]); > > > + igt_assert_eq_u32(bb[2], bb[3]); > > > + igt_assert_neq_u32(bb[0], bb[2]); > > > > > > spin = igt_spin_new(i915, > > > .ahnd = ahnd, > > > @@ -792,8 +792,8 @@ static void gem_pool(int i915) > > > bb[2] = single_exec_from_pool(i915, ahnd, 8192); > > > bb[3] = single_exec_from_pool(i915, ahnd, 8192); > > > igt_spin_free(i915, spin); > > > - igt_assert(bb[0] != bb[1]); > > > - igt_assert(bb[2] != bb[3]); > > > + igt_assert_neq_u32(bb[0], bb[1]); > > > + igt_assert_neq_u32(bb[2], bb[3]); > > > > > > put_ahnd(ahnd); > > > > > > diff --git a/tests/intel/api_intel_bb.c b/tests/intel/api_intel_bb.c > > > index 6cb5d4f9e..db039dc3b 100644 > > > --- a/tests/intel/api_intel_bb.c > > > +++ b/tests/intel/api_intel_bb.c > > > @@ -1024,11 +1024,11 @@ static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling) > > > > > > /* We'll fail on src <-> final compare so just warn */ > > > if (tiling == I915_TILING_NONE) { > > > - if (compare_bufs(&src, &dst, false) > 0) > > > - igt_warn("none->none blit failed!"); > > > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > > > + "none->none blit failed!"); > > > } else { > > > - if (compare_bufs(&src, &dst, false) == 0) > > > - igt_warn("none->tiled blit failed!"); > > > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > > > + "none->tiled blit failed!"); > > > } > > > > > > fails = compare_bufs(&src, &final, true); > > > @@ -1367,11 +1367,11 @@ static int render(struct buf_ops *bops, uint32_t tiling, bool do_reloc, > > > > > > /* We'll fail on src <-> final compare so just warn */ > > > if (tiling == I915_TILING_NONE) { > > > - if (compare_bufs(&src, &dst, false) > 0) > > > - igt_warn("%s: none->none failed!\n", __func__); > > > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > > > + "%s: none->none failed!\n", __func__); > > > } else { > > > - if (compare_bufs(&src, &dst, false) == 0) > > > - igt_warn("%s: none->tiled failed!\n", __func__); > > > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > > > + "%s: none->tiled failed!\n", __func__); > > > } > > > > > > fails = compare_bufs(&src, &final, true); > > > @@ -1535,7 +1535,7 @@ static void test_crc32(int i915, const intel_ctx_t *ctx, > > > > > > put_offset(ahnd, data); > > > gem_close(i915, data); > > > - igt_assert(cpu_crc == gpu_crc); > > > + igt_assert_eq_u32(cpu_crc, gpu_crc); > > > } > > > > > > put_ahnd(ahnd); > > > diff --git a/tests/intel/drm_fdinfo.c b/tests/intel/drm_fdinfo.c > > > index a790f9255..160dc3d0a 100644 > > > --- a/tests/intel/drm_fdinfo.c > > > +++ b/tests/intel/drm_fdinfo.c > > > @@ -275,7 +275,7 @@ static void log_busy(unsigned int num_engines, uint64_t *val) > > > int len; > > > > > > len = snprintf(p, rem, "%u=%" PRIu64 "\n", i, val[i]); > > > - igt_assert(len > 0); > > > + igt_assert_lt(0, len); > > > rem -= len; > > > p += len; > > > } > > > @@ -805,7 +805,7 @@ static size_t read_fdinfo(char *buf, const size_t sz, int at, const char *name) > > > buf[count - 1] = 0; > > > close(fd); > > > > > > - return count > 0 ? count : 0; > > > + return max(count, 0); > > > } > > > > > > /* > > > @@ -855,7 +855,7 @@ test_memory(int i915, struct gem_memory_region *mr, unsigned int flags) > > > > > > gem_quiescent_gpu(i915); > > > ret = __igt_parse_drm_fdinfo(dir, buf, &info, NULL, 0, NULL, 0); > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > igt_require(info.num_regions); > > > memcpy(&prev_info, &info, sizeof(info)); > > > memcpy(&base_info, &info, sizeof(info)); > > > @@ -905,7 +905,7 @@ test_memory(int i915, struct gem_memory_region *mr, unsigned int flags) > > > ret = __igt_parse_drm_fdinfo(dir, buf, &info, > > > NULL, 0, > > > region_map, ARRAY_SIZE(region_map)); > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > igt_assert(info.num_regions); > > > > > > read_fdinfo(fdinfo_buf, sizeof(fdinfo_buf), dir, buf); > > > diff --git a/tests/intel/gem_blits.c b/tests/intel/gem_blits.c > > > index 5ca81fbfe..b2af48ef1 100644 > > > --- a/tests/intel/gem_blits.c > > > +++ b/tests/intel/gem_blits.c > > > @@ -267,7 +267,7 @@ static void buffer_set_tiling(const struct device *device, > > > batch[i++] = obj[1].offset >> 32; > > > > > > if ((tiling | buffer->tiling) >= T_YMAJOR) { > > > - igt_assert(device->gen >= 6); > > > + igt_assert_lte(6, device->gen); > > > batch[i++] = MI_FLUSH_DW_CMD | 2; > > > batch[i++] = 0; > > > batch[i++] = 0; > > > @@ -415,7 +415,7 @@ static bool blit_to_linear(const struct device *device, > > > batch[i++] = obj[1].offset >> 32; > > > > > > if (buffer->tiling >= T_YMAJOR) { > > > - igt_assert(device->gen >= 6); > > > + igt_assert_lte(6, device->gen); > > > batch[i++] = MI_FLUSH_DW_CMD | 2; > > > batch[i++] = 0; > > > batch[i++] = 0; > > > @@ -542,11 +542,9 @@ static bool buffer_check(const struct device *device, > > > continue; > > > > > > for (int x = 0; x < buffer->width; x++) { > > > - if (row[x] != model[x] && num_errors++ < 5) { > > > - igt_warn("buffer handle=%d mismatch at (%d, %d): expected %08x, found %08x\n", > > > - buffer->handle, > > > - x, y, model[x], row[x]); > > > - } > > > + igt_warn_on_f(row[x] != model[x] && num_errors++ < 5, > > > + "buffer handle=%d mismatch at (%d, %d): expected %08x, found %08x\n", > > > + buffer->handle, x, y, model[x], row[x]); > > > } > > > } > > > > > > @@ -664,7 +662,7 @@ blit(const struct device *device, > > > height = dst->height - dst_y; > > > > > > if (dst->caching) { > > > - igt_assert(device->gen >= 3); > > > + igt_assert_lte(3, device->gen); > > > igt_assert(device->llc || !src->caching); > > > } > > > > > > @@ -764,7 +762,7 @@ blit(const struct device *device, > > > batch[i++] = obj[1].offset >> 32; > > > > > > if ((src->tiling | dst->tiling) >= T_YMAJOR) { > > > - igt_assert(device->gen >= 6); > > > + igt_assert_lte(6, device->gen); > > > batch[i++] = MI_FLUSH_DW_CMD | 2; > > > batch[i++] = 0; > > > batch[i++] = 0; > > > diff --git a/tests/intel/gem_ccs.c b/tests/intel/gem_ccs.c > > > index 6ced67d7a..07aa6d322 100644 > > > --- a/tests/intel/gem_ccs.c > > > +++ b/tests/intel/gem_ccs.c > > > @@ -175,7 +175,7 @@ static void surf_copy(int i915, > > > gem_sync(i915, blt.dst.handle); > > > WRITE_PNG(i915, run_id, "corrupted", &blt.dst, dst->x2, dst->y2, bpp); > > > result = memcmp(src->ptr, dst->ptr, src->size); > > > - igt_assert(result != 0); > > > + igt_assert_neq(result, 0); > > > > > > /* retrieve back ccs */ > > > memcpy(ccsmap, ccscopy, ccssize); > > > @@ -601,7 +601,7 @@ static int opt_handler(int opt, int opt_index, void *data) > > > case 'f': > > > param.compression_format = atoi(optarg); > > > igt_debug("Compression format: %d\n", param.compression_format); > > > - igt_assert((param.compression_format & ~0x1f) == 0); > > > + igt_assert_eq((param.compression_format & ~0x1f), 0); > > > break; > > > case 'p': > > > param.write_png = true; > > > diff --git a/tests/intel/gem_close_race.c b/tests/intel/gem_close_race.c > > > index 9edcf13eb..c68e2fa73 100644 > > > --- a/tests/intel/gem_close_race.c > > > +++ b/tests/intel/gem_close_race.c > > > @@ -307,7 +307,7 @@ static void multigpu_threads(int timeout, unsigned int flags, int gpu_count) > > > struct drm_gem_open name; > > > int fd = __drm_open_driver_another(gpu, DRIVER_INTEL); > > > > > > - igt_assert(fd > 0); > > > + igt_assert_lt(0, fd); > > > > > > igt_fork(child, size) > > > thread(fd, name, timeout, flags); > > > diff --git a/tests/intel/gem_concurrent_all.c b/tests/intel/gem_concurrent_all.c > > > index dbb7622d3..acc6a230d 100644 > > > --- a/tests/intel/gem_concurrent_all.c > > > +++ b/tests/intel/gem_concurrent_all.c > > > @@ -306,7 +306,7 @@ userptr_create_bo(const struct buffers *b) > > > igt_assert(ptr != (void *)-1); > > > userptr.user_ptr = to_user_pointer(ptr); > > > > > > - do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr)); > > > + do_ioctl(fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr); > > > buf = intel_buf_create_using_handle_and_size(b->bops, userptr.handle, > > > b->width, b->height, 32, 0, > > > I915_TILING_NONE, 0, > > > @@ -497,7 +497,7 @@ vgem_create_bo(const struct buffers *b) > > > struct dmabuf *dmabuf; > > > uint32_t handle; > > > > > > - igt_assert(vgem_drv != -1); > > > + igt_assert_neq(vgem_drv, -1); > > > > > > vgem.width = b->width; > > > vgem.height = b->height; > > > @@ -915,7 +915,7 @@ static void buffers_create(struct buffers *b) > > > igt_assert(b->bops); > > > > > > buffers_destroy(b); > > > - igt_assert(b->count == 0); > > > + igt_assert_eq(b->count, 0); > > > b->count = count; > > > > > > ahnd = alloc_open(); > > > @@ -941,7 +941,7 @@ static void __buffers_create(struct buffers *b) > > > { > > > b->bops = buf_ops_create(fd); > > > igt_assert(b->bops); > > > - igt_assert(b->num_buffers > 0); > > > + igt_assert_lt(0, b->num_buffers); > > > igt_assert(b->mode); > > > igt_assert(b->mode->create_bo); > > > > > > diff --git a/tests/intel/gem_create.c b/tests/intel/gem_create.c > > > index 26cd6e32e..ca39a8b64 100644 > > > --- a/tests/intel/gem_create.c > > > +++ b/tests/intel/gem_create.c > > > @@ -637,7 +637,7 @@ static void create_ext_set_pat(int fd) > > > * This means that we are on a Meteor Lake and the PAT > > > * index is already supported by the running i915 > > > */ > > > - igt_assert(ret == 0); > > > + igt_assert_eq(ret, 0); > > > > > > /* > > > * {set|get}_caching ioctl should fail for objects created with set_pat > > > diff --git a/tests/intel/gem_ctx_create.c b/tests/intel/gem_ctx_create.c > > > index 6afb10a7b..0332ecbb9 100644 > > > --- a/tests/intel/gem_ctx_create.c > > > +++ b/tests/intel/gem_ctx_create.c > > > @@ -297,18 +297,14 @@ static void xchg_u32(void *array, unsigned i, unsigned j) > > > { > > > uint32_t *a = array, tmp; > > > > > > - tmp = a[i]; > > > - a[i] = a[j]; > > > - a[j] = tmp; > > > + igt_swap(a[i], a[j]); > > > } > > > > > > static void xchg_ptr(void *array, unsigned i, unsigned j) > > > { > > > void **a = array, *tmp; > > > > > > - tmp = a[i]; > > > - a[i] = a[j]; > > > - a[j] = tmp; > > > + igt_swap(a[i], a[j]); > > > } > > > > > > static unsigned __context_size(int fd) > > > diff --git a/tests/intel/gem_ctx_exec.c b/tests/intel/gem_ctx_exec.c > > > index f3e252d10..a45a7e378 100644 > > > --- a/tests/intel/gem_ctx_exec.c > > > +++ b/tests/intel/gem_ctx_exec.c > > > @@ -346,7 +346,7 @@ static void nohangcheck_hostile(int i915) > > > IGT_SPIN_FENCE_OUT)); > > > > > > new = fill_ring(i915, &spin->execbuf); > > > - igt_assert(new != -1); > > > + igt_assert_neq(new, -1); > > > spin->out_fence = -1; > > > > > > if (fence < 0) { > > > @@ -362,7 +362,7 @@ static void nohangcheck_hostile(int i915) > > > } > > > } > > > intel_ctx_destroy(i915, ctx); > > > - igt_assert(fence != -1); > > > + igt_assert_neq(fence, -1); > > > > > > err = 0; > > > if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */ > > > diff --git a/tests/intel/gem_ctx_persistence.c b/tests/intel/gem_ctx_persistence.c > > > index 90c1e0112..8d4a874d4 100644 > > > --- a/tests/intel/gem_ctx_persistence.c > > > +++ b/tests/intel/gem_ctx_persistence.c > > > @@ -1093,10 +1093,12 @@ static void test_processes(int i915) > > > > > > /* Wait until we are told to die */ > > > pid = getpid(); > > > - write(p[i].sv[0], &pid, sizeof(pid)); > > > + igt_assert_eq(write(p[i].sv[0], &pid, sizeof(pid)), > > > + sizeof(pid)); > > > > > > pid = 0; > > > - read(p[i].sv[0], &pid, sizeof(pid)); > > > + igt_assert_eq(read(p[i].sv[0], &pid, sizeof(pid)), > > > + sizeof(pid)); > > > igt_assert(pid == getpid()); > > > } > > > } > > > @@ -1109,8 +1111,10 @@ static void test_processes(int i915) > > > igt_assert_eq(sync_fence_wait(fence, 0), -ETIME); > > > > > > /* Kill *this* process */ > > > - read(p[i].sv[1], &pid, sizeof(pid)); > > > - write(p[i].sv[1], &pid, sizeof(pid)); > > > + igt_assert_eq(read(p[i].sv[1], &pid, sizeof(pid)), > > > + sizeof(pid)); > > > + igt_assert_eq(write(p[i].sv[1], &pid, sizeof(pid)), > > > + sizeof(pid)); > > > > > > /* > > > * A little bit of slack required for the signal to terminate > > > diff --git a/tests/intel/gem_eio.c b/tests/intel/gem_eio.c > > > index dc6178d63..b65b914fa 100644 > > > --- a/tests/intel/gem_eio.c > > > +++ b/tests/intel/gem_eio.c > > > @@ -627,7 +627,7 @@ static void test_inflight(int fd, unsigned int wait) > > > for (unsigned int n = 0; n < max; n++) { > > > gem_execbuf_wr(fd, &execbuf); > > > fence[n] = execbuf.rsvd2 >> 32; > > > - igt_assert(fence[n] != -1); > > > + igt_assert_neq(fence[n], -1); > > > } > > > > > > igt_debugfs_dump(fd, "i915_engine_info"); > > > @@ -687,7 +687,7 @@ static void test_inflight_suspend(int fd) > > > for (unsigned int n = 0; n < max; n++) { > > > gem_execbuf_wr(fd, &execbuf); > > > fence[n] = execbuf.rsvd2 >> 32; > > > - igt_assert(fence[n] != -1); > > > + igt_assert_neq(fence[n], -1); > > > } > > > > > > igt_set_autoresume_delay(30); > > > @@ -774,7 +774,7 @@ static void test_inflight_contexts(int fd, unsigned int wait) > > > if (__gem_execbuf_wr(fd, &execbuf)) > > > break; /* small shared ring */ > > > fence[n] = execbuf.rsvd2 >> 32; > > > - igt_assert(fence[n] != -1); > > > + igt_assert_neq(fence[n], -1); > > > count++; > > > } > > > > > > @@ -885,7 +885,7 @@ static void test_inflight_internal(int fd, unsigned int wait) > > > gem_execbuf_wr(fd, &execbuf); > > > > > > fences[nfence] = execbuf.rsvd2 >> 32; > > > - igt_assert(fences[nfence] != -1); > > > + igt_assert_neq(fences[nfence], -1); > > > nfence++; > > > } > > > > > > diff --git a/tests/intel/gem_exec_alignment.c b/tests/intel/gem_exec_alignment.c > > > index 7b51b7af0..6a9905d95 100644 > > > --- a/tests/intel/gem_exec_alignment.c > > > +++ b/tests/intel/gem_exec_alignment.c > > > @@ -302,7 +302,8 @@ static void prio_inversion(int i915, unsigned int flags) > > > naughty_child(i915, link[1], obj.handle, flags); > > > > > > igt_debug("Waiting for naughty client\n"); > > > - read(link[0], &elapsed, sizeof(elapsed)); > > > + igt_assert_eq(read(link[0], &elapsed, sizeof(elapsed)), > > > + sizeof(elapsed)); > > > igt_debug("Ready...\n"); > > > usleep(250 * 1000); /* let the naughty execbuf begin */ > > > igt_debug("Go!\n"); > > > @@ -331,7 +332,8 @@ static void prio_inversion(int i915, unsigned int flags) > > > igt_waitchildren(); > > > gem_close(i915, obj.handle); > > > > > > - read(link[0], &naughty, sizeof(naughty)); > > > + igt_assert_eq(read(link[0], &naughty, sizeof(naughty)), > > > + sizeof(naughty)); > > > igt_info("Naughty client took %'"PRIu64"ns\n", naughty); > > > > > > igt_assert(elapsed < naughty / 2); > > > diff --git a/tests/intel/gem_exec_big.c b/tests/intel/gem_exec_big.c > > > index 7bd91c2a0..86849f322 100644 > > > --- a/tests/intel/gem_exec_big.c > > > +++ b/tests/intel/gem_exec_big.c > > > @@ -143,9 +143,7 @@ static void xchg_reloc(void *array, unsigned i, unsigned j) > > > struct drm_i915_gem_relocation_entry *b = &reloc[j]; > > > struct drm_i915_gem_relocation_entry tmp; > > > > > > - tmp = *a; > > > - *a = *b; > > > - *b = tmp; > > > + igt_swap(*a, *b); > > > } > > > > > > static void execN(int fd, uint32_t handle, uint64_t batch_size, unsigned flags, char *ptr) > > > diff --git a/tests/intel/gem_exec_capture.c b/tests/intel/gem_exec_capture.c > > > index 720ff796d..2340ad495 100644 > > > --- a/tests/intel/gem_exec_capture.c > > > +++ b/tests/intel/gem_exec_capture.c > > > @@ -406,7 +406,7 @@ static void __capture1(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx, > > > gem_execbuf_wr(fd, &execbuf); > > > > > > fence_out = execbuf.rsvd2 >> 32; > > > - igt_assert(fence_out >= 0); > > > + igt_assert_lte(0, fence_out); > > > > > > /* Wait for the request to start */ > > > while (READ_ONCE(*seqno) != 0xc0ffee) > > > @@ -792,11 +792,11 @@ static void prioinv(int fd, int dir, const intel_ctx_t *ctx, > > > &fence_out, REGION_SMEM, true)); > > > put_ahnd(ahnd); > > > > > > - write(link[1], &fd, sizeof(fd)); /* wake the parent up */ > > > + igt_assert_eq(write(link[1], &fd, sizeof(fd)), sizeof(fd)); /* wake the parent up */ > > > wait_to_die(fence_out); > > > - write(link[1], &fd, sizeof(fd)); /* wake the parent up */ > > > + igt_assert_eq(write(link[1], &fd, sizeof(fd)), sizeof(fd)); /* wake the parent up */ > > > } > > > - read(link[0], &dummy, sizeof(dummy)); > > > + igt_assert_eq(read(link[0], &dummy, sizeof(dummy)), sizeof(dummy)); > > > igt_require_f(poll(&(struct pollfd){link[0], POLLIN}, 1, 500) == 0, > > > "Capture completed too quickly! Will not block\n"); > > > > > > diff --git a/tests/intel/gem_exec_fair.c b/tests/intel/gem_exec_fair.c > > > index 2f7ef3800..19df66921 100644 > > > --- a/tests/intel/gem_exec_fair.c > > > +++ b/tests/intel/gem_exec_fair.c > > > @@ -579,10 +579,12 @@ static void fair_child(int i915, const intel_ctx_t *ctx, > > > > > > /* Synchronize with other children/parent upon construction */ > > > if (sv != -1) > > > - write(sv, &p_fence, sizeof(p_fence)); > > > + igt_assert_eq(write(sv, &p_fence, sizeof(p_fence)), > > > + sizeof(p_fence)); > > > if (rv != -1) > > > - read(rv, &p_fence, sizeof(p_fence)); > > > - igt_assert(p_fence == -1); > > > + igt_assert_eq(read(rv, &p_fence, sizeof(p_fence)), > > > + sizeof(p_fence)); > > > + igt_assert_eq(p_fence, -1); > > > > > > aux_flags = 0; > > > if (intel_gen(intel_get_drm_devid(i915)) < 8) > > > @@ -850,9 +852,11 @@ static void fairness(int i915, const intel_ctx_cfg_t *cfg, > > > { > > > int sync; > > > for (int child = 0; child < nchild; child++) > > > - read(lnk.child[0], &sync, sizeof(sync)); > > > + igt_assert_eq(read(lnk.child[0], &sync, sizeof(sync)), > > > + sizeof(sync)); > > > for (int child = 0; child < nchild; child++) > > > - write(lnk.parent[1], &sync, sizeof(sync)); > > > + igt_assert_eq(write(lnk.parent[1], &sync, sizeof(sync)), > > > + sizeof(sync)); > > > } > > > > > > while (nfences--) > > > @@ -1028,9 +1032,9 @@ static void deadline_child(int i915, > > > if (!(flags & DL_PRIO)) > > > execbuf.flags |= I915_EXEC_FENCE_IN; > > > > > > - write(sv, &prev, sizeof(int)); > > > - read(rv, &prev, sizeof(int)); > > > - igt_assert(prev == -1); > > > + igt_assert_eq(write(sv, &prev, sizeof(int)), sizeof(int)); > > > + igt_assert_eq(read(rv, &prev, sizeof(int)), sizeof(int)); > > > + igt_assert_eq(prev, -1); > > > > > > prev = execbuf.rsvd2; > > > next = execbuf.rsvd2 >> 32; > > > @@ -1044,7 +1048,8 @@ static void deadline_child(int i915, > > > gem_execbuf_wr(i915, &execbuf); > > > close(execbuf.rsvd2); > > > > > > - write(sv, &fence.handle, sizeof(uint32_t)); > > > + igt_assert_eq(write(sv, &fence.handle, sizeof(uint32_t)), > > > + sizeof(uint32_t)); > > > > > > prev = next; > > > next = execbuf.rsvd2 >> 32; > > > @@ -1187,10 +1192,12 @@ static void deadline(int i915, const intel_ctx_cfg_t *cfg, > > > } > > > > > > for (int i = 0; i < num_children; i++) > > > - read(link[i].child[0], &over, sizeof(int)); > > > + igt_assert_eq(read(link[i].child[0], &over, sizeof(int)), > > > + sizeof(int)); > > > igt_info("Testing %d children, with %'dns\n", num_children, child_ns); > > > for (int i = 0; i < num_children; i++) > > > - write(link[i].parent[1], &over, sizeof(int)); > > > + igt_assert_eq(write(link[i].parent[1], &over, sizeof(int)), > > > + sizeof(int)); > > > > > > over = 0; > > > missed = 0; > > > @@ -1207,7 +1214,8 @@ static void deadline(int i915, const intel_ctx_cfg_t *cfg, > > > > > > sw_sync_timeline_inc(timeline, 1); > > > for (int i = 0; i < num_children; i++) { > > > - read(link[i].child[0], &fences[i].handle, sizeof(uint32_t)); > > > + igt_assert_eq(read(link[i].child[0], &fences[i].handle, sizeof(uint32_t)), > > > + sizeof(uint32_t)); > > > fences[i].flags = I915_EXEC_FENCE_WAIT; > > > } > > > > > > diff --git a/tests/intel/gem_exec_fence.c b/tests/intel/gem_exec_fence.c > > > index a313c31f2..7f39c73d7 100644 > > > --- a/tests/intel/gem_exec_fence.c > > > +++ b/tests/intel/gem_exec_fence.c > > > @@ -366,7 +366,7 @@ static void test_fence_busy_all(int fd, const intel_ctx_t *ctx, unsigned flags) > > > execbuf.rsvd2 = -1; > > > gem_execbuf_wr(fd, &execbuf); > > > fence = execbuf.rsvd2 >> 32; > > > - igt_assert(fence != -1); > > > + igt_assert_neq(fence, -1); > > > > > > if (all < 0) { > > > all = fence; > > > diff --git a/tests/intel/gem_exec_gttfill.c b/tests/intel/gem_exec_gttfill.c > > > index 096681740..ff600e0ca 100644 > > > --- a/tests/intel/gem_exec_gttfill.c > > > +++ b/tests/intel/gem_exec_gttfill.c > > > @@ -66,9 +66,7 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) > > > struct batch *batches = array; > > > struct batch tmp; > > > > > > - tmp = batches[i]; > > > - batches[i] = batches[j]; > > > - batches[j] = tmp; > > > + igt_swap(batches[i], batches[j]); > > > } > > > > > > static void submit(int fd, uint64_t ahnd, unsigned int gen, > > > diff --git a/tests/intel/gem_exec_nop.c b/tests/intel/gem_exec_nop.c > > > index fb37cb511..1b20cc870 100644 > > > --- a/tests/intel/gem_exec_nop.c > > > +++ b/tests/intel/gem_exec_nop.c > > > @@ -415,7 +415,7 @@ stable_nop_on_ring(int fd, uint32_t handle, const intel_ctx_t *ctx, > > > igt_stats_t s; > > > double n; > > > > > > - igt_assert(reps >= 5); > > > + igt_assert_lte(5, reps); > > > > > > igt_stats_init_with_size(&s, reps); > > > s.is_float = true; > > > diff --git a/tests/intel/gem_exec_reloc.c b/tests/intel/gem_exec_reloc.c > > > index d8013ccfc..44c09c3e2 100644 > > > --- a/tests/intel/gem_exec_reloc.c > > > +++ b/tests/intel/gem_exec_reloc.c > > > @@ -1343,7 +1343,7 @@ static void concurrent_child(int i915, const intel_ctx_t *ctx, > > > x += idx * CONCURRENT; > > > > > > do { > > > - read(in, batch, sizeof(*batch)); > > > + igt_assert_eq(read(in, batch, sizeof(*batch)), sizeof(*batch)); > > > if (!*batch) > > > break; > > > > > > @@ -1359,7 +1359,7 @@ static void concurrent_child(int i915, const intel_ctx_t *ctx, > > > } > > > } > > > > > > - write(out, &err, sizeof(err)); > > > + igt_assert_eq(write(out, &err, sizeof(err)), sizeof(err)); > > > count++; > > > } while (err == 0); > > > > > > diff --git a/tests/intel/gem_gtt_speed.c b/tests/intel/gem_gtt_speed.c > > > index 996e54af0..0f4e174d2 100644 > > > --- a/tests/intel/gem_gtt_speed.c > > > +++ b/tests/intel/gem_gtt_speed.c > > > @@ -70,7 +70,7 @@ static void streaming_load(void *src, int len) > > > { > > > __m128i tmp, *s = src; > > > > > > - igt_assert((len & 15) == 0); > > > + igt_assert_eq((len & 15), 0); > > > igt_assert((((uintptr_t)src) & 15) == 0); > > > > > > while (len >= 16) { > > > diff --git a/tests/intel/gem_linear_blits.c b/tests/intel/gem_linear_blits.c > > > index 2eeec5b6a..b6c0b13ac 100644 > > > --- a/tests/intel/gem_linear_blits.c > > > +++ b/tests/intel/gem_linear_blits.c > > > @@ -212,9 +212,9 @@ check_bo(int fd, uint32_t handle, uint32_t val) > > > > > > num_errors = 0; > > > for (i = 0; i < WIDTH*HEIGHT; i++) { > > > - if (linear[i] != val && num_errors++ < 32) > > > - igt_warn("[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > > > - i * 4, val, linear[i], val ^ linear[i]); > > > + igt_warn_on_f(linear[i] != val && num_errors++ < 32, > > > + "[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > > > + i * 4, val, linear[i], val ^ linear[i]); > > > val++; > > > } > > > igt_assert_eq(num_errors, 0); > > > diff --git a/tests/intel/gem_pread.c b/tests/intel/gem_pread.c > > > index e5e662361..70a38e75c 100644 > > > --- a/tests/intel/gem_pread.c > > > +++ b/tests/intel/gem_pread.c > > > @@ -151,7 +151,7 @@ static void write_value(const char *path, int value) > > > > > > fd = open(path, O_WRONLY); > > > if (fd != -1) { > > > - write(fd, buf, len); > > > + igt_assert_eq(write(fd, buf, len), len); > > > close(fd); > > > } > > > } > > > @@ -223,8 +223,7 @@ static void test_exhaustion(int i915) > > > count++; > > > } > > > igt_assert(count); > > > - if (t.err) > > > - igt_warn("err:%d after %lu threads\n", t.err, count); > > > + igt_warn_on_f(t.err, "err:%d after %lu threads\n", t.err, count); > > > > > > /* Service the fault; releasing the stuck ioctls */ > > > memset(©, 0, sizeof(copy)); > > > diff --git a/tests/intel/gem_pwrite.c b/tests/intel/gem_pwrite.c > > > index 025684a33..05a47b7b1 100644 > > > --- a/tests/intel/gem_pwrite.c > > > +++ b/tests/intel/gem_pwrite.c > > > @@ -425,7 +425,7 @@ static void write_value(const char *path, int value) > > > > > > fd = open(path, O_WRONLY); > > > if (fd != -1) { > > > - write(fd, buf, len); > > > + igt_assert_eq(write(fd, buf, len), len); > > > close(fd); > > > } > > > } > > > @@ -497,8 +497,7 @@ static void test_exhaustion(int i915) > > > count++; > > > } > > > igt_assert(count); > > > - if (t.err) > > > - igt_warn("err:%d after %lu threads\n", t.err, count); > > > + igt_warn_on_f(t.err, "err:%d after %lu threads\n", t.err, count); > > > > > > /* Service the fault; releasing the stuck ioctls */ > > > memset(©, 0, sizeof(copy)); > > > diff --git a/tests/intel/gem_pxp.c b/tests/intel/gem_pxp.c > > > index 6be19318a..e2c12df17 100644 > > > --- a/tests/intel/gem_pxp.c > > > +++ b/tests/intel/gem_pxp.c > > > @@ -811,7 +811,7 @@ static void test_pxp_dmabuffshare_refcnt(int i915) > > > for (n = 0; n < (TSTSURF_SIZE/4); ++n) > > > if (encrypted[0][n] == encrypted[1][n]) > > > ++num_matches; > > > - igt_assert(num_matches == (TSTSURF_SIZE/4)); > > > + igt_assert_eq(num_matches, (TSTSURF_SIZE / 4)); > > > } > > > > > > > > > @@ -988,7 +988,7 @@ static void test_pxp_stale_ctx_execution(int i915) > > > */ > > > prepare_exec_assets(i915, &data, true, false); > > > ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); > > > - igt_assert(ret == 0); > > > + igt_assert_eq(ret, 0); > > > > > > trigger_pxp_debugfs_forced_teardown(i915); > > > > > > @@ -1008,7 +1008,7 @@ static void test_pxp_stale_buf_execution(int i915) > > > /* Use pxp buffers with pxp context for testing for invalidation of protected buffers. */ > > > prepare_exec_assets(i915, &data, true, true); > > > ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); > > > - igt_assert(ret == 0); > > > + igt_assert_eq(ret, 0); > > > > > > trigger_pxp_debugfs_forced_teardown(i915); > > > > > > @@ -1055,7 +1055,7 @@ static void test_pxp_stale_buf_optout_execution(int i915) > > > * the intent of the subtest) to ensure ARB session is alive. > > > */ > > > ret = create_ctx_with_params(i915, true, true, true, false, &tmpctx); > > > - igt_assert(ret == 0); > > > + igt_assert_eq(ret, 0); > > > > > > /* > > > * Use a normal context for testing opt-out behavior > > > @@ -1063,7 +1063,7 @@ static void test_pxp_stale_buf_optout_execution(int i915) > > > */ > > > prepare_exec_assets(i915, &data, false, true); > > > ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf); > > > - igt_assert(ret == 0); > > > + igt_assert_eq(ret, 0); > > > > > > trigger_pxp_debugfs_forced_teardown(i915); > > > > > > @@ -1088,7 +1088,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat > > > */ > > > prepare_exec_assets(i915, &data[0], true, false); > > > ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf); > > > - igt_assert(ret == 0); > > > + igt_assert_eq(ret, 0); > > > > > > /* > > > * For asset data[1]: Use pxp buffers with pxp context for testing for invalidation > > > @@ -1096,7 +1096,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat > > > */ > > > prepare_exec_assets(i915, &data[1], true, true); > > > ret = gem_execbuf_flush_store_dw(i915, data[1].ibb, data[1].ctx, data[1].fencebuf); > > > - igt_assert(ret == 0); > > > + igt_assert_eq(ret, 0); > > > > > > /* > > > * For asset data[2]: Use a normal context for testing opt-out behavior > > > @@ -1104,7 +1104,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat > > > */ > > > prepare_exec_assets(i915, &data[2], false, true); > > > ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf); > > > - igt_assert(ret == 0); > > > + igt_assert_eq(ret, 0); > > > > > > /* Do an S3 suspend resume cycle which also causes the pxp teardown event */ > > > trigger_powermgt_suspend_cycle(i915, pm); > > > diff --git a/tests/intel/gem_reset_stats.c b/tests/intel/gem_reset_stats.c > > > index 91bec96c0..8c74ce28c 100644 > > > --- a/tests/intel/gem_reset_stats.c > > > +++ b/tests/intel/gem_reset_stats.c > > > @@ -315,7 +315,7 @@ static int noop(int fd, uint32_t ctx, const struct intel_execution_ring *e) > > > > > > memset(&exec, 0, sizeof(exec)); > > > exec.handle = gem_create(fd, 4096); > > > - igt_assert((int)exec.handle > 0); > > > + igt_assert_lt(0, (int)exec.handle); > > > gem_write(fd, exec.handle, 0, &bbe, sizeof(bbe)); > > > > > > memset(&eb, 0, sizeof(eb)); > > > @@ -457,7 +457,7 @@ static void test_rs(const struct intel_execution_ring *e, > > > if (i == hang_index) > > > inject_hang(fd[i], 0, e, ASYNC); > > > else > > > - igt_assert(noop(fd[i], 0, e) > 0); > > > + igt_assert_lt(0, noop(fd[i], 0, e)); > > > } > > > sync_gpu(); > > > > > > @@ -524,7 +524,7 @@ static void test_rs_ctx(const struct intel_execution_ring *e, > > > if (i == hang_index && j == hang_context) > > > inject_hang(fd[i], ctx[i][j], e, ASYNC); > > > else > > > - igt_assert(noop(fd[i], ctx[i][j], e) > 0); > > > + igt_assert_lt(0, noop(fd[i], ctx[i][j], e)); > > > } > > > } > > > sync_gpu(); > > > @@ -876,7 +876,7 @@ static void _check_param_ctx(const int fd, const int ctx, const cap_t cap) > > > igt_assert_eq(_test_params(fd, ctx, 0, 0), 0); > > > > > > if (cap != root) { > > > - igt_assert(get_reset_count(fd, ctx) == 0); > > > + igt_assert_eq(get_reset_count(fd, ctx), 0); > > > } > > > } > > > > > > diff --git a/tests/intel/gem_softpin.c b/tests/intel/gem_softpin.c > > > index b7c1b34e1..c542bf741 100644 > > > --- a/tests/intel/gem_softpin.c > > > +++ b/tests/intel/gem_softpin.c > > > @@ -793,7 +793,7 @@ static void __reserve(uint64_t ahnd, int i915, bool pinned, > > > unsigned int flags; > > > int i; > > > > > > - igt_assert(num_obj > 1); > > > + igt_assert_lt(1, num_obj); > > > > > > flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > > if (pinned) > > > @@ -843,7 +843,7 @@ static void __exec_using_allocator(uint64_t ahnd, int i915, int num_obj, > > > uint64_t sz = 4096; > > > int i; > > > > > > - igt_assert(num_obj > 10); > > > + igt_assert_lt(10, num_obj); > > > > > > flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > > if (pinned) > > > @@ -969,9 +969,7 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) > > > struct batch *batches = array; > > > struct batch tmp; > > > > > > - tmp = batches[i]; > > > - batches[i] = batches[j]; > > > - batches[j] = tmp; > > > + igt_swap(batches[i], batches[j]); > > > } > > > > > > static void submit(int fd, unsigned int gen, > > > diff --git a/tests/intel/gem_tiled_blits.c b/tests/intel/gem_tiled_blits.c > > > index 6fcc8616e..d8e80ca60 100644 > > > --- a/tests/intel/gem_tiled_blits.c > > > +++ b/tests/intel/gem_tiled_blits.c > > > @@ -129,9 +129,9 @@ check_bo(struct intel_buf *buf, uint32_t val, struct intel_bb *ibb) > > > linear = intel_buf_cpu_map(linear_buf, 0); > > > num_errors = 0; > > > for (i = 0; i < width * height; i++) { > > > - if (linear[i] != val && num_errors++ < 32) > > > - igt_warn("[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > > > - i * 4, val, linear[i], val ^ linear[i]); > > > + igt_warn_on_f(linear[i] != val && num_errors++ < 32, > > > + "[%08x] Expected 0x%08x, found 0x%08x (difference 0x%08x)\n", > > > + i * 4, val, linear[i], val ^ linear[i]); > > > val++; > > > } > > > igt_assert_eq(num_errors, 0); > > > diff --git a/tests/intel/gem_tiled_fence_blits.c b/tests/intel/gem_tiled_fence_blits.c > > > index 5e5bc6939..f5a3d9311 100644 > > > --- a/tests/intel/gem_tiled_fence_blits.c > > > +++ b/tests/intel/gem_tiled_fence_blits.c > > > @@ -158,9 +158,7 @@ static void xchg_u32(void *array, unsigned i, unsigned j) > > > { > > > uint32_t tmp, *base = array; > > > > > > - tmp = base[i]; > > > - base[i] = base[j]; > > > - base[j] = tmp; > > > + igt_swap(base[i], base[j]); > > > } > > > > > > static void run_test(int fd, int count, uint64_t end) > > > diff --git a/tests/intel/gem_userptr_blits.c b/tests/intel/gem_userptr_blits.c > > > index 807c209e8..67283c182 100644 > > > --- a/tests/intel/gem_userptr_blits.c > > > +++ b/tests/intel/gem_userptr_blits.c > > > @@ -814,7 +814,7 @@ static void test_nohangcheck_hostile(int i915) > > > IGT_SPIN_FENCE_OUT)); > > > > > > new = fill_ring(i915, &spin->execbuf); > > > - igt_assert(new != -1); > > > + igt_assert_neq(new, -1); > > > spin->out_fence = -1; > > > > > > if (fence < 0) { > > > @@ -831,7 +831,7 @@ static void test_nohangcheck_hostile(int i915) > > > } > > > intel_ctx_destroy(i915, ctx); > > > put_ahnd(ahnd); > > > - igt_assert(fence != -1); > > > + igt_assert_neq(fence, -1); > > > > > > if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */ > > > igt_debugfs_dump(i915, "i915_engine_info"); > > > diff --git a/tests/intel/gem_wait.c b/tests/intel/gem_wait.c > > > index 7a353a11e..9265d1d7a 100644 > > > --- a/tests/intel/gem_wait.c > > > +++ b/tests/intel/gem_wait.c > > > @@ -167,9 +167,11 @@ static void basic(int fd, const intel_ctx_t *ctx, unsigned engine, > > > igt_seconds_elapsed(&tv) < timeout) > > > ; > > > > > > - if ((flags & HANG) == 0 && !timespec_isset(&spin->last_signal)) > > > - igt_warn("spinner not terminated, expired? %d!\n", > > > - poll(&(struct pollfd){ spin->timerfd, POLLIN }, 1, 0)); > > > + igt_warn_on_f((flags & HANG) == 0 && !timespec_isset(&spin->last_signal), > > > + "spinner not terminated, expired? %d!\n", poll(&(struct pollfd){ > > > + spin->timerfd, > > > + POLLIN, > > > + }, 1, 0)); > > > > > > igt_assert_eq(__gem_wait(fd, &wait), 0); > > > } else { > > > diff --git a/tests/intel/gem_watchdog.c b/tests/intel/gem_watchdog.c > > > index 3d2fd68a8..1edde8b3c 100644 > > > --- a/tests/intel/gem_watchdog.c > > > +++ b/tests/intel/gem_watchdog.c > > > @@ -500,7 +500,7 @@ far_delay(int i915, unsigned long delay, unsigned int target, > > > batch[1] = batch[0]; > > > batch[1].flags &= ~EXEC_OBJECT_WRITE; > > > batch[0].handle = handle; > > > - assert(batch[0].flags & EXEC_OBJECT_WRITE); > > > + igt_assert(batch[0].flags & EXEC_OBJECT_WRITE); > > > gem_execbuf_wr(i915, &execbuf); > > > > > > gem_close(i915, obj.handle); > > > diff --git a/tests/intel/i915_hangman.c b/tests/intel/i915_hangman.c > > > index f100118b6..a556eec53 100644 > > > --- a/tests/intel/i915_hangman.c > > > +++ b/tests/intel/i915_hangman.c > > > @@ -470,7 +470,7 @@ static void test_hang_detector(const intel_ctx_t *ctx, > > > igt_stop_hang_detector(); > > > > > > /* Did it work? */ > > > - igt_assert(hang_count == 1); > > > + igt_assert_eq(hang_count, 1); > > > > > > check_alive(); > > > } > > > diff --git a/tests/intel/i915_module_load.c b/tests/intel/i915_module_load.c > > > index e3e4470df..cd1ee6d10 100644 > > > --- a/tests/intel/i915_module_load.c > > > +++ b/tests/intel/i915_module_load.c > > > @@ -230,7 +230,7 @@ inject_fault(const char *module_name, const char *opt, int fault) > > > char buf[1024]; > > > int dir; > > > > > > - igt_assert(fault > 0); > > > + igt_assert_lt(0, fault); > > > snprintf(buf, sizeof(buf), "%s=%d", opt, fault); > > > > > > if (igt_kmod_load(module_name, buf)) { > > > @@ -343,8 +343,8 @@ static uint32_t driver_load_with_lmem_bar_size(uint32_t lmem_bar_size, bool che > > > char *tmp; > > > > > > tmp = __igt_params_get(i915, "lmem_bar_size"); > > > - if (!tmp) > > > - igt_skip("lmem_bar_size modparam not supported on this kernel. Skipping the test.\n"); > > > + igt_skip_on_f(!tmp, > > > + "lmem_bar_size modparam not supported on this kernel. Skipping the test.\n"); > > > free(tmp); > > > } > > > > > > diff --git a/tests/intel/i915_pm_freq_api.c b/tests/intel/i915_pm_freq_api.c > > > index 2a3da6f4a..f2106cd3e 100644 > > > --- a/tests/intel/i915_pm_freq_api.c > > > +++ b/tests/intel/i915_pm_freq_api.c > > > @@ -61,34 +61,34 @@ static void test_freq_basic_api(int dirfd, int gt) > > > igt_debug("GT: %d, RPn: %d, RPe: %d, RP0: %d\n", gt, rpn, rpe, rp0); > > > > > > /* Set min/max to RPn, RP0 for baseline behavior */ > > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0) > 0); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0)); > > > > > > /* > > > * Negative bound tests > > > * RPn is the floor > > > * RP0 is the ceiling > > > */ > > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn - 1) < 0); > > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0 + 1) < 0); > > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn - 1) < 0); > > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0 + 1) < 0); > > > + igt_assert_lt(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn - 1), 0); > > > + igt_assert_lt(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0 + 1), 0); > > > + igt_assert_lt(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn - 1), 0); > > > + igt_assert_lt(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0 + 1), 0); > > > > > > /* Assert min requests are respected from rp0 to rpn */ > > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0) > 0); > > > - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rp0); > > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpe) > 0); > > > - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpe); > > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > > > - igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0)); > > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rp0); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpe)); > > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rpe); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MIN_FREQ_MHZ), rpn); > > > > > > /* Assert max requests are respected from rpn to rp0 */ > > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); > > > - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn); > > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpe) > 0); > > > - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpe); > > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0) > 0); > > > - igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rp0); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); > > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rpn); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpe)); > > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rpe); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0)); > > > + igt_assert_eq_u32(get_freq(dirfd, RPS_MAX_FREQ_MHZ), rp0); > > > > > > } > > > > > > @@ -100,8 +100,8 @@ static void test_reset(int i915, int dirfd, int gt, int count) > > > > > > for (int i = 0; i < count; i++) { > > > igt_debug("Running cycle: %d", i); > > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); > > > usleep(ACT_FREQ_LATENCY_US); > > > req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ); > > > if (req_freq) > > > @@ -124,8 +124,8 @@ static void test_suspend(int i915, int dirfd, int gt) > > > uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ); > > > uint32_t req_freq; > > > > > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); > > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn)); > > > + igt_assert_lt(0, set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn)); > > > usleep(ACT_FREQ_LATENCY_US); > > > req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ); > > > if (req_freq) > > > @@ -149,8 +149,10 @@ static void restore_sysfs_freq(int sig) > > > /* Restore frequencies */ > > > for_each_sysfs_gt_dirfd(i915, dirfd, gt) { > > > igt_pm_ignore_slpc_efficient_freq(i915, dirfd, false); > > > - igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, stash_max[gt]) > 0); > > > - igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, stash_min[gt]) > 0); > > > + igt_assert_lt(0, > > > + set_freq(dirfd, RPS_MAX_FREQ_MHZ, stash_max[gt])); > > > + igt_assert_lt(0, > > > + set_freq(dirfd, RPS_MIN_FREQ_MHZ, stash_min[gt])); > > > } > > > free(stash_min); > > > free(stash_max); > > > diff --git a/tests/intel/i915_pm_rc6_residency.c b/tests/intel/i915_pm_rc6_residency.c > > > index ebc0c235c..7942d46d3 100644 > > > --- a/tests/intel/i915_pm_rc6_residency.c > > > +++ b/tests/intel/i915_pm_rc6_residency.c > > > @@ -250,7 +250,7 @@ static char *get_drpc(int i915, int gt_id) > > > int gt_dir; > > > > > > gt_dir = igt_debugfs_gt_dir(i915, gt_id); > > > - igt_assert(gt_dir != -1); > > > + igt_assert_neq(gt_dir, -1); > > > return igt_sysfs_get(gt_dir, "drpc"); > > > } > > > > > > @@ -307,7 +307,7 @@ static int open_pmu(int i915, uint64_t config) > > > > > > fd = perf_i915_open(i915, config); > > > igt_skip_on(fd < 0 && errno == ENODEV); > > > - igt_assert(fd >= 0); > > > + igt_assert_lte(0, fd); > > > > > > return fd; > > > } > > > diff --git a/tests/intel/i915_pm_rps.c b/tests/intel/i915_pm_rps.c > > > index 99b83f315..3b7da197d 100644 > > > --- a/tests/intel/i915_pm_rps.c > > > +++ b/tests/intel/i915_pm_rps.c > > > @@ -322,7 +322,8 @@ static void load_helper_run(enum load load) > > > spin[high_load] = __igt_spin_new(drm_fd, .ahnd = ahnd); > > > > > > if (lh.signal && high_load != prev_load) { > > > - write(lh.link, &lh.signal, sizeof(lh.signal)); > > > + igt_assert_eq(write(lh.link, &lh.signal, sizeof(lh.signal)), > > > + sizeof(lh.signal)); > > > lh.signal = false; > > > } > > > prev_load = high_load; > > > @@ -690,9 +691,9 @@ static uint64_t __fence_order(int i915, > > > obj->flags = flags1; > > > gem_execbuf(i915, eb); > > > > > > - read(fd, before, sizeof(before)); > > > + igt_assert_eq(read(fd, before, sizeof(before)), sizeof(before)); > > > gem_sync(i915, obj->handle); > > > - read(fd, after, sizeof(after)); > > > + igt_assert_eq(read(fd, after, sizeof(after)), sizeof(after)); > > > close(fd); > > > > > > after[0] -= before[0]; > > > @@ -796,9 +797,9 @@ static uint64_t __engine_order(int i915, > > > gem_execbuf(i915, eb); > > > } > > > > > > - read(fd, before, sizeof(before)); > > > + igt_assert_eq(read(fd, before, sizeof(before)), sizeof(before)); > > > gem_sync(i915, obj->handle); > > > - read(fd, after, sizeof(after)); > > > + igt_assert_eq(read(fd, after, sizeof(after)), sizeof(after)); > > > close(fd); > > > > > > after[0] -= before[0]; > > > diff --git a/tests/intel/i915_query.c b/tests/intel/i915_query.c > > > index f886297ed..4d706d62b 100644 > > > --- a/tests/intel/i915_query.c > > > +++ b/tests/intel/i915_query.c > > > @@ -491,7 +491,7 @@ test_query_topology_matches_eu_total(int fd) > > > > > > free(topo_info); > > > > > > - igt_assert(n_eus_topology == n_eus); > > > + igt_assert_eq(n_eus_topology, n_eus); > > > } > > > > > > /* > > > @@ -1380,7 +1380,7 @@ static void query_parse_and_validate_hwconfig_table(int i915) > > > i915_query_items(i915, &item, 1); > > > igt_assert(item.length == table_size); > > > igt_info("Table size = %d bytes\n", table_size); > > > - igt_assert(table_size > 0); > > > + igt_assert_lt(0, table_size); > > > > > > /* HWConfig table is a list of KLV sets */ > > > max_words = table_size / sizeof(uint32_t); > > > @@ -1391,21 +1391,21 @@ static void query_parse_and_validate_hwconfig_table(int i915) > > > igt_assert(data[i] < __INTEL_HWCONFIG_KEY_LIMIT); > > > > > > len = data[i + 1]; > > > - igt_assert(len > 0); > > > - igt_assert((i + 2 + len) <= max_words); > > > + igt_assert_lt(0, len); > > > + igt_assert_lte((i + 2 + len), max_words); > > > > > > igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]); > > > > > > value = data[i + 2]; > > > switch (data[i]) { > > > case INTEL_HWCONFIG_MEMORY_TYPE: > > > - igt_assert(len == 1); > > > + igt_assert_eq(len, 1); > > > igt_assert(value < __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT); > > > igt_info("%s\n", hwconfig_memtypes[value]); > > > break; > > > > > > case INTEL_HWCONFIG_CACHE_TYPES: > > > - igt_assert(len == 1); > > > + igt_assert_eq(len, 1); > > > > > > if (!value) > > > igt_info("-\n"); > > > diff --git a/tests/intel/kms_big_fb.c b/tests/intel/kms_big_fb.c > > > index 605813f7f..b808b4a02 100644 > > > --- a/tests/intel/kms_big_fb.c > > > +++ b/tests/intel/kms_big_fb.c > > > @@ -307,7 +307,7 @@ static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width, > > > igt_remove_fb(data->drm_fd, &col_fb); > > > } > > > > > > - igt_assert(drmIoctl(data->drm_fd, DRM_IOCTL_MODE_ADDFB2, &f) == 0); > > > + do_ioctl(data->drm_fd, DRM_IOCTL_MODE_ADDFB2, &f); > > > newfb->fb_id = f.fb_id; > > > } > > > > > > diff --git a/tests/intel/kms_busy.c b/tests/intel/kms_busy.c > > > index db45e286e..5917b888f 100644 > > > --- a/tests/intel/kms_busy.c > > > +++ b/tests/intel/kms_busy.c > > > @@ -388,7 +388,7 @@ static void gpu_engines_init_timeouts(int fd, int max_engines, > > > > > > *num_engines = 0; > > > for_each_physical_engine(fd, e) { > > > - igt_assert(*num_engines < max_engines); > > > + igt_assert_lt(*num_engines, max_engines); > > > > > > props[*num_engines].engine = *e; > > > props[*num_engines].preempt_timeout = 0; > > > diff --git a/tests/intel/kms_ccs.c b/tests/intel/kms_ccs.c > > > index c91370a9a..f262b271c 100644 > > > --- a/tests/intel/kms_ccs.c > > > +++ b/tests/intel/kms_ccs.c > > > @@ -348,7 +348,7 @@ static void check_ccs_cc_plane(int drm_fd, igt_fb_t *fb, int plane, const float > > > (uint8_t)(cc_color[1] * 0xff) << 8 | > > > (uint8_t)(cc_color[2] * 0xff); > > > > > > - igt_assert(native_color == cc_p[4].d); > > > + igt_assert_eq_u32(native_color, cc_p[4].d); > > > > > > igt_assert(gem_munmap(map, fb->size) == 0); > > > }; > > > diff --git a/tests/intel/kms_cdclk.c b/tests/intel/kms_cdclk.c > > > index 7baf7d98e..6fe6e6c3f 100644 > > > --- a/tests/intel/kms_cdclk.c > > > +++ b/tests/intel/kms_cdclk.c > > > @@ -236,9 +236,8 @@ static void test_mode_transition(data_t *data, enum pipe pipe, igt_output_t *out > > > mode_hi = get_highres_mode(output); > > > igt_require(mode_hi != NULL); > > > > > > - if (mode_hi->hdisplay == mode_lo->hdisplay && > > > - mode_hi->vdisplay == mode_lo->vdisplay) > > > - igt_skip("Highest and lowest mode resolutions are same; no transition\n"); > > > + igt_skip_on_f(mode_hi->hdisplay == mode_lo->hdisplay && mode_hi->vdisplay == mode_lo->vdisplay, > > > + "Highest and lowest mode resolutions are same; no transition\n"); > > > > > > primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); > > > > > > diff --git a/tests/intel/kms_dsc_helper.c b/tests/intel/kms_dsc_helper.c > > > index 58057aca3..0de09b8e9 100644 > > > --- a/tests/intel/kms_dsc_helper.c > > > +++ b/tests/intel/kms_dsc_helper.c > > > @@ -35,7 +35,7 @@ void save_force_dsc_en(int drmfd, igt_output_t *output) > > > igt_is_force_dsc_enabled(drmfd, output->name); > > > force_dsc_restore_fd = > > > igt_get_dsc_debugfs_fd(drmfd, output->name); > > > - igt_assert(force_dsc_restore_fd >= 0); > > > + igt_assert_lte(0, force_dsc_restore_fd); > > > } > > > > > > void restore_force_dsc_en(void) > > > @@ -163,7 +163,7 @@ void save_force_dsc_fractional_bpp_en(int drmfd, igt_output_t *output) > > > igt_is_force_dsc_fractional_bpp_enabled(drmfd, output->name); > > > force_dsc_fractional_bpp_restore_fd = > > > igt_get_dsc_fractional_bpp_debugfs_fd(drmfd, output->name); > > > - igt_assert(force_dsc_fractional_bpp_restore_fd >= 0); > > > + igt_assert_lte(0, force_dsc_fractional_bpp_restore_fd); > > > } > > > > > > void restore_force_dsc_fractional_bpp_en(void) > > > diff --git a/tests/intel/kms_fbcon_fbt.c b/tests/intel/kms_fbcon_fbt.c > > > index 71e42f19c..edf6f8d4e 100644 > > > --- a/tests/intel/kms_fbcon_fbt.c > > > +++ b/tests/intel/kms_fbcon_fbt.c > > > @@ -317,8 +317,7 @@ static void fbc_skips_on_fbcon(int debugfs_fd) > > > for (i = 0; skip == false && i < ARRAY_SIZE(reasons); i++) > > > skip = strstr(buf, reasons[i]); > > > > > > - if (skip) > > > - igt_skip("fbcon modeset is not compatible with FBC\n"); > > > + igt_skip_on_f(skip, "fbcon modeset is not compatible with FBC\n"); > > > } > > > > > > static void psr_skips_on_fbcon(int debugfs_fd) > > > diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c > > > index e1318bfa6..1aef1e02d 100644 > > > --- a/tests/intel/kms_pm_dc.c > > > +++ b/tests/intel/kms_pm_dc.c > > > @@ -230,11 +230,10 @@ static uint32_t get_dc_counter(char *dc_data) > > > long ret; > > > char *s = strchr(dc_data, ':'); > > > > > > - assert(s); > > > + igt_assert(s); > > > s++; > > > ret = strtol(s, &e, 10); > > > - assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) && > > > - e > s && *e == '\n' && ret >= 0); > > > + igt_assert(((ret != LONG_MIN && ret != LONG_MAX) || errno != ERANGE) && e > s && *e == '\n' && ret >= 0); > > > return ret; > > > } > > > > > > @@ -611,8 +610,8 @@ static void test_deep_pkgc_state(data_t *data) > > > } > > > > > > /* Skip the test if no VRR capable output is found */ > > > - if (!vrr_supported) > > > - igt_skip("No VRR capable output found, skipping the test.\n"); > > > + igt_skip_on_f(!vrr_supported, > > > + "No VRR capable output found, skipping the test.\n"); > > > > > > igt_display_reset(display); > > > > > > diff --git a/tests/intel/kms_pm_rpm.c b/tests/intel/kms_pm_rpm.c > > > index 66c68b902..5af3e81bc 100644 > > > --- a/tests/intel/kms_pm_rpm.c > > > +++ b/tests/intel/kms_pm_rpm.c > > > @@ -1527,7 +1527,7 @@ static void pm_test_tiling(void) > > > gem_set_tiling(drm_fd, handles[j], > > > tiling_modes[i], stride); > > > gem_get_tiling(drm_fd, handles[j], &ti, &sw); > > > - igt_assert(tiling_modes[i] == ti); > > > + igt_assert_eq_u32(tiling_modes[i], ti); > > > } > > > > > > enable_one_screen_and_wait(&ms_data); > > > diff --git a/tests/intel/kms_psr.c b/tests/intel/kms_psr.c > > > index f3caa9ecc..cf0ce4bb8 100644 > > > --- a/tests/intel/kms_psr.c > > > +++ b/tests/intel/kms_psr.c > > > @@ -499,27 +499,27 @@ static void fill_render(data_t *data, const struct igt_fb *fb, > > > > > > static bool psr_wait_entry_if_enabled(data_t *data) > > > { > > > - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) > > > - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", > > > - data->op_psr_mode); > > > + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), > > > + "enable_psr modparam doesn't allow psr mode %d\n", > > > + data->op_psr_mode); > > > > > > return psr_wait_entry(data->debugfs_fd, data->op_psr_mode, data->output); > > > } > > > > > > static bool psr_wait_update_if_enabled(data_t *data) > > > { > > > - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) > > > - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", > > > - data->op_psr_mode); > > > + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), > > > + "enable_psr modparam doesn't allow psr mode %d\n", > > > + data->op_psr_mode); > > > > > > return psr_wait_update(data->debugfs_fd, data->op_psr_mode, data->output); > > > } > > > > > > static bool psr_enable_if_enabled(data_t *data) > > > { > > > - if (!is_psr_enable_possible(data->drm_fd, data->op_psr_mode)) > > > - igt_skip("enable_psr modparam doesn't allow psr mode %d\n", > > > - data->op_psr_mode); > > > + igt_skip_on_f(!is_psr_enable_possible(data->drm_fd, data->op_psr_mode), > > > + "enable_psr modparam doesn't allow psr mode %d\n", > > > + data->op_psr_mode); > > > > > > return psr_enable(data->drm_fd, data->debugfs_fd, data->op_psr_mode, data->output); > > > } > > > diff --git a/tests/intel/perf.c b/tests/intel/perf.c > > > index 95b17f522..c5a103c94 100644 > > > --- a/tests/intel/perf.c > > > +++ b/tests/intel/perf.c > > > @@ -493,12 +493,12 @@ __perf_open(int fd, struct drm_i915_perf_open_param *param, bool prevent_pm) > > > > > > ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param); > > > > > > - igt_assert(ret >= 0); > > > + igt_assert_lte(0, ret); > > > errno = 0; > > > > > > if (prevent_pm) { > > > pm_fd = open("/dev/cpu_dma_latency", O_RDWR); > > > - igt_assert(pm_fd >= 0); > > > + igt_assert_lte(0, pm_fd); > > > > > > igt_assert_eq(write(pm_fd, &pm_value, sizeof(pm_value)), sizeof(pm_value)); > > > } > > > @@ -625,7 +625,7 @@ elapsed_delta(uint64_t t1, uint64_t t0, uint32_t width) > > > { > > > uint32_t max_bits = sizeof(t1) * 8; > > > > > > - igt_assert(width <= max_bits); > > > + igt_assert_lte_u32(width, max_bits); > > > > > > if (t1 < t0 && width != max_bits) > > > return ((1ULL << width) - t0) + t1; > > > @@ -2128,7 +2128,7 @@ test_oa_exponents(const struct intel_execution_engine2 *e) > > > /* igt_debug(" > read %i bytes\n", ret); */ > > > > > > /* We should never have no data. */ > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > > > > for (int offset = 0; > > > offset < ret && n_timer_reports < NUM_TIMER_REPORTS; > > > @@ -2472,7 +2472,7 @@ test_blocking(uint64_t requested_oa_period, > > > errno == EINTR) > > > ; > > > > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > > > > /* For Haswell reports don't contain a well defined reason > > > * field we so assume all reports to be 'periodic'. For gen8+ > > > @@ -2526,12 +2526,12 @@ test_blocking(uint64_t requested_oa_period, > > > /* With completely broken blocking (but also not returning an error) we > > > * could end up with an open loop, > > > */ > > > - igt_assert(n <= (max_iterations + n_extra_iterations)); > > > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > > > > > /* Make sure the driver is reporting new samples with a reasonably > > > * low latency... > > > */ > > > - igt_assert(n > (min_iterations + n_extra_iterations)); > > > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > > > > > if (!set_kernel_hrtimer) > > > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > > > @@ -2728,12 +2728,12 @@ test_polling(uint64_t requested_oa_period, > > > /* With completely broken blocking while polling (but still somehow > > > * reporting a POLLIN event) we could end up with an open loop. > > > */ > > > - igt_assert(n <= (max_iterations + n_extra_iterations)); > > > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > > > > > /* Make sure the driver is reporting new samples with a reasonably > > > * low latency... > > > */ > > > - igt_assert(n > (min_iterations + n_extra_iterations)); > > > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > > > > > if (!set_kernel_hrtimer) > > > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > > > @@ -2821,7 +2821,7 @@ num_valid_reports_captured(struct drm_i915_perf_open_param *param, > > > errno == EINTR) > > > ; > > > > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > > > > for (int offset = 0; offset < ret; offset += header->size) { > > > header = (void *)(buf + offset); > > > @@ -3343,7 +3343,7 @@ test_short_reads(void) > > > ret = read(stream_fd, > > > header, > > > page_size); > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > } while (header->type == DRM_I915_PERF_RECORD_OA_REPORT_LOST); > > > > > > igt_assert_eq(ret, record_size); > > > @@ -5001,7 +5001,7 @@ static int i915_perf_add_config(int fd, struct drm_i915_perf_oa_config *config) > > > int config_id = __i915_perf_add_config(fd, config); > > > > > > igt_debug("config_id=%i\n", config_id); > > > - igt_assert(config_id > 0); > > > + igt_assert_lt(0, config_id); > > > > > > return config_id; > > > } > > > @@ -5339,7 +5339,7 @@ test_whitelisted_registers_userspace_config(void) > > > > > > /* Create a new config */ > > > ret = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, &config); > > > - igt_assert(ret > 0); /* Config 0 should be used by the kernel */ > > > + igt_assert_lt(0, ret); /* Config 0 should be used by the kernel */ > > > config_id = ret; > > > > > > i915_perf_remove_config(drm_fd, config_id); > > > @@ -5360,7 +5360,7 @@ read_i915_module_ref(void) > > > if (strncmp(line, "i915 ", 5) == 0) { > > > unsigned long mem; > > > int ret = sscanf(line + 5, "%lu %u", &mem, &ref_count); > > > - igt_assert(ret == 2); > > > + igt_assert_eq(ret, 2); > > > goto done; > > > } > > > } > > > @@ -5381,7 +5381,7 @@ static int perf_sysfs_open(int i915) > > > for_each_sysfs_gt_dirfd(i915, dirfd, gt) > > > break; > > > > > > - igt_assert(dirfd != -1); > > > + igt_assert_neq(dirfd, -1); > > > > > > return dirfd; > > > } > > > @@ -5784,7 +5784,7 @@ test_group_exclusive_stream(const intel_ctx_t *ctx, bool exponent) > > > grp->perf_fd = igt_ioctl(drm_fd, > > > DRM_IOCTL_I915_PERF_OPEN, > > > ¶m); > > > - igt_assert(grp->perf_fd >= 0); > > > + igt_assert_lte(0, grp->perf_fd); > > > igt_debug("opened OA buffer with c:i %d:%d\n", > > > ci->engine_class, ci->engine_instance); > > > } > > > @@ -5826,7 +5826,7 @@ test_group_exclusive_stream(const intel_ctx_t *ctx, bool exponent) > > > param.num_properties = ARRAY_SIZE(properties) / 2 - 1; > > > errno = 0; > > > err = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m); > > > - igt_assert(err < 0); > > > + igt_assert_lt(err, 0); > > > igt_assert(errno == EBUSY || errno == ENODEV); > > > igt_debug("try OA ci unit with c:i %d:%d\n", > > > ci->engine_class, ci->engine_instance); > > > diff --git a/tests/intel/perf_pmu.c b/tests/intel/perf_pmu.c > > > index e3f51d0c7..bfa2d501a 100644 > > > --- a/tests/intel/perf_pmu.c > > > +++ b/tests/intel/perf_pmu.c > > > @@ -200,7 +200,7 @@ static char *get_drpc(int i915, int gt_id) > > > int gt_dir; > > > > > > gt_dir = igt_debugfs_gt_dir(i915, gt_id); > > > - igt_assert(gt_dir != -1); > > > + igt_assert_neq(gt_dir, -1); > > > return igt_sysfs_get(gt_dir, "drpc"); > > > } > > > > > > @@ -210,7 +210,7 @@ static int open_pmu(int i915, uint64_t config) > > > > > > fd = perf_i915_open(i915, config); > > > igt_skip_on(fd < 0 && errno == ENODEV); > > > - igt_assert(fd >= 0); > > > + igt_assert_lte(0, fd); > > > > > > return fd; > > > } > > > @@ -221,7 +221,7 @@ static int open_group(int i915, uint64_t config, int group) > > > > > > fd = perf_i915_open_group(i915, config, group); > > > igt_skip_on(fd < 0 && errno == ENODEV); > > > - igt_assert(fd >= 0); > > > + igt_assert_lte(0, fd); > > > > > > return fd; > > > } > > > @@ -527,7 +527,7 @@ static void log_busy(unsigned int num_engines, uint64_t *val) > > > int len; > > > > > > len = snprintf(p, rem, "%u=%" PRIu64 "\n", i, val[i]); > > > - igt_assert(len > 0); > > > + igt_assert_lt(0, len); > > > rem -= len; > > > p += len; > > > } > > > @@ -950,7 +950,7 @@ __sema_busy(int gem_fd, uint64_t ahnd, int pmu, const intel_ctx_t *ctx, > > > int timeout = 3; > > > > > > /* Time spent being busy includes time waiting on semaphores */ > > > - igt_assert(busy_pct >= sema_pct); > > > + igt_assert_lte(sema_pct, busy_pct); > > > > > > gem_quiescent_gpu(gem_fd); > > > > > > @@ -1359,7 +1359,7 @@ static void open_invalid(int i915) > > > int fd; > > > > > > fd = perf_i915_open(i915, -1ULL); > > > - igt_assert(fd < 0); > > > + igt_assert_lt(fd, 0); > > > } > > > > > > static bool cpu0_hotplug_support(void) > > > @@ -1415,7 +1415,7 @@ static void cpu_hotplug(int gem_fd) > > > cpu), sizeof(name)); > > > cpufd = open(name, O_WRONLY); > > > if (cpufd == -1) { > > > - igt_assert(cpu > 0); > > > + igt_assert_lt(0, cpu); > > > /* > > > * Signal parent that we cycled through all > > > * CPUs and we are done. > > > @@ -1534,7 +1534,7 @@ test_interrupts(int gem_fd) > > > close(old_fd); > > > } > > > > > > - igt_assert(fence_fd >= 0); > > > + igt_assert_lte(0, fence_fd); > > > } > > > > > > /* Wait for idle state. */ > > > @@ -1755,9 +1755,9 @@ test_frequency(int gem_fd, unsigned int gt) > > > */ > > > __igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq); > > > __igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz", &read_value); > > > - if (read_value != min_freq) > > > - igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n", > > > - min_freq, read_value); > > > + igt_warn_on_f(read_value != min_freq, > > > + "Unable to restore min frequency to saved value [%u MHz], now %u MHz\n", > > > + min_freq, read_value); > > > close(fd[0]); > > > close(fd[1]); > > > put_ahnd(ahnd); > > > @@ -1880,7 +1880,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) > > > continue; > > > > > > if (gt_ == gt) { > > > - igt_assert(test_idx == -1); > > > + igt_assert_eq(test_idx, -1); > > > test_idx = pmus; > > > } > > > > > > @@ -1890,7 +1890,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) > > > igt_skip_on(fd[pmus] < 0 && errno == ENODEV); > > > pmus++; > > > } > > > - igt_assert(test_idx >= 0); > > > + igt_assert_lte(0, test_idx); > > > > > > if (flags & TEST_RUNTIME_PM) { > > > drmModeRes *res; > > > @@ -1981,7 +1981,7 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags) > > > continue; > > > > > > fw[gt_] = open_forcewake_handle(gem_fd, gt_); > > > - igt_assert(fw[gt_] >= 0); > > > + igt_assert_lte(0, fw[gt_]); > > > } > > > > > > usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */ > > > @@ -2206,7 +2206,8 @@ accuracy(int gem_fd, const intel_ctx_t *ctx, > > > 100 * expected, target_busy_pct, > > > avg, sqrt(var / n)); > > > > > > - write(link[1], &expected, sizeof(expected)); > > > + igt_assert_eq(write(link[1], &expected, sizeof(expected)), > > > + sizeof(expected)); > > > } > > > > > > igt_spin_free(gem_fd, spin); > > > @@ -2216,12 +2217,14 @@ accuracy(int gem_fd, const intel_ctx_t *ctx, > > > fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance)); > > > > > > /* Let the child run. */ > > > - read(link[0], &expected, sizeof(expected)); > > > + igt_assert_eq(read(link[0], &expected, sizeof(expected)), > > > + sizeof(expected)); > > > assert_within(100.0 * expected, target_busy_pct, 5); > > > > > > /* Collect engine busyness for an interesting part of child runtime. */ > > > val[0] = __pmu_read_single(fd, &ts[0]); > > > - read(link[0], &expected, sizeof(expected)); > > > + igt_assert_eq(read(link[0], &expected, sizeof(expected)), > > > + sizeof(expected)); > > > val[1] = __pmu_read_single(fd, &ts[1]); > > > close(fd); > > > > > > diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c > > > index beccfcb1a..a55ee5abd 100644 > > > --- a/tests/intel/xe_ccs.c > > > +++ b/tests/intel/xe_ccs.c > > > @@ -212,7 +212,7 @@ static void surf_copy(int xe, > > > WRITE_PNG(xe, run_id, "corrupted", &blt.dst, dst->x2, dst->y2, bpp); > > > result = memcmp(src->ptr, dst->ptr, src->size); > > > if (blt_platform_has_flat_ccs_enabled(xe)) > > > - igt_assert(result != 0); > > > + igt_assert_neq(result, 0); > > > > > > /* In case of suspend_resume, buffer object would become > > > * uncompressed in xe2+ dgfx, and therefore retrieve the > > > @@ -696,7 +696,7 @@ static int opt_handler(int opt, int opt_index, void *data) > > > case 'f': > > > param.compression_format = atoi(optarg); > > > igt_debug("Compression format: %d\n", param.compression_format); > > > - igt_assert((param.compression_format & ~0x1f) == 0); > > > + igt_assert_eq((param.compression_format & ~0x1f), 0); > > > break; > > > case 'p': > > > param.write_png = true; > > > diff --git a/tests/intel/xe_debugfs.c b/tests/intel/xe_debugfs.c > > > index a7d56a0be..a7c567c45 100644 > > > --- a/tests/intel/xe_debugfs.c > > > +++ b/tests/intel/xe_debugfs.c > > > @@ -222,7 +222,7 @@ test_forcewake(int fd) > > > { > > > int handle = igt_debugfs_open(fd, "forcewake_all", O_WRONLY); > > > > > > - igt_assert(handle != -1); > > > + igt_assert_neq(handle, -1); > > > close(handle); > > > } > > > > > > diff --git a/tests/intel/xe_dma_buf_sync.c b/tests/intel/xe_dma_buf_sync.c > > > index f0d3f0d54..7af80dd2f 100644 > > > --- a/tests/intel/xe_dma_buf_sync.c > > > +++ b/tests/intel/xe_dma_buf_sync.c > > > @@ -108,7 +108,7 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0, > > > } *data [MAX_N_BO]; > > > int i; > > > > > > - igt_assert(n_bo <= MAX_N_BO); > > > + igt_assert_lte(n_bo, MAX_N_BO); > > > > > > for (i = 0; i < N_FD; ++i) { > > > fd[i] = drm_open_driver(DRIVER_XE); > > > diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c > > > index eebdbc84b..f0c66c49e 100644 > > > --- a/tests/intel/xe_evict.c > > > +++ b/tests/intel/xe_evict.c > > > @@ -57,7 +57,7 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci, > > > } *data; > > > int i, b; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > > > bo = calloc(n_execs / 2, sizeof(*bo)); > > > igt_assert(bo); > > > @@ -237,7 +237,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, > > > } *data; > > > int i, b; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > > > bo = calloc(n_execs / 2, sizeof(*bo)); > > > igt_assert(bo); > > > diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c > > > index a6dbd748b..73f69e7b0 100644 > > > --- a/tests/intel/xe_exec_balancer.c > > > +++ b/tests/intel/xe_exec_balancer.c > > > @@ -190,7 +190,7 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs, > > > struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; > > > int i, j, b, num_placements = 0; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > > > xe_for_each_engine(fd, hwe) { > > > if (hwe->engine_class != class || hwe->gt_id != gt) > > > @@ -410,7 +410,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > > > int i, j, b, num_placements = 0; > > > int map_fd = -1; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > > > xe_for_each_engine(fd, hwe) { > > > if (hwe->engine_class != class || hwe->gt_id != gt) > > > @@ -534,7 +534,8 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, > > > if (flags & RACE) { > > > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > > > 0x666); > > > - write(map_fd, data, bo_size); > > > + igt_assert_eq(write(map_fd, data, bo_size), > > > + bo_size); > > > data = mmap((void *)MAP_ADDRESS, bo_size, > > > PROT_READ | PROT_WRITE, MAP_SHARED | > > > MAP_FIXED, map_fd, 0); > > > diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c > > > index 0fd1ae062..dfbd68d1d 100644 > > > --- a/tests/intel/xe_exec_basic.c > > > +++ b/tests/intel/xe_exec_basic.c > > > @@ -122,8 +122,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > > } *data; > > > int i, b; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > - igt_assert(n_vm <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_vm, MAX_N_EXEC_QUEUES); > > > > > > for (i = 0; i < n_vm; ++i) > > > vm[i] = xe_vm_create(fd, 0, 0); > > > diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c > > > index 389de7ca4..b92feee2c 100644 > > > --- a/tests/intel/xe_exec_compute_mode.c > > > +++ b/tests/intel/xe_exec_compute_mode.c > > > @@ -115,7 +115,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > > int map_fd = -1; > > > int64_t fence_timeout; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > > > > > vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); > > > bo_size = sizeof(*data) * n_execs; > > > @@ -243,7 +243,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > > if (flags & RACE) { > > > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > > > 0x666); > > > - write(map_fd, data, bo_size); > > > + igt_assert_eq(write(map_fd, data, bo_size), > > > + bo_size); > > > data = mmap((void *)MAP_ADDRESS, bo_size, > > > PROT_READ | PROT_WRITE, MAP_SHARED | > > > MAP_FIXED, map_fd, 0); > > > @@ -457,7 +458,7 @@ static void lr_mode_workload(int fd) > > > ts_1 = spin->timestamp; > > > sleep(1); > > > ts_2 = spin->timestamp; > > > - igt_assert(ts_1 != ts_2); > > > + igt_assert_neq_u32(ts_1, ts_2); > > > > > > xe_spin_end(spin); > > > xe_wait_ufence(fd, &spin->exec_sync, USER_FENCE_VALUE, 0, ONE_SEC); > > > @@ -466,7 +467,7 @@ static void lr_mode_workload(int fd) > > > ts_1 = spin->timestamp; > > > sleep(1); > > > ts_2 = spin->timestamp; > > > - igt_assert(ts_1 == ts_2); > > > + igt_assert_eq_u32(ts_1, ts_2); > > > > > > sync.addr = to_user_pointer(&vm_sync); > > > xe_vm_unbind_async(fd, vm, 0, 0, spin_addr, bo_size, &sync, 1); > > > diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c > > > index b022f97d3..56bad2b75 100644 > > > --- a/tests/intel/xe_exec_fault_mode.c > > > +++ b/tests/intel/xe_exec_fault_mode.c > > > @@ -140,7 +140,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > > int i, j, b; > > > int map_fd = -1; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > > > if (flags & ENABLE_SCRATCH) > > > vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE | > > > @@ -291,7 +291,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, > > > if (flags & RACE) { > > > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > > > 0x666); > > > - write(map_fd, data, bo_size); > > > + igt_assert_eq(write(map_fd, data, bo_size), > > > + bo_size); > > > data = mmap((void *)MAP_ADDRESS, bo_size, > > > PROT_READ | PROT_WRITE, MAP_SHARED | > > > MAP_FIXED, map_fd, 0); > > > diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c > > > index dcb22f275..72f2133e5 100644 > > > --- a/tests/intel/xe_exec_reset.c > > > +++ b/tests/intel/xe_exec_reset.c > > > @@ -155,7 +155,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, > > > struct drm_xe_engine_class_instance eci[MAX_INSTANCE]; > > > int i, j, b, num_placements = 0, bad_batches = 1; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > > > > > if (flags & CLOSE_FD) > > > fd = drm_open_driver(DRIVER_XE); > > > @@ -326,7 +326,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, > > > struct xe_spin_opts spin_opts = { .preempt = false }; > > > int i, b; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > > > > > if (flags & CLOSE_FD) > > > fd = drm_open_driver(DRIVER_XE); > > > @@ -475,7 +475,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > > > struct xe_spin_opts spin_opts = { .preempt = false }; > > > int i, b; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES); > > > > > > if (flags & CLOSE_FD) > > > fd = drm_open_driver(DRIVER_XE); > > > @@ -704,7 +704,7 @@ gt_reset(int fd, int n_threads, int n_sec) > > > for (i = 0; i < n_threads; i++) > > > pthread_join(threads[i].thread, NULL); > > > > > > - printf("number of resets %d\n", num_reset); > > > + igt_info("number of resets %d\n", num_reset); > > > > > > free(threads); > > > } > > > diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c > > > index c872c22d5..5c1dd0a01 100644 > > > --- a/tests/intel/xe_exec_store.c > > > +++ b/tests/intel/xe_exec_store.c > > > @@ -249,7 +249,7 @@ static void store_cachelines(int fd, struct drm_xe_engine_class_instance *eci, > > > object_index = n % (count - 1); > > > ptr[n] = bo_map[object_index] + delta / 4; > > > > > > - igt_assert(*ptr[n] == value[n]); > > > + igt_assert_eq_u32(*ptr[n], value[n]); > > > } > > > > > > for (i = 0; i < count; i++) { > > > diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c > > > index e7a0a7cd0..6e53d3cf8 100644 > > > --- a/tests/intel/xe_exec_threads.c > > > +++ b/tests/intel/xe_exec_threads.c > > > @@ -70,7 +70,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr, > > > int i, j, b, num_placements = 0; > > > bool owns_vm = false, owns_fd = false; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > > > if (flags & FD) { > > > fd = drm_reopen_driver(fd); > > > @@ -88,7 +88,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr, > > > > > > eci[num_placements++] = *hwe; > > > } > > > - igt_assert(num_placements > 1); > > > + igt_assert_lt(1, num_placements); > > > > > > bo_size = sizeof(*data) * n_execs; > > > bo_size = xe_bb_size(fd, bo_size); > > > @@ -272,7 +272,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > > > int map_fd = -1; > > > bool owns_vm = false, owns_fd = false; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > > > if (flags & FD) { > > > fd = drm_reopen_driver(fd); > > > @@ -396,7 +396,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > > > if (flags & RACE) { > > > map_fd = open("/tmp", O_TMPFILE | O_RDWR, > > > 0x666); > > > - write(map_fd, data, bo_size); > > > + igt_assert_eq(write(map_fd, data, bo_size), > > > + bo_size); > > > data = mmap(from_user_pointer(userptr), bo_size, > > > PROT_READ | PROT_WRITE, > > > MAP_SHARED | MAP_FIXED, > > > @@ -476,7 +477,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, > > > int i, j, b, hang_exec_queue = n_exec_queues / 2; > > > bool owns_vm = false, owns_fd = false; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > > > if (flags & FD) { > > > fd = drm_reopen_driver(fd); > > > diff --git a/tests/intel/xe_gt_freq.c b/tests/intel/xe_gt_freq.c > > > index 93ebb5ed0..365c9b9e6 100644 > > > --- a/tests/intel/xe_gt_freq.c > > > +++ b/tests/intel/xe_gt_freq.c > > > @@ -41,7 +41,7 @@ static int set_freq(int fd, int gt_id, const char *freq_name, uint32_t freq) > > > > > > snprintf(freq_attr, sizeof(freq_attr), "freq0/%s_freq", freq_name); > > > gt_fd = xe_sysfs_gt_open(fd, gt_id); > > > - igt_assert(gt_fd >= 0); > > > + igt_assert_lte(0, gt_fd); > > > > > > while (ret == -EAGAIN) > > > ret = igt_sysfs_printf(gt_fd, freq_attr, "%u", freq); > > > @@ -59,7 +59,7 @@ static uint32_t get_freq(int fd, int gt_id, const char *freq_name) > > > > > > snprintf(freq_attr, sizeof(freq_attr), "freq0/%s_freq", freq_name); > > > gt_fd = xe_sysfs_gt_open(fd, gt_id); > > > - igt_assert(gt_fd >= 0); > > > + igt_assert_lte(0, gt_fd); > > > > > > while (err == -EAGAIN) > > > err = igt_sysfs_scanf(gt_fd, freq_attr, "%u", &freq); > > > @@ -84,7 +84,7 @@ static uint32_t get_throttle(int fd, int gt_id, const char *throttle_file) > > > snprintf(throttle_attr, sizeof(throttle_attr), > > > "freq0/throttle/%s", throttle_file); > > > gt_fd = xe_sysfs_gt_open(fd, gt_id); > > > - igt_assert(gt_fd >= 0); > > > + igt_assert_lte(0, gt_fd); > > > > > > igt_sysfs_scanf(gt_fd, throttle_attr, "%u", &val); > > > > > > @@ -134,26 +134,26 @@ static void test_freq_basic_api(int fd, int gt_id) > > > * RPn is the floor > > > * RP0 is the ceiling > > > */ > > > - igt_assert(set_freq(fd, gt_id, "min", rpn - 1) < 0); > > > - igt_assert(set_freq(fd, gt_id, "min", rp0 + 1) < 0); > > > - igt_assert(set_freq(fd, gt_id, "max", rpn - 1) < 0); > > > - igt_assert(set_freq(fd, gt_id, "max", rp0 + 1) < 0); > > > + igt_assert_lt(set_freq(fd, gt_id, "min", rpn - 1), 0); > > > + igt_assert_lt(set_freq(fd, gt_id, "min", rp0 + 1), 0); > > > + igt_assert_lt(set_freq(fd, gt_id, "max", rpn - 1), 0); > > > + igt_assert_lt(set_freq(fd, gt_id, "max", rp0 + 1), 0); > > > > > > /* Assert min requests are respected from rp0 to rpn */ > > > - igt_assert(set_freq(fd, gt_id, "min", rp0) > 0); > > > - igt_assert(get_freq(fd, gt_id, "min") == rp0); > > > - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); > > > - igt_assert(get_freq(fd, gt_id, "min") == rpe(fd, gt_id)); > > > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > > > - igt_assert(get_freq(fd, gt_id, "min") == rpn); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rp0)); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rp0); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpe(fd, gt_id)); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpn); > > > > > > /* Assert max requests are respected from rpn to rp0 */ > > > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > > > - igt_assert(get_freq(fd, gt_id, "max") == rpn); > > > - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); > > > - igt_assert(get_freq(fd, gt_id, "max") == rpe(fd, gt_id)); > > > - igt_assert(set_freq(fd, gt_id, "max", rp0) > 0); > > > - igt_assert(get_freq(fd, gt_id, "max") == rp0); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpn); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpe(fd, gt_id)); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rp0)); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rp0); > > > } > > > > > > /** > > > @@ -176,10 +176,10 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle) > > > * Then we check if hardware is actually operating at the desired freq > > > * And let's do this for all the 3 known Render Performance (RP) values. > > > */ > > > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > > > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > > > usleep(ACT_FREQ_LATENCY_US); > > > - igt_assert(get_freq(fd, gt_id, "cur") == rpn); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpn); > > > > > > if (gt_idle) { > > > /* Wait for GT to go in C6 as previous get_freq wakes up GT*/ > > > @@ -187,31 +187,31 @@ static void test_freq_fixed(int fd, int gt_id, bool gt_idle) > > > "GT %d should be in C6\n", gt_id); > > > igt_assert(get_freq(fd, gt_id, "act") == 0); > > > } else { > > > - igt_assert(get_freq(fd, gt_id, "act") == rpn); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "act"), rpn); > > > } > > > > > > - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); > > > - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); > > > usleep(ACT_FREQ_LATENCY_US); > > > - igt_assert(get_freq(fd, gt_id, "cur") == rpe(fd, gt_id)); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpe(fd, gt_id)); > > > > > > if (gt_idle) { > > > igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10), > > > "GT %d should be in C6\n", gt_id); > > > igt_assert(get_freq(fd, gt_id, "act") == 0); > > > } else { > > > - igt_assert(get_freq(fd, gt_id, "act") == rpe(fd, gt_id)); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "act"), rpe(fd, gt_id)); > > > } > > > > > > - igt_assert(set_freq(fd, gt_id, "min", rp0) > 0); > > > - igt_assert(set_freq(fd, gt_id, "max", rp0) > 0); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rp0)); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rp0)); > > > usleep(ACT_FREQ_LATENCY_US); > > > /* > > > * It is unlikely that PCODE will *always* respect any request above RPe > > > * So for this level let's only check if GuC PC is doing its job > > > * and respecting our request, by propagating it to the hardware. > > > */ > > > - igt_assert(get_freq(fd, gt_id, "cur") == rp0); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rp0); > > > > > > if (gt_idle) { > > > igt_assert_f(igt_wait(xe_is_gt_in_c6(fd, gt_id), 1000, 10), > > > @@ -236,8 +236,8 @@ static void test_freq_range(int fd, int gt_id, bool gt_idle) > > > > > > igt_debug("Starting testing range request\n"); > > > > > > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > > > - igt_assert(set_freq(fd, gt_id, "max", rpe(fd, gt_id)) > 0); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpe(fd, gt_id))); > > > usleep(ACT_FREQ_LATENCY_US); > > > cur = get_freq(fd, gt_id, "cur"); > > > igt_assert(rpn <= cur && cur <= rpe(fd, gt_id)); > > > @@ -267,12 +267,12 @@ static void test_freq_low_max(int fd, int gt_id) > > > * When max request < min request, max is ignored and min works like > > > * a fixed one. Let's assert this assumption > > > */ > > > - igt_assert(set_freq(fd, gt_id, "min", rpe(fd, gt_id)) > 0); > > > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpe(fd, gt_id))); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > > > usleep(ACT_FREQ_LATENCY_US); > > > > > > /* Refresh value of rpe, pcode could have adjusted it */ > > > - igt_assert(get_freq(fd, gt_id, "cur") == rpe(fd, gt_id)); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpe(fd, gt_id)); > > > } > > > > > > /** > > > @@ -284,16 +284,16 @@ static void test_suspend(int fd, int gt_id) > > > { > > > uint32_t rpn = get_freq(fd, gt_id, "rpn"); > > > > > > - igt_assert(set_freq(fd, gt_id, "min", rpn) > 0); > > > - igt_assert(set_freq(fd, gt_id, "max", rpn) > 0); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "min", rpn)); > > > + igt_assert_lt(0, set_freq(fd, gt_id, "max", rpn)); > > > usleep(ACT_FREQ_LATENCY_US); > > > - igt_assert(get_freq(fd, gt_id, "cur") == rpn); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "cur"), rpn); > > > > > > igt_system_suspend_autoresume(SUSPEND_STATE_S3, > > > SUSPEND_TEST_NONE); > > > > > > - igt_assert(get_freq(fd, gt_id, "min") == rpn); > > > - igt_assert(get_freq(fd, gt_id, "max") == rpn); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "min"), rpn); > > > + igt_assert_eq_u32(get_freq(fd, gt_id, "max"), rpn); > > > } > > > > > > /** > > > diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c > > > index 647fd64e7..845052bf2 100644 > > > --- a/tests/intel/xe_intel_bb.c > > > +++ b/tests/intel/xe_intel_bb.c > > > @@ -674,11 +674,11 @@ static int __do_intel_bb_blit(struct buf_ops *bops, uint32_t tiling) > > > > > > /* We'll fail on src <-> final compare so just warn */ > > > if (tiling == I915_TILING_NONE) { > > > - if (compare_bufs(&src, &dst, false) > 0) > > > - igt_warn("none->none blit failed!"); > > > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > > > + "none->none blit failed!"); > > > } else { > > > - if (compare_bufs(&src, &dst, false) == 0) > > > - igt_warn("none->tiled blit failed!"); > > > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > > > + "none->tiled blit failed!"); > > > } > > > > > > fails = compare_bufs(&src, &final, true); > > > @@ -925,11 +925,11 @@ static int render(struct buf_ops *bops, uint32_t tiling, > > > > > > /* We'll fail on src <-> final compare so just warn */ > > > if (tiling == I915_TILING_NONE) { > > > - if (compare_bufs(&src, &dst, false) > 0) > > > - igt_warn("%s: none->none failed!\n", __func__); > > > + igt_warn_on_f(compare_bufs(&src, &dst, false) > 0, > > > + "%s: none->none failed!\n", __func__); > > > } else { > > > - if (compare_bufs(&src, &dst, false) == 0) > > > - igt_warn("%s: none->tiled failed!\n", __func__); > > > + igt_warn_on_f(compare_bufs(&src, &dst, false) == 0, > > > + "%s: none->tiled failed!\n", __func__); > > > } > > > > > > fails = compare_bufs(&src, &final, true); > > > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c > > > index ff2218300..e26ebceb9 100644 > > > --- a/tests/intel/xe_oa.c > > > +++ b/tests/intel/xe_oa.c > > > @@ -492,12 +492,12 @@ __perf_open(int fd, struct intel_xe_oa_open_prop *param, bool prevent_pm) > > > > > > ret = intel_xe_perf_ioctl(fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, param); > > > > > > - igt_assert(ret >= 0); > > > + igt_assert_lte(0, ret); > > > errno = 0; > > > > > > if (prevent_pm) { > > > pm_fd = open("/dev/cpu_dma_latency", O_RDWR); > > > - igt_assert(pm_fd >= 0); > > > + igt_assert_lte(0, pm_fd); > > > > > > igt_assert_eq(write(pm_fd, &pm_value, sizeof(pm_value)), sizeof(pm_value)); > > > } > > > @@ -568,7 +568,7 @@ elapsed_delta(uint64_t t1, uint64_t t0, uint32_t width) > > > { > > > uint32_t max_bits = sizeof(t1) * 8; > > > > > > - igt_assert(width <= max_bits); > > > + igt_assert_lte_u32(width, max_bits); > > > > > > if (t1 < t0 && width != max_bits) > > > return ((1ULL << width) - t0) + t1; > > > @@ -1710,7 +1710,7 @@ static void test_oa_exponents(const struct drm_xe_engine_class_instance *hwe) > > > > > > /* igt_debug(" > read %i bytes\n", ret); */ > > > /* We should never have no data. */ > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > > > > for (int offset = 0; > > > offset < ret && n_timer_reports < NUM_TIMER_REPORTS; > > > @@ -1933,7 +1933,7 @@ static void test_blocking(uint64_t requested_oa_period, > > > while ((ret = read(perf_fd, buf, sizeof(buf))) < 0 && > > > (errno == EINTR || errno == EIO)) > > > ; > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > > > > for (int offset = 0; offset < ret; offset += format_size) { > > > uint32_t *report = (void *)(buf + offset); > > > @@ -1972,12 +1972,12 @@ static void test_blocking(uint64_t requested_oa_period, > > > /* With completely broken blocking (but also not returning an error) we > > > * could end up with an open loop, > > > */ > > > - igt_assert(n <= (max_iterations + n_extra_iterations)); > > > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > > > > > /* Make sure the driver is reporting new samples with a reasonably > > > * low latency... > > > */ > > > - igt_assert(n > (min_iterations + n_extra_iterations)); > > > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > > > > > if (!set_kernel_hrtimer) > > > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > > > @@ -2163,12 +2163,12 @@ static void test_polling(uint64_t requested_oa_period, > > > /* With completely broken blocking while polling (but still somehow > > > * reporting a POLLIN event) we could end up with an open loop. > > > */ > > > - igt_assert(n <= (max_iterations + n_extra_iterations)); > > > + igt_assert_lte(n, (max_iterations + n_extra_iterations)); > > > > > > /* Make sure the driver is reporting new samples with a reasonably > > > * low latency... > > > */ > > > - igt_assert(n > (min_iterations + n_extra_iterations)); > > > + igt_assert_lt((min_iterations + n_extra_iterations), n); > > > > > > if (!set_kernel_hrtimer) > > > igt_assert(kernel_ns <= (test_duration_ns / 100ull)); > > > @@ -2260,7 +2260,7 @@ num_valid_reports_captured(struct intel_xe_oa_open_prop *param, > > > (errno == EINTR || errno == EIO)) > > > ; > > > > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > > > > for (int offset = 0; offset < ret; offset += format_size) { > > > uint32_t *report = (void *)(buf + offset); > > > @@ -3473,7 +3473,7 @@ static int xe_oa_add_config(int fd, struct drm_xe_oa_config *config) > > > int config_id = __xe_oa_add_config(fd, config); > > > > > > igt_debug("config_id=%i\n", config_id); > > > - igt_assert(config_id > 0); > > > + igt_assert_lt(0, config_id); > > > > > > return config_id; > > > } > > > @@ -3769,7 +3769,7 @@ test_whitelisted_registers_userspace_config(void) > > > > > > /* Create a new config */ > > > ret = intel_xe_perf_ioctl(drm_fd, DRM_XE_OBSERVATION_OP_ADD_CONFIG, &config); > > > - igt_assert(ret > 0); /* Config 0 should be used by the kernel */ > > > + igt_assert_lt(0, ret); /* Config 0 should be used by the kernel */ > > > config_id = ret; > > > > > > xe_oa_remove_config(drm_fd, config_id); > > > @@ -4195,7 +4195,7 @@ test_oa_unit_exclusive_stream(bool exponent) > > > properties[11] = exec_q[i]; > > > errno = 0; > > > err = intel_xe_perf_ioctl(drm_fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, ¶m); > > > - igt_assert(err < 0); > > > + igt_assert_lt(err, 0); > > > igt_assert(errno == EBUSY || errno == ENODEV); > > > poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); > > > } > > > diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c > > > index 82155f1d5..153d9ce1d 100644 > > > --- a/tests/intel/xe_pat.c > > > +++ b/tests/intel/xe_pat.c > > > @@ -808,7 +808,7 @@ static void display_vs_wb_transient(int fd) > > > > > > /* c0 -> c6 might flush caches */ > > > fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY); > > > - igt_assert(fw_handle >= 0); > > > + igt_assert_lte(0, fw_handle); > > > > > > render_copy(ibb, > > > &src, > > > diff --git a/tests/intel/xe_peer2peer.c b/tests/intel/xe_peer2peer.c > > > index 6ff4774bb..2a941abe6 100644 > > > --- a/tests/intel/xe_peer2peer.c > > > +++ b/tests/intel/xe_peer2peer.c > > > @@ -279,7 +279,7 @@ static char *region_name(int xe, uint32_t region) > > > r = snprintf(name, len, "%s", > > > xe_region_name(region)); > > > > > > - igt_assert(r > 0); > > > + igt_assert_lt(0, r); > > > > > > return name; > > > } > > > diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c > > > index 8b115e2f6..eee89428c 100644 > > > --- a/tests/intel/xe_pm.c > > > +++ b/tests/intel/xe_pm.c > > > @@ -94,7 +94,7 @@ static uint64_t get_vram_d3cold_threshold(int sysfs) > > > igt_require_f(!faccessat(sysfs, path, R_OK, 0), "vram_d3cold_threshold is not present\n"); > > > > > > ret = igt_sysfs_scanf(sysfs, path, "%lu", &threshold); > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > > > > return threshold; > > > } > > > @@ -111,7 +111,7 @@ static void set_vram_d3cold_threshold(int sysfs, uint64_t threshold) > > > else > > > igt_warn("vram_d3cold_threshold is not present\n"); > > > > > > - igt_assert(ret > 0); > > > + igt_assert_lt(0, ret); > > > } > > > > > > static void vram_d3cold_threshold_restore(int sig) > > > @@ -305,8 +305,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci, > > > bool check_rpm = (d_state == IGT_ACPI_D3Hot || > > > d_state == IGT_ACPI_D3Cold); > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > - igt_assert(n_execs > 0); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > + igt_assert_lt(0, n_execs); > > > > > > if (check_rpm) { > > > igt_assert(in_d3(device, d_state)); > > > @@ -507,7 +507,7 @@ static void test_vram_d3cold_threshold(device_t device, int sysfs_fd) > > > * Therefore open and close fw handle to wake the device. > > > */ > > > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > > > - igt_assert(fw_handle >= 0); > > > + igt_assert_lte(0, fw_handle); > > > active = igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE; > > > close(fw_handle); > > > igt_assert(active); > > > @@ -557,7 +557,7 @@ static void test_mmap(device_t device, uint32_t placement, uint32_t flags, > > > > > > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > > > > > > - igt_assert(fw_handle >= 0); > > > + igt_assert_lte(0, fw_handle); > > > igt_assert(igt_pm_get_runtime_active_time(device.pci_xe) > > > > active_time); > > > > > > @@ -600,7 +600,7 @@ static void test_mmap(device_t device, uint32_t placement, uint32_t flags, > > > > > > /* Runtime resume and check the pattern */ > > > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > > > - igt_assert(fw_handle >= 0); > > > + igt_assert_lte(0, fw_handle); > > > igt_assert(igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE); > > > for (i = 0; i < bo_size / sizeof(*map); i++) > > > igt_assert(map[i] == MAGIC_2); > > > @@ -651,7 +651,7 @@ static void test_mocs_suspend_resume(device_t device, enum igt_suspend_state s_s > > > active_time = igt_pm_get_runtime_active_time(device.pci_xe); > > > > > > fw_handle = igt_debugfs_open(device.fd_xe, "forcewake_all", O_RDONLY); > > > - igt_assert(fw_handle >= 0); > > > + igt_assert_lte(0, fw_handle); > > > igt_assert(igt_pm_get_runtime_active_time(device.pci_xe) > > > > active_time); > > > > > > diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c > > > index 51735d887..1d3ce0762 100644 > > > --- a/tests/intel/xe_pm_residency.c > > > +++ b/tests/intel/xe_pm_residency.c > > > @@ -182,7 +182,7 @@ static unsigned long read_idle_residency(int fd, int gt) > > > int gt_fd; > > > > > > gt_fd = xe_sysfs_gt_open(fd, gt); > > > - igt_assert(gt_fd >= 0); > > > + igt_assert_lte(0, gt_fd); > > > igt_assert(igt_sysfs_scanf(gt_fd, "gtidle/idle_residency_ms", "%lu", &residency) == 1); > > > close(gt_fd); > > > > > > @@ -280,7 +280,7 @@ static void toggle_gt_c6(int fd, int n) > > > > > > do { > > > fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY); > > > - igt_assert(fw_handle >= 0); > > > + igt_assert_lte(0, fw_handle); > > > /* check if all gts are in C0 after forcewake is acquired */ > > > xe_for_each_gt(fd, gt) > > > igt_assert_f(!xe_is_gt_in_c6(fd, gt), > > > diff --git a/tests/intel/xe_query.c b/tests/intel/xe_query.c > > > index c13613e0a..c6d88b258 100644 > > > --- a/tests/intel/xe_query.c > > > +++ b/tests/intel/xe_query.c > > > @@ -198,7 +198,7 @@ test_query_engines(int fd) > > > hwe->gt_id); > > > } > > > > > > - igt_assert(i > 0); > > > + igt_assert_lt(0, i); > > > } > > > > > > /** > > > @@ -464,15 +464,15 @@ test_query_gt_topology_l3_bank_mask(int fd) > > > > > > igt_info(" count: %d\n", count); > > > if (intel_get_device_info(dev_id)->graphics_ver < 20) { > > > - igt_assert(count > 0); > > > + igt_assert_lt(0, count); > > > } > > > > > > if (IS_METEORLAKE(dev_id)) > > > - igt_assert((count % 2) == 0); > > > + igt_assert_eq((count % 2), 0); > > > else if (IS_PONTEVECCHIO(dev_id)) > > > - igt_assert((count % 4) == 0); > > > + igt_assert_eq((count % 4), 0); > > > else if (IS_DG2(dev_id)) > > > - igt_assert((count % 8) == 0); > > > + igt_assert_eq((count % 8), 0); > > > } > > > > > > query.size -= sz; > > > @@ -786,7 +786,7 @@ __engine_cycles(int fd, struct drm_xe_engine_class_instance *hwe) > > > if (!((i + 1) % NUM_SNAPSHOTS)) { > > > igt_debug("clock %s\n", clock[index].name); > > > igt_debug("usable %d\n", usable); > > > - igt_assert(usable > 2); > > > + igt_assert_lt(2, usable); > > > usable = 0; > > > } > > > } > > > diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c > > > index a4f6c7a0b..f20a1f474 100644 > > > --- a/tests/intel/xe_vm.c > > > +++ b/tests/intel/xe_vm.c > > > @@ -408,7 +408,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo, > > > int n_exec_queues = n_bo, n_execs = n_bo; > > > int i, b; > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > > > > bo = malloc(sizeof(*bo) * n_bo); > > > igt_assert(bo); > > > @@ -778,7 +778,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs, > > > } *data; > > > int i, b; > > > > > > - igt_assert(n_execs <= BIND_ARRAY_MAX_N_EXEC); > > > + igt_assert_lte(n_execs, BIND_ARRAY_MAX_N_EXEC); > > > > > > vm = xe_vm_create(fd, 0, 0); > > > bo_size = sizeof(*data) * n_execs; > > > @@ -974,7 +974,7 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci, > > > base_addr -= xe_get_default_alignment(fd); > > > } > > > > > > - igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); > > > + igt_assert_lte(n_exec_queues, MAX_N_EXEC_QUEUES); > > > vm = xe_vm_create(fd, 0, 0); > > > > > > if (flags & LARGE_BIND_FLAG_USERPTR) { > > -- > Matt Roper > Graphics Software Engineer > Linux GPU Platform Enablement > Intel Corporation ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH i-g-t 2/2] tests/intel: Apply igt.cocci transforms 2024-07-29 22:02 ` [PATCH i-g-t 2/2] tests/intel: Apply igt.cocci transforms Matt Roper 2024-07-31 12:25 ` [i-g-t,2/2] " Vivekanandan, Balasubramani @ 2024-08-01 21:46 ` Dixit, Ashutosh 1 sibling, 0 replies; 12+ messages in thread From: Dixit, Ashutosh @ 2024-08-01 21:46 UTC (permalink / raw) To: Matt Roper; +Cc: igt-dev On Mon, 29 Jul 2024 15:02:51 -0700, Matt Roper wrote: > > A number of Intel tests are using checks like "igt_assert(x < y)" rather > than using the dedicated comparison assertions that print the actual > values on assertion failure. Run the Intel test directory through > Coccinelle to apply these conversions and also apply some other general > coding style cleanup: > > spatch --in-place --sp-file lib/igt.cocci tests/intel Seems to have caused a bunch of unused variable warnings: $ gcc --version gcc (GCC) 12.2.1 20221121 (Red Hat 12.2.1-4) ninja: Entering directory `build' [34/912] Compiling C object tests/drm_fdinfo.p/intel_drm_fdinfo.c.o In file included from ../lib/igt.h:29, from ../tests/intel/drm_fdinfo.c:28: ../tests/intel/drm_fdinfo.c: In function ‘read_fdinfo’: ../lib/igt_aux.h:229:35: warning: comparison of distinct pointer types lacks a cast 229 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1))) | ^~ ../lib/igt_aux.h:246:10: note: in expansion of macro ‘__typecheck’ 246 | (__typecheck(x, y) && __no_side_effects(x, y)) | ^~~~~~~~~~~ ../lib/igt_aux.h:249:31: note: in expansion of macro ‘__safe_cmp’ 249 | __builtin_choose_expr(__safe_cmp(x, y), \ | ^~~~~~~~~~ ../lib/igt_aux.h:254:25: note: in expansion of macro ‘__careful_cmp’ 254 | #define max(x, y) __careful_cmp(x, y, >, max) | ^~~~~~~~~~~~~ ../tests/intel/drm_fdinfo.c:808:16: note: in expansion of macro ‘max’ 808 | return max(count, 0); | ^~~ [35/912] Compiling C object tests/gem_ctx_create.p/intel_gem_ctx_create.c.o ../tests/intel/gem_ctx_create.c: In function ‘xchg_u32’: ../tests/intel/gem_ctx_create.c:298:30: warning: unused variable ‘tmp’ [-Wunused-variable] 298 | uint32_t *a = array, tmp; | ^~~ ../tests/intel/gem_ctx_create.c: In function ‘xchg_ptr’: ../tests/intel/gem_ctx_create.c:305:28: warning: unused variable ‘tmp’ [-Wunused-variable] 305 | void **a = array, *tmp; | ^~~ [36/912] Compiling C object tests/gem_exec_big.p/intel_gem_exec_big.c.o ../tests/intel/gem_exec_big.c: In function ‘xchg_reloc’: ../tests/intel/gem_exec_big.c:144:46: warning: unused variable ‘tmp’ [-Wunused-variable] 144 | struct drm_i915_gem_relocation_entry tmp; | ^~~ [37/912] Compiling C object tests/gem_exec_gttfill.p/intel_gem_exec_gttfill.c.o ../tests/intel/gem_exec_gttfill.c: In function ‘xchg_batch’: ../tests/intel/gem_exec_gttfill.c:67:22: warning: unused variable ‘tmp’ [-Wunused-variable] 67 | struct batch tmp; | ^~~ [38/912] Compiling C object tests/gem_softpin.p/intel_gem_softpin.c.o ../tests/intel/gem_softpin.c: In function ‘xchg_batch’: ../tests/intel/gem_softpin.c:970:22: warning: unused variable ‘tmp’ [-Wunused-variable] 970 | struct batch tmp; | ^~~ [39/912] Compiling C object tests/gem_tiled_fence_blits.p/intel_gem_tiled_fence_blits.c.o ../tests/intel/gem_tiled_fence_blits.c: In function ‘xchg_u32’: ../tests/intel/gem_tiled_fence_blits.c:159:18: warning: unused variable ‘tmp’ [-Wunused-variable] 159 | uint32_t tmp, *base = array; | ^~~ ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ CI.xeBAT: success for series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} 2024-07-29 22:02 [PATCH i-g-t 1/2] lib: Add u32 variants of igt_assert_{lt,lte} Matt Roper 2024-07-29 22:02 ` [PATCH i-g-t 2/2] tests/intel: Apply igt.cocci transforms Matt Roper @ 2024-07-29 22:43 ` Patchwork 2024-07-29 23:13 ` ✗ Fi.CI.BAT: failure " Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2024-07-29 22:43 UTC (permalink / raw) To: Matt Roper; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 1761 bytes --] == Series Details == Series: series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} URL : https://patchwork.freedesktop.org/series/136636/ State : success == Summary == CI Bug Log - changes from XEIGT_7942_BAT -> XEIGTPW_11488_BAT ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (7 -> 7) ------------------------------ No changes in participating hosts Known issues ------------ Here are the changes found in XEIGTPW_11488_BAT that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@xe_intel_bb@blit-simple: - {bat-lnl-2}: [DMESG-WARN][1] ([Intel XE#1705]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/bat-lnl-2/igt@xe_intel_bb@blit-simple.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/bat-lnl-2/igt@xe_intel_bb@blit-simple.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [Intel XE#1705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1705 Build changes ------------- * IGT: IGT_7942 -> IGTPW_11488 * Linux: xe-1684-3a93d4a1f4872fbdfe43e9b7f1a7dfd9236a642d -> xe-1686-b6f9528c7fffc2f65c8e4969d35d9346fd503c9b IGTPW_11488: 11488 IGT_7942: 0f02dc176959e6296866b1bafd3982e277a5e44b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-1684-3a93d4a1f4872fbdfe43e9b7f1a7dfd9236a642d: 3a93d4a1f4872fbdfe43e9b7f1a7dfd9236a642d xe-1686-b6f9528c7fffc2f65c8e4969d35d9346fd503c9b: b6f9528c7fffc2f65c8e4969d35d9346fd503c9b == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/index.html [-- Attachment #2: Type: text/html, Size: 2347 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} 2024-07-29 22:02 [PATCH i-g-t 1/2] lib: Add u32 variants of igt_assert_{lt,lte} Matt Roper 2024-07-29 22:02 ` [PATCH i-g-t 2/2] tests/intel: Apply igt.cocci transforms Matt Roper 2024-07-29 22:43 ` ✓ CI.xeBAT: success for series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} Patchwork @ 2024-07-29 23:13 ` Patchwork 2024-07-29 23:24 ` Matt Roper 2024-07-30 2:16 ` ✗ CI.xeFULL: " Patchwork 2024-07-31 15:57 ` [PATCH i-g-t 1/2] " Kamil Konieczny 4 siblings, 1 reply; 12+ messages in thread From: Patchwork @ 2024-07-29 23:13 UTC (permalink / raw) To: Matt Roper; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 2711 bytes --] == Series Details == Series: series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} URL : https://patchwork.freedesktop.org/series/136636/ State : failure == Summary == CI Bug Log - changes from CI_DRM_15151 -> IGTPW_11488 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_11488 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_11488, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11488/index.html Participating hosts (41 -> 37) ------------------------------ Additional (1): fi-tgl-1115g4 Missing (5): bat-arlh-3 fi-bsw-n3050 fi-snb-2520m bat-dg2-11 bat-mtlp-6 Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_11488: ### IGT changes ### #### Possible regressions #### * igt@runner@aborted: - fi-tgl-1115g4: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11488/fi-tgl-1115g4/igt@runner@aborted.html Known issues ------------ Here are the changes found in IGTPW_11488 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@hangcheck: - bat-dg2-14: [PASS][2] -> [ABORT][3] ([i915#9500]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15151/bat-dg2-14/igt@i915_selftest@live@hangcheck.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11488/bat-dg2-14/igt@i915_selftest@live@hangcheck.html #### Possible fixes #### * igt@i915_selftest@live@gt_lrc: - bat-twl-2: [INCOMPLETE][4] ([i915#9413]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15151/bat-twl-2/igt@i915_selftest@live@gt_lrc.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11488/bat-twl-2/igt@i915_selftest@live@gt_lrc.html [i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413 [i915#9500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9500 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7942 -> IGTPW_11488 CI-20190529: 20190529 CI_DRM_15151: b6f9528c7fffc2f65c8e4969d35d9346fd503c9b @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_11488: 11488 IGT_7942: 0f02dc176959e6296866b1bafd3982e277a5e44b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11488/index.html [-- Attachment #2: Type: text/html, Size: 3370 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} 2024-07-29 23:13 ` ✗ Fi.CI.BAT: failure " Patchwork @ 2024-07-29 23:24 ` Matt Roper 0 siblings, 0 replies; 12+ messages in thread From: Matt Roper @ 2024-07-29 23:24 UTC (permalink / raw) To: igt-dev On Mon, Jul 29, 2024 at 11:13:23PM +0000, Patchwork wrote: > == Series Details == > > Series: series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} > URL : https://patchwork.freedesktop.org/series/136636/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_15151 -> IGTPW_11488 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with IGTPW_11488 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in IGTPW_11488, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11488/index.html > > Participating hosts (41 -> 37) > ------------------------------ > > Additional (1): fi-tgl-1115g4 > Missing (5): bat-arlh-3 fi-bsw-n3050 fi-snb-2520m bat-dg2-11 bat-mtlp-6 > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in IGTPW_11488: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@runner@aborted: > - fi-tgl-1115g4: NOTRUN -> [FAIL][1] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11488/fi-tgl-1115g4/igt@runner@aborted.html "WARNING: possible circular locking dependency detected" while the system is loading. Not caused by the graphics driver, and not caused by the IGT changes here. Matt > > > Known issues > ------------ > > Here are the changes found in IGTPW_11488 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@i915_selftest@live@hangcheck: > - bat-dg2-14: [PASS][2] -> [ABORT][3] ([i915#9500]) > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15151/bat-dg2-14/igt@i915_selftest@live@hangcheck.html > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11488/bat-dg2-14/igt@i915_selftest@live@hangcheck.html > > > #### Possible fixes #### > > * igt@i915_selftest@live@gt_lrc: > - bat-twl-2: [INCOMPLETE][4] ([i915#9413]) -> [PASS][5] > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15151/bat-twl-2/igt@i915_selftest@live@gt_lrc.html > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11488/bat-twl-2/igt@i915_selftest@live@gt_lrc.html > > > [i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413 > [i915#9500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9500 > > > Build changes > ------------- > > * CI: CI-20190529 -> None > * IGT: IGT_7942 -> IGTPW_11488 > > CI-20190529: 20190529 > CI_DRM_15151: b6f9528c7fffc2f65c8e4969d35d9346fd503c9b @ git://anongit.freedesktop.org/gfx-ci/linux > IGTPW_11488: 11488 > IGT_7942: 0f02dc176959e6296866b1bafd3982e277a5e44b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11488/index.html -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ CI.xeFULL: failure for series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} 2024-07-29 22:02 [PATCH i-g-t 1/2] lib: Add u32 variants of igt_assert_{lt,lte} Matt Roper ` (2 preceding siblings ...) 2024-07-29 23:13 ` ✗ Fi.CI.BAT: failure " Patchwork @ 2024-07-30 2:16 ` Patchwork 2024-07-30 15:44 ` Matt Roper 2024-07-31 15:57 ` [PATCH i-g-t 1/2] " Kamil Konieczny 4 siblings, 1 reply; 12+ messages in thread From: Patchwork @ 2024-07-30 2:16 UTC (permalink / raw) To: Matt Roper; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 128732 bytes --] == Series Details == Series: series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} URL : https://patchwork.freedesktop.org/series/136636/ State : failure == Summary == CI Bug Log - changes from XEIGT_7942_full -> XEIGTPW_11488_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with XEIGTPW_11488_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in XEIGTPW_11488_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (3 -> 3) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in XEIGTPW_11488_full: ### IGT changes ### #### Possible regressions #### * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-6: - shard-dg2-set2: [PASS][1] -> [FAIL][2] +2 other tests fail [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-6.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-6.html * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs: - shard-lnl: NOTRUN -> [SKIP][3] +21 other tests skip [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html * igt@kms_invalid_mode@uint-max-clock: - shard-lnl: [PASS][4] -> [SKIP][5] +63 other tests skip [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_invalid_mode@uint-max-clock.html [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_invalid_mode@uint-max-clock.html * igt@kms_pipe_crc_basic@suspend-read-crc: - shard-lnl: [PASS][6] -> [DMESG-WARN][7] +1 other test dmesg-warn [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_pipe_crc_basic@suspend-read-crc.html [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_pipe_crc_basic@suspend-read-crc.html * igt@xe_live_ktest@xe_dma_buf: - shard-lnl: [PASS][8] -> [FAIL][9] +1 other test fail [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@xe_live_ktest@xe_dma_buf.html [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@xe_live_ktest@xe_dma_buf.html * igt@xe_pm@s4-basic: - shard-dg2-set2: [PASS][10] -> [DMESG-WARN][11] +1 other test dmesg-warn [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_pm@s4-basic.html [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_pm@s4-basic.html #### Warnings #### * igt@core_hotunplug@hotunbind-rebind: - shard-lnl: [ABORT][12] -> [SKIP][13] [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@core_hotunplug@hotunbind-rebind.html [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@core_hotunplug@hotunbind-rebind.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-lnl: [FAIL][14] ([Intel XE#1659]) -> [SKIP][15] [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@linear-32bpp-rotate-90: - shard-lnl: [SKIP][16] ([Intel XE#1407]) -> [SKIP][17] +2 other tests skip [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_big_fb@linear-32bpp-rotate-90.html [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_big_fb@linear-32bpp-rotate-90.html * igt@kms_big_fb@y-tiled-32bpp-rotate-0: - shard-lnl: [SKIP][18] ([Intel XE#1124]) -> [SKIP][19] +7 other tests skip [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html * igt@kms_bw@linear-tiling-4-displays-2560x1440p: - shard-lnl: [SKIP][20] ([Intel XE#1512]) -> [SKIP][21] [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-2/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs: - shard-lnl: [SKIP][22] ([Intel XE#1399]) -> [SKIP][23] +11 other tests skip [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html * igt@kms_chamelium_color@ctm-0-50: - shard-lnl: [SKIP][24] ([Intel XE#306]) -> [SKIP][25] [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_chamelium_color@ctm-0-50.html [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_chamelium_color@ctm-0-50.html * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k: - shard-lnl: [SKIP][26] ([Intel XE#373]) -> [SKIP][27] +6 other tests skip [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-2/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html * igt@kms_content_protection@dp-mst-lic-type-1: - shard-lnl: [SKIP][28] ([Intel XE#307]) -> [SKIP][29] [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_content_protection@dp-mst-lic-type-1.html [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_content_protection@dp-mst-lic-type-1.html * igt@kms_cursor_crc@cursor-onscreen-128x42: - shard-lnl: [SKIP][30] ([Intel XE#1424]) -> [SKIP][31] +3 other tests skip [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_cursor_crc@cursor-onscreen-128x42.html [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_cursor_crc@cursor-onscreen-128x42.html * igt@kms_cursor_crc@cursor-sliding-512x170: - shard-lnl: [SKIP][32] ([Intel XE#1413]) -> [SKIP][33] [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_cursor_crc@cursor-sliding-512x170.html [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_cursor_crc@cursor-sliding-512x170.html * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-dg2-set2: [SKIP][34] ([Intel XE#1201] / [i915#2575]) -> [INCOMPLETE][35] [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-lnl: [SKIP][36] ([Intel XE#309]) -> [SKIP][37] +2 other tests skip [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_feature_discovery@display-2x: - shard-lnl: [SKIP][38] ([Intel XE#702]) -> [SKIP][39] [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_feature_discovery@display-2x.html [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_feature_discovery@display-2x.html * igt@kms_feature_discovery@display-3x: - shard-lnl: [SKIP][40] ([Intel XE#703]) -> [SKIP][41] [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_feature_discovery@display-3x.html [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_feature_discovery@display-3x.html * igt@kms_flip@2x-flip-vs-dpms: - shard-lnl: [SKIP][42] ([Intel XE#1421]) -> [SKIP][43] +4 other tests skip [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_flip@2x-flip-vs-dpms.html [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_flip@2x-flip-vs-dpms.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling: - shard-lnl: [SKIP][44] ([Intel XE#1401] / [Intel XE#1745]) -> [SKIP][45] +2 other tests skip [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling: - shard-lnl: [SKIP][46] ([Intel XE#1397] / [Intel XE#1745]) -> [SKIP][47] [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt: - shard-lnl: [SKIP][48] ([Intel XE#656]) -> [SKIP][49] +21 other tests skip [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@fbc-tiling-y: - shard-lnl: [SKIP][50] ([Intel XE#1469]) -> [SKIP][51] [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-tiling-y.html [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_frontbuffer_tracking@fbc-tiling-y.html * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt: - shard-lnl: [SKIP][52] ([Intel XE#651]) -> [SKIP][53] +10 other tests skip [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html * igt@kms_plane_multiple@tiling-y: - shard-lnl: [SKIP][54] ([Intel XE#599]) -> [SKIP][55] +3 other tests skip [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_plane_multiple@tiling-y.html [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_plane_multiple@tiling-y.html * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation: - shard-lnl: [SKIP][56] ([Intel XE#498]) -> [SKIP][57] [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation.html [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation.html * igt@kms_plane_scaling@planes-downscale-factor-0-5: - shard-lnl: [SKIP][58] ([Intel XE#2318]) -> [SKIP][59] +1 other test skip [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_plane_scaling@planes-downscale-factor-0-5.html [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_plane_scaling@planes-downscale-factor-0-5.html * igt@kms_pm_dc@deep-pkgc: - shard-lnl: [FAIL][60] ([Intel XE#2029]) -> [SKIP][61] [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-2/igt@kms_pm_dc@deep-pkgc.html [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_pm_dc@deep-pkgc.html * igt@kms_psr@pr-no-drrs: - shard-lnl: [SKIP][62] ([Intel XE#1406]) -> [SKIP][63] +4 other tests skip [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_psr@pr-no-drrs.html [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_psr@pr-no-drrs.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270: - shard-lnl: [SKIP][64] ([Intel XE#1437]) -> [SKIP][65] +1 other test skip [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html * igt@kms_vrr@seamless-rr-switch-drrs: - shard-lnl: [SKIP][66] ([Intel XE#1499] / [Intel XE#599]) -> [SKIP][67] [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_vrr@seamless-rr-switch-drrs.html [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-drrs.html * igt@kms_writeback@writeback-check-output: - shard-lnl: [SKIP][68] ([Intel XE#756]) -> [SKIP][69] [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_writeback@writeback-check-output.html [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_writeback@writeback-check-output.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p}: - shard-lnl: [SKIP][70] ([Intel XE#2191]) -> [SKIP][71] [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html * {igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p}: - shard-lnl: [SKIP][72] ([Intel XE#1512]) -> [SKIP][73] [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html * {igt@kms_vrr@cmrr}: - shard-lnl: [PASS][74] -> [SKIP][75] [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_vrr@cmrr.html [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_vrr@cmrr.html * {igt@xe_oa@invalid-remove-userspace-config}: - shard-lnl: NOTRUN -> [SKIP][76] +3 other tests skip [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@xe_oa@invalid-remove-userspace-config.html * {igt@xe_oa@non-zero-reason}: - shard-dg2-set2: [SKIP][77] ([Intel XE#1201]) -> [SKIP][78] [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@xe_oa@non-zero-reason.html [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_oa@non-zero-reason.html * {igt@xe_oa@oa-unit-concurrent-oa-buffer-read}: - shard-dg2-set2: NOTRUN -> [SKIP][79] [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_oa@oa-unit-concurrent-oa-buffer-read.html Known issues ------------ Here are the changes found in XEIGTPW_11488_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6: - shard-dg2-set2: [PASS][80] -> [FAIL][81] ([Intel XE#1426]) +2 other tests fail [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6.html [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6.html * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1: - shard-lnl: [PASS][82] -> [FAIL][83] ([Intel XE#1426]) +3 other tests fail [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html * igt@kms_big_fb@4-tiled-16bpp-rotate-270: - shard-lnl: NOTRUN -> [SKIP][84] ([Intel XE#1407]) +3 other tests skip [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html - shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#316]) [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html * igt@kms_big_fb@4-tiled-addfb-size-overflow: - shard-dg2-set2: [PASS][86] -> [SKIP][87] ([Intel XE#1201]) +23 other tests skip [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_big_fb@4-tiled-addfb-size-overflow.html [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_big_fb@4-tiled-addfb-size-overflow.html * igt@kms_big_fb@x-tiled-64bpp-rotate-90: - shard-dg2-set2: NOTRUN -> [SKIP][88] ([Intel XE#1201] / [Intel XE#316]) +2 other tests skip [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html * igt@kms_big_fb@y-tiled-32bpp-rotate-180: - shard-lnl: NOTRUN -> [SKIP][89] ([Intel XE#1124]) +6 other tests skip [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-dg2-set2: NOTRUN -> [SKIP][90] ([Intel XE#1124] / [Intel XE#1201]) +7 other tests skip [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html * igt@kms_big_fb@yf-tiled-addfb-size-overflow: - shard-dg2-set2: NOTRUN -> [SKIP][91] ([Intel XE#610]) [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180: - shard-dg2-set2: NOTRUN -> [SKIP][92] ([Intel XE#1124]) [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html * igt@kms_bw@linear-tiling-2-displays-2560x1440p: - shard-dg2-set2: NOTRUN -> [SKIP][93] ([Intel XE#1201] / [Intel XE#367]) [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html - shard-lnl: NOTRUN -> [SKIP][94] ([Intel XE#367]) [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html * igt@kms_ccs@bad-aux-stride-y-tiled-ccs: - shard-lnl: NOTRUN -> [SKIP][95] ([Intel XE#1399]) +4 other tests skip [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_ccs@bad-aux-stride-y-tiled-ccs.html * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-a-dp-4: - shard-dg2-set2: NOTRUN -> [SKIP][96] ([Intel XE#787]) +6 other tests skip [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-a-dp-4.html * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-d-dp-4: - shard-dg2-set2: NOTRUN -> [SKIP][97] ([Intel XE#455] / [Intel XE#787]) [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-d-dp-4.html * igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-dp-4: - shard-dg2-set2: NOTRUN -> [SKIP][98] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +22 other tests skip [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-dp-4.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6: - shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#1201] / [Intel XE#787]) +97 other tests skip [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html * igt@kms_chamelium_color@degamma: - shard-dg2-set2: NOTRUN -> [SKIP][100] ([Intel XE#1201] / [Intel XE#306]) +2 other tests skip [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_chamelium_color@degamma.html - shard-lnl: NOTRUN -> [SKIP][101] ([Intel XE#306]) +1 other test skip [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_chamelium_color@degamma.html * igt@kms_chamelium_frames@hdmi-cmp-planes-random: - shard-lnl: NOTRUN -> [SKIP][102] ([Intel XE#373]) +5 other tests skip [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_chamelium_frames@hdmi-cmp-planes-random.html * igt@kms_chamelium_frames@vga-frame-dump: - shard-dg2-set2: NOTRUN -> [SKIP][103] ([Intel XE#1201] / [Intel XE#373]) +8 other tests skip [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_chamelium_frames@vga-frame-dump.html * igt@kms_cursor_crc@cursor-rapid-movement-512x170: - shard-dg2-set2: NOTRUN -> [SKIP][104] ([Intel XE#1201] / [Intel XE#308]) +1 other test skip [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html - shard-lnl: NOTRUN -> [SKIP][105] ([Intel XE#1413]) +1 other test skip [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html * igt@kms_cursor_crc@cursor-sliding-64x21: - shard-lnl: NOTRUN -> [SKIP][106] ([Intel XE#1424]) [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_cursor_crc@cursor-sliding-64x21.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-dg2-set2: NOTRUN -> [SKIP][107] ([Intel XE#1201] / [Intel XE#323]) [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic: - shard-lnl: NOTRUN -> [SKIP][108] ([Intel XE#309]) [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6: - shard-dg2-set2: NOTRUN -> [SKIP][109] ([Intel XE#1201] / [i915#3804]) [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6.html * igt@kms_fbcon_fbt@psr: - shard-dg2-set2: NOTRUN -> [SKIP][110] ([Intel XE#1201] / [Intel XE#776]) [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_fbcon_fbt@psr.html * igt@kms_flip@2x-flip-vs-suspend-interruptible: - shard-lnl: NOTRUN -> [SKIP][111] ([Intel XE#1421]) +2 other tests skip [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_flip@2x-flip-vs-suspend-interruptible.html * igt@kms_flip@flip-vs-absolute-wf_vblank: - shard-lnl: [PASS][112] -> [FAIL][113] ([Intel XE#886]) +2 other tests fail [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_flip@flip-vs-absolute-wf_vblank.html [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_flip@flip-vs-absolute-wf_vblank.html * igt@kms_flip@flip-vs-suspend@a-hdmi-a6: - shard-dg2-set2: NOTRUN -> [DMESG-WARN][114] ([Intel XE#1551]) +1 other test dmesg-warn [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_flip@flip-vs-suspend@a-hdmi-a6.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling: - shard-lnl: NOTRUN -> [SKIP][115] ([Intel XE#1397] / [Intel XE#1745]) [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling: - shard-lnl: [PASS][116] -> [SKIP][117] ([Intel XE#2351]) [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling.html [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode: - shard-lnl: NOTRUN -> [SKIP][118] ([Intel XE#1397]) +3 other tests skip [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling: - shard-lnl: NOTRUN -> [SKIP][119] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode: - shard-lnl: NOTRUN -> [SKIP][120] ([Intel XE#1401]) +2 other tests skip [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render: - shard-lnl: NOTRUN -> [SKIP][121] ([Intel XE#651]) +8 other tests skip [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render.html * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc: - shard-dg2-set2: NOTRUN -> [SKIP][122] ([Intel XE#1201] / [Intel XE#651]) +17 other tests skip [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt: - shard-lnl: NOTRUN -> [SKIP][123] ([Intel XE#656]) +16 other tests skip [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt: - shard-dg2-set2: NOTRUN -> [SKIP][124] ([Intel XE#651]) [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move: - shard-dg2-set2: NOTRUN -> [SKIP][125] ([Intel XE#653]) +1 other test skip [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt: - shard-lnl: NOTRUN -> [SKIP][126] ([Intel XE#2351]) [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-suspend: - shard-lnl: [PASS][127] -> [FAIL][128] ([Intel XE#2028]) [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc: - shard-dg2-set2: NOTRUN -> [SKIP][129] ([Intel XE#1201] / [Intel XE#653]) +22 other tests skip [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html * igt@kms_hdmi_inject@inject-audio: - shard-dg2-set2: NOTRUN -> [SKIP][130] ([Intel XE#1201] / [Intel XE#417]) [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_hdmi_inject@inject-audio.html - shard-lnl: NOTRUN -> [SKIP][131] ([Intel XE#1470]) [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_hdmi_inject@inject-audio.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - shard-dg2-set2: NOTRUN -> [SKIP][132] ([Intel XE#1201] / [i915#2575]) +10 other tests skip [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@suspend-read-crc: - shard-dg2-set2: [PASS][133] -> [DMESG-WARN][134] ([Intel XE#1162]) [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_pipe_crc_basic@suspend-read-crc.html [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_pipe_crc_basic@suspend-read-crc.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-4: - shard-dg2-set2: [PASS][135] -> [DMESG-WARN][136] ([Intel XE#2019]) [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-4.html [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-4.html * igt@kms_plane@plane-position-hole-dpms: - shard-lnl: [PASS][137] -> [DMESG-WARN][138] ([Intel XE#324]) [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_plane@plane-position-hole-dpms.html [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_plane@plane-position-hole-dpms.html * igt@kms_plane_lowres@tiling-x@pipe-b-edp-1: - shard-lnl: NOTRUN -> [SKIP][139] ([Intel XE#599]) +3 other tests skip [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_plane_lowres@tiling-x@pipe-b-edp-1.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-c-edp-1: - shard-lnl: NOTRUN -> [SKIP][140] ([Intel XE#498]) +3 other tests skip [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-c-edp-1.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling: - shard-dg2-set2: NOTRUN -> [SKIP][141] ([Intel XE#2318] / [Intel XE#455]) [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-6: - shard-dg2-set2: NOTRUN -> [SKIP][142] ([Intel XE#2318]) +2 other tests skip [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-6.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-6: - shard-dg2-set2: NOTRUN -> [SKIP][143] ([Intel XE#455]) +2 other tests skip [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-6.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25: - shard-dg2-set2: NOTRUN -> [SKIP][144] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) +1 other test skip [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1: - shard-lnl: NOTRUN -> [SKIP][145] ([Intel XE#2318]) +14 other tests skip [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-6: - shard-dg2-set2: NOTRUN -> [SKIP][146] ([Intel XE#1201] / [Intel XE#2318]) +5 other tests skip [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-6.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-6: - shard-dg2-set2: NOTRUN -> [SKIP][147] ([Intel XE#1201] / [Intel XE#455]) +10 other tests skip [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-6.html * igt@kms_pm_rpm@modeset-non-lpsp: - shard-lnl: NOTRUN -> [SKIP][148] ([Intel XE#1439]) [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_pm_rpm@modeset-non-lpsp.html * igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-sf: - shard-dg2-set2: NOTRUN -> [SKIP][149] ([Intel XE#1201] / [Intel XE#1489]) [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-sf.html * igt@kms_psr2_su@page_flip-p010: - shard-dg2-set2: NOTRUN -> [SKIP][150] ([Intel XE#1122] / [Intel XE#1201]) [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_psr2_su@page_flip-p010.html - shard-lnl: NOTRUN -> [SKIP][151] ([Intel XE#1128]) [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_psr2_su@page_flip-p010.html * igt@kms_psr@fbc-psr2-sprite-plane-move: - shard-dg2-set2: NOTRUN -> [SKIP][152] ([Intel XE#1201] / [Intel XE#929]) +11 other tests skip [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_psr@fbc-psr2-sprite-plane-move.html * igt@kms_psr@fbc-psr2-suspend: - shard-dg2-set2: NOTRUN -> [SKIP][153] ([Intel XE#1201]) +23 other tests skip [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_psr@fbc-psr2-suspend.html * igt@kms_psr@pr-primary-blt: - shard-lnl: NOTRUN -> [SKIP][154] ([Intel XE#1406]) +1 other test skip [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_psr@pr-primary-blt.html * igt@kms_psr@psr2-no-drrs: - shard-dg2-set2: NOTRUN -> [SKIP][155] ([Intel XE#929]) +2 other tests skip [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_psr@psr2-no-drrs.html * igt@kms_rmfb@close-fd@pipe-a-edp-1: - shard-lnl: NOTRUN -> [FAIL][156] ([Intel XE#294]) [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_rmfb@close-fd@pipe-a-edp-1.html * igt@kms_rmfb@close-fd@pipe-b-dp-4: - shard-dg2-set2: NOTRUN -> [FAIL][157] ([Intel XE#294]) +1 other test fail [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_rmfb@close-fd@pipe-b-dp-4.html * igt@kms_vblank@ts-continuation-suspend: - shard-dg2-set2: NOTRUN -> [DMESG-WARN][158] ([Intel XE#2019]) +3 other tests dmesg-warn [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_vblank@ts-continuation-suspend.html * igt@kms_vblank@wait-forked-busy-hang: - shard-dg2-set2: [PASS][159] -> [SKIP][160] ([Intel XE#1201] / [i915#2575]) +45 other tests skip [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_vblank@wait-forked-busy-hang.html [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_vblank@wait-forked-busy-hang.html * igt@kms_writeback@writeback-check-output-xrgb2101010: - shard-dg2-set2: NOTRUN -> [SKIP][161] ([Intel XE#1201] / [Intel XE#756]) [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_writeback@writeback-check-output-xrgb2101010.html * igt@kms_writeback@writeback-fb-id: - shard-lnl: NOTRUN -> [SKIP][162] ([Intel XE#756]) [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_writeback@writeback-fb-id.html * igt@xe_copy_basic@mem-copy-linear-0xfffe: - shard-dg2-set2: NOTRUN -> [SKIP][163] ([Intel XE#1123]) [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_copy_basic@mem-copy-linear-0xfffe.html * igt@xe_copy_basic@mem-set-linear-0xfffe: - shard-dg2-set2: NOTRUN -> [SKIP][164] ([Intel XE#1126] / [Intel XE#1201]) [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@xe_copy_basic@mem-set-linear-0xfffe.html * igt@xe_evict@evict-beng-cm-threads-large: - shard-dg2-set2: NOTRUN -> [INCOMPLETE][165] ([Intel XE#1473] / [Intel XE#392]) [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_evict@evict-beng-cm-threads-large.html * igt@xe_evict@evict-beng-cm-threads-small-multi-vm: - shard-lnl: NOTRUN -> [SKIP][166] ([Intel XE#688]) +4 other tests skip [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@xe_evict@evict-beng-cm-threads-small-multi-vm.html * igt@xe_evict@evict-beng-large-external-cm: - shard-lnl: NOTRUN -> [SKIP][167] ([Intel XE#1130]) +12 other tests skip [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@xe_evict@evict-beng-large-external-cm.html * igt@xe_evict@evict-beng-large-multi-vm-cm: - shard-dg2-set2: NOTRUN -> [FAIL][168] ([Intel XE#1600]) [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@xe_evict@evict-beng-large-multi-vm-cm.html * igt@xe_evict@evict-beng-mixed-many-threads-small: - shard-dg2-set2: [PASS][169] -> [TIMEOUT][170] ([Intel XE#1473] / [Intel XE#402]) [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@xe_evict@evict-beng-mixed-many-threads-small.html [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_evict@evict-beng-mixed-many-threads-small.html * igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-reopen: - shard-dg2-set2: NOTRUN -> [SKIP][171] ([Intel XE#1130] / [Intel XE#1201]) +24 other tests skip [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-reopen.html * igt@xe_exec_balancer@many-cm-virtual-userptr-invalidate: - shard-dg2-set2: [PASS][172] -> [SKIP][173] ([Intel XE#1130] / [Intel XE#1201]) +81 other tests skip [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_exec_balancer@many-cm-virtual-userptr-invalidate.html [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_exec_balancer@many-cm-virtual-userptr-invalidate.html * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race: - shard-lnl: NOTRUN -> [SKIP][174] ([Intel XE#1392]) +5 other tests skip [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html * igt@xe_exec_basic@no-exec-null-defer-bind: - shard-lnl: [PASS][175] -> [SKIP][176] ([Intel XE#1130]) +95 other tests skip [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@xe_exec_basic@no-exec-null-defer-bind.html [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@xe_exec_basic@no-exec-null-defer-bind.html * igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-prefetch: - shard-dg2-set2: NOTRUN -> [SKIP][177] ([Intel XE#1201] / [Intel XE#288]) +15 other tests skip [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-prefetch.html * igt@xe_exec_fault_mode@once-rebind-prefetch: - shard-dg2-set2: NOTRUN -> [SKIP][178] ([Intel XE#288]) +1 other test skip [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_exec_fault_mode@once-rebind-prefetch.html * igt@xe_huc_copy@huc_copy: - shard-dg2-set2: NOTRUN -> [SKIP][179] ([Intel XE#1201] / [Intel XE#255]) [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_huc_copy@huc_copy.html * igt@xe_module_load@force-load: - shard-dg2-set2: NOTRUN -> [SKIP][180] ([Intel XE#1201] / [Intel XE#378]) [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_module_load@force-load.html * igt@xe_pat@display-vs-wb-transient: - shard-dg2-set2: NOTRUN -> [SKIP][181] ([Intel XE#1201] / [Intel XE#1337]) [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_pat@display-vs-wb-transient.html * igt@xe_pat@pat-index-xelpg: - shard-dg2-set2: NOTRUN -> [SKIP][182] ([Intel XE#1201] / [Intel XE#979]) [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_pat@pat-index-xelpg.html - shard-lnl: NOTRUN -> [SKIP][183] ([Intel XE#979]) [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@xe_pat@pat-index-xelpg.html * igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p: - shard-dg2-set2: NOTRUN -> [FAIL][184] ([Intel XE#1173]) [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html * igt@xe_pm@s2idle-basic-exec: - shard-lnl: [PASS][185] -> [FAIL][186] ([Intel XE#1924] / [Intel XE#2028]) [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@xe_pm@s2idle-basic-exec.html [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@xe_pm@s2idle-basic-exec.html * igt@xe_pm@s3-vm-bind-userptr: - shard-dg2-set2: NOTRUN -> [DMESG-WARN][187] ([Intel XE#1551] / [Intel XE#569]) +1 other test dmesg-warn [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_pm@s3-vm-bind-userptr.html - shard-lnl: NOTRUN -> [SKIP][188] ([Intel XE#584]) [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@xe_pm@s3-vm-bind-userptr.html * igt@xe_query@multigpu-query-uc-fw-version-huc: - shard-dg2-set2: NOTRUN -> [SKIP][189] ([Intel XE#1201] / [Intel XE#944]) +2 other tests skip [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_query@multigpu-query-uc-fw-version-huc.html - shard-lnl: NOTRUN -> [SKIP][190] ([Intel XE#944]) +2 other tests skip [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@xe_query@multigpu-query-uc-fw-version-huc.html #### Possible fixes #### * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-lnl: [FAIL][191] ([Intel XE#1659]) -> [PASS][192] [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-dg2-set2: [DMESG-WARN][193] -> [PASS][194] [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-lnl: [SKIP][195] ([Intel XE#2351]) -> [PASS][196] +1 other test pass [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_cursor_crc@cursor-sliding-64x64: - shard-dg2-set2: [SKIP][197] ([Intel XE#1201] / [i915#2575]) -> [PASS][198] +43 other tests pass [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_cursor_crc@cursor-sliding-64x64.html [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_cursor_crc@cursor-sliding-64x64.html * igt@kms_flip@flip-vs-wf_vblank-interruptible: - shard-lnl: [SKIP][199] ([Intel XE#2366]) -> [PASS][200] +2 other tests pass [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_flip@flip-vs-wf_vblank-interruptible.html [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_flip@flip-vs-wf_vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc: - shard-dg2-set2: [SKIP][201] ([Intel XE#1201]) -> [PASS][202] +24 other tests pass [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt: - shard-lnl: [SKIP][203] -> [PASS][204] +65 other tests pass [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html * igt@kms_hdr@bpc-switch-suspend@pipe-a-edp-1: - shard-lnl: [FAIL][205] ([Intel XE#2028]) -> [PASS][206] +1 other test pass [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_hdr@bpc-switch-suspend@pipe-a-edp-1.html [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_hdr@bpc-switch-suspend@pipe-a-edp-1.html * {igt@kms_plane@plane-position-hole@pipe-a-plane-2}: - shard-lnl: [DMESG-FAIL][207] ([Intel XE#324]) -> [PASS][208] [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_plane@plane-position-hole@pipe-a-plane-2.html [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_plane@plane-position-hole@pipe-a-plane-2.html * {igt@kms_plane@plane-position-hole@pipe-b-plane-4}: - shard-lnl: [DMESG-WARN][209] ([Intel XE#324]) -> [PASS][210] [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_plane@plane-position-hole@pipe-b-plane-4.html [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_plane@plane-position-hole@pipe-b-plane-4.html * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6: - shard-dg2-set2: [FAIL][211] ([Intel XE#361]) -> [PASS][212] [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html * igt@kms_pm_backlight@fade-with-suspend: - shard-lnl: [INCOMPLETE][213] -> [PASS][214] [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_pm_backlight@fade-with-suspend.html [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_pm_backlight@fade-with-suspend.html * igt@kms_universal_plane@cursor-fb-leak: - shard-dg2-set2: [FAIL][215] ([Intel XE#771] / [Intel XE#899]) -> [PASS][216] [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_universal_plane@cursor-fb-leak.html [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_universal_plane@cursor-fb-leak.html * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6: - shard-dg2-set2: [FAIL][217] ([Intel XE#899]) -> [PASS][218] +1 other test pass [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html * igt@xe_evict@evict-mixed-threads-large: - shard-dg2-set2: [INCOMPLETE][219] ([Intel XE#1195] / [Intel XE#1473] / [Intel XE#392]) -> [PASS][220] +1 other test pass [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_evict@evict-mixed-threads-large.html [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@xe_evict@evict-mixed-threads-large.html * igt@xe_exec_basic@multigpu-no-exec-basic: - shard-dg2-set2: [SKIP][221] ([Intel XE#1130] / [Intel XE#1201]) -> [PASS][222] +64 other tests pass [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_exec_basic@multigpu-no-exec-basic.html [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_exec_basic@multigpu-no-exec-basic.html * igt@xe_exec_threads@threads-userptr-rebind-err: - shard-lnl: [SKIP][223] ([Intel XE#1130]) -> [PASS][224] +79 other tests pass [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@xe_exec_threads@threads-userptr-rebind-err.html [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@xe_exec_threads@threads-userptr-rebind-err.html * igt@xe_gt_freq@freq_fixed_exec: - shard-dg2-set2: [FAIL][225] ([Intel XE#2262]) -> [PASS][226] [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_gt_freq@freq_fixed_exec.html [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_gt_freq@freq_fixed_exec.html * igt@xe_gt_freq@freq_reset_multiple: - shard-lnl: [INCOMPLETE][227] ([Intel XE#1620] / [Intel XE#1760]) -> [PASS][228] [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@xe_gt_freq@freq_reset_multiple.html [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@xe_gt_freq@freq_reset_multiple.html * igt@xe_live_ktest@xe_bo: - shard-dg2-set2: [SKIP][229] ([Intel XE#1192] / [Intel XE#1201]) -> [PASS][230] [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_live_ktest@xe_bo.html [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_live_ktest@xe_bo.html * igt@xe_pm@s2idle-basic: - shard-lnl: [FAIL][231] ([Intel XE#1924] / [Intel XE#2028]) -> [PASS][232] [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@xe_pm@s2idle-basic.html [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@xe_pm@s2idle-basic.html * igt@xe_pm@s4-multiple-execs: - shard-lnl: [ABORT][233] ([Intel XE#1358] / [Intel XE#1794]) -> [PASS][234] [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-2/igt@xe_pm@s4-multiple-execs.html [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@xe_pm@s4-multiple-execs.html * igt@xe_pm@s4-vm-bind-prefetch: - shard-dg2-set2: [DMESG-WARN][235] ([Intel XE#2019]) -> [PASS][236] +1 other test pass [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_pm@s4-vm-bind-prefetch.html [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_pm@s4-vm-bind-prefetch.html * igt@xe_pm@s4-vm-bind-unbind-all: - shard-dg2-set2: [DMESG-WARN][237] ([Intel XE#2019] / [Intel XE#2280]) -> [PASS][238] [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_pm@s4-vm-bind-unbind-all.html [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_pm@s4-vm-bind-unbind-all.html #### Warnings #### * igt@core_hotunplug@hotunbind-rebind: - shard-dg2-set2: [ABORT][239] -> [SKIP][240] ([Intel XE#1201]) [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@core_hotunplug@hotunbind-rebind.html [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@core_hotunplug@hotunbind-rebind.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - shard-dg2-set2: [SKIP][241] ([Intel XE#623]) -> [SKIP][242] ([Intel XE#1201] / [Intel XE#623]) [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html * igt@kms_big_fb@4-tiled-64bpp-rotate-90: - shard-dg2-set2: [SKIP][243] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][244] ([Intel XE#316]) [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html * igt@kms_big_fb@linear-16bpp-rotate-270: - shard-dg2-set2: [SKIP][245] ([Intel XE#316]) -> [SKIP][246] ([Intel XE#1201] / [Intel XE#316]) +1 other test skip [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-270.html [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_big_fb@linear-16bpp-rotate-270.html * igt@kms_big_fb@x-tiled-16bpp-rotate-90: - shard-dg2-set2: [SKIP][247] ([Intel XE#316]) -> [SKIP][248] ([Intel XE#1201]) [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html * igt@kms_big_fb@x-tiled-32bpp-rotate-270: - shard-dg2-set2: [SKIP][249] ([Intel XE#1201]) -> [SKIP][250] ([Intel XE#1201] / [Intel XE#316]) +2 other tests skip [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html - shard-lnl: [SKIP][251] -> [SKIP][252] ([Intel XE#1407]) +2 other tests skip [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html * igt@kms_big_fb@x-tiled-8bpp-rotate-270: - shard-dg2-set2: [SKIP][253] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][254] ([Intel XE#1201]) +1 other test skip [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html * igt@kms_big_fb@y-tiled-8bpp-rotate-270: - shard-dg2-set2: [SKIP][255] ([Intel XE#1201]) -> [SKIP][256] ([Intel XE#1124] / [Intel XE#1201]) +2 other tests skip [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html * igt@kms_big_fb@y-tiled-addfb: - shard-dg2-set2: [SKIP][257] ([Intel XE#1201]) -> [SKIP][258] ([Intel XE#1201] / [Intel XE#619]) [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_big_fb@y-tiled-addfb.html [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_big_fb@y-tiled-addfb.html - shard-lnl: [SKIP][259] -> [SKIP][260] ([Intel XE#1467]) [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_big_fb@y-tiled-addfb.html [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_big_fb@y-tiled-addfb.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0: - shard-dg2-set2: [SKIP][261] ([Intel XE#1124]) -> [SKIP][262] ([Intel XE#1124] / [Intel XE#1201]) +6 other tests skip [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-dg2-set2: [SKIP][263] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][264] ([Intel XE#1124]) +1 other test skip [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-90: - shard-dg2-set2: [SKIP][265] ([Intel XE#1201]) -> [SKIP][266] ([Intel XE#1124]) [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html - shard-lnl: [SKIP][267] -> [SKIP][268] ([Intel XE#1124]) +3 other tests skip [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-addfb-size-overflow: - shard-lnl: [SKIP][269] -> [SKIP][270] ([Intel XE#1428]) [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-dg2-set2: [SKIP][271] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][272] ([Intel XE#1201]) +6 other tests skip [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html * igt@kms_big_joiner@basic: - shard-dg2-set2: [SKIP][273] ([Intel XE#1201]) -> [SKIP][274] ([Intel XE#1201] / [Intel XE#346]) [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_big_joiner@basic.html [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_big_joiner@basic.html - shard-lnl: [SKIP][275] -> [SKIP][276] ([Intel XE#346]) [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_big_joiner@basic.html [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_big_joiner@basic.html * igt@kms_bw@linear-tiling-1-displays-3840x2160p: - shard-dg2-set2: [SKIP][277] ([Intel XE#367]) -> [SKIP][278] ([Intel XE#1201] / [Intel XE#367]) +1 other test skip [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html * igt@kms_bw@linear-tiling-2-displays-2160x1440p: - shard-dg2-set2: [SKIP][279] ([Intel XE#1201] / [i915#2575]) -> [SKIP][280] ([Intel XE#1201] / [Intel XE#367]) [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html - shard-lnl: [SKIP][281] -> [SKIP][282] ([Intel XE#367]) [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html * igt@kms_bw@linear-tiling-4-displays-1920x1080p: - shard-dg2-set2: [SKIP][283] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][284] ([Intel XE#367]) [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html * igt@kms_bw@linear-tiling-4-displays-2560x1440p: - shard-dg2-set2: [SKIP][285] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][286] ([Intel XE#1201] / [i915#2575]) [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs: - shard-dg2-set2: [SKIP][287] ([Intel XE#1201]) -> [SKIP][288] ([Intel XE#455] / [Intel XE#787]) [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs: - shard-lnl: [SKIP][289] -> [SKIP][290] ([Intel XE#1399]) +11 other tests skip [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4: - shard-dg2-set2: [SKIP][291] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][292] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +11 other tests skip [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs: - shard-dg2-set2: [SKIP][293] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][294] ([Intel XE#1201]) +1 other test skip [293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs.html [294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs.html * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs: - shard-dg2-set2: [SKIP][295] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][296] ([Intel XE#1201]) +6 other tests skip [295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html [296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs: - shard-dg2-set2: [SKIP][297] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][298] ([Intel XE#455] / [Intel XE#787]) +5 other tests skip [297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html [298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-6: - shard-dg2-set2: [SKIP][299] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][300] ([Intel XE#787]) +20 other tests skip [299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-6.html [300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-6.html * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc: - shard-dg2-set2: [SKIP][301] ([Intel XE#1201]) -> [SKIP][302] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +4 other tests skip [301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc.html [302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc.html * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4: - shard-dg2-set2: [SKIP][303] ([Intel XE#787]) -> [SKIP][304] ([Intel XE#1201] / [Intel XE#787]) +41 other tests skip [303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html [304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html * igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs: - shard-dg2-set2: [SKIP][305] ([Intel XE#1252]) -> [SKIP][306] ([Intel XE#1201]) [305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html [306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html * igt@kms_chamelium_color@ctm-0-50: - shard-dg2-set2: [SKIP][307] ([Intel XE#306]) -> [SKIP][308] ([Intel XE#1201] / [i915#2575]) [307]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_chamelium_color@ctm-0-50.html [308]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_chamelium_color@ctm-0-50.html * igt@kms_chamelium_color@gamma: - shard-dg2-set2: [SKIP][309] ([Intel XE#1201] / [Intel XE#306]) -> [SKIP][310] ([Intel XE#306]) +1 other test skip [309]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_chamelium_color@gamma.html [310]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_chamelium_color@gamma.html * igt@kms_chamelium_edid@dp-edid-stress-resolution-4k: - shard-dg2-set2: [SKIP][311] ([Intel XE#373]) -> [SKIP][312] ([Intel XE#1201] / [Intel XE#373]) +5 other tests skip [311]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html [312]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k: - shard-dg2-set2: [SKIP][313] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][314] ([Intel XE#1201] / [i915#2575]) +4 other tests skip [313]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html [314]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend: - shard-lnl: [SKIP][315] -> [SKIP][316] ([Intel XE#373]) +5 other tests skip [315]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html [316]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k: - shard-dg2-set2: [SKIP][317] ([Intel XE#1201] / [i915#2575]) -> [SKIP][318] ([Intel XE#1201] / [Intel XE#373]) +3 other tests skip [317]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html [318]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html * igt@kms_chamelium_frames@hdmi-aspect-ratio: - shard-dg2-set2: [SKIP][319] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][320] ([Intel XE#373]) [319]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_chamelium_frames@hdmi-aspect-ratio.html [320]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_chamelium_frames@hdmi-aspect-ratio.html * igt@kms_chamelium_frames@hdmi-crc-single: - shard-dg2-set2: [SKIP][321] ([Intel XE#1201] / [i915#2575]) -> [SKIP][322] ([Intel XE#373]) [321]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_chamelium_frames@hdmi-crc-single.html [322]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_chamelium_frames@hdmi-crc-single.html * igt@kms_chamelium_hpd@vga-hpd: - shard-dg2-set2: [SKIP][323] ([Intel XE#373]) -> [SKIP][324] ([Intel XE#1201] / [i915#2575]) +1 other test skip [323]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_chamelium_hpd@vga-hpd.html [324]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_chamelium_hpd@vga-hpd.html - shard-lnl: [SKIP][325] ([Intel XE#373]) -> [SKIP][326] ([Intel XE#2366]) [325]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_chamelium_hpd@vga-hpd.html [326]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_chamelium_hpd@vga-hpd.html * igt@kms_content_protection@dp-mst-lic-type-0: - shard-dg2-set2: [SKIP][327] ([Intel XE#1201] / [i915#2575]) -> [SKIP][328] ([Intel XE#1201] / [Intel XE#307]) [327]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_content_protection@dp-mst-lic-type-0.html [328]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_content_protection@dp-mst-lic-type-0.html - shard-lnl: [SKIP][329] -> [SKIP][330] ([Intel XE#307]) [329]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_content_protection@dp-mst-lic-type-0.html [330]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_content_protection@dp-mst-lic-type-0.html * igt@kms_content_protection@dp-mst-lic-type-1: - shard-dg2-set2: [SKIP][331] ([Intel XE#1201] / [Intel XE#307]) -> [SKIP][332] ([Intel XE#1201] / [i915#2575]) [331]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_content_protection@dp-mst-lic-type-1.html [332]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_content_protection@dp-mst-lic-type-1.html * igt@kms_content_protection@lic-type-1: - shard-dg2-set2: [SKIP][333] ([Intel XE#455]) -> [SKIP][334] ([Intel XE#1201] / [i915#2575]) +2 other tests skip [333]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_content_protection@lic-type-1.html [334]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_content_protection@lic-type-1.html - shard-lnl: [SKIP][335] ([Intel XE#599]) -> [SKIP][336] ([Intel XE#2366]) [335]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_content_protection@lic-type-1.html [336]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_content_protection@lic-type-1.html * igt@kms_cursor_crc@cursor-offscreen-512x512: - shard-dg2-set2: [SKIP][337] ([Intel XE#1201] / [i915#2575]) -> [SKIP][338] ([Intel XE#1201] / [Intel XE#308]) +1 other test skip [337]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_cursor_crc@cursor-offscreen-512x512.html [338]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_cursor_crc@cursor-offscreen-512x512.html - shard-lnl: [SKIP][339] -> [SKIP][340] ([Intel XE#1413]) +1 other test skip [339]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_cursor_crc@cursor-offscreen-512x512.html [340]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_cursor_crc@cursor-offscreen-512x512.html * igt@kms_cursor_crc@cursor-rapid-movement-256x85: - shard-lnl: [SKIP][341] -> [SKIP][342] ([Intel XE#1424]) +1 other test skip [341]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html [342]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html * igt@kms_cursor_crc@cursor-sliding-512x170: - shard-dg2-set2: [SKIP][343] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][344] ([Intel XE#1201] / [i915#2575]) [343]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_cursor_crc@cursor-sliding-512x170.html [344]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_cursor_crc@cursor-sliding-512x170.html * igt@kms_cursor_crc@cursor-sliding-512x512: - shard-dg2-set2: [SKIP][345] ([Intel XE#308]) -> [SKIP][346] ([Intel XE#1201] / [Intel XE#308]) +1 other test skip [345]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_cursor_crc@cursor-sliding-512x512.html [346]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_cursor_crc@cursor-sliding-512x512.html * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-lnl: [SKIP][347] -> [SKIP][348] ([Intel XE#309]) +3 other tests skip [347]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html [348]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-lnl: [SKIP][349] -> [SKIP][350] ([Intel XE#323]) [349]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [350]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic: - shard-lnl: [SKIP][351] ([Intel XE#309]) -> [SKIP][352] ([Intel XE#2366]) [351]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html [352]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html * igt@kms_dirtyfb@drrs-dirtyfb-ioctl: - shard-dg2-set2: [SKIP][353] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][354] ([Intel XE#455]) +3 other tests skip [353]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html [354]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html * igt@kms_dsc@dsc-fractional-bpp-with-bpc: - shard-dg2-set2: [SKIP][355] ([Intel XE#1201]) -> [SKIP][356] ([Intel XE#1201] / [Intel XE#455]) +1 other test skip [355]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html [356]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html * igt@kms_dsc@dsc-with-bpc-formats: - shard-dg2-set2: [SKIP][357] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][358] ([Intel XE#1201]) +3 other tests skip [357]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_dsc@dsc-with-bpc-formats.html [358]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_dsc@dsc-with-bpc-formats.html * igt@kms_fbcon_fbt@psr-suspend: - shard-dg2-set2: [SKIP][359] ([Intel XE#1201] / [Intel XE#776]) -> [SKIP][360] ([Intel XE#1201]) [359]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_fbcon_fbt@psr-suspend.html [360]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_feature_discovery@chamelium: - shard-dg2-set2: [SKIP][361] ([Intel XE#701]) -> [SKIP][362] ([Intel XE#1201] / [Intel XE#701]) [361]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_feature_discovery@chamelium.html [362]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_feature_discovery@chamelium.html * igt@kms_feature_discovery@display-3x: - shard-dg2-set2: [SKIP][363] ([Intel XE#1201] / [Intel XE#703]) -> [SKIP][364] ([Intel XE#1201] / [i915#2575]) [363]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_feature_discovery@display-3x.html [364]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_feature_discovery@display-3x.html * igt@kms_feature_discovery@display-4x: - shard-dg2-set2: [SKIP][365] ([Intel XE#1201] / [i915#2575]) -> [SKIP][366] ([Intel XE#1138]) [365]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_feature_discovery@display-4x.html [366]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_feature_discovery@display-4x.html - shard-lnl: [SKIP][367] -> [SKIP][368] ([Intel XE#1138]) [367]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_feature_discovery@display-4x.html [368]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_feature_discovery@display-4x.html * igt@kms_feature_discovery@psr1: - shard-dg2-set2: [SKIP][369] ([Intel XE#1201] / [i915#2575]) -> [SKIP][370] ([Intel XE#1135] / [Intel XE#1201]) [369]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_feature_discovery@psr1.html [370]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_feature_discovery@psr1.html * igt@kms_flip@2x-absolute-wf_vblank-interruptible: - shard-lnl: [SKIP][371] -> [SKIP][372] ([Intel XE#1421]) +1 other test skip [371]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html [372]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling: - shard-lnl: [SKIP][373] -> [SKIP][374] ([Intel XE#1397] / [Intel XE#1745]) +2 other tests skip [373]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html [374]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling: - shard-lnl: [SKIP][375] -> [SKIP][376] ([Intel XE#1401] / [Intel XE#1745]) [375]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html [376]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling: - shard-dg2-set2: [SKIP][377] ([Intel XE#455]) -> [SKIP][378] ([Intel XE#1201] / [Intel XE#455]) +12 other tests skip [377]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html [378]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html * igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-blt: - shard-dg2-set2: [SKIP][379] ([Intel XE#1201]) -> [SKIP][380] ([Intel XE#651]) +2 other tests skip [379]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-blt.html [380]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff: - shard-dg2-set2: [SKIP][381] ([Intel XE#651]) -> [SKIP][382] ([Intel XE#1201]) +2 other tests skip [381]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html [382]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt: - shard-lnl: [SKIP][383] -> [SKIP][384] ([Intel XE#651]) +8 other tests skip [383]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt.html [384]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt: - shard-dg2-set2: [SKIP][385] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][386] ([Intel XE#1201]) +14 other tests skip [385]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt.html [386]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render: - shard-lnl: [SKIP][387] -> [SKIP][388] ([Intel XE#656]) +17 other tests skip [387]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render.html [388]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-tiling-y: - shard-dg2-set2: [SKIP][389] ([Intel XE#1201] / [Intel XE#658]) -> [SKIP][390] ([Intel XE#1201]) [389]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-tiling-y.html [390]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-tiling-y.html * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-render: - shard-lnl: [SKIP][391] ([Intel XE#651]) -> [SKIP][392] ([Intel XE#2351]) [391]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-render.html [392]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt: - shard-dg2-set2: [SKIP][393] ([Intel XE#1201]) -> [SKIP][394] ([Intel XE#1201] / [Intel XE#651]) +10 other tests skip [393]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt.html [394]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-blt: - shard-dg2-set2: [SKIP][395] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][396] ([Intel XE#651]) +6 other tests skip [395]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-blt.html [396]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-blt.html * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear: - shard-dg2-set2: [SKIP][397] ([Intel XE#651]) -> [SKIP][398] ([Intel XE#1201] / [Intel XE#651]) +16 other tests skip [397]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear.html [398]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-dg2-set2: [SKIP][399] ([Intel XE#1201]) -> [SKIP][400] ([Intel XE#653]) [399]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html [400]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt: - shard-dg2-set2: [SKIP][401] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][402] ([Intel XE#1201]) +12 other tests skip [401]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html [402]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-slowdraw: - shard-dg2-set2: [SKIP][403] ([Intel XE#1201]) -> [SKIP][404] ([Intel XE#1201] / [Intel XE#653]) +12 other tests skip [403]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html [404]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y: - shard-dg2-set2: [SKIP][405] ([Intel XE#658]) -> [SKIP][406] ([Intel XE#1201] / [Intel XE#658]) [405]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html [406]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt: - shard-dg2-set2: [SKIP][407] ([Intel XE#653]) -> [SKIP][408] ([Intel XE#1201] / [Intel XE#653]) +16 other tests skip [407]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html [408]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move: - shard-dg2-set2: [SKIP][409] ([Intel XE#653]) -> [SKIP][410] ([Intel XE#1201]) +2 other tests skip [409]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html [410]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc: - shard-dg2-set2: [SKIP][411] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][412] ([Intel XE#653]) +8 other tests skip [411]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html [412]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_getfb@getfb-reject-ccs: - shard-lnl: [SKIP][413] -> [SKIP][414] ([Intel XE#605]) [413]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_getfb@getfb-reject-ccs.html [414]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_getfb@getfb-reject-ccs.html - shard-dg2-set2: [SKIP][415] ([Intel XE#1201] / [i915#2575]) -> [SKIP][416] ([Intel XE#1201] / [Intel XE#605]) [415]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_getfb@getfb-reject-ccs.html [416]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_getfb@getfb-reject-ccs.html * igt@kms_getfb@getfb2-accept-ccs: - shard-lnl: [SKIP][417] ([Intel XE#2340]) -> [SKIP][418] ([Intel XE#2366]) [417]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_getfb@getfb2-accept-ccs.html [418]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_getfb@getfb2-accept-ccs.html * igt@kms_panel_fitting@legacy: - shard-dg2-set2: [SKIP][419] ([Intel XE#1201] / [i915#2575]) -> [SKIP][420] ([Intel XE#1201] / [Intel XE#455]) +2 other tests skip [419]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_panel_fitting@legacy.html [420]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_panel_fitting@legacy.html * igt@kms_plane_multiple@tiling-y: - shard-dg2-set2: [SKIP][421] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][422] ([Intel XE#1201] / [i915#2575]) +4 other tests skip [421]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_plane_multiple@tiling-y.html [422]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_plane_multiple@tiling-y.html * igt@kms_plane_multiple@tiling-yf: - shard-lnl: [SKIP][423] -> [SKIP][424] ([Intel XE#599]) +2 other tests skip [423]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_plane_multiple@tiling-yf.html [424]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_plane_multiple@tiling-yf.html * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25: - shard-lnl: [SKIP][425] -> [SKIP][426] ([Intel XE#2318]) [425]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html [426]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25: - shard-dg2-set2: [SKIP][427] ([Intel XE#2318] / [Intel XE#455]) -> [SKIP][428] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) [427]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html [428]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6: - shard-dg2-set2: [SKIP][429] ([Intel XE#2318]) -> [SKIP][430] ([Intel XE#1201] / [Intel XE#2318]) +2 other tests skip [429]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6.html [430]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6.html * igt@kms_pm_backlight@fade: - shard-dg2-set2: [SKIP][431] ([Intel XE#870]) -> [SKIP][432] ([Intel XE#1201] / [Intel XE#870]) [431]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_pm_backlight@fade.html [432]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_pm_backlight@fade.html * igt@kms_pm_dc@dc3co-vpb-simulation: - shard-dg2-set2: [SKIP][433] ([Intel XE#1201]) -> [SKIP][434] ([Intel XE#1122] / [Intel XE#1201]) [433]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_pm_dc@dc3co-vpb-simulation.html [434]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_pm_dc@dc3co-vpb-simulation.html - shard-lnl: [SKIP][435] -> [SKIP][436] ([Intel XE#736]) [435]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_pm_dc@dc3co-vpb-simulation.html [436]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_pm_dc@dc3co-vpb-simulation.html * igt@kms_pm_dc@dc6-psr: - shard-dg2-set2: [SKIP][437] ([Intel XE#1129] / [Intel XE#1201]) -> [SKIP][438] ([Intel XE#1129]) [437]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_pm_dc@dc6-psr.html [438]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_pm_dc@dc6-psr.html * igt@kms_pm_dc@deep-pkgc: - shard-dg2-set2: [SKIP][439] ([Intel XE#1201] / [Intel XE#908]) -> [SKIP][440] ([Intel XE#1201]) [439]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_pm_dc@deep-pkgc.html [440]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_pm_dc@deep-pkgc.html * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf: - shard-dg2-set2: [SKIP][441] ([Intel XE#1201]) -> [SKIP][442] ([Intel XE#1201] / [Intel XE#1489]) +2 other tests skip [441]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html [442]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html * igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area: - shard-dg2-set2: [SKIP][443] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][444] ([Intel XE#1201]) +1 other test skip [443]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area.html [444]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area.html * igt@kms_psr2_sf@overlay-plane-move-continuous-sf: - shard-dg2-set2: [SKIP][445] ([Intel XE#1489]) -> [SKIP][446] ([Intel XE#1201] / [Intel XE#1489]) +2 other tests skip [445]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html [446]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area: - shard-dg2-set2: [SKIP][447] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][448] ([Intel XE#1489]) +2 other tests skip [447]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html [448]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html * igt@kms_psr@fbc-pr-cursor-plane-move: - shard-dg2-set2: [SKIP][449] ([Intel XE#1201]) -> [SKIP][450] ([Intel XE#1201] / [Intel XE#929]) +6 other tests skip [449]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_psr@fbc-pr-cursor-plane-move.html [450]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_psr@fbc-pr-cursor-plane-move.html - shard-lnl: [SKIP][451] -> [SKIP][452] ([Intel XE#1406]) +2 other tests skip [451]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_psr@fbc-pr-cursor-plane-move.html [452]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_psr@fbc-pr-cursor-plane-move.html * igt@kms_psr@fbc-pr-no-drrs: - shard-dg2-set2: [SKIP][453] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][454] ([Intel XE#1201]) +6 other tests skip [453]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_psr@fbc-pr-no-drrs.html [454]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_psr@fbc-pr-no-drrs.html * igt@kms_psr@fbc-psr2-primary-blt: - shard-dg2-set2: [SKIP][455] ([Intel XE#929]) -> [SKIP][456] ([Intel XE#1201] / [Intel XE#929]) +8 other tests skip [455]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_psr@fbc-psr2-primary-blt.html [456]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_psr@fbc-psr2-primary-blt.html * igt@kms_psr@pr-basic: - shard-lnl: [SKIP][457] ([Intel XE#2351]) -> [SKIP][458] ([Intel XE#1406]) [457]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_psr@pr-basic.html [458]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_psr@pr-basic.html * igt@kms_psr@psr-cursor-render: - shard-dg2-set2: [SKIP][459] ([Intel XE#1201]) -> [SKIP][460] ([Intel XE#929]) +1 other test skip [459]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_psr@psr-cursor-render.html [460]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_psr@psr-cursor-render.html * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: - shard-dg2-set2: [SKIP][461] ([Intel XE#1201]) -> [SKIP][462] ([Intel XE#1149] / [Intel XE#1201]) [461]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html [462]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html * igt@kms_rmfb@close-fd: - shard-dg2-set2: [SKIP][463] ([Intel XE#1201] / [i915#2575]) -> [FAIL][464] ([Intel XE#294]) [463]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_rmfb@close-fd.html [464]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_rmfb@close-fd.html - shard-lnl: [SKIP][465] -> [FAIL][466] ([Intel XE#294]) [465]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_rmfb@close-fd.html [466]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_rmfb@close-fd.html * igt@kms_rotation_crc@bad-tiling: - shard-dg2-set2: [SKIP][467] ([Intel XE#1201] / [i915#2575]) -> [SKIP][468] ([Intel XE#327]) [467]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_rotation_crc@bad-tiling.html [468]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_rotation_crc@bad-tiling.html - shard-lnl: [SKIP][469] -> [SKIP][470] ([Intel XE#1437]) [469]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_rotation_crc@bad-tiling.html [470]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_rotation_crc@bad-tiling.html * igt@kms_rotation_crc@primary-rotation-90: - shard-dg2-set2: [SKIP][471] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][472] ([Intel XE#327]) [471]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_rotation_crc@primary-rotation-90.html [472]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_rotation_crc@primary-rotation-90.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180: - shard-dg2-set2: [SKIP][473] ([Intel XE#1201] / [i915#2575]) -> [SKIP][474] ([Intel XE#1127] / [Intel XE#1201]) +1 other test skip [473]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html [474]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90: - shard-dg2-set2: [SKIP][475] ([Intel XE#327]) -> [SKIP][476] ([Intel XE#1201] / [Intel XE#327]) +1 other test skip [475]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html [476]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0: - shard-lnl: [SKIP][477] -> [SKIP][478] ([Intel XE#1127]) +1 other test skip [477]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html [478]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270: - shard-dg2-set2: [SKIP][479] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][480] ([Intel XE#1201] / [i915#2575]) +1 other test skip [479]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html [480]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html * igt@kms_writeback@writeback-check-output: - shard-dg2-set2: [SKIP][481] ([Intel XE#1201] / [Intel XE#756]) -> [SKIP][482] ([Intel XE#1201] / [i915#2575]) [481]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_writeback@writeback-check-output.html [482]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_writeback@writeback-check-output.html * igt@kms_writeback@writeback-check-output-xrgb2101010: - shard-lnl: [SKIP][483] -> [SKIP][484] ([Intel XE#756]) [483]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_writeback@writeback-check-output-xrgb2101010.html [484]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_writeback@writeback-check-output-xrgb2101010.html * igt@kms_writeback@writeback-invalid-parameters: - shard-dg2-set2: [SKIP][485] ([Intel XE#756]) -> [SKIP][486] ([Intel XE#1201] / [Intel XE#756]) [485]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_writeback@writeback-invalid-parameters.html [486]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_writeback@writeback-invalid-parameters.html * igt@sriov_basic@enable-vfs-autoprobe-off: - shard-dg2-set2: [SKIP][487] ([Intel XE#1091] / [Intel XE#1201]) -> [SKIP][488] ([Intel XE#1091]) [487]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@sriov_basic@enable-vfs-autoprobe-off.html [488]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@sriov_basic@enable-vfs-autoprobe-off.html * igt@xe_compute@ccs-mode-compute-kernel: - shard-dg2-set2: [SKIP][489] ([Intel XE#1130] / [Intel XE#1201]) -> [FAIL][490] ([Intel XE#1050]) [489]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_compute@ccs-mode-compute-kernel.html [490]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_compute@ccs-mode-compute-kernel.html - shard-lnl: [SKIP][491] ([Intel XE#1130]) -> [SKIP][492] ([Intel XE#1447]) [491]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@xe_compute@ccs-mode-compute-kernel.html [492]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@xe_compute@ccs-mode-compute-kernel.html * igt@xe_compute_preempt@compute-preempt: - shard-dg2-set2: [SKIP][493] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][494] ([Intel XE#1201] / [Intel XE#1280] / [Intel XE#455]) +1 other test skip [493]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_compute_preempt@compute-preempt.html [494]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_compute_preempt@compute-preempt.html * igt@xe_compute_preempt@compute-threadgroup-preempt: - shard-dg2-set2: [SKIP][495] ([Intel XE#1201] / [Intel XE#1280] / [Intel XE#455]) -> [SKIP][496] ([Intel XE#1130] / [Intel XE#1201]) [495]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_compute_preempt@compute-threadgroup-preempt.html [496]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@xe_compute_preempt@compute-threadgroup-preempt.html * igt@xe_copy_basic@mem-copy-linear-0x369: - shard-dg2-set2: [SKIP][497] ([Intel XE#1123] / [Intel XE#1201]) -> [SKIP][498] ([Intel XE#1123]) [497]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@xe_copy_basic@mem-copy-linear-0x369.html [498]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_copy_basic@mem-copy-linear-0x369.html * igt@xe_copy_basic@mem-set-linear-0x3fff: - shard-dg2-set2: [SKIP][499] ([Intel XE#1126] / [Intel XE#1201]) -> [SKIP][500] ([Intel XE#1130] / [Intel XE#1201]) [499]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_copy_basic@mem-set-linear-0x3fff.html [500]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_copy_basic@mem-set-linear-0x3fff.html * igt@xe_evict@evict-beng-mixed-threads-large-multi-vm: - shard-lnl: [SKIP][501] ([Intel XE#688]) -> [SKIP][502] ([Intel XE#1130]) +6 other tests skip [501]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@xe_evict@evict-beng-mixed-threads-large-multi-vm.html [502]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@xe_evict@evict-beng-mixed-threads-large-multi-vm.html * igt@xe_evict@evict-mixed-many-threads-large: - shard-dg2-set2: [TIMEOUT][503] ([Intel XE#1041] / [Intel XE#1473] / [Intel XE#392]) -> [SKIP][504] ([Intel XE#1130] / [Intel XE#1201]) [503]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_evict@evict-mixed-many-threads-large.html [504]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_evict@evict-mixed-many-threads-large.html * igt@xe_evict@evict-threads-small-multi-vm: - shard-lnl: [SKIP][505] ([Intel XE#1130]) -> [SKIP][506] ([Intel XE#688]) +2 other tests skip [505]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@xe_evict@evict-threads-small-multi-vm.html [506]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@xe_evict@evict-threads-small-multi-vm.html * igt@xe_exec_basic@multigpu-no-exec-basic: - shard-lnl: [SKIP][507] ([Intel XE#1130]) -> [SKIP][508] ([Intel XE#1392]) +3 other tests skip [507]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@xe_exec_basic@multigpu-no-exec-basic.html [508]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@xe_exec_basic@multigpu-no-exec-basic.html * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind: - shard-lnl: [SKIP][509] ([Intel XE#1392]) -> [SKIP][510] ([Intel XE#1130]) +2 other tests skip [509]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html [510]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html * igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate: - shard-dg2-set2: [SKIP][511] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][512] ([Intel XE#1130] / [Intel XE#1201]) +10 other tests skip [511]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate.html [512]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate.html * igt@xe_exec_fault_mode@many-execqueues-userptr-rebind: - shard-dg2-set2: [SKIP][513] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][514] ([Intel XE#288]) [513]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_exec_fault_mode@many-execqueues-userptr-rebind.html [514]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_exec_fault_mode@many-execqueues-userptr-rebind.html * igt@xe_exec_fault_mode@once-invalid-userptr-fault: - shard-dg2-set2: [SKIP][515] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][516] ([Intel XE#1201] / [Intel XE#288]) +13 other tests skip [515]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html [516]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html * igt@xe_exec_fault_mode@once-userptr-invalidate-race-imm: - shard-dg2-set2: [SKIP][517] ([Intel XE#288]) -> [SKIP][518] ([Intel XE#1201] / [Intel XE#288]) +18 other tests skip [517]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_exec_fault_mode@once-userptr-invalidate-race-imm.html [518]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_exec_fault_mode@once-userptr-invalidate-race-imm.html * igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm: - shard-dg2-set2: [SKIP][519] ([Intel XE#288]) -> [SKIP][520] ([Intel XE#1130] / [Intel XE#1201]) [519]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html [520]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html * igt@xe_exec_fault_mode@twice-userptr-rebind-imm: - shard-dg2-set2: [SKIP][521] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][522] ([Intel XE#288]) +7 other tests skip [521]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html [522]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html * igt@xe_exec_reset@parallel-gt-reset: - shard-dg2-set2: [TIMEOUT][523] ([Intel XE#2105]) -> [INCOMPLETE][524] ([Intel XE#1195] / [Intel XE#2105]) [523]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_exec_reset@parallel-gt-reset.html [524]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_exec_reset@parallel-gt-reset.html * igt@xe_mmap@small-bar: - shard-dg2-set2: [SKIP][525] ([Intel XE#1201] / [Intel XE#512]) -> [SKIP][526] ([Intel XE#512]) [525]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@xe_mmap@small-bar.html [526]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_mmap@small-bar.html * igt@xe_module_load@many-reload: - shard-dg2-set2: [DMESG-FAIL][527] -> [FAIL][528] ([Intel XE#2136]) [527]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_module_load@many-reload.html [528]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_module_load@many-reload.html * igt@xe_module_load@reload: - shard-dg2-set2: [DMESG-FAIL][529] ([Intel XE#2019]) -> [FAIL][530] ([Intel XE#2136]) [529]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_module_load@reload.html [530]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_module_load@reload.html * igt@xe_pat@pat-index-xelp: - shard-lnl: [SKIP][531] ([Intel XE#977]) -> [SKIP][532] ([Intel XE#1130]) [531]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@xe_pat@pat-index-xelp.html [532]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@xe_pat@pat-index-xelp.html * igt@xe_peer2peer@write: - shard-dg2-set2: [SKIP][533] ([Intel XE#1061] / [Intel XE#1201]) -> [FAIL][534] ([Intel XE#1173]) [533]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_peer2peer@write.html [534]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_peer2peer@write.html * igt@xe_pm@d3cold-basic: - shard-lnl: [SKIP][535] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][536] ([Intel XE#1130]) +2 other tests skip [535]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@xe_pm@d3cold-basic.html [536]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@xe_pm@d3cold-basic.html * igt@xe_pm@d3cold-basic-exec: - shard-dg2-set2: [SKIP][537] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][538] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) [537]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_pm@d3cold-basic-exec.html [538]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_pm@d3cold-basic-exec.html - shard-lnl: [SKIP][539] ([Intel XE#1130]) -> [SKIP][540] ([Intel XE#2284] / [Intel XE#366]) [539]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@xe_pm@d3cold-basic-exec.html [540]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@xe_pm@d3cold-basic-exec.html * igt@xe_pm@s2idle-d3cold-basic-exec: - shard-dg2-set2: [SKIP][541] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][542] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) [541]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_pm@s2idle-d3cold-basic-exec.html [542]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_pm@s2idle-d3cold-basic-exec.html * igt@xe_pm@s3-basic: - shard-lnl: [SKIP][543] ([Intel XE#1130]) -> [SKIP][544] ([Intel XE#584]) [543]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@xe_pm@s3-basic.html [544]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@xe_pm@s3-basic.html * igt@xe_pm@s3-d3cold-basic-exec: - shard-dg2-set2: [SKIP][545] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) -> [SKIP][546] ([Intel XE#1130] / [Intel XE#1201]) +2 other tests skip [545]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@xe_pm@s3-d3cold-basic-exec.html [546]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_pm@s3-d3cold-basic-exec.html * igt@xe_query@multigpu-query-config: - shard-dg2-set2: [SKIP][547] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][548] ([Intel XE#1201] / [Intel XE#944]) +1 other test skip [547]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_query@multigpu-query-config.html [548]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_query@multigpu-query-config.html * igt@xe_query@multigpu-query-invalid-size: - shard-lnl: [SKIP][549] ([Intel XE#1130]) -> [SKIP][550] ([Intel XE#944]) +1 other test skip [549]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@xe_query@multigpu-query-invalid-size.html [550]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@xe_query@multigpu-query-invalid-size.html * igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz: - shard-dg2-set2: [SKIP][551] ([Intel XE#1201] / [Intel XE#944]) -> [SKIP][552] ([Intel XE#1130] / [Intel XE#1201]) [551]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html [552]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html * igt@xe_query@multigpu-query-mem-usage: - shard-dg2-set2: [SKIP][553] ([Intel XE#944]) -> [SKIP][554] ([Intel XE#1201] / [Intel XE#944]) +1 other test skip [553]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_query@multigpu-query-mem-usage.html [554]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@xe_query@multigpu-query-mem-usage.html * igt@xe_query@multigpu-query-topology-l3-bank-mask: - shard-lnl: [SKIP][555] ([Intel XE#944]) -> [SKIP][556] ([Intel XE#1130]) +2 other tests skip [555]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@xe_query@multigpu-query-topology-l3-bank-mask.html [556]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@xe_query@multigpu-query-topology-l3-bank-mask.html * igt@xe_wedged@wedged-at-any-timeout: - shard-dg2-set2: [DMESG-FAIL][557] ([Intel XE#1760]) -> [SKIP][558] ([Intel XE#1130] / [Intel XE#1201]) [557]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_wedged@wedged-at-any-timeout.html [558]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@xe_wedged@wedged-at-any-timeout.html - shard-lnl: [DMESG-FAIL][559] ([Intel XE#1760]) -> [SKIP][560] ([Intel XE#1130]) [559]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@xe_wedged@wedged-at-any-timeout.html [560]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@xe_wedged@wedged-at-any-timeout.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [Intel XE#1041]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1041 [Intel XE#1050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1050 [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061 [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091 [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122 [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123 [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124 [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126 [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127 [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128 [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129 [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130 [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135 [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138 [Intel XE#1149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1149 [Intel XE#1162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1162 [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173 [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192 [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195 [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201 [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252 [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280 [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337 [Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358 [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392 [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397 [Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399 [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401 [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406 [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407 [Intel XE#1413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1413 [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421 [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424 [Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426 [Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428 [Intel XE#1437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1437 [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439 [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447 [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467 [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469 [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470 [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473 [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489 [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499 [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512 [Intel XE#1551]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1551 [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600 [Intel XE#1620]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1620 [Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659 [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745 [Intel XE#1760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1760 [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794 [Intel XE#1924]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1924 [Intel XE#2019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2019 [Intel XE#2028]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2028 [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029 [Intel XE#2105]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2105 [Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136 [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191 [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229 [Intel XE#2262]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2262 [Intel XE#2280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2280 [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284 [Intel XE#2318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2318 [Intel XE#2340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2340 [Intel XE#2343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2343 [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351 [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360 [Intel XE#2366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2366 [Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255 [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288 [Intel XE#294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/294 [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306 [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307 [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308 [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309 [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316 [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323 [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324 [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327 [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346 [Intel XE#361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/361 [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366 [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367 [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373 [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378 [Intel XE#392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/392 [Intel XE#402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/402 [Intel XE#417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/417 [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455 [Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498 [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512 [Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569 [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584 [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599 [Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605 [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610 [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619 [Intel XE#623]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/623 [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651 [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653 [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656 [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658 [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688 [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701 [Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702 [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703 [Intel XE#736]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/736 [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756 [Intel XE#771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/771 [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776 [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787 [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870 [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886 [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899 [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908 [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929 [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944 [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977 [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979 [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575 [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804 Build changes ------------- * IGT: IGT_7942 -> IGTPW_11488 * Linux: xe-1684-3a93d4a1f4872fbdfe43e9b7f1a7dfd9236a642d -> xe-1686-b6f9528c7fffc2f65c8e4969d35d9346fd503c9b IGTPW_11488: 11488 IGT_7942: 0f02dc176959e6296866b1bafd3982e277a5e44b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-1684-3a93d4a1f4872fbdfe43e9b7f1a7dfd9236a642d: 3a93d4a1f4872fbdfe43e9b7f1a7dfd9236a642d xe-1686-b6f9528c7fffc2f65c8e4969d35d9346fd503c9b: b6f9528c7fffc2f65c8e4969d35d9346fd503c9b == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/index.html [-- Attachment #2: Type: text/html, Size: 172222 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: ✗ CI.xeFULL: failure for series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} 2024-07-30 2:16 ` ✗ CI.xeFULL: " Patchwork @ 2024-07-30 15:44 ` Matt Roper 0 siblings, 0 replies; 12+ messages in thread From: Matt Roper @ 2024-07-30 15:44 UTC (permalink / raw) To: igt-dev On Tue, Jul 30, 2024 at 02:16:00AM +0000, Patchwork wrote: > == Series Details == > > Series: series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} > URL : https://patchwork.freedesktop.org/series/136636/ > State : failure > > == Summary == > > CI Bug Log - changes from XEIGT_7942_full -> XEIGTPW_11488_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with XEIGTPW_11488_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in XEIGTPW_11488_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (3 -> 3) > ------------------------------ > > No changes in participating hosts > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in XEIGTPW_11488_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-6: > - shard-dg2-set2: [PASS][1] -> [FAIL][2] +2 other tests fail > [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-6.html > [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-6.html https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1426 > > * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs: > - shard-lnl: NOTRUN -> [SKIP][3] +21 other tests skip > [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html The PCI device became unusable/unavailable after igt@xe_module_load@unload was run. Everything after that skipped because the driver couldn't re-probe. Unrelated to this IGT series. > > * igt@kms_invalid_mode@uint-max-clock: > - shard-lnl: [PASS][4] -> [SKIP][5] +63 other tests skip > [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_invalid_mode@uint-max-clock.html > [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_invalid_mode@uint-max-clock.html Similar to the above, the PCI device became unavailable/unusable after igt@xe_module_load@reload-no-display. None of the later tests can run since the device is missing. Unrelated to this IGT series. > > * igt@kms_pipe_crc_basic@suspend-read-crc: > - shard-lnl: [PASS][6] -> [DMESG-WARN][7] +1 other test dmesg-warn > [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_pipe_crc_basic@suspend-read-crc.html > [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_pipe_crc_basic@suspend-read-crc.html "NMI backtrace for cpu 2 skipped: idling at intel_idle_s2idle+0x79/0xe0" Comes from the intel_idle driver, not the graphics driver. Appears to be a general s0ix issue, not caused by Xe or by this IGT change. > > * igt@xe_live_ktest@xe_dma_buf: > - shard-lnl: [PASS][8] -> [FAIL][9] +1 other test fail > [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@xe_live_ktest@xe_dma_buf.html > [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@xe_live_ktest@xe_dma_buf.html https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2420 > > * igt@xe_pm@s4-basic: > - shard-dg2-set2: [PASS][10] -> [DMESG-WARN][11] +1 other test dmesg-warn > [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_pm@s4-basic.html > [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_pm@s4-basic.html https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2019 > > > #### Warnings #### Spot checking these warnings, they seem to be more skips caused by the xe_module_load behavior noted above (PCI device becomes unavailable). Matt > > * igt@core_hotunplug@hotunbind-rebind: > - shard-lnl: [ABORT][12] -> [SKIP][13] > [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@core_hotunplug@hotunbind-rebind.html > [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@core_hotunplug@hotunbind-rebind.html > > * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip: > - shard-lnl: [FAIL][14] ([Intel XE#1659]) -> [SKIP][15] > [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html > [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html > > * igt@kms_big_fb@linear-32bpp-rotate-90: > - shard-lnl: [SKIP][16] ([Intel XE#1407]) -> [SKIP][17] +2 other tests skip > [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_big_fb@linear-32bpp-rotate-90.html > [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_big_fb@linear-32bpp-rotate-90.html > > * igt@kms_big_fb@y-tiled-32bpp-rotate-0: > - shard-lnl: [SKIP][18] ([Intel XE#1124]) -> [SKIP][19] +7 other tests skip > [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html > [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html > > * igt@kms_bw@linear-tiling-4-displays-2560x1440p: > - shard-lnl: [SKIP][20] ([Intel XE#1512]) -> [SKIP][21] > [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-2/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html > [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html > > * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs: > - shard-lnl: [SKIP][22] ([Intel XE#1399]) -> [SKIP][23] +11 other tests skip > [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html > [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html > > * igt@kms_chamelium_color@ctm-0-50: > - shard-lnl: [SKIP][24] ([Intel XE#306]) -> [SKIP][25] > [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_chamelium_color@ctm-0-50.html > [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_chamelium_color@ctm-0-50.html > > * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k: > - shard-lnl: [SKIP][26] ([Intel XE#373]) -> [SKIP][27] +6 other tests skip > [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-2/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html > [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html > > * igt@kms_content_protection@dp-mst-lic-type-1: > - shard-lnl: [SKIP][28] ([Intel XE#307]) -> [SKIP][29] > [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_content_protection@dp-mst-lic-type-1.html > [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_content_protection@dp-mst-lic-type-1.html > > * igt@kms_cursor_crc@cursor-onscreen-128x42: > - shard-lnl: [SKIP][30] ([Intel XE#1424]) -> [SKIP][31] +3 other tests skip > [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_cursor_crc@cursor-onscreen-128x42.html > [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_cursor_crc@cursor-onscreen-128x42.html > > * igt@kms_cursor_crc@cursor-sliding-512x170: > - shard-lnl: [SKIP][32] ([Intel XE#1413]) -> [SKIP][33] > [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_cursor_crc@cursor-sliding-512x170.html > [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_cursor_crc@cursor-sliding-512x170.html > > * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: > - shard-dg2-set2: [SKIP][34] ([Intel XE#1201] / [i915#2575]) -> [INCOMPLETE][35] > [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html > [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html > > * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: > - shard-lnl: [SKIP][36] ([Intel XE#309]) -> [SKIP][37] +2 other tests skip > [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html > [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html > > * igt@kms_feature_discovery@display-2x: > - shard-lnl: [SKIP][38] ([Intel XE#702]) -> [SKIP][39] > [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_feature_discovery@display-2x.html > [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_feature_discovery@display-2x.html > > * igt@kms_feature_discovery@display-3x: > - shard-lnl: [SKIP][40] ([Intel XE#703]) -> [SKIP][41] > [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_feature_discovery@display-3x.html > [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_feature_discovery@display-3x.html > > * igt@kms_flip@2x-flip-vs-dpms: > - shard-lnl: [SKIP][42] ([Intel XE#1421]) -> [SKIP][43] +4 other tests skip > [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_flip@2x-flip-vs-dpms.html > [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_flip@2x-flip-vs-dpms.html > > * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling: > - shard-lnl: [SKIP][44] ([Intel XE#1401] / [Intel XE#1745]) -> [SKIP][45] +2 other tests skip > [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html > [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html > > * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling: > - shard-lnl: [SKIP][46] ([Intel XE#1397] / [Intel XE#1745]) -> [SKIP][47] > [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html > [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html > > * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt: > - shard-lnl: [SKIP][48] ([Intel XE#656]) -> [SKIP][49] +21 other tests skip > [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html > [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html > > * igt@kms_frontbuffer_tracking@fbc-tiling-y: > - shard-lnl: [SKIP][50] ([Intel XE#1469]) -> [SKIP][51] > [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-tiling-y.html > [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_frontbuffer_tracking@fbc-tiling-y.html > > * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt: > - shard-lnl: [SKIP][52] ([Intel XE#651]) -> [SKIP][53] +10 other tests skip > [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html > [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html > > * igt@kms_plane_multiple@tiling-y: > - shard-lnl: [SKIP][54] ([Intel XE#599]) -> [SKIP][55] +3 other tests skip > [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_plane_multiple@tiling-y.html > [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_plane_multiple@tiling-y.html > > * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation: > - shard-lnl: [SKIP][56] ([Intel XE#498]) -> [SKIP][57] > [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation.html > [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation.html > > * igt@kms_plane_scaling@planes-downscale-factor-0-5: > - shard-lnl: [SKIP][58] ([Intel XE#2318]) -> [SKIP][59] +1 other test skip > [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_plane_scaling@planes-downscale-factor-0-5.html > [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_plane_scaling@planes-downscale-factor-0-5.html > > * igt@kms_pm_dc@deep-pkgc: > - shard-lnl: [FAIL][60] ([Intel XE#2029]) -> [SKIP][61] > [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-2/igt@kms_pm_dc@deep-pkgc.html > [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_pm_dc@deep-pkgc.html > > * igt@kms_psr@pr-no-drrs: > - shard-lnl: [SKIP][62] ([Intel XE#1406]) -> [SKIP][63] +4 other tests skip > [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_psr@pr-no-drrs.html > [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_psr@pr-no-drrs.html > > * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270: > - shard-lnl: [SKIP][64] ([Intel XE#1437]) -> [SKIP][65] +1 other test skip > [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html > [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html > > * igt@kms_vrr@seamless-rr-switch-drrs: > - shard-lnl: [SKIP][66] ([Intel XE#1499] / [Intel XE#599]) -> [SKIP][67] > [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_vrr@seamless-rr-switch-drrs.html > [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-drrs.html > > * igt@kms_writeback@writeback-check-output: > - shard-lnl: [SKIP][68] ([Intel XE#756]) -> [SKIP][69] > [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_writeback@writeback-check-output.html > [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_writeback@writeback-check-output.html > > > #### Suppressed #### > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * {igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p}: > - shard-lnl: [SKIP][70] ([Intel XE#2191]) -> [SKIP][71] > [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html > [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html > > * {igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p}: > - shard-lnl: [SKIP][72] ([Intel XE#1512]) -> [SKIP][73] > [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html > [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html > > * {igt@kms_vrr@cmrr}: > - shard-lnl: [PASS][74] -> [SKIP][75] > [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_vrr@cmrr.html > [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_vrr@cmrr.html > > * {igt@xe_oa@invalid-remove-userspace-config}: > - shard-lnl: NOTRUN -> [SKIP][76] +3 other tests skip > [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@xe_oa@invalid-remove-userspace-config.html > > * {igt@xe_oa@non-zero-reason}: > - shard-dg2-set2: [SKIP][77] ([Intel XE#1201]) -> [SKIP][78] > [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@xe_oa@non-zero-reason.html > [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_oa@non-zero-reason.html > > * {igt@xe_oa@oa-unit-concurrent-oa-buffer-read}: > - shard-dg2-set2: NOTRUN -> [SKIP][79] > [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_oa@oa-unit-concurrent-oa-buffer-read.html > > > Known issues > ------------ > > Here are the changes found in XEIGTPW_11488_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6: > - shard-dg2-set2: [PASS][80] -> [FAIL][81] ([Intel XE#1426]) +2 other tests fail > [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6.html > [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6.html > > * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1: > - shard-lnl: [PASS][82] -> [FAIL][83] ([Intel XE#1426]) +3 other tests fail > [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html > [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html > > * igt@kms_big_fb@4-tiled-16bpp-rotate-270: > - shard-lnl: NOTRUN -> [SKIP][84] ([Intel XE#1407]) +3 other tests skip > [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html > - shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#316]) > [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html > > * igt@kms_big_fb@4-tiled-addfb-size-overflow: > - shard-dg2-set2: [PASS][86] -> [SKIP][87] ([Intel XE#1201]) +23 other tests skip > [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_big_fb@4-tiled-addfb-size-overflow.html > [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_big_fb@4-tiled-addfb-size-overflow.html > > * igt@kms_big_fb@x-tiled-64bpp-rotate-90: > - shard-dg2-set2: NOTRUN -> [SKIP][88] ([Intel XE#1201] / [Intel XE#316]) +2 other tests skip > [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html > > * igt@kms_big_fb@y-tiled-32bpp-rotate-180: > - shard-lnl: NOTRUN -> [SKIP][89] ([Intel XE#1124]) +6 other tests skip > [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html > > * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: > - shard-dg2-set2: NOTRUN -> [SKIP][90] ([Intel XE#1124] / [Intel XE#1201]) +7 other tests skip > [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html > > * igt@kms_big_fb@yf-tiled-addfb-size-overflow: > - shard-dg2-set2: NOTRUN -> [SKIP][91] ([Intel XE#610]) > [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html > > * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180: > - shard-dg2-set2: NOTRUN -> [SKIP][92] ([Intel XE#1124]) > [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html > > * igt@kms_bw@linear-tiling-2-displays-2560x1440p: > - shard-dg2-set2: NOTRUN -> [SKIP][93] ([Intel XE#1201] / [Intel XE#367]) > [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html > - shard-lnl: NOTRUN -> [SKIP][94] ([Intel XE#367]) > [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html > > * igt@kms_ccs@bad-aux-stride-y-tiled-ccs: > - shard-lnl: NOTRUN -> [SKIP][95] ([Intel XE#1399]) +4 other tests skip > [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_ccs@bad-aux-stride-y-tiled-ccs.html > > * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-a-dp-4: > - shard-dg2-set2: NOTRUN -> [SKIP][96] ([Intel XE#787]) +6 other tests skip > [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-a-dp-4.html > > * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-d-dp-4: > - shard-dg2-set2: NOTRUN -> [SKIP][97] ([Intel XE#455] / [Intel XE#787]) > [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-d-dp-4.html > > * igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-dp-4: > - shard-dg2-set2: NOTRUN -> [SKIP][98] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +22 other tests skip > [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-dp-4.html > > * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6: > - shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#1201] / [Intel XE#787]) +97 other tests skip > [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html > > * igt@kms_chamelium_color@degamma: > - shard-dg2-set2: NOTRUN -> [SKIP][100] ([Intel XE#1201] / [Intel XE#306]) +2 other tests skip > [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_chamelium_color@degamma.html > - shard-lnl: NOTRUN -> [SKIP][101] ([Intel XE#306]) +1 other test skip > [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_chamelium_color@degamma.html > > * igt@kms_chamelium_frames@hdmi-cmp-planes-random: > - shard-lnl: NOTRUN -> [SKIP][102] ([Intel XE#373]) +5 other tests skip > [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_chamelium_frames@hdmi-cmp-planes-random.html > > * igt@kms_chamelium_frames@vga-frame-dump: > - shard-dg2-set2: NOTRUN -> [SKIP][103] ([Intel XE#1201] / [Intel XE#373]) +8 other tests skip > [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_chamelium_frames@vga-frame-dump.html > > * igt@kms_cursor_crc@cursor-rapid-movement-512x170: > - shard-dg2-set2: NOTRUN -> [SKIP][104] ([Intel XE#1201] / [Intel XE#308]) +1 other test skip > [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html > - shard-lnl: NOTRUN -> [SKIP][105] ([Intel XE#1413]) +1 other test skip > [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html > > * igt@kms_cursor_crc@cursor-sliding-64x21: > - shard-lnl: NOTRUN -> [SKIP][106] ([Intel XE#1424]) > [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_cursor_crc@cursor-sliding-64x21.html > > * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: > - shard-dg2-set2: NOTRUN -> [SKIP][107] ([Intel XE#1201] / [Intel XE#323]) > [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html > > * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic: > - shard-lnl: NOTRUN -> [SKIP][108] ([Intel XE#309]) > [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html > > * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6: > - shard-dg2-set2: NOTRUN -> [SKIP][109] ([Intel XE#1201] / [i915#3804]) > [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6.html > > * igt@kms_fbcon_fbt@psr: > - shard-dg2-set2: NOTRUN -> [SKIP][110] ([Intel XE#1201] / [Intel XE#776]) > [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_fbcon_fbt@psr.html > > * igt@kms_flip@2x-flip-vs-suspend-interruptible: > - shard-lnl: NOTRUN -> [SKIP][111] ([Intel XE#1421]) +2 other tests skip > [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_flip@2x-flip-vs-suspend-interruptible.html > > * igt@kms_flip@flip-vs-absolute-wf_vblank: > - shard-lnl: [PASS][112] -> [FAIL][113] ([Intel XE#886]) +2 other tests fail > [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_flip@flip-vs-absolute-wf_vblank.html > [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_flip@flip-vs-absolute-wf_vblank.html > > * igt@kms_flip@flip-vs-suspend@a-hdmi-a6: > - shard-dg2-set2: NOTRUN -> [DMESG-WARN][114] ([Intel XE#1551]) +1 other test dmesg-warn > [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_flip@flip-vs-suspend@a-hdmi-a6.html > > * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling: > - shard-lnl: NOTRUN -> [SKIP][115] ([Intel XE#1397] / [Intel XE#1745]) > [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html > > * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling: > - shard-lnl: [PASS][116] -> [SKIP][117] ([Intel XE#2351]) > [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling.html > [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling.html > > * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode: > - shard-lnl: NOTRUN -> [SKIP][118] ([Intel XE#1397]) +3 other tests skip > [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html > > * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling: > - shard-lnl: NOTRUN -> [SKIP][119] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip > [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html > > * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode: > - shard-lnl: NOTRUN -> [SKIP][120] ([Intel XE#1401]) +2 other tests skip > [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html > > * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render: > - shard-lnl: NOTRUN -> [SKIP][121] ([Intel XE#651]) +8 other tests skip > [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render.html > > * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc: > - shard-dg2-set2: NOTRUN -> [SKIP][122] ([Intel XE#1201] / [Intel XE#651]) +17 other tests skip > [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc.html > > * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt: > - shard-lnl: NOTRUN -> [SKIP][123] ([Intel XE#656]) +16 other tests skip > [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html > > * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt: > - shard-dg2-set2: NOTRUN -> [SKIP][124] ([Intel XE#651]) > [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt.html > > * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move: > - shard-dg2-set2: NOTRUN -> [SKIP][125] ([Intel XE#653]) +1 other test skip > [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move.html > > * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt: > - shard-lnl: NOTRUN -> [SKIP][126] ([Intel XE#2351]) > [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html > > * igt@kms_frontbuffer_tracking@fbcpsr-suspend: > - shard-lnl: [PASS][127] -> [FAIL][128] ([Intel XE#2028]) > [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html > [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html > > * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc: > - shard-dg2-set2: NOTRUN -> [SKIP][129] ([Intel XE#1201] / [Intel XE#653]) +22 other tests skip > [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html > > * igt@kms_hdmi_inject@inject-audio: > - shard-dg2-set2: NOTRUN -> [SKIP][130] ([Intel XE#1201] / [Intel XE#417]) > [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_hdmi_inject@inject-audio.html > - shard-lnl: NOTRUN -> [SKIP][131] ([Intel XE#1470]) > [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_hdmi_inject@inject-audio.html > > * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: > - shard-dg2-set2: NOTRUN -> [SKIP][132] ([Intel XE#1201] / [i915#2575]) +10 other tests skip > [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html > > * igt@kms_pipe_crc_basic@suspend-read-crc: > - shard-dg2-set2: [PASS][133] -> [DMESG-WARN][134] ([Intel XE#1162]) > [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_pipe_crc_basic@suspend-read-crc.html > [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_pipe_crc_basic@suspend-read-crc.html > > * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-4: > - shard-dg2-set2: [PASS][135] -> [DMESG-WARN][136] ([Intel XE#2019]) > [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-4.html > [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-4.html > > * igt@kms_plane@plane-position-hole-dpms: > - shard-lnl: [PASS][137] -> [DMESG-WARN][138] ([Intel XE#324]) > [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-7/igt@kms_plane@plane-position-hole-dpms.html > [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_plane@plane-position-hole-dpms.html > > * igt@kms_plane_lowres@tiling-x@pipe-b-edp-1: > - shard-lnl: NOTRUN -> [SKIP][139] ([Intel XE#599]) +3 other tests skip > [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_plane_lowres@tiling-x@pipe-b-edp-1.html > > * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-c-edp-1: > - shard-lnl: NOTRUN -> [SKIP][140] ([Intel XE#498]) +3 other tests skip > [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-c-edp-1.html > > * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling: > - shard-dg2-set2: NOTRUN -> [SKIP][141] ([Intel XE#2318] / [Intel XE#455]) > [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html > > * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-6: > - shard-dg2-set2: NOTRUN -> [SKIP][142] ([Intel XE#2318]) +2 other tests skip > [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-6.html > > * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-6: > - shard-dg2-set2: NOTRUN -> [SKIP][143] ([Intel XE#455]) +2 other tests skip > [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-6.html > > * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25: > - shard-dg2-set2: NOTRUN -> [SKIP][144] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) +1 other test skip > [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html > > * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1: > - shard-lnl: NOTRUN -> [SKIP][145] ([Intel XE#2318]) +14 other tests skip > [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1.html > > * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-6: > - shard-dg2-set2: NOTRUN -> [SKIP][146] ([Intel XE#1201] / [Intel XE#2318]) +5 other tests skip > [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-6.html > > * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-6: > - shard-dg2-set2: NOTRUN -> [SKIP][147] ([Intel XE#1201] / [Intel XE#455]) +10 other tests skip > [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-6.html > > * igt@kms_pm_rpm@modeset-non-lpsp: > - shard-lnl: NOTRUN -> [SKIP][148] ([Intel XE#1439]) > [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_pm_rpm@modeset-non-lpsp.html > > * igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-sf: > - shard-dg2-set2: NOTRUN -> [SKIP][149] ([Intel XE#1201] / [Intel XE#1489]) > [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-sf.html > > * igt@kms_psr2_su@page_flip-p010: > - shard-dg2-set2: NOTRUN -> [SKIP][150] ([Intel XE#1122] / [Intel XE#1201]) > [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_psr2_su@page_flip-p010.html > - shard-lnl: NOTRUN -> [SKIP][151] ([Intel XE#1128]) > [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_psr2_su@page_flip-p010.html > > * igt@kms_psr@fbc-psr2-sprite-plane-move: > - shard-dg2-set2: NOTRUN -> [SKIP][152] ([Intel XE#1201] / [Intel XE#929]) +11 other tests skip > [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_psr@fbc-psr2-sprite-plane-move.html > > * igt@kms_psr@fbc-psr2-suspend: > - shard-dg2-set2: NOTRUN -> [SKIP][153] ([Intel XE#1201]) +23 other tests skip > [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_psr@fbc-psr2-suspend.html > > * igt@kms_psr@pr-primary-blt: > - shard-lnl: NOTRUN -> [SKIP][154] ([Intel XE#1406]) +1 other test skip > [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_psr@pr-primary-blt.html > > * igt@kms_psr@psr2-no-drrs: > - shard-dg2-set2: NOTRUN -> [SKIP][155] ([Intel XE#929]) +2 other tests skip > [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_psr@psr2-no-drrs.html > > * igt@kms_rmfb@close-fd@pipe-a-edp-1: > - shard-lnl: NOTRUN -> [FAIL][156] ([Intel XE#294]) > [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_rmfb@close-fd@pipe-a-edp-1.html > > * igt@kms_rmfb@close-fd@pipe-b-dp-4: > - shard-dg2-set2: NOTRUN -> [FAIL][157] ([Intel XE#294]) +1 other test fail > [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_rmfb@close-fd@pipe-b-dp-4.html > > * igt@kms_vblank@ts-continuation-suspend: > - shard-dg2-set2: NOTRUN -> [DMESG-WARN][158] ([Intel XE#2019]) +3 other tests dmesg-warn > [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_vblank@ts-continuation-suspend.html > > * igt@kms_vblank@wait-forked-busy-hang: > - shard-dg2-set2: [PASS][159] -> [SKIP][160] ([Intel XE#1201] / [i915#2575]) +45 other tests skip > [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_vblank@wait-forked-busy-hang.html > [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_vblank@wait-forked-busy-hang.html > > * igt@kms_writeback@writeback-check-output-xrgb2101010: > - shard-dg2-set2: NOTRUN -> [SKIP][161] ([Intel XE#1201] / [Intel XE#756]) > [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_writeback@writeback-check-output-xrgb2101010.html > > * igt@kms_writeback@writeback-fb-id: > - shard-lnl: NOTRUN -> [SKIP][162] ([Intel XE#756]) > [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_writeback@writeback-fb-id.html > > * igt@xe_copy_basic@mem-copy-linear-0xfffe: > - shard-dg2-set2: NOTRUN -> [SKIP][163] ([Intel XE#1123]) > [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_copy_basic@mem-copy-linear-0xfffe.html > > * igt@xe_copy_basic@mem-set-linear-0xfffe: > - shard-dg2-set2: NOTRUN -> [SKIP][164] ([Intel XE#1126] / [Intel XE#1201]) > [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@xe_copy_basic@mem-set-linear-0xfffe.html > > * igt@xe_evict@evict-beng-cm-threads-large: > - shard-dg2-set2: NOTRUN -> [INCOMPLETE][165] ([Intel XE#1473] / [Intel XE#392]) > [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_evict@evict-beng-cm-threads-large.html > > * igt@xe_evict@evict-beng-cm-threads-small-multi-vm: > - shard-lnl: NOTRUN -> [SKIP][166] ([Intel XE#688]) +4 other tests skip > [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@xe_evict@evict-beng-cm-threads-small-multi-vm.html > > * igt@xe_evict@evict-beng-large-external-cm: > - shard-lnl: NOTRUN -> [SKIP][167] ([Intel XE#1130]) +12 other tests skip > [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@xe_evict@evict-beng-large-external-cm.html > > * igt@xe_evict@evict-beng-large-multi-vm-cm: > - shard-dg2-set2: NOTRUN -> [FAIL][168] ([Intel XE#1600]) > [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@xe_evict@evict-beng-large-multi-vm-cm.html > > * igt@xe_evict@evict-beng-mixed-many-threads-small: > - shard-dg2-set2: [PASS][169] -> [TIMEOUT][170] ([Intel XE#1473] / [Intel XE#402]) > [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@xe_evict@evict-beng-mixed-many-threads-small.html > [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_evict@evict-beng-mixed-many-threads-small.html > > * igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-reopen: > - shard-dg2-set2: NOTRUN -> [SKIP][171] ([Intel XE#1130] / [Intel XE#1201]) +24 other tests skip > [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-reopen.html > > * igt@xe_exec_balancer@many-cm-virtual-userptr-invalidate: > - shard-dg2-set2: [PASS][172] -> [SKIP][173] ([Intel XE#1130] / [Intel XE#1201]) +81 other tests skip > [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_exec_balancer@many-cm-virtual-userptr-invalidate.html > [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_exec_balancer@many-cm-virtual-userptr-invalidate.html > > * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race: > - shard-lnl: NOTRUN -> [SKIP][174] ([Intel XE#1392]) +5 other tests skip > [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html > > * igt@xe_exec_basic@no-exec-null-defer-bind: > - shard-lnl: [PASS][175] -> [SKIP][176] ([Intel XE#1130]) +95 other tests skip > [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@xe_exec_basic@no-exec-null-defer-bind.html > [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@xe_exec_basic@no-exec-null-defer-bind.html > > * igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-prefetch: > - shard-dg2-set2: NOTRUN -> [SKIP][177] ([Intel XE#1201] / [Intel XE#288]) +15 other tests skip > [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-prefetch.html > > * igt@xe_exec_fault_mode@once-rebind-prefetch: > - shard-dg2-set2: NOTRUN -> [SKIP][178] ([Intel XE#288]) +1 other test skip > [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_exec_fault_mode@once-rebind-prefetch.html > > * igt@xe_huc_copy@huc_copy: > - shard-dg2-set2: NOTRUN -> [SKIP][179] ([Intel XE#1201] / [Intel XE#255]) > [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_huc_copy@huc_copy.html > > * igt@xe_module_load@force-load: > - shard-dg2-set2: NOTRUN -> [SKIP][180] ([Intel XE#1201] / [Intel XE#378]) > [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_module_load@force-load.html > > * igt@xe_pat@display-vs-wb-transient: > - shard-dg2-set2: NOTRUN -> [SKIP][181] ([Intel XE#1201] / [Intel XE#1337]) > [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_pat@display-vs-wb-transient.html > > * igt@xe_pat@pat-index-xelpg: > - shard-dg2-set2: NOTRUN -> [SKIP][182] ([Intel XE#1201] / [Intel XE#979]) > [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_pat@pat-index-xelpg.html > - shard-lnl: NOTRUN -> [SKIP][183] ([Intel XE#979]) > [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@xe_pat@pat-index-xelpg.html > > * igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p: > - shard-dg2-set2: NOTRUN -> [FAIL][184] ([Intel XE#1173]) > [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html > > * igt@xe_pm@s2idle-basic-exec: > - shard-lnl: [PASS][185] -> [FAIL][186] ([Intel XE#1924] / [Intel XE#2028]) > [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@xe_pm@s2idle-basic-exec.html > [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@xe_pm@s2idle-basic-exec.html > > * igt@xe_pm@s3-vm-bind-userptr: > - shard-dg2-set2: NOTRUN -> [DMESG-WARN][187] ([Intel XE#1551] / [Intel XE#569]) +1 other test dmesg-warn > [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_pm@s3-vm-bind-userptr.html > - shard-lnl: NOTRUN -> [SKIP][188] ([Intel XE#584]) > [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@xe_pm@s3-vm-bind-userptr.html > > * igt@xe_query@multigpu-query-uc-fw-version-huc: > - shard-dg2-set2: NOTRUN -> [SKIP][189] ([Intel XE#1201] / [Intel XE#944]) +2 other tests skip > [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_query@multigpu-query-uc-fw-version-huc.html > - shard-lnl: NOTRUN -> [SKIP][190] ([Intel XE#944]) +2 other tests skip > [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@xe_query@multigpu-query-uc-fw-version-huc.html > > > #### Possible fixes #### > > * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip: > - shard-lnl: [FAIL][191] ([Intel XE#1659]) -> [PASS][192] > [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html > [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html > > * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip: > - shard-dg2-set2: [DMESG-WARN][193] -> [PASS][194] > [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html > [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html > > * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: > - shard-lnl: [SKIP][195] ([Intel XE#2351]) -> [PASS][196] +1 other test pass > [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html > [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html > > * igt@kms_cursor_crc@cursor-sliding-64x64: > - shard-dg2-set2: [SKIP][197] ([Intel XE#1201] / [i915#2575]) -> [PASS][198] +43 other tests pass > [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_cursor_crc@cursor-sliding-64x64.html > [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_cursor_crc@cursor-sliding-64x64.html > > * igt@kms_flip@flip-vs-wf_vblank-interruptible: > - shard-lnl: [SKIP][199] ([Intel XE#2366]) -> [PASS][200] +2 other tests pass > [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_flip@flip-vs-wf_vblank-interruptible.html > [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_flip@flip-vs-wf_vblank-interruptible.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc: > - shard-dg2-set2: [SKIP][201] ([Intel XE#1201]) -> [PASS][202] +24 other tests pass > [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html > [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt: > - shard-lnl: [SKIP][203] -> [PASS][204] +65 other tests pass > [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html > [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html > > * igt@kms_hdr@bpc-switch-suspend@pipe-a-edp-1: > - shard-lnl: [FAIL][205] ([Intel XE#2028]) -> [PASS][206] +1 other test pass > [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_hdr@bpc-switch-suspend@pipe-a-edp-1.html > [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_hdr@bpc-switch-suspend@pipe-a-edp-1.html > > * {igt@kms_plane@plane-position-hole@pipe-a-plane-2}: > - shard-lnl: [DMESG-FAIL][207] ([Intel XE#324]) -> [PASS][208] > [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_plane@plane-position-hole@pipe-a-plane-2.html > [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_plane@plane-position-hole@pipe-a-plane-2.html > > * {igt@kms_plane@plane-position-hole@pipe-b-plane-4}: > - shard-lnl: [DMESG-WARN][209] ([Intel XE#324]) -> [PASS][210] > [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_plane@plane-position-hole@pipe-b-plane-4.html > [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_plane@plane-position-hole@pipe-b-plane-4.html > > * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6: > - shard-dg2-set2: [FAIL][211] ([Intel XE#361]) -> [PASS][212] > [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html > [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html > > * igt@kms_pm_backlight@fade-with-suspend: > - shard-lnl: [INCOMPLETE][213] -> [PASS][214] > [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_pm_backlight@fade-with-suspend.html > [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_pm_backlight@fade-with-suspend.html > > * igt@kms_universal_plane@cursor-fb-leak: > - shard-dg2-set2: [FAIL][215] ([Intel XE#771] / [Intel XE#899]) -> [PASS][216] > [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_universal_plane@cursor-fb-leak.html > [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_universal_plane@cursor-fb-leak.html > > * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6: > - shard-dg2-set2: [FAIL][217] ([Intel XE#899]) -> [PASS][218] +1 other test pass > [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html > [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html > > * igt@xe_evict@evict-mixed-threads-large: > - shard-dg2-set2: [INCOMPLETE][219] ([Intel XE#1195] / [Intel XE#1473] / [Intel XE#392]) -> [PASS][220] +1 other test pass > [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_evict@evict-mixed-threads-large.html > [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@xe_evict@evict-mixed-threads-large.html > > * igt@xe_exec_basic@multigpu-no-exec-basic: > - shard-dg2-set2: [SKIP][221] ([Intel XE#1130] / [Intel XE#1201]) -> [PASS][222] +64 other tests pass > [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_exec_basic@multigpu-no-exec-basic.html > [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_exec_basic@multigpu-no-exec-basic.html > > * igt@xe_exec_threads@threads-userptr-rebind-err: > - shard-lnl: [SKIP][223] ([Intel XE#1130]) -> [PASS][224] +79 other tests pass > [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@xe_exec_threads@threads-userptr-rebind-err.html > [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@xe_exec_threads@threads-userptr-rebind-err.html > > * igt@xe_gt_freq@freq_fixed_exec: > - shard-dg2-set2: [FAIL][225] ([Intel XE#2262]) -> [PASS][226] > [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_gt_freq@freq_fixed_exec.html > [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_gt_freq@freq_fixed_exec.html > > * igt@xe_gt_freq@freq_reset_multiple: > - shard-lnl: [INCOMPLETE][227] ([Intel XE#1620] / [Intel XE#1760]) -> [PASS][228] > [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@xe_gt_freq@freq_reset_multiple.html > [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@xe_gt_freq@freq_reset_multiple.html > > * igt@xe_live_ktest@xe_bo: > - shard-dg2-set2: [SKIP][229] ([Intel XE#1192] / [Intel XE#1201]) -> [PASS][230] > [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_live_ktest@xe_bo.html > [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_live_ktest@xe_bo.html > > * igt@xe_pm@s2idle-basic: > - shard-lnl: [FAIL][231] ([Intel XE#1924] / [Intel XE#2028]) -> [PASS][232] > [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@xe_pm@s2idle-basic.html > [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@xe_pm@s2idle-basic.html > > * igt@xe_pm@s4-multiple-execs: > - shard-lnl: [ABORT][233] ([Intel XE#1358] / [Intel XE#1794]) -> [PASS][234] > [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-2/igt@xe_pm@s4-multiple-execs.html > [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@xe_pm@s4-multiple-execs.html > > * igt@xe_pm@s4-vm-bind-prefetch: > - shard-dg2-set2: [DMESG-WARN][235] ([Intel XE#2019]) -> [PASS][236] +1 other test pass > [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_pm@s4-vm-bind-prefetch.html > [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_pm@s4-vm-bind-prefetch.html > > * igt@xe_pm@s4-vm-bind-unbind-all: > - shard-dg2-set2: [DMESG-WARN][237] ([Intel XE#2019] / [Intel XE#2280]) -> [PASS][238] > [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_pm@s4-vm-bind-unbind-all.html > [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_pm@s4-vm-bind-unbind-all.html > > > #### Warnings #### > > * igt@core_hotunplug@hotunbind-rebind: > - shard-dg2-set2: [ABORT][239] -> [SKIP][240] ([Intel XE#1201]) > [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@core_hotunplug@hotunbind-rebind.html > [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@core_hotunplug@hotunbind-rebind.html > > * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: > - shard-dg2-set2: [SKIP][241] ([Intel XE#623]) -> [SKIP][242] ([Intel XE#1201] / [Intel XE#623]) > [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html > [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html > > * igt@kms_big_fb@4-tiled-64bpp-rotate-90: > - shard-dg2-set2: [SKIP][243] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][244] ([Intel XE#316]) > [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html > [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html > > * igt@kms_big_fb@linear-16bpp-rotate-270: > - shard-dg2-set2: [SKIP][245] ([Intel XE#316]) -> [SKIP][246] ([Intel XE#1201] / [Intel XE#316]) +1 other test skip > [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-270.html > [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_big_fb@linear-16bpp-rotate-270.html > > * igt@kms_big_fb@x-tiled-16bpp-rotate-90: > - shard-dg2-set2: [SKIP][247] ([Intel XE#316]) -> [SKIP][248] ([Intel XE#1201]) > [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html > [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html > > * igt@kms_big_fb@x-tiled-32bpp-rotate-270: > - shard-dg2-set2: [SKIP][249] ([Intel XE#1201]) -> [SKIP][250] ([Intel XE#1201] / [Intel XE#316]) +2 other tests skip > [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html > [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html > - shard-lnl: [SKIP][251] -> [SKIP][252] ([Intel XE#1407]) +2 other tests skip > [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html > [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html > > * igt@kms_big_fb@x-tiled-8bpp-rotate-270: > - shard-dg2-set2: [SKIP][253] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][254] ([Intel XE#1201]) +1 other test skip > [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html > [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html > > * igt@kms_big_fb@y-tiled-8bpp-rotate-270: > - shard-dg2-set2: [SKIP][255] ([Intel XE#1201]) -> [SKIP][256] ([Intel XE#1124] / [Intel XE#1201]) +2 other tests skip > [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html > [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html > > * igt@kms_big_fb@y-tiled-addfb: > - shard-dg2-set2: [SKIP][257] ([Intel XE#1201]) -> [SKIP][258] ([Intel XE#1201] / [Intel XE#619]) > [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_big_fb@y-tiled-addfb.html > [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_big_fb@y-tiled-addfb.html > - shard-lnl: [SKIP][259] -> [SKIP][260] ([Intel XE#1467]) > [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_big_fb@y-tiled-addfb.html > [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_big_fb@y-tiled-addfb.html > > * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0: > - shard-dg2-set2: [SKIP][261] ([Intel XE#1124]) -> [SKIP][262] ([Intel XE#1124] / [Intel XE#1201]) +6 other tests skip > [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html > [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html > > * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip: > - shard-dg2-set2: [SKIP][263] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][264] ([Intel XE#1124]) +1 other test skip > [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html > [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html > > * igt@kms_big_fb@yf-tiled-64bpp-rotate-90: > - shard-dg2-set2: [SKIP][265] ([Intel XE#1201]) -> [SKIP][266] ([Intel XE#1124]) > [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html > [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html > - shard-lnl: [SKIP][267] -> [SKIP][268] ([Intel XE#1124]) +3 other tests skip > [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html > [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html > > * igt@kms_big_fb@yf-tiled-addfb-size-overflow: > - shard-lnl: [SKIP][269] -> [SKIP][270] ([Intel XE#1428]) > [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html > [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html > > * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: > - shard-dg2-set2: [SKIP][271] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][272] ([Intel XE#1201]) +6 other tests skip > [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html > [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html > > * igt@kms_big_joiner@basic: > - shard-dg2-set2: [SKIP][273] ([Intel XE#1201]) -> [SKIP][274] ([Intel XE#1201] / [Intel XE#346]) > [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_big_joiner@basic.html > [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_big_joiner@basic.html > - shard-lnl: [SKIP][275] -> [SKIP][276] ([Intel XE#346]) > [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_big_joiner@basic.html > [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_big_joiner@basic.html > > * igt@kms_bw@linear-tiling-1-displays-3840x2160p: > - shard-dg2-set2: [SKIP][277] ([Intel XE#367]) -> [SKIP][278] ([Intel XE#1201] / [Intel XE#367]) +1 other test skip > [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html > [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html > > * igt@kms_bw@linear-tiling-2-displays-2160x1440p: > - shard-dg2-set2: [SKIP][279] ([Intel XE#1201] / [i915#2575]) -> [SKIP][280] ([Intel XE#1201] / [Intel XE#367]) > [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html > [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html > - shard-lnl: [SKIP][281] -> [SKIP][282] ([Intel XE#367]) > [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html > [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html > > * igt@kms_bw@linear-tiling-4-displays-1920x1080p: > - shard-dg2-set2: [SKIP][283] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][284] ([Intel XE#367]) > [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html > [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html > > * igt@kms_bw@linear-tiling-4-displays-2560x1440p: > - shard-dg2-set2: [SKIP][285] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][286] ([Intel XE#1201] / [i915#2575]) > [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html > [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html > > * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs: > - shard-dg2-set2: [SKIP][287] ([Intel XE#1201]) -> [SKIP][288] ([Intel XE#455] / [Intel XE#787]) > [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html > [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html > > * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs: > - shard-lnl: [SKIP][289] -> [SKIP][290] ([Intel XE#1399]) +11 other tests skip > [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html > [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html > > * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4: > - shard-dg2-set2: [SKIP][291] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][292] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +11 other tests skip > [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html > [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html > > * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs: > - shard-dg2-set2: [SKIP][293] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][294] ([Intel XE#1201]) +1 other test skip > [293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs.html > [294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs.html > > * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs: > - shard-dg2-set2: [SKIP][295] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][296] ([Intel XE#1201]) +6 other tests skip > [295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html > [296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html > > * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs: > - shard-dg2-set2: [SKIP][297] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][298] ([Intel XE#455] / [Intel XE#787]) +5 other tests skip > [297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html > [298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html > > * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-6: > - shard-dg2-set2: [SKIP][299] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][300] ([Intel XE#787]) +20 other tests skip > [299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-6.html > [300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-6.html > > * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc: > - shard-dg2-set2: [SKIP][301] ([Intel XE#1201]) -> [SKIP][302] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +4 other tests skip > [301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc.html > [302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc.html > > * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4: > - shard-dg2-set2: [SKIP][303] ([Intel XE#787]) -> [SKIP][304] ([Intel XE#1201] / [Intel XE#787]) +41 other tests skip > [303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html > [304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html > > * igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs: > - shard-dg2-set2: [SKIP][305] ([Intel XE#1252]) -> [SKIP][306] ([Intel XE#1201]) > [305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html > [306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html > > * igt@kms_chamelium_color@ctm-0-50: > - shard-dg2-set2: [SKIP][307] ([Intel XE#306]) -> [SKIP][308] ([Intel XE#1201] / [i915#2575]) > [307]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_chamelium_color@ctm-0-50.html > [308]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_chamelium_color@ctm-0-50.html > > * igt@kms_chamelium_color@gamma: > - shard-dg2-set2: [SKIP][309] ([Intel XE#1201] / [Intel XE#306]) -> [SKIP][310] ([Intel XE#306]) +1 other test skip > [309]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_chamelium_color@gamma.html > [310]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_chamelium_color@gamma.html > > * igt@kms_chamelium_edid@dp-edid-stress-resolution-4k: > - shard-dg2-set2: [SKIP][311] ([Intel XE#373]) -> [SKIP][312] ([Intel XE#1201] / [Intel XE#373]) +5 other tests skip > [311]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html > [312]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html > > * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k: > - shard-dg2-set2: [SKIP][313] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][314] ([Intel XE#1201] / [i915#2575]) +4 other tests skip > [313]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html > [314]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html > > * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend: > - shard-lnl: [SKIP][315] -> [SKIP][316] ([Intel XE#373]) +5 other tests skip > [315]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html > [316]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html > > * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k: > - shard-dg2-set2: [SKIP][317] ([Intel XE#1201] / [i915#2575]) -> [SKIP][318] ([Intel XE#1201] / [Intel XE#373]) +3 other tests skip > [317]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html > [318]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html > > * igt@kms_chamelium_frames@hdmi-aspect-ratio: > - shard-dg2-set2: [SKIP][319] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][320] ([Intel XE#373]) > [319]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_chamelium_frames@hdmi-aspect-ratio.html > [320]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_chamelium_frames@hdmi-aspect-ratio.html > > * igt@kms_chamelium_frames@hdmi-crc-single: > - shard-dg2-set2: [SKIP][321] ([Intel XE#1201] / [i915#2575]) -> [SKIP][322] ([Intel XE#373]) > [321]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_chamelium_frames@hdmi-crc-single.html > [322]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_chamelium_frames@hdmi-crc-single.html > > * igt@kms_chamelium_hpd@vga-hpd: > - shard-dg2-set2: [SKIP][323] ([Intel XE#373]) -> [SKIP][324] ([Intel XE#1201] / [i915#2575]) +1 other test skip > [323]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_chamelium_hpd@vga-hpd.html > [324]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_chamelium_hpd@vga-hpd.html > - shard-lnl: [SKIP][325] ([Intel XE#373]) -> [SKIP][326] ([Intel XE#2366]) > [325]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_chamelium_hpd@vga-hpd.html > [326]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_chamelium_hpd@vga-hpd.html > > * igt@kms_content_protection@dp-mst-lic-type-0: > - shard-dg2-set2: [SKIP][327] ([Intel XE#1201] / [i915#2575]) -> [SKIP][328] ([Intel XE#1201] / [Intel XE#307]) > [327]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_content_protection@dp-mst-lic-type-0.html > [328]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_content_protection@dp-mst-lic-type-0.html > - shard-lnl: [SKIP][329] -> [SKIP][330] ([Intel XE#307]) > [329]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_content_protection@dp-mst-lic-type-0.html > [330]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_content_protection@dp-mst-lic-type-0.html > > * igt@kms_content_protection@dp-mst-lic-type-1: > - shard-dg2-set2: [SKIP][331] ([Intel XE#1201] / [Intel XE#307]) -> [SKIP][332] ([Intel XE#1201] / [i915#2575]) > [331]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_content_protection@dp-mst-lic-type-1.html > [332]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_content_protection@dp-mst-lic-type-1.html > > * igt@kms_content_protection@lic-type-1: > - shard-dg2-set2: [SKIP][333] ([Intel XE#455]) -> [SKIP][334] ([Intel XE#1201] / [i915#2575]) +2 other tests skip > [333]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_content_protection@lic-type-1.html > [334]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_content_protection@lic-type-1.html > - shard-lnl: [SKIP][335] ([Intel XE#599]) -> [SKIP][336] ([Intel XE#2366]) > [335]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_content_protection@lic-type-1.html > [336]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_content_protection@lic-type-1.html > > * igt@kms_cursor_crc@cursor-offscreen-512x512: > - shard-dg2-set2: [SKIP][337] ([Intel XE#1201] / [i915#2575]) -> [SKIP][338] ([Intel XE#1201] / [Intel XE#308]) +1 other test skip > [337]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_cursor_crc@cursor-offscreen-512x512.html > [338]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_cursor_crc@cursor-offscreen-512x512.html > - shard-lnl: [SKIP][339] -> [SKIP][340] ([Intel XE#1413]) +1 other test skip > [339]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_cursor_crc@cursor-offscreen-512x512.html > [340]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_cursor_crc@cursor-offscreen-512x512.html > > * igt@kms_cursor_crc@cursor-rapid-movement-256x85: > - shard-lnl: [SKIP][341] -> [SKIP][342] ([Intel XE#1424]) +1 other test skip > [341]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html > [342]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html > > * igt@kms_cursor_crc@cursor-sliding-512x170: > - shard-dg2-set2: [SKIP][343] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][344] ([Intel XE#1201] / [i915#2575]) > [343]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_cursor_crc@cursor-sliding-512x170.html > [344]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_cursor_crc@cursor-sliding-512x170.html > > * igt@kms_cursor_crc@cursor-sliding-512x512: > - shard-dg2-set2: [SKIP][345] ([Intel XE#308]) -> [SKIP][346] ([Intel XE#1201] / [Intel XE#308]) +1 other test skip > [345]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_cursor_crc@cursor-sliding-512x512.html > [346]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_cursor_crc@cursor-sliding-512x512.html > > * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: > - shard-lnl: [SKIP][347] -> [SKIP][348] ([Intel XE#309]) +3 other tests skip > [347]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html > [348]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html > > * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: > - shard-lnl: [SKIP][349] -> [SKIP][350] ([Intel XE#323]) > [349]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html > [350]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html > > * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic: > - shard-lnl: [SKIP][351] ([Intel XE#309]) -> [SKIP][352] ([Intel XE#2366]) > [351]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html > [352]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html > > * igt@kms_dirtyfb@drrs-dirtyfb-ioctl: > - shard-dg2-set2: [SKIP][353] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][354] ([Intel XE#455]) +3 other tests skip > [353]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html > [354]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html > > * igt@kms_dsc@dsc-fractional-bpp-with-bpc: > - shard-dg2-set2: [SKIP][355] ([Intel XE#1201]) -> [SKIP][356] ([Intel XE#1201] / [Intel XE#455]) +1 other test skip > [355]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html > [356]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html > > * igt@kms_dsc@dsc-with-bpc-formats: > - shard-dg2-set2: [SKIP][357] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][358] ([Intel XE#1201]) +3 other tests skip > [357]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_dsc@dsc-with-bpc-formats.html > [358]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_dsc@dsc-with-bpc-formats.html > > * igt@kms_fbcon_fbt@psr-suspend: > - shard-dg2-set2: [SKIP][359] ([Intel XE#1201] / [Intel XE#776]) -> [SKIP][360] ([Intel XE#1201]) > [359]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_fbcon_fbt@psr-suspend.html > [360]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_fbcon_fbt@psr-suspend.html > > * igt@kms_feature_discovery@chamelium: > - shard-dg2-set2: [SKIP][361] ([Intel XE#701]) -> [SKIP][362] ([Intel XE#1201] / [Intel XE#701]) > [361]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_feature_discovery@chamelium.html > [362]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_feature_discovery@chamelium.html > > * igt@kms_feature_discovery@display-3x: > - shard-dg2-set2: [SKIP][363] ([Intel XE#1201] / [Intel XE#703]) -> [SKIP][364] ([Intel XE#1201] / [i915#2575]) > [363]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_feature_discovery@display-3x.html > [364]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_feature_discovery@display-3x.html > > * igt@kms_feature_discovery@display-4x: > - shard-dg2-set2: [SKIP][365] ([Intel XE#1201] / [i915#2575]) -> [SKIP][366] ([Intel XE#1138]) > [365]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_feature_discovery@display-4x.html > [366]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_feature_discovery@display-4x.html > - shard-lnl: [SKIP][367] -> [SKIP][368] ([Intel XE#1138]) > [367]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_feature_discovery@display-4x.html > [368]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_feature_discovery@display-4x.html > > * igt@kms_feature_discovery@psr1: > - shard-dg2-set2: [SKIP][369] ([Intel XE#1201] / [i915#2575]) -> [SKIP][370] ([Intel XE#1135] / [Intel XE#1201]) > [369]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_feature_discovery@psr1.html > [370]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_feature_discovery@psr1.html > > * igt@kms_flip@2x-absolute-wf_vblank-interruptible: > - shard-lnl: [SKIP][371] -> [SKIP][372] ([Intel XE#1421]) +1 other test skip > [371]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html > [372]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html > > * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling: > - shard-lnl: [SKIP][373] -> [SKIP][374] ([Intel XE#1397] / [Intel XE#1745]) +2 other tests skip > [373]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html > [374]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html > > * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling: > - shard-lnl: [SKIP][375] -> [SKIP][376] ([Intel XE#1401] / [Intel XE#1745]) > [375]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html > [376]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html > > * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling: > - shard-dg2-set2: [SKIP][377] ([Intel XE#455]) -> [SKIP][378] ([Intel XE#1201] / [Intel XE#455]) +12 other tests skip > [377]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html > [378]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html > > * igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-blt: > - shard-dg2-set2: [SKIP][379] ([Intel XE#1201]) -> [SKIP][380] ([Intel XE#651]) +2 other tests skip > [379]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-blt.html > [380]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-blt.html > > * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff: > - shard-dg2-set2: [SKIP][381] ([Intel XE#651]) -> [SKIP][382] ([Intel XE#1201]) +2 other tests skip > [381]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html > [382]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html > > * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt: > - shard-lnl: [SKIP][383] -> [SKIP][384] ([Intel XE#651]) +8 other tests skip > [383]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt.html > [384]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt.html > > * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt: > - shard-dg2-set2: [SKIP][385] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][386] ([Intel XE#1201]) +14 other tests skip > [385]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt.html > [386]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt.html > > * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render: > - shard-lnl: [SKIP][387] -> [SKIP][388] ([Intel XE#656]) +17 other tests skip > [387]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render.html > [388]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render.html > > * igt@kms_frontbuffer_tracking@fbc-tiling-y: > - shard-dg2-set2: [SKIP][389] ([Intel XE#1201] / [Intel XE#658]) -> [SKIP][390] ([Intel XE#1201]) > [389]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-tiling-y.html > [390]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-tiling-y.html > > * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-render: > - shard-lnl: [SKIP][391] ([Intel XE#651]) -> [SKIP][392] ([Intel XE#2351]) > [391]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-render.html > [392]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-render.html > > * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt: > - shard-dg2-set2: [SKIP][393] ([Intel XE#1201]) -> [SKIP][394] ([Intel XE#1201] / [Intel XE#651]) +10 other tests skip > [393]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt.html > [394]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt.html > > * igt@kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-blt: > - shard-dg2-set2: [SKIP][395] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][396] ([Intel XE#651]) +6 other tests skip > [395]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-blt.html > [396]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-blt.html > > * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear: > - shard-dg2-set2: [SKIP][397] ([Intel XE#651]) -> [SKIP][398] ([Intel XE#1201] / [Intel XE#651]) +16 other tests skip > [397]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear.html > [398]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear.html > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc: > - shard-dg2-set2: [SKIP][399] ([Intel XE#1201]) -> [SKIP][400] ([Intel XE#653]) > [399]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html > [400]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html > > * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt: > - shard-dg2-set2: [SKIP][401] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][402] ([Intel XE#1201]) +12 other tests skip > [401]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html > [402]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html > > * igt@kms_frontbuffer_tracking@fbcpsr-slowdraw: > - shard-dg2-set2: [SKIP][403] ([Intel XE#1201]) -> [SKIP][404] ([Intel XE#1201] / [Intel XE#653]) +12 other tests skip > [403]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html > [404]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html > > * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y: > - shard-dg2-set2: [SKIP][405] ([Intel XE#658]) -> [SKIP][406] ([Intel XE#1201] / [Intel XE#658]) > [405]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html > [406]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt: > - shard-dg2-set2: [SKIP][407] ([Intel XE#653]) -> [SKIP][408] ([Intel XE#1201] / [Intel XE#653]) +16 other tests skip > [407]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html > [408]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move: > - shard-dg2-set2: [SKIP][409] ([Intel XE#653]) -> [SKIP][410] ([Intel XE#1201]) +2 other tests skip > [409]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html > [410]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html > > * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc: > - shard-dg2-set2: [SKIP][411] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][412] ([Intel XE#653]) +8 other tests skip > [411]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html > [412]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html > > * igt@kms_getfb@getfb-reject-ccs: > - shard-lnl: [SKIP][413] -> [SKIP][414] ([Intel XE#605]) > [413]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_getfb@getfb-reject-ccs.html > [414]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_getfb@getfb-reject-ccs.html > - shard-dg2-set2: [SKIP][415] ([Intel XE#1201] / [i915#2575]) -> [SKIP][416] ([Intel XE#1201] / [Intel XE#605]) > [415]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_getfb@getfb-reject-ccs.html > [416]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_getfb@getfb-reject-ccs.html > > * igt@kms_getfb@getfb2-accept-ccs: > - shard-lnl: [SKIP][417] ([Intel XE#2340]) -> [SKIP][418] ([Intel XE#2366]) > [417]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_getfb@getfb2-accept-ccs.html > [418]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_getfb@getfb2-accept-ccs.html > > * igt@kms_panel_fitting@legacy: > - shard-dg2-set2: [SKIP][419] ([Intel XE#1201] / [i915#2575]) -> [SKIP][420] ([Intel XE#1201] / [Intel XE#455]) +2 other tests skip > [419]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_panel_fitting@legacy.html > [420]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_panel_fitting@legacy.html > > * igt@kms_plane_multiple@tiling-y: > - shard-dg2-set2: [SKIP][421] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][422] ([Intel XE#1201] / [i915#2575]) +4 other tests skip > [421]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_plane_multiple@tiling-y.html > [422]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_plane_multiple@tiling-y.html > > * igt@kms_plane_multiple@tiling-yf: > - shard-lnl: [SKIP][423] -> [SKIP][424] ([Intel XE#599]) +2 other tests skip > [423]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_plane_multiple@tiling-yf.html > [424]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_plane_multiple@tiling-yf.html > > * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25: > - shard-lnl: [SKIP][425] -> [SKIP][426] ([Intel XE#2318]) > [425]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html > [426]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html > > * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25: > - shard-dg2-set2: [SKIP][427] ([Intel XE#2318] / [Intel XE#455]) -> [SKIP][428] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) > [427]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html > [428]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html > > * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6: > - shard-dg2-set2: [SKIP][429] ([Intel XE#2318]) -> [SKIP][430] ([Intel XE#1201] / [Intel XE#2318]) +2 other tests skip > [429]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6.html > [430]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-6.html > > * igt@kms_pm_backlight@fade: > - shard-dg2-set2: [SKIP][431] ([Intel XE#870]) -> [SKIP][432] ([Intel XE#1201] / [Intel XE#870]) > [431]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_pm_backlight@fade.html > [432]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_pm_backlight@fade.html > > * igt@kms_pm_dc@dc3co-vpb-simulation: > - shard-dg2-set2: [SKIP][433] ([Intel XE#1201]) -> [SKIP][434] ([Intel XE#1122] / [Intel XE#1201]) > [433]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_pm_dc@dc3co-vpb-simulation.html > [434]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_pm_dc@dc3co-vpb-simulation.html > - shard-lnl: [SKIP][435] -> [SKIP][436] ([Intel XE#736]) > [435]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@kms_pm_dc@dc3co-vpb-simulation.html > [436]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_pm_dc@dc3co-vpb-simulation.html > > * igt@kms_pm_dc@dc6-psr: > - shard-dg2-set2: [SKIP][437] ([Intel XE#1129] / [Intel XE#1201]) -> [SKIP][438] ([Intel XE#1129]) > [437]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_pm_dc@dc6-psr.html > [438]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_pm_dc@dc6-psr.html > > * igt@kms_pm_dc@deep-pkgc: > - shard-dg2-set2: [SKIP][439] ([Intel XE#1201] / [Intel XE#908]) -> [SKIP][440] ([Intel XE#1201]) > [439]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_pm_dc@deep-pkgc.html > [440]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_pm_dc@deep-pkgc.html > > * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf: > - shard-dg2-set2: [SKIP][441] ([Intel XE#1201]) -> [SKIP][442] ([Intel XE#1201] / [Intel XE#1489]) +2 other tests skip > [441]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html > [442]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html > > * igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area: > - shard-dg2-set2: [SKIP][443] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][444] ([Intel XE#1201]) +1 other test skip > [443]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area.html > [444]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area.html > > * igt@kms_psr2_sf@overlay-plane-move-continuous-sf: > - shard-dg2-set2: [SKIP][445] ([Intel XE#1489]) -> [SKIP][446] ([Intel XE#1201] / [Intel XE#1489]) +2 other tests skip > [445]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html > [446]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html > > * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area: > - shard-dg2-set2: [SKIP][447] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][448] ([Intel XE#1489]) +2 other tests skip > [447]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html > [448]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html > > * igt@kms_psr@fbc-pr-cursor-plane-move: > - shard-dg2-set2: [SKIP][449] ([Intel XE#1201]) -> [SKIP][450] ([Intel XE#1201] / [Intel XE#929]) +6 other tests skip > [449]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_psr@fbc-pr-cursor-plane-move.html > [450]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_psr@fbc-pr-cursor-plane-move.html > - shard-lnl: [SKIP][451] -> [SKIP][452] ([Intel XE#1406]) +2 other tests skip > [451]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_psr@fbc-pr-cursor-plane-move.html > [452]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@kms_psr@fbc-pr-cursor-plane-move.html > > * igt@kms_psr@fbc-pr-no-drrs: > - shard-dg2-set2: [SKIP][453] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][454] ([Intel XE#1201]) +6 other tests skip > [453]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@kms_psr@fbc-pr-no-drrs.html > [454]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@kms_psr@fbc-pr-no-drrs.html > > * igt@kms_psr@fbc-psr2-primary-blt: > - shard-dg2-set2: [SKIP][455] ([Intel XE#929]) -> [SKIP][456] ([Intel XE#1201] / [Intel XE#929]) +8 other tests skip > [455]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_psr@fbc-psr2-primary-blt.html > [456]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@kms_psr@fbc-psr2-primary-blt.html > > * igt@kms_psr@pr-basic: > - shard-lnl: [SKIP][457] ([Intel XE#2351]) -> [SKIP][458] ([Intel XE#1406]) > [457]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_psr@pr-basic.html > [458]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@kms_psr@pr-basic.html > > * igt@kms_psr@psr-cursor-render: > - shard-dg2-set2: [SKIP][459] ([Intel XE#1201]) -> [SKIP][460] ([Intel XE#929]) +1 other test skip > [459]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_psr@psr-cursor-render.html > [460]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_psr@psr-cursor-render.html > > * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: > - shard-dg2-set2: [SKIP][461] ([Intel XE#1201]) -> [SKIP][462] ([Intel XE#1149] / [Intel XE#1201]) > [461]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html > [462]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html > > * igt@kms_rmfb@close-fd: > - shard-dg2-set2: [SKIP][463] ([Intel XE#1201] / [i915#2575]) -> [FAIL][464] ([Intel XE#294]) > [463]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@kms_rmfb@close-fd.html > [464]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@kms_rmfb@close-fd.html > - shard-lnl: [SKIP][465] -> [FAIL][466] ([Intel XE#294]) > [465]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@kms_rmfb@close-fd.html > [466]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_rmfb@close-fd.html > > * igt@kms_rotation_crc@bad-tiling: > - shard-dg2-set2: [SKIP][467] ([Intel XE#1201] / [i915#2575]) -> [SKIP][468] ([Intel XE#327]) > [467]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_rotation_crc@bad-tiling.html > [468]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_rotation_crc@bad-tiling.html > - shard-lnl: [SKIP][469] -> [SKIP][470] ([Intel XE#1437]) > [469]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@kms_rotation_crc@bad-tiling.html > [470]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@kms_rotation_crc@bad-tiling.html > > * igt@kms_rotation_crc@primary-rotation-90: > - shard-dg2-set2: [SKIP][471] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][472] ([Intel XE#327]) > [471]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@kms_rotation_crc@primary-rotation-90.html > [472]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@kms_rotation_crc@primary-rotation-90.html > > * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180: > - shard-dg2-set2: [SKIP][473] ([Intel XE#1201] / [i915#2575]) -> [SKIP][474] ([Intel XE#1127] / [Intel XE#1201]) +1 other test skip > [473]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html > [474]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html > > * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90: > - shard-dg2-set2: [SKIP][475] ([Intel XE#327]) -> [SKIP][476] ([Intel XE#1201] / [Intel XE#327]) +1 other test skip > [475]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html > [476]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html > > * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0: > - shard-lnl: [SKIP][477] -> [SKIP][478] ([Intel XE#1127]) +1 other test skip > [477]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html > [478]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html > > * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270: > - shard-dg2-set2: [SKIP][479] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][480] ([Intel XE#1201] / [i915#2575]) +1 other test skip > [479]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html > [480]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html > > * igt@kms_writeback@writeback-check-output: > - shard-dg2-set2: [SKIP][481] ([Intel XE#1201] / [Intel XE#756]) -> [SKIP][482] ([Intel XE#1201] / [i915#2575]) > [481]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@kms_writeback@writeback-check-output.html > [482]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@kms_writeback@writeback-check-output.html > > * igt@kms_writeback@writeback-check-output-xrgb2101010: > - shard-lnl: [SKIP][483] -> [SKIP][484] ([Intel XE#756]) > [483]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-4/igt@kms_writeback@writeback-check-output-xrgb2101010.html > [484]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@kms_writeback@writeback-check-output-xrgb2101010.html > > * igt@kms_writeback@writeback-invalid-parameters: > - shard-dg2-set2: [SKIP][485] ([Intel XE#756]) -> [SKIP][486] ([Intel XE#1201] / [Intel XE#756]) > [485]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@kms_writeback@writeback-invalid-parameters.html > [486]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@kms_writeback@writeback-invalid-parameters.html > > * igt@sriov_basic@enable-vfs-autoprobe-off: > - shard-dg2-set2: [SKIP][487] ([Intel XE#1091] / [Intel XE#1201]) -> [SKIP][488] ([Intel XE#1091]) > [487]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@sriov_basic@enable-vfs-autoprobe-off.html > [488]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@sriov_basic@enable-vfs-autoprobe-off.html > > * igt@xe_compute@ccs-mode-compute-kernel: > - shard-dg2-set2: [SKIP][489] ([Intel XE#1130] / [Intel XE#1201]) -> [FAIL][490] ([Intel XE#1050]) > [489]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_compute@ccs-mode-compute-kernel.html > [490]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_compute@ccs-mode-compute-kernel.html > - shard-lnl: [SKIP][491] ([Intel XE#1130]) -> [SKIP][492] ([Intel XE#1447]) > [491]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@xe_compute@ccs-mode-compute-kernel.html > [492]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@xe_compute@ccs-mode-compute-kernel.html > > * igt@xe_compute_preempt@compute-preempt: > - shard-dg2-set2: [SKIP][493] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][494] ([Intel XE#1201] / [Intel XE#1280] / [Intel XE#455]) +1 other test skip > [493]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_compute_preempt@compute-preempt.html > [494]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_compute_preempt@compute-preempt.html > > * igt@xe_compute_preempt@compute-threadgroup-preempt: > - shard-dg2-set2: [SKIP][495] ([Intel XE#1201] / [Intel XE#1280] / [Intel XE#455]) -> [SKIP][496] ([Intel XE#1130] / [Intel XE#1201]) > [495]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_compute_preempt@compute-threadgroup-preempt.html > [496]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@xe_compute_preempt@compute-threadgroup-preempt.html > > * igt@xe_copy_basic@mem-copy-linear-0x369: > - shard-dg2-set2: [SKIP][497] ([Intel XE#1123] / [Intel XE#1201]) -> [SKIP][498] ([Intel XE#1123]) > [497]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-433/igt@xe_copy_basic@mem-copy-linear-0x369.html > [498]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_copy_basic@mem-copy-linear-0x369.html > > * igt@xe_copy_basic@mem-set-linear-0x3fff: > - shard-dg2-set2: [SKIP][499] ([Intel XE#1126] / [Intel XE#1201]) -> [SKIP][500] ([Intel XE#1130] / [Intel XE#1201]) > [499]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_copy_basic@mem-set-linear-0x3fff.html > [500]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_copy_basic@mem-set-linear-0x3fff.html > > * igt@xe_evict@evict-beng-mixed-threads-large-multi-vm: > - shard-lnl: [SKIP][501] ([Intel XE#688]) -> [SKIP][502] ([Intel XE#1130]) +6 other tests skip > [501]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@xe_evict@evict-beng-mixed-threads-large-multi-vm.html > [502]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@xe_evict@evict-beng-mixed-threads-large-multi-vm.html > > * igt@xe_evict@evict-mixed-many-threads-large: > - shard-dg2-set2: [TIMEOUT][503] ([Intel XE#1041] / [Intel XE#1473] / [Intel XE#392]) -> [SKIP][504] ([Intel XE#1130] / [Intel XE#1201]) > [503]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_evict@evict-mixed-many-threads-large.html > [504]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_evict@evict-mixed-many-threads-large.html > > * igt@xe_evict@evict-threads-small-multi-vm: > - shard-lnl: [SKIP][505] ([Intel XE#1130]) -> [SKIP][506] ([Intel XE#688]) +2 other tests skip > [505]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@xe_evict@evict-threads-small-multi-vm.html > [506]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-4/igt@xe_evict@evict-threads-small-multi-vm.html > > * igt@xe_exec_basic@multigpu-no-exec-basic: > - shard-lnl: [SKIP][507] ([Intel XE#1130]) -> [SKIP][508] ([Intel XE#1392]) +3 other tests skip > [507]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-6/igt@xe_exec_basic@multigpu-no-exec-basic.html > [508]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-3/igt@xe_exec_basic@multigpu-no-exec-basic.html > > * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind: > - shard-lnl: [SKIP][509] ([Intel XE#1392]) -> [SKIP][510] ([Intel XE#1130]) +2 other tests skip > [509]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html > [510]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-7/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html > > * igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate: > - shard-dg2-set2: [SKIP][511] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][512] ([Intel XE#1130] / [Intel XE#1201]) +10 other tests skip > [511]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-466/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate.html > [512]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate.html > > * igt@xe_exec_fault_mode@many-execqueues-userptr-rebind: > - shard-dg2-set2: [SKIP][513] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][514] ([Intel XE#288]) > [513]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_exec_fault_mode@many-execqueues-userptr-rebind.html > [514]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_exec_fault_mode@many-execqueues-userptr-rebind.html > > * igt@xe_exec_fault_mode@once-invalid-userptr-fault: > - shard-dg2-set2: [SKIP][515] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][516] ([Intel XE#1201] / [Intel XE#288]) +13 other tests skip > [515]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html > [516]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-466/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html > > * igt@xe_exec_fault_mode@once-userptr-invalidate-race-imm: > - shard-dg2-set2: [SKIP][517] ([Intel XE#288]) -> [SKIP][518] ([Intel XE#1201] / [Intel XE#288]) +18 other tests skip > [517]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_exec_fault_mode@once-userptr-invalidate-race-imm.html > [518]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_exec_fault_mode@once-userptr-invalidate-race-imm.html > > * igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm: > - shard-dg2-set2: [SKIP][519] ([Intel XE#288]) -> [SKIP][520] ([Intel XE#1130] / [Intel XE#1201]) > [519]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html > [520]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html > > * igt@xe_exec_fault_mode@twice-userptr-rebind-imm: > - shard-dg2-set2: [SKIP][521] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][522] ([Intel XE#288]) +7 other tests skip > [521]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html > [522]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html > > * igt@xe_exec_reset@parallel-gt-reset: > - shard-dg2-set2: [TIMEOUT][523] ([Intel XE#2105]) -> [INCOMPLETE][524] ([Intel XE#1195] / [Intel XE#2105]) > [523]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_exec_reset@parallel-gt-reset.html > [524]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_exec_reset@parallel-gt-reset.html > > * igt@xe_mmap@small-bar: > - shard-dg2-set2: [SKIP][525] ([Intel XE#1201] / [Intel XE#512]) -> [SKIP][526] ([Intel XE#512]) > [525]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@xe_mmap@small-bar.html > [526]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-432/igt@xe_mmap@small-bar.html > > * igt@xe_module_load@many-reload: > - shard-dg2-set2: [DMESG-FAIL][527] -> [FAIL][528] ([Intel XE#2136]) > [527]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_module_load@many-reload.html > [528]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_module_load@many-reload.html > > * igt@xe_module_load@reload: > - shard-dg2-set2: [DMESG-FAIL][529] ([Intel XE#2019]) -> [FAIL][530] ([Intel XE#2136]) > [529]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_module_load@reload.html > [530]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_module_load@reload.html > > * igt@xe_pat@pat-index-xelp: > - shard-lnl: [SKIP][531] ([Intel XE#977]) -> [SKIP][532] ([Intel XE#1130]) > [531]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@xe_pat@pat-index-xelp.html > [532]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@xe_pat@pat-index-xelp.html > > * igt@xe_peer2peer@write: > - shard-dg2-set2: [SKIP][533] ([Intel XE#1061] / [Intel XE#1201]) -> [FAIL][534] ([Intel XE#1173]) > [533]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-434/igt@xe_peer2peer@write.html > [534]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-436/igt@xe_peer2peer@write.html > > * igt@xe_pm@d3cold-basic: > - shard-lnl: [SKIP][535] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][536] ([Intel XE#1130]) +2 other tests skip > [535]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@xe_pm@d3cold-basic.html > [536]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-2/igt@xe_pm@d3cold-basic.html > > * igt@xe_pm@d3cold-basic-exec: > - shard-dg2-set2: [SKIP][537] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][538] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) > [537]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_pm@d3cold-basic-exec.html > [538]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-463/igt@xe_pm@d3cold-basic-exec.html > - shard-lnl: [SKIP][539] ([Intel XE#1130]) -> [SKIP][540] ([Intel XE#2284] / [Intel XE#366]) > [539]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@xe_pm@d3cold-basic-exec.html > [540]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-6/igt@xe_pm@d3cold-basic-exec.html > > * igt@xe_pm@s2idle-d3cold-basic-exec: > - shard-dg2-set2: [SKIP][541] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][542] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) > [541]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_pm@s2idle-d3cold-basic-exec.html > [542]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_pm@s2idle-d3cold-basic-exec.html > > * igt@xe_pm@s3-basic: > - shard-lnl: [SKIP][543] ([Intel XE#1130]) -> [SKIP][544] ([Intel XE#584]) > [543]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-8/igt@xe_pm@s3-basic.html > [544]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-1/igt@xe_pm@s3-basic.html > > * igt@xe_pm@s3-d3cold-basic-exec: > - shard-dg2-set2: [SKIP][545] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) -> [SKIP][546] ([Intel XE#1130] / [Intel XE#1201]) +2 other tests skip > [545]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-436/igt@xe_pm@s3-d3cold-basic-exec.html > [546]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_pm@s3-d3cold-basic-exec.html > > * igt@xe_query@multigpu-query-config: > - shard-dg2-set2: [SKIP][547] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][548] ([Intel XE#1201] / [Intel XE#944]) +1 other test skip > [547]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-435/igt@xe_query@multigpu-query-config.html > [548]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_query@multigpu-query-config.html > > * igt@xe_query@multigpu-query-invalid-size: > - shard-lnl: [SKIP][549] ([Intel XE#1130]) -> [SKIP][550] ([Intel XE#944]) +1 other test skip > [549]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-3/igt@xe_query@multigpu-query-invalid-size.html > [550]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-8/igt@xe_query@multigpu-query-invalid-size.html > > * igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz: > - shard-dg2-set2: [SKIP][551] ([Intel XE#1201] / [Intel XE#944]) -> [SKIP][552] ([Intel XE#1130] / [Intel XE#1201]) > [551]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html > [552]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-433/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html > > * igt@xe_query@multigpu-query-mem-usage: > - shard-dg2-set2: [SKIP][553] ([Intel XE#944]) -> [SKIP][554] ([Intel XE#1201] / [Intel XE#944]) +1 other test skip > [553]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-432/igt@xe_query@multigpu-query-mem-usage.html > [554]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-435/igt@xe_query@multigpu-query-mem-usage.html > > * igt@xe_query@multigpu-query-topology-l3-bank-mask: > - shard-lnl: [SKIP][555] ([Intel XE#944]) -> [SKIP][556] ([Intel XE#1130]) +2 other tests skip > [555]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-5/igt@xe_query@multigpu-query-topology-l3-bank-mask.html > [556]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@xe_query@multigpu-query-topology-l3-bank-mask.html > > * igt@xe_wedged@wedged-at-any-timeout: > - shard-dg2-set2: [DMESG-FAIL][557] ([Intel XE#1760]) -> [SKIP][558] ([Intel XE#1130] / [Intel XE#1201]) > [557]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-dg2-463/igt@xe_wedged@wedged-at-any-timeout.html > [558]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-dg2-434/igt@xe_wedged@wedged-at-any-timeout.html > - shard-lnl: [DMESG-FAIL][559] ([Intel XE#1760]) -> [SKIP][560] ([Intel XE#1130]) > [559]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7942/shard-lnl-1/igt@xe_wedged@wedged-at-any-timeout.html > [560]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/shard-lnl-5/igt@xe_wedged@wedged-at-any-timeout.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [Intel XE#1041]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1041 > [Intel XE#1050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1050 > [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061 > [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091 > [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122 > [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123 > [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124 > [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126 > [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127 > [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128 > [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129 > [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130 > [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135 > [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138 > [Intel XE#1149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1149 > [Intel XE#1162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1162 > [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173 > [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192 > [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195 > [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201 > [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252 > [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280 > [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337 > [Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358 > [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392 > [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397 > [Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399 > [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401 > [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406 > [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407 > [Intel XE#1413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1413 > [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421 > [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424 > [Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426 > [Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428 > [Intel XE#1437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1437 > [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439 > [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447 > [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467 > [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469 > [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470 > [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473 > [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489 > [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499 > [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512 > [Intel XE#1551]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1551 > [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600 > [Intel XE#1620]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1620 > [Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659 > [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745 > [Intel XE#1760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1760 > [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794 > [Intel XE#1924]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1924 > [Intel XE#2019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2019 > [Intel XE#2028]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2028 > [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029 > [Intel XE#2105]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2105 > [Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136 > [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191 > [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229 > [Intel XE#2262]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2262 > [Intel XE#2280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2280 > [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284 > [Intel XE#2318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2318 > [Intel XE#2340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2340 > [Intel XE#2343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2343 > [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351 > [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360 > [Intel XE#2366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2366 > [Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255 > [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288 > [Intel XE#294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/294 > [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306 > [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307 > [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308 > [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309 > [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316 > [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323 > [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324 > [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327 > [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346 > [Intel XE#361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/361 > [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366 > [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367 > [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373 > [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378 > [Intel XE#392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/392 > [Intel XE#402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/402 > [Intel XE#417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/417 > [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455 > [Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498 > [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512 > [Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569 > [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584 > [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599 > [Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605 > [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610 > [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619 > [Intel XE#623]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/623 > [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651 > [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653 > [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656 > [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658 > [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688 > [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701 > [Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702 > [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703 > [Intel XE#736]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/736 > [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756 > [Intel XE#771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/771 > [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776 > [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787 > [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870 > [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886 > [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899 > [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908 > [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929 > [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944 > [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977 > [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979 > [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575 > [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804 > > > Build changes > ------------- > > * IGT: IGT_7942 -> IGTPW_11488 > * Linux: xe-1684-3a93d4a1f4872fbdfe43e9b7f1a7dfd9236a642d -> xe-1686-b6f9528c7fffc2f65c8e4969d35d9346fd503c9b > > IGTPW_11488: 11488 > IGT_7942: 0f02dc176959e6296866b1bafd3982e277a5e44b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > xe-1684-3a93d4a1f4872fbdfe43e9b7f1a7dfd9236a642d: 3a93d4a1f4872fbdfe43e9b7f1a7dfd9236a642d > xe-1686-b6f9528c7fffc2f65c8e4969d35d9346fd503c9b: b6f9528c7fffc2f65c8e4969d35d9346fd503c9b > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11488/index.html -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH i-g-t 1/2] lib: Add u32 variants of igt_assert_{lt,lte} 2024-07-29 22:02 [PATCH i-g-t 1/2] lib: Add u32 variants of igt_assert_{lt,lte} Matt Roper ` (3 preceding siblings ...) 2024-07-30 2:16 ` ✗ CI.xeFULL: " Patchwork @ 2024-07-31 15:57 ` Kamil Konieczny 4 siblings, 0 replies; 12+ messages in thread From: Kamil Konieczny @ 2024-07-31 15:57 UTC (permalink / raw) To: igt-dev; +Cc: Matt Roper Hi Matt, On 2024-07-29 at 15:02:50 -0700, Matt Roper wrote: > igt.cocci assumes that u32 variants of the comparison assertions exist, > so add the two that were missing. > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com> > --- > lib/igt_core.h | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/lib/igt_core.h b/lib/igt_core.h > index 084d94da7..82f474c5f 100644 > --- a/lib/igt_core.h > +++ b/lib/igt_core.h > @@ -915,6 +915,15 @@ void igt_describe_f(const char *fmt, ...); > */ > #define igt_assert_lte(n1, n2) igt_assert_cmpint(n1, <=, >, n2) > > +/** > + * igt_assert_lte_u32: > + * @n1: first integer > + * @n2: second integer > + * > + * Like igt_assert_lte(), but for uint32_t. > + */ > +#define igt_assert_lte_u32(n1, n2) igt_assert_cmpuint(n1, <=, >, n2) > + > /** > * igt_assert_lte_u64: > * @n1: first integer > @@ -954,6 +963,15 @@ void igt_describe_f(const char *fmt, ...); > */ > #define igt_assert_lt(n1, n2) igt_assert_cmpint(n1, <, >=, n2) > > +/** > + * igt_assert_lt_u32: > + * @n1: first integer > + * @n2: second integer > + * > + * Like igt_assert_lt(), but for uint32_t. > + */ > +#define igt_assert_lt_u32(n1, n2) igt_assert_cmpuint(n1, <, >=, n2) > + > /** > * igt_assert_lt_u64: > * @n1: first integer > -- > 2.45.2 > ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2024-08-01 21:46 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
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2024-07-29 22:02 [PATCH i-g-t 1/2] lib: Add u32 variants of igt_assert_{lt,lte} Matt Roper
2024-07-29 22:02 ` [PATCH i-g-t 2/2] tests/intel: Apply igt.cocci transforms Matt Roper
2024-07-31 12:25 ` [i-g-t,2/2] " Vivekanandan, Balasubramani
2024-07-31 16:26 ` Matt Roper
2024-08-01 10:19 ` Vivekanandan, Balasubramani
2024-08-01 21:46 ` [PATCH i-g-t 2/2] " Dixit, Ashutosh
2024-07-29 22:43 ` ✓ CI.xeBAT: success for series starting with [i-g-t,1/2] lib: Add u32 variants of igt_assert_{lt,lte} Patchwork
2024-07-29 23:13 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-07-29 23:24 ` Matt Roper
2024-07-30 2:16 ` ✗ CI.xeFULL: " Patchwork
2024-07-30 15:44 ` Matt Roper
2024-07-31 15:57 ` [PATCH i-g-t 1/2] " Kamil Konieczny
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