[PATCH i-g-t 0/2] tests/intel/xe_drm_fdinfo: Virtual and parallel

[PATCH i-g-t 0/2] tests/intel/xe_drm_fdinfo: Virtual and parallel

[Lucas De Marchi]

Add virtual and parallel test coverage to xe_drm_fdinfo.

Lucas De Marchi (2):
  tests/intel/xe_drm_fdinfo: Wire up parallel/virtual submission
  tests/intel/xe_drm_fdinfo: Implement virtual/parallel exec queues

 tests/intel/xe_drm_fdinfo.c | 185 +++++++++++++++++++++++++++++++-----
 1 file changed, 163 insertions(+), 22 deletions(-)

-- 
2.43.0

[PATCH i-g-t 1/2] tests/intel/xe_drm_fdinfo: Wire up parallel/virtual submission

[Lucas De Marchi]

Add the boiler plate code for parallel and virtual submission in the
spin_ctx_* and check_results(). This is based on previous code by Umesh
that got simplified before applying.

Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 61 ++++++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 21 deletions(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index d1ed0fcaa..8acb95040 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -365,7 +365,7 @@ static void basic_engine_utilization(int xe)
 
 struct spin_ctx {
 	uint32_t vm;
-	uint64_t addr;
+	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
 	struct drm_xe_sync sync[2];
 	struct drm_xe_exec exec;
 	uint32_t exec_queue;
@@ -375,18 +375,29 @@ struct spin_ctx {
 	struct xe_spin_opts spin_opts;
 	bool ended;
 	uint16_t class;
+	uint16_t width;
+	uint16_t num_placements;
 };
 
 static struct spin_ctx *
-spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm)
+spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
+	      uint16_t width, uint16_t num_placements)
 {
 	struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
 
+	igt_assert(width && num_placements &&
+		   (width == 1 || num_placements == 1));
+	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
+
 	ctx->class = hwe->engine_class;
+	ctx->width = width;
+	ctx->num_placements = num_placements;
 	ctx->vm = vm;
-	ctx->addr = 0x100000 + 0x100000 * hwe->engine_class;
 
-	ctx->exec.num_batch_buffer = 1;
+	for (unsigned int i = 0; i < width; i++)
+		ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
+
+	ctx->exec.num_batch_buffer = width;
 	ctx->exec.num_syncs = 2;
 	ctx->exec.syncs = to_user_pointer(ctx->sync);
 
@@ -405,10 +416,10 @@ spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm)
 			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
 	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
 
-	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, 1, 1,
+	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
 					     hwe, 0, &ctx->exec_queue), 0);
 
-	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr, ctx->bo_size,
+	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
 			 ctx->sync, 1);
 
 	return ctx;
@@ -420,7 +431,7 @@ spin_sync_start(int fd, struct spin_ctx *ctx)
 	if (!ctx)
 		return;
 
-	ctx->spin_opts.addr = ctx->addr;
+	ctx->spin_opts.addr = ctx->addr[0];
 	ctx->spin_opts.write_timestamp = true;
 	ctx->spin_opts.preempt = true;
 	xe_spin_init(ctx->spin, &ctx->spin_opts);
@@ -429,7 +440,12 @@ spin_sync_start(int fd, struct spin_ctx *ctx)
 	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
 
 	ctx->exec.exec_queue_id = ctx->exec_queue;
-	ctx->exec.address = ctx->addr;
+
+	if (ctx->width > 1)
+		ctx->exec.address = to_user_pointer(ctx->addr);
+	else
+		ctx->exec.address = ctx->addr[0];
+
 	xe_exec(fd, &ctx->exec);
 
 	xe_spin_wait_started(ctx->spin);
@@ -450,7 +466,7 @@ spin_sync_end(int fd, struct spin_ctx *ctx)
 	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
 
 	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
-	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr, ctx->bo_size, ctx->sync, 1);
+	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
 	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
 
 	ctx->ended = true;
@@ -476,7 +492,7 @@ spin_ctx_destroy(int fd, struct spin_ctx *ctx)
 
 static void
 check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
-	      int class, enum expected_load expected_load)
+	      int class, int width, enum expected_load expected_load)
 {
 	double percent;
 	u64 den, num;
@@ -490,6 +506,9 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
 	den = s2[class].total_cycles - s1[class].total_cycles;
 	percent = (num * 100.0) / (den + 1);
 
+	/* for parallel submission scale the busyness with width */
+	percent /= width;
+
 	igt_debug("%s: percent: %f\n", engine_map[class], percent);
 
 	switch (expected_load) {
@@ -522,7 +541,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 
 	vm = xe_vm_create(fd, 0, 0);
 	if (flags & TEST_BUSY) {
-		ctx = spin_ctx_init(fd, hwe, vm);
+		ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
 		spin_sync_start(fd, ctx);
 	}
 
@@ -540,14 +559,14 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 
 	expected_load = flags & TEST_BUSY ?
 	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
-	check_results(pceu1[0], pceu2[0], hwe->engine_class, expected_load);
+	check_results(pceu1[0], pceu2[0], hwe->engine_class, 1, expected_load);
 
 	if (flags & TEST_ISOLATION) {
 		/*
 		 * Load from one client shouldn't spill on another,
 		 * so check for idle
 		 */
-		check_results(pceu1[1], pceu2[1], hwe->engine_class, EXPECTED_LOAD_IDLE);
+		check_results(pceu1[1], pceu2[1], hwe->engine_class, 1, EXPECTED_LOAD_IDLE);
 		close(new_fd);
 	}
 
@@ -565,7 +584,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
 	uint32_t vm;
 
 	vm = xe_vm_create(fd, 0, 0);
-	ctx = spin_ctx_init(fd, hwe, vm);
+	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
 	spin_sync_start(fd, ctx);
 
 	read_engine_cycles(fd, pceu1);
@@ -579,7 +598,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
 
 	xe_vm_destroy(fd, vm);
 
-	check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
+	check_results(pceu1, pceu2, hwe->engine_class, 1, EXPECTED_LOAD_FULL);
 }
 
 static void
@@ -593,7 +612,7 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
 
 	vm = xe_vm_create(fd, 0, 0);
 
-	ctx = spin_ctx_init(fd, hwe, vm);
+	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
 	spin_sync_start(fd, ctx);
 
 	read_engine_cycles(fd, pceu1);
@@ -605,7 +624,7 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
 		enum expected_load expected_load = hwe->engine_class != class ?
 			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
 
-		check_results(pceu1, pceu2, class, expected_load);
+		check_results(pceu1, pceu2, class, 1, expected_load);
 	}
 
 	spin_sync_end(fd, ctx);
@@ -632,7 +651,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 		if (_class == hwe->engine_class || ctx[_class])
 			continue;
 
-		ctx[_class] = spin_ctx_init(fd, _hwe, vm);
+		ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
 		spin_sync_start(fd, ctx[_class]);
 	}
 
@@ -649,7 +668,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 		if (!ctx[class])
 			continue;
 
-		check_results(pceu1, pceu2, class, expected_load);
+		check_results(pceu1, pceu2, class, 1, expected_load);
 		spin_sync_end(fd, ctx[class]);
 		spin_ctx_destroy(fd, ctx[class]);
 	}
@@ -675,7 +694,7 @@ utilization_all_full_load(int fd)
 		if (ctx[class])
 			continue;
 
-		ctx[class] = spin_ctx_init(fd, hwe, vm);
+		ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
 		spin_sync_start(fd, ctx[class]);
 	}
 
@@ -689,7 +708,7 @@ utilization_all_full_load(int fd)
 		if (!ctx[class])
 			continue;
 
-		check_results(pceu1, pceu2, class, EXPECTED_LOAD_FULL);
+		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
 		spin_sync_end(fd, ctx[class]);
 		spin_ctx_destroy(fd, ctx[class]);
 	}
-- 
2.43.0

Re: [PATCH i-g-t 1/2] tests/intel/xe_drm_fdinfo: Wire up parallel/virtual submission

[Matthew Brost]

On Wed, Sep 04, 2024 at 03:57:45PM -0700, Lucas De Marchi wrote:
> Add the boiler plate code for parallel and virtual submission in the
> spin_ctx_* and check_results(). This is based on previous code by Umesh
> that got simplified before applying.
> 
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  tests/intel/xe_drm_fdinfo.c | 61 ++++++++++++++++++++++++-------------
>  1 file changed, 40 insertions(+), 21 deletions(-)
> 
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index d1ed0fcaa..8acb95040 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -365,7 +365,7 @@ static void basic_engine_utilization(int xe)
>  
>  struct spin_ctx {
>  	uint32_t vm;
> -	uint64_t addr;
> +	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
>  	struct drm_xe_sync sync[2];
>  	struct drm_xe_exec exec;
>  	uint32_t exec_queue;
> @@ -375,18 +375,29 @@ struct spin_ctx {
>  	struct xe_spin_opts spin_opts;
>  	bool ended;
>  	uint16_t class;
> +	uint16_t width;
> +	uint16_t num_placements;
>  };
>  
>  static struct spin_ctx *
> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm)
> +spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> +	      uint16_t width, uint16_t num_placements)
>  {
>  	struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
>  
> +	igt_assert(width && num_placements &&
> +		   (width == 1 || num_placements == 1));
> +	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> +
>  	ctx->class = hwe->engine_class;
> +	ctx->width = width;
> +	ctx->num_placements = num_placements;
>  	ctx->vm = vm;
> -	ctx->addr = 0x100000 + 0x100000 * hwe->engine_class;
>  
> -	ctx->exec.num_batch_buffer = 1;
> +	for (unsigned int i = 0; i < width; i++)
> +		ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> +
> +	ctx->exec.num_batch_buffer = width;
>  	ctx->exec.num_syncs = 2;
>  	ctx->exec.syncs = to_user_pointer(ctx->sync);
>  
> @@ -405,10 +416,10 @@ spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm)
>  			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>  	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
>  
> -	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, 1, 1,
> +	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
>  					     hwe, 0, &ctx->exec_queue), 0);
>  
> -	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr, ctx->bo_size,
> +	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
>  			 ctx->sync, 1);
>  
>  	return ctx;
> @@ -420,7 +431,7 @@ spin_sync_start(int fd, struct spin_ctx *ctx)
>  	if (!ctx)
>  		return;
>  
> -	ctx->spin_opts.addr = ctx->addr;
> +	ctx->spin_opts.addr = ctx->addr[0];
>  	ctx->spin_opts.write_timestamp = true;
>  	ctx->spin_opts.preempt = true;
>  	xe_spin_init(ctx->spin, &ctx->spin_opts);
> @@ -429,7 +440,12 @@ spin_sync_start(int fd, struct spin_ctx *ctx)
>  	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>  
>  	ctx->exec.exec_queue_id = ctx->exec_queue;
> -	ctx->exec.address = ctx->addr;
> +
> +	if (ctx->width > 1)
> +		ctx->exec.address = to_user_pointer(ctx->addr);
> +	else
> +		ctx->exec.address = ctx->addr[0];
> +
>  	xe_exec(fd, &ctx->exec);
>  
>  	xe_spin_wait_started(ctx->spin);
> @@ -450,7 +466,7 @@ spin_sync_end(int fd, struct spin_ctx *ctx)
>  	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>  
>  	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> -	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr, ctx->bo_size, ctx->sync, 1);
> +	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
>  	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>  
>  	ctx->ended = true;
> @@ -476,7 +492,7 @@ spin_ctx_destroy(int fd, struct spin_ctx *ctx)
>  
>  static void
>  check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> -	      int class, enum expected_load expected_load)
> +	      int class, int width, enum expected_load expected_load)
>  {
>  	double percent;
>  	u64 den, num;
> @@ -490,6 +506,9 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>  	den = s2[class].total_cycles - s1[class].total_cycles;
>  	percent = (num * 100.0) / (den + 1);
>  
> +	/* for parallel submission scale the busyness with width */
> +	percent /= width;

This doesn't look right. Wouldn't a width submission be busier?

Maybe I'm confusing myself but everything else LGTM.

Matt

> +
>  	igt_debug("%s: percent: %f\n", engine_map[class], percent);
>  
>  	switch (expected_load) {
> @@ -522,7 +541,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  
>  	vm = xe_vm_create(fd, 0, 0);
>  	if (flags & TEST_BUSY) {
> -		ctx = spin_ctx_init(fd, hwe, vm);
> +		ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>  		spin_sync_start(fd, ctx);
>  	}
>  
> @@ -540,14 +559,14 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  
>  	expected_load = flags & TEST_BUSY ?
>  	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
> -	check_results(pceu1[0], pceu2[0], hwe->engine_class, expected_load);
> +	check_results(pceu1[0], pceu2[0], hwe->engine_class, 1, expected_load);
>  
>  	if (flags & TEST_ISOLATION) {
>  		/*
>  		 * Load from one client shouldn't spill on another,
>  		 * so check for idle
>  		 */
> -		check_results(pceu1[1], pceu2[1], hwe->engine_class, EXPECTED_LOAD_IDLE);
> +		check_results(pceu1[1], pceu2[1], hwe->engine_class, 1, EXPECTED_LOAD_IDLE);
>  		close(new_fd);
>  	}
>  
> @@ -565,7 +584,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>  	uint32_t vm;
>  
>  	vm = xe_vm_create(fd, 0, 0);
> -	ctx = spin_ctx_init(fd, hwe, vm);
> +	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>  	spin_sync_start(fd, ctx);
>  
>  	read_engine_cycles(fd, pceu1);
> @@ -579,7 +598,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>  
>  	xe_vm_destroy(fd, vm);
>  
> -	check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
> +	check_results(pceu1, pceu2, hwe->engine_class, 1, EXPECTED_LOAD_FULL);
>  }
>  
>  static void
> @@ -593,7 +612,7 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>  
>  	vm = xe_vm_create(fd, 0, 0);
>  
> -	ctx = spin_ctx_init(fd, hwe, vm);
> +	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>  	spin_sync_start(fd, ctx);
>  
>  	read_engine_cycles(fd, pceu1);
> @@ -605,7 +624,7 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>  		enum expected_load expected_load = hwe->engine_class != class ?
>  			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
>  
> -		check_results(pceu1, pceu2, class, expected_load);
> +		check_results(pceu1, pceu2, class, 1, expected_load);
>  	}
>  
>  	spin_sync_end(fd, ctx);
> @@ -632,7 +651,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>  		if (_class == hwe->engine_class || ctx[_class])
>  			continue;
>  
> -		ctx[_class] = spin_ctx_init(fd, _hwe, vm);
> +		ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
>  		spin_sync_start(fd, ctx[_class]);
>  	}
>  
> @@ -649,7 +668,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>  		if (!ctx[class])
>  			continue;
>  
> -		check_results(pceu1, pceu2, class, expected_load);
> +		check_results(pceu1, pceu2, class, 1, expected_load);
>  		spin_sync_end(fd, ctx[class]);
>  		spin_ctx_destroy(fd, ctx[class]);
>  	}
> @@ -675,7 +694,7 @@ utilization_all_full_load(int fd)
>  		if (ctx[class])
>  			continue;
>  
> -		ctx[class] = spin_ctx_init(fd, hwe, vm);
> +		ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
>  		spin_sync_start(fd, ctx[class]);
>  	}
>  
> @@ -689,7 +708,7 @@ utilization_all_full_load(int fd)
>  		if (!ctx[class])
>  			continue;
>  
> -		check_results(pceu1, pceu2, class, EXPECTED_LOAD_FULL);
> +		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
>  		spin_sync_end(fd, ctx[class]);
>  		spin_ctx_destroy(fd, ctx[class]);
>  	}
> -- 
> 2.43.0
> 

Re: [PATCH i-g-t 1/2] tests/intel/xe_drm_fdinfo: Wire up parallel/virtual submission

[Lucas De Marchi]

On Fri, Sep 06, 2024 at 05:56:59PM GMT, Matthew Brost wrote:
>On Wed, Sep 04, 2024 at 03:57:45PM -0700, Lucas De Marchi wrote:
>> Add the boiler plate code for parallel and virtual submission in the
>> spin_ctx_* and check_results(). This is based on previous code by Umesh
>> that got simplified before applying.
>>
>> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  tests/intel/xe_drm_fdinfo.c | 61 ++++++++++++++++++++++++-------------
>>  1 file changed, 40 insertions(+), 21 deletions(-)
>>
>> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
>> index d1ed0fcaa..8acb95040 100644
>> --- a/tests/intel/xe_drm_fdinfo.c
>> +++ b/tests/intel/xe_drm_fdinfo.c
>> @@ -365,7 +365,7 @@ static void basic_engine_utilization(int xe)
>>
>>  struct spin_ctx {
>>  	uint32_t vm;
>> -	uint64_t addr;
>> +	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
>>  	struct drm_xe_sync sync[2];
>>  	struct drm_xe_exec exec;
>>  	uint32_t exec_queue;
>> @@ -375,18 +375,29 @@ struct spin_ctx {
>>  	struct xe_spin_opts spin_opts;
>>  	bool ended;
>>  	uint16_t class;
>> +	uint16_t width;
>> +	uint16_t num_placements;
>>  };
>>
>>  static struct spin_ctx *
>> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm)
>> +spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
>> +	      uint16_t width, uint16_t num_placements)
>>  {
>>  	struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
>>
>> +	igt_assert(width && num_placements &&
>> +		   (width == 1 || num_placements == 1));
>> +	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
>> +
>>  	ctx->class = hwe->engine_class;
>> +	ctx->width = width;
>> +	ctx->num_placements = num_placements;
>>  	ctx->vm = vm;
>> -	ctx->addr = 0x100000 + 0x100000 * hwe->engine_class;
>>
>> -	ctx->exec.num_batch_buffer = 1;
>> +	for (unsigned int i = 0; i < width; i++)
>> +		ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
>> +
>> +	ctx->exec.num_batch_buffer = width;
>>  	ctx->exec.num_syncs = 2;
>>  	ctx->exec.syncs = to_user_pointer(ctx->sync);
>>
>> @@ -405,10 +416,10 @@ spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm)
>>  			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>>  	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
>>
>> -	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, 1, 1,
>> +	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
>>  					     hwe, 0, &ctx->exec_queue), 0);
>>
>> -	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr, ctx->bo_size,
>> +	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
>>  			 ctx->sync, 1);
>>
>>  	return ctx;
>> @@ -420,7 +431,7 @@ spin_sync_start(int fd, struct spin_ctx *ctx)
>>  	if (!ctx)
>>  		return;
>>
>> -	ctx->spin_opts.addr = ctx->addr;
>> +	ctx->spin_opts.addr = ctx->addr[0];
>>  	ctx->spin_opts.write_timestamp = true;
>>  	ctx->spin_opts.preempt = true;
>>  	xe_spin_init(ctx->spin, &ctx->spin_opts);
>> @@ -429,7 +440,12 @@ spin_sync_start(int fd, struct spin_ctx *ctx)
>>  	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>>
>>  	ctx->exec.exec_queue_id = ctx->exec_queue;
>> -	ctx->exec.address = ctx->addr;
>> +
>> +	if (ctx->width > 1)
>> +		ctx->exec.address = to_user_pointer(ctx->addr);
>> +	else
>> +		ctx->exec.address = ctx->addr[0];
>> +
>>  	xe_exec(fd, &ctx->exec);
>>
>>  	xe_spin_wait_started(ctx->spin);
>> @@ -450,7 +466,7 @@ spin_sync_end(int fd, struct spin_ctx *ctx)
>>  	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>>
>>  	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>> -	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr, ctx->bo_size, ctx->sync, 1);
>> +	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
>>  	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>>
>>  	ctx->ended = true;
>> @@ -476,7 +492,7 @@ spin_ctx_destroy(int fd, struct spin_ctx *ctx)
>>
>>  static void
>>  check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>> -	      int class, enum expected_load expected_load)
>> +	      int class, int width, enum expected_load expected_load)
>>  {
>>  	double percent;
>>  	u64 den, num;
>> @@ -490,6 +506,9 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>>  	den = s2[class].total_cycles - s1[class].total_cycles;
>>  	percent = (num * 100.0) / (den + 1);
>>
>> +	/* for parallel submission scale the busyness with width */
>> +	percent /= width;
>
>This doesn't look right. Wouldn't a width submission be busier?
>
>Maybe I'm confusing myself but everything else LGTM.

the thing is... the fdinfo reports the number of engines of each class
(drm-engine-capacity-<engine>) and expects the reader to scale the
total_cycles according to that number.  We are lazy here and instead of
using that number we use width that was passed as input.

Example, with "*" denoting when cycle is ticking.

		s1		    s2
ccs0		[**********..........] == 10
ccs1		[**********..........] == 10
total_cycles	[********************] == 20

cycles[ccs] == 20
total_cycles == 20
width == 2

Calculating according to check_results():

num = 20
den = 20
percent = (20 * 100) / 20
percent /= width == 50%

which corresponds to the reality that this client occupied CCS
for 50% of the available time.

Lucas De Marchi

>
>Matt
>
>> +
>>  	igt_debug("%s: percent: %f\n", engine_map[class], percent);
>>
>>  	switch (expected_load) {
>> @@ -522,7 +541,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>>
>>  	vm = xe_vm_create(fd, 0, 0);
>>  	if (flags & TEST_BUSY) {
>> -		ctx = spin_ctx_init(fd, hwe, vm);
>> +		ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>>  		spin_sync_start(fd, ctx);
>>  	}
>>
>> @@ -540,14 +559,14 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>>
>>  	expected_load = flags & TEST_BUSY ?
>>  	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
>> -	check_results(pceu1[0], pceu2[0], hwe->engine_class, expected_load);
>> +	check_results(pceu1[0], pceu2[0], hwe->engine_class, 1, expected_load);
>>
>>  	if (flags & TEST_ISOLATION) {
>>  		/*
>>  		 * Load from one client shouldn't spill on another,
>>  		 * so check for idle
>>  		 */
>> -		check_results(pceu1[1], pceu2[1], hwe->engine_class, EXPECTED_LOAD_IDLE);
>> +		check_results(pceu1[1], pceu2[1], hwe->engine_class, 1, EXPECTED_LOAD_IDLE);
>>  		close(new_fd);
>>  	}
>>
>> @@ -565,7 +584,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>>  	uint32_t vm;
>>
>>  	vm = xe_vm_create(fd, 0, 0);
>> -	ctx = spin_ctx_init(fd, hwe, vm);
>> +	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>>  	spin_sync_start(fd, ctx);
>>
>>  	read_engine_cycles(fd, pceu1);
>> @@ -579,7 +598,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>>
>>  	xe_vm_destroy(fd, vm);
>>
>> -	check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
>> +	check_results(pceu1, pceu2, hwe->engine_class, 1, EXPECTED_LOAD_FULL);
>>  }
>>
>>  static void
>> @@ -593,7 +612,7 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>>
>>  	vm = xe_vm_create(fd, 0, 0);
>>
>> -	ctx = spin_ctx_init(fd, hwe, vm);
>> +	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>>  	spin_sync_start(fd, ctx);
>>
>>  	read_engine_cycles(fd, pceu1);
>> @@ -605,7 +624,7 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>>  		enum expected_load expected_load = hwe->engine_class != class ?
>>  			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
>>
>> -		check_results(pceu1, pceu2, class, expected_load);
>> +		check_results(pceu1, pceu2, class, 1, expected_load);
>>  	}
>>
>>  	spin_sync_end(fd, ctx);
>> @@ -632,7 +651,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>>  		if (_class == hwe->engine_class || ctx[_class])
>>  			continue;
>>
>> -		ctx[_class] = spin_ctx_init(fd, _hwe, vm);
>> +		ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
>>  		spin_sync_start(fd, ctx[_class]);
>>  	}
>>
>> @@ -649,7 +668,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>>  		if (!ctx[class])
>>  			continue;
>>
>> -		check_results(pceu1, pceu2, class, expected_load);
>> +		check_results(pceu1, pceu2, class, 1, expected_load);
>>  		spin_sync_end(fd, ctx[class]);
>>  		spin_ctx_destroy(fd, ctx[class]);
>>  	}
>> @@ -675,7 +694,7 @@ utilization_all_full_load(int fd)
>>  		if (ctx[class])
>>  			continue;
>>
>> -		ctx[class] = spin_ctx_init(fd, hwe, vm);
>> +		ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
>>  		spin_sync_start(fd, ctx[class]);
>>  	}
>>
>> @@ -689,7 +708,7 @@ utilization_all_full_load(int fd)
>>  		if (!ctx[class])
>>  			continue;
>>
>> -		check_results(pceu1, pceu2, class, EXPECTED_LOAD_FULL);
>> +		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
>>  		spin_sync_end(fd, ctx[class]);
>>  		spin_ctx_destroy(fd, ctx[class]);
>>  	}
>> --
>> 2.43.0
>>

Re: [PATCH i-g-t 1/2] tests/intel/xe_drm_fdinfo: Wire up parallel/virtual submission

[Matthew Brost]

On Fri, Sep 06, 2024 at 01:54:36PM -0500, Lucas De Marchi wrote:
> On Fri, Sep 06, 2024 at 05:56:59PM GMT, Matthew Brost wrote:
> > On Wed, Sep 04, 2024 at 03:57:45PM -0700, Lucas De Marchi wrote:
> > > Add the boiler plate code for parallel and virtual submission in the
> > > spin_ctx_* and check_results(). This is based on previous code by Umesh
> > > that got simplified before applying.
> > > 
> > > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  tests/intel/xe_drm_fdinfo.c | 61 ++++++++++++++++++++++++-------------
> > >  1 file changed, 40 insertions(+), 21 deletions(-)
> > > 
> > > diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> > > index d1ed0fcaa..8acb95040 100644
> > > --- a/tests/intel/xe_drm_fdinfo.c
> > > +++ b/tests/intel/xe_drm_fdinfo.c
> > > @@ -365,7 +365,7 @@ static void basic_engine_utilization(int xe)
> > > 
> > >  struct spin_ctx {
> > >  	uint32_t vm;
> > > -	uint64_t addr;
> > > +	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> > >  	struct drm_xe_sync sync[2];
> > >  	struct drm_xe_exec exec;
> > >  	uint32_t exec_queue;
> > > @@ -375,18 +375,29 @@ struct spin_ctx {
> > >  	struct xe_spin_opts spin_opts;
> > >  	bool ended;
> > >  	uint16_t class;
> > > +	uint16_t width;
> > > +	uint16_t num_placements;
> > >  };
> > > 
> > >  static struct spin_ctx *
> > > -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm)
> > > +spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> > > +	      uint16_t width, uint16_t num_placements)
> > >  {
> > >  	struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
> > > 
> > > +	igt_assert(width && num_placements &&
> > > +		   (width == 1 || num_placements == 1));
> > > +	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> > > +
> > >  	ctx->class = hwe->engine_class;
> > > +	ctx->width = width;
> > > +	ctx->num_placements = num_placements;
> > >  	ctx->vm = vm;
> > > -	ctx->addr = 0x100000 + 0x100000 * hwe->engine_class;
> > > 
> > > -	ctx->exec.num_batch_buffer = 1;
> > > +	for (unsigned int i = 0; i < width; i++)
> > > +		ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> > > +
> > > +	ctx->exec.num_batch_buffer = width;
> > >  	ctx->exec.num_syncs = 2;
> > >  	ctx->exec.syncs = to_user_pointer(ctx->sync);
> > > 
> > > @@ -405,10 +416,10 @@ spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm)
> > >  			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> > >  	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> > > 
> > > -	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, 1, 1,
> > > +	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> > >  					     hwe, 0, &ctx->exec_queue), 0);
> > > 
> > > -	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr, ctx->bo_size,
> > > +	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> > >  			 ctx->sync, 1);
> > > 
> > >  	return ctx;
> > > @@ -420,7 +431,7 @@ spin_sync_start(int fd, struct spin_ctx *ctx)
> > >  	if (!ctx)
> > >  		return;
> > > 
> > > -	ctx->spin_opts.addr = ctx->addr;
> > > +	ctx->spin_opts.addr = ctx->addr[0];
> > >  	ctx->spin_opts.write_timestamp = true;
> > >  	ctx->spin_opts.preempt = true;
> > >  	xe_spin_init(ctx->spin, &ctx->spin_opts);
> > > @@ -429,7 +440,12 @@ spin_sync_start(int fd, struct spin_ctx *ctx)
> > >  	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> > > 
> > >  	ctx->exec.exec_queue_id = ctx->exec_queue;
> > > -	ctx->exec.address = ctx->addr;
> > > +
> > > +	if (ctx->width > 1)
> > > +		ctx->exec.address = to_user_pointer(ctx->addr);
> > > +	else
> > > +		ctx->exec.address = ctx->addr[0];
> > > +
> > >  	xe_exec(fd, &ctx->exec);
> > > 
> > >  	xe_spin_wait_started(ctx->spin);
> > > @@ -450,7 +466,7 @@ spin_sync_end(int fd, struct spin_ctx *ctx)
> > >  	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> > > 
> > >  	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> > > -	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr, ctx->bo_size, ctx->sync, 1);
> > > +	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> > >  	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> > > 
> > >  	ctx->ended = true;
> > > @@ -476,7 +492,7 @@ spin_ctx_destroy(int fd, struct spin_ctx *ctx)
> > > 
> > >  static void
> > >  check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> > > -	      int class, enum expected_load expected_load)
> > > +	      int class, int width, enum expected_load expected_load)
> > >  {
> > >  	double percent;
> > >  	u64 den, num;
> > > @@ -490,6 +506,9 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> > >  	den = s2[class].total_cycles - s1[class].total_cycles;
> > >  	percent = (num * 100.0) / (den + 1);
> > > 
> > > +	/* for parallel submission scale the busyness with width */
> > > +	percent /= width;
> > 
> > This doesn't look right. Wouldn't a width submission be busier?
> > 
> > Maybe I'm confusing myself but everything else LGTM.
> 
> the thing is... the fdinfo reports the number of engines of each class
> (drm-engine-capacity-<engine>) and expects the reader to scale the
> total_cycles according to that number.  We are lazy here and instead of
> using that number we use width that was passed as input.
> 
> Example, with "*" denoting when cycle is ticking.
> 
> 		s1		    s2
> ccs0		[**********..........] == 10
> ccs1		[**********..........] == 10
> total_cycles	[********************] == 20
> 
> cycles[ccs] == 20
> total_cycles == 20
> width == 2
> 
> Calculating according to check_results():
> 
> num = 20
> den = 20
> percent = (20 * 100) / 20
> percent /= width == 50%
> 
> which corresponds to the reality that this client occupied CCS
> for 50% of the available time.

I kinda reasoned this after sending my reply. Thanks for confirming.

With that:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> 
> Lucas De Marchi
> 
> > 
> > Matt
> > 
> > > +
> > >  	igt_debug("%s: percent: %f\n", engine_map[class], percent);
> > > 
> > >  	switch (expected_load) {
> > > @@ -522,7 +541,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
> > > 
> > >  	vm = xe_vm_create(fd, 0, 0);
> > >  	if (flags & TEST_BUSY) {
> > > -		ctx = spin_ctx_init(fd, hwe, vm);
> > > +		ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> > >  		spin_sync_start(fd, ctx);
> > >  	}
> > > 
> > > @@ -540,14 +559,14 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
> > > 
> > >  	expected_load = flags & TEST_BUSY ?
> > >  	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
> > > -	check_results(pceu1[0], pceu2[0], hwe->engine_class, expected_load);
> > > +	check_results(pceu1[0], pceu2[0], hwe->engine_class, 1, expected_load);
> > > 
> > >  	if (flags & TEST_ISOLATION) {
> > >  		/*
> > >  		 * Load from one client shouldn't spill on another,
> > >  		 * so check for idle
> > >  		 */
> > > -		check_results(pceu1[1], pceu2[1], hwe->engine_class, EXPECTED_LOAD_IDLE);
> > > +		check_results(pceu1[1], pceu2[1], hwe->engine_class, 1, EXPECTED_LOAD_IDLE);
> > >  		close(new_fd);
> > >  	}
> > > 
> > > @@ -565,7 +584,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
> > >  	uint32_t vm;
> > > 
> > >  	vm = xe_vm_create(fd, 0, 0);
> > > -	ctx = spin_ctx_init(fd, hwe, vm);
> > > +	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> > >  	spin_sync_start(fd, ctx);
> > > 
> > >  	read_engine_cycles(fd, pceu1);
> > > @@ -579,7 +598,7 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
> > > 
> > >  	xe_vm_destroy(fd, vm);
> > > 
> > > -	check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL);
> > > +	check_results(pceu1, pceu2, hwe->engine_class, 1, EXPECTED_LOAD_FULL);
> > >  }
> > > 
> > >  static void
> > > @@ -593,7 +612,7 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
> > > 
> > >  	vm = xe_vm_create(fd, 0, 0);
> > > 
> > > -	ctx = spin_ctx_init(fd, hwe, vm);
> > > +	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> > >  	spin_sync_start(fd, ctx);
> > > 
> > >  	read_engine_cycles(fd, pceu1);
> > > @@ -605,7 +624,7 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
> > >  		enum expected_load expected_load = hwe->engine_class != class ?
> > >  			EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL;
> > > 
> > > -		check_results(pceu1, pceu2, class, expected_load);
> > > +		check_results(pceu1, pceu2, class, 1, expected_load);
> > >  	}
> > > 
> > >  	spin_sync_end(fd, ctx);
> > > @@ -632,7 +651,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> > >  		if (_class == hwe->engine_class || ctx[_class])
> > >  			continue;
> > > 
> > > -		ctx[_class] = spin_ctx_init(fd, _hwe, vm);
> > > +		ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
> > >  		spin_sync_start(fd, ctx[_class]);
> > >  	}
> > > 
> > > @@ -649,7 +668,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
> > >  		if (!ctx[class])
> > >  			continue;
> > > 
> > > -		check_results(pceu1, pceu2, class, expected_load);
> > > +		check_results(pceu1, pceu2, class, 1, expected_load);
> > >  		spin_sync_end(fd, ctx[class]);
> > >  		spin_ctx_destroy(fd, ctx[class]);
> > >  	}
> > > @@ -675,7 +694,7 @@ utilization_all_full_load(int fd)
> > >  		if (ctx[class])
> > >  			continue;
> > > 
> > > -		ctx[class] = spin_ctx_init(fd, hwe, vm);
> > > +		ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
> > >  		spin_sync_start(fd, ctx[class]);
> > >  	}
> > > 
> > > @@ -689,7 +708,7 @@ utilization_all_full_load(int fd)
> > >  		if (!ctx[class])
> > >  			continue;
> > > 
> > > -		check_results(pceu1, pceu2, class, EXPECTED_LOAD_FULL);
> > > +		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
> > >  		spin_sync_end(fd, ctx[class]);
> > >  		spin_ctx_destroy(fd, ctx[class]);
> > >  	}
> > > --
> > > 2.43.0
> > > 

[PATCH i-g-t 2/2] tests/intel/xe_drm_fdinfo: Implement virtual/parallel exec queues

[Lucas De Marchi]

Implement a similar function to utilization_single(), but also taking
virtual/parallel into account. I chose some different variable names
to make it more obvious what exactly it is testing and integrated
with the xe_gt_fill_engines_by_class() function recently added.
A possible refactor in the future is to make the other tests use
this function and remove utilization_single().

Based on previous patch by Umesh.

Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/intel/xe_drm_fdinfo.c | 124 +++++++++++++++++++++++++++++++++++-
 1 file changed, 123 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 8acb95040..747b6155c 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -12,6 +12,8 @@
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "xe/xe_spin.h"
+#include "xe/xe_util.h"
+
 /**
  * TEST: xe drm fdinfo
  * Description: Read and verify drm client memory consumption and engine utilization using fdinfo
@@ -67,6 +69,8 @@ IGT_TEST_DESCRIPTION("Read and verify drm client memory consumption and engine u
 #define TEST_BUSY		(1 << 0)
 #define TEST_TRAILING_IDLE	(1 << 1)
 #define TEST_ISOLATION		(1 << 2)
+#define TEST_VIRTUAL		(1 << 3)
+#define TEST_PARALLEL		(1 << 4)
 
 enum expected_load {
 	EXPECTED_LOAD_IDLE,
@@ -715,10 +719,102 @@ utilization_all_full_load(int fd)
 
 	xe_vm_destroy(fd, vm);
 }
+
+/**
+ * SUBTEST: %s-utilization-single-idle
+ * Description: Check that each engine shows no load
+ *
+ * SUBTEST: %s-utilization-single-full-load
+ * Description: Check that each engine shows full load
+ *
+ * SUBTEST: %s-utilization-single-full-load-isolation
+ * Description: Check that each engine load does not spill over to other drm clients
+ *
+ * arg[1]:
+ *
+ * @virtual:			virtual
+ * @parallel:			parallel
+ */
+static void
+utilization_multi(int fd, int gt, int class, unsigned int flags)
+{
+	struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
+	struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
+	struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
+	struct spin_ctx *ctx = NULL;
+	enum expected_load expected_load;
+	int fd_spill, num_placements;
+	uint32_t vm;
+	bool virtual = flags & TEST_VIRTUAL;
+	bool parallel = flags & TEST_PARALLEL;
+	uint16_t width;
+
+	igt_assert(virtual ^ parallel);
+
+	num_placements = xe_gt_fill_engines_by_class(fd, gt, class, eci);
+	if (num_placements < 2)
+		return;
+
+	if (parallel) {
+		width = num_placements;
+		num_placements = 1;
+	} else {
+		width = 1;
+	}
+
+	if (flags & TEST_ISOLATION)
+		fd_spill = drm_reopen_driver(fd);
+
+	vm = xe_vm_create(fd, 0, 0);
+	if (flags & TEST_BUSY) {
+		ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
+		spin_sync_start(fd, ctx);
+	}
+
+	read_engine_cycles(fd, pceu[0]);
+	if (flags & TEST_ISOLATION)
+		read_engine_cycles(fd_spill, pceu_spill[0]);
+
+	usleep(batch_duration_usec);
+	if (flags & TEST_TRAILING_IDLE)
+		spin_sync_end(fd, ctx);
+
+	read_engine_cycles(fd, pceu[1]);
+	if (flags & TEST_ISOLATION)
+		read_engine_cycles(fd_spill, pceu_spill[1]);
+
+	expected_load = flags & TEST_BUSY ?
+	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
+	check_results(pceu[0], pceu[1], class, width, expected_load);
+
+	if (flags & TEST_ISOLATION) {
+		/*
+		 * Load from one client shouldn't spill on another,
+		 * so check for idle
+		 */
+		check_results(pceu_spill[0], pceu_spill[1], class, width,
+			      EXPECTED_LOAD_IDLE);
+		close(fd_spill);
+	}
+
+	spin_sync_end(fd, ctx);
+	spin_ctx_destroy(fd, ctx);
+
+	xe_vm_destroy(fd, vm);
+}
+
 igt_main
 {
+	const struct section {
+		const char *name;
+		unsigned int flags;
+	} sections[] = {
+		{ .name = "virtual", .flags = TEST_VIRTUAL },
+		{ .name = "parallel", .flags = TEST_PARALLEL },
+		{ }
+	};
 	struct drm_xe_engine_class_instance *hwe;
-	int xe;
+	int xe, gt, class;
 
 	igt_fixture {
 		struct drm_client_fdinfo info = { };
@@ -775,6 +871,32 @@ igt_main
 	igt_subtest("utilization-all-full-load")
 		utilization_all_full_load(xe);
 
+
+	for (const struct section *s = sections; s->name; s++) {
+		igt_subtest_f("%s-utilization-single-idle", s->name)
+			xe_for_each_gt(xe, gt)
+				xe_for_each_engine_class(class)
+					utilization_multi(xe, gt, class, s->flags);
+
+		igt_subtest_f("%s-utilization-single-full-load", s->name)
+			xe_for_each_gt(xe, gt)
+				xe_for_each_engine_class(class)
+					utilization_multi(xe, gt, class,
+							  s->flags |
+							  TEST_BUSY |
+							  TEST_TRAILING_IDLE);
+
+		igt_subtest_f("%s-utilization-single-full-load-isolation",
+			      s->name)
+			xe_for_each_gt(xe, gt)
+				xe_for_each_engine_class(class)
+					utilization_multi(xe, gt, class,
+							  s->flags |
+							  TEST_BUSY |
+							  TEST_TRAILING_IDLE |
+							  TEST_ISOLATION);
+	}
+
 	igt_fixture {
 		drm_close_driver(xe);
 	}
-- 
2.43.0

Re: [PATCH i-g-t 2/2] tests/intel/xe_drm_fdinfo: Implement virtual/parallel exec queues

[Matthew Brost]

On Wed, Sep 04, 2024 at 03:57:46PM -0700, Lucas De Marchi wrote:
> Implement a similar function to utilization_single(), but also taking
> virtual/parallel into account. I chose some different variable names
> to make it more obvious what exactly it is testing and integrated
> with the xe_gt_fill_engines_by_class() function recently added.
> A possible refactor in the future is to make the other tests use
> this function and remove utilization_single().
> 
> Based on previous patch by Umesh.
> 
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

One outstanding question in previous patch, but this one LGTM.

Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> ---
>  tests/intel/xe_drm_fdinfo.c | 124 +++++++++++++++++++++++++++++++++++-
>  1 file changed, 123 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 8acb95040..747b6155c 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -12,6 +12,8 @@
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_spin.h"
> +#include "xe/xe_util.h"
> +
>  /**
>   * TEST: xe drm fdinfo
>   * Description: Read and verify drm client memory consumption and engine utilization using fdinfo
> @@ -67,6 +69,8 @@ IGT_TEST_DESCRIPTION("Read and verify drm client memory consumption and engine u
>  #define TEST_BUSY		(1 << 0)
>  #define TEST_TRAILING_IDLE	(1 << 1)
>  #define TEST_ISOLATION		(1 << 2)
> +#define TEST_VIRTUAL		(1 << 3)
> +#define TEST_PARALLEL		(1 << 4)
>  
>  enum expected_load {
>  	EXPECTED_LOAD_IDLE,
> @@ -715,10 +719,102 @@ utilization_all_full_load(int fd)
>  
>  	xe_vm_destroy(fd, vm);
>  }
> +
> +/**
> + * SUBTEST: %s-utilization-single-idle
> + * Description: Check that each engine shows no load
> + *
> + * SUBTEST: %s-utilization-single-full-load
> + * Description: Check that each engine shows full load
> + *
> + * SUBTEST: %s-utilization-single-full-load-isolation
> + * Description: Check that each engine load does not spill over to other drm clients
> + *
> + * arg[1]:
> + *
> + * @virtual:			virtual
> + * @parallel:			parallel
> + */
> +static void
> +utilization_multi(int fd, int gt, int class, unsigned int flags)
> +{
> +	struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> +	struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> +	struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
> +	struct spin_ctx *ctx = NULL;
> +	enum expected_load expected_load;
> +	int fd_spill, num_placements;
> +	uint32_t vm;
> +	bool virtual = flags & TEST_VIRTUAL;
> +	bool parallel = flags & TEST_PARALLEL;
> +	uint16_t width;
> +
> +	igt_assert(virtual ^ parallel);
> +
> +	num_placements = xe_gt_fill_engines_by_class(fd, gt, class, eci);
> +	if (num_placements < 2)
> +		return;
> +
> +	if (parallel) {
> +		width = num_placements;
> +		num_placements = 1;
> +	} else {
> +		width = 1;
> +	}
> +
> +	if (flags & TEST_ISOLATION)
> +		fd_spill = drm_reopen_driver(fd);
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	if (flags & TEST_BUSY) {
> +		ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
> +		spin_sync_start(fd, ctx);
> +	}
> +
> +	read_engine_cycles(fd, pceu[0]);
> +	if (flags & TEST_ISOLATION)
> +		read_engine_cycles(fd_spill, pceu_spill[0]);
> +
> +	usleep(batch_duration_usec);
> +	if (flags & TEST_TRAILING_IDLE)
> +		spin_sync_end(fd, ctx);
> +
> +	read_engine_cycles(fd, pceu[1]);
> +	if (flags & TEST_ISOLATION)
> +		read_engine_cycles(fd_spill, pceu_spill[1]);
> +
> +	expected_load = flags & TEST_BUSY ?
> +	       EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE;
> +	check_results(pceu[0], pceu[1], class, width, expected_load);
> +
> +	if (flags & TEST_ISOLATION) {
> +		/*
> +		 * Load from one client shouldn't spill on another,
> +		 * so check for idle
> +		 */
> +		check_results(pceu_spill[0], pceu_spill[1], class, width,
> +			      EXPECTED_LOAD_IDLE);
> +		close(fd_spill);
> +	}
> +
> +	spin_sync_end(fd, ctx);
> +	spin_ctx_destroy(fd, ctx);
> +
> +	xe_vm_destroy(fd, vm);
> +}
> +
>  igt_main
>  {
> +	const struct section {
> +		const char *name;
> +		unsigned int flags;
> +	} sections[] = {
> +		{ .name = "virtual", .flags = TEST_VIRTUAL },
> +		{ .name = "parallel", .flags = TEST_PARALLEL },
> +		{ }
> +	};
>  	struct drm_xe_engine_class_instance *hwe;
> -	int xe;
> +	int xe, gt, class;
>  
>  	igt_fixture {
>  		struct drm_client_fdinfo info = { };
> @@ -775,6 +871,32 @@ igt_main
>  	igt_subtest("utilization-all-full-load")
>  		utilization_all_full_load(xe);
>  
> +
> +	for (const struct section *s = sections; s->name; s++) {
> +		igt_subtest_f("%s-utilization-single-idle", s->name)
> +			xe_for_each_gt(xe, gt)
> +				xe_for_each_engine_class(class)
> +					utilization_multi(xe, gt, class, s->flags);
> +
> +		igt_subtest_f("%s-utilization-single-full-load", s->name)
> +			xe_for_each_gt(xe, gt)
> +				xe_for_each_engine_class(class)
> +					utilization_multi(xe, gt, class,
> +							  s->flags |
> +							  TEST_BUSY |
> +							  TEST_TRAILING_IDLE);
> +
> +		igt_subtest_f("%s-utilization-single-full-load-isolation",
> +			      s->name)
> +			xe_for_each_gt(xe, gt)
> +				xe_for_each_engine_class(class)
> +					utilization_multi(xe, gt, class,
> +							  s->flags |
> +							  TEST_BUSY |
> +							  TEST_TRAILING_IDLE |
> +							  TEST_ISOLATION);
> +	}
> +
>  	igt_fixture {
>  		drm_close_driver(xe);
>  	}
> -- 
> 2.43.0
> 

✓ CI.xeBAT: success for tests/intel/xe_drm_fdinfo: Virtual and parallel

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1615 bytes --]

== Series Details ==

Series: tests/intel/xe_drm_fdinfo: Virtual and parallel
URL   : https://patchwork.freedesktop.org/series/138225/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8005_BAT -> XEIGTPW_11698_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_11698_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-lnl-1:          [PASS][1] -> [FAIL][2] ([Intel XE#886]) +2 other tests fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886


Build changes
-------------

  * IGT: IGT_8005 -> IGTPW_11698
  * Linux: xe-1890-c72d3ffc0308b71024de6f80c3596668991c67ea -> xe-1891-8b1096500fd6fae573f7d9c4416778d6442e985d

  IGTPW_11698: 11698
  IGT_8005: fc3113c8c1e99797b2d4769aaf02265be64a7589 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1890-c72d3ffc0308b71024de6f80c3596668991c67ea: c72d3ffc0308b71024de6f80c3596668991c67ea
  xe-1891-8b1096500fd6fae573f7d9c4416778d6442e985d: 8b1096500fd6fae573f7d9c4416778d6442e985d

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/index.html

[-- Attachment #2: Type: text/html, Size: 2192 bytes --]

✗ Fi.CI.BAT: failure for tests/intel/xe_drm_fdinfo: Virtual and parallel

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9780 bytes --]

== Series Details ==

Series: tests/intel/xe_drm_fdinfo: Virtual and parallel
URL   : https://patchwork.freedesktop.org/series/138225/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_15359 -> IGTPW_11698
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_11698 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_11698, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/index.html

Participating hosts (38 -> 32)
------------------------------

  Additional (1): bat-mtlp-6 
  Missing    (7): fi-kbl-7567u bat-mtlp-8 bat-dg1-7 fi-snb-2520m fi-cfl-8109u fi-elk-e7500 bat-arlh-2 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_11698:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@hangcheck:
    - bat-arls-5:         [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/bat-arls-5/igt@i915_selftest@live@hangcheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-arls-5/igt@i915_selftest@live@hangcheck.html

  
Known issues
------------

  Here are the changes found in IGTPW_11698 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-mtlp-6:         NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html

  * igt@fbdev@eof:
    - bat-arls-1:         [PASS][4] -> [DMESG-WARN][5] ([i915#12102])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/bat-arls-1/igt@fbdev@eof.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-arls-1/igt@fbdev@eof.html

  * igt@fbdev@info:
    - bat-mtlp-6:         NOTRUN -> [SKIP][6] ([i915#1849] / [i915#2582])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@fbdev@info.html

  * igt@fbdev@write:
    - bat-mtlp-6:         NOTRUN -> [SKIP][7] ([i915#2582]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@fbdev@write.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-mtlp-6:         NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-mtlp-6:         NOTRUN -> [SKIP][9] ([i915#4083])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@gem_mmap@basic.html

  * igt@gem_tiled_blits@basic:
    - bat-mtlp-6:         NOTRUN -> [SKIP][10] ([i915#4077]) +2 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-mtlp-6:         NOTRUN -> [SKIP][11] ([i915#4079]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-mtlp-6:         NOTRUN -> [SKIP][12] ([i915#11681] / [i915#6621])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@hangcheck:
    - bat-arls-2:         [PASS][13] -> [DMESG-WARN][14] ([i915#11349])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/bat-arls-2/igt@i915_selftest@live@hangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-arls-2/igt@i915_selftest@live@hangcheck.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - bat-mtlp-6:         NOTRUN -> [SKIP][15] ([i915#4212] / [i915#9792]) +8 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-mtlp-6:         NOTRUN -> [SKIP][16] ([i915#5190] / [i915#9792])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - bat-mtlp-6:         NOTRUN -> [SKIP][17] ([i915#9792]) +17 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-mtlp-6:         NOTRUN -> [SKIP][18] ([i915#3637] / [i915#9792]) +3 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-mtlp-6:         NOTRUN -> [SKIP][19] ([i915#5274] / [i915#9792])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-mtlp-6:         NOTRUN -> [SKIP][20] ([i915#4342] / [i915#5354] / [i915#9792])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-mtlp-6:         NOTRUN -> [SKIP][21] ([i915#5354] / [i915#9792])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-cursor-plane-move:
    - bat-mtlp-6:         NOTRUN -> [SKIP][22] ([i915#1072] / [i915#9673] / [i915#9732] / [i915#9792]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@kms_psr@psr-cursor-plane-move.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-mtlp-6:         NOTRUN -> [SKIP][23] ([i915#3555] / [i915#8809] / [i915#9792])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-mtlp-6:         NOTRUN -> [SKIP][24] ([i915#3708] / [i915#9792])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-mtlp-6:         NOTRUN -> [SKIP][25] ([i915#3708] / [i915#4077]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-read:
    - bat-mtlp-6:         NOTRUN -> [SKIP][26] ([i915#3708]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - bat-mtlp-6:         NOTRUN -> [SKIP][27] ([i915#10216] / [i915#3708])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-mtlp-6/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@fbdev@write:
    - bat-arls-1:         [FAIL][28] ([i915#12030]) -> [PASS][29] +1 other test pass
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/bat-arls-1/igt@fbdev@write.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/bat-arls-1/igt@fbdev@write.html

  
  [i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#12030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12030
  [i915#12102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12102
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4342
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
  [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
  [i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9792]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9792


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8005 -> IGTPW_11698

  CI-20190529: 20190529
  CI_DRM_15359: 8b1096500fd6fae573f7d9c4416778d6442e985d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_11698: 11698
  IGT_8005: fc3113c8c1e99797b2d4769aaf02265be64a7589 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11698/index.html

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✗ CI.xeFULL: failure for tests/intel/xe_drm_fdinfo: Virtual and parallel

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 54915 bytes --]

== Series Details ==

Series: tests/intel/xe_drm_fdinfo: Virtual and parallel
URL   : https://patchwork.freedesktop.org/series/138225/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8005_full -> XEIGTPW_11698_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_11698_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_11698_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_11698_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][1] -> [DMESG-WARN][2] +2 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4.html

  * igt@xe_vm@large-split-misaligned-binds-134217728:
    - shard-lnl:          [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-3/igt@xe_vm@large-split-misaligned-binds-134217728.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-7/igt@xe_vm@large-split-misaligned-binds-134217728.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_plane@pixel-format:
    - {shard-bmg}:        [DMESG-WARN][5] ([Intel XE#877]) -> [INCOMPLETE][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-bmg-5/igt@kms_plane@pixel-format.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-bmg-8/igt@kms_plane@pixel-format.html

  * igt@kms_plane@pixel-format@pipe-b-plane-0:
    - {shard-bmg}:        [PASS][7] -> [INCOMPLETE][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-bmg-5/igt@kms_plane@pixel-format@pipe-b-plane-0.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-bmg-8/igt@kms_plane@pixel-format@pipe-b-plane-0.html

  
New tests
---------

  New tests have been introduced between XEIGT_8005_full and XEIGTPW_11698_full:

### New IGT tests (9) ###

  * igt@kms_plane_multiple@tiling-none@pipe-a-dp-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.87] s

  * igt@kms_plane_multiple@tiling-none@pipe-b-dp-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.94] s

  * igt@kms_plane_multiple@tiling-none@pipe-c-dp-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.96] s

  * igt@xe_drm_fdinfo@parallel-utilization-single-full-load:
    - Statuses : 2 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.52] s

  * igt@xe_drm_fdinfo@parallel-utilization-single-full-load-isolation:
    - Statuses : 3 pass(s)
    - Exec time: [0.0, 0.51] s

  * igt@xe_drm_fdinfo@parallel-utilization-single-idle:
    - Statuses : 3 pass(s)
    - Exec time: [0.0, 0.51] s

  * igt@xe_drm_fdinfo@virtual-utilization-single-full-load:
    - Statuses : 3 pass(s)
    - Exec time: [0.0, 0.51] s

  * igt@xe_drm_fdinfo@virtual-utilization-single-full-load-isolation:
    - Statuses : 2 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.52] s

  * igt@xe_drm_fdinfo@virtual-utilization-single-idle:
    - Statuses : 3 pass(s)
    - Exec time: [0.0, 0.51] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_11698_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotreplug:
    - shard-lnl:          [PASS][9] -> [SKIP][10] ([Intel XE#1885])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-4/igt@core_hotunplug@hotreplug.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@core_hotunplug@hotreplug.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
    - shard-lnl:          [PASS][11] -> [FAIL][12] ([Intel XE#1701]) +1 other test fail
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-6/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#1201] / [Intel XE#316])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-433/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#1124] / [Intel XE#1201]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-463/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#1201] / [Intel XE#373]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-466/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-set2:     NOTRUN -> [FAIL][16] ([Intel XE#1178]) +1 other test fail
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-466/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - shard-lnl:          [PASS][17] -> [SKIP][18] ([Intel XE#2423]) +3 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-8/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#1201] / [Intel XE#455])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-436/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1:
    - shard-lnl:          [PASS][20] -> [FAIL][21] ([Intel XE#886]) +3 other tests fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-8/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-2/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg2-set2:     [PASS][22] -> [INCOMPLETE][23] ([Intel XE#2049] / [Intel XE#2597])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-435/igt@kms_flip@flip-vs-suspend.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@d-dp4:
    - shard-dg2-set2:     [PASS][24] -> [INCOMPLETE][25] ([Intel XE#2049])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-435/igt@kms_flip@flip-vs-suspend@d-dp4.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_flip@flip-vs-suspend@d-dp4.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#1201] / [Intel XE#651]) +5 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-lnl:          [PASS][27] -> [SKIP][28] ([Intel XE#2351]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][29] ([Intel XE#1201] / [Intel XE#653]) +4 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-edp-1:
    - shard-lnl:          [PASS][30] -> [DMESG-FAIL][31] ([Intel XE#1620] / [Intel XE#1760]) +1 other test dmesg-fail
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-3/igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-edp-1.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-edp-1.html

  * igt@kms_plane@plane-position-hole@pipe-b-plane-4:
    - shard-lnl:          [PASS][32] -> [DMESG-WARN][33] ([Intel XE#324])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-5/igt@kms_plane@plane-position-hole@pipe-b-plane-4.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-6/igt@kms_plane@plane-position-hole@pipe-b-plane-4.html

  * igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
    - shard-dg2-set2:     [PASS][34] -> [FAIL][35] ([Intel XE#616]) +1 other test fail
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-463/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html

  * igt@kms_psr@psr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][36] ([Intel XE#1201] / [Intel XE#929]) +2 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-433/igt@kms_psr@psr-dpms.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#1149] / [Intel XE#1201])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-463/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-lnl:          [PASS][38] -> [FAIL][39] ([Intel XE#899]) +1 other test fail
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-8/igt@kms_universal_plane@cursor-fb-leak.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-2/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-lnl:          [PASS][40] -> [FAIL][41] ([Intel XE#2443]) +1 other test fail
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-7/igt@kms_vrr@flip-basic-fastset.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-6/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@lobf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][42] ([Intel XE#1201] / [Intel XE#2168])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-433/igt@kms_vrr@lobf.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#1201] / [Intel XE#756])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-436/igt@kms_writeback@writeback-invalid-parameters.html

  * {igt@xe_drm_fdinfo@parallel-utilization-single-full-load} (NEW):
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#1130]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@xe_drm_fdinfo@parallel-utilization-single-full-load.html

  * igt@xe_exec_balancer@no-exec-cm-parallel-userptr-invalidate-race:
    - shard-lnl:          [PASS][45] -> [SKIP][46] ([Intel XE#1130]) +5 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-8/igt@xe_exec_balancer@no-exec-cm-parallel-userptr-invalidate-race.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@xe_exec_balancer@no-exec-cm-parallel-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-bindexecqueue-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][47] ([Intel XE#288]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@xe_exec_fault_mode@many-bindexecqueue-prefetch.html

  * igt@xe_exec_fault_mode@many-bindexecqueue-rebind-prefetch:
    - shard-lnl:          [PASS][48] -> [FAIL][49] ([Intel XE#1069])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-5/igt@xe_exec_fault_mode@many-bindexecqueue-rebind-prefetch.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-7/igt@xe_exec_fault_mode@many-bindexecqueue-rebind-prefetch.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][50] ([Intel XE#1201] / [Intel XE#288]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-434/igt@xe_exec_fault_mode@once-bindexecqueue-imm.html

  * igt@xe_oa@mi-rpc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#1201] / [Intel XE#2541]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-466/igt@xe_oa@mi-rpc.html

  * igt@xe_oa@mmio-triggered-reports:
    - shard-lnl:          [PASS][52] -> [FAIL][53] ([Intel XE#2249])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-1/igt@xe_oa@mmio-triggered-reports.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-8/igt@xe_oa@mmio-triggered-reports.html

  * igt@xe_oa@mmio-triggered-reports@rcs-0:
    - shard-lnl:          NOTRUN -> [FAIL][54] ([Intel XE#2249])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-8/igt@xe_oa@mmio-triggered-reports@rcs-0.html

  * igt@xe_oa@oa-regs-whitelisted:
    - shard-lnl:          [PASS][55] -> [FAIL][56] ([Intel XE#2514])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-3/igt@xe_oa@oa-regs-whitelisted.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-7/igt@xe_oa@oa-regs-whitelisted.html

  * igt@xe_oa@oa-regs-whitelisted@ccs-0:
    - shard-lnl:          NOTRUN -> [FAIL][57] ([Intel XE#2514])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-7/igt@xe_oa@oa-regs-whitelisted@ccs-0.html

  * igt@xe_pm@s4-mocs:
    - shard-lnl:          [PASS][58] -> [ABORT][59] ([Intel XE#1794])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-1/igt@xe_pm@s4-mocs.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-2/igt@xe_pm@s4-mocs.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2:
    - {shard-bmg}:        [FAIL][60] ([Intel XE#1426]) -> [PASS][61] +1 other test pass
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-bmg-4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-bmg-4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [FAIL][62] ([Intel XE#1426]) -> [PASS][63] +1 other test pass
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-435/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-6.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-436/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-6.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1:
    - shard-lnl:          [FAIL][64] ([Intel XE#1426]) -> [PASS][65] +1 other test pass
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-5/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-7/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          [FAIL][66] ([Intel XE#1659]) -> [PASS][67] +1 other test pass
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-dp-2:
    - {shard-bmg}:        [FAIL][68] ([Intel XE#2436]) -> [PASS][69] +3 other tests pass
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-bmg-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-dp-2.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-dp-2.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - {shard-bmg}:        [DMESG-WARN][70] ([Intel XE#877]) -> [PASS][71] +6 other tests pass
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
    - {shard-bmg}:        [INCOMPLETE][72] -> [PASS][73] +1 other test pass
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-bmg-4/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-bmg-1/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-lnl:          [FAIL][74] ([Intel XE#886]) -> [PASS][75] +1 other test pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-2/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-7/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_hdr@invalid-hdr:
    - {shard-bmg}:        [SKIP][76] ([Intel XE#1503]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-bmg-7/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane@plane-position-hole@pipe-a-plane-2:
    - shard-lnl:          [DMESG-FAIL][78] ([Intel XE#324]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-5/igt@kms_plane@plane-position-hole@pipe-a-plane-2.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-6/igt@kms_plane@plane-position-hole@pipe-a-plane-2.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - {shard-bmg}:        [FAIL][80] ([Intel XE#899]) -> [PASS][81] +1 other test pass
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-bmg-8/igt@kms_universal_plane@cursor-fb-leak.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-bmg-8/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - {shard-bmg}:        [TIMEOUT][82] ([Intel XE#2105]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-bmg-2/igt@xe_exec_reset@parallel-gt-reset.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-bmg-2/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_intel_bb@destroy-bb:
    - shard-dg2-set2:     [DMESG-WARN][84] -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-433/igt@xe_intel_bb@destroy-bb.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-434/igt@xe_intel_bb@destroy-bb.html

  * igt@xe_live_ktest@xe_dma_buf:
    - shard-lnl:          [SKIP][86] ([Intel XE#1192]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-1/igt@xe_live_ktest@xe_dma_buf.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-3/igt@xe_live_ktest@xe_dma_buf.html

  * igt@xe_module_load@reload:
    - shard-dg2-set2:     [FAIL][88] ([Intel XE#2136]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-436/igt@xe_module_load@reload.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@xe_module_load@reload.html

  * igt@xe_pm@s2idle-vm-bind-unbind-all:
    - {shard-bmg}:        [INCOMPLETE][90] ([Intel XE#1616]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-bmg-2/igt@xe_pm@s2idle-vm-bind-unbind-all.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-bmg-1/igt@xe_pm@s2idle-vm-bind-unbind-all.html
    - shard-dg2-set2:     [INCOMPLETE][92] ([Intel XE#1694]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@xe_pm@s2idle-vm-bind-unbind-all.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-434/igt@xe_pm@s2idle-vm-bind-unbind-all.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-6-4-mc-ccs:
    - shard-dg2-set2:     [SKIP][94] ([Intel XE#1201] / [Intel XE#801]) -> [SKIP][95] ([Intel XE#801]) +23 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-466/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-6-4-mc-ccs.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-6-4-mc-ccs.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-dg2-set2:     [SKIP][96] ([Intel XE#873]) -> [SKIP][97] ([Intel XE#1201] / [Intel XE#873])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_async_flips@invalid-async-flip.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][98] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][99] ([Intel XE#316]) +2 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-434/igt@kms_big_fb@linear-16bpp-rotate-270.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][100] ([Intel XE#316]) -> [SKIP][101] ([Intel XE#1201] / [Intel XE#316]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_big_fb@linear-32bpp-rotate-90.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-434/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-lnl:          [SKIP][102] ([Intel XE#1407]) -> [SKIP][103] ([Intel XE#2351])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-4/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-dg2-set2:     [SKIP][104] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][105] ([Intel XE#1124]) +3 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-436/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-lnl:          [SKIP][106] ([Intel XE#1124]) -> [SKIP][107] ([Intel XE#2351]) +1 other test skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg2-set2:     [SKIP][108] ([Intel XE#1124]) -> [SKIP][109] ([Intel XE#1124] / [Intel XE#1201]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-463/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p:
    - shard-dg2-set2:     [SKIP][110] ([Intel XE#367]) -> [SKIP][111] ([Intel XE#1201] / [Intel XE#367])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][112] ([Intel XE#1201] / [Intel XE#2191]) -> [SKIP][113] ([Intel XE#2191])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-466/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][114] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][115] ([Intel XE#367]) +3 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-433/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][116] ([Intel XE#787]) -> [SKIP][117] ([Intel XE#1201] / [Intel XE#787]) +62 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-433/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-dg2-set2:     [SKIP][118] ([Intel XE#1201] / [Intel XE#1252]) -> [SKIP][119] ([Intel XE#1252]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-463/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs:
    - shard-dg2-set2:     [SKIP][120] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][121] ([Intel XE#455] / [Intel XE#787]) +13 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][122] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][123] ([Intel XE#787]) +48 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     [SKIP][124] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][125] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +17 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4.html

  * igt@kms_cdclk@mode-transition@pipe-d-dp-4:
    - shard-dg2-set2:     [SKIP][126] ([Intel XE#314]) -> [SKIP][127] ([Intel XE#1201] / [Intel XE#314]) +3 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-433/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-dg2-set2:     [SKIP][128] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][129] ([Intel XE#373]) +6 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-435/igt@kms_chamelium_audio@dp-audio.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-lnl:          [SKIP][130] ([Intel XE#373]) -> [SKIP][131] ([Intel XE#2423]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-3/igt@kms_chamelium_audio@hdmi-audio-edid.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-dg2-set2:     [SKIP][132] ([Intel XE#1201] / [Intel XE#306]) -> [SKIP][133] ([Intel XE#306]) +2 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-463/igt@kms_chamelium_color@ctm-red-to-blue.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_hpd@dp-hpd-fast:
    - shard-dg2-set2:     [SKIP][134] ([Intel XE#373]) -> [SKIP][135] ([Intel XE#1201] / [Intel XE#373]) +3 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_chamelium_hpd@dp-hpd-fast.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@kms_chamelium_hpd@dp-hpd-fast.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-dg2-set2:     [SKIP][136] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][137] ([Intel XE#308]) +3 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-466/igt@kms_cursor_crc@cursor-offscreen-512x170.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-dg2-set2:     [SKIP][138] ([Intel XE#308]) -> [SKIP][139] ([Intel XE#1201] / [Intel XE#308])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_cursor_crc@cursor-offscreen-512x512.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-433/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg2-set2:     [SKIP][140] ([Intel XE#1201] / [Intel XE#323]) -> [SKIP][141] ([Intel XE#323])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-435/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2-set2:     [SKIP][142] ([Intel XE#455]) -> [SKIP][143] ([Intel XE#1201] / [Intel XE#455]) +4 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-436/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [SKIP][144] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][145] ([Intel XE#651]) +23 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-suspend:
    - shard-dg2-set2:     [SKIP][146] ([Intel XE#651]) -> [SKIP][147] ([Intel XE#1201] / [Intel XE#651]) +18 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-suspend.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          [SKIP][148] ([Intel XE#656]) -> [SKIP][149] ([Intel XE#2351]) +2 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2-set2:     [SKIP][150] ([Intel XE#1201] / [Intel XE#658]) -> [SKIP][151] ([Intel XE#658])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][152] ([Intel XE#653]) -> [SKIP][153] ([Intel XE#1201] / [Intel XE#653]) +15 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt:
    - shard-dg2-set2:     [SKIP][154] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][155] ([Intel XE#653]) +19 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_plane@plane-position-hole:
    - shard-lnl:          [DMESG-FAIL][156] ([Intel XE#324]) -> [DMESG-WARN][157] ([Intel XE#324])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-5/igt@kms_plane@plane-position-hole.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-6/igt@kms_plane@plane-position-hole.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation:
    - shard-dg2-set2:     [SKIP][158] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#498]) -> [SKIP][159] ([Intel XE#455] / [Intel XE#498]) +1 other test skip
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-435/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][160] ([Intel XE#1201] / [Intel XE#498]) -> [SKIP][161] ([Intel XE#498]) +2 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-435/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
    - shard-dg2-set2:     [SKIP][162] ([Intel XE#2318] / [Intel XE#455]) -> [SKIP][163] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-463/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][164] ([Intel XE#2318]) -> [SKIP][165] ([Intel XE#1201] / [Intel XE#2318]) +2 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-6.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-463/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-6.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-dg2-set2:     [SKIP][166] ([Intel XE#870]) -> [SKIP][167] ([Intel XE#1201] / [Intel XE#870]) +1 other test skip
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_pm_backlight@bad-brightness.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-434/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area:
    - shard-dg2-set2:     [SKIP][168] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][169] ([Intel XE#1489]) +1 other test skip
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-435/igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
    - shard-dg2-set2:     [SKIP][170] ([Intel XE#1489]) -> [SKIP][171] ([Intel XE#1201] / [Intel XE#1489]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2-set2:     [SKIP][172] ([Intel XE#1122]) -> [SKIP][173] ([Intel XE#1122] / [Intel XE#1201]) +1 other test skip
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_psr2_su@page_flip-p010.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff:
    - shard-dg2-set2:     [SKIP][174] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][175] ([Intel XE#929]) +10 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-463/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html

  * igt@kms_psr@pr-sprite-plane-move:
    - shard-dg2-set2:     [SKIP][176] ([Intel XE#929]) -> [SKIP][177] ([Intel XE#1201] / [Intel XE#929]) +3 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_psr@pr-sprite-plane-move.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-466/igt@kms_psr@pr-sprite-plane-move.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2-set2:     [SKIP][178] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][179] ([Intel XE#327])
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-433/igt@kms_rotation_crc@bad-tiling.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-dg2-set2:     [SKIP][180] ([Intel XE#1127]) -> [SKIP][181] ([Intel XE#1127] / [Intel XE#1201])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-dg2-set2:     [SKIP][182] ([Intel XE#327]) -> [SKIP][183] ([Intel XE#1201] / [Intel XE#327]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-466/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_vrr@flip-dpms:
    - shard-dg2-set2:     [SKIP][184] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][185] ([Intel XE#455]) +9 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-433/igt@kms_vrr@flip-dpms.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_vrr@flip-dpms.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-dg2-set2:     [SKIP][186] ([Intel XE#1201] / [Intel XE#756]) -> [SKIP][187] ([Intel XE#756]) +1 other test skip
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-434/igt@kms_writeback@writeback-pixel-formats.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@kms_writeback@writeback-pixel-formats.html

  * igt@xe_evict@evict-beng-mixed-many-threads-large:
    - shard-dg2-set2:     [TIMEOUT][188] ([Intel XE#1473]) -> [INCOMPLETE][189] ([Intel XE#1195] / [Intel XE#1473])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-434/igt@xe_evict@evict-beng-mixed-many-threads-large.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-large.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-lnl:          [SKIP][190] ([Intel XE#688]) -> [SKIP][191] ([Intel XE#1130]) +1 other test skip
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-2/igt@xe_evict@evict-mixed-many-threads-small.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-5/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-imm:
    - shard-dg2-set2:     [SKIP][192] ([Intel XE#288]) -> [SKIP][193] ([Intel XE#1201] / [Intel XE#288]) +17 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@xe_exec_fault_mode@many-execqueues-userptr-imm.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-434/igt@xe_exec_fault_mode@many-execqueues-userptr-imm.html

  * igt@xe_exec_fault_mode@once-invalid-userptr-fault:
    - shard-dg2-set2:     [SKIP][194] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][195] ([Intel XE#288]) +16 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-434/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
    - shard-dg2-set2:     [SKIP][196] ([Intel XE#1201] / [Intel XE#2360]) -> [SKIP][197] ([Intel XE#2360])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-463/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html

  * igt@xe_mmap@small-bar:
    - shard-dg2-set2:     [SKIP][198] ([Intel XE#512]) -> [SKIP][199] ([Intel XE#1201] / [Intel XE#512])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@xe_mmap@small-bar.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-463/igt@xe_mmap@small-bar.html

  * igt@xe_module_load@load:
    - shard-dg2-set2:     [SKIP][200] ([Intel XE#1201] / [Intel XE#378]) -> [SKIP][201] ([Intel XE#378])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-435/igt@xe_module_load@load.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@xe_module_load@load.html

  * igt@xe_oa@rc6-disable:
    - shard-dg2-set2:     [SKIP][202] ([Intel XE#2541]) -> [SKIP][203] ([Intel XE#1201] / [Intel XE#2541]) +1 other test skip
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@xe_oa@rc6-disable.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-463/igt@xe_oa@rc6-disable.html

  * igt@xe_oa@whitelisted-registers-userspace-config:
    - shard-dg2-set2:     [SKIP][204] ([Intel XE#1201] / [Intel XE#2541]) -> [SKIP][205] ([Intel XE#2541]) +6 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-433/igt@xe_oa@whitelisted-registers-userspace-config.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@xe_oa@whitelisted-registers-userspace-config.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-dg2-set2:     [SKIP][206] ([Intel XE#1337]) -> [SKIP][207] ([Intel XE#1201] / [Intel XE#1337])
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@xe_pat@display-vs-wb-transient.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-dg2-set2:     [SKIP][208] ([Intel XE#944]) -> [SKIP][209] ([Intel XE#1201] / [Intel XE#944]) +3 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-432/igt@xe_query@multigpu-query-oa-units.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-433/igt@xe_query@multigpu-query-oa-units.html

  * igt@xe_query@multigpu-query-topology:
    - shard-dg2-set2:     [SKIP][210] ([Intel XE#1201] / [Intel XE#944]) -> [SKIP][211] ([Intel XE#944]) +1 other test skip
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-433/igt@xe_query@multigpu-query-topology.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-432/igt@xe_query@multigpu-query-topology.html

  * igt@xe_wedged@basic-wedged:
    - shard-dg2-set2:     [DMESG-WARN][212] ([Intel XE#1760]) -> [SKIP][213] ([Intel XE#1130] / [Intel XE#1201])
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-433/igt@xe_wedged@basic-wedged.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@xe_wedged@basic-wedged.html

  * igt@xe_wedged@wedged-at-any-timeout:
    - shard-dg2-set2:     [DMESG-WARN][214] ([Intel XE#1760]) -> [DMESG-FAIL][215] ([Intel XE#1760])
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-dg2-434/igt@xe_wedged@wedged-at-any-timeout.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-dg2-435/igt@xe_wedged@wedged-at-any-timeout.html
    - shard-lnl:          [DMESG-WARN][216] ([Intel XE#1760]) -> [DMESG-FAIL][217] ([Intel XE#1760])
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8005/shard-lnl-3/igt@xe_wedged@wedged-at-any-timeout.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/shard-lnl-6/igt@xe_wedged@wedged-at-any-timeout.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1069
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
  [Intel XE#1149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1149
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
  [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
  [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1616
  [Intel XE#1620]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1620
  [Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659
  [Intel XE#1694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1694
  [Intel XE#1701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1701
  [Intel XE#1760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1760
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1885]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1885
  [Intel XE#2026]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2026
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2105]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2105
  [Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2249
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2318
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2357]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2357
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
  [Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
  [Intel XE#2436]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2436
  [Intel XE#2443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2443
  [Intel XE#2514]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2514
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
  [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498
  [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#801]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/801
  [Intel XE#827]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/827
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8005 -> IGTPW_11698
  * Linux: xe-1890-c72d3ffc0308b71024de6f80c3596668991c67ea -> xe-1891-8b1096500fd6fae573f7d9c4416778d6442e985d

  IGTPW_11698: 11698
  IGT_8005: fc3113c8c1e99797b2d4769aaf02265be64a7589 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1890-c72d3ffc0308b71024de6f80c3596668991c67ea: c72d3ffc0308b71024de6f80c3596668991c67ea
  xe-1891-8b1096500fd6fae573f7d9c4416778d6442e985d: 8b1096500fd6fae573f7d9c4416778d6442e985d

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11698/index.html

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