[PATCH i-g-t 0/2] Execute and validate 'write_on_exception' shader

[PATCH i-g-t 0/2] Execute and validate 'write_on_exception' shader

[Christoph Manszewski]

Hi,

this is a followup to the 'Test coverage for GPU debug support' series
which addresses the review feedback about 'write_on_excepton' shader
usage. Currently it is only used in a negative way thus we don't
ensure that it actually works as expected. This series changes that.

Thanks,
Christoph

Christoph Manszewski (2):
  lib/gpgpu_shader: Add x_offset parameter for
    gpgpu_shader__write_on_exception
  tests/xe_exec_sip: Write on invalidinstr

 lib/gpgpu_shader.c          | 29 ++++++++------
 lib/gpgpu_shader.h          |  4 +-
 lib/iga64_generated_codes.c | 77 ++++++++++++++++++-----------------
 tests/intel/xe_exec_sip.c   | 80 +++++++++++++++++++++++--------------
 4 files changed, 108 insertions(+), 82 deletions(-)

-- 
2.34.1

[PATCH i-g-t 1/2] lib/gpgpu_shader: Add x_offset parameter for gpgpu_shader__write_on_exception

[Christoph Manszewski]

Currently gpgpu_shader__write_on_exception always writes the first
column equal to thread group ID x. Make it possible to specify an offset
from that value.

Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/gpgpu_shader.c          | 29 +++++++-------
 lib/gpgpu_shader.h          |  4 +-
 lib/iga64_generated_codes.c | 77 ++++++++++++++++++++-----------------
 tests/intel/xe_exec_sip.c   |  6 +--
 4 files changed, 62 insertions(+), 54 deletions(-)

diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
index 6d8c7ebb8..8df8d9612 100644
--- a/lib/gpgpu_shader.c
+++ b/lib/gpgpu_shader.c
@@ -670,6 +670,7 @@ void gpgpu_shader__set_exception(struct gpgpu_shader *shdr, uint32_t value)
  * gpgpu_shader__write_on_exception:
  * @shdr: shader to be modified
  * @value: dword to be written
+ * @x_offset: write target offset within the surface in columns added to the 'thread group id x'
  * @y_offset: write target offset within the surface in rows
  * @mask: mask to be applied on exception register
  * @expected: expected value of exception register with @mask applied
@@ -678,45 +679,47 @@ void gpgpu_shader__set_exception(struct gpgpu_shader *shdr, uint32_t value)
  * to provided ones: cr0.1 & @mask == @expected,
  * if yes fill dword in (row, column/dword) == (tg_id_y + @y_offset, tg_id_x).
  */
-void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t value,
+void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t value, uint32_t x_offset,
 				      uint32_t y_offset, uint32_t mask, uint32_t expected)
 {
 	emit_iga64_code(shdr, write_on_exception, "					\n\
 	// Clear message header								\n\
 (W)	mov (16|M0)              r4.0<1>:ud    0x0:ud					\n\
 	// Payload									\n\
-(W)	mov (1|M0)               r5.0<1>:ud    ARG(3):ud				\n\
+(W)	mov (1|M0)               r5.0<1>:ud    ARG(4):ud				\n\
 #if GEN_VER < 2000 // prepare Media Block Write						\n\
 	// X offset of the block in bytes := (thread group id X << ARG(0))		\n\
-(W)	shl (1|M0)               r4.0<1>:ud    r0.1<0;1,0>:ud    ARG(0):ud		\n\
+(W)	add (1|M0)               r4.0<1>:ud    r0.1<0;1,0>:ud	 ARG(1):ud		\n\
+(W)	shl (1|M0)               r4.0<1>:ud    r4.0<0;1,0>:ud    ARG(0):ud		\n\
 	// Y offset of the block in rows := thread group id Y				\n\
 (W)	mov (1|M0)               r4.1<1>:ud    r0.6<0;1,0>:ud				\n\
-(W)	add (1|M0)               r4.1<1>:ud    r4.1<0;1,0>:ud   ARG(1):ud		\n\
+(W)	add (1|M0)               r4.1<1>:ud    r4.1<0;1,0>:ud   ARG(2):ud		\n\
 	// block width [0,63] representing 1 to 64 bytes				\n\
-(W)	mov (1|M0)               r4.2<1>:ud    ARG(2):ud				\n\
+(W)	mov (1|M0)               r4.2<1>:ud    ARG(3):ud				\n\
 	// FFTID := FFTID from R0 header						\n\
 (W)	mov (1|M0)               r4.4<1>:ud    r0.5<0;1,0>:ud				\n\
 #else // prepare Typed 2D Block Store							\n\
-	// Load r2.0-3 with tg id X << ARG(0)						\n\
-(W)	shl (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud    ARG(0):ud		\n\
-	// Load r2.4-7 with tg id Y + ARG(1):ud						\n\
+	// Load r2.0 with tg id (X + ARG(1)) << ARG(0)					\n\
+(W)	add (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud	 ARG(1):ud		\n\
+(W)	shl (1|M0)               r2.0<1>:ud    r2.0<0;1,0>:ud    ARG(0):ud		\n\
+	// Load r2.4-7 with tg id Y + ARG(2):ud						\n\
 (W)	mov (1|M0)               r2.1<1>:ud    r0.6<0;1,0>:ud				\n\
-(W)	add (1|M0)               r2.1<1>:ud    r2.1<0;1,0>:ud    ARG(1):ud		\n\
+(W)	add (1|M0)               r2.1<1>:ud    r2.1<0;1,0>:ud    ARG(2):ud		\n\
 	// Store X and Y block start (160:191 and 192:223)				\n\
 (W)	mov (2|M0)               r4.5<1>:ud    r2.0<2;2,1>:ud				\n\
 	// Store X and Y block max_size (224:231 and 232:239)				\n\
-(W)	mov (1|M0)               r4.7<1>:ud    ARG(2):ud				\n\
+(W)	mov (1|M0)               r4.7<1>:ud    ARG(3):ud				\n\
 #endif											\n\
 	// Check if masked exception is equal to provided value and write conditionally \n\
-(W)      and (1|M0)              r3.0<1>:ud     cr0.1<0;1,0>:ud ARG(4):ud		\n\
+(W)      and (1|M0)              r3.0<1>:ud     cr0.1<0;1,0>:ud ARG(5):ud		\n\
 (W)      mov (1|M0)              f0.0<1>:ud     0x0:ud					\n\
-(W)      cmp (1|M0)     (eq)f0.0 null:ud        r3.0<0;1,0>:ud  ARG(5):ud		\n\
+(W)      cmp (1|M0)     (eq)f0.0 null:ud        r3.0<0;1,0>:ud  ARG(6):ud		\n\
 #if GEN_VER < 2000 // Media Block Write							\n\
 (W&f0.0) send.dc1 (16|M0)        null     r4   src1_null 0    0x40A8000			\n\
 #else // Typed 2D Block Store								\n\
 (W&f0.0) send.tgm (16|M0)        null     r4   null:0    0    0x64000007		\n\
 #endif											\n\
-	", 2, y_offset, 3, value, mask, expected);
+	", 2, x_offset, y_offset, 3, value, mask, expected);
 }
 
 /**
diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
index 53fe2869e..5f6260fb3 100644
--- a/lib/gpgpu_shader.h
+++ b/lib/gpgpu_shader.h
@@ -82,8 +82,8 @@ void gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
 void gpgpu_shader__write_aip(struct gpgpu_shader *shdr, uint32_t y_offset);
 void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
 			       uint32_t y_offset);
-void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw,
-			       uint32_t y_offset, uint32_t mask, uint32_t value);
+void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
+				      uint32_t y_offset, uint32_t mask, uint32_t value);
 void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
 void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
 void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
index fe6d68b70..91adc7313 100644
--- a/lib/iga64_generated_codes.c
+++ b/lib/iga64_generated_codes.c
@@ -3,7 +3,7 @@
 
 #include "gpgpu_shader.h"
 
-#define MD5_SUM_IGA64_ASMS aa5c79b36f48404f1da21d2316e9f9f3
+#define MD5_SUM_IGA64_ASMS a1dfb701367264e53d0d33f53d8769e3
 
 struct iga64_template const iga64_code_gpgpu_fill[] = {
 	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
@@ -193,83 +193,88 @@ struct iga64_template const iga64_code_breakpoint_suppress[] = {
 };
 
 struct iga64_template const iga64_code_write_on_exception[] = {
-	{ .gen_ver = 2000, .size = 56, .code = (const uint32_t []) {
+	{ .gen_ver = 2000, .size = 60, .code = (const uint32_t []) {
 		0x80100061, 0x04054220, 0x00000000, 0x00000000,
-		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
-		0x80000069, 0x02058220, 0x02000014, 0xc0ded000,
+		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
+		0x80000040, 0x02058220, 0x02000014, 0xc0ded001,
+		0x80001969, 0x02058220, 0x02000204, 0xc0ded000,
 		0x80000061, 0x02150220, 0x00000064, 0x00000000,
-		0x80001940, 0x02158220, 0x02000214, 0xc0ded001,
+		0x80001940, 0x02158220, 0x02000214, 0xc0ded002,
 		0x80041961, 0x04550220, 0x00220205, 0x00000000,
-		0x80000061, 0x04754220, 0x00000000, 0xc0ded002,
-		0x80000965, 0x03058220, 0x02008010, 0xc0ded004,
+		0x80000061, 0x04754220, 0x00000000, 0xc0ded003,
+		0x80000965, 0x03058220, 0x02008010, 0xc0ded005,
 		0x80000961, 0x30014220, 0x00000000, 0x00000000,
-		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
+		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
 		0x84134031, 0x00000000, 0xd00e0494, 0x04000000,
 		0x80000001, 0x00010000, 0x20000000, 0x00000000,
 		0x80000001, 0x00010000, 0x30000000, 0x00000000,
 		0x80000901, 0x00010000, 0x00000000, 0x00000000,
 	}},
-	{ .gen_ver = 1270, .size = 60, .code = (const uint32_t []) {
+	{ .gen_ver = 1270, .size = 64, .code = (const uint32_t []) {
 		0x80040061, 0x04054220, 0x00000000, 0x00000000,
-		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
-		0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
+		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
+		0x80000040, 0x04058220, 0x02000024, 0xc0ded001,
+		0x80001969, 0x04058220, 0x02000404, 0xc0ded000,
 		0x80000061, 0x04250220, 0x000000c4, 0x00000000,
-		0x80001940, 0x04258220, 0x02000424, 0xc0ded001,
-		0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
+		0x80001940, 0x04258220, 0x02000424, 0xc0ded002,
+		0x80000061, 0x04454220, 0x00000000, 0xc0ded003,
 		0x80000061, 0x04850220, 0x000000a4, 0x00000000,
-		0x80000965, 0x03058220, 0x02008020, 0xc0ded004,
+		0x80000965, 0x03058220, 0x02008020, 0xc0ded005,
 		0x80000961, 0x30014220, 0x00000000, 0x00000000,
-		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
+		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
 		0x80001a01, 0x00010000, 0x00000000, 0x00000000,
 		0x81044031, 0x00000000, 0xc0000414, 0x02a00000,
 		0x80000001, 0x00010000, 0x20000000, 0x00000000,
 		0x80000001, 0x00010000, 0x30000000, 0x00000000,
 		0x80000901, 0x00010000, 0x00000000, 0x00000000,
 	}},
-	{ .gen_ver = 1260, .size = 56, .code = (const uint32_t []) {
+	{ .gen_ver = 1260, .size = 60, .code = (const uint32_t []) {
 		0x80100061, 0x04054220, 0x00000000, 0x00000000,
-		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
-		0x80000069, 0x04058220, 0x02000014, 0xc0ded000,
+		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
+		0x80000040, 0x04058220, 0x02000014, 0xc0ded001,
+		0x80001969, 0x04058220, 0x02000404, 0xc0ded000,
 		0x80000061, 0x04150220, 0x00000064, 0x00000000,
-		0x80001940, 0x04158220, 0x02000414, 0xc0ded001,
-		0x80000061, 0x04254220, 0x00000000, 0xc0ded002,
+		0x80001940, 0x04158220, 0x02000414, 0xc0ded002,
+		0x80000061, 0x04254220, 0x00000000, 0xc0ded003,
 		0x80000061, 0x04450220, 0x00000054, 0x00000000,
-		0x80000965, 0x03058220, 0x02008010, 0xc0ded004,
+		0x80000965, 0x03058220, 0x02008010, 0xc0ded005,
 		0x80000961, 0x30014220, 0x00000000, 0x00000000,
-		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
+		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
 		0x84134031, 0x00000000, 0xc0000414, 0x02a00000,
 		0x80000001, 0x00010000, 0x20000000, 0x00000000,
 		0x80000001, 0x00010000, 0x30000000, 0x00000000,
 		0x80000901, 0x00010000, 0x00000000, 0x00000000,
 	}},
-	{ .gen_ver = 1250, .size = 60, .code = (const uint32_t []) {
+	{ .gen_ver = 1250, .size = 64, .code = (const uint32_t []) {
 		0x80040061, 0x04054220, 0x00000000, 0x00000000,
-		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
-		0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
+		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
+		0x80000040, 0x04058220, 0x02000024, 0xc0ded001,
+		0x80001969, 0x04058220, 0x02000404, 0xc0ded000,
 		0x80000061, 0x04250220, 0x000000c4, 0x00000000,
-		0x80001940, 0x04258220, 0x02000424, 0xc0ded001,
-		0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
+		0x80001940, 0x04258220, 0x02000424, 0xc0ded002,
+		0x80000061, 0x04454220, 0x00000000, 0xc0ded003,
 		0x80000061, 0x04850220, 0x000000a4, 0x00000000,
-		0x80000965, 0x03058220, 0x02008020, 0xc0ded004,
+		0x80000965, 0x03058220, 0x02008020, 0xc0ded005,
 		0x80000961, 0x30014220, 0x00000000, 0x00000000,
-		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
+		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
 		0x80001a01, 0x00010000, 0x00000000, 0x00000000,
 		0x81044031, 0x00000000, 0xc0000414, 0x02a00000,
 		0x80000001, 0x00010000, 0x20000000, 0x00000000,
 		0x80000001, 0x00010000, 0x30000000, 0x00000000,
 		0x80000901, 0x00010000, 0x00000000, 0x00000000,
 	}},
-	{ .gen_ver = 0, .size = 56, .code = (const uint32_t []) {
+	{ .gen_ver = 0, .size = 60, .code = (const uint32_t []) {
 		0x80040061, 0x04054220, 0x00000000, 0x00000000,
-		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
-		0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
+		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
+		0x80000040, 0x04058220, 0x02000024, 0xc0ded001,
+		0x80000169, 0x04058220, 0x02000404, 0xc0ded000,
 		0x80000061, 0x04250220, 0x000000c4, 0x00000000,
-		0x80000140, 0x04258220, 0x02000424, 0xc0ded001,
-		0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
+		0x80000140, 0x04258220, 0x02000424, 0xc0ded002,
+		0x80000061, 0x04454220, 0x00000000, 0xc0ded003,
 		0x80000061, 0x04850220, 0x000000a4, 0x00000000,
-		0x80000165, 0x03058220, 0x02008020, 0xc0ded004,
+		0x80000165, 0x03058220, 0x02008020, 0xc0ded005,
 		0x80000161, 0x30014220, 0x00000000, 0x00000000,
-		0x80000270, 0x00018220, 0x12000304, 0xc0ded005,
+		0x80000270, 0x00018220, 0x12000304, 0xc0ded006,
 		0x8104a031, 0x00000000, 0xc0000414, 0x02a00000,
 		0x80000001, 0x00010000, 0x20000000, 0x00000000,
 		0x80000001, 0x00010000, 0x30000000, 0x00000000,
diff --git a/tests/intel/xe_exec_sip.c b/tests/intel/xe_exec_sip.c
index ee4787d61..ed27d9c32 100644
--- a/tests/intel/xe_exec_sip.c
+++ b/tests/intel/xe_exec_sip.c
@@ -93,14 +93,14 @@ static struct gpgpu_shader *get_shader(int fd, enum shader_type shader_type)
 	case SHADER_INV_INSTR_DISABLED:
 	case SHADER_INV_INSTR_WALKER_ENABLED:
 		bad = (shader_type == SHADER_INV_INSTR_DISABLED) ? ILLEGAL_OPCODE_ENABLE : 0;
-		gpgpu_shader__write_on_exception(shader, 1, 0, ILLEGAL_OPCODE_ENABLE, bad);
+		gpgpu_shader__write_on_exception(shader, 1, 0, 0, ILLEGAL_OPCODE_ENABLE, bad);
 		gpgpu_shader__nop(shader);
 		gpgpu_shader__nop(shader);
 		/* modify second nop, set only opcode bits[6:0] */
 		shader->instr[gpgpu_shader_last_instr(shader)][0] = 0x7f;
 		/* SIP should clear exception bit */
 		bad = ILLEGAL_OPCODE_STATUS;
-		gpgpu_shader__write_on_exception(shader, 2, 0, ILLEGAL_OPCODE_STATUS, bad);
+		gpgpu_shader__write_on_exception(shader, 2, 0, 0, ILLEGAL_OPCODE_STATUS, bad);
 		break;
 	}
 
@@ -120,7 +120,7 @@ static struct gpgpu_shader *get_sip(int fd, enum sip_type sip_type, unsigned int
 
 	switch (sip_type) {
 	case SIP_INV_INSTR:
-		gpgpu_shader__write_on_exception(sip, 1, y_offset, ILLEGAL_OPCODE_STATUS, 0);
+		gpgpu_shader__write_on_exception(sip, 1, 0, y_offset, ILLEGAL_OPCODE_STATUS, 0);
 		break;
 	default:
 		break;
-- 
2.34.1

Re: [PATCH i-g-t 1/2] lib/gpgpu_shader: Add x_offset parameter for gpgpu_shader__write_on_exception

[Zbigniew Kempczyński]

On Wed, Sep 25, 2024 at 03:30:02PM +0200, Christoph Manszewski wrote:
> Currently gpgpu_shader__write_on_exception always writes the first
> column equal to thread group ID x. Make it possible to specify an offset
> from that value.
> 
> Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  lib/gpgpu_shader.c          | 29 +++++++-------
>  lib/gpgpu_shader.h          |  4 +-
>  lib/iga64_generated_codes.c | 77 ++++++++++++++++++++-----------------
>  tests/intel/xe_exec_sip.c   |  6 +--
>  4 files changed, 62 insertions(+), 54 deletions(-)
> 
> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
> index 6d8c7ebb8..8df8d9612 100644
> --- a/lib/gpgpu_shader.c
> +++ b/lib/gpgpu_shader.c
> @@ -670,6 +670,7 @@ void gpgpu_shader__set_exception(struct gpgpu_shader *shdr, uint32_t value)
>   * gpgpu_shader__write_on_exception:
>   * @shdr: shader to be modified
>   * @value: dword to be written
> + * @x_offset: write target offset within the surface in columns added to the 'thread group id x'
>   * @y_offset: write target offset within the surface in rows
>   * @mask: mask to be applied on exception register
>   * @expected: expected value of exception register with @mask applied
> @@ -678,45 +679,47 @@ void gpgpu_shader__set_exception(struct gpgpu_shader *shdr, uint32_t value)
>   * to provided ones: cr0.1 & @mask == @expected,
>   * if yes fill dword in (row, column/dword) == (tg_id_y + @y_offset, tg_id_x).

tg_id_x + @x_offset

>   */
> -void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t value,
> +void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t value, uint32_t x_offset,
>  				      uint32_t y_offset, uint32_t mask, uint32_t expected)
>  {
>  	emit_iga64_code(shdr, write_on_exception, "					\n\
>  	// Clear message header								\n\
>  (W)	mov (16|M0)              r4.0<1>:ud    0x0:ud					\n\
>  	// Payload									\n\
> -(W)	mov (1|M0)               r5.0<1>:ud    ARG(3):ud				\n\
> +(W)	mov (1|M0)               r5.0<1>:ud    ARG(4):ud				\n\
>  #if GEN_VER < 2000 // prepare Media Block Write						\n\
>  	// X offset of the block in bytes := (thread group id X << ARG(0))		\n\
> -(W)	shl (1|M0)               r4.0<1>:ud    r0.1<0;1,0>:ud    ARG(0):ud		\n\
> +(W)	add (1|M0)               r4.0<1>:ud    r0.1<0;1,0>:ud	 ARG(1):ud		\n\
> +(W)	shl (1|M0)               r4.0<1>:ud    r4.0<0;1,0>:ud    ARG(0):ud		\n\
>  	// Y offset of the block in rows := thread group id Y				\n\
>  (W)	mov (1|M0)               r4.1<1>:ud    r0.6<0;1,0>:ud				\n\
> -(W)	add (1|M0)               r4.1<1>:ud    r4.1<0;1,0>:ud   ARG(1):ud		\n\
> +(W)	add (1|M0)               r4.1<1>:ud    r4.1<0;1,0>:ud   ARG(2):ud		\n\

You may drop mov and below should be enough:

	add (1|M0)               r4.1<1>:ud    r0.6<0;1,0>:ud    ARG(2):ud

>  	// block width [0,63] representing 1 to 64 bytes				\n\
> -(W)	mov (1|M0)               r4.2<1>:ud    ARG(2):ud				\n\
> +(W)	mov (1|M0)               r4.2<1>:ud    ARG(3):ud				\n\
>  	// FFTID := FFTID from R0 header						\n\
>  (W)	mov (1|M0)               r4.4<1>:ud    r0.5<0;1,0>:ud				\n\
>  #else // prepare Typed 2D Block Store							\n\
> -	// Load r2.0-3 with tg id X << ARG(0)						\n\
> -(W)	shl (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud    ARG(0):ud		\n\
> -	// Load r2.4-7 with tg id Y + ARG(1):ud						\n\
> +	// Load r2.0 with tg id (X + ARG(1)) << ARG(0)					\n\
> +(W)	add (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud	 ARG(1):ud		\n\
> +(W)	shl (1|M0)               r2.0<1>:ud    r2.0<0;1,0>:ud    ARG(0):ud		\n\
> +	// Load r2.4-7 with tg id Y + ARG(2):ud						\n\
>  (W)	mov (1|M0)               r2.1<1>:ud    r0.6<0;1,0>:ud				\n\
> -(W)	add (1|M0)               r2.1<1>:ud    r2.1<0;1,0>:ud    ARG(1):ud		\n\
> +(W)	add (1|M0)               r2.1<1>:ud    r2.1<0;1,0>:ud    ARG(2):ud		\n\

Same here.

>  	// Store X and Y block start (160:191 and 192:223)				\n\
>  (W)	mov (2|M0)               r4.5<1>:ud    r2.0<2;2,1>:ud				\n\
>  	// Store X and Y block max_size (224:231 and 232:239)				\n\
> -(W)	mov (1|M0)               r4.7<1>:ud    ARG(2):ud				\n\
> +(W)	mov (1|M0)               r4.7<1>:ud    ARG(3):ud				\n\
>  #endif											\n\
>  	// Check if masked exception is equal to provided value and write conditionally \n\
> -(W)      and (1|M0)              r3.0<1>:ud     cr0.1<0;1,0>:ud ARG(4):ud		\n\
> +(W)      and (1|M0)              r3.0<1>:ud     cr0.1<0;1,0>:ud ARG(5):ud		\n\
>  (W)      mov (1|M0)              f0.0<1>:ud     0x0:ud					\n\
> -(W)      cmp (1|M0)     (eq)f0.0 null:ud        r3.0<0;1,0>:ud  ARG(5):ud		\n\
> +(W)      cmp (1|M0)     (eq)f0.0 null:ud        r3.0<0;1,0>:ud  ARG(6):ud		\n\

Adding argument in the middle of the list makes a lot of noise in ARG(x)
changing. What a pity we don't have possibility of making definitions
like:

#define x_offset ARG(1)
#define y_offset ARG(2)

in the code. Changing definitions would keep code clear.

But that was my lousy thought, patch looks correct to me.
Feel free to incorporate my suggestions or not:

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

>  #if GEN_VER < 2000 // Media Block Write							\n\
>  (W&f0.0) send.dc1 (16|M0)        null     r4   src1_null 0    0x40A8000			\n\
>  #else // Typed 2D Block Store								\n\
>  (W&f0.0) send.tgm (16|M0)        null     r4   null:0    0    0x64000007		\n\
>  #endif											\n\
> -	", 2, y_offset, 3, value, mask, expected);
> +	", 2, x_offset, y_offset, 3, value, mask, expected);
>  }
>  
>  /**
> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
> index 53fe2869e..5f6260fb3 100644
> --- a/lib/gpgpu_shader.h
> +++ b/lib/gpgpu_shader.h
> @@ -82,8 +82,8 @@ void gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
>  void gpgpu_shader__write_aip(struct gpgpu_shader *shdr, uint32_t y_offset);
>  void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
>  			       uint32_t y_offset);
> -void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw,
> -			       uint32_t y_offset, uint32_t mask, uint32_t value);
> +void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
> +				      uint32_t y_offset, uint32_t mask, uint32_t value);
>  void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
>  void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
>  void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
> index fe6d68b70..91adc7313 100644
> --- a/lib/iga64_generated_codes.c
> +++ b/lib/iga64_generated_codes.c
> @@ -3,7 +3,7 @@
>  
>  #include "gpgpu_shader.h"
>  
> -#define MD5_SUM_IGA64_ASMS aa5c79b36f48404f1da21d2316e9f9f3
> +#define MD5_SUM_IGA64_ASMS a1dfb701367264e53d0d33f53d8769e3
>  
>  struct iga64_template const iga64_code_gpgpu_fill[] = {
>  	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> @@ -193,83 +193,88 @@ struct iga64_template const iga64_code_breakpoint_suppress[] = {
>  };
>  
>  struct iga64_template const iga64_code_write_on_exception[] = {
> -	{ .gen_ver = 2000, .size = 56, .code = (const uint32_t []) {
> +	{ .gen_ver = 2000, .size = 60, .code = (const uint32_t []) {
>  		0x80100061, 0x04054220, 0x00000000, 0x00000000,
> -		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
> -		0x80000069, 0x02058220, 0x02000014, 0xc0ded000,
> +		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
> +		0x80000040, 0x02058220, 0x02000014, 0xc0ded001,
> +		0x80001969, 0x02058220, 0x02000204, 0xc0ded000,
>  		0x80000061, 0x02150220, 0x00000064, 0x00000000,
> -		0x80001940, 0x02158220, 0x02000214, 0xc0ded001,
> +		0x80001940, 0x02158220, 0x02000214, 0xc0ded002,
>  		0x80041961, 0x04550220, 0x00220205, 0x00000000,
> -		0x80000061, 0x04754220, 0x00000000, 0xc0ded002,
> -		0x80000965, 0x03058220, 0x02008010, 0xc0ded004,
> +		0x80000061, 0x04754220, 0x00000000, 0xc0ded003,
> +		0x80000965, 0x03058220, 0x02008010, 0xc0ded005,
>  		0x80000961, 0x30014220, 0x00000000, 0x00000000,
> -		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
> +		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
>  		0x84134031, 0x00000000, 0xd00e0494, 0x04000000,
>  		0x80000001, 0x00010000, 0x20000000, 0x00000000,
>  		0x80000001, 0x00010000, 0x30000000, 0x00000000,
>  		0x80000901, 0x00010000, 0x00000000, 0x00000000,
>  	}},
> -	{ .gen_ver = 1270, .size = 60, .code = (const uint32_t []) {
> +	{ .gen_ver = 1270, .size = 64, .code = (const uint32_t []) {
>  		0x80040061, 0x04054220, 0x00000000, 0x00000000,
> -		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
> -		0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
> +		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
> +		0x80000040, 0x04058220, 0x02000024, 0xc0ded001,
> +		0x80001969, 0x04058220, 0x02000404, 0xc0ded000,
>  		0x80000061, 0x04250220, 0x000000c4, 0x00000000,
> -		0x80001940, 0x04258220, 0x02000424, 0xc0ded001,
> -		0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
> +		0x80001940, 0x04258220, 0x02000424, 0xc0ded002,
> +		0x80000061, 0x04454220, 0x00000000, 0xc0ded003,
>  		0x80000061, 0x04850220, 0x000000a4, 0x00000000,
> -		0x80000965, 0x03058220, 0x02008020, 0xc0ded004,
> +		0x80000965, 0x03058220, 0x02008020, 0xc0ded005,
>  		0x80000961, 0x30014220, 0x00000000, 0x00000000,
> -		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
> +		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
>  		0x80001a01, 0x00010000, 0x00000000, 0x00000000,
>  		0x81044031, 0x00000000, 0xc0000414, 0x02a00000,
>  		0x80000001, 0x00010000, 0x20000000, 0x00000000,
>  		0x80000001, 0x00010000, 0x30000000, 0x00000000,
>  		0x80000901, 0x00010000, 0x00000000, 0x00000000,
>  	}},
> -	{ .gen_ver = 1260, .size = 56, .code = (const uint32_t []) {
> +	{ .gen_ver = 1260, .size = 60, .code = (const uint32_t []) {
>  		0x80100061, 0x04054220, 0x00000000, 0x00000000,
> -		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
> -		0x80000069, 0x04058220, 0x02000014, 0xc0ded000,
> +		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
> +		0x80000040, 0x04058220, 0x02000014, 0xc0ded001,
> +		0x80001969, 0x04058220, 0x02000404, 0xc0ded000,
>  		0x80000061, 0x04150220, 0x00000064, 0x00000000,
> -		0x80001940, 0x04158220, 0x02000414, 0xc0ded001,
> -		0x80000061, 0x04254220, 0x00000000, 0xc0ded002,
> +		0x80001940, 0x04158220, 0x02000414, 0xc0ded002,
> +		0x80000061, 0x04254220, 0x00000000, 0xc0ded003,
>  		0x80000061, 0x04450220, 0x00000054, 0x00000000,
> -		0x80000965, 0x03058220, 0x02008010, 0xc0ded004,
> +		0x80000965, 0x03058220, 0x02008010, 0xc0ded005,
>  		0x80000961, 0x30014220, 0x00000000, 0x00000000,
> -		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
> +		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
>  		0x84134031, 0x00000000, 0xc0000414, 0x02a00000,
>  		0x80000001, 0x00010000, 0x20000000, 0x00000000,
>  		0x80000001, 0x00010000, 0x30000000, 0x00000000,
>  		0x80000901, 0x00010000, 0x00000000, 0x00000000,
>  	}},
> -	{ .gen_ver = 1250, .size = 60, .code = (const uint32_t []) {
> +	{ .gen_ver = 1250, .size = 64, .code = (const uint32_t []) {
>  		0x80040061, 0x04054220, 0x00000000, 0x00000000,
> -		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
> -		0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
> +		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
> +		0x80000040, 0x04058220, 0x02000024, 0xc0ded001,
> +		0x80001969, 0x04058220, 0x02000404, 0xc0ded000,
>  		0x80000061, 0x04250220, 0x000000c4, 0x00000000,
> -		0x80001940, 0x04258220, 0x02000424, 0xc0ded001,
> -		0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
> +		0x80001940, 0x04258220, 0x02000424, 0xc0ded002,
> +		0x80000061, 0x04454220, 0x00000000, 0xc0ded003,
>  		0x80000061, 0x04850220, 0x000000a4, 0x00000000,
> -		0x80000965, 0x03058220, 0x02008020, 0xc0ded004,
> +		0x80000965, 0x03058220, 0x02008020, 0xc0ded005,
>  		0x80000961, 0x30014220, 0x00000000, 0x00000000,
> -		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
> +		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
>  		0x80001a01, 0x00010000, 0x00000000, 0x00000000,
>  		0x81044031, 0x00000000, 0xc0000414, 0x02a00000,
>  		0x80000001, 0x00010000, 0x20000000, 0x00000000,
>  		0x80000001, 0x00010000, 0x30000000, 0x00000000,
>  		0x80000901, 0x00010000, 0x00000000, 0x00000000,
>  	}},
> -	{ .gen_ver = 0, .size = 56, .code = (const uint32_t []) {
> +	{ .gen_ver = 0, .size = 60, .code = (const uint32_t []) {
>  		0x80040061, 0x04054220, 0x00000000, 0x00000000,
> -		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
> -		0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
> +		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
> +		0x80000040, 0x04058220, 0x02000024, 0xc0ded001,
> +		0x80000169, 0x04058220, 0x02000404, 0xc0ded000,
>  		0x80000061, 0x04250220, 0x000000c4, 0x00000000,
> -		0x80000140, 0x04258220, 0x02000424, 0xc0ded001,
> -		0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
> +		0x80000140, 0x04258220, 0x02000424, 0xc0ded002,
> +		0x80000061, 0x04454220, 0x00000000, 0xc0ded003,
>  		0x80000061, 0x04850220, 0x000000a4, 0x00000000,
> -		0x80000165, 0x03058220, 0x02008020, 0xc0ded004,
> +		0x80000165, 0x03058220, 0x02008020, 0xc0ded005,
>  		0x80000161, 0x30014220, 0x00000000, 0x00000000,
> -		0x80000270, 0x00018220, 0x12000304, 0xc0ded005,
> +		0x80000270, 0x00018220, 0x12000304, 0xc0ded006,
>  		0x8104a031, 0x00000000, 0xc0000414, 0x02a00000,
>  		0x80000001, 0x00010000, 0x20000000, 0x00000000,
>  		0x80000001, 0x00010000, 0x30000000, 0x00000000,
> diff --git a/tests/intel/xe_exec_sip.c b/tests/intel/xe_exec_sip.c
> index ee4787d61..ed27d9c32 100644
> --- a/tests/intel/xe_exec_sip.c
> +++ b/tests/intel/xe_exec_sip.c
> @@ -93,14 +93,14 @@ static struct gpgpu_shader *get_shader(int fd, enum shader_type shader_type)
>  	case SHADER_INV_INSTR_DISABLED:
>  	case SHADER_INV_INSTR_WALKER_ENABLED:
>  		bad = (shader_type == SHADER_INV_INSTR_DISABLED) ? ILLEGAL_OPCODE_ENABLE : 0;
> -		gpgpu_shader__write_on_exception(shader, 1, 0, ILLEGAL_OPCODE_ENABLE, bad);
> +		gpgpu_shader__write_on_exception(shader, 1, 0, 0, ILLEGAL_OPCODE_ENABLE, bad);
>  		gpgpu_shader__nop(shader);
>  		gpgpu_shader__nop(shader);
>  		/* modify second nop, set only opcode bits[6:0] */
>  		shader->instr[gpgpu_shader_last_instr(shader)][0] = 0x7f;
>  		/* SIP should clear exception bit */
>  		bad = ILLEGAL_OPCODE_STATUS;
> -		gpgpu_shader__write_on_exception(shader, 2, 0, ILLEGAL_OPCODE_STATUS, bad);
> +		gpgpu_shader__write_on_exception(shader, 2, 0, 0, ILLEGAL_OPCODE_STATUS, bad);
>  		break;
>  	}
>  
> @@ -120,7 +120,7 @@ static struct gpgpu_shader *get_sip(int fd, enum sip_type sip_type, unsigned int
>  
>  	switch (sip_type) {
>  	case SIP_INV_INSTR:
> -		gpgpu_shader__write_on_exception(sip, 1, y_offset, ILLEGAL_OPCODE_STATUS, 0);
> +		gpgpu_shader__write_on_exception(sip, 1, 0, y_offset, ILLEGAL_OPCODE_STATUS, 0);
>  		break;
>  	default:
>  		break;
> -- 
> 2.34.1
> 

Re: [PATCH i-g-t 1/2] lib/gpgpu_shader: Add x_offset parameter for gpgpu_shader__write_on_exception

[Manszewski, Christoph]

Hi Zbigniew,

On 1.10.2024 17:07, Zbigniew Kempczyński wrote:
> On Wed, Sep 25, 2024 at 03:30:02PM +0200, Christoph Manszewski wrote:
>> Currently gpgpu_shader__write_on_exception always writes the first
>> column equal to thread group ID x. Make it possible to specify an offset
>> from that value.
>>
>> Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
>> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>> ---
>>   lib/gpgpu_shader.c          | 29 +++++++-------
>>   lib/gpgpu_shader.h          |  4 +-
>>   lib/iga64_generated_codes.c | 77 ++++++++++++++++++++-----------------
>>   tests/intel/xe_exec_sip.c   |  6 +--
>>   4 files changed, 62 insertions(+), 54 deletions(-)
>>
>> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
>> index 6d8c7ebb8..8df8d9612 100644
>> --- a/lib/gpgpu_shader.c
>> +++ b/lib/gpgpu_shader.c
>> @@ -670,6 +670,7 @@ void gpgpu_shader__set_exception(struct gpgpu_shader *shdr, uint32_t value)
>>    * gpgpu_shader__write_on_exception:
>>    * @shdr: shader to be modified
>>    * @value: dword to be written
>> + * @x_offset: write target offset within the surface in columns added to the 'thread group id x'
>>    * @y_offset: write target offset within the surface in rows
>>    * @mask: mask to be applied on exception register
>>    * @expected: expected value of exception register with @mask applied
>> @@ -678,45 +679,47 @@ void gpgpu_shader__set_exception(struct gpgpu_shader *shdr, uint32_t value)
>>    * to provided ones: cr0.1 & @mask == @expected,
>>    * if yes fill dword in (row, column/dword) == (tg_id_y + @y_offset, tg_id_x).
> 
> tg_id_x + @x_offset

Sure, nice catch!

> 
>>    */
>> -void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t value,
>> +void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t value, uint32_t x_offset,
>>   				      uint32_t y_offset, uint32_t mask, uint32_t expected)
>>   {
>>   	emit_iga64_code(shdr, write_on_exception, "					\n\
>>   	// Clear message header								\n\
>>   (W)	mov (16|M0)              r4.0<1>:ud    0x0:ud					\n\
>>   	// Payload									\n\
>> -(W)	mov (1|M0)               r5.0<1>:ud    ARG(3):ud				\n\
>> +(W)	mov (1|M0)               r5.0<1>:ud    ARG(4):ud				\n\
>>   #if GEN_VER < 2000 // prepare Media Block Write						\n\
>>   	// X offset of the block in bytes := (thread group id X << ARG(0))		\n\
>> -(W)	shl (1|M0)               r4.0<1>:ud    r0.1<0;1,0>:ud    ARG(0):ud		\n\
>> +(W)	add (1|M0)               r4.0<1>:ud    r0.1<0;1,0>:ud	 ARG(1):ud		\n\
>> +(W)	shl (1|M0)               r4.0<1>:ud    r4.0<0;1,0>:ud    ARG(0):ud		\n\
>>   	// Y offset of the block in rows := thread group id Y				\n\
>>   (W)	mov (1|M0)               r4.1<1>:ud    r0.6<0;1,0>:ud				\n\
>> -(W)	add (1|M0)               r4.1<1>:ud    r4.1<0;1,0>:ud   ARG(1):ud		\n\
>> +(W)	add (1|M0)               r4.1<1>:ud    r4.1<0;1,0>:ud   ARG(2):ud		\n\
> 
> You may drop mov and below should be enough:
> 
> 	add (1|M0)               r4.1<1>:ud    r0.6<0;1,0>:ud    ARG(2):ud

Ok, makes sense.

> 
>>   	// block width [0,63] representing 1 to 64 bytes				\n\
>> -(W)	mov (1|M0)               r4.2<1>:ud    ARG(2):ud				\n\
>> +(W)	mov (1|M0)               r4.2<1>:ud    ARG(3):ud				\n\
>>   	// FFTID := FFTID from R0 header						\n\
>>   (W)	mov (1|M0)               r4.4<1>:ud    r0.5<0;1,0>:ud				\n\
>>   #else // prepare Typed 2D Block Store							\n\
>> -	// Load r2.0-3 with tg id X << ARG(0)						\n\
>> -(W)	shl (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud    ARG(0):ud		\n\
>> -	// Load r2.4-7 with tg id Y + ARG(1):ud						\n\
>> +	// Load r2.0 with tg id (X + ARG(1)) << ARG(0)					\n\
>> +(W)	add (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud	 ARG(1):ud		\n\
>> +(W)	shl (1|M0)               r2.0<1>:ud    r2.0<0;1,0>:ud    ARG(0):ud		\n\
>> +	// Load r2.4-7 with tg id Y + ARG(2):ud						\n\
>>   (W)	mov (1|M0)               r2.1<1>:ud    r0.6<0;1,0>:ud				\n\
>> -(W)	add (1|M0)               r2.1<1>:ud    r2.1<0;1,0>:ud    ARG(1):ud		\n\
>> +(W)	add (1|M0)               r2.1<1>:ud    r2.1<0;1,0>:ud    ARG(2):ud		\n\
> 
> Same here.

Ok

> 
>>   	// Store X and Y block start (160:191 and 192:223)				\n\
>>   (W)	mov (2|M0)               r4.5<1>:ud    r2.0<2;2,1>:ud				\n\
>>   	// Store X and Y block max_size (224:231 and 232:239)				\n\
>> -(W)	mov (1|M0)               r4.7<1>:ud    ARG(2):ud				\n\
>> +(W)	mov (1|M0)               r4.7<1>:ud    ARG(3):ud				\n\
>>   #endif											\n\
>>   	// Check if masked exception is equal to provided value and write conditionally \n\
>> -(W)      and (1|M0)              r3.0<1>:ud     cr0.1<0;1,0>:ud ARG(4):ud		\n\
>> +(W)      and (1|M0)              r3.0<1>:ud     cr0.1<0;1,0>:ud ARG(5):ud		\n\
>>   (W)      mov (1|M0)              f0.0<1>:ud     0x0:ud					\n\
>> -(W)      cmp (1|M0)     (eq)f0.0 null:ud        r3.0<0;1,0>:ud  ARG(5):ud		\n\
>> +(W)      cmp (1|M0)     (eq)f0.0 null:ud        r3.0<0;1,0>:ud  ARG(6):ud		\n\
> 
> Adding argument in the middle of the list makes a lot of noise in ARG(x)
> changing. What a pity we don't have possibility of making definitions
> like:
> 
> #define x_offset ARG(1)
> #define y_offset ARG(2)
> 
> in the code. Changing definitions would keep code clear.
> 
> But that was my lousy thought, patch looks correct to me.
> Feel free to incorporate my suggestions or not:
> 
> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Thanks,
Christoph

> 
> --
> Zbigniew
> 
>>   #if GEN_VER < 2000 // Media Block Write							\n\
>>   (W&f0.0) send.dc1 (16|M0)        null     r4   src1_null 0    0x40A8000			\n\
>>   #else // Typed 2D Block Store								\n\
>>   (W&f0.0) send.tgm (16|M0)        null     r4   null:0    0    0x64000007		\n\
>>   #endif											\n\
>> -	", 2, y_offset, 3, value, mask, expected);
>> +	", 2, x_offset, y_offset, 3, value, mask, expected);
>>   }
>>   
>>   /**
>> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
>> index 53fe2869e..5f6260fb3 100644
>> --- a/lib/gpgpu_shader.h
>> +++ b/lib/gpgpu_shader.h
>> @@ -82,8 +82,8 @@ void gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
>>   void gpgpu_shader__write_aip(struct gpgpu_shader *shdr, uint32_t y_offset);
>>   void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
>>   			       uint32_t y_offset);
>> -void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw,
>> -			       uint32_t y_offset, uint32_t mask, uint32_t value);
>> +void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
>> +				      uint32_t y_offset, uint32_t mask, uint32_t value);
>>   void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
>>   void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
>>   void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
>> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
>> index fe6d68b70..91adc7313 100644
>> --- a/lib/iga64_generated_codes.c
>> +++ b/lib/iga64_generated_codes.c
>> @@ -3,7 +3,7 @@
>>   
>>   #include "gpgpu_shader.h"
>>   
>> -#define MD5_SUM_IGA64_ASMS aa5c79b36f48404f1da21d2316e9f9f3
>> +#define MD5_SUM_IGA64_ASMS a1dfb701367264e53d0d33f53d8769e3
>>   
>>   struct iga64_template const iga64_code_gpgpu_fill[] = {
>>   	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> @@ -193,83 +193,88 @@ struct iga64_template const iga64_code_breakpoint_suppress[] = {
>>   };
>>   
>>   struct iga64_template const iga64_code_write_on_exception[] = {
>> -	{ .gen_ver = 2000, .size = 56, .code = (const uint32_t []) {
>> +	{ .gen_ver = 2000, .size = 60, .code = (const uint32_t []) {
>>   		0x80100061, 0x04054220, 0x00000000, 0x00000000,
>> -		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
>> -		0x80000069, 0x02058220, 0x02000014, 0xc0ded000,
>> +		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
>> +		0x80000040, 0x02058220, 0x02000014, 0xc0ded001,
>> +		0x80001969, 0x02058220, 0x02000204, 0xc0ded000,
>>   		0x80000061, 0x02150220, 0x00000064, 0x00000000,
>> -		0x80001940, 0x02158220, 0x02000214, 0xc0ded001,
>> +		0x80001940, 0x02158220, 0x02000214, 0xc0ded002,
>>   		0x80041961, 0x04550220, 0x00220205, 0x00000000,
>> -		0x80000061, 0x04754220, 0x00000000, 0xc0ded002,
>> -		0x80000965, 0x03058220, 0x02008010, 0xc0ded004,
>> +		0x80000061, 0x04754220, 0x00000000, 0xc0ded003,
>> +		0x80000965, 0x03058220, 0x02008010, 0xc0ded005,
>>   		0x80000961, 0x30014220, 0x00000000, 0x00000000,
>> -		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
>> +		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
>>   		0x84134031, 0x00000000, 0xd00e0494, 0x04000000,
>>   		0x80000001, 0x00010000, 0x20000000, 0x00000000,
>>   		0x80000001, 0x00010000, 0x30000000, 0x00000000,
>>   		0x80000901, 0x00010000, 0x00000000, 0x00000000,
>>   	}},
>> -	{ .gen_ver = 1270, .size = 60, .code = (const uint32_t []) {
>> +	{ .gen_ver = 1270, .size = 64, .code = (const uint32_t []) {
>>   		0x80040061, 0x04054220, 0x00000000, 0x00000000,
>> -		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
>> -		0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
>> +		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
>> +		0x80000040, 0x04058220, 0x02000024, 0xc0ded001,
>> +		0x80001969, 0x04058220, 0x02000404, 0xc0ded000,
>>   		0x80000061, 0x04250220, 0x000000c4, 0x00000000,
>> -		0x80001940, 0x04258220, 0x02000424, 0xc0ded001,
>> -		0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
>> +		0x80001940, 0x04258220, 0x02000424, 0xc0ded002,
>> +		0x80000061, 0x04454220, 0x00000000, 0xc0ded003,
>>   		0x80000061, 0x04850220, 0x000000a4, 0x00000000,
>> -		0x80000965, 0x03058220, 0x02008020, 0xc0ded004,
>> +		0x80000965, 0x03058220, 0x02008020, 0xc0ded005,
>>   		0x80000961, 0x30014220, 0x00000000, 0x00000000,
>> -		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
>> +		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
>>   		0x80001a01, 0x00010000, 0x00000000, 0x00000000,
>>   		0x81044031, 0x00000000, 0xc0000414, 0x02a00000,
>>   		0x80000001, 0x00010000, 0x20000000, 0x00000000,
>>   		0x80000001, 0x00010000, 0x30000000, 0x00000000,
>>   		0x80000901, 0x00010000, 0x00000000, 0x00000000,
>>   	}},
>> -	{ .gen_ver = 1260, .size = 56, .code = (const uint32_t []) {
>> +	{ .gen_ver = 1260, .size = 60, .code = (const uint32_t []) {
>>   		0x80100061, 0x04054220, 0x00000000, 0x00000000,
>> -		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
>> -		0x80000069, 0x04058220, 0x02000014, 0xc0ded000,
>> +		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
>> +		0x80000040, 0x04058220, 0x02000014, 0xc0ded001,
>> +		0x80001969, 0x04058220, 0x02000404, 0xc0ded000,
>>   		0x80000061, 0x04150220, 0x00000064, 0x00000000,
>> -		0x80001940, 0x04158220, 0x02000414, 0xc0ded001,
>> -		0x80000061, 0x04254220, 0x00000000, 0xc0ded002,
>> +		0x80001940, 0x04158220, 0x02000414, 0xc0ded002,
>> +		0x80000061, 0x04254220, 0x00000000, 0xc0ded003,
>>   		0x80000061, 0x04450220, 0x00000054, 0x00000000,
>> -		0x80000965, 0x03058220, 0x02008010, 0xc0ded004,
>> +		0x80000965, 0x03058220, 0x02008010, 0xc0ded005,
>>   		0x80000961, 0x30014220, 0x00000000, 0x00000000,
>> -		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
>> +		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
>>   		0x84134031, 0x00000000, 0xc0000414, 0x02a00000,
>>   		0x80000001, 0x00010000, 0x20000000, 0x00000000,
>>   		0x80000001, 0x00010000, 0x30000000, 0x00000000,
>>   		0x80000901, 0x00010000, 0x00000000, 0x00000000,
>>   	}},
>> -	{ .gen_ver = 1250, .size = 60, .code = (const uint32_t []) {
>> +	{ .gen_ver = 1250, .size = 64, .code = (const uint32_t []) {
>>   		0x80040061, 0x04054220, 0x00000000, 0x00000000,
>> -		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
>> -		0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
>> +		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
>> +		0x80000040, 0x04058220, 0x02000024, 0xc0ded001,
>> +		0x80001969, 0x04058220, 0x02000404, 0xc0ded000,
>>   		0x80000061, 0x04250220, 0x000000c4, 0x00000000,
>> -		0x80001940, 0x04258220, 0x02000424, 0xc0ded001,
>> -		0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
>> +		0x80001940, 0x04258220, 0x02000424, 0xc0ded002,
>> +		0x80000061, 0x04454220, 0x00000000, 0xc0ded003,
>>   		0x80000061, 0x04850220, 0x000000a4, 0x00000000,
>> -		0x80000965, 0x03058220, 0x02008020, 0xc0ded004,
>> +		0x80000965, 0x03058220, 0x02008020, 0xc0ded005,
>>   		0x80000961, 0x30014220, 0x00000000, 0x00000000,
>> -		0x80001a70, 0x00018220, 0x12000304, 0xc0ded005,
>> +		0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
>>   		0x80001a01, 0x00010000, 0x00000000, 0x00000000,
>>   		0x81044031, 0x00000000, 0xc0000414, 0x02a00000,
>>   		0x80000001, 0x00010000, 0x20000000, 0x00000000,
>>   		0x80000001, 0x00010000, 0x30000000, 0x00000000,
>>   		0x80000901, 0x00010000, 0x00000000, 0x00000000,
>>   	}},
>> -	{ .gen_ver = 0, .size = 56, .code = (const uint32_t []) {
>> +	{ .gen_ver = 0, .size = 60, .code = (const uint32_t []) {
>>   		0x80040061, 0x04054220, 0x00000000, 0x00000000,
>> -		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
>> -		0x80000069, 0x04058220, 0x02000024, 0xc0ded000,
>> +		0x80000061, 0x05054220, 0x00000000, 0xc0ded004,
>> +		0x80000040, 0x04058220, 0x02000024, 0xc0ded001,
>> +		0x80000169, 0x04058220, 0x02000404, 0xc0ded000,
>>   		0x80000061, 0x04250220, 0x000000c4, 0x00000000,
>> -		0x80000140, 0x04258220, 0x02000424, 0xc0ded001,
>> -		0x80000061, 0x04454220, 0x00000000, 0xc0ded002,
>> +		0x80000140, 0x04258220, 0x02000424, 0xc0ded002,
>> +		0x80000061, 0x04454220, 0x00000000, 0xc0ded003,
>>   		0x80000061, 0x04850220, 0x000000a4, 0x00000000,
>> -		0x80000165, 0x03058220, 0x02008020, 0xc0ded004,
>> +		0x80000165, 0x03058220, 0x02008020, 0xc0ded005,
>>   		0x80000161, 0x30014220, 0x00000000, 0x00000000,
>> -		0x80000270, 0x00018220, 0x12000304, 0xc0ded005,
>> +		0x80000270, 0x00018220, 0x12000304, 0xc0ded006,
>>   		0x8104a031, 0x00000000, 0xc0000414, 0x02a00000,
>>   		0x80000001, 0x00010000, 0x20000000, 0x00000000,
>>   		0x80000001, 0x00010000, 0x30000000, 0x00000000,
>> diff --git a/tests/intel/xe_exec_sip.c b/tests/intel/xe_exec_sip.c
>> index ee4787d61..ed27d9c32 100644
>> --- a/tests/intel/xe_exec_sip.c
>> +++ b/tests/intel/xe_exec_sip.c
>> @@ -93,14 +93,14 @@ static struct gpgpu_shader *get_shader(int fd, enum shader_type shader_type)
>>   	case SHADER_INV_INSTR_DISABLED:
>>   	case SHADER_INV_INSTR_WALKER_ENABLED:
>>   		bad = (shader_type == SHADER_INV_INSTR_DISABLED) ? ILLEGAL_OPCODE_ENABLE : 0;
>> -		gpgpu_shader__write_on_exception(shader, 1, 0, ILLEGAL_OPCODE_ENABLE, bad);
>> +		gpgpu_shader__write_on_exception(shader, 1, 0, 0, ILLEGAL_OPCODE_ENABLE, bad);
>>   		gpgpu_shader__nop(shader);
>>   		gpgpu_shader__nop(shader);
>>   		/* modify second nop, set only opcode bits[6:0] */
>>   		shader->instr[gpgpu_shader_last_instr(shader)][0] = 0x7f;
>>   		/* SIP should clear exception bit */
>>   		bad = ILLEGAL_OPCODE_STATUS;
>> -		gpgpu_shader__write_on_exception(shader, 2, 0, ILLEGAL_OPCODE_STATUS, bad);
>> +		gpgpu_shader__write_on_exception(shader, 2, 0, 0, ILLEGAL_OPCODE_STATUS, bad);
>>   		break;
>>   	}
>>   
>> @@ -120,7 +120,7 @@ static struct gpgpu_shader *get_sip(int fd, enum sip_type sip_type, unsigned int
>>   
>>   	switch (sip_type) {
>>   	case SIP_INV_INSTR:
>> -		gpgpu_shader__write_on_exception(sip, 1, y_offset, ILLEGAL_OPCODE_STATUS, 0);
>> +		gpgpu_shader__write_on_exception(sip, 1, 0, y_offset, ILLEGAL_OPCODE_STATUS, 0);
>>   		break;
>>   	default:
>>   		break;
>> -- 
>> 2.34.1
>>

Re: [PATCH i-g-t 1/2] lib/gpgpu_shader: Add x_offset parameter for gpgpu_shader__write_on_exception

[Hajda, Andrzej]

Somehow I missed this.

W dniu 01.10.2024 o 17:07, Zbigniew Kempczyński pisze:
> On Wed, Sep 25, 2024 at 03:30:02PM +0200, Christoph Manszewski wrote:
>> Currently gpgpu_shader__write_on_exception always writes the first
>> column equal to thread group ID x. Make it possible to specify an offset
>> from that value.
>>
>> Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
>> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>> ---
>>   lib/gpgpu_shader.c          | 29 +++++++-------
>>   lib/gpgpu_shader.h          |  4 +-
>>   lib/iga64_generated_codes.c | 77 ++++++++++++++++++++-----------------
>>   tests/intel/xe_exec_sip.c   |  6 +--
>>   4 files changed, 62 insertions(+), 54 deletions(-)
>>
>> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
>> index 6d8c7ebb8..8df8d9612 100644
>> --- a/lib/gpgpu_shader.c
>> +++ b/lib/gpgpu_shader.c
>> @@ -670,6 +670,7 @@ void gpgpu_shader__set_exception(struct gpgpu_shader *shdr, uint32_t value)
>>    * gpgpu_shader__write_on_exception:
>>    * @shdr: shader to be modified
>>    * @value: dword to be written
>> + * @x_offset: write target offset within the surface in columns added to the 'thread group id x'
>>    * @y_offset: write target offset within the surface in rows
>>    * @mask: mask to be applied on exception register
>>    * @expected: expected value of exception register with @mask applied
>> @@ -678,45 +679,47 @@ void gpgpu_shader__set_exception(struct gpgpu_shader *shdr, uint32_t value)
>>    * to provided ones: cr0.1 & @mask == @expected,
>>    * if yes fill dword in (row, column/dword) == (tg_id_y + @y_offset, tg_id_x).
> tg_id_x + @x_offset
>
>>    */
>> -void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t value,
>> +void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t value, uint32_t x_offset,
>>   				      uint32_t y_offset, uint32_t mask, uint32_t expected)
>>   {
>>   	emit_iga64_code(shdr, write_on_exception, "					\n\
>>   	// Clear message header								\n\
>>   (W)	mov (16|M0)              r4.0<1>:ud    0x0:ud					\n\
>>   	// Payload									\n\
>> -(W)	mov (1|M0)               r5.0<1>:ud    ARG(3):ud				\n\
>> +(W)	mov (1|M0)               r5.0<1>:ud    ARG(4):ud				\n\
>>   #if GEN_VER < 2000 // prepare Media Block Write						\n\
>>   	// X offset of the block in bytes := (thread group id X << ARG(0))		\n\
>> -(W)	shl (1|M0)               r4.0<1>:ud    r0.1<0;1,0>:ud    ARG(0):ud		\n\
>> +(W)	add (1|M0)               r4.0<1>:ud    r0.1<0;1,0>:ud	 ARG(1):ud		\n\
>> +(W)	shl (1|M0)               r4.0<1>:ud    r4.0<0;1,0>:ud    ARG(0):ud		\n\
>>   	// Y offset of the block in rows := thread group id Y				\n\
>>   (W)	mov (1|M0)               r4.1<1>:ud    r0.6<0;1,0>:ud				\n\
>> -(W)	add (1|M0)               r4.1<1>:ud    r4.1<0;1,0>:ud   ARG(1):ud		\n\
>> +(W)	add (1|M0)               r4.1<1>:ud    r4.1<0;1,0>:ud   ARG(2):ud		\n\
> You may drop mov and below should be enough:
>
> 	add (1|M0)               r4.1<1>:ud    r0.6<0;1,0>:ud    ARG(2):ud
>
>>   	// block width [0,63] representing 1 to 64 bytes				\n\
>> -(W)	mov (1|M0)               r4.2<1>:ud    ARG(2):ud				\n\
>> +(W)	mov (1|M0)               r4.2<1>:ud    ARG(3):ud				\n\
>>   	// FFTID := FFTID from R0 header						\n\
>>   (W)	mov (1|M0)               r4.4<1>:ud    r0.5<0;1,0>:ud				\n\
>>   #else // prepare Typed 2D Block Store							\n\
>> -	// Load r2.0-3 with tg id X << ARG(0)						\n\
>> -(W)	shl (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud    ARG(0):ud		\n\
>> -	// Load r2.4-7 with tg id Y + ARG(1):ud						\n\
>> +	// Load r2.0 with tg id (X + ARG(1)) << ARG(0)					\n\
>> +(W)	add (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud	 ARG(1):ud		\n\
>> +(W)	shl (1|M0)               r2.0<1>:ud    r2.0<0;1,0>:ud    ARG(0):ud		\n\
>> +	// Load r2.4-7 with tg id Y + ARG(2):ud						\n\
>>   (W)	mov (1|M0)               r2.1<1>:ud    r0.6<0;1,0>:ud				\n\
>> -(W)	add (1|M0)               r2.1<1>:ud    r2.1<0;1,0>:ud    ARG(1):ud		\n\
>> +(W)	add (1|M0)               r2.1<1>:ud    r2.1<0;1,0>:ud    ARG(2):ud		\n\
> Same here.
>
>>   	// Store X and Y block start (160:191 and 192:223)				\n\
>>   (W)	mov (2|M0)               r4.5<1>:ud    r2.0<2;2,1>:ud				\n\
>>   	// Store X and Y block max_size (224:231 and 232:239)				\n\
>> -(W)	mov (1|M0)               r4.7<1>:ud    ARG(2):ud				\n\
>> +(W)	mov (1|M0)               r4.7<1>:ud    ARG(3):ud				\n\
>>   #endif											\n\
>>   	// Check if masked exception is equal to provided value and write conditionally \n\
>> -(W)      and (1|M0)              r3.0<1>:ud     cr0.1<0;1,0>:ud ARG(4):ud		\n\
>> +(W)      and (1|M0)              r3.0<1>:ud     cr0.1<0;1,0>:ud ARG(5):ud		\n\
>>   (W)      mov (1|M0)              f0.0<1>:ud     0x0:ud					\n\
>> -(W)      cmp (1|M0)     (eq)f0.0 null:ud        r3.0<0;1,0>:ud  ARG(5):ud		\n\
>> +(W)      cmp (1|M0)     (eq)f0.0 null:ud        r3.0<0;1,0>:ud  ARG(6):ud		\n\
> Adding argument in the middle of the list makes a lot of noise in ARG(x)
> changing. What a pity we don't have possibility of making definitions
> like:
>
> #define x_offset ARG(1)
> #define y_offset ARG(2)
>
> in the code. Changing definitions would keep code clear.

Why not:

        emit_iga64_code(shdr, end_system_routine_step_if_eq, "   \n\

#define x_offset ARG(1)						\n\
#define y_offset ARG(2)						\n\
...
	mov (1|M0)               r30.6<1>:ud    y_offset:ud     \n\
...

Regards
Andrzej

Re: [PATCH i-g-t 1/2] lib/gpgpu_shader: Add x_offset parameter for gpgpu_shader__write_on_exception

[Zbigniew Kempczyński]

On Mon, Oct 14, 2024 at 03:49:27PM +0200, Hajda, Andrzej wrote:
> Somehow I missed this.
> 

<cut>

> > >   	// Check if masked exception is equal to provided value and write conditionally \n\
> > > -(W)      and (1|M0)              r3.0<1>:ud     cr0.1<0;1,0>:ud ARG(4):ud		\n\
> > > +(W)      and (1|M0)              r3.0<1>:ud     cr0.1<0;1,0>:ud ARG(5):ud		\n\
> > >   (W)      mov (1|M0)              f0.0<1>:ud     0x0:ud					\n\
> > > -(W)      cmp (1|M0)     (eq)f0.0 null:ud        r3.0<0;1,0>:ud  ARG(5):ud		\n\
> > > +(W)      cmp (1|M0)     (eq)f0.0 null:ud        r3.0<0;1,0>:ud  ARG(6):ud		\n\
> > Adding argument in the middle of the list makes a lot of noise in ARG(x)
> > changing. What a pity we don't have possibility of making definitions
> > like:
> > 
> > #define x_offset ARG(1)
> > #define y_offset ARG(2)
> > 
> > in the code. Changing definitions would keep code clear.
> 
> Why not:
> 
>        emit_iga64_code(shdr, end_system_routine_step_if_eq, "   \n\
> 
> #define x_offset ARG(1)						\n\
> #define y_offset ARG(2)						\n\
> ...
> 	mov (1|M0)               r30.6<1>:ud    y_offset:ud     \n\
> ...
> 

Great, I forgot this is preprocessed first. So we need to refactor
this, it will be likely quick and easy.

--
Zbigniew

> Regards
> Andrzej
> 

[PATCH i-g-t 2/2] tests/xe_exec_sip: Write on invalidinstr

[Christoph Manszewski]

Currently we use 'gpgpu_shader__write_on_exception' only in a negative
way which causes the write not happening in the default (passing) case.
Change one of the usages to positive, to ensure the expected value has
been written.

Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_exec_sip.c | 80 ++++++++++++++++++++++++---------------
 1 file changed, 49 insertions(+), 31 deletions(-)

diff --git a/tests/intel/xe_exec_sip.c b/tests/intel/xe_exec_sip.c
index ed27d9c32..2294468c2 100644
--- a/tests/intel/xe_exec_sip.c
+++ b/tests/intel/xe_exec_sip.c
@@ -27,10 +27,12 @@
 #define WIDTH 64
 #define HEIGHT 64
 
-#define COLOR_C4 0xc4
+#define COLOR_C4 0xc4c4c4c4
 
 #define SHADER_CANARY 0x01010101
-#define SIP_CANARY 0x02020202
+#define SHADER_CANARY2 0x02020202
+#define SIP_CANARY 0x03030303
+#define SIP_CANARY2 0x04040404
 
 enum shader_type {
 	SHADER_HANG,
@@ -71,7 +73,7 @@ create_fill_buf(int fd, int width, int height, uint8_t color)
 static struct gpgpu_shader *get_shader(int fd, enum shader_type shader_type)
 {
 	static struct gpgpu_shader *shader;
-	uint32_t bad;
+	uint32_t expected_cr0_bit;
 
 	shader = gpgpu_shader_create(fd);
 	if (shader_type == SHADER_INV_INSTR_WALKER_ENABLED)
@@ -92,15 +94,17 @@ static struct gpgpu_shader *get_shader(int fd, enum shader_type shader_type)
 		__attribute__ ((fallthrough));
 	case SHADER_INV_INSTR_DISABLED:
 	case SHADER_INV_INSTR_WALKER_ENABLED:
-		bad = (shader_type == SHADER_INV_INSTR_DISABLED) ? ILLEGAL_OPCODE_ENABLE : 0;
-		gpgpu_shader__write_on_exception(shader, 1, 0, 0, ILLEGAL_OPCODE_ENABLE, bad);
+		expected_cr0_bit = shader_type == SHADER_INV_INSTR_DISABLED ?
+				   0 : ILLEGAL_OPCODE_ENABLE;
+		gpgpu_shader__write_on_exception(shader, SHADER_CANARY2, 1, 0,
+						 ILLEGAL_OPCODE_ENABLE, expected_cr0_bit);
 		gpgpu_shader__nop(shader);
 		gpgpu_shader__nop(shader);
 		/* modify second nop, set only opcode bits[6:0] */
 		shader->instr[gpgpu_shader_last_instr(shader)][0] = 0x7f;
-		/* SIP should clear exception bit */
-		bad = ILLEGAL_OPCODE_STATUS;
-		gpgpu_shader__write_on_exception(shader, 2, 0, 0, ILLEGAL_OPCODE_STATUS, bad);
+		/* SIP should clear exception bit, negative check */
+		gpgpu_shader__write_on_exception(shader, SHADER_CANARY2, 0, 0,
+						 ILLEGAL_OPCODE_STATUS, ILLEGAL_OPCODE_STATUS);
 		break;
 	}
 
@@ -120,7 +124,8 @@ static struct gpgpu_shader *get_sip(int fd, enum sip_type sip_type, unsigned int
 
 	switch (sip_type) {
 	case SIP_INV_INSTR:
-		gpgpu_shader__write_on_exception(sip, 1, 0, y_offset, ILLEGAL_OPCODE_STATUS, 0);
+		gpgpu_shader__write_on_exception(sip, SIP_CANARY2, 0, y_offset,
+						 ILLEGAL_OPCODE_STATUS, 0);
 		break;
 	default:
 		break;
@@ -135,7 +140,7 @@ static uint32_t gpgpu_shader(int fd, struct intel_bb *ibb, enum shader_type shad
 			     enum sip_type sip_type, unsigned int threads, unsigned int width,
 			     unsigned int height)
 {
-	struct intel_buf *buf = create_fill_buf(fd, width, height, COLOR_C4);
+	struct intel_buf *buf = create_fill_buf(fd, width, height, (uint8_t)COLOR_C4);
 	struct gpgpu_shader *sip = get_sip(fd, sip_type, height / 2);
 	struct gpgpu_shader *shader = get_shader(fd, shader_type);
 
@@ -148,59 +153,72 @@ static uint32_t gpgpu_shader(int fd, struct intel_bb *ibb, enum shader_type shad
 	return buf->handle;
 }
 
-static void check_fill_buf(uint8_t *ptr, const int width, const int x,
-			   const int y, const uint8_t color)
+static void check_fill_buf(uint32_t *ptr, const int dword_width, const int x, const int y,
+			   const uint32_t color)
 {
-	const uint8_t val = ptr[y * width + x];
+	const uint32_t val = ptr[y * dword_width + x];
 
 	igt_assert_f(val == color,
-		     "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
+		     "Expected 0x%08x, found 0x%08x at (%d,%d)\n",
 		     color, val, x, y);
 }
 
-static void check_buf(int fd, uint32_t handle, int width, int height,
-		      enum shader_type shader_type, enum sip_type sip_type, uint8_t poison_c)
+static void check_buf(int fd, uint32_t handle, int width, int height, int thread_count_expected,
+		      enum shader_type shader_type, enum sip_type sip_type, uint32_t poison_c)
 {
+	int thread_count = 0, sip_count = 0, invalidinstr_count = 0;
 	unsigned int sz = ALIGN(width * height, 4096);
-	int thread_count = 0, sip_count = 0;
+	const uint32_t dword_width = width / 4;
 	uint32_t *ptr;
 	int i, j;
 
 	ptr = xe_bo_mmap_ext(fd, handle, sz, PROT_READ);
 
-	for (i = 0, j = 0; j < height / 2; ++j) {
-		if (ptr[j * width / 4] == SHADER_CANARY) {
+	for (i = 1, j = 0; j < height / 2; ++j) {
+		if (ptr[j * dword_width] == SHADER_CANARY)
 			++thread_count;
-			i = 4;
+		else
+			check_fill_buf(ptr, dword_width, 0, j, poison_c);
+
+		if (ptr[j * dword_width + 1] == SHADER_CANARY2) {
+			++invalidinstr_count;
+			++i;
 		}
 
-		for (; i < width; i++)
-			check_fill_buf((uint8_t *)ptr, width, i, j, poison_c);
+		for (; i < dword_width; i++)
+			check_fill_buf(ptr, dword_width, i, j, poison_c);
 
-		i = 0;
+		i = 1;
 	}
 
 	for (i = 0, j = height / 2; j < height; ++j) {
-		if (ptr[j * width / 4] == SIP_CANARY) {
+		if (ptr[j * dword_width] == SIP_CANARY) {
 			++sip_count;
 			i = 4;
 		}
 
-		for (; i < width; i++)
-			check_fill_buf((uint8_t *)ptr, width, i, j, poison_c);
+		for (; i < dword_width; i++)
+			check_fill_buf(ptr, dword_width, i, j, poison_c);
 
 		i = 0;
 	}
 
 	igt_assert(thread_count);
-	if (shader_type == SHADER_INV_INSTR_DISABLED)
-		igt_assert(!sip_count);
-	else if (sip_type == SIP_INV_INSTR && shader_type != SHADER_INV_INSTR_DISABLED)
+
+	if (shader_type >= SHADER_INV_INSTR_DISABLED &&
+	    shader_type <= SHADER_INV_INSTR_WALKER_ENABLED)
+		igt_assert_f(thread_count == invalidinstr_count,
+			     "Thread and invalid instruction count mismatch, %d != %d\n",
+			     thread_count, invalidinstr_count);
+	else
+		igt_assert_eq(invalidinstr_count, 0);
+
+	if (sip_type == SIP_INV_INSTR && shader_type != SHADER_INV_INSTR_DISABLED)
 		igt_assert_f(thread_count == sip_count,
 			     "Thread and SIP count mismatch, %d != %d\n",
 			     thread_count, sip_count);
 	else
-		igt_assert(sip_count == 0);
+		igt_assert_eq(sip_count, 0);
 
 	munmap(ptr, sz);
 }
@@ -270,7 +288,7 @@ static void test_sip(enum shader_type shader_type, enum sip_type sip_type,
 	intel_bb_sync(ibb);
 	igt_assert_lt_u64(igt_nsec_elapsed(&ts), timeout);
 
-	check_buf(fd, handle, width, height, shader_type, sip_type, COLOR_C4);
+	check_buf(fd, handle, width, height, threads, shader_type, sip_type, COLOR_C4);
 
 	gem_close(fd, handle);
 	intel_bb_destroy(ibb);
-- 
2.34.1

Re: [PATCH i-g-t 2/2] tests/xe_exec_sip: Write on invalidinstr

[Zbigniew Kempczyński]

On Wed, Sep 25, 2024 at 03:30:03PM +0200, Christoph Manszewski wrote:
> Currently we use 'gpgpu_shader__write_on_exception' only in a negative
> way which causes the write not happening in the default (passing) case.
> Change one of the usages to positive, to ensure the expected value has
> been written.
> 
> Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  tests/intel/xe_exec_sip.c | 80 ++++++++++++++++++++++++---------------
>  1 file changed, 49 insertions(+), 31 deletions(-)
> 
> diff --git a/tests/intel/xe_exec_sip.c b/tests/intel/xe_exec_sip.c
> index ed27d9c32..2294468c2 100644
> --- a/tests/intel/xe_exec_sip.c
> +++ b/tests/intel/xe_exec_sip.c
> @@ -27,10 +27,12 @@
>  #define WIDTH 64
>  #define HEIGHT 64
>  
> -#define COLOR_C4 0xc4
> +#define COLOR_C4 0xc4c4c4c4
>  
>  #define SHADER_CANARY 0x01010101
> -#define SIP_CANARY 0x02020202
> +#define SHADER_CANARY2 0x02020202
> +#define SIP_CANARY 0x03030303
> +#define SIP_CANARY2 0x04040404
>  
>  enum shader_type {
>  	SHADER_HANG,
> @@ -71,7 +73,7 @@ create_fill_buf(int fd, int width, int height, uint8_t color)
>  static struct gpgpu_shader *get_shader(int fd, enum shader_type shader_type)
>  {
>  	static struct gpgpu_shader *shader;
> -	uint32_t bad;
> +	uint32_t expected_cr0_bit;
>  
>  	shader = gpgpu_shader_create(fd);
>  	if (shader_type == SHADER_INV_INSTR_WALKER_ENABLED)
> @@ -92,15 +94,17 @@ static struct gpgpu_shader *get_shader(int fd, enum shader_type shader_type)
>  		__attribute__ ((fallthrough));
>  	case SHADER_INV_INSTR_DISABLED:
>  	case SHADER_INV_INSTR_WALKER_ENABLED:
> -		bad = (shader_type == SHADER_INV_INSTR_DISABLED) ? ILLEGAL_OPCODE_ENABLE : 0;
> -		gpgpu_shader__write_on_exception(shader, 1, 0, 0, ILLEGAL_OPCODE_ENABLE, bad);
> +		expected_cr0_bit = shader_type == SHADER_INV_INSTR_DISABLED ?
> +				   0 : ILLEGAL_OPCODE_ENABLE;
> +		gpgpu_shader__write_on_exception(shader, SHADER_CANARY2, 1, 0,
> +						 ILLEGAL_OPCODE_ENABLE, expected_cr0_bit);
>  		gpgpu_shader__nop(shader);
>  		gpgpu_shader__nop(shader);
>  		/* modify second nop, set only opcode bits[6:0] */
>  		shader->instr[gpgpu_shader_last_instr(shader)][0] = 0x7f;
> -		/* SIP should clear exception bit */
> -		bad = ILLEGAL_OPCODE_STATUS;
> -		gpgpu_shader__write_on_exception(shader, 2, 0, 0, ILLEGAL_OPCODE_STATUS, bad);
> +		/* SIP should clear exception bit, negative check */
> +		gpgpu_shader__write_on_exception(shader, SHADER_CANARY2, 0, 0,
> +						 ILLEGAL_OPCODE_STATUS, ILLEGAL_OPCODE_STATUS);
>  		break;
>  	}
>  
> @@ -120,7 +124,8 @@ static struct gpgpu_shader *get_sip(int fd, enum sip_type sip_type, unsigned int
>  
>  	switch (sip_type) {
>  	case SIP_INV_INSTR:
> -		gpgpu_shader__write_on_exception(sip, 1, 0, y_offset, ILLEGAL_OPCODE_STATUS, 0);
> +		gpgpu_shader__write_on_exception(sip, SIP_CANARY2, 0, y_offset,
> +						 ILLEGAL_OPCODE_STATUS, 0);
>  		break;
>  	default:
>  		break;
> @@ -135,7 +140,7 @@ static uint32_t gpgpu_shader(int fd, struct intel_bb *ibb, enum shader_type shad
>  			     enum sip_type sip_type, unsigned int threads, unsigned int width,
>  			     unsigned int height)
>  {
> -	struct intel_buf *buf = create_fill_buf(fd, width, height, COLOR_C4);
> +	struct intel_buf *buf = create_fill_buf(fd, width, height, (uint8_t)COLOR_C4);
>  	struct gpgpu_shader *sip = get_sip(fd, sip_type, height / 2);
>  	struct gpgpu_shader *shader = get_shader(fd, shader_type);
>  
> @@ -148,59 +153,72 @@ static uint32_t gpgpu_shader(int fd, struct intel_bb *ibb, enum shader_type shad
>  	return buf->handle;
>  }
>  
> -static void check_fill_buf(uint8_t *ptr, const int width, const int x,
> -			   const int y, const uint8_t color)
> +static void check_fill_buf(uint32_t *ptr, const int dword_width, const int x, const int y,
> +			   const uint32_t color)
>  {
> -	const uint8_t val = ptr[y * width + x];
> +	const uint32_t val = ptr[y * dword_width + x];
>  
>  	igt_assert_f(val == color,
> -		     "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
> +		     "Expected 0x%08x, found 0x%08x at (%d,%d)\n",
>  		     color, val, x, y);
>  }
>  
> -static void check_buf(int fd, uint32_t handle, int width, int height,
> -		      enum shader_type shader_type, enum sip_type sip_type, uint8_t poison_c)
> +static void check_buf(int fd, uint32_t handle, int width, int height, int thread_count_expected,
> +		      enum shader_type shader_type, enum sip_type sip_type, uint32_t poison_c)
>  {
> +	int thread_count = 0, sip_count = 0, invalidinstr_count = 0;
>  	unsigned int sz = ALIGN(width * height, 4096);
> -	int thread_count = 0, sip_count = 0;
> +	const uint32_t dword_width = width / 4;
>  	uint32_t *ptr;
>  	int i, j;
>  
>  	ptr = xe_bo_mmap_ext(fd, handle, sz, PROT_READ);
>  
> -	for (i = 0, j = 0; j < height / 2; ++j) {
> -		if (ptr[j * width / 4] == SHADER_CANARY) {
> +	for (i = 1, j = 0; j < height / 2; ++j) {
> +		if (ptr[j * dword_width] == SHADER_CANARY)
>  			++thread_count;
> -			i = 4;
> +		else
> +			check_fill_buf(ptr, dword_width, 0, j, poison_c);
> +
> +		if (ptr[j * dword_width + 1] == SHADER_CANARY2) {
> +			++invalidinstr_count;
> +			++i;
>  		}
>  
> -		for (; i < width; i++)
> -			check_fill_buf((uint8_t *)ptr, width, i, j, poison_c);
> +		for (; i < dword_width; i++)
> +			check_fill_buf(ptr, dword_width, i, j, poison_c);
>  
> -		i = 0;
> +		i = 1;
>  	}
>  
>  	for (i = 0, j = height / 2; j < height; ++j) {
> -		if (ptr[j * width / 4] == SIP_CANARY) {
> +		if (ptr[j * dword_width] == SIP_CANARY) {
>  			++sip_count;
>  			i = 4;
>  		}
>  
> -		for (; i < width; i++)
> -			check_fill_buf((uint8_t *)ptr, width, i, j, poison_c);
> +		for (; i < dword_width; i++)
> +			check_fill_buf(ptr, dword_width, i, j, poison_c);
>  
>  		i = 0;
>  	}

I thought to simplify above to avoid looping twice, especially you've
added x position in write_on_exception(). This would require to write
SHADER_CANARY on x == 0, SHADER_CANARY2 on x == 1, SHADER_SIP on x == 2
and SHADER_SIP2 on x == 3. I think this would make code clearer, especially
you wouldn't need to double the surface size. But this is not a blocker
for this patch, especially it is doing what I asked for (proves
write_on_exception() has the reflection in the memory).

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

>  
>  	igt_assert(thread_count);
> -	if (shader_type == SHADER_INV_INSTR_DISABLED)
> -		igt_assert(!sip_count);
> -	else if (sip_type == SIP_INV_INSTR && shader_type != SHADER_INV_INSTR_DISABLED)
> +
> +	if (shader_type >= SHADER_INV_INSTR_DISABLED &&
> +	    shader_type <= SHADER_INV_INSTR_WALKER_ENABLED)
> +		igt_assert_f(thread_count == invalidinstr_count,
> +			     "Thread and invalid instruction count mismatch, %d != %d\n",
> +			     thread_count, invalidinstr_count);
> +	else
> +		igt_assert_eq(invalidinstr_count, 0);
> +
> +	if (sip_type == SIP_INV_INSTR && shader_type != SHADER_INV_INSTR_DISABLED)
>  		igt_assert_f(thread_count == sip_count,
>  			     "Thread and SIP count mismatch, %d != %d\n",
>  			     thread_count, sip_count);
>  	else
> -		igt_assert(sip_count == 0);
> +		igt_assert_eq(sip_count, 0);
>  
>  	munmap(ptr, sz);
>  }
> @@ -270,7 +288,7 @@ static void test_sip(enum shader_type shader_type, enum sip_type sip_type,
>  	intel_bb_sync(ibb);
>  	igt_assert_lt_u64(igt_nsec_elapsed(&ts), timeout);
>  
> -	check_buf(fd, handle, width, height, shader_type, sip_type, COLOR_C4);
> +	check_buf(fd, handle, width, height, threads, shader_type, sip_type, COLOR_C4);
>  
>  	gem_close(fd, handle);
>  	intel_bb_destroy(ibb);
> -- 
> 2.34.1
> 

Re: [PATCH i-g-t 2/2] tests/xe_exec_sip: Write on invalidinstr

[Manszewski, Christoph]

Hi Zbigniew,

On 2.10.2024 09:50, Zbigniew Kempczyński wrote:
> On Wed, Sep 25, 2024 at 03:30:03PM +0200, Christoph Manszewski wrote:
>> Currently we use 'gpgpu_shader__write_on_exception' only in a negative
>> way which causes the write not happening in the default (passing) case.
>> Change one of the usages to positive, to ensure the expected value has
>> been written.
>>
>> Signed-off-by: Christoph Manszewski <christoph.manszewski@intel.com>
>> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>> ---
>>   tests/intel/xe_exec_sip.c | 80 ++++++++++++++++++++++++---------------
>>   1 file changed, 49 insertions(+), 31 deletions(-)
>>
>> diff --git a/tests/intel/xe_exec_sip.c b/tests/intel/xe_exec_sip.c
>> index ed27d9c32..2294468c2 100644
>> --- a/tests/intel/xe_exec_sip.c
>> +++ b/tests/intel/xe_exec_sip.c
>> @@ -27,10 +27,12 @@
>>   #define WIDTH 64
>>   #define HEIGHT 64
>>   
>> -#define COLOR_C4 0xc4
>> +#define COLOR_C4 0xc4c4c4c4
>>   
>>   #define SHADER_CANARY 0x01010101
>> -#define SIP_CANARY 0x02020202
>> +#define SHADER_CANARY2 0x02020202
>> +#define SIP_CANARY 0x03030303
>> +#define SIP_CANARY2 0x04040404
>>   
>>   enum shader_type {
>>   	SHADER_HANG,
>> @@ -71,7 +73,7 @@ create_fill_buf(int fd, int width, int height, uint8_t color)
>>   static struct gpgpu_shader *get_shader(int fd, enum shader_type shader_type)
>>   {
>>   	static struct gpgpu_shader *shader;
>> -	uint32_t bad;
>> +	uint32_t expected_cr0_bit;
>>   
>>   	shader = gpgpu_shader_create(fd);
>>   	if (shader_type == SHADER_INV_INSTR_WALKER_ENABLED)
>> @@ -92,15 +94,17 @@ static struct gpgpu_shader *get_shader(int fd, enum shader_type shader_type)
>>   		__attribute__ ((fallthrough));
>>   	case SHADER_INV_INSTR_DISABLED:
>>   	case SHADER_INV_INSTR_WALKER_ENABLED:
>> -		bad = (shader_type == SHADER_INV_INSTR_DISABLED) ? ILLEGAL_OPCODE_ENABLE : 0;
>> -		gpgpu_shader__write_on_exception(shader, 1, 0, 0, ILLEGAL_OPCODE_ENABLE, bad);
>> +		expected_cr0_bit = shader_type == SHADER_INV_INSTR_DISABLED ?
>> +				   0 : ILLEGAL_OPCODE_ENABLE;
>> +		gpgpu_shader__write_on_exception(shader, SHADER_CANARY2, 1, 0,
>> +						 ILLEGAL_OPCODE_ENABLE, expected_cr0_bit);
>>   		gpgpu_shader__nop(shader);
>>   		gpgpu_shader__nop(shader);
>>   		/* modify second nop, set only opcode bits[6:0] */
>>   		shader->instr[gpgpu_shader_last_instr(shader)][0] = 0x7f;
>> -		/* SIP should clear exception bit */
>> -		bad = ILLEGAL_OPCODE_STATUS;
>> -		gpgpu_shader__write_on_exception(shader, 2, 0, 0, ILLEGAL_OPCODE_STATUS, bad);
>> +		/* SIP should clear exception bit, negative check */
>> +		gpgpu_shader__write_on_exception(shader, SHADER_CANARY2, 0, 0,
>> +						 ILLEGAL_OPCODE_STATUS, ILLEGAL_OPCODE_STATUS);
>>   		break;
>>   	}
>>   
>> @@ -120,7 +124,8 @@ static struct gpgpu_shader *get_sip(int fd, enum sip_type sip_type, unsigned int
>>   
>>   	switch (sip_type) {
>>   	case SIP_INV_INSTR:
>> -		gpgpu_shader__write_on_exception(sip, 1, 0, y_offset, ILLEGAL_OPCODE_STATUS, 0);
>> +		gpgpu_shader__write_on_exception(sip, SIP_CANARY2, 0, y_offset,
>> +						 ILLEGAL_OPCODE_STATUS, 0);
>>   		break;
>>   	default:
>>   		break;
>> @@ -135,7 +140,7 @@ static uint32_t gpgpu_shader(int fd, struct intel_bb *ibb, enum shader_type shad
>>   			     enum sip_type sip_type, unsigned int threads, unsigned int width,
>>   			     unsigned int height)
>>   {
>> -	struct intel_buf *buf = create_fill_buf(fd, width, height, COLOR_C4);
>> +	struct intel_buf *buf = create_fill_buf(fd, width, height, (uint8_t)COLOR_C4);
>>   	struct gpgpu_shader *sip = get_sip(fd, sip_type, height / 2);
>>   	struct gpgpu_shader *shader = get_shader(fd, shader_type);
>>   
>> @@ -148,59 +153,72 @@ static uint32_t gpgpu_shader(int fd, struct intel_bb *ibb, enum shader_type shad
>>   	return buf->handle;
>>   }
>>   
>> -static void check_fill_buf(uint8_t *ptr, const int width, const int x,
>> -			   const int y, const uint8_t color)
>> +static void check_fill_buf(uint32_t *ptr, const int dword_width, const int x, const int y,
>> +			   const uint32_t color)
>>   {
>> -	const uint8_t val = ptr[y * width + x];
>> +	const uint32_t val = ptr[y * dword_width + x];
>>   
>>   	igt_assert_f(val == color,
>> -		     "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
>> +		     "Expected 0x%08x, found 0x%08x at (%d,%d)\n",
>>   		     color, val, x, y);
>>   }
>>   
>> -static void check_buf(int fd, uint32_t handle, int width, int height,
>> -		      enum shader_type shader_type, enum sip_type sip_type, uint8_t poison_c)
>> +static void check_buf(int fd, uint32_t handle, int width, int height, int thread_count_expected,
>> +		      enum shader_type shader_type, enum sip_type sip_type, uint32_t poison_c)
>>   {
>> +	int thread_count = 0, sip_count = 0, invalidinstr_count = 0;
>>   	unsigned int sz = ALIGN(width * height, 4096);
>> -	int thread_count = 0, sip_count = 0;
>> +	const uint32_t dword_width = width / 4;
>>   	uint32_t *ptr;
>>   	int i, j;
>>   
>>   	ptr = xe_bo_mmap_ext(fd, handle, sz, PROT_READ);
>>   
>> -	for (i = 0, j = 0; j < height / 2; ++j) {
>> -		if (ptr[j * width / 4] == SHADER_CANARY) {
>> +	for (i = 1, j = 0; j < height / 2; ++j) {
>> +		if (ptr[j * dword_width] == SHADER_CANARY)
>>   			++thread_count;
>> -			i = 4;
>> +		else
>> +			check_fill_buf(ptr, dword_width, 0, j, poison_c);
>> +
>> +		if (ptr[j * dword_width + 1] == SHADER_CANARY2) {
>> +			++invalidinstr_count;
>> +			++i;
>>   		}
>>   
>> -		for (; i < width; i++)
>> -			check_fill_buf((uint8_t *)ptr, width, i, j, poison_c);
>> +		for (; i < dword_width; i++)
>> +			check_fill_buf(ptr, dword_width, i, j, poison_c);
>>   
>> -		i = 0;
>> +		i = 1;
>>   	}
>>   
>>   	for (i = 0, j = height / 2; j < height; ++j) {
>> -		if (ptr[j * width / 4] == SIP_CANARY) {
>> +		if (ptr[j * dword_width] == SIP_CANARY) {
>>   			++sip_count;
>>   			i = 4;
>>   		}
>>   
>> -		for (; i < width; i++)
>> -			check_fill_buf((uint8_t *)ptr, width, i, j, poison_c);
>> +		for (; i < dword_width; i++)
>> +			check_fill_buf(ptr, dword_width, i, j, poison_c);
>>   
>>   		i = 0;
>>   	}
> 
> I thought to simplify above to avoid looping twice, especially you've
> added x position in write_on_exception(). This would require to write
> SHADER_CANARY on x == 0, SHADER_CANARY2 on x == 1, SHADER_SIP on x == 2
> and SHADER_SIP2 on x == 3. I think this would make code clearer, especially
> you wouldn't need to double the surface size. But this is not a blocker
> for this patch, especially it is doing what I asked for (proves
> write_on_exception() has the reflection in the memory).
> 
> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Thanks, I'll allow myself to take that r-b and leave the check buf logic 
refactor for another day =)

Thanks,
Christoph

> 
> --
> Zbigniew
> 
>>   
>>   	igt_assert(thread_count);
>> -	if (shader_type == SHADER_INV_INSTR_DISABLED)
>> -		igt_assert(!sip_count);
>> -	else if (sip_type == SIP_INV_INSTR && shader_type != SHADER_INV_INSTR_DISABLED)
>> +
>> +	if (shader_type >= SHADER_INV_INSTR_DISABLED &&
>> +	    shader_type <= SHADER_INV_INSTR_WALKER_ENABLED)
>> +		igt_assert_f(thread_count == invalidinstr_count,
>> +			     "Thread and invalid instruction count mismatch, %d != %d\n",
>> +			     thread_count, invalidinstr_count);
>> +	else
>> +		igt_assert_eq(invalidinstr_count, 0);
>> +
>> +	if (sip_type == SIP_INV_INSTR && shader_type != SHADER_INV_INSTR_DISABLED)
>>   		igt_assert_f(thread_count == sip_count,
>>   			     "Thread and SIP count mismatch, %d != %d\n",
>>   			     thread_count, sip_count);
>>   	else
>> -		igt_assert(sip_count == 0);
>> +		igt_assert_eq(sip_count, 0);
>>   
>>   	munmap(ptr, sz);
>>   }
>> @@ -270,7 +288,7 @@ static void test_sip(enum shader_type shader_type, enum sip_type sip_type,
>>   	intel_bb_sync(ibb);
>>   	igt_assert_lt_u64(igt_nsec_elapsed(&ts), timeout);
>>   
>> -	check_buf(fd, handle, width, height, shader_type, sip_type, COLOR_C4);
>> +	check_buf(fd, handle, width, height, threads, shader_type, sip_type, COLOR_C4);
>>   
>>   	gem_close(fd, handle);
>>   	intel_bb_destroy(ibb);
>> -- 
>> 2.34.1
>>

✗ Fi.CI.BAT: failure for Execute and validate 'write_on_exception' shader

[Patchwork]

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== Series Details ==

Series: Execute and validate 'write_on_exception' shader
URL   : https://patchwork.freedesktop.org/series/139094/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_15444 -> IGTPW_11801
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_11801 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_11801, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/index.html

Participating hosts (37 -> 37)
------------------------------

  Additional (1): bat-rpls-4 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_11801:

### IGT changes ###

#### Possible regressions ####

  * igt@debugfs_test@basic-hwmon:
    - bat-rpls-4:         NOTRUN -> [SKIP][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-rpls-4/igt@debugfs_test@basic-hwmon.html

  
#### Warnings ####

  * igt@fbdev@eof:
    - bat-arlh-2:         [SKIP][2] ([i915#11345]) -> [SKIP][3] +3 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15444/bat-arlh-2/igt@fbdev@eof.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-arlh-2/igt@fbdev@eof.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - bat-twl-2:          [SKIP][4] ([i915#11731]) -> [SKIP][5] +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15444/bat-twl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-twl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-twl-1:          [SKIP][6] ([i915#11731]) -> [SKIP][7] +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15444/bat-twl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-twl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  
Known issues
------------

  Here are the changes found in IGTPW_11801 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_lmem_swapping@basic:
    - bat-rpls-4:         NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-rpls-4/igt@gem_lmem_swapping@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-rpls-4:         NOTRUN -> [SKIP][9] ([i915#3282])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-rpls-4/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][10] -> [ABORT][11] ([i915#12216]) +1 other test abort
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15444/bat-mtlp-8/igt@i915_selftest@live.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - bat-dg2-13:         NOTRUN -> [SKIP][12] ([i915#7828]) +8 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-dg2-13/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - bat-rpls-4:         NOTRUN -> [SKIP][13] ([i915#4103]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-rpls-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
    - bat-rpls-4:         NOTRUN -> [SKIP][14] ([i915#3555] / [i915#3840] / [i915#9886])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-rpls-4/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-rpls-4:         NOTRUN -> [SKIP][15]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-rpls-4/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-rpls-4:         NOTRUN -> [SKIP][16] ([i915#5354])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-rpls-4/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - bat-rpls-4:         NOTRUN -> [SKIP][17] ([i915#1072] / [i915#9732]) +3 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-rpls-4/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-rpls-4:         NOTRUN -> [SKIP][18] ([i915#3555])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-rpls-4/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-read:
    - bat-rpls-4:         NOTRUN -> [SKIP][19] ([i915#3708]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-rpls-4/igt@prime_vgem@basic-read.html

  
#### Possible fixes ####

  * igt@i915_module_load@load:
    - bat-dg2-9:          [DMESG-WARN][20] ([i915#12257]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15444/bat-dg2-9/igt@i915_module_load@load.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-dg2-9/igt@i915_module_load@load.html

  * igt@i915_selftest@live:
    - bat-mtlp-6:         [DMESG-WARN][22] ([i915#10341]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15444/bat-mtlp-6/igt@i915_selftest@live.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-mtlp-6/igt@i915_selftest@live.html

  * igt@i915_selftest@live@hangcheck:
    - bat-mtlp-6:         [DMESG-WARN][24] ([i915#11349]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15444/bat-mtlp-6/igt@i915_selftest@live@hangcheck.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-mtlp-6/igt@i915_selftest@live@hangcheck.html

  
#### Warnings ####

  * igt@fbdev@read:
    - bat-arls-1:         [DMESG-FAIL][26] ([i915#12102]) -> [DMESG-WARN][27] ([i915#12102])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15444/bat-arls-1/igt@fbdev@read.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/bat-arls-1/igt@fbdev@read.html

  
  [i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11345]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11345
  [i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
  [i915#11731]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11731
  [i915#12102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12102
  [i915#12216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12216
  [i915#12257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12257
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8032 -> IGTPW_11801

  CI-20190529: 20190529
  CI_DRM_15444: 88d592f72f7bc508d6a027b1f96aa2e53f803e1b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_11801: 0cde297f64e94e5ef79a198dca1b2e0990945734 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8032: 8032

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11801/index.html

[-- Attachment #2: Type: text/html, Size: 9586 bytes --]

✗ CI.xeBAT: failure for Execute and validate 'write_on_exception' shader

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4471 bytes --]

== Series Details ==

Series: Execute and validate 'write_on_exception' shader
URL   : https://patchwork.freedesktop.org/series/139094/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8032_BAT -> XEIGTPW_11801_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_11801_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_11801_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_11801_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit:
    - bat-adlp-7:         [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/bat-adlp-7/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/bat-adlp-7/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html

  
#### Warnings ####

  * igt@xe_pat@pat-index-xelpg:
    - bat-bmg-1:          [SKIP][3] ([Intel XE#2236]) -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/bat-bmg-1/igt@xe_pat@pat-index-xelpg.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/bat-bmg-1/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pm_residency@gt-c6-on-idle:
    - bat-adlp-vf:        [SKIP][5] ([Intel XE#2468]) -> [SKIP][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/bat-adlp-vf/igt@xe_pm_residency@gt-c6-on-idle.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/bat-adlp-vf/igt@xe_pm_residency@gt-c6-on-idle.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@xe_pat@pat-index-xelpg:
    - {bat-bmg-2}:        [SKIP][7] ([Intel XE#2236]) -> [SKIP][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/bat-bmg-2/igt@xe_pat@pat-index-xelpg.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/bat-bmg-2/igt@xe_pat@pat-index-xelpg.html

  
Known issues
------------

  Here are the changes found in XEIGTPW_11801_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_psr@psr-primary-page-flip@edp-1:
    - bat-lnl-1:          [PASS][9] -> [FAIL][10] ([Intel XE#1649]) +5 other tests fail
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/bat-lnl-1/igt@kms_psr@psr-primary-page-flip@edp-1.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/bat-lnl-1/igt@kms_psr@psr-primary-page-flip@edp-1.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@basic:
    - bat-lnl-2:          [SKIP][11] ([Intel XE#2235]) -> [SKIP][12] ([Intel XE#2235] / [Intel XE#2548])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/bat-lnl-2/igt@kms_frontbuffer_tracking@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/bat-lnl-2/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1649]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1649
  [Intel XE#2235]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2235
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2468]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2468
  [Intel XE#2548]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2548


Build changes
-------------

  * IGT: IGT_8032 -> IGTPW_11801
  * Linux: xe-1975-abfe8cf977e1abd1f414b2a90d223cd4dd2f1f47 -> xe-1976-88d592f72f7bc508d6a027b1f96aa2e53f803e1b

  IGTPW_11801: 0cde297f64e94e5ef79a198dca1b2e0990945734 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8032: 8032
  xe-1975-abfe8cf977e1abd1f414b2a90d223cd4dd2f1f47: abfe8cf977e1abd1f414b2a90d223cd4dd2f1f47
  xe-1976-88d592f72f7bc508d6a027b1f96aa2e53f803e1b: 88d592f72f7bc508d6a027b1f96aa2e53f803e1b

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/index.html

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✗ CI.xeFULL: failure for Execute and validate 'write_on_exception' shader

[Patchwork]

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== Series Details ==

Series: Execute and validate 'write_on_exception' shader
URL   : https://patchwork.freedesktop.org/series/139094/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8032_full -> XEIGTPW_11801_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_11801_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_11801_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_11801_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-lnl:          NOTRUN -> [SKIP][1] +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-2/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [PASS][2] -> [SKIP][3] +1 other test skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-4/igt@kms_pm_dc@dc5-psr.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-4/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1:
    - shard-lnl:          [PASS][4] -> [FAIL][5] +54 other tests fail
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-3/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-5/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area@psr2-pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [FAIL][6] +1 other test fail
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-1/igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area@psr2-pipe-a-edp-1.html

  * igt@xe_exec_fault_mode@many-userptr-invalidate-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@xe_exec_fault_mode@many-userptr-invalidate-imm.html

  
#### Warnings ####

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [FAIL][8] ([Intel XE#1430]) -> [SKIP][9]
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-2/igt@kms_pm_dc@dc6-psr.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-5/igt@kms_pm_dc@dc6-psr.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-imm:
    - shard-dg2-set2:     [SKIP][10] ([Intel XE#1201]) -> [SKIP][11] +14 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@xe_exec_fault_mode@once-bindexecqueue-imm.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@xe_exec_fault_mode@once-bindexecqueue-imm.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - {shard-bmg}:        [SKIP][12] ([Intel XE#2385]) -> [SKIP][13]
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-5/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - {shard-bmg}:        [SKIP][14] ([Intel XE#2370]) -> [SKIP][15]
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - {shard-bmg}:        [SKIP][16] ([Intel XE#2327]) -> [SKIP][17] +6 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-6/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - {shard-bmg}:        [PASS][18] -> [SKIP][19] +137 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - {shard-bmg}:        [SKIP][20] ([Intel XE#1124]) -> [SKIP][21] +16 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-7/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - {shard-bmg}:        [SKIP][22] ([Intel XE#610]) -> [SKIP][23]
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-2/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - {shard-bmg}:        [SKIP][24] ([Intel XE#367]) -> [SKIP][25] +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-6/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - {shard-bmg}:        [SKIP][26] ([Intel XE#2251]) -> [SKIP][27] +20 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-4/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - {shard-bmg}:        [SKIP][28] ([Intel XE#2652] / [Intel XE#787]) -> [SKIP][29]
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-7/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_cdclk@plane-scaling:
    - {shard-bmg}:        [SKIP][30] ([Intel XE#2724]) -> [SKIP][31] +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-3/igt@kms_cdclk@plane-scaling.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - {shard-bmg}:        [SKIP][32] ([Intel XE#2252]) -> [SKIP][33] +15 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-2/igt@kms_chamelium_edid@dp-edid-resolution-list.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_content_protection@content-type-change:
    - {shard-bmg}:        [SKIP][34] ([Intel XE#2341]) -> [SKIP][35]
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-2/igt@kms_content_protection@content-type-change.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@lic-type-0:
    - {shard-bmg}:        [FAIL][36] ([Intel XE#1178]) -> [SKIP][37]
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-4/igt@kms_content_protection@lic-type-0.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@uevent:
    - {shard-bmg}:        [FAIL][38] ([Intel XE#1188]) -> [SKIP][39]
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-3/igt@kms_content_protection@uevent.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - {shard-bmg}:        [SKIP][40] ([Intel XE#2320]) -> [SKIP][41] +4 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-5/igt@kms_cursor_crc@cursor-offscreen-128x42.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_crc@cursor-random-64x64:
    - {shard-bmg}:        [PASS][42] -> [INCOMPLETE][43] +1 other test incomplete
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-2/igt@kms_cursor_crc@cursor-random-64x64.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-2/igt@kms_cursor_crc@cursor-random-64x64.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - {shard-bmg}:        [FAIL][44] ([Intel XE#2141]) -> [SKIP][45]
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-4/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - {shard-bmg}:        [SKIP][46] ([Intel XE#2244]) -> [SKIP][47]
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-7/igt@kms_dsc@dsc-fractional-bpp.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_fbcon_fbt@fbc:
    - {shard-bmg}:        [FAIL][48] ([Intel XE#1695]) -> [SKIP][49]
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-7/igt@kms_fbcon_fbt@fbc.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_fbcon_fbt@psr:
    - {shard-bmg}:        [SKIP][50] ([Intel XE#776]) -> [SKIP][51]
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-5/igt@kms_fbcon_fbt@psr.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_fbcon_fbt@psr.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - {shard-bmg}:        [SKIP][52] ([Intel XE#2380]) -> [SKIP][53] +6 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt:
    - {shard-bmg}:        [SKIP][54] ([Intel XE#2311]) -> [SKIP][55] +37 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - {shard-bmg}:        [FAIL][56] -> [SKIP][57] +11 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - {shard-bmg}:        [FAIL][58] ([Intel XE#2333]) -> [SKIP][59] +9 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - {shard-bmg}:        [SKIP][60] ([Intel XE#2352]) -> [SKIP][61]
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
    - {shard-bmg}:        [SKIP][62] ([Intel XE#2312]) -> [SKIP][63] +2 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
    - {shard-bmg}:        [SKIP][64] ([Intel XE#2313]) -> [SKIP][65] +38 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_plane_lowres@tiling-yf:
    - {shard-bmg}:        [SKIP][66] ([Intel XE#2393]) -> [SKIP][67]
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-8/igt@kms_plane_lowres@tiling-yf.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@tiling-yf:
    - {shard-bmg}:        [SKIP][68] ([Intel XE#2493]) -> [SKIP][69] +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-7/igt@kms_plane_multiple@tiling-yf.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
    - {shard-bmg}:        [SKIP][70] ([Intel XE#2763]) -> [SKIP][71]
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-7/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html

  * igt@kms_pm_backlight@fade:
    - {shard-bmg}:        [SKIP][72] ([Intel XE#870]) -> [SKIP][73]
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-6/igt@kms_pm_backlight@fade.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - {shard-bmg}:        NOTRUN -> [SKIP][74] +29 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-2/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
    - {shard-bmg}:        [SKIP][75] ([Intel XE#1489]) -> [SKIP][76] +3 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - {shard-bmg}:        [SKIP][77] ([Intel XE#2850]) -> [SKIP][78] +19 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-1/igt@kms_psr@fbc-psr2-cursor-plane-move.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - {shard-bmg}:        [SKIP][79] ([Intel XE#2329]) -> [SKIP][80] +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - {shard-bmg}:        [SKIP][81] ([Intel XE#2413]) -> [SKIP][82]
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-3/igt@kms_scaling_modes@scaling-mode-center.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_tiled_display@basic-test-pattern:
    - {shard-bmg}:        [SKIP][83] ([Intel XE#2426]) -> [SKIP][84]
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tv_load_detect@load-detect:
    - {shard-bmg}:        [SKIP][85] ([Intel XE#2450]) -> [SKIP][86]
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-1/igt@kms_tv_load_detect@load-detect.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@flip-suspend:
    - {shard-bmg}:        [SKIP][87] ([Intel XE#1499]) -> [SKIP][88]
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-5/igt@kms_vrr@flip-suspend.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_vrr@flip-suspend.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - {shard-bmg}:        [SKIP][89] ([Intel XE#756]) -> [SKIP][90] +1 other test skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-4/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-6/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@xe_oa@mmio-triggered-reports@rcs-0:
    - {shard-bmg}:        NOTRUN -> [FAIL][91] +1 other test fail
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-2/igt@xe_oa@mmio-triggered-reports@rcs-0.html

  * igt@xe_pat@pat-index-xelpg:
    - {shard-bmg}:        [SKIP][92] ([Intel XE#2236]) -> [SKIP][93]
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-1/igt@xe_pat@pat-index-xelpg.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-1/igt@xe_pat@pat-index-xelpg.html

  
Known issues
------------

  Here are the changes found in XEIGTPW_11801_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear:
    - shard-lnl:          [PASS][94] -> [FAIL][95] ([Intel XE#911]) +3 other tests fail
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-2/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1:
    - shard-lnl:          [PASS][96] -> [FAIL][97] ([Intel XE#1426]) +1 other test fail
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-3/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#1407])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-8/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][99] ([Intel XE#1201] / [Intel XE#316])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][100] ([Intel XE#1124])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#1124]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-2/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][102] ([Intel XE#1124] / [Intel XE#1201]) +2 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-436/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][103] ([Intel XE#1201] / [Intel XE#367]) +1 other test skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][104] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][105] ([Intel XE#787]) +6 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][106] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +1 other test skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][107] ([Intel XE#1201] / [Intel XE#787]) +6 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-dp-4.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][108] ([Intel XE#1252])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [PASS][109] -> [INCOMPLETE][110] ([Intel XE#1195] / [Intel XE#1727])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     [PASS][111] -> [INCOMPLETE][112] ([Intel XE#1195]) +2 other tests incomplete
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-dg2-set2:     NOTRUN -> [SKIP][113] ([Intel XE#373])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][114] ([Intel XE#373]) +2 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-4/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
    - shard-dg2-set2:     NOTRUN -> [SKIP][115] ([Intel XE#1201] / [Intel XE#373]) +3 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-466/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html

  * igt@kms_cursor_crc@cursor-random-256x85:
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#1424])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-8/igt@kms_cursor_crc@cursor-random-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][117] ([Intel XE#1201] / [Intel XE#455]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-435/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-lnl:          [PASS][118] -> [SKIP][119] ([Intel XE#1508])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-5/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-8/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][120] ([Intel XE#1401] / [Intel XE#1745])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][121] ([Intel XE#1401])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][122] ([Intel XE#1397] / [Intel XE#1745])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][123] ([Intel XE#1397])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][124] ([Intel XE#656]) +7 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][125] ([Intel XE#651])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][126] ([Intel XE#1201] / [Intel XE#651]) +6 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][127] ([Intel XE#1201] / [Intel XE#653]) +6 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][128] ([Intel XE#653]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     [PASS][129] -> [SKIP][130] ([Intel XE#1201] / [Intel XE#455])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-434/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane@plane-position-covered:
    - shard-lnl:          [PASS][131] -> [DMESG-FAIL][132] ([Intel XE#324]) +2 other tests dmesg-fail
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-4/igt@kms_plane@plane-position-covered.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-1/igt@kms_plane@plane-position-covered.html

  * igt@kms_plane@plane-position-hole-dpms@pipe-b-plane-3:
    - shard-lnl:          [PASS][133] -> [DMESG-WARN][134] ([Intel XE#324]) +3 other tests dmesg-warn
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-4/igt@kms_plane@plane-position-hole-dpms@pipe-b-plane-3.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-3/igt@kms_plane@plane-position-hole-dpms@pipe-b-plane-3.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b:
    - shard-lnl:          NOTRUN -> [SKIP][135] ([Intel XE#2763]) +3 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-7/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b.html

  * igt@kms_pm_backlight@fade:
    - shard-dg2-set2:     NOTRUN -> [SKIP][136] ([Intel XE#1201] / [Intel XE#870])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-466/igt@kms_pm_backlight@fade.html

  * igt@kms_psr@fbc-psr2-cursor-render@edp-1:
    - shard-lnl:          [PASS][137] -> [FAIL][138] ([Intel XE#1649]) +113 other tests fail
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-5/igt@kms_psr@fbc-psr2-cursor-render@edp-1.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-3/igt@kms_psr@fbc-psr2-cursor-render@edp-1.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-lnl:          NOTRUN -> [FAIL][139] ([Intel XE#1649]) +5 other tests fail
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-5/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@pr-sprite-blt:
    - shard-lnl:          NOTRUN -> [SKIP][140] ([Intel XE#1406])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-4/igt@kms_psr@pr-sprite-blt.html

  * igt@kms_psr@psr2-primary-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][141] ([Intel XE#1201] / [Intel XE#2850])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-463/igt@kms_psr@psr2-primary-blt.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-lnl:          [PASS][142] -> [FAIL][143] ([Intel XE#899]) +1 other test fail
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-8/igt@kms_universal_plane@cursor-fb-leak.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-7/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][144] -> [FAIL][145] ([Intel XE#2159]) +1 other test fail
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-3/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@kms_vrr@flip-basic:
    - shard-lnl:          [PASS][146] -> [FAIL][147] ([Intel XE#2443]) +1 other test fail
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-1/igt@kms_vrr@flip-basic.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-1/igt@kms_vrr@flip-basic.html

  * igt@kms_vrr@lobf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [FAIL][148] ([Intel XE#2443]) +1 other test fail
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-7/igt@kms_vrr@lobf@pipe-a-edp-1.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-dg2-set2:     NOTRUN -> [SKIP][149] ([Intel XE#1201] / [Intel XE#756])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-436/igt@kms_writeback@writeback-fb-id.html

  * igt@xe_evict@evict-large-multi-vm-cm:
    - shard-dg2-set2:     NOTRUN -> [FAIL][150] ([Intel XE#1600])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-464/igt@xe_evict@evict-large-multi-vm-cm.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
    - shard-lnl:          NOTRUN -> [SKIP][151] ([Intel XE#1392])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-3/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html

  * igt@xe_exec_compute_mode@many-bindexecqueue-userptr-invalidate:
    - shard-lnl:          [PASS][152] -> [DMESG-WARN][153] ([Intel XE#2687])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-5/igt@xe_exec_compute_mode@many-bindexecqueue-userptr-invalidate.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-5/igt@xe_exec_compute_mode@many-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_compute_mode@once-userptr-invalidate:
    - shard-lnl:          [PASS][154] -> [FAIL][155] ([Intel XE#1069]) +1 other test fail
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-1/igt@xe_exec_compute_mode@once-userptr-invalidate.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-4/igt@xe_exec_compute_mode@once-userptr-invalidate.html

  * igt@xe_exec_fault_mode@twice-basic-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][156] ([Intel XE#1201] / [Intel XE#288])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-435/igt@xe_exec_fault_mode@twice-basic-prefetch.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-dg2-set2:     [PASS][157] -> [TIMEOUT][158] ([Intel XE#2105])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-436/igt@xe_exec_reset@parallel-gt-reset.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_oa@invalid-map-oa-buffer:
    - shard-dg2-set2:     NOTRUN -> [SKIP][159] ([Intel XE#2541])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@xe_oa@invalid-map-oa-buffer.html

  * igt@xe_oa@mmio-triggered-reports:
    - shard-lnl:          [PASS][160] -> [FAIL][161] ([Intel XE#2249])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-1/igt@xe_oa@mmio-triggered-reports.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-1/igt@xe_oa@mmio-triggered-reports.html

  * igt@xe_oa@privileged-forked-access-vaddr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][162] ([Intel XE#1201] / [Intel XE#2541]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@xe_oa@privileged-forked-access-vaddr.html

  * igt@xe_pm@s2idle-multiple-execs:
    - shard-dg2-set2:     [PASS][163] -> [INCOMPLETE][164] ([Intel XE#1195] / [Intel XE#1358])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-466/igt@xe_pm@s2idle-multiple-execs.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-435/igt@xe_pm@s2idle-multiple-execs.html

  * igt@xe_pm@s4-vm-bind-prefetch:
    - shard-lnl:          [PASS][165] -> [ABORT][166] ([Intel XE#1607] / [Intel XE#1794])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-5/igt@xe_pm@s4-vm-bind-prefetch.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-2/igt@xe_pm@s4-vm-bind-prefetch.html

  * igt@xe_query@multigpu-query-engines:
    - shard-dg2-set2:     NOTRUN -> [SKIP][167] ([Intel XE#1201]) +5 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@xe_query@multigpu-query-engines.html

  
#### Possible fixes ####

  * igt@core_hotunplug@hotreplug-lateclose:
    - {shard-bmg}:        [ABORT][168] -> [PASS][169]
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-6/igt@core_hotunplug@hotreplug-lateclose.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-7/igt@core_hotunplug@hotreplug-lateclose.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
    - {shard-bmg}:        [FAIL][170] ([Intel XE#1426]) -> [PASS][171] +1 other test pass
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-2/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-1/igt@kms_atomic_transition@plane-toggle-modeset-transition.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1:
    - shard-lnl:          [FAIL][172] ([Intel XE#1426]) -> [PASS][173] +1 other test pass
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-1/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [FAIL][174] ([Intel XE#1426]) -> [PASS][175] +1 other test pass
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-6.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-6.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - {shard-bmg}:        [INCOMPLETE][176] -> [PASS][177]
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-8/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-7/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-d-hdmi-a-3:
    - {shard-bmg}:        [DMESG-WARN][178] ([Intel XE#877]) -> [PASS][179] +5 other tests pass
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-4/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-d-hdmi-a-3.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-1/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1:
    - shard-lnl:          [INCOMPLETE][180] ([Intel XE#1616]) -> [PASS][181] +1 other test pass
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-4/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-5/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html

  * igt@kms_display_modes@extended-mode-basic:
    - {shard-bmg}:        [SKIP][182] ([Intel XE#2425]) -> [PASS][183]
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-5/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - {shard-bmg}:        [SKIP][184] -> [PASS][185] +2 other tests pass
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a3:
    - {shard-bmg}:        [DMESG-WARN][186] -> [PASS][187] +5 other tests pass
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-6/igt@kms_flip@flip-vs-suspend@b-hdmi-a3.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-3/igt@kms_flip@flip-vs-suspend@b-hdmi-a3.html

  * igt@kms_flip@wf_vblank-ts-check@c-edp1:
    - shard-lnl:          [FAIL][188] ([Intel XE#886]) -> [PASS][189]
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-8/igt@kms_flip@wf_vblank-ts-check@c-edp1.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-4/igt@kms_flip@wf_vblank-ts-check@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-valid-mode:
    - shard-dg2-set2:     [INCOMPLETE][190] ([Intel XE#1195]) -> [PASS][191] +1 other test pass
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-463/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-valid-mode.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-434/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-valid-mode.html

  * igt@kms_plane@plane-position-hole@pipe-a-plane-4:
    - shard-lnl:          [DMESG-FAIL][192] ([Intel XE#324]) -> [PASS][193] +1 other test pass
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-5/igt@kms_plane@plane-position-hole@pipe-a-plane-4.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-3/igt@kms_plane@plane-position-hole@pipe-a-plane-4.html

  * igt@kms_plane@plane-position-hole@pipe-b-plane-3:
    - shard-lnl:          [DMESG-WARN][194] ([Intel XE#324]) -> [PASS][195]
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-5/igt@kms_plane@plane-position-hole@pipe-b-plane-3.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-3/igt@kms_plane@plane-position-hole@pipe-b-plane-3.html

  * igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
    - shard-dg2-set2:     [FAIL][196] ([Intel XE#616]) -> [PASS][197] +3 other tests pass
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-433/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-463/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html

  * igt@kms_plane_scaling@planes-upscale-20x20@pipe-a:
    - {shard-bmg}:        [SKIP][198] ([Intel XE#2763]) -> [PASS][199] +4 other tests pass
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-6/igt@kms_plane_scaling@planes-upscale-20x20@pipe-a.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-7/igt@kms_plane_scaling@planes-upscale-20x20@pipe-a.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [FAIL][200] ([Intel XE#718]) -> [PASS][201]
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-8/igt@kms_pm_dc@dc5-dpms.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-4/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-lnl:          [FAIL][202] ([Intel XE#2029]) -> [PASS][203]
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-5/igt@kms_pm_dc@deep-pkgc.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-3/igt@kms_pm_dc@deep-pkgc.html

  * igt@xe_pm@s3-vm-bind-userptr:
    - {shard-bmg}:        [DMESG-WARN][204] ([Intel XE#569]) -> [PASS][205]
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-bmg-6/igt@xe_pm@s3-vm-bind-userptr.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-bmg-3/igt@xe_pm@s3-vm-bind-userptr.html
    - shard-dg2-set2:     [INCOMPLETE][206] ([Intel XE#1195] / [Intel XE#569]) -> [PASS][207]
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-464/igt@xe_pm@s3-vm-bind-userptr.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-434/igt@xe_pm@s3-vm-bind-userptr.html

  * igt@xe_pm@s4-basic:
    - shard-lnl:          [ABORT][208] ([Intel XE#1358] / [Intel XE#1607]) -> [PASS][209]
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-2/igt@xe_pm@s4-basic.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-7/igt@xe_pm@s4-basic.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-lnl:          [ABORT][210] ([Intel XE#1794]) -> [PASS][211]
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-2/igt@xe_pm@s4-vm-bind-userptr.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-1/igt@xe_pm@s4-vm-bind-userptr.html

  * igt@xe_pm_residency@toggle-gt-c6:
    - shard-lnl:          [FAIL][212] ([Intel XE#958]) -> [PASS][213]
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-4/igt@xe_pm_residency@toggle-gt-c6.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-1/igt@xe_pm_residency@toggle-gt-c6.html

  
#### Warnings ####

  * igt@kms_big_fb@4-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][214] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][215] ([Intel XE#316])
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-436/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][216] ([Intel XE#316]) -> [SKIP][217] ([Intel XE#1201] / [Intel XE#316]) +6 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-434/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][218] ([Intel XE#1124]) -> [SKIP][219] ([Intel XE#1124] / [Intel XE#1201]) +3 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-464/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-dg2-set2:     [SKIP][220] ([Intel XE#619]) -> [SKIP][221] ([Intel XE#1201] / [Intel XE#619])
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_big_fb@y-tiled-addfb.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-463/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-dg2-set2:     [SKIP][222] ([Intel XE#610]) -> [SKIP][223] ([Intel XE#1201] / [Intel XE#610])
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-466/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg2-set2:     [SKIP][224] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][225] ([Intel XE#1124]) +5 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][226] ([Intel XE#367]) -> [SKIP][227] ([Intel XE#1201] / [Intel XE#367]) +1 other test skip
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-466/igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][228] ([Intel XE#2191]) -> [SKIP][229] ([Intel XE#1201] / [Intel XE#2191])
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-463/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
    - shard-dg2-set2:     [SKIP][230] ([Intel XE#1201] / [Intel XE#2191]) -> [SKIP][231] ([Intel XE#2191]) +1 other test skip
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-433/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-2-displays-3840x2160p:
    - shard-dg2-set2:     [SKIP][232] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][233] ([Intel XE#367])
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-435/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][234] ([Intel XE#787]) -> [SKIP][235] ([Intel XE#1201] / [Intel XE#787]) +62 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs:
    - shard-dg2-set2:     [SKIP][236] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][237] ([Intel XE#455] / [Intel XE#787]) +15 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-433/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4:
    - shard-dg2-set2:     [SKIP][238] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][239] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +17 other tests skip
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-464/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][240] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][241] ([Intel XE#787]) +55 other tests skip
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-435/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-dg2-set2:     [SKIP][242] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][243] ([Intel XE#373]) +7 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-466/igt@kms_chamelium_audio@dp-audio.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-dg2-set2:     [SKIP][244] ([Intel XE#306]) -> [SKIP][245] ([Intel XE#1201] / [Intel XE#306])
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_chamelium_color@ctm-0-25.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-464/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_hpd@vga-hpd:
    - shard-dg2-set2:     [SKIP][246] ([Intel XE#373]) -> [SKIP][247] ([Intel XE#1201] / [Intel XE#373]) +7 other tests skip
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_chamelium_hpd@vga-hpd.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-434/igt@kms_chamelium_hpd@vga-hpd.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2-set2:     [SKIP][248] ([Intel XE#307]) -> [SKIP][249] ([Intel XE#1201] / [Intel XE#307])
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_content_protection@dp-mst-lic-type-0.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-466/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-dg2-set2:     [SKIP][250] ([Intel XE#1201] / [Intel XE#307]) -> [SKIP][251] ([Intel XE#307]) +2 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-435/igt@kms_content_protection@dp-mst-type-1.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-dg2-set2:     [SKIP][252] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][253] ([Intel XE#455]) +5 other tests skip
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-435/igt@kms_dsc@dsc-with-bpc.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_flip@bo-too-big-interruptible@a-edp1:
    - shard-lnl:          [TIMEOUT][254] ([Intel XE#1504]) -> [INCOMPLETE][255] ([Intel XE#1504]) +1 other test incomplete
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-lnl-3/igt@kms_flip@bo-too-big-interruptible@a-edp1.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-lnl-8/igt@kms_flip@bo-too-big-interruptible@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2-set2:     [SKIP][256] ([Intel XE#455]) -> [SKIP][257] ([Intel XE#1201] / [Intel XE#455]) +7 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff:
    - shard-dg2-set2:     [SKIP][258] ([Intel XE#651]) -> [SKIP][259] ([Intel XE#1201] / [Intel XE#651]) +19 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-suspend:
    - shard-dg2-set2:     [SKIP][260] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][261] ([Intel XE#651]) +18 other tests skip
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-suspend.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2-set2:     [SKIP][262] ([Intel XE#1201]) -> [SKIP][263] ([Intel XE#658])
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-dg2-set2:     [SKIP][264] ([Intel XE#1201]) -> [SKIP][265] ([Intel XE#1201] / [Intel XE#658])
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][266] ([Intel XE#653]) -> [SKIP][267] ([Intel XE#1201] / [Intel XE#653]) +19 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][268] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][269] ([Intel XE#653]) +19 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d:
    - shard-dg2-set2:     [SKIP][270] ([Intel XE#455]) -> [SKIP][271] ([Intel XE#2763] / [Intel XE#455]) +1 other test skip
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling:
    - shard-dg2-set2:     [SKIP][272] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][273] ([Intel XE#1201] / [Intel XE#2763] / [Intel XE#455]) +11 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-433/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a:
    - shard-dg2-set2:     [SKIP][274] ([Intel XE#2763]) -> [SKIP][275] ([Intel XE#1201] / [Intel XE#2763]) +5 other tests skip
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-434/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b:
    - shard-dg2-set2:     [SKIP][276] ([Intel XE#1201]) -> [SKIP][277] ([Intel XE#1201] / [Intel XE#2763]) +17 other tests skip
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-466/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-434/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d:
    - shard-dg2-set2:     [SKIP][278] ([Intel XE#455]) -> [SKIP][279] ([Intel XE#1201] / [Intel XE#2763] / [Intel XE#455]) +3 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-464/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-dg2-set2:     [SKIP][280] ([Intel XE#1201]) -> [SKIP][281] ([Intel XE#1201] / [Intel XE#870]) +1 other test skip
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@kms_pm_backlight@fade-with-dpms.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-463/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-dg2-set2:     [SKIP][282] ([Intel XE#1201]) -> [SKIP][283] ([Intel XE#870]) +1 other test skip
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-435/igt@kms_pm_backlight@fade-with-suspend.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area:
    - shard-dg2-set2:     [SKIP][284] ([Intel XE#1489]) -> [SKIP][285] ([Intel XE#1201] / [Intel XE#1489]) +2 other tests skip
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-436/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
    - shard-dg2-set2:     [SKIP][286] ([Intel XE#1201]) -> [SKIP][287] ([Intel XE#1201] / [Intel XE#1489]) +18 other tests skip
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-466/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
    - shard-dg2-set2:     [SKIP][288] ([Intel XE#1201]) -> [SKIP][289] ([Intel XE#1489]) +1 other test skip
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-dg2-set2:     [SKIP][290] ([Intel XE#1201]) -> [SKIP][291] ([Intel XE#2850]) +6 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-466/igt@kms_psr@fbc-psr2-primary-render.html
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff:
    - shard-dg2-set2:     [SKIP][292] ([Intel XE#2850]) -> [SKIP][293] ([Intel XE#1201] / [Intel XE#2850]) +8 other tests skip
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-466/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html

  * igt@kms_psr@psr-dpms:
    - shard-dg2-set2:     [SKIP][294] ([Intel XE#1201]) -> [SKIP][295] ([Intel XE#1201] / [Intel XE#2850]) +60 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-464/igt@kms_psr@psr-dpms.html
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@kms_psr@psr-dpms.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-dg2-set2:     [SKIP][296] ([Intel XE#327]) -> [SKIP][297] ([Intel XE#1201] / [Intel XE#327]) +1 other test skip
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_rotation_crc@bad-pixel-format.html
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-436/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2-set2:     [SKIP][298] ([Intel XE#1127] / [Intel XE#1201]) -> [SKIP][299] ([Intel XE#1127])
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-dg2-set2:     [SKIP][300] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][301] ([Intel XE#327]) +2 other tests skip
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-435/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_writeback@writeback-check-output:
    - shard-dg2-set2:     [SKIP][302] ([Intel XE#756]) -> [SKIP][303] ([Intel XE#1201] / [Intel XE#756])
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@kms_writeback@writeback-check-output.html
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-435/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-dg2-set2:     [SKIP][304] ([Intel XE#1201] / [Intel XE#756]) -> [SKIP][305] ([Intel XE#756])
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-435/igt@kms_writeback@writeback-check-output-xrgb2101010.html
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-dg2-set2:     [SKIP][306] ([Intel XE#2849]) -> [SKIP][307] ([Intel XE#1201] / [Intel XE#2849])
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@sriov_basic@enable-vfs-autoprobe-off.html
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-463/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-dg2-set2:     [SKIP][308] ([Intel XE#1201]) -> [SKIP][309] ([Intel XE#1201] / [Intel XE#2849])
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-464/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute:
    - shard-dg2-set2:     [SKIP][310] ([Intel XE#1201] / [Intel XE#1280] / [Intel XE#455]) -> [SKIP][311] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-435/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html

  * igt@xe_evict@evict-mixed-many-threads-large:
    - shard-dg2-set2:     [TIMEOUT][312] ([Intel XE#1473]) -> [FAIL][313] ([Intel XE#1000])
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@xe_evict@evict-mixed-many-threads-large.html
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-435/igt@xe_evict@evict-mixed-many-threads-large.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-imm:
    - shard-dg2-set2:     [SKIP][314] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][315] ([Intel XE#288]) +2 other tests skip
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-463/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-imm.html
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-imm.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind:
    - shard-dg2-set2:     [SKIP][316] ([Intel XE#288]) -> [SKIP][317] ([Intel XE#1201] / [Intel XE#288]) +1 other test skip
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind.html
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-race:
    - shard-dg2-set2:     [SKIP][318] -> [SKIP][319] ([Intel XE#1201]) +11 other tests skip
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@xe_exec_fault_mode@twice-userptr-invalidate-race.html
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-466/igt@xe_exec_fault_mode@twice-userptr-invalidate-race.html

  * igt@xe_live_ktest@xe_bo:
    - shard-dg2-set2:     [TIMEOUT][320] -> [INCOMPLETE][321] ([Intel XE#1195]) +1 other test incomplete
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@xe_live_ktest@xe_bo.html
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-434/igt@xe_live_ktest@xe_bo.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - shard-dg2-set2:     [SKIP][322] ([Intel XE#1201] / [Intel XE#2229]) -> [SKIP][323] ([Intel XE#2229])
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-464/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  * igt@xe_mmap@small-bar:
    - shard-dg2-set2:     [SKIP][324] ([Intel XE#512]) -> [SKIP][325] ([Intel XE#1201] / [Intel XE#512])
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@xe_mmap@small-bar.html
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-434/igt@xe_mmap@small-bar.html

  * igt@xe_oa@closed-fd-and-unmapped-access:
    - shard-dg2-set2:     [SKIP][326] ([Intel XE#1201]) -> [SKIP][327] ([Intel XE#1201] / [Intel XE#2541]) +25 other tests skip
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-436/igt@xe_oa@closed-fd-and-unmapped-access.html
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-435/igt@xe_oa@closed-fd-and-unmapped-access.html

  * igt@xe_oa@disabled-read-error:
    - shard-dg2-set2:     [SKIP][328] ([Intel XE#2541]) -> [SKIP][329] ([Intel XE#1201] / [Intel XE#2541]) +1 other test skip
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@xe_oa@disabled-read-error.html
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-466/igt@xe_oa@disabled-read-error.html

  * igt@xe_oa@enable-disable:
    - shard-dg2-set2:     [SKIP][330] ([Intel XE#1201]) -> [SKIP][331] ([Intel XE#2541]) +1 other test skip
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-435/igt@xe_oa@enable-disable.html
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@xe_oa@enable-disable.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-dg2-set2:     [SKIP][332] ([Intel XE#1337]) -> [SKIP][333] ([Intel XE#1201] / [Intel XE#1337])
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@xe_pat@display-vs-wb-transient.html
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-433/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pat@pat-index-xe2:
    - shard-dg2-set2:     [SKIP][334] ([Intel XE#1201]) -> [SKIP][335] ([Intel XE#1201] / [Intel XE#977])
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-466/igt@xe_pat@pat-index-xe2.html
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-464/igt@xe_pat@pat-index-xe2.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-dg2-set2:     [SKIP][336] ([Intel XE#1201] / [Intel XE#979]) -> [SKIP][337] ([Intel XE#979])
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-434/igt@xe_pat@pat-index-xelpg.html
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-432/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-dg2-set2:     [SKIP][338] ([Intel XE#366]) -> [SKIP][339] ([Intel XE#1201] / [Intel XE#366]) +1 other test skip
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8032/shard-dg2-432/igt@xe_pm@d3cold-mmap-system.html
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/shard-dg2-464/igt@xe_pm@d3cold-mmap-system.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1000]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1000
  [Intel XE#1050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1050
  [Intel XE#1069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1069
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
  [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1288
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
  [Intel XE#1430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1430
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1504
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
  [Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
  [Intel XE#1616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1616
  [Intel XE#1649]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1649
  [Intel XE#1695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1695
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
  [Intel XE#2105]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2105
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
  [Intel XE#2141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2141
  [Intel XE#2159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2159
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2249
  [Intel XE#2251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2251
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2329
  [Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2385
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2425
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2443
  [Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
  [Intel XE#2452]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2452
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2472]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2472
  [Intel XE#2493]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2493
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2687]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2687
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
  [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
  [Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
  [Intel XE#958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/958
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * IGT: IGT_8032 -> IGTPW_11801
  * Linux: xe-1975-abfe8cf977e1abd1f414b2a90d223cd4dd2f1f47 -> xe-1976-88d592f72f7bc508d6a027b1f96aa2e53f803e1b

  IGTPW_11801: 0cde297f64e94e5ef79a198dca1b2e0990945734 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8032: 8032
  xe-1975-abfe8cf977e1abd1f414b2a90d223cd4dd2f1f47: abfe8cf977e1abd1f414b2a90d223cd4dd2f1f47
  xe-1976-88d592f72f7bc508d6a027b1f96aa2e53f803e1b: 88d592f72f7bc508d6a027b1f96aa2e53f803e1b

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11801/index.html

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