[igt-dev] [PATCH i-g-t v6 1/2] include: bump drm uAPI headers

[igt-dev] [PATCH i-g-t v6 1/2] include: bump drm uAPI headers

[Lionel Landwerlin]

For testing only, to be updated with proper commit id from drm-next.
---
 include/drm-uapi/i915_drm.h | 146 +++++++++++++++++++++++++++++++++++++++++++-
 lib/igt_perf.h              |   7 ---
 2 files changed, 145 insertions(+), 8 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 7f28eea4..9dfebbbe 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -102,6 +102,46 @@ enum drm_i915_gem_engine_class {
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
+/**
+ * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
+ *
+ */
+
+enum drm_i915_pmu_engine_sample {
+	I915_SAMPLE_BUSY = 0,
+	I915_SAMPLE_WAIT = 1,
+	I915_SAMPLE_SEMA = 2
+};
+
+#define I915_PMU_SAMPLE_BITS (4)
+#define I915_PMU_SAMPLE_MASK (0xf)
+#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
+#define I915_PMU_CLASS_SHIFT \
+	(I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
+
+#define __I915_PMU_ENGINE(class, instance, sample) \
+	((class) << I915_PMU_CLASS_SHIFT | \
+	(instance) << I915_PMU_SAMPLE_BITS | \
+	(sample))
+
+#define I915_PMU_ENGINE_BUSY(class, instance) \
+	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
+
+#define I915_PMU_ENGINE_WAIT(class, instance) \
+	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
+
+#define I915_PMU_ENGINE_SEMA(class, instance) \
+	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
+
+#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
+
+#define I915_PMU_ACTUAL_FREQUENCY	__I915_PMU_OTHER(0)
+#define I915_PMU_REQUESTED_FREQUENCY	__I915_PMU_OTHER(1)
+#define I915_PMU_INTERRUPTS		__I915_PMU_OTHER(2)
+#define I915_PMU_RC6_RESIDENCY		__I915_PMU_OTHER(3)
+
+#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
+
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
@@ -278,6 +318,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_OPEN		0x36
 #define DRM_I915_PERF_ADD_CONFIG	0x37
 #define DRM_I915_PERF_REMOVE_CONFIG	0x38
+#define DRM_I915_QUERY			0x39
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -335,6 +376,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_OPEN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
+#define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -1318,7 +1360,9 @@ struct drm_intel_overlay_attrs {
  * active on a given plane.
  */
 
-#define I915_SET_COLORKEY_NONE		(1<<0) /* disable color key matching */
+#define I915_SET_COLORKEY_NONE		(1<<0) /* Deprecated. Instead set
+						* flags==0 to disable colorkeying.
+						*/
 #define I915_SET_COLORKEY_DESTINATION	(1<<1)
 #define I915_SET_COLORKEY_SOURCE	(1<<2)
 struct drm_intel_sprite_colorkey {
@@ -1573,6 +1617,106 @@ struct drm_i915_perf_oa_config {
 	__u64 flex_regs_ptr;
 };
 
+struct drm_i915_query_item {
+	__u64 query_id;
+#define DRM_I915_QUERY_TOPOLOGY_INFO    1
+
+	/*
+	 * When set to zero by userspace, this is filled with the size of the
+	 * data to be written at the data_ptr pointer. The kernel set this
+	 * value to a negative value to signal an error on a particular query
+	 * item.
+	 */
+	__s32 length;
+
+	/*
+	 * Unused for now.
+	 */
+	__u32 flags;
+
+	/*
+	 * Data will be written at the location pointed by data_ptr when the
+	 * value of length matches the length of the data to be written by the
+	 * kernel.
+	 */
+	__u64 data_ptr;
+};
+
+struct drm_i915_query {
+	__u32 num_items;
+
+	/*
+	 * Unused for now.
+	 */
+	__u32 flags;
+
+	/*
+	 * This point to an array of num_items drm_i915_query_item structures.
+	 */
+	__u64 items_ptr;
+};
+
+/*
+ * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
+ *
+ * data: contains the 3 pieces of information :
+ *
+ * - the slice mask with one bit per slice telling whether a slice is
+ *   available. The availability of slice X can be queried with the following
+ *   formula :
+ *
+ *           (data[X / 8] >> (X % 8)) & 1
+ *
+ * - the subslice mask for each slice with one bit per subslice telling
+ *   whether a subslice is available. The availability of subslice Y in slice
+ *   X can be queried with the following formula :
+ *
+ *           (data[subslice_offset +
+ *                 X * subslice_stride +
+ *                 Y / 8] >> (Y % 8)) & 1
+ *
+ * - the EU mask for each subslice in each slice with one bit per EU telling
+ *   whether an EU is available. The availability of EU Z in subslice Y in
+ *   slice X can be queried with the following formula :
+ *
+ *           (data[eu_offset +
+ *                 (X * max_subslices Y) * eu_stride +
+ *                 Z / 8] >> (Z % 8)) & 1
+ */
+struct drm_i915_query_topology_info {
+	/*
+	 * Unused for now.
+	 */
+	__u16 flags;
+
+	__u16 max_slices;
+	__u16 max_subslices;
+	__u16 max_eus_per_subslice;
+
+	/*
+	 * Offset in data[] at which the subslice masks are stored.
+	 */
+	__u16 subslice_offset;
+
+	/*
+	 * Stride at which each of the subslice masks for each slice are
+	 * stored.
+	 */
+	__u16 subslice_stride;
+
+	/*
+	 * Offset in data[] at which the EU masks are stored.
+	 */
+	__u16 eu_offset;
+
+	/*
+	 * Stride at which each of the EU masks for each subslice are stored.
+	 */
+	__u16 eu_stride;
+
+	__u8 data[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index 7b66fc58..105b8cd9 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -31,13 +31,6 @@
 
 #include "igt_gt.h"
 
-enum drm_i915_pmu_engine_sample {
-	I915_SAMPLE_BUSY = 0,
-	I915_SAMPLE_WAIT = 1,
-	I915_SAMPLE_SEMA = 2,
-	I915_ENGINE_SAMPLE_MAX /* non-ABI */
-};
-
 #define I915_PMU_SAMPLE_BITS (4)
 #define I915_PMU_SAMPLE_MASK (0xf)
 #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
-- 
2.16.2

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[igt-dev] [PATCH i-g-t v6 2/2] tests: add i915 query tests

[Lionel Landwerlin]

v2: Complete invalid cases (Chris)
    Some styling (to_user_pointer, etc...) (Chris)
    New error check, through item.length (Chris)

v3: Update for new uAPI iteration (Lionel)

v4: Return errno from a single point (Chris)
    Poising checks (Chris)

v5: Add more debug traces (Lionel)
    Update uAPI (Joonas/Lionel)
    Make sure Haswell is tested (Lionel)

v6: s/query_item/query_items/ (Tvrtko)
    test that flags fields != 0 fail (Tvrtko)
    Split kernel writes checks out (Tvrtko)
    Verify that when an EU is available, so is slice & subslice it
    belongs to (same with subslice). (Tvrtko)
    Verify kernel errors out with read only memory (Tvrtko)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/Makefile.sources |   1 +
 tests/i915_query.c     | 397 +++++++++++++++++++++++++++++++++++++++++++++++++
 tests/meson.build      |   1 +
 3 files changed, 399 insertions(+)
 create mode 100644 tests/i915_query.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 4a81ac4a..4e6f5319 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -167,6 +167,7 @@ TESTS_progs = \
 	gen3_render_tiledx_blits \
 	gen3_render_tiledy_blits \
 	gvt_basic \
+	i915_query \
 	kms_3d \
 	kms_addfb_basic \
 	kms_atomic \
diff --git a/tests/i915_query.c b/tests/i915_query.c
new file mode 100644
index 00000000..7e35fb97
--- /dev/null
+++ b/tests/i915_query.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+
+#include <limits.h>
+
+IGT_TEST_DESCRIPTION("Testing the i915 query uAPI.");
+
+static int
+__i915_query(int fd, struct drm_i915_query *q)
+{
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		return -errno;
+	return 0;
+}
+
+static int
+__i915_query_items(int fd, struct drm_i915_query_item *items, uint32_t n_items)
+{
+	struct drm_i915_query q = {
+		.num_items = n_items,
+		.items_ptr = to_user_pointer(items),
+	};
+	return __i915_query(fd, &q);
+}
+
+#define i915_query_items(fd, items, n_items) do { \
+		igt_assert_eq(__i915_query_items(fd, items, n_items), 0); \
+		errno = 0; \
+	} while (0)
+#define i915_query_items_err(fd, items, n_items, err) do { \
+		igt_assert_eq(__i915_query_items(fd, items, n_items), -err); \
+	} while (0)
+
+static bool has_query_supports(int fd)
+{
+	struct drm_i915_query query = {};
+
+	return __i915_query(fd, &query) == 0;
+}
+
+static void test_query_garbage(int fd)
+{
+	struct drm_i915_query query;
+	struct drm_i915_query_item items[2];
+	struct drm_i915_query_item *items_ptr;
+	int i, len, ret;
+
+	/* Query flags field is currently valid only if equals to 0. This might
+	 * change in the future.
+	 */
+	memset(&query, 0, sizeof(query));
+	query.flags = 42;
+	igt_assert_eq(__i915_query(fd, &query), -EINVAL);
+
+	/* Test a couple of invalid pointers. */
+	i915_query_items_err(fd, (void *) ULONG_MAX, 1, EFAULT);
+	i915_query_items_err(fd, (void *) 0, 1, EFAULT);
+
+	/* Test the invalid query id = 0. */
+	memset(items, 0, sizeof(items));
+	i915_query_items_err(fd, items, 1, EINVAL);
+
+	/* Query item flags field is currently valid only if equals to 0.
+	 * Subject to change in the future.
+	 */
+	memset(items, 0, sizeof(items));
+	items[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	items[0].flags = 42;
+	i915_query_items(fd, items, 1);
+	igt_assert_eq(items[0].length, -EINVAL);
+
+	/* Test a couple of invalid query id. */
+	memset(items, 0, sizeof(items));
+	items[0].query_id = ULONG_MAX;
+	items[1].query_id = ULONG_MAX - 2;
+	i915_query_items(fd, items, 2);
+	igt_assert_eq(items[0].length, -EINVAL);
+	igt_assert_eq(items[1].length, -EINVAL);
+
+	/* Test an invalid query item length. */
+	memset(items, 0, sizeof(items));
+	items[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	items[1].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	items[1].length = sizeof(struct drm_i915_query_topology_info) - 1;
+	i915_query_items(fd, items, 2);
+	igt_assert_lte(0, items[0].length);
+	igt_assert_eq(items[1].length, -EINVAL);
+
+	memset(items, 0, sizeof(items));
+	items[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	items[1].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	items[1].length = sizeof(struct drm_i915_query_topology_info) - 1;
+	i915_query_items(fd, items, 2);
+	igt_assert_lte(0, items[0].length);
+	igt_assert_eq(items[1].length, -EINVAL);
+
+	/* Map memory for a query item in which the kernel is going to write the
+	 * length of the item in the first ioctl(). Then unmap that memory and
+	 * verify that the kernel correctly returns EFAULT as memory of the item
+	 * has been removed from our address space.
+	 */
+	items_ptr = mmap(0, 4096, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+	items_ptr[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	i915_query_items(fd, items_ptr, 1);
+	igt_assert(items_ptr[0].length >= sizeof(struct drm_i915_query_topology_info));
+	munmap(items_ptr, 4096);
+	i915_query_items_err(fd, items_ptr, 1, EFAULT);
+
+	/* Map memory for a query item, then make it read only and verify that
+	 * the kernel errors out with EFAULT.
+	 */
+	items_ptr = mmap(0, 4096, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+	items_ptr[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	igt_assert_eq(0, mprotect(items_ptr, 4096, PROT_READ));
+	i915_query_items_err(fd, items_ptr, 1, EFAULT);
+	munmap(items_ptr, 4096);
+
+	/* Map memory for 10 query items and with a valid query id, but tell the
+	 * kernel there are actually INT_MAX / sizeof(query_item) items in our
+	 * query. We should either get an EFAULT or EINVAL at some point as the
+	 * kernel will either read invalid data from another mapping or unmapped
+	 * addresses.
+	 */
+	len = sizeof(struct drm_i915_query_item) * 10;
+	items_ptr = mmap(0, len, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+	for (i = 0; i < 10; i++)
+		items_ptr[i].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	ret = __i915_query_items(fd, items_ptr,
+				 INT_MAX / sizeof(struct drm_i915_query_item) + 1);
+	igt_assert(ret == -EFAULT || ret == -EINVAL);
+	munmap(items_ptr, len);
+}
+
+/* Allocate more on both sides of where the kernel is going to write and verify
+ * that it writes only where it's supposed to.
+ */
+static void test_query_topology_kernel_writes(int fd)
+{
+	struct drm_i915_query_item item;
+	struct drm_i915_query_topology_info *topo_info;
+	uint8_t *_topo_info;
+	int b, total_size;
+
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	i915_query_items(fd, &item, 1);
+	igt_assert_lte(3, item.length);
+
+	total_size = item.length + 2 * sizeof(*_topo_info);
+	_topo_info = malloc(total_size);
+	memset(_topo_info, 0xff, total_size);
+	topo_info = (struct drm_i915_query_topology_info *) (_topo_info + sizeof(*_topo_info));
+	memset(topo_info, 0, item.length);
+
+	for (b = 0; b < sizeof(*_topo_info); b++) {
+		igt_assert_eq(_topo_info[b], 0xff);
+		igt_assert_eq(_topo_info[sizeof(*_topo_info) + item.length + b], 0xff);
+	}
+}
+
+static bool query_topology_supported(int fd)
+{
+	struct drm_i915_query_item item = {
+		.query_id = DRM_I915_QUERY_TOPOLOGY_INFO,
+	};
+
+	return __i915_query_items(fd, &item, 1) == 0 && item.length != -EINVAL;
+}
+
+static void test_query_topology_unsupported(int fd)
+{
+	struct drm_i915_query_item item = {
+		.query_id = DRM_I915_QUERY_TOPOLOGY_INFO,
+	};
+
+	i915_query_items(fd, &item, 1);
+	igt_assert_eq(item.length, -ENODEV);
+}
+
+#define DIV_ROUND_UP(val, div) (ALIGN(val, div) / div)
+
+static bool
+slice_available(const struct drm_i915_query_topology_info *topo_info,
+		int s)
+{
+	return (topo_info->data[s / 8] >> (s % 8)) & 1;
+}
+
+static bool
+subslice_available(const struct drm_i915_query_topology_info *topo_info,
+		   int s, int ss)
+{
+	return (topo_info->data[topo_info->subslice_offset +
+				s * topo_info->subslice_stride +
+				ss / 8] >> (ss % 8)) & 1;
+}
+
+static bool
+eu_available(const struct drm_i915_query_topology_info *topo_info,
+	     int s, int ss, int eu)
+{
+	return (topo_info->data[topo_info->eu_offset +
+				(s * topo_info->max_subslices + ss) * topo_info->eu_stride +
+				eu / 8] >> (eu % 8)) & 1;
+}
+
+static void
+test_query_topology_coherent_slice_mask(int fd)
+{
+	struct drm_i915_query_item item;
+	struct drm_i915_query_topology_info *topo_info;
+	drm_i915_getparam_t gp;
+	int slice_mask, subslice_mask;
+	int s, topology_slices, topology_subslices_slice0;
+
+	gp.param = I915_PARAM_SLICE_MASK;
+	gp.value = &slice_mask;
+	igt_skip_on(igt_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) != 0);
+
+	gp.param = I915_PARAM_SUBSLICE_MASK;
+	gp.value = &subslice_mask;
+	igt_skip_on(igt_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) != 0);
+
+	/* Slices */
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	i915_query_items(fd, &item, 1);
+	/* We expect at least one byte for each slices, subslices & EUs masks. */
+	igt_assert(item.length >= 3);
+
+	topo_info = malloc(item.length);
+	memset(topo_info, 0, item.length);
+
+	item.data_ptr = to_user_pointer(topo_info);
+	i915_query_items(fd, &item, 1);
+	/* We expect at least one byte for each slices, subslices & EUs masks. */
+	igt_assert(item.length >= 3);
+
+	topology_slices = 0;
+	for (s = 0; s < topo_info->max_slices; s++) {
+		if (slice_available(topo_info, s))
+			topology_slices |= 1UL << s;
+	}
+
+	igt_debug("slice mask getparam=0x%x / query=0x%x\n",
+		  slice_mask, topology_slices);
+
+	/* These 2 should always match. */
+	igt_assert_eq_u32(slice_mask, topology_slices);
+
+	topology_subslices_slice0 = 0;
+	for (s = 0; s < topo_info->max_subslices; s++) {
+		if (subslice_available(topo_info, 0, s))
+			topology_subslices_slice0 |= 1UL << s;
+	}
+
+	igt_debug("subslice mask getparam=0x%x / query=0x%x\n",
+		  subslice_mask, topology_subslices_slice0);
+
+	/* I915_PARAM_SUBSLICE_MASK returns the value for slice0, we
+	 * should match the values for the first slice of the
+	 * topology.
+	 */
+	igt_assert_eq_u32(subslice_mask, topology_subslices_slice0);
+
+	free(topo_info);
+}
+
+static void
+test_query_topology_matches_eu_total(int fd)
+{
+	struct drm_i915_query_item item;
+	struct drm_i915_query_topology_info *topo_info;
+	drm_i915_getparam_t gp;
+	int n_eus, n_eus_topology, s;
+
+	gp.param = I915_PARAM_EU_TOTAL;
+	gp.value = &n_eus;
+	do_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+	igt_debug("n_eus=%i\n", n_eus);
+
+	memset(&item, 0, sizeof(item));
+	item.query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
+	i915_query_items(fd, &item, 1);
+
+	topo_info = (struct drm_i915_query_topology_info *) calloc(1, item.length);
+
+	item.data_ptr = to_user_pointer(topo_info);
+	i915_query_items(fd, &item, 1);
+
+	igt_debug("max_slices=%hu max_subslices=%hu max_eus_per_subslice=%hu\n",
+		  topo_info->max_slices, topo_info->max_subslices,
+		  topo_info->max_eus_per_subslice);
+	igt_debug(" subslice_offset=%hu subslice_stride=%hu\n",
+		  topo_info->subslice_offset, topo_info->subslice_stride);
+	igt_debug(" eu_offset=%hu eu_stride=%hu\n",
+		  topo_info->eu_offset, topo_info->eu_stride);
+
+	n_eus_topology = 0;
+	for (s = 0; s < topo_info->max_slices; s++) {
+		int ss;
+
+		igt_debug("slice%i:\n", s);
+
+		for (ss = 0; ss < topo_info->max_subslices; ss++) {
+			int eu, n_subslice_eus = 0;
+
+			igt_debug("\tsubslice: %i\n", ss);
+
+			igt_debug("\t\teu_mask: 0b");
+			for (eu = 0; eu < topo_info->max_eus_per_subslice; eu++) {
+				uint8_t val = eu_available(topo_info, s, ss,
+							   topo_info->max_eus_per_subslice - 1 - eu);
+				igt_debug("%hhi", val);
+				n_subslice_eus += __builtin_popcount(val);
+				n_eus_topology += __builtin_popcount(val);
+			}
+
+			igt_debug(" (%i)\n", n_subslice_eus);
+
+			/* Sanity checks. */
+			if (n_subslice_eus > 0) {
+				igt_assert(slice_available(topo_info, s) &&
+					   subslice_available(topo_info, s, ss));
+			}
+			if (subslice_available(topo_info, s, ss)) {
+				igt_assert(slice_available(topo_info, s));
+			}
+		}
+	}
+
+	igt_assert(n_eus_topology == n_eus);
+}
+
+igt_main
+{
+	int fd = -1;
+	int devid;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_INTEL);
+		igt_require(has_query_supports(fd));
+		devid = intel_get_drm_devid(fd);
+	}
+
+	igt_subtest("query-garbage")
+		test_query_garbage(fd);
+
+	igt_subtest("query-topology-kernel-writes") {
+		igt_require(query_topology_supported(fd));
+		test_query_topology_kernel_writes(fd);
+	}
+
+	igt_subtest("query-topology-unsupported") {
+		igt_require(intel_gen(devid) < 8 && !IS_HASWELL(devid));
+		igt_require(query_topology_supported(fd));
+		test_query_topology_unsupported(fd);
+	}
+
+	igt_subtest("query-topology-coherent-slice-mask") {
+		igt_require(intel_gen(devid) >= 8 || IS_HASWELL(devid));
+		igt_require(query_topology_supported(fd));
+		test_query_topology_coherent_slice_mask(fd);
+	}
+
+	igt_subtest("query-topology-matches-eu-total") {
+		igt_require(intel_gen(devid) >= 8 || IS_HASWELL(devid));
+		igt_require(query_topology_supported(fd));
+		test_query_topology_matches_eu_total(fd);
+	}
+
+	igt_fixture {
+		close(fd);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 58729231..5788dfd0 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -143,6 +143,7 @@ test_progs = [
 	'gen3_render_tiledx_blits',
 	'gen3_render_tiledy_blits',
 	'gvt_basic',
+	'i915_query',
 	'kms_3d',
 	'kms_addfb_basic',
 	'kms_atomic',
-- 
2.16.2

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Re: [igt-dev] [PATCH i-g-t v6 1/2] include: bump drm uAPI headers

[Chris Wilson]

Quoting Lionel Landwerlin (2018-03-08 14:39:59)
> For testing only, to be updated with proper commit id from drm-next.

Surely, we can declare this to be ready with

commit c822e059185585f79b2007b1d2cafacf4264e610
Author: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date:   Tue Mar 6 12:28:57 2018 +0000

    drm/i915: expose rcs topology through query uAPI

? Then this can land.
-Chris
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Re: [igt-dev] [PATCH i-g-t v6 1/2] include: bump drm uAPI headers

[Lionel Landwerlin]

On 08/03/18 14:46, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2018-03-08 14:39:59)
>> For testing only, to be updated with proper commit id from drm-next.
> Surely, we can declare this to be ready with
>
> commit c822e059185585f79b2007b1d2cafacf4264e610
> Author: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Date:   Tue Mar 6 12:28:57 2018 +0000
>
>      drm/i915: expose rcs topology through query uAPI
>
> ? Then this can land.
> -Chris
>
I was told by the drm gods that nothing should land in userspace before 
it hits drm-next :/
At least that seems to be the rule for mesa.
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Re: [igt-dev] [PATCH i-g-t v6 1/2] include: bump drm uAPI headers

[Chris Wilson]

Quoting Lionel Landwerlin (2018-03-08 14:53:52)
> On 08/03/18 14:46, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2018-03-08 14:39:59)
> >> For testing only, to be updated with proper commit id from drm-next.
> > Surely, we can declare this to be ready with
> >
> > commit c822e059185585f79b2007b1d2cafacf4264e610
> > Author: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > Date:   Tue Mar 6 12:28:57 2018 +0000
> >
> >      drm/i915: expose rcs topology through query uAPI
> >
> > ? Then this can land.
> > -Chris
> >
> I was told by the drm gods that nothing should land in userspace before 
> it hits drm-next :/

It's in-flight, the commit id is set. It'll be there in the morning.
-Chris
> 
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[igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v6,1/2] include: bump drm uAPI headers

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,v6,1/2] include: bump drm uAPI headers
URL   : https://patchwork.freedesktop.org/series/39608/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
b4689dce36d0fbd9aec70d5a4b077c43a6b9c254 igt: Remove gen7_forcewake_mt

with latest DRM-Tip kernel build CI_DRM_3897
da319f89899f drm-tip: 2018y-03m-08d-12h-49m-27s UTC integration manifest

Testlist changes:
+igt@i915_query@query-garbage
+igt@i915_query@query-topology-coherent-slice-mask
+igt@i915_query@query-topology-kernel-writes
+igt@i915_query@query-topology-matches-eu-total
+igt@i915_query@query-topology-unsupported

---- Known issues:

Test debugfs_test:
        Subgroup read_all_entries:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713 +1
Test kms_frontbuffer_tracking:
        Subgroup basic:
                fail       -> PASS       (fi-cnl-y3) fdo#103167

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:427s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:424s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:373s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:508s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:279s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:489s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:489s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:485s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:478s
fi-cfl-8700k     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:406s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:579s
fi-cfl-u         total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:513s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:584s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:420s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:292s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:518s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:399s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:413s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:465s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:420s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:470s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:464s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:509s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:584s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:431s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:528s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:535s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:495s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:482s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:422s
fi-snb-2520m     total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:395s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1084/issues.html
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[igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,v6,1/2] include: bump drm uAPI headers

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,v6,1/2] include: bump drm uAPI headers
URL   : https://patchwork.freedesktop.org/series/39608/
State : success

== Summary ==

---- Possible new issues:

Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-primscrn-spr-indfb-draw-render:
                fail       -> PASS       (shard-apl)

---- Known issues:

Test gem_softpin:
        Subgroup noreloc-s3:
                skip       -> PASS       (shard-snb) fdo#103375
Test kms_flip:
        Subgroup 2x-plain-flip-ts-check:
                fail       -> PASS       (shard-hsw) fdo#100368 +1
Test kms_frontbuffer_tracking:
        Subgroup fbc-suspend:
                fail       -> PASS       (shard-apl) fdo#101623
Test kms_rotation_crc:
        Subgroup sprite-rotation-90-pos-100-0:
                fail       -> PASS       (shard-apl) fdo#105185 +4

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185

shard-apl        total:3472 pass:1829 dwarn:1   dfail:0   fail:8   skip:1633 time:12306s
shard-hsw        total:3472 pass:1775 dwarn:1   dfail:0   fail:3   skip:1692 time:11951s
shard-snb        total:3472 pass:1362 dwarn:3   dfail:0   fail:5   skip:2102 time:7192s
Blacklisted hosts:
shard-kbl        total:3425 pass:1927 dwarn:2   dfail:0   fail:8   skip:1487 time:9308s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1084/shards.html
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