* [PATCH i-g-t 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests
@ 2024-11-15 14:11 Gwan-gyeong Mun
2024-11-15 14:11 ` [PATCH i-g-t 1/4] lib/gppgu_shader: Add write to ppgtt offset Gwan-gyeong Mun
` (7 more replies)
0 siblings, 8 replies; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-15 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
Add a pagefault read/write test case so that the xe_eudebug_online test can
validate the invalid access pagefault scenario that the eu thread can cause.
For these tests, use the newly introduced DRM_XE_EUDEBUG_EVENT_PAGEFAULT
event and struct drm_xe_eudebug_event_pagefault.
The added test cases are shown below.
xe_eudebug_online@pagefault-read
xe_eudebug_online@pagefault-write
Gwan-gyeong Mun (2):
lib/gpgpu_shader: Add causing a read pagefault from the eu thread
tests/intel/xe_eudebug_online: Add read/write pagefault online tests
Jonathan Cavitt (2):
lib/gppgu_shader: Add write to ppgtt offset
eudebug: Add eudebug pagefault event declarations
.../drm-uapi-experimental/xe_drm_eudebug.h | 13 ++
lib/gpgpu_shader.c | 201 ++++++++++++++++
lib/gpgpu_shader.h | 3 +
lib/iga64_generated_codes.c | 100 +++++++-
lib/xe/xe_eudebug.c | 11 +
tests/intel/xe_eudebug_online.c | 219 +++++++++++++++++-
6 files changed, 542 insertions(+), 5 deletions(-)
--
2.46.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH i-g-t 1/4] lib/gppgu_shader: Add write to ppgtt offset
2024-11-15 14:11 [PATCH i-g-t 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Gwan-gyeong Mun
@ 2024-11-15 14:11 ` Gwan-gyeong Mun
2024-11-18 13:00 ` Hajda, Andrzej
2024-11-15 14:11 ` [PATCH i-g-t 2/4] lib/gpgpu_shader: Add causing a read pagefault from the eu thread Gwan-gyeong Mun
` (6 subsequent siblings)
7 siblings, 1 reply; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-15 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
From: Jonathan Cavitt <jonathan.cavitt@intel.com>
Create a function that adds the capacity to fill an oword at a given
ppgtt offset with a dword value. Xe2 does this with an Untyped 2D Block
Array Store operation, though older platforms used to do this with a
Media Write Block, so both means are supported.
Suggested-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
lib/gpgpu_shader.c | 109 ++++++++++++++++++++++++++++++++++++
lib/gpgpu_shader.h | 2 +
lib/iga64_generated_codes.c | 81 ++++++++++++++++++++++++++-
3 files changed, 191 insertions(+), 1 deletion(-)
diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
index 4e1b8d5e9..7a2f0d28d 100644
--- a/lib/gpgpu_shader.c
+++ b/lib/gpgpu_shader.c
@@ -652,6 +652,115 @@ void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
", 2, y_offset, 3, value, value, value, value);
}
+/**
+ * gpgpu_shader__write_offset:
+ * @shdr: shader to be modified
+ * @ppgtt_offset: write target virtual address
+ * @value: dword to be written
+ *
+ * Fill oword at @ppgtt with dword stored in @value.
+ *
+ * Note: for the write to succeed, the address specified by @ppgtt_offset has
+ * to be bound. Otherwise a page fault will be triggered.
+ */
+void gpgpu_shader__write_offset(struct gpgpu_shader *shdr, uint64_t ppgtt_offset,
+ uint32_t value)
+{
+ uint64_t offset = CANONICAL(ppgtt_offset);
+ igt_assert_f((offset & 0xf) == 0, "Offset must be aligned to oword!\n");
+
+ emit_iga64_code(shdr, write_offset, " \n\
+#if GEN_VER < 2000 // Media Block Write \n\
+(W) mov (8|M0) r30.0<1>:ud 0x0:ud \n\
+ // canonical address \n\
+(W) mov (1|M0) r30.0<1>:ud ARG(0):ud \n\
+(W) mov (1|M0) r30.1<1>:ud ARG(1):ud \n\
+ // written value \n\
+(W) mov (1|M0) r31.0<1>:ud ARG(2):ud \n\
+(W) mov (1|M0) r31.1<1>:ud ARG(3):ud \n\
+(W) mov (1|M0) r31.2<1>:ud ARG(4):ud \n\
+(W) mov (1|M0) r31.3<1>:ud ARG(5):ud \n\
+ // owblock write \n\
+(W) send.dc1 (16|M0) null r30 r31 0x0 0x20d40ff \n\
+ // owblock read, to block the thread until the write is materialized \n\
+(W) send.dc1 (16|M0) r32 r30 null 0x0 0x21500ff \n\
+#else // Unyped 2D Block Store \n\
+// Instruction_Store2DBlock \n\
+// bspec: 63981 \n\
+// src0 address payload (Untyped2DBLOCKAddressPayload) specifies both \n\
+// the block parameters and the 2D Surface parameters. \n\
+// src1 data payload format is selected by Data Size. \n\
+// Untyped2DBLOCKAddressPayload \n\
+// bspec: 63986 \n\
+// [243:240] Array Length: 0 (length is 1) \n\
+// [239:232] Block Height: 0 (height is 1) \n\
+// [231:224] Block Width: 0xf (width is 16) \n\
+// [223:192] Block Start Y: 0 \n\
+// [191:160] Block Start X: 0 \n\
+// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 bytes) \n\
+// [127:96] Untyped 2D Surface Height: 0 (height is 1) \n\
+// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 bytes) \n\
+// [63:0] Untyped 2D Surface Base Address \n\
+// initialize register \n\
+(W) mov (8) r30.0<1>:uq 0x0:uq \n\
+// [0:31] Untyped 2D Surface Base Address low \n\
+(W) mov (1) r30.0<1>:ud ARG(0):ud \n\
+// [32:63] Untyped 2D Surface Base Address high \n\
+(W) mov (1) r30.1<1>:ud ARG(1):ud \n\
+// [95:64] Untyped 2D Surface Width: 0x3f \n\
+// (Width minus 1 (in bytes) of the 2D surface, it represents 64) \n\
+(W) mov (1) r30.2<1>:ud 0x3f:ud \n\
+// [127:96] Untyped 2D Surface Height: 0x0 \n\
+// (Height minus 1 (in number of data elements) of \n\
+// the Untyped 2D surface, it represents 1) \n\
+(W) mov (1) r30.3<1>:ud 0x0:ud \n\
+// [159:128] Untyped 2D Surface Pitch: 0x3f \n\
+// (Pitch minus 1 (in bytes) of the 2D surface, it represents 64) \n\
+(W) mov (1) r30.4<1>:ud 0x3f:ud \n\
+// [231:224] Block Width: 0xf (15) \n\
+// (Specifies the width minus 1 (in number of data elements) for this \n\
+// rectangular region, it represents 16) \n\
+// Block width (encoded_value + 1) must be a multiple of DW (4 bytes). \n\
+// [239:232] Block Height: 0 \n\
+// (Specifies the height minus 1 (in number of data elements) for \n\
+// this rectangular region, it represents 1) \n\
+// [243:240] Array Length: 0 \n\
+// (Specifies Array Length minus 1 for Load2DBlockArray messages, \n\
+// must be zero for 2D Block Store messages, it represents 1) \n\
+(W) mov (1) r30.7<1>:ud 0xf:ud \n\
+// src1 data payload size \n\
+// Block Height x Block Width x Data size / GRF Register size \n\
+// => 1 x 16 x 32bit / 512bit = 1 \n\
+// data payload size is 1 \n\
+(W) mov (8) r31.0<1>:uq 0x0:uq \n\
+(W) mov (1|M0) r31.0<1>:ud ARG(2):ud \n\
+(W) mov (1|M0) r31.1<1>:ud ARG(3):ud \n\
+(W) mov (1|M0) r31.2<1>:ud ARG(4):ud \n\
+(W) mov (1|M0) r31.3<1>:ud ARG(5):ud \n\
+// send.ugm Untyped 2D Block Array Store \n\
+// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc \n\
+// Execution Mask restriction: SIMT1 \n\
+// \n\
+// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D Block) \n\
+// bspec: 67780 \n\
+// 0x0 => \n\
+// [32:22] Global Y_offset: 0 \n\
+// [21:12] Global X_offset: 0 \n\
+// \n\
+// Message Descriptor \n\
+// bspec: 63981 \n\
+// 0x2020407 => \n\
+// [30:29] Address Type: 0 (FLAT) \n\
+// [28:25] Src0 Length: 1 \n\
+// [24:20] Dest Length: 0 \n\
+// [19:16] Cache : 2 (L1UC_L3UC) \n\
+// [11:9] Data Size: 2 (D32) \n\
+// [5:0] Store Operation: 7 \n\
+(W) send.ugm (1) null r30 r31:1 0x0 0x2020407 \n\
+#endif \n\
+ ", offset & 0xffffffff, offset >> 32, value, value, value, value);
+}
+
/**
* gpgpu_shader__clear_exception:
* @shdr: shader to be modified
diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
index c7c21c115..355b128b5 100644
--- a/lib/gpgpu_shader.h
+++ b/lib/gpgpu_shader.h
@@ -83,6 +83,8 @@ void gpgpu_shader__write_aip(struct gpgpu_shader *shdr, uint32_t y_offset);
void gpgpu_shader__increase_aip(struct gpgpu_shader *shdr, uint32_t value);
void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
uint32_t y_offset);
+void gpgpu_shader__write_offset(struct gpgpu_shader *shdr, uint64_t ppgtt_offset,
+ uint32_t value);
void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
uint32_t y_offset, uint32_t mask, uint32_t value);
void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
index 6638be07b..b23613ac4 100644
--- a/lib/iga64_generated_codes.c
+++ b/lib/iga64_generated_codes.c
@@ -3,7 +3,7 @@
#include "gpgpu_shader.h"
-#define MD5_SUM_IGA64_ASMS ec9d477415eebb7d6983395f1bcde78f
+#define MD5_SUM_IGA64_ASMS 4fcde43dedb9d3212f1d85b5b180b0c1
struct iga64_template const iga64_code_gpgpu_fill[] = {
{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
@@ -323,6 +323,85 @@ struct iga64_template const iga64_code_clear_exception[] = {
}}
};
+struct iga64_template const iga64_code_write_offset[] = {
+ { .gen_ver = 2000, .size = 64, .code = (const uint32_t []) {
+ 0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
+ 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
+ 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
+ 0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
+ 0x80000061, 0x1e354220, 0x00000000, 0x00000000,
+ 0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
+ 0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
+ 0x800c0061, 0x1f054330, 0x00000000, 0x00000000,
+ 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
+ 0x80000061, 0x1f154220, 0x00000000, 0xc0ded003,
+ 0x80000061, 0x1f254220, 0x00000000, 0xc0ded004,
+ 0x80000061, 0x1f354220, 0x00000000, 0xc0ded005,
+ 0x80032031, 0x00000000, 0xf80e1e0c, 0x00801f0c,
+ 0x80000001, 0x00010000, 0x20000000, 0x00000000,
+ 0x80000001, 0x00010000, 0x30000000, 0x00000000,
+ 0x80000901, 0x00010000, 0x00000000, 0x00000000,
+ }},
+ { .gen_ver = 1270, .size = 52, .code = (const uint32_t []) {
+ 0x80030061, 0x1e054220, 0x00000000, 0x00000000,
+ 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
+ 0x80000061, 0x1e254220, 0x00000000, 0xc0ded001,
+ 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
+ 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
+ 0x80000061, 0x1f454220, 0x00000000, 0xc0ded004,
+ 0x80000061, 0x1f654220, 0x00000000, 0xc0ded005,
+ 0x80001d01, 0x00010000, 0x00000000, 0x00000000,
+ 0x80044031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
+ 0x80044131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
+ 0x80000001, 0x00010000, 0x20000000, 0x00000000,
+ 0x80000001, 0x00010000, 0x30000000, 0x00000000,
+ 0x80000901, 0x00010000, 0x00000000, 0x00000000,
+ }},
+ { .gen_ver = 1260, .size = 48, .code = (const uint32_t []) {
+ 0x800c0061, 0x1e054220, 0x00000000, 0x00000000,
+ 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
+ 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
+ 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
+ 0x80000061, 0x1f154220, 0x00000000, 0xc0ded003,
+ 0x80000061, 0x1f254220, 0x00000000, 0xc0ded004,
+ 0x80000061, 0x1f354220, 0x00000000, 0xc0ded005,
+ 0x8013a031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
+ 0x8010c131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
+ 0x80000001, 0x00010000, 0x20000000, 0x00000000,
+ 0x80000001, 0x00010000, 0x30000000, 0x00000000,
+ 0x80000901, 0x00010000, 0x00000000, 0x00000000,
+ }},
+ { .gen_ver = 1250, .size = 52, .code = (const uint32_t []) {
+ 0x80030061, 0x1e054220, 0x00000000, 0x00000000,
+ 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
+ 0x80000061, 0x1e254220, 0x00000000, 0xc0ded001,
+ 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
+ 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
+ 0x80000061, 0x1f454220, 0x00000000, 0xc0ded004,
+ 0x80000061, 0x1f654220, 0x00000000, 0xc0ded005,
+ 0x80001d01, 0x00010000, 0x00000000, 0x00000000,
+ 0x80044031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
+ 0x80044131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
+ 0x80000001, 0x00010000, 0x20000000, 0x00000000,
+ 0x80000001, 0x00010000, 0x30000000, 0x00000000,
+ 0x80000901, 0x00010000, 0x00000000, 0x00000000,
+ }},
+ { .gen_ver = 0, .size = 48, .code = (const uint32_t []) {
+ 0x80030061, 0x1e054220, 0x00000000, 0x00000000,
+ 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
+ 0x80000061, 0x1e254220, 0x00000000, 0xc0ded001,
+ 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
+ 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
+ 0x80000061, 0x1f454220, 0x00000000, 0xc0ded004,
+ 0x80000061, 0x1f654220, 0x00000000, 0xc0ded005,
+ 0x8004d031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
+ 0x80044131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
+ 0x80000001, 0x00010000, 0x20000000, 0x00000000,
+ 0x80000001, 0x00010000, 0x30000000, 0x00000000,
+ 0x80000101, 0x00010000, 0x00000000, 0x00000000,
+ }}
+};
+
struct iga64_template const iga64_code_media_block_write[] = {
{ .gen_ver = 2000, .size = 56, .code = (const uint32_t []) {
0x80100061, 0x04054220, 0x00000000, 0x00000000,
--
2.46.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH i-g-t 2/4] lib/gpgpu_shader: Add causing a read pagefault from the eu thread
2024-11-15 14:11 [PATCH i-g-t 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Gwan-gyeong Mun
2024-11-15 14:11 ` [PATCH i-g-t 1/4] lib/gppgu_shader: Add write to ppgtt offset Gwan-gyeong Mun
@ 2024-11-15 14:11 ` Gwan-gyeong Mun
2024-11-18 13:08 ` Hajda, Andrzej
2024-11-19 11:38 ` Manszewski, Christoph
2024-11-15 14:11 ` [PATCH i-g-t 3/4] eudebug: Add eudebug pagefault event declarations Gwan-gyeong Mun
` (5 subsequent siblings)
7 siblings, 2 replies; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-15 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
Create a function that causing a read pagefault using the eu thread load
instruction. If the given ppgtt address points to an unallocated ppgtt
virtual address, this shader can cause a read pagefault.
To directly use a 64-bit address as an argument, use the
Untyped 2D Block Array Load Instruction.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
lib/gpgpu_shader.c | 92 +++++++++++++++++++++++++++++++++++++
lib/gpgpu_shader.h | 1 +
lib/iga64_generated_codes.c | 21 ++++++++-
3 files changed, 113 insertions(+), 1 deletion(-)
diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
index 7a2f0d28d..d7c47be80 100644
--- a/lib/gpgpu_shader.c
+++ b/lib/gpgpu_shader.c
@@ -912,3 +912,95 @@ void gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
", 0x807fffff, /* leave breakpoint exception */
y_offset, value, 0x7fffff /* clear all exceptions */ );
}
+
+/**
+ * gpgpu_shader__read_page_fault:
+ * @shdr: shader to be modified
+ * @ppgtt_addr: ppgtt virtual address to raise pagefault
+ *
+ * For a given arbitrary ppgtt virtual address, it raises a pagefault using
+ * the eu thread load instruction.
+ */
+void gpgpu_shader__read_page_fault(struct gpgpu_shader *shdr, uint64_t ppgtt_addr)
+{
+ /* pagefault ppgtt virtual address */
+ uint64_t addr = CANONICAL(ppgtt_addr);
+
+ igt_assert_f((addr & 0x3) == 0, "address must be aligned to DWord!\n");
+
+ emit_iga64_code(shdr, read_page_fault, " \n\
+#if GEN_VER >= 2000 \n\
+// Unyped 2D Block Array Load \n\
+// Instruction_Load2DBlockArray \n\
+// bspec: 63972 \n\
+// src0 address payload (Untyped2DBLOCKAddressPayload) specifies both \n\
+// the block parameters and the 2D Surface parameters. \n\
+// Untyped2DBLOCKAddressPayload \n\
+// bspec: 63986 \n\
+// [243:240] Array Length: 0 (length is 1) \n\
+// [239:232] Block Height: 0 (height is 1) \n\
+// [231:224] Block Width: 0xf (width is 16) \n\
+// [223:192] Block Start Y: 0 \n\
+// [191:160] Block Start X: 0 \n\
+// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 bytes) \n\
+// [127:96] Untyped 2D Surface Height: 0 (height is 1) \n\
+// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 bytes) \n\
+// [63:0] Untyped 2D Surface Base Address \n\
+// initialize register \n\
+(W) mov (8) r30.0<1>:uq 0x0:uq \n\
+// [0:31] Untyped 2D Surface Base Address low \n\
+(W) mov (1) r30.0<1>:ud ARG(0):ud \n\
+// [32:63] Untyped 2D Surface Base Address high \n\
+(W) mov (1) r30.1<1>:ud ARG(1):ud \n\
+// [95:64] Untyped 2D Surface Width: 0x3f \n\
+// (Width minus 1 (in bytes) of the 2D surface, it represents 64) \n\
+(W) mov (1) r30.2<1>:ud 0x3f:ud \n\
+// [127:96] Untyped 2D Surface Height: 0x0 \n\
+// (Height minus 1 (in number of data elements) of \n\
+// the Untyped 2D surface, it represents 1) \n\
+(W) mov (1) r30.3<1>:ud 0x0:ud \n\
+// [159:128] Untyped 2D Surface Pitch: 0x3f \n\
+// (Pitch minus 1 (in bytes) of the 2D surface, it represents 64) \n\
+(W) mov (1) r30.4<1>:ud 0x3f:ud \n\
+// [231:224] Block Width: 0xf (15) \n\
+// (Specifies the width minus 1 (in number of data elements) for this \n\
+// rectangular region, it represents 16) \n\
+// Block width (encoded_value + 1) must be a multiple of DW (4 bytes). \n\
+// [239:232] Block Height: 0 \n\
+// (Specifies the height minus 1 (in number of data elements) for \n\
+// this rectangular region, it represents 1) \n\
+// [243:240] Array Length: 0 \n\
+// (Specifies Array Length minus 1 for Load2DBlockArray messages, \n\
+// must be zero for 2D Block Store messages, it represents 1) \n\
+(W) mov (1) r30.7<1>:ud 0xf:ud \n\
+// \n\
+// dest data payload format is selected by Data Size. \n\
+// Block Height x Block Width x Data size / GRF Register size \n\
+// => 1 x 16 x 32bit / 512bit = 1 \n\
+// data payload format size is 1 GRF Register. \n\
+// \n\
+// send.ugm Untyped 2D Block Array Load \n\
+// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc \n\
+// Execution Mask restriction: SIMT1 \n\
+// \n\
+// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D Block) \n\
+// bspec: 67780 \n\
+// 0x0 => \n\
+// [32:22] Global Y_offset: 0 \n\
+// [21:12] Global X_offset: 0 \n\
+// \n\
+// Message Descriptor \n\
+// bspec: 63972 \n\
+// 0x2128403 => \n\
+// [30:29] Address Type: 0 (FLAT) \n\
+// [28:25] Src0 Length: 1 \n\
+// [24:20] Dest Length: 1 \n\
+// [19:16] Cache : 2 (L1UC_L3UC) 10 \n\
+// [15] Transpose Block: 1 \n\
+// [11:9] Data Size: 2 (D32) 10 \n\
+// [7] VNNI Transform: 0 \n\
+// [5:0] Load Operation: 3 (Load 2D Block) 11 \n\
+(W) send.ugm (1) r31 r30 null 0x0 0x2128403 \n\
+#endif \n\
+ ", lower_32_bits(addr), upper_32_bits(addr));
+}
\ No newline at end of file
diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
index 355b128b5..318550c52 100644
--- a/lib/gpgpu_shader.h
+++ b/lib/gpgpu_shader.h
@@ -87,6 +87,7 @@ void gpgpu_shader__write_offset(struct gpgpu_shader *shdr, uint64_t ppgtt_offset
uint32_t value);
void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
uint32_t y_offset, uint32_t mask, uint32_t value);
+void gpgpu_shader__read_page_fault(struct gpgpu_shader *shdr, uint64_t ppgtt_addr);
void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
index b23613ac4..53a705358 100644
--- a/lib/iga64_generated_codes.c
+++ b/lib/iga64_generated_codes.c
@@ -3,7 +3,7 @@
#include "gpgpu_shader.h"
-#define MD5_SUM_IGA64_ASMS 4fcde43dedb9d3212f1d85b5b180b0c1
+#define MD5_SUM_IGA64_ASMS 01290b5ecda7a6e765463558d6f59952
struct iga64_template const iga64_code_gpgpu_fill[] = {
{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
@@ -79,6 +79,25 @@ struct iga64_template const iga64_code_gpgpu_fill[] = {
}}
};
+struct iga64_template const iga64_code_read_page_fault[] = {
+ { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
+ 0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
+ 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
+ 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
+ 0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
+ 0x80000061, 0x1e354220, 0x00000000, 0x00000000,
+ 0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
+ 0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
+ 0x80032031, 0x1f0c0000, 0xf8061e0c, 0x00a00000,
+ 0x80000001, 0x00010000, 0x20000000, 0x00000000,
+ 0x80000001, 0x00010000, 0x30000000, 0x00000000,
+ 0x80000901, 0x00010000, 0x00000000, 0x00000000,
+ }},
+ { .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
+
+ }}
+};
+
struct iga64_template const iga64_code_end_system_routine_step_if_eq[] = {
{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
0x80000966, 0x80018220, 0x02008000, 0x00008000,
--
2.46.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH i-g-t 3/4] eudebug: Add eudebug pagefault event declarations
2024-11-15 14:11 [PATCH i-g-t 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Gwan-gyeong Mun
2024-11-15 14:11 ` [PATCH i-g-t 1/4] lib/gppgu_shader: Add write to ppgtt offset Gwan-gyeong Mun
2024-11-15 14:11 ` [PATCH i-g-t 2/4] lib/gpgpu_shader: Add causing a read pagefault from the eu thread Gwan-gyeong Mun
@ 2024-11-15 14:11 ` Gwan-gyeong Mun
2024-11-18 16:52 ` Hajda, Andrzej
2024-11-19 12:26 ` Manszewski, Christoph
2024-11-15 14:11 ` [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests Gwan-gyeong Mun
` (4 subsequent siblings)
7 siblings, 2 replies; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-15 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
From: Jonathan Cavitt <jonathan.cavitt@intel.com>
Update the xe_eudebug drm to include pagefault events.
Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
include/drm-uapi-experimental/xe_drm_eudebug.h | 13 +++++++++++++
lib/xe/xe_eudebug.c | 11 +++++++++++
2 files changed, 24 insertions(+)
diff --git a/include/drm-uapi-experimental/xe_drm_eudebug.h b/include/drm-uapi-experimental/xe_drm_eudebug.h
index f50051e9a..ed2e728c2 100644
--- a/include/drm-uapi-experimental/xe_drm_eudebug.h
+++ b/include/drm-uapi-experimental/xe_drm_eudebug.h
@@ -154,6 +154,7 @@ struct drm_xe_eudebug_event {
#define DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE 9
#define DRM_XE_EUDEBUG_EVENT_METADATA 10
#define DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_METADATA 11
+#define DRM_XE_EUDEBUG_EVENT_PAGEFAULT 12
__u16 flags;
#define DRM_XE_EUDEBUG_EVENT_CREATE (1 << 0)
@@ -352,6 +353,18 @@ struct drm_xe_eudebug_event_vm_bind_op_metadata {
__u64 metadata_cookie;
};
+struct drm_xe_eudebug_event_pagefault {
+ struct drm_xe_eudebug_event base;
+
+ __u64 client_handle;
+ __u64 exec_queue_handle;
+ __u64 lrc_handle;
+ __u32 flags;
+ __u32 bitmask_size;
+ __u64 pagefault_address;
+ __u8 bitmask[];
+};
+
#if defined(__cplusplus)
}
#endif
diff --git a/lib/xe/xe_eudebug.c b/lib/xe/xe_eudebug.c
index c5814421b..de01e6b49 100644
--- a/lib/xe/xe_eudebug.c
+++ b/lib/xe/xe_eudebug.c
@@ -91,6 +91,8 @@ static const char *type_to_str(unsigned int type)
return "metadata";
case DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_METADATA:
return "vm_bind_op_metadata";
+ case DRM_XE_EUDEBUG_EVENT_PAGEFAULT:
+ return "pagefault";
}
return "UNKNOWN";
@@ -222,6 +224,15 @@ static const char *event_members_to_str(struct drm_xe_eudebug_event *e, char *bu
op->vm_bind_op_ref_seqno, op->metadata_handle, op->metadata_cookie);
break;
}
+ case DRM_XE_EUDEBUG_EVENT_PAGEFAULT: {
+ struct drm_xe_eudebug_event_pagefault *pf = (void *)e;
+
+ sprintf(buf, "client_handle=%llu, exec_queue_handle=%llu, "
+ "lrc_handle=%llu, bitmask_size=%d, pagefault_address=0x%llx",
+ pf->client_handle, pf->exec_queue_handle, pf->lrc_handle,
+ pf->bitmask_size, pf->pagefault_address);
+ break;
+ }
default:
strcpy(buf, "<...>");
}
--
2.46.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests
2024-11-15 14:11 [PATCH i-g-t 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Gwan-gyeong Mun
` (2 preceding siblings ...)
2024-11-15 14:11 ` [PATCH i-g-t 3/4] eudebug: Add eudebug pagefault event declarations Gwan-gyeong Mun
@ 2024-11-15 14:11 ` Gwan-gyeong Mun
2024-11-19 8:10 ` Hajda, Andrzej
` (2 more replies)
2024-11-15 14:42 ` ✓ CI.xeBAT: success for tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Patchwork
` (3 subsequent siblings)
7 siblings, 3 replies; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-15 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
Add read and write pagefault tests to xe_eudebug_online that checks if a
pagefault event is submitted by the KMD debugger when a pagefault occurs.
Test that read (load instruction) and write(store instruction) attempt to
load or store access to unallocated memory, causing a pagefault.
Examine the address causing the page fault and the number of eu threads
causing the pagefault.
Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
tests/intel/xe_eudebug_online.c | 219 +++++++++++++++++++++++++++++++-
1 file changed, 215 insertions(+), 4 deletions(-)
diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/xe_eudebug_online.c
index 0ef0d8093..eae0eb520 100644
--- a/tests/intel/xe_eudebug_online.c
+++ b/tests/intel/xe_eudebug_online.c
@@ -36,6 +36,8 @@
#define BB_IN_VRAM (1 << 11)
#define TARGET_IN_SRAM (1 << 12)
#define TARGET_IN_VRAM (1 << 13)
+#define SHADER_PAGEFAULT_READ (1 << 14)
+#define SHADER_PAGEFAULT_WRITE (1 << 15)
#define TRIGGER_UFENCE_SET_BREAKPOINT (1 << 24)
#define TRIGGER_RESUME_SINGLE_WALK (1 << 25)
#define TRIGGER_RESUME_PARALLEL_WALK (1 << 26)
@@ -45,6 +47,7 @@
#define TRIGGER_RESUME_DSS (1 << 30)
#define TRIGGER_RESUME_ONE (1 << 31)
+#define SHADER_PAGEFAULT (SHADER_PAGEFAULT_READ | SHADER_PAGEFAULT_WRITE)
#define BB_REGION_BITMASK (BB_IN_SRAM | BB_IN_VRAM)
#define TARGET_REGION_BITMASK (TARGET_IN_SRAM | TARGET_IN_VRAM)
@@ -61,6 +64,8 @@
#define CACHING_VALUE(n) (CACHING_INIT_VALUE + (n))
#define SHADER_CANARY 0x01010101
+#define BAD_CANARY 0xf1f1f1f
+#define BAD_OFFSET (0x12345678ull << 12)
#define WALKER_X_DIM 4
#define WALKER_ALIGNMENT 16
@@ -123,6 +128,9 @@ static int get_number_of_threads(uint64_t flags)
if (flags & SHADER_MIN_THREADS)
return 16;
+ if (flags & SHADER_PAGEFAULT)
+ return 16;
+
if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
TRIGGER_RESUME_PARALLEL_WALK | SHADER_CACHING_SRAM | SHADER_CACHING_VRAM))
return 32;
@@ -179,6 +187,16 @@ static struct gpgpu_shader *get_shader(int fd, const unsigned int flags)
gpgpu_shader__common_target_write_u32(shader, s_dim.y + i, CACHING_VALUE(i));
gpgpu_shader__nop(shader);
gpgpu_shader__breakpoint(shader);
+ } else if (flags & SHADER_PAGEFAULT) {
+ if (flags & SHADER_PAGEFAULT_READ)
+ gpgpu_shader__read_page_fault(shader, BAD_OFFSET);
+ else if (flags & SHADER_PAGEFAULT_WRITE)
+ gpgpu_shader__write_offset(shader, BAD_OFFSET, BAD_CANARY);
+
+ gpgpu_shader__label(shader, 0);
+ gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
+ gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
+ gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
}
gpgpu_shader__eot(shader);
@@ -217,6 +235,17 @@ static int count_set_bits(void *ptr, size_t size)
return count;
}
+static int
+eu_attentions_xor_count(const uint32_t *a, const uint32_t *b, uint32_t size)
+{
+ int count = 0;
+
+ for (int i = 0; i < size / 4 ; i++)
+ count += igt_hweight(a[i] ^ b[i]);
+
+ return count;
+}
+
static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim, uint32_t value)
{
int count = 0;
@@ -636,7 +665,7 @@ static void eu_attention_resume_trigger(struct xe_eudebug_debugger *d,
}
}
- if (d->flags & SHADER_LOOP) {
+ if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
uint32_t threads = get_number_of_threads(d->flags);
uint32_t val = STEERING_END_LOOP;
@@ -746,6 +775,43 @@ static void eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
data->single_step_bitmask[i] &= ~att->bitmask[i];
}
+static void eu_attention_resume_pagefault_trigger(struct xe_eudebug_debugger *d,
+ struct drm_xe_eudebug_event *e)
+{
+ struct drm_xe_eudebug_event_eu_attention *att = (void *) e;
+ struct online_debug_data *data = d->ptr;
+ uint32_t bitmask_size = att->bitmask_size;
+ uint8_t *bitmask;
+
+ if (data->last_eu_control_seqno > att->base.seqno)
+ return;
+
+ bitmask = calloc(1, att->bitmask_size);
+
+ eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
+ att->lrc_handle, bitmask, &bitmask_size);
+ igt_assert(bitmask_size == att->bitmask_size);
+
+ pthread_mutex_lock(&data->mutex);
+
+ if (d->flags & SHADER_PAGEFAULT) {
+ uint32_t threads = get_number_of_threads(d->flags);
+ uint32_t val = STEERING_END_LOOP;
+
+ igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
+ data->target_offset + steering_offset(threads)),
+ sizeof(uint32_t));
+ fsync(data->vm_fd);
+ }
+ pthread_mutex_unlock(&data->mutex);
+
+ data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, att->client_handle,
+ att->exec_queue_handle, att->lrc_handle,
+ bitmask, att->bitmask_size);
+
+ free(bitmask);
+}
+
static void open_trigger(struct xe_eudebug_debugger *d,
struct drm_xe_eudebug_event *e)
{
@@ -1015,7 +1081,7 @@ static void run_online_client(struct xe_eudebug_client *c)
struct intel_bb *ibb;
struct intel_buf *buf;
uint32_t *ptr;
- int fd;
+ int fd, vm_flags;
metadata[0] = calloc(2, sizeof(*metadata));
metadata[1] = calloc(2, sizeof(*metadata));
@@ -1025,7 +1091,7 @@ static void run_online_client(struct xe_eudebug_client *c)
fd = xe_eudebug_client_open_driver(c);
/* Additional memory for steering control */
- if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
+ if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c->flags & SHADER_PAGEFAULT)
s_dim.y++;
/* Additional memory for caching check */
if ((c->flags & SHADER_CACHING_SRAM) || (c->flags & SHADER_CACHING_VRAM))
@@ -1045,7 +1111,11 @@ static void run_online_client(struct xe_eudebug_client *c)
DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
2 * sizeof(*metadata), metadata[1]);
- create.vm_id = xe_eudebug_client_vm_create(c, fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
+ vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
+ vm_flags |= c->flags & SHADER_PAGEFAULT ? DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
+
+ create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
+
xe_eudebug_client_exec_queue_create(c, fd, &create);
ibb = xe_bb_create_on_offset(fd, create.exec_queue_id, create.vm_id, bb_offset, bb_size,
@@ -1245,11 +1315,14 @@ match_attention_with_exec_queue(struct xe_eudebug_event_log *log,
static void online_session_check(struct xe_eudebug_session *s, int flags)
{
struct drm_xe_eudebug_event_eu_attention *ea = NULL;
+ struct drm_xe_eudebug_event_pagefault *pf = NULL;
struct drm_xe_eudebug_event *event = NULL;
struct online_debug_data *data = s->client->ptr;
bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
int sum = 0;
int bitmask_size;
+ int pagefault_threads = 0;
+ uint32_t *ptr = NULL;
xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
@@ -1265,6 +1338,16 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
igt_assert_eq(ea->bitmask_size, bitmask_size);
sum += count_set_bits(ea->bitmask, bitmask_size);
igt_assert(match_attention_with_exec_queue(s->debugger->log, ea));
+ } else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
+ uint32_t after_offset = bitmask_size / sizeof(uint32_t);
+ uint32_t resolved_offset = bitmask_size / sizeof(uint32_t) * 2;
+
+ pf = (struct drm_xe_eudebug_event_pagefault *)event;
+ ptr = (uint32_t *) pf->bitmask;
+ igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
+ pagefault_threads += eu_attentions_xor_count(ptr + after_offset,
+ ptr + resolved_offset,
+ bitmask_size);
}
}
@@ -1279,6 +1362,9 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
igt_assert(sum > 0);
else
igt_assert(sum == 0);
+
+ if (flags & SHADER_PAGEFAULT)
+ igt_assert(pagefault_threads > 0);
}
static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
@@ -1302,6 +1388,55 @@ static void ufence_ack_set_bp_trigger(struct xe_eudebug_debugger *d,
}
}
+static void pagefault_trigger(struct xe_eudebug_debugger *d,
+ struct drm_xe_eudebug_event *e)
+{
+ struct drm_xe_eudebug_event_pagefault *pf = (void *) e;
+ int before_threads, after_threads, resolved_threads, pagefault_threads;
+ uint32_t attn_size = pf->bitmask_size / 3;
+ uint32_t *ptr = (uint32_t *) pf->bitmask;
+ uint32_t offset, before_offset = 0;
+ uint32_t after_offset = attn_size / sizeof(uint32_t);
+ uint32_t resolved_offset = attn_size / sizeof(uint32_t) * 2;
+
+ before_threads = count_set_bits(ptr + before_offset, attn_size);
+ after_threads = count_set_bits(ptr + after_offset, attn_size);
+ resolved_threads = count_set_bits(ptr + resolved_offset, attn_size);
+
+ pagefault_threads = eu_attentions_xor_count(ptr + after_offset,
+ ptr + resolved_offset,
+ attn_size);
+
+ igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
+ "resolved=%d, pagefault=%d] "
+ "client[%llu], exec_queue[%llu], lrc[%llu], bitmask_size[%d], "
+ "pagefault_address[0x%llx]\n",
+ pf->base.seqno, before_threads, after_threads, resolved_threads,
+ pagefault_threads, pf->client_handle, pf->exec_queue_handle,
+ pf->lrc_handle, pf->bitmask_size,
+ pf->pagefault_address);
+
+ for (int idx = 0; idx < 3; idx++) {
+ if (idx == 0) {
+ igt_debug("=== Attentions before ===\n");
+ offset = before_offset;
+ } else if (idx == 1) {
+ igt_debug("=== Attentions after ===\n");
+ offset = after_offset;
+ } else {
+ igt_debug("=== Attentions resolved ===\n");
+ offset = resolved_offset;
+ }
+
+ for (uint32_t i = 0; i < attn_size / sizeof(uint32_t); i += 2)
+ igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
+ ptr[offset + i], ptr[offset + i + 1]);
+ }
+
+ igt_assert(pagefault_threads > 0);
+ igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
+}
+
/**
* SUBTEST: basic-breakpoint
* Description:
@@ -1383,6 +1518,77 @@ static void test_set_breakpoint_online(int fd, struct drm_xe_engine_class_instan
online_debug_data_destroy(data);
}
+/**
+ * SUBTEST: pagefault-read
+ * Description:
+ * Check whether KMD sends pagefault event for workload in debug mode that
+ * triggers a read pagefault.
+ *
+ * SUBTEST: pagefault-write
+ * Description:
+ * Check whether KMD sends pagefault event for workload in debug mode that
+ * triggers a write pagefault.
+ */
+static void test_pagefault_online(int fd, struct drm_xe_engine_class_instance *hwe,
+ int flags)
+{
+ struct xe_eudebug_session *s;
+ struct online_debug_data *data;
+ uint32_t val;
+
+ data = online_debug_data_create(hwe);
+ s = xe_eudebug_session_create(fd, run_online_client, flags, data);
+
+ xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_OPEN,
+ open_trigger);
+ xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
+ exec_queue_trigger);
+ xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
+ eu_attention_debug_trigger);
+ xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
+ eu_attention_resume_pagefault_trigger);
+ xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
+ xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_METADATA,
+ create_metadata_trigger);
+ xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
+ ufence_ack_trigger);
+ xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
+ pagefault_trigger);
+
+ igt_assert_eq(xe_eudebug_debugger_attach(s->debugger, s->client), 0);
+ xe_eudebug_debugger_start_worker(s->debugger);
+ xe_eudebug_client_start(s->client);
+
+ /* wait for workload to start */
+ igt_for_milliseconds(STARTUP_TIMEOUT_MS) {
+ /* collect needed data from triggers */
+ if (READ_ONCE(data->vm_fd) == -1 || READ_ONCE(data->target_size) == 0)
+ continue;
+
+ if (pread(data->vm_fd, &val, sizeof(val), data->target_offset) == sizeof(val))
+ if (val != 0)
+ break;
+ }
+
+ pthread_mutex_lock(&data->mutex);
+ igt_assert(data->client_handle != -1);
+ igt_assert(data->exec_queue_handle != -1);
+
+ pthread_mutex_unlock(&data->mutex);
+
+ xe_eudebug_client_wait_done(s->client);
+
+ xe_eudebug_debugger_stop_worker(s->debugger, 1);
+
+ xe_eudebug_event_log_print(s->debugger->log, true);
+ xe_eudebug_event_log_print(s->client->log, true);
+
+ online_session_check(s, s->flags);
+
+ xe_eudebug_session_destroy(s);
+ online_debug_data_destroy(data);
+}
+
/**
* SUBTEST: preempt-breakpoint
* Description:
@@ -2344,6 +2550,11 @@ igt_main
igt_subtest("breakpoint-many-sessions-tiles")
test_many_sessions_on_tiles(fd, true);
+ test_gt_render_or_compute("pagefault-read", fd, hwe)
+ test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
+ test_gt_render_or_compute("pagefault-write", fd, hwe)
+ test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
+
igt_fixture {
xe_eudebug_enable(fd, was_enabled);
--
2.46.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* ✓ CI.xeBAT: success for tests/intel/xe_eudebug_online: Introduce read/write pagefault tests
2024-11-15 14:11 [PATCH i-g-t 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Gwan-gyeong Mun
` (3 preceding siblings ...)
2024-11-15 14:11 ` [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests Gwan-gyeong Mun
@ 2024-11-15 14:42 ` Patchwork
2024-11-15 14:48 ` ✓ Fi.CI.BAT: " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2024-11-15 14:42 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 1409 bytes --]
== Series Details ==
Series: tests/intel/xe_eudebug_online: Introduce read/write pagefault tests
URL : https://patchwork.freedesktop.org/series/141401/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_8113_BAT -> XEIGTPW_12115_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in XEIGTPW_12115_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- bat-adlp-7: [PASS][1] -> [FAIL][2] ([Intel XE#1861])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
[Intel XE#1861]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1861
Build changes
-------------
* IGT: IGT_8113 -> IGTPW_12115
IGTPW_12115: 12115
IGT_8113: 55e8731f083c9dbb1b5969104b56e8be85225cc7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2235-36fec0eb87867bca47f8829c9e5dbf5b3e2b3aaf: 36fec0eb87867bca47f8829c9e5dbf5b3e2b3aaf
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/index.html
[-- Attachment #2: Type: text/html, Size: 1971 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ Fi.CI.BAT: success for tests/intel/xe_eudebug_online: Introduce read/write pagefault tests
2024-11-15 14:11 [PATCH i-g-t 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Gwan-gyeong Mun
` (4 preceding siblings ...)
2024-11-15 14:42 ` ✓ CI.xeBAT: success for tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Patchwork
@ 2024-11-15 14:48 ` Patchwork
2024-11-15 21:24 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-11-15 23:25 ` ✗ CI.xeFULL: " Patchwork
7 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2024-11-15 14:48 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 6678 bytes --]
== Series Details ==
Series: tests/intel/xe_eudebug_online: Introduce read/write pagefault tests
URL : https://patchwork.freedesktop.org/series/141401/
State : success
== Summary ==
CI Bug Log - changes from IGT_8113 -> IGTPW_12115
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/index.html
Participating hosts (46 -> 45)
------------------------------
Additional (1): bat-adls-6
Missing (2): bat-mtlp-9 fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_12115 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-adls-6: NOTRUN -> [SKIP][1] ([i915#9318])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-adls-6/igt@debugfs_test@basic-hwmon.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adls-6: NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_tiled_pread_basic:
- bat-adls-6: NOTRUN -> [SKIP][3] ([i915#3282])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-adls-6/igt@gem_tiled_pread_basic.html
* igt@i915_selftest@live:
- bat-twl-2: [PASS][4] -> [INCOMPLETE][5] ([i915#12816] / [i915#9413])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/bat-twl-2/igt@i915_selftest@live.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-twl-2/igt@i915_selftest@live.html
* igt@i915_selftest@live@gt_lrc:
- bat-twl-2: [PASS][6] -> [INCOMPLETE][7] ([i915#12445] / [i915#9413])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/bat-twl-2/igt@i915_selftest@live@gt_lrc.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-twl-2/igt@i915_selftest@live@gt_lrc.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adls-6: NOTRUN -> [SKIP][8] ([i915#4103]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-adls-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-adls-6: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#3840])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-adls-6/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adls-6: NOTRUN -> [SKIP][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-adls-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pm_backlight@basic-brightness:
- bat-adls-6: NOTRUN -> [SKIP][11] ([i915#5354])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-adls-6/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-primary-mmap-gtt:
- bat-adls-6: NOTRUN -> [SKIP][12] ([i915#1072] / [i915#9732]) +3 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-adls-6/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adls-6: NOTRUN -> [SKIP][13] ([i915#3555])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-adls-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-adls-6: NOTRUN -> [SKIP][14] ([i915#3291]) +2 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-adls-6/igt@prime_vgem@basic-fence-read.html
#### Possible fixes ####
* igt@i915_selftest@live:
- bat-arls-5: [ABORT][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/bat-arls-5/igt@i915_selftest@live.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-arls-5/igt@i915_selftest@live.html
- bat-arlh-2: [ABORT][17] -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/bat-arlh-2/igt@i915_selftest@live.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-arlh-2/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-arls-5: [ABORT][19] ([i915#12061]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/bat-arls-5/igt@i915_selftest@live@workarounds.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-arls-5/igt@i915_selftest@live@workarounds.html
- bat-arlh-2: [ABORT][21] ([i915#12061]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/bat-arlh-2/igt@i915_selftest@live@workarounds.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-arlh-2/igt@i915_selftest@live@workarounds.html
* igt@kms_addfb_basic@addfb25-modifier-no-flag:
- bat-arls-5: [DMESG-WARN][23] -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/bat-arls-5/igt@kms_addfb_basic@addfb25-modifier-no-flag.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/bat-arls-5/igt@kms_addfb_basic@addfb25-modifier-no-flag.html
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12445]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12445
[i915#12816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12816
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_8113 -> IGTPW_12115
CI-20190529: 20190529
CI_DRM_15707: c43ac257e8f2dfe3a5f56d3565472cb8051ca32d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_12115: 12115
IGT_8113: 55e8731f083c9dbb1b5969104b56e8be85225cc7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/index.html
[-- Attachment #2: Type: text/html, Size: 7888 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ Fi.CI.IGT: failure for tests/intel/xe_eudebug_online: Introduce read/write pagefault tests
2024-11-15 14:11 [PATCH i-g-t 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Gwan-gyeong Mun
` (5 preceding siblings ...)
2024-11-15 14:48 ` ✓ Fi.CI.BAT: " Patchwork
@ 2024-11-15 21:24 ` Patchwork
2024-11-15 23:25 ` ✗ CI.xeFULL: " Patchwork
7 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2024-11-15 21:24 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 100287 bytes --]
== Series Details ==
Series: tests/intel/xe_eudebug_online: Introduce read/write pagefault tests
URL : https://patchwork.freedesktop.org/series/141401/
State : failure
== Summary ==
CI Bug Log - changes from IGT_8113_full -> IGTPW_12115_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_12115_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_12115_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/index.html
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_12115_full:
### IGT changes ###
#### Possible regressions ####
* igt@fbdev@read:
- shard-tglu: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-9/igt@fbdev@read.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-6/igt@fbdev@read.html
* igt@gem_softpin@softpin:
- shard-tglu: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-6/igt@gem_softpin@softpin.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-8/igt@gem_softpin@softpin.html
* igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-5:
- shard-tglu: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-9/igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-5.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-4/igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-5.html
* igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-7:
- shard-tglu: [PASS][7] -> [DMESG-WARN][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-9/igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-7.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-4/igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-7.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][9] +8 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@kms_prime@basic-crc-hybrid.html
* igt@perf_pmu@interrupts:
- shard-dg2: [PASS][10] -> [SKIP][11] +13 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-1/igt@perf_pmu@interrupts.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@perf_pmu@interrupts.html
#### Warnings ####
* igt@device_reset@unbind-cold-reset-rebind:
- shard-dg2: [SKIP][12] ([i915#11078]) -> [SKIP][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-3/igt@device_reset@unbind-cold-reset-rebind.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@isolation:
- shard-dg2: [SKIP][14] ([i915#8414]) -> [SKIP][15] +2 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-5/igt@drm_fdinfo@isolation.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@drm_fdinfo@isolation.html
* igt@kms_pm_rpm@fences:
- shard-dg2: [SKIP][16] ([i915#4077]) -> [SKIP][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-8/igt@kms_pm_rpm@fences.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@kms_pm_rpm@fences.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2: [SKIP][18] ([i915#9519]) -> [SKIP][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp-stress.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@perf@mi-rpc:
- shard-dg2: [SKIP][20] ([i915#2434]) -> [SKIP][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-7/igt@perf@mi-rpc.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@perf@mi-rpc.html
Known issues
------------
Here are the changes found in IGTPW_12115_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_allocator@default-alignment:
- shard-dg2: NOTRUN -> [SKIP][22] +51 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@api_intel_allocator@default-alignment.html
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-mtlp: NOTRUN -> [SKIP][23] ([i915#8411])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-7/igt@api_intel_bb@object-reloc-purge-cache.html
- shard-dg2: NOTRUN -> [SKIP][24] ([i915#8411]) +1 other test skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@api_intel_bb@object-reloc-purge-cache.html
- shard-rkl: NOTRUN -> [SKIP][25] ([i915#8411]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@api_intel_bb@object-reloc-purge-cache.html
- shard-dg1: NOTRUN -> [SKIP][26] ([i915#8411])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@device_reset@cold-reset-bound:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#11078])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-3/igt@device_reset@cold-reset-bound.html
- shard-rkl: NOTRUN -> [SKIP][28] ([i915#11078])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@all-busy-idle-check-all:
- shard-mtlp: NOTRUN -> [SKIP][29] ([i915#8414]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-7/igt@drm_fdinfo@all-busy-idle-check-all.html
* igt@drm_fdinfo@busy-check-all@vecs1:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#8414]) +10 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@drm_fdinfo@busy-check-all@vecs1.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#8414]) +2 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@drm_fdinfo@virtual-busy-all.html
* igt@fbdev@read:
- shard-dg2: [PASS][32] -> [FAIL][33] ([i915#12673])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-3/igt@fbdev@read.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-6/igt@fbdev@read.html
- shard-dg1: [PASS][34] -> [FAIL][35] ([i915#12673])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-17/igt@fbdev@read.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-17/igt@fbdev@read.html
* igt@gem_busy@close-race:
- shard-mtlp: NOTRUN -> [FAIL][36] ([i915#12296] / [i915#12577])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-4/igt@gem_busy@close-race.html
- shard-dg2: NOTRUN -> [FAIL][37] ([i915#12296] / [i915#12577])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-2/igt@gem_busy@close-race.html
- shard-rkl: NOTRUN -> [FAIL][38] ([i915#12296] / [i915#12577])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@gem_busy@close-race.html
- shard-snb: NOTRUN -> [FAIL][39] ([i915#12296] / [i915#12577])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-snb4/igt@gem_busy@close-race.html
- shard-dg1: NOTRUN -> [FAIL][40] ([i915#12296] / [i915#12577])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-16/igt@gem_busy@close-race.html
- shard-tglu: NOTRUN -> [FAIL][41] ([i915#12296] / [i915#12577])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-4/igt@gem_busy@close-race.html
* igt@gem_ccs@block-copy-compressed:
- shard-rkl: NOTRUN -> [SKIP][42] ([i915#3555] / [i915#9323])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-6/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-tglu-1: NOTRUN -> [SKIP][43] ([i915#9323])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ccs@suspend-resume:
- shard-dg2: NOTRUN -> [INCOMPLETE][44] ([i915#7297])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@gem_ccs@suspend-resume.html
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#9323])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-4/igt@gem_ccs@suspend-resume.html
* igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0:
- shard-dg2: NOTRUN -> [INCOMPLETE][46] ([i915#12392] / [i915#7297])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#7697])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@gem_close_race@multigpu-basic-threads.html
- shard-rkl: NOTRUN -> [SKIP][48] ([i915#7697]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-tglu-1: NOTRUN -> [SKIP][49] ([i915#6335])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_engines@invalid-engines:
- shard-mtlp: [PASS][50] -> [FAIL][51] ([i915#12031])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-mtlp-1/igt@gem_ctx_engines@invalid-engines.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-4/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_ctx_persistence@engines-queued:
- shard-snb: NOTRUN -> [SKIP][52] ([i915#1099]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-snb6/igt@gem_ctx_persistence@engines-queued.html
* igt@gem_ctx_persistence@hostile:
- shard-tglu: [PASS][53] -> [FAIL][54] ([i915#11980] / [i915#12580])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-6/igt@gem_ctx_persistence@hostile.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-9/igt@gem_ctx_persistence@hostile.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-tglu-1: NOTRUN -> [SKIP][55] ([i915#280])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@hibernate:
- shard-dg1: [PASS][56] -> [ABORT][57] ([i915#7975] / [i915#8213])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-16/igt@gem_eio@hibernate.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-14/igt@gem_eio@hibernate.html
* igt@gem_eio@unwedge-stress:
- shard-dg1: [PASS][58] -> [FAIL][59] ([i915#12714] / [i915#5784])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-18/igt@gem_eio@unwedge-stress.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@bonded-dual:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#4771])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@noheartbeat:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#8555])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@gem_exec_balancer@noheartbeat.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#4525])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-1/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_big@single:
- shard-tglu: [PASS][63] -> [ABORT][64] ([i915#11713])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-3/igt@gem_exec_big@single.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-7/igt@gem_exec_big@single.html
* igt@gem_exec_capture@capture-invisible:
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#6334]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-1/igt@gem_exec_capture@capture-invisible.html
* igt@gem_exec_capture@capture-recoverable:
- shard-tglu: NOTRUN -> [SKIP][66] ([i915#6344])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-6/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: NOTRUN -> [FAIL][67] ([i915#2846])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@gem_exec_fair@basic-deadline.html
- shard-dg1: NOTRUN -> [SKIP][68] ([i915#3539] / [i915#4852]) +2 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-17/igt@gem_exec_fair@basic-deadline.html
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#4473] / [i915#4771])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-rrul:
- shard-dg2: NOTRUN -> [SKIP][70] ([i915#3539] / [i915#4852]) +2 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@gem_exec_fair@basic-none-rrul.html
- shard-tglu-1: NOTRUN -> [FAIL][71] ([i915#2842]) +1 other test fail
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@gem_exec_fair@basic-none-rrul.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: NOTRUN -> [FAIL][72] ([i915#2842]) +4 other tests fail
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-4/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#3711])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-4/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_flush@basic-uc-prw-default:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#3539])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@gem_exec_flush@basic-uc-prw-default.html
* igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#2575]) +74 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
* igt@gem_exec_reloc@basic-cpu-wc-active:
- shard-mtlp: NOTRUN -> [SKIP][76] ([i915#3281]) +5 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-4/igt@gem_exec_reloc@basic-cpu-wc-active.html
* igt@gem_exec_reloc@basic-wc-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#3281]) +9 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@gem_exec_reloc@basic-wc-read-noreloc.html
* igt@gem_exec_reloc@basic-write-cpu-active:
- shard-dg1: NOTRUN -> [SKIP][78] ([i915#3281]) +6 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@gem_exec_reloc@basic-write-cpu-active.html
* igt@gem_exec_reloc@basic-write-gtt:
- shard-dg2: NOTRUN -> [SKIP][79] ([i915#3281]) +7 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@gem_exec_reloc@basic-write-gtt.html
* igt@gem_exec_schedule@pi-common@vcs0:
- shard-rkl: NOTRUN -> [FAIL][80] ([i915#12296]) +4 other tests fail
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@gem_exec_schedule@pi-common@vcs0.html
* igt@gem_exec_schedule@pi-common@vecs0:
- shard-dg2: NOTRUN -> [FAIL][81] ([i915#12296]) +6 other tests fail
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-1/igt@gem_exec_schedule@pi-common@vecs0.html
* igt@gem_exec_schedule@preempt-queue:
- shard-dg1: NOTRUN -> [SKIP][82] ([i915#4812])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-16/igt@gem_exec_schedule@preempt-queue.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#7276])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@gem_exec_schedule@semaphore-power.html
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#4537] / [i915#4812])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_fenced_exec_thrash@no-spare-fences:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#4860])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@gem_fenced_exec_thrash@no-spare-fences.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: NOTRUN -> [SKIP][86] ([i915#2190])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@gem_huc_copy@huc-copy.html
- shard-tglu: NOTRUN -> [SKIP][87] ([i915#2190])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-4/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-tglu: NOTRUN -> [SKIP][88] ([i915#4613])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-6/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-tglu-1: NOTRUN -> [SKIP][89] ([i915#4613]) +1 other test skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@random-engines:
- shard-rkl: NOTRUN -> [SKIP][90] ([i915#4613]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@gem_lmem_swapping@random-engines.html
* igt@gem_media_fill@media-fill:
- shard-mtlp: NOTRUN -> [SKIP][91] ([i915#8289])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-6/igt@gem_media_fill@media-fill.html
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#8289])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-1/igt@gem_media_fill@media-fill.html
* igt@gem_media_vme:
- shard-tglu: NOTRUN -> [SKIP][93] ([i915#284])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-6/igt@gem_media_vme.html
* igt@gem_mmap_gtt@basic:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#4077]) +2 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-6/igt@gem_mmap_gtt@basic.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-dg1: NOTRUN -> [SKIP][95] ([i915#4077]) +5 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-17/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#4077]) +8 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@gem_mmap_gtt@fault-concurrent-x.html
* igt@gem_mmap_wc@invalid-flags:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#4083]) +2 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@gem_mmap_wc@invalid-flags.html
* igt@gem_mmap_wc@write-read:
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#4083]) +4 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-17/igt@gem_mmap_wc@write-read.html
- shard-mtlp: NOTRUN -> [SKIP][99] ([i915#4083]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-7/igt@gem_mmap_wc@write-read.html
* igt@gem_partial_pwrite_pread@write:
- shard-dg2: NOTRUN -> [SKIP][100] ([i915#3282]) +3 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-3/igt@gem_partial_pwrite_pread@write.html
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#3282]) +3 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
* igt@gem_pwrite@basic-exhaustion:
- shard-dg1: NOTRUN -> [SKIP][102] ([i915#3282])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-17/igt@gem_pwrite@basic-exhaustion.html
- shard-mtlp: NOTRUN -> [SKIP][103] ([i915#3282])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-8/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@display-protected-crc:
- shard-tglu-1: NOTRUN -> [SKIP][104] ([i915#4270]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg1: NOTRUN -> [SKIP][105] ([i915#4270]) +1 other test skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-13/igt@gem_pxp@protected-raw-src-copy-not-readible.html
- shard-mtlp: NOTRUN -> [SKIP][106] ([i915#4270]) +1 other test skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-6/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-rkl: NOTRUN -> [SKIP][107] ([i915#4270]) +3 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-4/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-tglu: NOTRUN -> [SKIP][108] ([i915#4270]) +4 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-6/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][109] ([i915#8428]) +2 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-3/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][110] ([i915#5190] / [i915#8428]) +3 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-dg1: NOTRUN -> [SKIP][111] ([i915#4079])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-17/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
- shard-mtlp: NOTRUN -> [SKIP][112] ([i915#4079])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-7/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#4079])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg1: NOTRUN -> [SKIP][114] ([i915#4885])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-14/igt@gem_softpin@evict-snoop-interruptible.html
- shard-mtlp: NOTRUN -> [SKIP][115] ([i915#4885])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-3/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_unfence_active_buffers:
- shard-dg2: NOTRUN -> [SKIP][116] ([i915#4879])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#3297])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-tglu: NOTRUN -> [SKIP][118] ([i915#3297])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-2/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@sd-probe:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#3297] / [i915#4958])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@gem_userptr_blits@sd-probe.html
- shard-dg1: NOTRUN -> [SKIP][120] ([i915#3297] / [i915#4958])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@gem_userptr_blits@sd-probe.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#3297])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-1/igt@gem_userptr_blits@unsync-unmap.html
- shard-rkl: NOTRUN -> [SKIP][122] ([i915#3297])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@gem_userptr_blits@unsync-unmap.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglu-1: NOTRUN -> [SKIP][123] ([i915#3297]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#2856]) +1 other test skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-6/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@batch-without-end:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#2856])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-1/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-oversize:
- shard-dg1: NOTRUN -> [SKIP][126] ([i915#2527]) +2 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-12/igt@gen9_exec_parse@bb-oversize.html
* igt@gen9_exec_parse@bb-secure:
- shard-tglu: NOTRUN -> [SKIP][127] ([i915#2527] / [i915#2856]) +3 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-10/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglu-1: NOTRUN -> [SKIP][128] ([i915#2527] / [i915#2856]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@valid-registers:
- shard-rkl: NOTRUN -> [SKIP][129] ([i915#2527]) +5 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@load:
- shard-tglu-1: NOTRUN -> [SKIP][130] ([i915#6227])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [PASS][131] -> [ABORT][132] ([i915#9820])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-14/igt@i915_module_load@reload-with-fault-injection.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_module_load@resize-bar:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#6412])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@i915_module_load@resize-bar.html
- shard-tglu: NOTRUN -> [SKIP][134] ([i915#6412])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-3/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-tglu-1: NOTRUN -> [SKIP][135] ([i915#8399])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_freq_api@freq-reset:
- shard-tglu: NOTRUN -> [SKIP][136] ([i915#8399])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-2/igt@i915_pm_freq_api@freq-reset.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-dg1: [PASS][137] -> [FAIL][138] ([i915#12548] / [i915#3591])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@i915_pm_sseu@full-enable:
- shard-tglu: NOTRUN -> [SKIP][139] ([i915#4387])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-2/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@hwconfig_table:
- shard-tglu: NOTRUN -> [SKIP][140] ([i915#6245])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-3/igt@i915_query@hwconfig_table.html
* igt@i915_selftest@mock:
- shard-mtlp: NOTRUN -> [DMESG-WARN][141] ([i915#9311]) +1 other test dmesg-warn
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-6/igt@i915_selftest@mock.html
* igt@i915_selftest@mock@memory_region:
- shard-dg1: NOTRUN -> [DMESG-WARN][142] ([i915#9311]) +1 other test dmesg-warn
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@i915_selftest@mock@memory_region.html
* igt@i915_suspend@basic-s2idle-without-i915:
- shard-dg1: [PASS][143] -> [DMESG-WARN][144] ([i915#4391] / [i915#4423])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-17/igt@i915_suspend@basic-s2idle-without-i915.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@forcewake:
- shard-dg1: NOTRUN -> [DMESG-WARN][145] ([i915#4423])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-16/igt@i915_suspend@forcewake.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-mtlp: NOTRUN -> [SKIP][146] ([i915#4212])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-7/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#4212])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
- shard-dg1: NOTRUN -> [SKIP][148] ([i915#4212])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@addfb25-yf-tiled-legacy:
- shard-dg2: [PASS][149] -> [SKIP][150] ([i915#2575] / [i915#5190])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-7/igt@kms_addfb_basic@addfb25-yf-tiled-legacy.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@kms_addfb_basic@addfb25-yf-tiled-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][151] ([i915#8709]) +3 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#8709]) +11 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#9531])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
- shard-tglu: NOTRUN -> [SKIP][154] ([i915#9531])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-10/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-mtlp: NOTRUN -> [SKIP][155] ([i915#1769] / [i915#3555])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-tglu-1: NOTRUN -> [SKIP][156] ([i915#1769] / [i915#3555])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg1: NOTRUN -> [SKIP][157] ([i915#1769] / [i915#3555])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-18/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][158] +11 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-4/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][159] ([i915#4538] / [i915#5286]) +5 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-18/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
- shard-tglu-1: NOTRUN -> [SKIP][160] ([i915#5286]) +5 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglu: NOTRUN -> [SKIP][161] ([i915#5286]) +4 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-9/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-rkl: NOTRUN -> [SKIP][162] ([i915#5286]) +4 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][163] ([i915#3638]) +2 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#3638]) +3 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#4538] / [i915#5190]) +8 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][166] ([i915#4538])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-13/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][167] ([i915#6095]) +136 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-17/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][168] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#6095]) +29 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-5/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-b-edp-1.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][170] ([i915#6095]) +44 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-8/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs:
- shard-snb: NOTRUN -> [SKIP][171] +92 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-snb7/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][172] ([i915#10307] / [i915#6095]) +144 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
- shard-rkl: NOTRUN -> [SKIP][173] ([i915#12313])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
- shard-dg1: NOTRUN -> [SKIP][174] ([i915#12313])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
- shard-tglu: NOTRUN -> [SKIP][175] ([i915#12313])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
- shard-mtlp: NOTRUN -> [SKIP][176] ([i915#12313])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][177] ([i915#6095]) +108 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#6095]) +18 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][179] ([i915#12313]) +1 other test skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][180] ([i915#6095]) +44 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_cdclk@mode-transition:
- shard-tglu-1: NOTRUN -> [SKIP][181] ([i915#3742])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-tglu: NOTRUN -> [SKIP][182] ([i915#3742])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-7/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@mode-transition@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#11616] / [i915#7213]) +3 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-a-dp-4.html
* igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#4087]) +3 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html
* igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#7828]) +10 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-6/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-dg1: NOTRUN -> [SKIP][186] ([i915#7828]) +5 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#7828]) +2 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-mtlp: NOTRUN -> [SKIP][188] ([i915#7828]) +3 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-6/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-tglu-1: NOTRUN -> [SKIP][189] ([i915#7828]) +6 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
- shard-tglu: NOTRUN -> [SKIP][190] ([i915#7828]) +5 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-2/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html
* igt@kms_content_protection@atomic:
- shard-dg1: NOTRUN -> [SKIP][191] ([i915#7116] / [i915#9424])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-18/igt@kms_content_protection@atomic.html
- shard-tglu: NOTRUN -> [SKIP][192] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-8/igt@kms_content_protection@atomic.html
- shard-mtlp: NOTRUN -> [SKIP][193] ([i915#6944] / [i915#9424])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@content-type-change:
- shard-tglu: NOTRUN -> [SKIP][194] ([i915#6944] / [i915#9424])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-5/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-rkl: NOTRUN -> [SKIP][195] ([i915#3116])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-tglu-1: NOTRUN -> [SKIP][196] ([i915#3116] / [i915#3299]) +1 other test skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: NOTRUN -> [SKIP][197] ([i915#9424])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-17/igt@kms_content_protection@mei-interface.html
- shard-mtlp: NOTRUN -> [SKIP][198] ([i915#8063] / [i915#9433])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-8/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@srm:
- shard-dg2: NOTRUN -> [SKIP][199] ([i915#7118])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-2/igt@kms_content_protection@srm.html
- shard-tglu: NOTRUN -> [SKIP][200] ([i915#6944] / [i915#7116] / [i915#7118])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-10/igt@kms_content_protection@srm.html
* igt@kms_content_protection@type1:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#7118] / [i915#9424]) +1 other test skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@kms_content_protection@type1.html
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#7118] / [i915#9424]) +1 other test skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-1/igt@kms_content_protection@type1.html
* igt@kms_content_protection@uevent:
- shard-tglu-1: NOTRUN -> [SKIP][203] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_content_protection@uevent.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][204] ([i915#1339] / [i915#7173])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-32x32:
- shard-tglu-1: NOTRUN -> [SKIP][205] ([i915#3555]) +5 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_cursor_crc@cursor-offscreen-32x32.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-dg1: NOTRUN -> [SKIP][206] ([i915#11453] / [i915#3359]) +1 other test skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-16/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-rkl: NOTRUN -> [SKIP][207] ([i915#11453] / [i915#3359])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-tglu: NOTRUN -> [SKIP][208] ([i915#3555]) +1 other test skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-6/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-sliding-128x42:
- shard-mtlp: NOTRUN -> [SKIP][209] ([i915#8814])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-1/igt@kms_cursor_crc@cursor-sliding-128x42.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-mtlp: NOTRUN -> [SKIP][210] ([i915#11453] / [i915#3359])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-5/igt@kms_cursor_crc@cursor-sliding-512x170.html
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#11453] / [i915#3359])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@kms_cursor_crc@cursor-sliding-512x170.html
- shard-tglu-1: NOTRUN -> [SKIP][212] ([i915#11453] / [i915#3359]) +1 other test skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-tglu: NOTRUN -> [SKIP][213] ([i915#11453] / [i915#3359]) +1 other test skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-2/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_crc@cursor-suspend:
- shard-dg2: [PASS][214] -> [INCOMPLETE][215] ([i915#12358] / [i915#7882])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-3/igt@kms_cursor_crc@cursor-suspend.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-6/igt@kms_cursor_crc@cursor-suspend.html
- shard-dg1: [PASS][216] -> [INCOMPLETE][217] ([i915#12358])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-16/igt@kms_cursor_crc@cursor-suspend.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-12/igt@kms_cursor_crc@cursor-suspend.html
* igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-3:
- shard-dg2: [PASS][218] -> [INCOMPLETE][219] ([i915#12358])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-3/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-3.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-6/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-3.html
- shard-dg1: NOTRUN -> [INCOMPLETE][220] ([i915#12358])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-12/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-3.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][221] ([i915#9809]) +3 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-5/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-tglu-1: NOTRUN -> [SKIP][222] ([i915#4103])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-rkl: NOTRUN -> [SKIP][223] +11 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-4/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
- shard-snb: [PASS][224] -> [SKIP][225] +2 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-snb7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-snb2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-rkl: NOTRUN -> [SKIP][226] ([i915#4103])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_display_modes@extended-mode-basic:
- shard-dg2: NOTRUN -> [SKIP][227] ([i915#3555]) +3 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@kms_display_modes@extended-mode-basic.html
- shard-rkl: NOTRUN -> [SKIP][228] ([i915#3555]) +1 other test skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-tglu-1: NOTRUN -> [SKIP][229] ([i915#8588])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][230] ([i915#3804])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][231] ([i915#8812])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@kms_draw_crc@draw-method-mmap-gtt.html
- shard-mtlp: NOTRUN -> [SKIP][232] ([i915#3555] / [i915#8812])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-7/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][233] ([i915#3840])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-2/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
- shard-tglu: NOTRUN -> [SKIP][234] ([i915#3840])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-10/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc:
- shard-tglu: NOTRUN -> [SKIP][235] ([i915#3555] / [i915#3840])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-7/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-formats:
- shard-rkl: NOTRUN -> [SKIP][236] ([i915#3555] / [i915#3840]) +1 other test skip
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-tglu-1: NOTRUN -> [SKIP][237] ([i915#3840] / [i915#9053])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][238] ([i915#3955])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html
- shard-tglu-1: NOTRUN -> [SKIP][239] ([i915#3469])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@chamelium:
- shard-tglu: NOTRUN -> [SKIP][240] ([i915#2065] / [i915#4854])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-3/igt@kms_feature_discovery@chamelium.html
- shard-mtlp: NOTRUN -> [SKIP][241] ([i915#4854])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-6/igt@kms_feature_discovery@chamelium.html
- shard-dg2: NOTRUN -> [SKIP][242] ([i915#4854])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-1/igt@kms_feature_discovery@chamelium.html
- shard-rkl: NOTRUN -> [SKIP][243] ([i915#4854])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@kms_feature_discovery@chamelium.html
- shard-dg1: NOTRUN -> [SKIP][244] ([i915#4854])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@kms_feature_discovery@chamelium.html
* igt@kms_fence_pin_leak:
- shard-dg1: NOTRUN -> [SKIP][245] ([i915#4881])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-16/igt@kms_fence_pin_leak.html
- shard-mtlp: NOTRUN -> [SKIP][246] ([i915#4881])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-4/igt@kms_fence_pin_leak.html
- shard-dg2: NOTRUN -> [SKIP][247] ([i915#4881])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-tglu-1: NOTRUN -> [SKIP][248] ([i915#3637]) +6 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-rkl: NOTRUN -> [SKIP][249] ([i915#9934]) +8 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@kms_flip@2x-flip-vs-fences-interruptible.html
- shard-tglu: NOTRUN -> [SKIP][250] ([i915#3637]) +4 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-8/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-mtlp: NOTRUN -> [SKIP][251] ([i915#3637]) +4 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-8/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_flip@2x-plain-flip:
- shard-dg1: NOTRUN -> [SKIP][252] ([i915#9934]) +7 other tests skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-dg1: [PASS][253] -> [INCOMPLETE][254] ([i915#4839] / [i915#6113])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-16/igt@kms_flip@flip-vs-suspend-interruptible.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-18/igt@kms_flip@flip-vs-suspend-interruptible.html
- shard-mtlp: [PASS][255] -> [INCOMPLETE][256] ([i915#6113])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-mtlp-7/igt@kms_flip@flip-vs-suspend-interruptible.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-5/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a4:
- shard-dg1: [PASS][257] -> [INCOMPLETE][258] ([i915#6113])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-16/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a4.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-18/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a4.html
* igt@kms_flip@flip-vs-suspend-interruptible@d-edp1:
- shard-mtlp: [PASS][259] -> [INCOMPLETE][260] ([i915#10056] / [i915#6113])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-mtlp-7/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-5/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-snb: [PASS][261] -> [FAIL][262] ([i915#2122]) +6 other tests fail
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-snb1/igt@kms_flip@plain-flip-ts-check-interruptible.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-snb6/igt@kms_flip@plain-flip-ts-check-interruptible.html
- shard-tglu: [PASS][263] -> [FAIL][264] ([i915#2122]) +4 other tests fail
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-10/igt@kms_flip@plain-flip-ts-check-interruptible.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-6/igt@kms_flip@plain-flip-ts-check-interruptible.html
- shard-mtlp: [PASS][265] -> [FAIL][266] ([i915#11989] / [i915#2122])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-mtlp-5/igt@kms_flip@plain-flip-ts-check-interruptible.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-2/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-mtlp: [PASS][267] -> [FAIL][268] ([i915#2122]) +1 other test fail
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-mtlp-5/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-2/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][269] ([i915#2587] / [i915#2672]) +3 other tests skip
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-9/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][270] ([i915#2587] / [i915#2672]) +2 other tests skip
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
- shard-tglu: NOTRUN -> [SKIP][271] ([i915#2672] / [i915#3555]) +1 other test skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-dg1: NOTRUN -> [SKIP][272] ([i915#2587] / [i915#2672] / [i915#3555]) +1 other test skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
- shard-tglu: NOTRUN -> [SKIP][273] ([i915#2587] / [i915#2672] / [i915#3555]) +1 other test skip
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][274] ([i915#2672] / [i915#8813]) +2 other tests skip
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][275] ([i915#2672]) +4 other tests skip
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
- shard-rkl: NOTRUN -> [SKIP][276] ([i915#2672]) +3 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][277] ([i915#5190]) +5 other tests skip
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling:
- shard-rkl: NOTRUN -> [SKIP][278] ([i915#2672] / [i915#3555]) +3 other tests skip
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][279] ([i915#2672] / [i915#3555]) +2 other tests skip
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
- shard-dg2: NOTRUN -> [SKIP][280] ([i915#2672] / [i915#3555])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-dg1: NOTRUN -> [SKIP][281] ([i915#2672] / [i915#3555]) +2 other tests skip
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][282] ([i915#2587] / [i915#2672]) +4 other tests skip
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][283] ([i915#2672] / [i915#3555] / [i915#8813]) +4 other tests skip
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
- shard-dg2: NOTRUN -> [SKIP][284] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][285] ([i915#1825]) +14 other tests skip
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][286] +23 other tests skip
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt:
- shard-dg1: NOTRUN -> [SKIP][287] ([i915#4423])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
- shard-dg2: [PASS][288] -> [SKIP][289] +21 other tests skip
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-dg1: [PASS][290] -> [DMESG-WARN][291] ([i915#4423]) +1 other test dmesg-warn
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-suspend.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-suspend.html
- shard-tglu: [PASS][292] -> [ABORT][293] ([i915#10159])
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-5/igt@kms_frontbuffer_tracking@fbc-suspend.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-9/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][294] ([i915#5439])
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][295] ([i915#8708]) +14 other tests skip
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
- shard-tglu-1: NOTRUN -> [SKIP][296] +54 other tests skip
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][297] ([i915#1825]) +33 other tests skip
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][298] ([i915#8708]) +11 other tests skip
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][299] ([i915#3023]) +23 other tests skip
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][300] ([i915#8708])
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-tglu: NOTRUN -> [SKIP][301] ([i915#9766])
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-10/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-dg2: NOTRUN -> [SKIP][302] ([i915#9766])
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][303] ([i915#10433] / [i915#3458])
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][304] ([i915#5354]) +34 other tests skip
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-tglu: NOTRUN -> [SKIP][305] +50 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][306] ([i915#3458]) +9 other tests skip
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][307] ([i915#3458]) +10 other tests skip
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
* igt@kms_hdr@invalid-hdr:
- shard-rkl: NOTRUN -> [SKIP][308] ([i915#3555] / [i915#8228]) +1 other test skip
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-4/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-swap:
- shard-dg1: NOTRUN -> [SKIP][309] ([i915#3555] / [i915#8228]) +2 other tests skip
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@kms_hdr@static-swap.html
- shard-tglu: NOTRUN -> [SKIP][310] ([i915#3555] / [i915#8228])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-9/igt@kms_hdr@static-swap.html
- shard-mtlp: NOTRUN -> [SKIP][311] ([i915#3555] / [i915#8228])
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-1/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle:
- shard-dg2: NOTRUN -> [SKIP][312] ([i915#3555] / [i915#8228])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@kms_hdr@static-toggle.html
* igt@kms_joiner@basic-big-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][313] ([i915#10656])
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-dg2: [PASS][314] -> [SKIP][315] ([i915#12388])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-10/igt@kms_joiner@basic-force-big-joiner.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-2/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-dg2: NOTRUN -> [SKIP][316] ([i915#10656])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-6/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-tglu: NOTRUN -> [SKIP][317] ([i915#12388])
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-tglu: NOTRUN -> [SKIP][318] ([i915#12339]) +1 other test skip
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-5/igt@kms_joiner@invalid-modeset-ultra-joiner.html
- shard-mtlp: NOTRUN -> [SKIP][319] ([i915#12339])
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-1/igt@kms_joiner@invalid-modeset-ultra-joiner.html
- shard-dg2: NOTRUN -> [SKIP][320] ([i915#12339]) +1 other test skip
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@kms_joiner@invalid-modeset-ultra-joiner.html
- shard-rkl: NOTRUN -> [SKIP][321] ([i915#12339])
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-1/igt@kms_joiner@invalid-modeset-ultra-joiner.html
- shard-dg1: NOTRUN -> [SKIP][322] ([i915#12339])
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-13/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-dg2: NOTRUN -> [SKIP][323] ([i915#6301])
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-2/igt@kms_panel_fitting@atomic-fastset.html
- shard-dg1: NOTRUN -> [SKIP][324] ([i915#6301])
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-16/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_panel_fitting@legacy:
- shard-tglu-1: NOTRUN -> [SKIP][325] ([i915#6301])
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_panel_fitting@legacy.html
* igt@kms_plane@pixel-format-source-clamping:
- shard-tglu: [PASS][326] -> [ABORT][327] ([i915#10354])
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-9/igt@kms_plane@pixel-format-source-clamping.html
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-4/igt@kms_plane@pixel-format-source-clamping.html
* igt@kms_plane_lowres@tiling-y:
- shard-dg2: NOTRUN -> [SKIP][328] ([i915#8821])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_lowres@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][329] ([i915#3555] / [i915#8821])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][330] ([i915#12247]) +2 other tests skip
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-1/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html
* igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d:
- shard-tglu-1: NOTRUN -> [SKIP][331] ([i915#12247]) +8 other tests skip
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][332] ([i915#2575] / [i915#9423]) +1 other test skip
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
- shard-tglu: NOTRUN -> [SKIP][333] ([i915#12247] / [i915#6953])
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-5/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b:
- shard-tglu: NOTRUN -> [SKIP][334] ([i915#12247]) +3 other tests skip
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-5/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][335] ([i915#12247] / [i915#6953] / [i915#9423])
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c:
- shard-dg2: NOTRUN -> [SKIP][336] ([i915#12247]) +7 other tests skip
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
- shard-dg2: [PASS][337] -> [SKIP][338] ([i915#2575] / [i915#9423])
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-5/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html
* igt@kms_pm_backlight@bad-brightness:
- shard-tglu: NOTRUN -> [SKIP][339] ([i915#9812])
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-4/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-dg1: NOTRUN -> [SKIP][340] ([i915#12343])
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-18/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_dc@dc5-psr:
- shard-dg1: NOTRUN -> [SKIP][341] ([i915#9685])
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-17/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg1: NOTRUN -> [SKIP][342] ([i915#3361])
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-15/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-mtlp: NOTRUN -> [SKIP][343] ([i915#10139])
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-1/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: NOTRUN -> [SKIP][344] ([i915#3361])
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@kms_pm_dc@dc9-dpms.html
- shard-tglu-1: NOTRUN -> [SKIP][345] ([i915#4281])
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: [PASS][346] -> [SKIP][347] ([i915#9340])
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-4/igt@kms_pm_lpsp@kms-lpsp.html
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-6/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-tglu: NOTRUN -> [SKIP][348] ([i915#8430])
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-2/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg1: NOTRUN -> [SKIP][349] ([i915#9519])
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-16/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: NOTRUN -> [SKIP][350] ([i915#9519]) +1 other test skip
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
- shard-tglu: NOTRUN -> [SKIP][351] ([i915#9519])
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-10/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
- shard-mtlp: NOTRUN -> [SKIP][352] ([i915#9519])
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-7/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@d3hot:
- shard-dg2: NOTRUN -> [SKIP][353] ([i915#6524] / [i915#6805])
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-tglu-1: NOTRUN -> [SKIP][354] ([i915#11520]) +4 other tests skip
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][355] ([i915#11520]) +8 other tests skip
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][356] ([i915#11520]) +1 other test skip
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-16/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-tglu: NOTRUN -> [SKIP][357] ([i915#11520]) +3 other tests skip
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-5/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][358] ([i915#11520]) +2 other tests skip
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@fbc-pr-cursor-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][359] ([i915#1072] / [i915#9732]) +25 other tests skip
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@kms_psr@fbc-pr-cursor-mmap-cpu.html
* igt@kms_psr@fbc-psr2-sprite-plane-onoff:
- shard-mtlp: NOTRUN -> [SKIP][360] ([i915#9688]) +6 other tests skip
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-6/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html
* igt@kms_psr@pr-cursor-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][361] ([i915#9732]) +14 other tests skip
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_psr@pr-cursor-mmap-gtt.html
* igt@kms_psr@pr-dpms:
- shard-tglu: NOTRUN -> [SKIP][362] ([i915#9732]) +16 other tests skip
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-7/igt@kms_psr@pr-dpms.html
* igt@kms_psr@psr-sprite-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][363] ([i915#1072] / [i915#9732]) +13 other tests skip
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-17/igt@kms_psr@psr-sprite-mmap-cpu.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][364] ([i915#1072] / [i915#9732]) +13 other tests skip
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-dg2: NOTRUN -> [SKIP][365] ([i915#12755])
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-dg2: NOTRUN -> [SKIP][366] ([i915#2575] / [i915#5190]) +3 other tests skip
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
- shard-rkl: NOTRUN -> [SKIP][367] ([i915#5289])
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
- shard-dg1: NOTRUN -> [SKIP][368] ([i915#5289]) +1 other test skip
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
- shard-mtlp: NOTRUN -> [SKIP][369] ([i915#5289])
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-tglu: NOTRUN -> [SKIP][370] ([i915#5289]) +1 other test skip
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_scaling_modes@scaling-mode-center:
- shard-dg1: NOTRUN -> [SKIP][371] ([i915#3555]) +2 other tests skip
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-16/igt@kms_scaling_modes@scaling-mode-center.html
* igt@kms_selftest@drm_framebuffer:
- shard-snb: NOTRUN -> [ABORT][372] ([i915#12231]) +1 other test abort
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-snb6/igt@kms_selftest@drm_framebuffer.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-mtlp: NOTRUN -> [SKIP][373] ([i915#3555] / [i915#8809] / [i915#8823])
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-5/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_vrr@negative-basic:
- shard-mtlp: [PASS][374] -> [FAIL][375] ([i915#10393]) +1 other test fail
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-mtlp-3/igt@kms_vrr@negative-basic.html
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-8/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-rkl: NOTRUN -> [SKIP][376] ([i915#9906])
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@kms_vrr@seamless-rr-switch-drrs.html
- shard-dg2: NOTRUN -> [SKIP][377] ([i915#9906])
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-tglu: NOTRUN -> [SKIP][378] ([i915#9906])
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-4/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-check-output:
- shard-dg1: NOTRUN -> [SKIP][379] ([i915#2437])
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-13/igt@kms_writeback@writeback-check-output.html
- shard-mtlp: NOTRUN -> [SKIP][380] ([i915#2437])
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-6/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][381] ([i915#2437] / [i915#9412])
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-6/igt@kms_writeback@writeback-check-output-xrgb2101010.html
- shard-rkl: NOTRUN -> [SKIP][382] ([i915#2437] / [i915#9412]) +1 other test skip
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-1/igt@kms_writeback@writeback-check-output-xrgb2101010.html
- shard-dg1: NOTRUN -> [SKIP][383] ([i915#2437] / [i915#9412])
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-12/igt@kms_writeback@writeback-check-output-xrgb2101010.html
- shard-tglu: NOTRUN -> [SKIP][384] ([i915#2437] / [i915#9412])
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-8/igt@kms_writeback@writeback-check-output-xrgb2101010.html
- shard-mtlp: NOTRUN -> [SKIP][385] ([i915#2437] / [i915#9412])
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-1/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-tglu-1: NOTRUN -> [SKIP][386] ([i915#2437])
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@global-sseu-config:
- shard-dg2: NOTRUN -> [SKIP][387] ([i915#7387])
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@perf@global-sseu-config.html
* igt@perf@mi-rpc:
- shard-rkl: NOTRUN -> [SKIP][388] ([i915#2434])
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-5/igt@perf@mi-rpc.html
* igt@perf@non-zero-reason:
- shard-dg2: NOTRUN -> [FAIL][389] ([i915#9100]) +1 other test fail
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-6/igt@perf@non-zero-reason.html
* igt@perf_pmu@busy-accuracy-98:
- shard-tglu: [PASS][390] -> [FAIL][391] ([i915#12513] / [i915#4349])
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-6/igt@perf_pmu@busy-accuracy-98.html
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-8/igt@perf_pmu@busy-accuracy-98.html
* igt@perf_pmu@busy-accuracy-98@vecs0:
- shard-tglu: [PASS][392] -> [FAIL][393] ([i915#4349])
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-6/igt@perf_pmu@busy-accuracy-98@vecs0.html
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-8/igt@perf_pmu@busy-accuracy-98@vecs0.html
* igt@perf_pmu@most-busy-idle-check-all@rcs0:
- shard-mtlp: [PASS][394] -> [FAIL][395] ([i915#11943] / [i915#12515]) +1 other test fail
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-mtlp-2/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-5/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg2: NOTRUN -> [SKIP][396] ([i915#8516])
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@perf_pmu@rc6-all-gts.html
- shard-rkl: NOTRUN -> [SKIP][397] ([i915#8516])
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-6/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@semaphore-busy@vcs1:
- shard-dg1: [PASS][398] -> [FAIL][399] ([i915#4349]) +3 other tests fail
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-17/igt@perf_pmu@semaphore-busy@vcs1.html
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-18/igt@perf_pmu@semaphore-busy@vcs1.html
* igt@perf_pmu@semaphore-busy@vecs0:
- shard-mtlp: [PASS][400] -> [FAIL][401] ([i915#4349]) +7 other tests fail
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-mtlp-3/igt@perf_pmu@semaphore-busy@vecs0.html
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-2/igt@perf_pmu@semaphore-busy@vecs0.html
- shard-dg2: [PASS][402] -> [FAIL][403] ([i915#4349]) +5 other tests fail
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-6/igt@perf_pmu@semaphore-busy@vecs0.html
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@perf_pmu@semaphore-busy@vecs0.html
* igt@prime_vgem@basic-fence-flip:
- shard-dg2: NOTRUN -> [SKIP][404] ([i915#3708])
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-8/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- shard-dg2: NOTRUN -> [SKIP][405] ([i915#3708] / [i915#4077])
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-4/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-read:
- shard-mtlp: NOTRUN -> [SKIP][406] ([i915#3708])
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-7/igt@prime_vgem@basic-read.html
- shard-dg2: NOTRUN -> [SKIP][407] ([i915#3291] / [i915#3708])
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-10/igt@prime_vgem@basic-read.html
- shard-rkl: NOTRUN -> [SKIP][408] ([i915#3291] / [i915#3708])
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- shard-dg1: NOTRUN -> [SKIP][409] ([i915#3708]) +1 other test skip
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-18/igt@prime_vgem@basic-write.html
- shard-mtlp: NOTRUN -> [SKIP][410] ([i915#10216] / [i915#3708])
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-8/igt@prime_vgem@basic-write.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-rkl: NOTRUN -> [SKIP][411] ([i915#9917])
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-4/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-tglu: NOTRUN -> [SKIP][412] ([i915#9917])
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-4/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-tglu-1: NOTRUN -> [SKIP][413] ([i915#9917])
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-1/igt@sriov_basic@enable-vfs-bind-unbind-each.html
* igt@syncobj_timeline@wait-all-for-submit-delayed-submit:
- shard-dg2: [PASS][414] -> [SKIP][415] ([i915#2575]) +157 other tests skip
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-8/igt@syncobj_timeline@wait-all-for-submit-delayed-submit.html
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@syncobj_timeline@wait-all-for-submit-delayed-submit.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-rkl: NOTRUN -> [FAIL][416] ([i915#12564] / [i915#9781])
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-4/igt@syncobj_wait@invalid-wait-zero-handles.html
#### Possible fixes ####
* igt@gem_ctx_engines@invalid-engines:
- shard-rkl: [FAIL][417] ([i915#12031]) -> [PASS][418]
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-rkl-7/igt@gem_ctx_engines@invalid-engines.html
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_ctx_persistence@hostile:
- shard-dg1: [FAIL][419] ([i915#11980] / [i915#12580]) -> [PASS][420]
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-16/igt@gem_ctx_persistence@hostile.html
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-19/igt@gem_ctx_persistence@hostile.html
* igt@gem_exec_fair@basic-none-share:
- shard-rkl: [FAIL][421] ([i915#2842]) -> [PASS][422] +4 other tests pass
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-rkl-5/igt@gem_exec_fair@basic-none-share.html
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-3/igt@gem_exec_fair@basic-none-share.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [FAIL][423] ([i915#2876]) -> [PASS][424]
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-rkl-1/igt@gem_exec_fair@basic-pace@rcs0.html
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
- shard-dg1: [INCOMPLETE][425] -> [PASS][426] +1 other test pass
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-14/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-12/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [ABORT][427] ([i915#12817] / [i915#9820]) -> [PASS][428]
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-8/igt@i915_module_load@reload-with-fault-injection.html
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-9/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: [ABORT][429] ([i915#9820]) -> [PASS][430]
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-10/igt@i915_module_load@reload-with-fault-injection.html
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-11/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [FAIL][431] ([i915#12739] / [i915#3591]) -> [PASS][432]
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][433] ([i915#7790]) -> [PASS][434]
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-snb2/igt@i915_pm_rps@reset.html
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-snb7/igt@i915_pm_rps@reset.html
* igt@i915_selftest@live@workarounds:
- shard-mtlp: [ABORT][435] ([i915#12061]) -> [PASS][436] +1 other test pass
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-mtlp-7/igt@i915_selftest@live@workarounds.html
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-mtlp-1/igt@i915_selftest@live@workarounds.html
* igt@i915_selftest@perf:
- shard-dg2: [FAIL][437] -> [PASS][438] +5 other tests pass
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-11/igt@i915_selftest@perf.html
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-6/igt@i915_selftest@perf.html
- shard-snb: [ABORT][439] ([i915#12450]) -> [PASS][440]
[439]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-snb2/igt@i915_selftest@perf.html
[440]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-snb2/igt@i915_selftest@perf.html
* igt@i915_selftest@perf@engine_cs:
- shard-snb: [ABORT][441] ([i915#11703]) -> [PASS][442]
[441]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-snb2/igt@i915_selftest@perf@engine_cs.html
[442]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-snb2/igt@i915_selftest@perf@engine_cs.html
* igt@kms_addfb_basic@addfb25-y-tiled-legacy:
- shard-dg2: [SKIP][443] ([i915#2575] / [i915#5190]) -> [PASS][444]
[443]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-legacy.html
[444]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg2-7/igt@kms_addfb_basic@addfb25-y-tiled-legacy.html
* igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
- shard-tglu: [FAIL][445] ([i915#11808]) -> [PASS][446] +1 other test pass
[445]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-5/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
[446]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-10/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition:
- shard-dg1: [FAIL][447] ([i915#5956]) -> [PASS][448]
[447]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-17/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
[448]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-13/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
- shard-tglu: [INCOMPLETE][449] -> [PASS][450] +1 other test pass
[449]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-tglu-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
[450]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-tglu-9/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_draw_crc@draw-method-pwrite:
- shard-dg1: [DMESG-WARN][451] ([i915#4423]) -> [PASS][452]
[451]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8113/shard-dg1-14/igt@kms_draw_crc@draw-method-pwrite.html
[452]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/shard-dg1-16/igt@kms_draw_crc@draw-method-pwrite.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-inte
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12115/index.html
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^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ CI.xeFULL: failure for tests/intel/xe_eudebug_online: Introduce read/write pagefault tests
2024-11-15 14:11 [PATCH i-g-t 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Gwan-gyeong Mun
` (6 preceding siblings ...)
2024-11-15 21:24 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2024-11-15 23:25 ` Patchwork
7 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2024-11-15 23:25 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 48040 bytes --]
== Series Details ==
Series: tests/intel/xe_eudebug_online: Introduce read/write pagefault tests
URL : https://patchwork.freedesktop.org/series/141401/
State : failure
== Summary ==
CI Bug Log - changes from XEIGT_8113_full -> XEIGTPW_12115_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with XEIGTPW_12115_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in XEIGTPW_12115_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in XEIGTPW_12115_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4:
- shard-dg2-set2: [PASS][1] -> [FAIL][2] +1 other test fail
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-434/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-dp2-hdmi-a3:
- shard-bmg: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-dp2-hdmi-a3.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-dp2-hdmi-a3.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp4:
- shard-dg2-set2: NOTRUN -> [FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-464/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html
* igt@kms_sysfs_edid_timing:
- shard-dg2-set2: [PASS][6] -> [DMESG-WARN][7]
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-466/igt@kms_sysfs_edid_timing.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-434/igt@kms_sysfs_edid_timing.html
* igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-system-system:
- shard-lnl: [PASS][8] -> [DMESG-WARN][9] +5 other tests dmesg-warn
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-4/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-system-system.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-3/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-system-system.html
* igt@xe_drm_fdinfo@utilization-single-full-load:
- shard-lnl: [PASS][10] -> [FAIL][11]
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-5/igt@xe_drm_fdinfo@utilization-single-full-load.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-7/igt@xe_drm_fdinfo@utilization-single-full-load.html
* {igt@xe_eudebug_online@pagefault-read} (NEW):
- shard-bmg: NOTRUN -> [SKIP][12] +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@xe_eudebug_online@pagefault-read.html
- shard-dg2-set2: NOTRUN -> [SKIP][13] +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@xe_eudebug_online@pagefault-read.html
- shard-lnl: NOTRUN -> [SKIP][14] +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-4/igt@xe_eudebug_online@pagefault-read.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init:
- shard-dg2-set2: NOTRUN -> [DMESG-WARN][15]
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-435/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html
#### Warnings ####
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
- shard-bmg: [SKIP][16] ([Intel XE#2311]) -> [INCOMPLETE][17]
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
* igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate:
- shard-bmg: [DMESG-FAIL][18] -> [DMESG-WARN][19]
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-7/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-6/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate.html
New tests
---------
New tests have been introduced between XEIGT_8113_full and XEIGTPW_12115_full:
### New IGT tests (2) ###
* igt@xe_eudebug_online@pagefault-read:
- Statuses : 3 skip(s)
- Exec time: [0.0] s
* igt@xe_eudebug_online@pagefault-write:
- Statuses : 3 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in XEIGTPW_12115_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs:
- shard-bmg: [PASS][20] -> [INCOMPLETE][21] ([Intel XE#2613]) +1 other test incomplete
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-6/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-4/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6:
- shard-dg2-set2: [PASS][22] -> [FAIL][23] ([Intel XE#1426]) +1 other test fail
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-436/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-434/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#2327])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
- shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#316])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-436/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-0:
- shard-bmg: [PASS][26] -> [INCOMPLETE][27] ([Intel XE#3225])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-3/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-3/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
- shard-dg2-set2: [PASS][28] -> [INCOMPLETE][29] ([Intel XE#1195] / [Intel XE#3225])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-436/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-433/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-dg2-set2: [PASS][30] -> [DMESG-WARN][31] ([Intel XE#877])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-435/igt@kms_big_fb@linear-64bpp-rotate-180.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#1124]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-6/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-dg2-set2: NOTRUN -> [SKIP][33] ([Intel XE#1124]) +3 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-434/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
- shard-dg2-set2: NOTRUN -> [SKIP][35] ([Intel XE#2191])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-436/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-2-displays-2560x1440p:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#367])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-2/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][37] ([Intel XE#787]) +76 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-436/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-dp-4.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#2887]) +6 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][39] ([Intel XE#2907])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-435/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][40] ([Intel XE#1195]) +2 other tests incomplete
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][42] ([Intel XE#455] / [Intel XE#787]) +23 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-434/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: [PASS][43] -> [INCOMPLETE][44] ([Intel XE#1195] / [Intel XE#1727])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4:
- shard-dg2-set2: [PASS][45] -> [DMESG-WARN][46] ([Intel XE#3113])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6:
- shard-dg2-set2: [PASS][47] -> [INCOMPLETE][48] ([Intel XE#1195] / [Intel XE#3124])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][49] ([Intel XE#314]) +3 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-464/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_chamelium_color@ctm-max:
- shard-dg2-set2: NOTRUN -> [SKIP][50] ([Intel XE#306])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-435/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_color@gamma:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#2325])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@kms_chamelium_color@gamma.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-dg2-set2: NOTRUN -> [SKIP][52] ([Intel XE#373]) +3 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-433/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_chamelium_hpd@dp-hpd-storm-disable:
- shard-bmg: NOTRUN -> [SKIP][53] ([Intel XE#2252]) +3 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-7/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html
* igt@kms_content_protection@legacy@pipe-a-dp-5:
- shard-dg2-set2: NOTRUN -> [FAIL][54] ([Intel XE#3304])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-466/igt@kms_content_protection@legacy@pipe-a-dp-5.html
* igt@kms_content_protection@type1:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#2341])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-7/igt@kms_content_protection@type1.html
* igt@kms_content_protection@uevent@pipe-a-dp-5:
- shard-dg2-set2: NOTRUN -> [FAIL][56] ([Intel XE#1188])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-466/igt@kms_content_protection@uevent@pipe-a-dp-5.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#2320]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_edge_walk@256x256-top-edge:
- shard-lnl: [PASS][58] -> [DMESG-WARN][59] ([Intel XE#2055])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-4/igt@kms_cursor_edge_walk@256x256-top-edge.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-8/igt@kms_cursor_edge_walk@256x256-top-edge.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-bmg: [PASS][60] -> [SKIP][61] ([Intel XE#2291]) +2 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-4/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-6/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2-set2: NOTRUN -> [SKIP][62] ([Intel XE#701])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@kms_feature_discovery@chamelium.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#2316]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1:
- shard-lnl: [PASS][64] -> [FAIL][65] ([Intel XE#886]) +7 other tests fail
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4:
- shard-dg2-set2: [PASS][66] -> [FAIL][67] ([Intel XE#301]) +8 other tests fail
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp2:
- shard-bmg: [PASS][68] -> [FAIL][69] ([Intel XE#2882]) +1 other test fail
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-6/igt@kms_flip@flip-vs-expired-vblank@a-dp2.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-7/igt@kms_flip@flip-vs-expired-vblank@a-dp2.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp4:
- shard-dg2-set2: NOTRUN -> [FAIL][70] ([Intel XE#301]) +2 other tests fail
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-464/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-lnl: [PASS][71] -> [FAIL][72] ([Intel XE#3149] / [Intel XE#886]) +1 other test fail
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-4/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-6/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_flip@wf_vblank-ts-check:
- shard-dg2-set2: [PASS][73] -> [FAIL][74] ([Intel XE#886]) +1 other test fail
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-433/igt@kms_flip@wf_vblank-ts-check.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-434/igt@kms_flip@wf_vblank-ts-check.html
* igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling:
- shard-lnl: [PASS][75] -> [DMESG-WARN][76] ([Intel XE#2929]) +1 other test dmesg-warn
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-6/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
- shard-dg2-set2: NOTRUN -> [SKIP][77] ([Intel XE#455]) +6 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-bmg: NOTRUN -> [SKIP][78] ([Intel XE#2380]) +1 other test skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][79] ([Intel XE#2293] / [Intel XE#2380])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][80] ([Intel XE#2293])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render:
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#2311]) +12 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-bmg: NOTRUN -> [FAIL][82] ([Intel XE#2333]) +7 other tests fail
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-dg2-set2: [PASS][83] -> [INCOMPLETE][84] ([Intel XE#1195])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#651]) +10 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-dg2-set2: NOTRUN -> [SKIP][86] ([Intel XE#1158])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-433/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
- shard-bmg: NOTRUN -> [SKIP][87] ([Intel XE#2350])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-1/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- shard-dg2-set2: NOTRUN -> [SKIP][88] ([Intel XE#653]) +11 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#2313]) +14 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3:
- shard-bmg: NOTRUN -> [FAIL][90] ([Intel XE#3312])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-1/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3.html
* igt@kms_joiner@basic-big-joiner:
- shard-bmg: NOTRUN -> [SKIP][91] ([Intel XE#346])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-3/igt@kms_joiner@basic-big-joiner.html
* igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
- shard-dg2-set2: [PASS][92] -> [FAIL][93] ([Intel XE#616]) +1 other test fail
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-436/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-433/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
* igt@kms_plane_cursor@viewport@pipe-a-edp-1-size-128:
- shard-lnl: [PASS][94] -> [FAIL][95] ([Intel XE#1471]) +1 other test fail
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-6/igt@kms_plane_cursor@viewport@pipe-a-edp-1-size-128.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-8/igt@kms_plane_cursor@viewport@pipe-a-edp-1-size-128.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a:
- shard-bmg: NOTRUN -> [SKIP][96] ([Intel XE#2763]) +4 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-3/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a.html
- shard-dg2-set2: NOTRUN -> [SKIP][97] ([Intel XE#2763]) +2 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-435/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d:
- shard-dg2-set2: NOTRUN -> [SKIP][98] ([Intel XE#2763] / [Intel XE#455]) +1 other test skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-435/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d.html
* igt@kms_pm_dc@deep-pkgc:
- shard-bmg: NOTRUN -> [SKIP][99] ([Intel XE#2505])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-2/igt@kms_pm_dc@deep-pkgc.html
* igt@kms_pm_rpm@cursor:
- shard-lnl: [PASS][100] -> [DMESG-WARN][101] ([Intel XE#3184]) +1 other test dmesg-warn
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-3/igt@kms_pm_rpm@cursor.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-7/igt@kms_pm_rpm@cursor.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
- shard-bmg: NOTRUN -> [SKIP][102] ([Intel XE#1489]) +2 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-7/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
- shard-dg2-set2: NOTRUN -> [SKIP][103] ([Intel XE#1489]) +3 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-434/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr@fbc-psr2-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][104] ([Intel XE#2850] / [Intel XE#929]) +6 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-435/igt@kms_psr@fbc-psr2-dpms.html
* igt@kms_psr@pr-suspend:
- shard-bmg: NOTRUN -> [SKIP][105] ([Intel XE#2234] / [Intel XE#2850]) +7 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-2/igt@kms_psr@pr-suspend.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-bmg: NOTRUN -> [SKIP][106] ([Intel XE#2414])
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-dg2-set2: NOTRUN -> [SKIP][107] ([Intel XE#3414])
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
- shard-lnl: [PASS][108] -> [FAIL][109] ([Intel XE#899]) +1 other test fail
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
* igt@kms_vrr@flip-basic-fastset:
- shard-bmg: NOTRUN -> [SKIP][110] ([Intel XE#1499])
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-5/igt@kms_vrr@flip-basic-fastset.html
* igt@xe_drm_fdinfo@utilization-others-full-load:
- shard-lnl: [PASS][111] -> [FAIL][112] ([Intel XE#2667])
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-1/igt@xe_drm_fdinfo@utilization-others-full-load.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-8/igt@xe_drm_fdinfo@utilization-others-full-load.html
* igt@xe_eudebug@basic-vm-access-parameters:
- shard-dg2-set2: NOTRUN -> [SKIP][113] ([Intel XE#2905]) +4 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-434/igt@xe_eudebug@basic-vm-access-parameters.html
* igt@xe_eudebug@discovery-race:
- shard-bmg: NOTRUN -> [SKIP][114] ([Intel XE#2905]) +2 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-6/igt@xe_eudebug@discovery-race.html
* igt@xe_evict@evict-beng-mixed-many-threads-large:
- shard-dg2-set2: NOTRUN -> [TIMEOUT][115] ([Intel XE#1473])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-434/igt@xe_evict@evict-beng-mixed-many-threads-large.html
* igt@xe_evict@evict-beng-threads-large:
- shard-bmg: NOTRUN -> [TIMEOUT][116] ([Intel XE#1473]) +1 other test timeout
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-5/igt@xe_evict@evict-beng-threads-large.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
- shard-bmg: NOTRUN -> [SKIP][117] ([Intel XE#2322]) +4 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-2/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html
* igt@xe_exec_fault_mode@once-invalid-userptr-fault:
- shard-dg2-set2: NOTRUN -> [SKIP][118] ([Intel XE#288]) +10 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-436/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html
* igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
- shard-dg2-set2: NOTRUN -> [SKIP][119] ([Intel XE#2360])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-433/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
* igt@xe_live_ktest@xe_migrate:
- shard-bmg: [PASS][120] -> [SKIP][121] ([Intel XE#1192])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-1/igt@xe_live_ktest@xe_migrate.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-6/igt@xe_live_ktest@xe_migrate.html
* igt@xe_oa@closed-fd-and-unmapped-access:
- shard-dg2-set2: NOTRUN -> [SKIP][122] ([Intel XE#2541]) +4 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-433/igt@xe_oa@closed-fd-and-unmapped-access.html
* igt@xe_pm@s2idle-d3cold-basic-exec:
- shard-bmg: NOTRUN -> [SKIP][123] ([Intel XE#2284])
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-3/igt@xe_pm@s2idle-d3cold-basic-exec.html
* igt@xe_pm@s4-vm-bind-prefetch:
- shard-lnl: [PASS][124] -> [ABORT][125] ([Intel XE#1607] / [Intel XE#1794])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-3/igt@xe_pm@s4-vm-bind-prefetch.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-2/igt@xe_pm@s4-vm-bind-prefetch.html
* igt@xe_pm_residency@toggle-gt-c6:
- shard-lnl: [PASS][126] -> [FAIL][127] ([Intel XE#958])
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-5/igt@xe_pm_residency@toggle-gt-c6.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-2/igt@xe_pm_residency@toggle-gt-c6.html
* igt@xe_query@multigpu-query-invalid-extension:
- shard-bmg: NOTRUN -> [SKIP][128] ([Intel XE#944])
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-3/igt@xe_query@multigpu-query-invalid-extension.html
- shard-dg2-set2: NOTRUN -> [SKIP][129] ([Intel XE#944]) +1 other test skip
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-436/igt@xe_query@multigpu-query-invalid-extension.html
* igt@xe_sriov_flr@flr-vf1-clear:
- shard-bmg: NOTRUN -> [SKIP][130] ([Intel XE#3342])
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-1/igt@xe_sriov_flr@flr-vf1-clear.html
#### Possible fixes ####
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-bmg: [FAIL][131] ([Intel XE#1426]) -> [PASS][132] +1 other test pass
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
- shard-bmg: [SKIP][133] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-2/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [INCOMPLETE][135] ([Intel XE#1195] / [Intel XE#1727]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
- shard-dg2-set2: [INCOMPLETE][137] ([Intel XE#1195]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6:
- shard-dg2-set2: [DMESG-WARN][139] -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html
* igt@kms_display_modes@extended-mode-basic@pipe-c-dp-2-pipe-a-hdmi-a-3:
- shard-bmg: [DMESG-WARN][141] ([Intel XE#877]) -> [PASS][142] +1 other test pass
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-7/igt@kms_display_modes@extended-mode-basic@pipe-c-dp-2-pipe-a-hdmi-a-3.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-1/igt@kms_display_modes@extended-mode-basic@pipe-c-dp-2-pipe-a-hdmi-a-3.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3:
- shard-bmg: [FAIL][143] -> [PASS][144] +3 other tests pass
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-3/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-bmg: [FAIL][145] ([Intel XE#2882]) -> [PASS][146] +1 other test pass
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-lnl: [FAIL][147] ([Intel XE#886]) -> [PASS][148] +2 other tests pass
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-4/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-6/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@xe_compute_preempt@compute-preempt:
- shard-bmg: [FAIL][149] ([Intel XE#3354]) -> [PASS][150] +1 other test pass
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-6/igt@xe_compute_preempt@compute-preempt.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-1/igt@xe_compute_preempt@compute-preempt.html
- shard-lnl: [FAIL][151] ([Intel XE#2959]) -> [PASS][152] +1 other test pass
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-5/igt@xe_compute_preempt@compute-preempt.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-3/igt@xe_compute_preempt@compute-preempt.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [TIMEOUT][153] ([Intel XE#1473] / [Intel XE#2472]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-1/igt@xe_evict@evict-mixed-many-threads-small.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_exec_threads@threads-cm-shared-vm-userptr-invalidate:
- shard-bmg: [DMESG-WARN][155] -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-4/igt@xe_exec_threads@threads-cm-shared-vm-userptr-invalidate.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-7/igt@xe_exec_threads@threads-cm-shared-vm-userptr-invalidate.html
* igt@xe_oa@oa-regs-whitelisted:
- shard-lnl: [FAIL][157] ([Intel XE#2514]) -> [PASS][158] +1 other test pass
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-7/igt@xe_oa@oa-regs-whitelisted.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-2/igt@xe_oa@oa-regs-whitelisted.html
- shard-bmg: [FAIL][159] ([Intel XE#2514]) -> [PASS][160]
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-2/igt@xe_oa@oa-regs-whitelisted.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-5/igt@xe_oa@oa-regs-whitelisted.html
* igt@xe_pm@d3hot-mmap-system:
- shard-lnl: [DMESG-WARN][161] ([Intel XE#3184]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-4/igt@xe_pm@d3hot-mmap-system.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-2/igt@xe_pm@d3hot-mmap-system.html
#### Warnings ####
* igt@kms_flip@plain-flip-fb-recreate:
- shard-lnl: [FAIL][163] ([Intel XE#886]) -> [FAIL][164] ([Intel XE#3149] / [Intel XE#886])
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-4/igt@kms_flip@plain-flip-fb-recreate.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-6/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][165] ([Intel XE#2311]) -> [SKIP][166] ([Intel XE#2312]) +1 other test skip
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][167] ([Intel XE#2312]) -> [SKIP][168] ([Intel XE#2311])
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][169] ([Intel XE#2312]) -> [SKIP][170] ([Intel XE#2313]) +2 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
- shard-dg2-set2: [SKIP][171] ([Intel XE#2763] / [Intel XE#455]) -> [INCOMPLETE][172] ([Intel XE#1195])
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-466/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-464/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c:
- shard-dg2-set2: [SKIP][173] ([Intel XE#2763]) -> [INCOMPLETE][174] ([Intel XE#1195])
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-dg2-466/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-dg2-464/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][175] ([Intel XE#2509]) -> [SKIP][176] ([Intel XE#2426])
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_live_ktest@xe_eudebug:
- shard-bmg: [SKIP][177] ([Intel XE#1192]) -> [SKIP][178] ([Intel XE#2833])
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-bmg-4/igt@xe_live_ktest@xe_eudebug.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-bmg-4/igt@xe_live_ktest@xe_eudebug.html
- shard-lnl: [SKIP][179] ([Intel XE#2833]) -> [SKIP][180] ([Intel XE#1192] / [Intel XE#3026])
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8113/shard-lnl-8/igt@xe_live_ktest@xe_eudebug.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/shard-lnl-7/igt@xe_live_ktest@xe_eudebug.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
[Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
[Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
[Intel XE#1471]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1471
[Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#2055]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2055
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2350
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2472]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2472
[Intel XE#2505]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2505
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2514]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2514
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#2613]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2613
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2667]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2667
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2929
[Intel XE#2959]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2959
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3026]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3026
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
[Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3184]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3184
[Intel XE#3225]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3225
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3312
[Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
[Intel XE#3354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3354
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[Intel XE#958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/958
Build changes
-------------
* IGT: IGT_8113 -> IGTPW_12115
IGTPW_12115: 12115
IGT_8113: 55e8731f083c9dbb1b5969104b56e8be85225cc7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2235-36fec0eb87867bca47f8829c9e5dbf5b3e2b3aaf: 36fec0eb87867bca47f8829c9e5dbf5b3e2b3aaf
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12115/index.html
[-- Attachment #2: Type: text/html, Size: 54734 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 1/4] lib/gppgu_shader: Add write to ppgtt offset
2024-11-15 14:11 ` [PATCH i-g-t 1/4] lib/gppgu_shader: Add write to ppgtt offset Gwan-gyeong Mun
@ 2024-11-18 13:00 ` Hajda, Andrzej
2024-11-21 12:01 ` Gwan-gyeong Mun
0 siblings, 1 reply; 24+ messages in thread
From: Hajda, Andrzej @ 2024-11-18 13:00 UTC (permalink / raw)
To: Gwan-gyeong Mun, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
W dniu 15.11.2024 o 15:11, Gwan-gyeong Mun pisze:
> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>
> Create a function that adds the capacity to fill an oword at a given
> ppgtt offset with a dword value. Xe2 does this with an Untyped 2D Block
> Array Store operation, though older platforms used to do this with a
> Media Write Block, so both means are supported.
>
> Suggested-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> ---
> lib/gpgpu_shader.c | 109 ++++++++++++++++++++++++++++++++++++
> lib/gpgpu_shader.h | 2 +
> lib/iga64_generated_codes.c | 81 ++++++++++++++++++++++++++-
> 3 files changed, 191 insertions(+), 1 deletion(-)
>
> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
> index 4e1b8d5e9..7a2f0d28d 100644
> --- a/lib/gpgpu_shader.c
> +++ b/lib/gpgpu_shader.c
> @@ -652,6 +652,115 @@ void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
> ", 2, y_offset, 3, value, value, value, value);
> }
>
> +/**
> + * gpgpu_shader__write_offset:
> + * @shdr: shader to be modified
> + * @ppgtt_offset: write target virtual address
> + * @value: dword to be written
> + *
> + * Fill oword at @ppgtt with dword stored in @value.
> + *
> + * Note: for the write to succeed, the address specified by @ppgtt_offset has
> + * to be bound. Otherwise a page fault will be triggered.
> + */
> +void gpgpu_shader__write_offset(struct gpgpu_shader *shdr, uint64_t ppgtt_offset,
> + uint32_t value)
The name is somehow misleading, maybe gpgpu_shader__fill_a64_4dw?
Anything better?
> +{
> + uint64_t offset = CANONICAL(ppgtt_offset);
> + igt_assert_f((offset & 0xf) == 0, "Offset must be aligned to oword!\n");
> +
> + emit_iga64_code(shdr, write_offset, " \n\
> +#if GEN_VER < 2000 // Media Block Write \n\
> +(W) mov (8|M0) r30.0<1>:ud 0x0:ud \n\
> + // canonical address \n\
> +(W) mov (1|M0) r30.0<1>:ud ARG(0):ud \n\
> +(W) mov (1|M0) r30.1<1>:ud ARG(1):ud \n\
> + // written value \n\
> +(W) mov (1|M0) r31.0<1>:ud ARG(2):ud \n\
> +(W) mov (1|M0) r31.1<1>:ud ARG(3):ud \n\
> +(W) mov (1|M0) r31.2<1>:ud ARG(4):ud \n\
> +(W) mov (1|M0) r31.3<1>:ud ARG(5):ud \n\
It could be replaced by "mov (4) r31.0<1>:ud ARG(2):ud", and then
removed duplicated arguments ARGS(3-5).
> + // owblock write \n\
> +(W) send.dc1 (16|M0) null r30 r31 0x0 0x20d40ff \n\
> + // owblock read, to block the thread until the write is materialized \n\
> +(W) send.dc1 (16|M0) r32 r30 null 0x0 0x21500ff \n\
> +#else // Unyped 2D Block Store \n\
> +// Instruction_Store2DBlock \n\
> +// bspec: 63981 \n\
> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies both \n\
> +// the block parameters and the 2D Surface parameters. \n\
> +// src1 data payload format is selected by Data Size. \n\
> +// Untyped2DBLOCKAddressPayload \n\
> +// bspec: 63986 \n\
> +// [243:240] Array Length: 0 (length is 1) \n\
> +// [239:232] Block Height: 0 (height is 1) \n\
> +// [231:224] Block Width: 0xf (width is 16) \n\
> +// [223:192] Block Start Y: 0 \n\
> +// [191:160] Block Start X: 0 \n\
> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 bytes) \n\
> +// [127:96] Untyped 2D Surface Height: 0 (height is 1) \n\
> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 bytes) \n\
> +// [63:0] Untyped 2D Surface Base Address \n\
> +// initialize register \n\
> +(W) mov (8) r30.0<1>:uq 0x0:uq \n\
> +// [0:31] Untyped 2D Surface Base Address low \n\
> +(W) mov (1) r30.0<1>:ud ARG(0):ud \n\
> +// [32:63] Untyped 2D Surface Base Address high \n\
> +(W) mov (1) r30.1<1>:ud ARG(1):ud \n\
> +// [95:64] Untyped 2D Surface Width: 0x3f \n\
> +// (Width minus 1 (in bytes) of the 2D surface, it represents 64) \n\
> +(W) mov (1) r30.2<1>:ud 0x3f:ud \n\
> +// [127:96] Untyped 2D Surface Height: 0x0 \n\
> +// (Height minus 1 (in number of data elements) of \n\
> +// the Untyped 2D surface, it represents 1) \n\
> +(W) mov (1) r30.3<1>:ud 0x0:ud \n\
> +// [159:128] Untyped 2D Surface Pitch: 0x3f \n\
> +// (Pitch minus 1 (in bytes) of the 2D surface, it represents 64) \n\
> +(W) mov (1) r30.4<1>:ud 0x3f:ud \n\
> +// [231:224] Block Width: 0xf (15) \n\
> +// (Specifies the width minus 1 (in number of data elements) for this \n\
> +// rectangular region, it represents 16) \n\
> +// Block width (encoded_value + 1) must be a multiple of DW (4 bytes). \n\
> +// [239:232] Block Height: 0 \n\
> +// (Specifies the height minus 1 (in number of data elements) for \n\
> +// this rectangular region, it represents 1) \n\
> +// [243:240] Array Length: 0 \n\
> +// (Specifies Array Length minus 1 for Load2DBlockArray messages, \n\
> +// must be zero for 2D Block Store messages, it represents 1) \n\
> +(W) mov (1) r30.7<1>:ud 0xf:ud \n\
> +// src1 data payload size \n\
> +// Block Height x Block Width x Data size / GRF Register size \n\
> +// => 1 x 16 x 32bit / 512bit = 1 \n\
> +// data payload size is 1 \n\
> +(W) mov (8) r31.0<1>:uq 0x0:uq \n\
> +(W) mov (1|M0) r31.0<1>:ud ARG(2):ud \n\
> +(W) mov (1|M0) r31.1<1>:ud ARG(3):ud \n\
> +(W) mov (1|M0) r31.2<1>:ud ARG(4):ud \n\
> +(W) mov (1|M0) r31.3<1>:ud ARG(5):ud \n\
> +// send.ugm Untyped 2D Block Array Store \n\
> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc \n\
> +// Execution Mask restriction: SIMT1 \n\
> +// \n\
> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D Block) \n\
> +// bspec: 67780 \n\
> +// 0x0 => \n\
> +// [32:22] Global Y_offset: 0 \n\
> +// [21:12] Global X_offset: 0 \n\
> +// \n\
> +// Message Descriptor \n\
> +// bspec: 63981 \n\
> +// 0x2020407 => \n\
> +// [30:29] Address Type: 0 (FLAT) \n\
> +// [28:25] Src0 Length: 1 \n\
> +// [24:20] Dest Length: 0 \n\
> +// [19:16] Cache : 2 (L1UC_L3UC) \n\
> +// [11:9] Data Size: 2 (D32) \n\
> +// [5:0] Store Operation: 7 \n\
> +(W) send.ugm (1) null r30 r31:1 0x0 0x2020407 \n\
> +#endif \n\
> + ", offset & 0xffffffff, offset >> 32, value, value, value, value);
with above change, and proper macros line above becomes:
, lower_32_bits(offset), upper_32_bits(offset), value);
> +}
> +
> /**
> * gpgpu_shader__clear_exception:
> * @shdr: shader to be modified
> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
> index c7c21c115..355b128b5 100644
> --- a/lib/gpgpu_shader.h
> +++ b/lib/gpgpu_shader.h
> @@ -83,6 +83,8 @@ void gpgpu_shader__write_aip(struct gpgpu_shader *shdr, uint32_t y_offset);
> void gpgpu_shader__increase_aip(struct gpgpu_shader *shdr, uint32_t value);
> void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
> uint32_t y_offset);
> +void gpgpu_shader__write_offset(struct gpgpu_shader *shdr, uint64_t ppgtt_offset,
> + uint32_t value);
> void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
> uint32_t y_offset, uint32_t mask, uint32_t value);
> void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
> index 6638be07b..b23613ac4 100644
> --- a/lib/iga64_generated_codes.c
> +++ b/lib/iga64_generated_codes.c
> @@ -3,7 +3,7 @@
>
> #include "gpgpu_shader.h"
>
> -#define MD5_SUM_IGA64_ASMS ec9d477415eebb7d6983395f1bcde78f
> +#define MD5_SUM_IGA64_ASMS 4fcde43dedb9d3212f1d85b5b180b0c1
>
> struct iga64_template const iga64_code_gpgpu_fill[] = {
> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> @@ -323,6 +323,85 @@ struct iga64_template const iga64_code_clear_exception[] = {
> }}
> };
>
> +struct iga64_template const iga64_code_write_offset[] = {
> + { .gen_ver = 2000, .size = 64, .code = (const uint32_t []) {
> + 0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
> + 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
> + 0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
> + 0x80000061, 0x1e354220, 0x00000000, 0x00000000,
> + 0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
> + 0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
> + 0x800c0061, 0x1f054330, 0x00000000, 0x00000000,
> + 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
> + 0x80000061, 0x1f154220, 0x00000000, 0xc0ded003,
> + 0x80000061, 0x1f254220, 0x00000000, 0xc0ded004,
> + 0x80000061, 0x1f354220, 0x00000000, 0xc0ded005,
> + 0x80032031, 0x00000000, 0xf80e1e0c, 0x00801f0c,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 1270, .size = 52, .code = (const uint32_t []) {
> + 0x80030061, 0x1e054220, 0x00000000, 0x00000000,
> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
> + 0x80000061, 0x1e254220, 0x00000000, 0xc0ded001,
> + 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
> + 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
> + 0x80000061, 0x1f454220, 0x00000000, 0xc0ded004,
> + 0x80000061, 0x1f654220, 0x00000000, 0xc0ded005,
> + 0x80001d01, 0x00010000, 0x00000000, 0x00000000,
> + 0x80044031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
> + 0x80044131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 1260, .size = 48, .code = (const uint32_t []) {
> + 0x800c0061, 0x1e054220, 0x00000000, 0x00000000,
> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
> + 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
> + 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
> + 0x80000061, 0x1f154220, 0x00000000, 0xc0ded003,
> + 0x80000061, 0x1f254220, 0x00000000, 0xc0ded004,
> + 0x80000061, 0x1f354220, 0x00000000, 0xc0ded005,
> + 0x8013a031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
> + 0x8010c131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 1250, .size = 52, .code = (const uint32_t []) {
> + 0x80030061, 0x1e054220, 0x00000000, 0x00000000,
> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
> + 0x80000061, 0x1e254220, 0x00000000, 0xc0ded001,
> + 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
> + 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
> + 0x80000061, 0x1f454220, 0x00000000, 0xc0ded004,
> + 0x80000061, 0x1f654220, 0x00000000, 0xc0ded005,
> + 0x80001d01, 0x00010000, 0x00000000, 0x00000000,
> + 0x80044031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
> + 0x80044131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 0, .size = 48, .code = (const uint32_t []) {
> + 0x80030061, 0x1e054220, 0x00000000, 0x00000000,
> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
> + 0x80000061, 0x1e254220, 0x00000000, 0xc0ded001,
> + 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
> + 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
> + 0x80000061, 0x1f454220, 0x00000000, 0xc0ded004,
> + 0x80000061, 0x1f654220, 0x00000000, 0xc0ded005,
> + 0x8004d031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
> + 0x80044131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000101, 0x00010000, 0x00000000, 0x00000000,
> + }}
> +};
> +
> struct iga64_template const iga64_code_media_block_write[] = {
> { .gen_ver = 2000, .size = 56, .code = (const uint32_t []) {
> 0x80100061, 0x04054220, 0x00000000, 0x00000000,
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 2/4] lib/gpgpu_shader: Add causing a read pagefault from the eu thread
2024-11-15 14:11 ` [PATCH i-g-t 2/4] lib/gpgpu_shader: Add causing a read pagefault from the eu thread Gwan-gyeong Mun
@ 2024-11-18 13:08 ` Hajda, Andrzej
2024-11-21 12:02 ` Gwan-gyeong Mun
2024-11-19 11:38 ` Manszewski, Christoph
1 sibling, 1 reply; 24+ messages in thread
From: Hajda, Andrzej @ 2024-11-18 13:08 UTC (permalink / raw)
To: Gwan-gyeong Mun, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
W dniu 15.11.2024 o 15:11, Gwan-gyeong Mun pisze:
> Create a function that causing a read pagefault using the eu thread load
> instruction. If the given ppgtt address points to an unallocated ppgtt
> virtual address, this shader can cause a read pagefault.
> To directly use a 64-bit address as an argument, use the
> Untyped 2D Block Array Load Instruction.
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> lib/gpgpu_shader.c | 92 +++++++++++++++++++++++++++++++++++++
> lib/gpgpu_shader.h | 1 +
> lib/iga64_generated_codes.c | 21 ++++++++-
> 3 files changed, 113 insertions(+), 1 deletion(-)
>
> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
> index 7a2f0d28d..d7c47be80 100644
> --- a/lib/gpgpu_shader.c
> +++ b/lib/gpgpu_shader.c
> @@ -912,3 +912,95 @@ void gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
> ", 0x807fffff, /* leave breakpoint exception */
> y_offset, value, 0x7fffff /* clear all exceptions */ );
> }
> +
> +/**
> + * gpgpu_shader__read_page_fault:
> + * @shdr: shader to be modified
> + * @ppgtt_addr: ppgtt virtual address to raise pagefault
> + *
> + * For a given arbitrary ppgtt virtual address, it raises a pagefault using
> + * the eu thread load instruction.
> + */
> +void gpgpu_shader__read_page_fault(struct gpgpu_shader *shdr, uint64_t ppgtt_addr)
> +{
> + /* pagefault ppgtt virtual address */
> + uint64_t addr = CANONICAL(ppgtt_addr);
> +
> + igt_assert_f((addr & 0x3) == 0, "address must be aligned to DWord!\n");
> +
> + emit_iga64_code(shdr, read_page_fault, " \n\
> +#if GEN_VER >= 2000 \n\
> +// Unyped 2D Block Array Load \n\
> +// Instruction_Load2DBlockArray \n\
> +// bspec: 63972 \n\
> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies both \n\
> +// the block parameters and the 2D Surface parameters. \n\
> +// Untyped2DBLOCKAddressPayload \n\
> +// bspec: 63986 \n\
> +// [243:240] Array Length: 0 (length is 1) \n\
> +// [239:232] Block Height: 0 (height is 1) \n\
> +// [231:224] Block Width: 0xf (width is 16) \n\
> +// [223:192] Block Start Y: 0 \n\
> +// [191:160] Block Start X: 0 \n\
> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 bytes) \n\
> +// [127:96] Untyped 2D Surface Height: 0 (height is 1) \n\
> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 bytes) \n\
> +// [63:0] Untyped 2D Surface Base Address \n\
> +// initialize register \n\
> +(W) mov (8) r30.0<1>:uq 0x0:uq \n\
> +// [0:31] Untyped 2D Surface Base Address low \n\
> +(W) mov (1) r30.0<1>:ud ARG(0):ud \n\
> +// [32:63] Untyped 2D Surface Base Address high \n\
> +(W) mov (1) r30.1<1>:ud ARG(1):ud \n\
> +// [95:64] Untyped 2D Surface Width: 0x3f \n\
> +// (Width minus 1 (in bytes) of the 2D surface, it represents 64) \n\
> +(W) mov (1) r30.2<1>:ud 0x3f:ud \n\
> +// [127:96] Untyped 2D Surface Height: 0x0 \n\
> +// (Height minus 1 (in number of data elements) of \n\
> +// the Untyped 2D surface, it represents 1) \n\
> +(W) mov (1) r30.3<1>:ud 0x0:ud \n\
> +// [159:128] Untyped 2D Surface Pitch: 0x3f \n\
> +// (Pitch minus 1 (in bytes) of the 2D surface, it represents 64) \n\
> +(W) mov (1) r30.4<1>:ud 0x3f:ud \n\
> +// [231:224] Block Width: 0xf (15) \n\
> +// (Specifies the width minus 1 (in number of data elements) for this \n\
> +// rectangular region, it represents 16) \n\
> +// Block width (encoded_value + 1) must be a multiple of DW (4 bytes). \n\
> +// [239:232] Block Height: 0 \n\
> +// (Specifies the height minus 1 (in number of data elements) for \n\
> +// this rectangular region, it represents 1) \n\
> +// [243:240] Array Length: 0 \n\
> +// (Specifies Array Length minus 1 for Load2DBlockArray messages, \n\
> +// must be zero for 2D Block Store messages, it represents 1) \n\
> +(W) mov (1) r30.7<1>:ud 0xf:ud \n\
It duplicates code from gpgpu_shader__write_offset, could be replaced
with macros as in https://patchwork.freedesktop.org/series/141348/ , but
no rush :)
> +// \n\
> +// dest data payload format is selected by Data Size. \n\
> +// Block Height x Block Width x Data size / GRF Register size \n\
> +// => 1 x 16 x 32bit / 512bit = 1 \n\
> +// data payload format size is 1 GRF Register. \n\
> +// \n\
> +// send.ugm Untyped 2D Block Array Load \n\
> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc \n\
> +// Execution Mask restriction: SIMT1 \n\
> +// \n\
> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D Block) \n\
> +// bspec: 67780 \n\
> +// 0x0 => \n\
> +// [32:22] Global Y_offset: 0 \n\
> +// [21:12] Global X_offset: 0 \n\
> +// \n\
> +// Message Descriptor \n\
> +// bspec: 63972 \n\
> +// 0x2128403 => \n\
> +// [30:29] Address Type: 0 (FLAT) \n\
> +// [28:25] Src0 Length: 1 \n\
> +// [24:20] Dest Length: 1 \n\
> +// [19:16] Cache : 2 (L1UC_L3UC) 10 \n\
> +// [15] Transpose Block: 1 \n\
> +// [11:9] Data Size: 2 (D32) 10 \n\
> +// [7] VNNI Transform: 0 \n\
> +// [5:0] Load Operation: 3 (Load 2D Block) 11 \n\
> +(W) send.ugm (1) r31 r30 null 0x0 0x2128403 \n\
> +#endif \n\
> + ", lower_32_bits(addr), upper_32_bits(addr));
> +}
> \ No newline at end of file
New line
> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
> index 355b128b5..318550c52 100644
> --- a/lib/gpgpu_shader.h
> +++ b/lib/gpgpu_shader.h
> @@ -87,6 +87,7 @@ void gpgpu_shader__write_offset(struct gpgpu_shader *shdr, uint64_t ppgtt_offset
> uint32_t value);
> void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
> uint32_t y_offset, uint32_t mask, uint32_t value);
> +void gpgpu_shader__read_page_fault(struct gpgpu_shader *shdr, uint64_t ppgtt_addr);
> void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
> void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
> void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
> index b23613ac4..53a705358 100644
> --- a/lib/iga64_generated_codes.c
> +++ b/lib/iga64_generated_codes.c
> @@ -3,7 +3,7 @@
>
> #include "gpgpu_shader.h"
>
> -#define MD5_SUM_IGA64_ASMS 4fcde43dedb9d3212f1d85b5b180b0c1
> +#define MD5_SUM_IGA64_ASMS 01290b5ecda7a6e765463558d6f59952
>
> struct iga64_template const iga64_code_gpgpu_fill[] = {
> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> @@ -79,6 +79,25 @@ struct iga64_template const iga64_code_gpgpu_fill[] = {
> }}
> };
>
> +struct iga64_template const iga64_code_read_page_fault[] = {
> + { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> + 0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
> + 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
> + 0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
> + 0x80000061, 0x1e354220, 0x00000000, 0x00000000,
> + 0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
> + 0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
> + 0x80032031, 0x1f0c0000, 0xf8061e0c, 0x00a00000,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
> +
> + }}
> +};
> +
> struct iga64_template const iga64_code_end_system_routine_step_if_eq[] = {
> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> 0x80000966, 0x80018220, 0x02008000, 0x00008000,
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 3/4] eudebug: Add eudebug pagefault event declarations
2024-11-15 14:11 ` [PATCH i-g-t 3/4] eudebug: Add eudebug pagefault event declarations Gwan-gyeong Mun
@ 2024-11-18 16:52 ` Hajda, Andrzej
2024-11-19 8:50 ` Manszewski, Christoph
2024-11-19 12:26 ` Manszewski, Christoph
1 sibling, 1 reply; 24+ messages in thread
From: Hajda, Andrzej @ 2024-11-18 16:52 UTC (permalink / raw)
To: Gwan-gyeong Mun, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
W dniu 15.11.2024 o 15:11, Gwan-gyeong Mun pisze:
> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>
> Update the xe_eudebug drm to include pagefault events.
>
> Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> ---
> include/drm-uapi-experimental/xe_drm_eudebug.h | 13 +++++++++++++
I am lost between prelim/eudebug/experimental header placements. So just
out of curiosity what is the role of drm-uapi-experimental comparing to
prelim or just drm-uapi?
> lib/xe/xe_eudebug.c | 11 +++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/include/drm-uapi-experimental/xe_drm_eudebug.h b/include/drm-uapi-experimental/xe_drm_eudebug.h
> index f50051e9a..ed2e728c2 100644
> --- a/include/drm-uapi-experimental/xe_drm_eudebug.h
> +++ b/include/drm-uapi-experimental/xe_drm_eudebug.h
> @@ -154,6 +154,7 @@ struct drm_xe_eudebug_event {
> #define DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE 9
> #define DRM_XE_EUDEBUG_EVENT_METADATA 10
> #define DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_METADATA 11
> +#define DRM_XE_EUDEBUG_EVENT_PAGEFAULT 12
>
> __u16 flags;
> #define DRM_XE_EUDEBUG_EVENT_CREATE (1 << 0)
> @@ -352,6 +353,18 @@ struct drm_xe_eudebug_event_vm_bind_op_metadata {
> __u64 metadata_cookie;
> };
>
> +struct drm_xe_eudebug_event_pagefault {
> + struct drm_xe_eudebug_event base;
> +
> + __u64 client_handle;
> + __u64 exec_queue_handle;
> + __u64 lrc_handle;
> + __u32 flags;
> + __u32 bitmask_size;
> + __u64 pagefault_address;
> + __u8 bitmask[];
> +};
> +
> #if defined(__cplusplus)
> }
> #endif
> diff --git a/lib/xe/xe_eudebug.c b/lib/xe/xe_eudebug.c
> index c5814421b..de01e6b49 100644
> --- a/lib/xe/xe_eudebug.c
> +++ b/lib/xe/xe_eudebug.c
> @@ -91,6 +91,8 @@ static const char *type_to_str(unsigned int type)
> return "metadata";
> case DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_METADATA:
> return "vm_bind_op_metadata";
> + case DRM_XE_EUDEBUG_EVENT_PAGEFAULT:
> + return "pagefault";
> }
>
> return "UNKNOWN";
> @@ -222,6 +224,15 @@ static const char *event_members_to_str(struct drm_xe_eudebug_event *e, char *bu
> op->vm_bind_op_ref_seqno, op->metadata_handle, op->metadata_cookie);
> break;
> }
> + case DRM_XE_EUDEBUG_EVENT_PAGEFAULT: {
> + struct drm_xe_eudebug_event_pagefault *pf = (void *)e;
maybe better: pf = container_of(e, pf, base);
Beside this:
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Regards
Andrzej
> +
> + sprintf(buf, "client_handle=%llu, exec_queue_handle=%llu, "
> + "lrc_handle=%llu, bitmask_size=%d, pagefault_address=0x%llx",
> + pf->client_handle, pf->exec_queue_handle, pf->lrc_handle,
> + pf->bitmask_size, pf->pagefault_address);
> + break;
> + }
> default:
> strcpy(buf, "<...>");
> }
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests
2024-11-15 14:11 ` [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests Gwan-gyeong Mun
@ 2024-11-19 8:10 ` Hajda, Andrzej
2024-11-21 12:06 ` Gwan-gyeong Mun
2024-11-19 15:58 ` Hajda, Andrzej
2024-11-19 16:49 ` Manszewski, Christoph
2 siblings, 1 reply; 24+ messages in thread
From: Hajda, Andrzej @ 2024-11-19 8:10 UTC (permalink / raw)
To: Gwan-gyeong Mun, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
W dniu 15.11.2024 o 15:11, Gwan-gyeong Mun pisze:
> Add read and write pagefault tests to xe_eudebug_online that checks if a
> pagefault event is submitted by the KMD debugger when a pagefault occurs.
>
> Test that read (load instruction) and write(store instruction) attempt to
> load or store access to unallocated memory, causing a pagefault.
> Examine the address causing the page fault and the number of eu threads
> causing the pagefault.
>
> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> tests/intel/xe_eudebug_online.c | 219 +++++++++++++++++++++++++++++++-
> 1 file changed, 215 insertions(+), 4 deletions(-)
>
> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/xe_eudebug_online.c
> index 0ef0d8093..eae0eb520 100644
> --- a/tests/intel/xe_eudebug_online.c
> +++ b/tests/intel/xe_eudebug_online.c
> @@ -36,6 +36,8 @@
> #define BB_IN_VRAM (1 << 11)
> #define TARGET_IN_SRAM (1 << 12)
> #define TARGET_IN_VRAM (1 << 13)
> +#define SHADER_PAGEFAULT_READ (1 << 14)
> +#define SHADER_PAGEFAULT_WRITE (1 << 15)
> #define TRIGGER_UFENCE_SET_BREAKPOINT (1 << 24)
> #define TRIGGER_RESUME_SINGLE_WALK (1 << 25)
> #define TRIGGER_RESUME_PARALLEL_WALK (1 << 26)
> @@ -45,6 +47,7 @@
> #define TRIGGER_RESUME_DSS (1 << 30)
> #define TRIGGER_RESUME_ONE (1 << 31)
>
> +#define SHADER_PAGEFAULT (SHADER_PAGEFAULT_READ | SHADER_PAGEFAULT_WRITE)
> #define BB_REGION_BITMASK (BB_IN_SRAM | BB_IN_VRAM)
> #define TARGET_REGION_BITMASK (TARGET_IN_SRAM | TARGET_IN_VRAM)
>
> @@ -61,6 +64,8 @@
> #define CACHING_VALUE(n) (CACHING_INIT_VALUE + (n))
>
> #define SHADER_CANARY 0x01010101
> +#define BAD_CANARY 0xf1f1f1f
> +#define BAD_OFFSET (0x12345678ull << 12)
>
> #define WALKER_X_DIM 4
> #define WALKER_ALIGNMENT 16
> @@ -123,6 +128,9 @@ static int get_number_of_threads(uint64_t flags)
> if (flags & SHADER_MIN_THREADS)
> return 16;
>
> + if (flags & SHADER_PAGEFAULT)
> + return 16;
> +
> if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
> TRIGGER_RESUME_PARALLEL_WALK | SHADER_CACHING_SRAM | SHADER_CACHING_VRAM))
> return 32;
> @@ -179,6 +187,16 @@ static struct gpgpu_shader *get_shader(int fd, const unsigned int flags)
> gpgpu_shader__common_target_write_u32(shader, s_dim.y + i, CACHING_VALUE(i));
> gpgpu_shader__nop(shader);
> gpgpu_shader__breakpoint(shader);
> + } else if (flags & SHADER_PAGEFAULT) {
> + if (flags & SHADER_PAGEFAULT_READ)
> + gpgpu_shader__read_page_fault(shader, BAD_OFFSET);
The name of the functions seems incorrect, it is bad offset which makes
page_fault.
So at least gpgpu_shader__read_offset, maybe gpgpu_shader__test_read ???
> + else if (flags & SHADER_PAGEFAULT_WRITE)
No need of "if (...)" - it suggests there should be another 'else' which
is not true.
> + gpgpu_shader__write_offset(shader, BAD_OFFSET, BAD_CANARY);
> +
> + gpgpu_shader__label(shader, 0);
> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
> + gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
> }
>
> gpgpu_shader__eot(shader);
> @@ -217,6 +235,17 @@ static int count_set_bits(void *ptr, size_t size)
> return count;
> }
>
> +static int
> +eu_attentions_xor_count(const uint32_t *a, const uint32_t *b, uint32_t size)
> +{
> + int count = 0;
> +
> + for (int i = 0; i < size / 4 ; i++)
> + count += igt_hweight(a[i] ^ b[i]);
> +
> + return count;
> +}
> +
> static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim, uint32_t value)
> {
> int count = 0;
> @@ -636,7 +665,7 @@ static void eu_attention_resume_trigger(struct xe_eudebug_debugger *d,
> }
> }
>
> - if (d->flags & SHADER_LOOP) {
> + if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
> uint32_t threads = get_number_of_threads(d->flags);
> uint32_t val = STEERING_END_LOOP;
>
> @@ -746,6 +775,43 @@ static void eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
> data->single_step_bitmask[i] &= ~att->bitmask[i];
> }
>
> +static void eu_attention_resume_pagefault_trigger(struct xe_eudebug_debugger *d,
> + struct drm_xe_eudebug_event *e)
> +{
> + struct drm_xe_eudebug_event_eu_attention *att = (void *) e;
att = igt_container_of(e, att, base);
> + struct online_debug_data *data = d->ptr;
> + uint32_t bitmask_size = att->bitmask_size;
> + uint8_t *bitmask;
In safe world could be:
uint8_t bitmask[att->bitmask_size];
your approach seems safer, however.
> +
> + if (data->last_eu_control_seqno > att->base.seqno)
> + return;
> +
> + bitmask = calloc(1, att->bitmask_size);
igt_assert(bitmask);
> +
> + eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
> + att->lrc_handle, bitmask, &bitmask_size);
> + igt_assert(bitmask_size == att->bitmask_size);
> +
> + pthread_mutex_lock(&data->mutex);
> +
> + if (d->flags & SHADER_PAGEFAULT) {
> + uint32_t threads = get_number_of_threads(d->flags);
> + uint32_t val = STEERING_END_LOOP;
> +
> + igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
> + data->target_offset + steering_offset(threads)),
> + sizeof(uint32_t));
> + fsync(data->vm_fd);
> + }
> + pthread_mutex_unlock(&data->mutex);
> +
> + data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, att->client_handle,
> + att->exec_queue_handle, att->lrc_handle,
> + bitmask, att->bitmask_size);
> +
> + free(bitmask);
> +}
> +
> static void open_trigger(struct xe_eudebug_debugger *d,
> struct drm_xe_eudebug_event *e)
> {
> @@ -1015,7 +1081,7 @@ static void run_online_client(struct xe_eudebug_client *c)
> struct intel_bb *ibb;
> struct intel_buf *buf;
> uint32_t *ptr;
> - int fd;
> + int fd, vm_flags;
>
> metadata[0] = calloc(2, sizeof(*metadata));
> metadata[1] = calloc(2, sizeof(*metadata));
> @@ -1025,7 +1091,7 @@ static void run_online_client(struct xe_eudebug_client *c)
> fd = xe_eudebug_client_open_driver(c);
>
> /* Additional memory for steering control */
> - if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
> + if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c->flags & SHADER_PAGEFAULT)
> s_dim.y++;
> /* Additional memory for caching check */
> if ((c->flags & SHADER_CACHING_SRAM) || (c->flags & SHADER_CACHING_VRAM))
> @@ -1045,7 +1111,11 @@ static void run_online_client(struct xe_eudebug_client *c)
> DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
> 2 * sizeof(*metadata), metadata[1]);
>
> - create.vm_id = xe_eudebug_client_vm_create(c, fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> + vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
> + vm_flags |= c->flags & SHADER_PAGEFAULT ? DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
> +
> + create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
> +
> xe_eudebug_client_exec_queue_create(c, fd, &create);
>
> ibb = xe_bb_create_on_offset(fd, create.exec_queue_id, create.vm_id, bb_offset, bb_size,
> @@ -1245,11 +1315,14 @@ match_attention_with_exec_queue(struct xe_eudebug_event_log *log,
> static void online_session_check(struct xe_eudebug_session *s, int flags)
> {
> struct drm_xe_eudebug_event_eu_attention *ea = NULL;
> + struct drm_xe_eudebug_event_pagefault *pf = NULL;
> struct drm_xe_eudebug_event *event = NULL;
> struct online_debug_data *data = s->client->ptr;
> bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
> int sum = 0;
> int bitmask_size;
> + int pagefault_threads = 0;
> + uint32_t *ptr = NULL;
ptr can be defined in else clause.
>
> xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
> XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
> @@ -1265,6 +1338,16 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
> igt_assert_eq(ea->bitmask_size, bitmask_size);
> sum += count_set_bits(ea->bitmask, bitmask_size);
> igt_assert(match_attention_with_exec_queue(s->debugger->log, ea));
> + } else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
> + uint32_t after_offset = bitmask_size / sizeof(uint32_t);
> + uint32_t resolved_offset = bitmask_size / sizeof(uint32_t) * 2;
> +
> + pf = (struct drm_xe_eudebug_event_pagefault *)event;
> + ptr = (uint32_t *) pf->bitmask;
> + igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
> + pagefault_threads += eu_attentions_xor_count(ptr + after_offset,
> + ptr + resolved_offset,
> + bitmask_size);
> }
> }
>
> @@ -1279,6 +1362,9 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
> igt_assert(sum > 0);
> else
> igt_assert(sum == 0);
> +
> + if (flags & SHADER_PAGEFAULT)
> + igt_assert(pagefault_threads > 0);
> }
>
> static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
> @@ -1302,6 +1388,55 @@ static void ufence_ack_set_bp_trigger(struct xe_eudebug_debugger *d,
> }
> }
>
> +static void pagefault_trigger(struct xe_eudebug_debugger *d,
> + struct drm_xe_eudebug_event *e)
> +{
> + struct drm_xe_eudebug_event_pagefault *pf = (void *) e;
> + int before_threads, after_threads, resolved_threads, pagefault_threads;
> + uint32_t attn_size = pf->bitmask_size / 3;
> + uint32_t *ptr = (uint32_t *) pf->bitmask;
> + uint32_t offset, before_offset = 0;
> + uint32_t after_offset = attn_size / sizeof(uint32_t);
> + uint32_t resolved_offset = attn_size / sizeof(uint32_t) * 2;
> +
> + before_threads = count_set_bits(ptr + before_offset, attn_size);
> + after_threads = count_set_bits(ptr + after_offset, attn_size);
> + resolved_threads = count_set_bits(ptr + resolved_offset, attn_size);
> +
> + pagefault_threads = eu_attentions_xor_count(ptr + after_offset,
> + ptr + resolved_offset,
> + attn_size);
> +
> + igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
> + "resolved=%d, pagefault=%d] "
> + "client[%llu], exec_queue[%llu], lrc[%llu], bitmask_size[%d], "
> + "pagefault_address[0x%llx]\n",
> + pf->base.seqno, before_threads, after_threads, resolved_threads,
> + pagefault_threads, pf->client_handle, pf->exec_queue_handle,
> + pf->lrc_handle, pf->bitmask_size,
> + pf->pagefault_address);
> +
> + for (int idx = 0; idx < 3; idx++) {
> + if (idx == 0) {
> + igt_debug("=== Attentions before ===\n");
> + offset = before_offset;
> + } else if (idx == 1) {
> + igt_debug("=== Attentions after ===\n");
> + offset = after_offset;
> + } else {
> + igt_debug("=== Attentions resolved ===\n");
> + offset = resolved_offset;
> + }
> +
> + for (uint32_t i = 0; i < attn_size / sizeof(uint32_t); i += 2)
> + igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
> + ptr[offset + i], ptr[offset + i + 1]);
> + }
I have impression we can put most of it into arrays, and drop *_offset,
kind of:
int attn_size_32 = attn_size / sizeof(uint32_t);
uint32_t *ptrs[3] = {ptr, ptr + attn_size_32, ptr + 2 * attn_size_32];
int threads[3];
const char * const name[3] = { "before", "after", "resolved" };
for (int idx = 0; idx < 3; idx++)
threads[i] = count_set_bits(ptr[i], attn_size);
...
for (int idx = 0; idx < 3; idx++) {
igt_debug("=== Attentions %s ===\n", name[idx]);
for (...)
igt_debug(..., ptr[idx][i]...);
}
Regards
Andrzej
> +
> + igt_assert(pagefault_threads > 0);
> + igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
> +}
> +
> /**
> * SUBTEST: basic-breakpoint
> * Description:
> @@ -1383,6 +1518,77 @@ static void test_set_breakpoint_online(int fd, struct drm_xe_engine_class_instan
> online_debug_data_destroy(data);
> }
>
> +/**
> + * SUBTEST: pagefault-read
> + * Description:
> + * Check whether KMD sends pagefault event for workload in debug mode that
> + * triggers a read pagefault.
> + *
> + * SUBTEST: pagefault-write
> + * Description:
> + * Check whether KMD sends pagefault event for workload in debug mode that
> + * triggers a write pagefault.
> + */
> +static void test_pagefault_online(int fd, struct drm_xe_engine_class_instance *hwe,
> + int flags)
> +{
> + struct xe_eudebug_session *s;
> + struct online_debug_data *data;
> + uint32_t val;
> +
> + data = online_debug_data_create(hwe);
> + s = xe_eudebug_session_create(fd, run_online_client, flags, data);
> +
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_OPEN,
> + open_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
> + exec_queue_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> + eu_attention_debug_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> + eu_attention_resume_pagefault_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_METADATA,
> + create_metadata_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
> + ufence_ack_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
> + pagefault_trigger);
> +
> + igt_assert_eq(xe_eudebug_debugger_attach(s->debugger, s->client), 0);
> + xe_eudebug_debugger_start_worker(s->debugger);
> + xe_eudebug_client_start(s->client);
> +
> + /* wait for workload to start */
> + igt_for_milliseconds(STARTUP_TIMEOUT_MS) {
> + /* collect needed data from triggers */
> + if (READ_ONCE(data->vm_fd) == -1 || READ_ONCE(data->target_size) == 0)
> + continue;
> +
> + if (pread(data->vm_fd, &val, sizeof(val), data->target_offset) == sizeof(val))
> + if (val != 0)
> + break;
> + }
> +
> + pthread_mutex_lock(&data->mutex);
> + igt_assert(data->client_handle != -1);
> + igt_assert(data->exec_queue_handle != -1);
> +
> + pthread_mutex_unlock(&data->mutex);
> +
> + xe_eudebug_client_wait_done(s->client);
> +
> + xe_eudebug_debugger_stop_worker(s->debugger, 1);
> +
> + xe_eudebug_event_log_print(s->debugger->log, true);
> + xe_eudebug_event_log_print(s->client->log, true);
> +
> + online_session_check(s, s->flags);
> +
> + xe_eudebug_session_destroy(s);
> + online_debug_data_destroy(data);
> +}
> +
> /**
> * SUBTEST: preempt-breakpoint
> * Description:
> @@ -2344,6 +2550,11 @@ igt_main
> igt_subtest("breakpoint-many-sessions-tiles")
> test_many_sessions_on_tiles(fd, true);
>
> + test_gt_render_or_compute("pagefault-read", fd, hwe)
> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
> + test_gt_render_or_compute("pagefault-write", fd, hwe)
> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
> +
> igt_fixture {
> xe_eudebug_enable(fd, was_enabled);
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 3/4] eudebug: Add eudebug pagefault event declarations
2024-11-18 16:52 ` Hajda, Andrzej
@ 2024-11-19 8:50 ` Manszewski, Christoph
0 siblings, 0 replies; 24+ messages in thread
From: Manszewski, Christoph @ 2024-11-19 8:50 UTC (permalink / raw)
To: Hajda, Andrzej, Gwan-gyeong Mun, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
Hi Andrzej,
On 18.11.2024 17:52, Hajda, Andrzej wrote:
> W dniu 15.11.2024 o 15:11, Gwan-gyeong Mun pisze:
>> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>
>> Update the xe_eudebug drm to include pagefault events.
>>
>> Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>> ---
>> include/drm-uapi-experimental/xe_drm_eudebug.h | 13 +++++++++++++
>
> I am lost between prelim/eudebug/experimental header placements. So just
> out of curiosity what is the role of drm-uapi-experimental comparing to
> prelim or just drm-uapi?
The experimental placement is there to ensure that the eudebug api won't
get removed by a uapi update procedure documented by igt docs. It was
reported by and requested by:
Ville Syrjälä <ville.syrjala@linux.intel.com>
Apart from the placement, this is also a single file (compared to two
files in the public kernel eudebug branch IIRC) which was requested
during upstream review. But the api itself should be identical to the
one found in the public eudebug-dev kernel branch.
Thanks,
Christoph
>
>
>> lib/xe/xe_eudebug.c | 11 +++++++++++
>> 2 files changed, 24 insertions(+)
>>
>> diff --git a/include/drm-uapi-experimental/xe_drm_eudebug.h
>> b/include/drm-uapi-experimental/xe_drm_eudebug.h
>> index f50051e9a..ed2e728c2 100644
>> --- a/include/drm-uapi-experimental/xe_drm_eudebug.h
>> +++ b/include/drm-uapi-experimental/xe_drm_eudebug.h
>> @@ -154,6 +154,7 @@ struct drm_xe_eudebug_event {
>> #define DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE 9
>> #define DRM_XE_EUDEBUG_EVENT_METADATA 10
>> #define DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_METADATA 11
>> +#define DRM_XE_EUDEBUG_EVENT_PAGEFAULT 12
>> __u16 flags;
>> #define DRM_XE_EUDEBUG_EVENT_CREATE (1 << 0)
>> @@ -352,6 +353,18 @@ struct drm_xe_eudebug_event_vm_bind_op_metadata {
>> __u64 metadata_cookie;
>> };
>> +struct drm_xe_eudebug_event_pagefault {
>> + struct drm_xe_eudebug_event base;
>> +
>> + __u64 client_handle;
>> + __u64 exec_queue_handle;
>> + __u64 lrc_handle;
>> + __u32 flags;
>> + __u32 bitmask_size;
>> + __u64 pagefault_address;
>> + __u8 bitmask[];
>> +};
>> +
>> #if defined(__cplusplus)
>> }
>> #endif
>> diff --git a/lib/xe/xe_eudebug.c b/lib/xe/xe_eudebug.c
>> index c5814421b..de01e6b49 100644
>> --- a/lib/xe/xe_eudebug.c
>> +++ b/lib/xe/xe_eudebug.c
>> @@ -91,6 +91,8 @@ static const char *type_to_str(unsigned int type)
>> return "metadata";
>> case DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_METADATA:
>> return "vm_bind_op_metadata";
>> + case DRM_XE_EUDEBUG_EVENT_PAGEFAULT:
>> + return "pagefault";
>> }
>> return "UNKNOWN";
>> @@ -222,6 +224,15 @@ static const char *event_members_to_str(struct
>> drm_xe_eudebug_event *e, char *bu
>> op->vm_bind_op_ref_seqno, op->metadata_handle,
>> op->metadata_cookie);
>> break;
>> }
>> + case DRM_XE_EUDEBUG_EVENT_PAGEFAULT: {
>> + struct drm_xe_eudebug_event_pagefault *pf = (void *)e;
>
> maybe better: pf = container_of(e, pf, base);
>
> Beside this:
>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
>
>
> Regards
> Andrzej
>
>> +
>> + sprintf(buf, "client_handle=%llu, exec_queue_handle=%llu, "
>> + "lrc_handle=%llu, bitmask_size=%d,
>> pagefault_address=0x%llx",
>> + pf->client_handle, pf->exec_queue_handle, pf->lrc_handle,
>> + pf->bitmask_size, pf->pagefault_address);
>> + break;
>> + }
>> default:
>> strcpy(buf, "<...>");
>> }
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 2/4] lib/gpgpu_shader: Add causing a read pagefault from the eu thread
2024-11-15 14:11 ` [PATCH i-g-t 2/4] lib/gpgpu_shader: Add causing a read pagefault from the eu thread Gwan-gyeong Mun
2024-11-18 13:08 ` Hajda, Andrzej
@ 2024-11-19 11:38 ` Manszewski, Christoph
2024-11-21 12:07 ` Gwan-gyeong Mun
1 sibling, 1 reply; 24+ messages in thread
From: Manszewski, Christoph @ 2024-11-19 11:38 UTC (permalink / raw)
To: Gwan-gyeong Mun, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
Hi Gwan-gyeong,
On 15.11.2024 15:11, Gwan-gyeong Mun wrote:
> Create a function that causing a read pagefault using the eu thread load
> instruction. If the given ppgtt address points to an unallocated ppgtt
> virtual address, this shader can cause a read pagefault.
> To directly use a 64-bit address as an argument, use the
> Untyped 2D Block Array Load Instruction.
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> lib/gpgpu_shader.c | 92 +++++++++++++++++++++++++++++++++++++
> lib/gpgpu_shader.h | 1 +
> lib/iga64_generated_codes.c | 21 ++++++++-
> 3 files changed, 113 insertions(+), 1 deletion(-)
>
> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
> index 7a2f0d28d..d7c47be80 100644
> --- a/lib/gpgpu_shader.c
> +++ b/lib/gpgpu_shader.c
> @@ -912,3 +912,95 @@ void gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
> ", 0x807fffff, /* leave breakpoint exception */
> y_offset, value, 0x7fffff /* clear all exceptions */ );
> }
> +
> +/**
> + * gpgpu_shader__read_page_fault:
> + * @shdr: shader to be modified
> + * @ppgtt_addr: ppgtt virtual address to raise pagefault
> + *
> + * For a given arbitrary ppgtt virtual address, it raises a pagefault using
> + * the eu thread load instruction.
> + */
> +void gpgpu_shader__read_page_fault(struct gpgpu_shader *shdr, uint64_t ppgtt_addr)
I admit I haven't read much into the assembly however a question about
the naming and intention of this function comes to mind - why does this
function carry the "read_page_fault" suffix? Isn't this supposed to be a
complementary "read" function to the previously introduced
"gpgpu_shader__write_offset" function?
It seems as if they both should just allow to read/write a specified
ppgtt address and if it isn't bound then a page fault will occur. If
that is the case I would suggest to use some matching naming, like
"__write_ppgtt_offset/__read_ppgtt_offset" or some variation of what
Andrzej suggested.
Thanks,
Christoph
> +{
> + /* pagefault ppgtt virtual address */
> + uint64_t addr = CANONICAL(ppgtt_addr);
> +
> + igt_assert_f((addr & 0x3) == 0, "address must be aligned to DWord!\n");
> +
> + emit_iga64_code(shdr, read_page_fault, " \n\
> +#if GEN_VER >= 2000 \n\
> +// Unyped 2D Block Array Load \n\
> +// Instruction_Load2DBlockArray \n\
> +// bspec: 63972 \n\
> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies both \n\
> +// the block parameters and the 2D Surface parameters. \n\
> +// Untyped2DBLOCKAddressPayload \n\
> +// bspec: 63986 \n\
> +// [243:240] Array Length: 0 (length is 1) \n\
> +// [239:232] Block Height: 0 (height is 1) \n\
> +// [231:224] Block Width: 0xf (width is 16) \n\
> +// [223:192] Block Start Y: 0 \n\
> +// [191:160] Block Start X: 0 \n\
> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 bytes) \n\
> +// [127:96] Untyped 2D Surface Height: 0 (height is 1) \n\
> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 bytes) \n\
> +// [63:0] Untyped 2D Surface Base Address \n\
> +// initialize register \n\
> +(W) mov (8) r30.0<1>:uq 0x0:uq \n\
> +// [0:31] Untyped 2D Surface Base Address low \n\
> +(W) mov (1) r30.0<1>:ud ARG(0):ud \n\
> +// [32:63] Untyped 2D Surface Base Address high \n\
> +(W) mov (1) r30.1<1>:ud ARG(1):ud \n\
> +// [95:64] Untyped 2D Surface Width: 0x3f \n\
> +// (Width minus 1 (in bytes) of the 2D surface, it represents 64) \n\
> +(W) mov (1) r30.2<1>:ud 0x3f:ud \n\
> +// [127:96] Untyped 2D Surface Height: 0x0 \n\
> +// (Height minus 1 (in number of data elements) of \n\
> +// the Untyped 2D surface, it represents 1) \n\
> +(W) mov (1) r30.3<1>:ud 0x0:ud \n\
> +// [159:128] Untyped 2D Surface Pitch: 0x3f \n\
> +// (Pitch minus 1 (in bytes) of the 2D surface, it represents 64) \n\
> +(W) mov (1) r30.4<1>:ud 0x3f:ud \n\
> +// [231:224] Block Width: 0xf (15) \n\
> +// (Specifies the width minus 1 (in number of data elements) for this \n\
> +// rectangular region, it represents 16) \n\
> +// Block width (encoded_value + 1) must be a multiple of DW (4 bytes). \n\
> +// [239:232] Block Height: 0 \n\
> +// (Specifies the height minus 1 (in number of data elements) for \n\
> +// this rectangular region, it represents 1) \n\
> +// [243:240] Array Length: 0 \n\
> +// (Specifies Array Length minus 1 for Load2DBlockArray messages, \n\
> +// must be zero for 2D Block Store messages, it represents 1) \n\
> +(W) mov (1) r30.7<1>:ud 0xf:ud \n\
> +// \n\
> +// dest data payload format is selected by Data Size. \n\
> +// Block Height x Block Width x Data size / GRF Register size \n\
> +// => 1 x 16 x 32bit / 512bit = 1 \n\
> +// data payload format size is 1 GRF Register. \n\
> +// \n\
> +// send.ugm Untyped 2D Block Array Load \n\
> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc \n\
> +// Execution Mask restriction: SIMT1 \n\
> +// \n\
> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D Block) \n\
> +// bspec: 67780 \n\
> +// 0x0 => \n\
> +// [32:22] Global Y_offset: 0 \n\
> +// [21:12] Global X_offset: 0 \n\
> +// \n\
> +// Message Descriptor \n\
> +// bspec: 63972 \n\
> +// 0x2128403 => \n\
> +// [30:29] Address Type: 0 (FLAT) \n\
> +// [28:25] Src0 Length: 1 \n\
> +// [24:20] Dest Length: 1 \n\
> +// [19:16] Cache : 2 (L1UC_L3UC) 10 \n\
> +// [15] Transpose Block: 1 \n\
> +// [11:9] Data Size: 2 (D32) 10 \n\
> +// [7] VNNI Transform: 0 \n\
> +// [5:0] Load Operation: 3 (Load 2D Block) 11 \n\
> +(W) send.ugm (1) r31 r30 null 0x0 0x2128403 \n\
> +#endif \n\
> + ", lower_32_bits(addr), upper_32_bits(addr));
> +}
> \ No newline at end of file
> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
> index 355b128b5..318550c52 100644
> --- a/lib/gpgpu_shader.h
> +++ b/lib/gpgpu_shader.h
> @@ -87,6 +87,7 @@ void gpgpu_shader__write_offset(struct gpgpu_shader *shdr, uint64_t ppgtt_offset
> uint32_t value);
> void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
> uint32_t y_offset, uint32_t mask, uint32_t value);
> +void gpgpu_shader__read_page_fault(struct gpgpu_shader *shdr, uint64_t ppgtt_addr);
> void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
> void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
> void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
> index b23613ac4..53a705358 100644
> --- a/lib/iga64_generated_codes.c
> +++ b/lib/iga64_generated_codes.c
> @@ -3,7 +3,7 @@
>
> #include "gpgpu_shader.h"
>
> -#define MD5_SUM_IGA64_ASMS 4fcde43dedb9d3212f1d85b5b180b0c1
> +#define MD5_SUM_IGA64_ASMS 01290b5ecda7a6e765463558d6f59952
>
> struct iga64_template const iga64_code_gpgpu_fill[] = {
> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> @@ -79,6 +79,25 @@ struct iga64_template const iga64_code_gpgpu_fill[] = {
> }}
> };
>
> +struct iga64_template const iga64_code_read_page_fault[] = {
> + { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> + 0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
> + 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
> + 0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
> + 0x80000061, 0x1e354220, 0x00000000, 0x00000000,
> + 0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
> + 0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
> + 0x80032031, 0x1f0c0000, 0xf8061e0c, 0x00a00000,
> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
> +
> + }}
> +};
> +
> struct iga64_template const iga64_code_end_system_routine_step_if_eq[] = {
> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> 0x80000966, 0x80018220, 0x02008000, 0x00008000,
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 3/4] eudebug: Add eudebug pagefault event declarations
2024-11-15 14:11 ` [PATCH i-g-t 3/4] eudebug: Add eudebug pagefault event declarations Gwan-gyeong Mun
2024-11-18 16:52 ` Hajda, Andrzej
@ 2024-11-19 12:26 ` Manszewski, Christoph
1 sibling, 0 replies; 24+ messages in thread
From: Manszewski, Christoph @ 2024-11-19 12:26 UTC (permalink / raw)
To: Gwan-gyeong Mun, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
Hi Gwan-gyeong,
On 15.11.2024 15:11, Gwan-gyeong Mun wrote:
> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>
> Update the xe_eudebug drm to include pagefault events.
>
> Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Acked-by: Christoph Manszewski <christoph.manszewski@intel.com>
Thanks,
Christoph
> ---
> include/drm-uapi-experimental/xe_drm_eudebug.h | 13 +++++++++++++
> lib/xe/xe_eudebug.c | 11 +++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/include/drm-uapi-experimental/xe_drm_eudebug.h b/include/drm-uapi-experimental/xe_drm_eudebug.h
> index f50051e9a..ed2e728c2 100644
> --- a/include/drm-uapi-experimental/xe_drm_eudebug.h
> +++ b/include/drm-uapi-experimental/xe_drm_eudebug.h
> @@ -154,6 +154,7 @@ struct drm_xe_eudebug_event {
> #define DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE 9
> #define DRM_XE_EUDEBUG_EVENT_METADATA 10
> #define DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_METADATA 11
> +#define DRM_XE_EUDEBUG_EVENT_PAGEFAULT 12
>
> __u16 flags;
> #define DRM_XE_EUDEBUG_EVENT_CREATE (1 << 0)
> @@ -352,6 +353,18 @@ struct drm_xe_eudebug_event_vm_bind_op_metadata {
> __u64 metadata_cookie;
> };
>
> +struct drm_xe_eudebug_event_pagefault {
> + struct drm_xe_eudebug_event base;
> +
> + __u64 client_handle;
> + __u64 exec_queue_handle;
> + __u64 lrc_handle;
> + __u32 flags;
> + __u32 bitmask_size;
> + __u64 pagefault_address;
> + __u8 bitmask[];
> +};
> +
> #if defined(__cplusplus)
> }
> #endif
> diff --git a/lib/xe/xe_eudebug.c b/lib/xe/xe_eudebug.c
> index c5814421b..de01e6b49 100644
> --- a/lib/xe/xe_eudebug.c
> +++ b/lib/xe/xe_eudebug.c
> @@ -91,6 +91,8 @@ static const char *type_to_str(unsigned int type)
> return "metadata";
> case DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_METADATA:
> return "vm_bind_op_metadata";
> + case DRM_XE_EUDEBUG_EVENT_PAGEFAULT:
> + return "pagefault";
> }
>
> return "UNKNOWN";
> @@ -222,6 +224,15 @@ static const char *event_members_to_str(struct drm_xe_eudebug_event *e, char *bu
> op->vm_bind_op_ref_seqno, op->metadata_handle, op->metadata_cookie);
> break;
> }
> + case DRM_XE_EUDEBUG_EVENT_PAGEFAULT: {
> + struct drm_xe_eudebug_event_pagefault *pf = (void *)e;
> +
> + sprintf(buf, "client_handle=%llu, exec_queue_handle=%llu, "
> + "lrc_handle=%llu, bitmask_size=%d, pagefault_address=0x%llx",
> + pf->client_handle, pf->exec_queue_handle, pf->lrc_handle,
> + pf->bitmask_size, pf->pagefault_address);
> + break;
> + }
> default:
> strcpy(buf, "<...>");
> }
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests
2024-11-15 14:11 ` [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests Gwan-gyeong Mun
2024-11-19 8:10 ` Hajda, Andrzej
@ 2024-11-19 15:58 ` Hajda, Andrzej
2024-11-21 12:11 ` Gwan-gyeong Mun
2024-11-19 16:49 ` Manszewski, Christoph
2 siblings, 1 reply; 24+ messages in thread
From: Hajda, Andrzej @ 2024-11-19 15:58 UTC (permalink / raw)
To: Gwan-gyeong Mun, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
W dniu 15.11.2024 o 15:11, Gwan-gyeong Mun pisze:
> Add read and write pagefault tests to xe_eudebug_online that checks if a
> pagefault event is submitted by the KMD debugger when a pagefault occurs.
>
> Test that read (load instruction) and write(store instruction) attempt to
> load or store access to unallocated memory, causing a pagefault.
> Examine the address causing the page fault and the number of eu threads
> causing the pagefault.
>
> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> tests/intel/xe_eudebug_online.c | 219 +++++++++++++++++++++++++++++++-
> 1 file changed, 215 insertions(+), 4 deletions(-)
>
> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/xe_eudebug_online.c
> index 0ef0d8093..eae0eb520 100644
> --- a/tests/intel/xe_eudebug_online.c
> +++ b/tests/intel/xe_eudebug_online.c
> @@ -36,6 +36,8 @@
> #define BB_IN_VRAM (1 << 11)
> #define TARGET_IN_SRAM (1 << 12)
> #define TARGET_IN_VRAM (1 << 13)
> +#define SHADER_PAGEFAULT_READ (1 << 14)
> +#define SHADER_PAGEFAULT_WRITE (1 << 15)
> #define TRIGGER_UFENCE_SET_BREAKPOINT (1 << 24)
> #define TRIGGER_RESUME_SINGLE_WALK (1 << 25)
> #define TRIGGER_RESUME_PARALLEL_WALK (1 << 26)
> @@ -45,6 +47,7 @@
> #define TRIGGER_RESUME_DSS (1 << 30)
> #define TRIGGER_RESUME_ONE (1 << 31)
>
> +#define SHADER_PAGEFAULT (SHADER_PAGEFAULT_READ | SHADER_PAGEFAULT_WRITE)
> #define BB_REGION_BITMASK (BB_IN_SRAM | BB_IN_VRAM)
> #define TARGET_REGION_BITMASK (TARGET_IN_SRAM | TARGET_IN_VRAM)
>
> @@ -61,6 +64,8 @@
> #define CACHING_VALUE(n) (CACHING_INIT_VALUE + (n))
>
> #define SHADER_CANARY 0x01010101
> +#define BAD_CANARY 0xf1f1f1f
> +#define BAD_OFFSET (0x12345678ull << 12)
>
> #define WALKER_X_DIM 4
> #define WALKER_ALIGNMENT 16
> @@ -123,6 +128,9 @@ static int get_number_of_threads(uint64_t flags)
> if (flags & SHADER_MIN_THREADS)
> return 16;
>
> + if (flags & SHADER_PAGEFAULT)
> + return 16;
> +
> if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
> TRIGGER_RESUME_PARALLEL_WALK | SHADER_CACHING_SRAM | SHADER_CACHING_VRAM))
> return 32;
> @@ -179,6 +187,16 @@ static struct gpgpu_shader *get_shader(int fd, const unsigned int flags)
> gpgpu_shader__common_target_write_u32(shader, s_dim.y + i, CACHING_VALUE(i));
> gpgpu_shader__nop(shader);
> gpgpu_shader__breakpoint(shader);
> + } else if (flags & SHADER_PAGEFAULT) {
> + if (flags & SHADER_PAGEFAULT_READ)
> + gpgpu_shader__read_page_fault(shader, BAD_OFFSET);
> + else if (flags & SHADER_PAGEFAULT_WRITE)
> + gpgpu_shader__write_offset(shader, BAD_OFFSET, BAD_CANARY);
> +
> + gpgpu_shader__label(shader, 0);
> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
> + gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
> }
>
> gpgpu_shader__eot(shader);
> @@ -217,6 +235,17 @@ static int count_set_bits(void *ptr, size_t size)
> return count;
> }
>
> +static int
> +eu_attentions_xor_count(const uint32_t *a, const uint32_t *b, uint32_t size)
> +{
> + int count = 0;
> +
> + for (int i = 0; i < size / 4 ; i++)
> + count += igt_hweight(a[i] ^ b[i]);
> +
> + return count;
> +}
> +
> static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim, uint32_t value)
> {
> int count = 0;
> @@ -636,7 +665,7 @@ static void eu_attention_resume_trigger(struct xe_eudebug_debugger *d,
> }
> }
>
> - if (d->flags & SHADER_LOOP) {
> + if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
> uint32_t threads = get_number_of_threads(d->flags);
> uint32_t val = STEERING_END_LOOP;
>
> @@ -746,6 +775,43 @@ static void eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
> data->single_step_bitmask[i] &= ~att->bitmask[i];
> }
>
> +static void eu_attention_resume_pagefault_trigger(struct xe_eudebug_debugger *d,
> + struct drm_xe_eudebug_event *e)
> +{
> + struct drm_xe_eudebug_event_eu_attention *att = (void *) e;
> + struct online_debug_data *data = d->ptr;
> + uint32_t bitmask_size = att->bitmask_size;
> + uint8_t *bitmask;
> +
> + if (data->last_eu_control_seqno > att->base.seqno)
> + return;
> +
> + bitmask = calloc(1, att->bitmask_size);
> +
> + eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
> + att->lrc_handle, bitmask, &bitmask_size);
> + igt_assert(bitmask_size == att->bitmask_size);
> +
> + pthread_mutex_lock(&data->mutex);
> +
> + if (d->flags & SHADER_PAGEFAULT) {
> + uint32_t threads = get_number_of_threads(d->flags);
> + uint32_t val = STEERING_END_LOOP;
> +
> + igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
> + data->target_offset + steering_offset(threads)),
> + sizeof(uint32_t));
> + fsync(data->vm_fd);
> + }
> + pthread_mutex_unlock(&data->mutex);
> +
> + data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, att->client_handle,
> + att->exec_queue_handle, att->lrc_handle,
> + bitmask, att->bitmask_size);
> +
> + free(bitmask);
> +}
> +
> static void open_trigger(struct xe_eudebug_debugger *d,
> struct drm_xe_eudebug_event *e)
> {
> @@ -1015,7 +1081,7 @@ static void run_online_client(struct xe_eudebug_client *c)
> struct intel_bb *ibb;
> struct intel_buf *buf;
> uint32_t *ptr;
> - int fd;
> + int fd, vm_flags;
>
> metadata[0] = calloc(2, sizeof(*metadata));
> metadata[1] = calloc(2, sizeof(*metadata));
> @@ -1025,7 +1091,7 @@ static void run_online_client(struct xe_eudebug_client *c)
> fd = xe_eudebug_client_open_driver(c);
>
> /* Additional memory for steering control */
> - if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
> + if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c->flags & SHADER_PAGEFAULT)
> s_dim.y++;
> /* Additional memory for caching check */
> if ((c->flags & SHADER_CACHING_SRAM) || (c->flags & SHADER_CACHING_VRAM))
> @@ -1045,7 +1111,11 @@ static void run_online_client(struct xe_eudebug_client *c)
> DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
> 2 * sizeof(*metadata), metadata[1]);
>
> - create.vm_id = xe_eudebug_client_vm_create(c, fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> + vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
> + vm_flags |= c->flags & SHADER_PAGEFAULT ? DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
> +
> + create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
> +
> xe_eudebug_client_exec_queue_create(c, fd, &create);
>
> ibb = xe_bb_create_on_offset(fd, create.exec_queue_id, create.vm_id, bb_offset, bb_size,
> @@ -1245,11 +1315,14 @@ match_attention_with_exec_queue(struct xe_eudebug_event_log *log,
> static void online_session_check(struct xe_eudebug_session *s, int flags)
> {
> struct drm_xe_eudebug_event_eu_attention *ea = NULL;
> + struct drm_xe_eudebug_event_pagefault *pf = NULL;
> struct drm_xe_eudebug_event *event = NULL;
> struct online_debug_data *data = s->client->ptr;
> bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
> int sum = 0;
> int bitmask_size;
> + int pagefault_threads = 0;
> + uint32_t *ptr = NULL;
>
> xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
> XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
> @@ -1265,6 +1338,16 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
> igt_assert_eq(ea->bitmask_size, bitmask_size);
> sum += count_set_bits(ea->bitmask, bitmask_size);
> igt_assert(match_attention_with_exec_queue(s->debugger->log, ea));
> + } else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
> + uint32_t after_offset = bitmask_size / sizeof(uint32_t);
> + uint32_t resolved_offset = bitmask_size / sizeof(uint32_t) * 2;
> +
> + pf = (struct drm_xe_eudebug_event_pagefault *)event;
> + ptr = (uint32_t *) pf->bitmask;
> + igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
> + pagefault_threads += eu_attentions_xor_count(ptr + after_offset,
> + ptr + resolved_offset,
> + bitmask_size);
> }
> }
>
> @@ -1279,6 +1362,9 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
> igt_assert(sum > 0);
> else
> igt_assert(sum == 0);
> +
> + if (flags & SHADER_PAGEFAULT)
> + igt_assert(pagefault_threads > 0);
> }
>
> static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
> @@ -1302,6 +1388,55 @@ static void ufence_ack_set_bp_trigger(struct xe_eudebug_debugger *d,
> }
> }
>
> +static void pagefault_trigger(struct xe_eudebug_debugger *d,
> + struct drm_xe_eudebug_event *e)
> +{
> + struct drm_xe_eudebug_event_pagefault *pf = (void *) e;
> + int before_threads, after_threads, resolved_threads, pagefault_threads;
> + uint32_t attn_size = pf->bitmask_size / 3;
> + uint32_t *ptr = (uint32_t *) pf->bitmask;
> + uint32_t offset, before_offset = 0;
> + uint32_t after_offset = attn_size / sizeof(uint32_t);
> + uint32_t resolved_offset = attn_size / sizeof(uint32_t) * 2;
> +
> + before_threads = count_set_bits(ptr + before_offset, attn_size);
> + after_threads = count_set_bits(ptr + after_offset, attn_size);
> + resolved_threads = count_set_bits(ptr + resolved_offset, attn_size);
> +
> + pagefault_threads = eu_attentions_xor_count(ptr + after_offset,
> + ptr + resolved_offset,
> + attn_size);
> +
> + igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
> + "resolved=%d, pagefault=%d] "
> + "client[%llu], exec_queue[%llu], lrc[%llu], bitmask_size[%d], "
> + "pagefault_address[0x%llx]\n",
> + pf->base.seqno, before_threads, after_threads, resolved_threads,
> + pagefault_threads, pf->client_handle, pf->exec_queue_handle,
> + pf->lrc_handle, pf->bitmask_size,
> + pf->pagefault_address);
> +
> + for (int idx = 0; idx < 3; idx++) {
> + if (idx == 0) {
> + igt_debug("=== Attentions before ===\n");
> + offset = before_offset;
> + } else if (idx == 1) {
> + igt_debug("=== Attentions after ===\n");
> + offset = after_offset;
> + } else {
> + igt_debug("=== Attentions resolved ===\n");
> + offset = resolved_offset;
> + }
> +
> + for (uint32_t i = 0; i < attn_size / sizeof(uint32_t); i += 2)
> + igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
> + ptr[offset + i], ptr[offset + i + 1]);
> + }
> +
> + igt_assert(pagefault_threads > 0);
Why not checking if pagefault_threads == num_of_threads ?
I am not sure what is worth checking else, I wonder if we couldn't for
example cause only some of test PF and check if they are reported correctly.
Regarding the flow I see nothing suspicious, AFAIK.
Regards
Andrzej
> + igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
> +}
> +
> /**
> * SUBTEST: basic-breakpoint
> * Description:
> @@ -1383,6 +1518,77 @@ static void test_set_breakpoint_online(int fd, struct drm_xe_engine_class_instan
> online_debug_data_destroy(data);
> }
>
> +/**
> + * SUBTEST: pagefault-read
> + * Description:
> + * Check whether KMD sends pagefault event for workload in debug mode that
> + * triggers a read pagefault.
> + *
> + * SUBTEST: pagefault-write
> + * Description:
> + * Check whether KMD sends pagefault event for workload in debug mode that
> + * triggers a write pagefault.
> + */
> +static void test_pagefault_online(int fd, struct drm_xe_engine_class_instance *hwe,
> + int flags)
> +{
> + struct xe_eudebug_session *s;
> + struct online_debug_data *data;
> + uint32_t val;
> +
> + data = online_debug_data_create(hwe);
> + s = xe_eudebug_session_create(fd, run_online_client, flags, data);
> +
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_OPEN,
> + open_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
> + exec_queue_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> + eu_attention_debug_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> + eu_attention_resume_pagefault_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_METADATA,
> + create_metadata_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
> + ufence_ack_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
> + pagefault_trigger);
> +
> + igt_assert_eq(xe_eudebug_debugger_attach(s->debugger, s->client), 0);
> + xe_eudebug_debugger_start_worker(s->debugger);
> + xe_eudebug_client_start(s->client);
> +
> + /* wait for workload to start */
> + igt_for_milliseconds(STARTUP_TIMEOUT_MS) {
> + /* collect needed data from triggers */
> + if (READ_ONCE(data->vm_fd) == -1 || READ_ONCE(data->target_size) == 0)
> + continue;
> +
> + if (pread(data->vm_fd, &val, sizeof(val), data->target_offset) == sizeof(val))
> + if (val != 0)
> + break;
> + }
> +
> + pthread_mutex_lock(&data->mutex);
> + igt_assert(data->client_handle != -1);
> + igt_assert(data->exec_queue_handle != -1);
> +
> + pthread_mutex_unlock(&data->mutex);
> +
> + xe_eudebug_client_wait_done(s->client);
> +
> + xe_eudebug_debugger_stop_worker(s->debugger, 1);
> +
> + xe_eudebug_event_log_print(s->debugger->log, true);
> + xe_eudebug_event_log_print(s->client->log, true);
> +
> + online_session_check(s, s->flags);
> +
> + xe_eudebug_session_destroy(s);
> + online_debug_data_destroy(data);
> +}
> +
> /**
> * SUBTEST: preempt-breakpoint
> * Description:
> @@ -2344,6 +2550,11 @@ igt_main
> igt_subtest("breakpoint-many-sessions-tiles")
> test_many_sessions_on_tiles(fd, true);
>
> + test_gt_render_or_compute("pagefault-read", fd, hwe)
> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
> + test_gt_render_or_compute("pagefault-write", fd, hwe)
> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
> +
> igt_fixture {
> xe_eudebug_enable(fd, was_enabled);
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests
2024-11-15 14:11 ` [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests Gwan-gyeong Mun
2024-11-19 8:10 ` Hajda, Andrzej
2024-11-19 15:58 ` Hajda, Andrzej
@ 2024-11-19 16:49 ` Manszewski, Christoph
2024-11-21 12:15 ` Gwan-gyeong Mun
2 siblings, 1 reply; 24+ messages in thread
From: Manszewski, Christoph @ 2024-11-19 16:49 UTC (permalink / raw)
To: Gwan-gyeong Mun, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
Hi Gwan-gyeong,
On 15.11.2024 15:11, Gwan-gyeong Mun wrote:
> Add read and write pagefault tests to xe_eudebug_online that checks if a
> pagefault event is submitted by the KMD debugger when a pagefault occurs.
For some reason when running the test with the '--debug' option it seems
like there are events missing in the debugger log. I haven't been able
to spot whether that's a problem on the kmd or igt side, but that seems
only to be the case for the page fault tests.
Yes, the test passing despite this... is not good. That inevitable igt
event processing rewrite is nocking on the door. But the debugger log
itself should report all events the debugger has sent - so that needs
some attention.
>
> Test that read (load instruction) and write(store instruction) attempt to
> load or store access to unallocated memory, causing a pagefault.
> Examine the address causing the page fault and the number of eu threads
> causing the pagefault.
>
> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> tests/intel/xe_eudebug_online.c | 219 +++++++++++++++++++++++++++++++-
> 1 file changed, 215 insertions(+), 4 deletions(-)
>
> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/xe_eudebug_online.c
> index 0ef0d8093..eae0eb520 100644
> --- a/tests/intel/xe_eudebug_online.c
> +++ b/tests/intel/xe_eudebug_online.c
> @@ -36,6 +36,8 @@
> #define BB_IN_VRAM (1 << 11)
> #define TARGET_IN_SRAM (1 << 12)
> #define TARGET_IN_VRAM (1 << 13)
> +#define SHADER_PAGEFAULT_READ (1 << 14)
> +#define SHADER_PAGEFAULT_WRITE (1 << 15)
> #define TRIGGER_UFENCE_SET_BREAKPOINT (1 << 24)
> #define TRIGGER_RESUME_SINGLE_WALK (1 << 25)
> #define TRIGGER_RESUME_PARALLEL_WALK (1 << 26)
> @@ -45,6 +47,7 @@
> #define TRIGGER_RESUME_DSS (1 << 30)
> #define TRIGGER_RESUME_ONE (1 << 31)
>
> +#define SHADER_PAGEFAULT (SHADER_PAGEFAULT_READ | SHADER_PAGEFAULT_WRITE)
> #define BB_REGION_BITMASK (BB_IN_SRAM | BB_IN_VRAM)
> #define TARGET_REGION_BITMASK (TARGET_IN_SRAM | TARGET_IN_VRAM)
>
> @@ -61,6 +64,8 @@
> #define CACHING_VALUE(n) (CACHING_INIT_VALUE + (n))
>
> #define SHADER_CANARY 0x01010101
> +#define BAD_CANARY 0xf1f1f1f
> +#define BAD_OFFSET (0x12345678ull << 12)
>
> #define WALKER_X_DIM 4
> #define WALKER_ALIGNMENT 16
> @@ -123,6 +128,9 @@ static int get_number_of_threads(uint64_t flags)
> if (flags & SHADER_MIN_THREADS)
> return 16;
>
> + if (flags & SHADER_PAGEFAULT)
> + return 16;
Nit: could be merged together with the above.
> +
> if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
> TRIGGER_RESUME_PARALLEL_WALK | SHADER_CACHING_SRAM | SHADER_CACHING_VRAM))
> return 32;
> @@ -179,6 +187,16 @@ static struct gpgpu_shader *get_shader(int fd, const unsigned int flags)
> gpgpu_shader__common_target_write_u32(shader, s_dim.y + i, CACHING_VALUE(i));
> gpgpu_shader__nop(shader);
> gpgpu_shader__breakpoint(shader);
> + } else if (flags & SHADER_PAGEFAULT) {
> + if (flags & SHADER_PAGEFAULT_READ)
> + gpgpu_shader__read_page_fault(shader, BAD_OFFSET);
> + else if (flags & SHADER_PAGEFAULT_WRITE)
> + gpgpu_shader__write_offset(shader, BAD_OFFSET, BAD_CANARY);
> +
> + gpgpu_shader__label(shader, 0);
> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
> + gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
> }
>
> gpgpu_shader__eot(shader);
> @@ -217,6 +235,17 @@ static int count_set_bits(void *ptr, size_t size)
> return count;
> }
>
> +static int
> +eu_attentions_xor_count(const uint32_t *a, const uint32_t *b, uint32_t size)
Nit: the current checkpatch line limit is 100 characters which means
this would fit in a single line.
> +{
> + int count = 0;
> +
> + for (int i = 0; i < size / 4 ; i++)
> + count += igt_hweight(a[i] ^ b[i]);
> +
> + return count;
> +}
> +
> static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim, uint32_t value)
> {
> int count = 0;
> @@ -636,7 +665,7 @@ static void eu_attention_resume_trigger(struct xe_eudebug_debugger *d,
> }
> }
>
> - if (d->flags & SHADER_LOOP) {
> + if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
> uint32_t threads = get_number_of_threads(d->flags);
> uint32_t val = STEERING_END_LOOP;
>
> @@ -746,6 +775,43 @@ static void eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
> data->single_step_bitmask[i] &= ~att->bitmask[i];
> }
>
> +static void eu_attention_resume_pagefault_trigger(struct xe_eudebug_debugger *d,
> + struct drm_xe_eudebug_event *e)
> +{
> + struct drm_xe_eudebug_event_eu_attention *att = (void *) e;
> + struct online_debug_data *data = d->ptr;
> + uint32_t bitmask_size = att->bitmask_size;
> + uint8_t *bitmask;
> +
> + if (data->last_eu_control_seqno > att->base.seqno)
> + return;
> +
> + bitmask = calloc(1, att->bitmask_size);
> +
> + eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
> + att->lrc_handle, bitmask, &bitmask_size);
> + igt_assert(bitmask_size == att->bitmask_size);
> +
> + pthread_mutex_lock(&data->mutex);
> +
> + if (d->flags & SHADER_PAGEFAULT) {
> + uint32_t threads = get_number_of_threads(d->flags);
> + uint32_t val = STEERING_END_LOOP;
> +
> + igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
> + data->target_offset + steering_offset(threads)),
> + sizeof(uint32_t));
> + fsync(data->vm_fd);
> + }
> + pthread_mutex_unlock(&data->mutex);
> +
> + data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, att->client_handle,
> + att->exec_queue_handle, att->lrc_handle,
> + bitmask, att->bitmask_size);
> +
> + free(bitmask);
> +}
> +
> static void open_trigger(struct xe_eudebug_debugger *d,
> struct drm_xe_eudebug_event *e)
> {
> @@ -1015,7 +1081,7 @@ static void run_online_client(struct xe_eudebug_client *c)
> struct intel_bb *ibb;
> struct intel_buf *buf;
> uint32_t *ptr;
> - int fd;
> + int fd, vm_flags;
>
> metadata[0] = calloc(2, sizeof(*metadata));
> metadata[1] = calloc(2, sizeof(*metadata));
> @@ -1025,7 +1091,7 @@ static void run_online_client(struct xe_eudebug_client *c)
> fd = xe_eudebug_client_open_driver(c);
>
> /* Additional memory for steering control */
> - if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
> + if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c->flags & SHADER_PAGEFAULT)
> s_dim.y++;
> /* Additional memory for caching check */
> if ((c->flags & SHADER_CACHING_SRAM) || (c->flags & SHADER_CACHING_VRAM))
> @@ -1045,7 +1111,11 @@ static void run_online_client(struct xe_eudebug_client *c)
> DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
> 2 * sizeof(*metadata), metadata[1]);
>
> - create.vm_id = xe_eudebug_client_vm_create(c, fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> + vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
> + vm_flags |= c->flags & SHADER_PAGEFAULT ? DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
> +
> + create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
> +
> xe_eudebug_client_exec_queue_create(c, fd, &create);
>
> ibb = xe_bb_create_on_offset(fd, create.exec_queue_id, create.vm_id, bb_offset, bb_size,
> @@ -1245,11 +1315,14 @@ match_attention_with_exec_queue(struct xe_eudebug_event_log *log,
> static void online_session_check(struct xe_eudebug_session *s, int flags)
> {
> struct drm_xe_eudebug_event_eu_attention *ea = NULL;
> + struct drm_xe_eudebug_event_pagefault *pf = NULL;
> struct drm_xe_eudebug_event *event = NULL;
> struct online_debug_data *data = s->client->ptr;
> bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
> int sum = 0;
> int bitmask_size;
> + int pagefault_threads = 0;
> + uint32_t *ptr = NULL;
>
> xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
> XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
> @@ -1265,6 +1338,16 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
> igt_assert_eq(ea->bitmask_size, bitmask_size);
> sum += count_set_bits(ea->bitmask, bitmask_size);
> igt_assert(match_attention_with_exec_queue(s->debugger->log, ea));
> + } else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
> + uint32_t after_offset = bitmask_size / sizeof(uint32_t);
> + uint32_t resolved_offset = bitmask_size / sizeof(uint32_t) * 2;
> +
> + pf = (struct drm_xe_eudebug_event_pagefault *)event;
> + ptr = (uint32_t *) pf->bitmask;
> + igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
> + pagefault_threads += eu_attentions_xor_count(ptr + after_offset,
> + ptr + resolved_offset,
> + bitmask_size);
> }
> }
>
> @@ -1279,6 +1362,9 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
> igt_assert(sum > 0);
> else
> igt_assert(sum == 0);
> +
> + if (flags & SHADER_PAGEFAULT)
> + igt_assert(pagefault_threads > 0);
> }
>
> static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
> @@ -1302,6 +1388,55 @@ static void ufence_ack_set_bp_trigger(struct xe_eudebug_debugger *d,
> }
> }
>
> +static void pagefault_trigger(struct xe_eudebug_debugger *d,
> + struct drm_xe_eudebug_event *e)
> +{
> + struct drm_xe_eudebug_event_pagefault *pf = (void *) e;
> + int before_threads, after_threads, resolved_threads, pagefault_threads;
> + uint32_t attn_size = pf->bitmask_size / 3;
> + uint32_t *ptr = (uint32_t *) pf->bitmask;
> + uint32_t offset, before_offset = 0;
> + uint32_t after_offset = attn_size / sizeof(uint32_t);
> + uint32_t resolved_offset = attn_size / sizeof(uint32_t) * 2;
> +
> + before_threads = count_set_bits(ptr + before_offset, attn_size);
> + after_threads = count_set_bits(ptr + after_offset, attn_size);
> + resolved_threads = count_set_bits(ptr + resolved_offset, attn_size);
> +
> + pagefault_threads = eu_attentions_xor_count(ptr + after_offset,
> + ptr + resolved_offset,
> + attn_size);
> +
> + igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
> + "resolved=%d, pagefault=%d] "
> + "client[%llu], exec_queue[%llu], lrc[%llu], bitmask_size[%d], "
> + "pagefault_address[0x%llx]\n",
> + pf->base.seqno, before_threads, after_threads, resolved_threads,
> + pagefault_threads, pf->client_handle, pf->exec_queue_handle,
> + pf->lrc_handle, pf->bitmask_size,
> + pf->pagefault_address);
> +
> + for (int idx = 0; idx < 3; idx++) {
> + if (idx == 0) {
> + igt_debug("=== Attentions before ===\n");
> + offset = before_offset;
> + } else if (idx == 1) {
> + igt_debug("=== Attentions after ===\n");
> + offset = after_offset;
> + } else {
> + igt_debug("=== Attentions resolved ===\n");
> + offset = resolved_offset;
> + }
> +
> + for (uint32_t i = 0; i < attn_size / sizeof(uint32_t); i += 2)
> + igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
> + ptr[offset + i], ptr[offset + i + 1]);
> + }
> +
> + igt_assert(pagefault_threads > 0);
> + igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
> +}
> +
> /**
> * SUBTEST: basic-breakpoint
> * Description:
> @@ -1383,6 +1518,77 @@ static void test_set_breakpoint_online(int fd, struct drm_xe_engine_class_instan
> online_debug_data_destroy(data);
> }
>
> +/**
> + * SUBTEST: pagefault-read
> + * Description:
> + * Check whether KMD sends pagefault event for workload in debug mode that
> + * triggers a read pagefault.
> + *
> + * SUBTEST: pagefault-write
> + * Description:
> + * Check whether KMD sends pagefault event for workload in debug mode that
> + * triggers a write pagefault.
> + */
> +static void test_pagefault_online(int fd, struct drm_xe_engine_class_instance *hwe,
> + int flags)
> +{
> + struct xe_eudebug_session *s;
> + struct online_debug_data *data;
> + uint32_t val;
> +
> + data = online_debug_data_create(hwe);
> + s = xe_eudebug_session_create(fd, run_online_client, flags, data);
> +
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_OPEN,
> + open_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
> + exec_queue_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> + eu_attention_debug_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> + eu_attention_resume_pagefault_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_METADATA,
> + create_metadata_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
> + ufence_ack_trigger);
> + xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
> + pagefault_trigger);
> +
> + igt_assert_eq(xe_eudebug_debugger_attach(s->debugger, s->client), 0);
> + xe_eudebug_debugger_start_worker(s->debugger);
> + xe_eudebug_client_start(s->client);
> +
> + /* wait for workload to start */
> + igt_for_milliseconds(STARTUP_TIMEOUT_MS) {
> + /* collect needed data from triggers */
> + if (READ_ONCE(data->vm_fd) == -1 || READ_ONCE(data->target_size) == 0)
> + continue;
> +
> + if (pread(data->vm_fd, &val, sizeof(val), data->target_offset) == sizeof(val))
> + if (val != 0)
> + break;
> + }
I think this is redundant. It looks like it copies the
'test_interrupt_all' function, but as far I'm concerned the waiting loop
is there to interact with the client thread while the gpu workload is
running. Since we don't do that here I think 'test_pagefault_online'
should rather resemble the 'test_basic_online' function.
Thanks,
Christoph
> +
> + pthread_mutex_lock(&data->mutex);
> + igt_assert(data->client_handle != -1);
> + igt_assert(data->exec_queue_handle != -1);
> +
> + pthread_mutex_unlock(&data->mutex);
> +
> + xe_eudebug_client_wait_done(s->client);
> +
> + xe_eudebug_debugger_stop_worker(s->debugger, 1);
> +
> + xe_eudebug_event_log_print(s->debugger->log, true);
> + xe_eudebug_event_log_print(s->client->log, true);
> +
> + online_session_check(s, s->flags);
> +
> + xe_eudebug_session_destroy(s);
> + online_debug_data_destroy(data);
> +}
> +
> /**
> * SUBTEST: preempt-breakpoint
> * Description:
> @@ -2344,6 +2550,11 @@ igt_main
> igt_subtest("breakpoint-many-sessions-tiles")
> test_many_sessions_on_tiles(fd, true);
>
> + test_gt_render_or_compute("pagefault-read", fd, hwe)
> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
> + test_gt_render_or_compute("pagefault-write", fd, hwe)
> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
> +
> igt_fixture {
> xe_eudebug_enable(fd, was_enabled);
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 1/4] lib/gppgu_shader: Add write to ppgtt offset
2024-11-18 13:00 ` Hajda, Andrzej
@ 2024-11-21 12:01 ` Gwan-gyeong Mun
0 siblings, 0 replies; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-21 12:01 UTC (permalink / raw)
To: Hajda, Andrzej, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
On 11/18/24 3:00 PM, Hajda, Andrzej wrote:
> W dniu 15.11.2024 o 15:11, Gwan-gyeong Mun pisze:
>> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>
>> Create a function that adds the capacity to fill an oword at a given
>> ppgtt offset with a dword value. Xe2 does this with an Untyped 2D Block
>> Array Store operation, though older platforms used to do this with a
>> Media Write Block, so both means are supported.
>>
>> Suggested-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
>> Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>> ---
>> lib/gpgpu_shader.c | 109 ++++++++++++++++++++++++++++++++++++
>> lib/gpgpu_shader.h | 2 +
>> lib/iga64_generated_codes.c | 81 ++++++++++++++++++++++++++-
>> 3 files changed, 191 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
>> index 4e1b8d5e9..7a2f0d28d 100644
>> --- a/lib/gpgpu_shader.c
>> +++ b/lib/gpgpu_shader.c
>> @@ -652,6 +652,115 @@ void gpgpu_shader__write_dword(struct
>> gpgpu_shader *shdr, uint32_t value,
>> ", 2, y_offset, 3, value, value, value, value);
>> }
>> +/**
>> + * gpgpu_shader__write_offset:
>> + * @shdr: shader to be modified
>> + * @ppgtt_offset: write target virtual address
>> + * @value: dword to be written
>> + *
>> + * Fill oword at @ppgtt with dword stored in @value.
>> + *
>> + * Note: for the write to succeed, the address specified by
>> @ppgtt_offset has
>> + * to be bound. Otherwise a page fault will be triggered.
>> + */
>> +void gpgpu_shader__write_offset(struct gpgpu_shader *shdr, uint64_t
>> ppgtt_offset,
>> + uint32_t value)
>
> The name is somehow misleading, maybe gpgpu_shader__fill_a64_4dw?
> Anything better?
>
I will update the function names more clearly and send the patch as
version 2.
candidate name: gpgpu_shader__write_a64_dword() and
gpgpu_shader__read_a64_dword
>> +{
>> + uint64_t offset = CANONICAL(ppgtt_offset);
>> + igt_assert_f((offset & 0xf) == 0, "Offset must be aligned to
>> oword!\n");
>> +
>> + emit_iga64_code(shdr, write_offset, " \n\
>> +#if GEN_VER < 2000 // Media Block Write \n\
>> +(W) mov (8|M0) r30.0<1>:ud 0x0:ud \n\
>> + // canonical address \n\
>> +(W) mov (1|M0) r30.0<1>:ud ARG(0):ud \n\
>> +(W) mov (1|M0) r30.1<1>:ud ARG(1):ud \n\
>> + // written value \n\
>> +(W) mov (1|M0) r31.0<1>:ud ARG(2):ud \n\
>> +(W) mov (1|M0) r31.1<1>:ud ARG(3):ud \n\
>> +(W) mov (1|M0) r31.2<1>:ud ARG(4):ud \n\
>> +(W) mov (1|M0) r31.3<1>:ud ARG(5):ud \n\
>
> It could be replaced by "mov (4) r31.0<1>:ud ARG(2):ud", and then
> removed duplicated arguments ARGS(3-5).
>
I will remove the shader code that is not currently in use and remove
the duplicate code on next version
>> + // owblock write \n\
>> +(W) send.dc1 (16|M0) null r30 r31 0x0 0x20d40ff \n\
>> + // owblock read, to block the thread until the write is
>> materialized \n\
>> +(W) send.dc1 (16|M0) r32 r30 null 0x0 0x21500ff \n\
>> +#else // Unyped 2D Block Store \n\
>> +// Instruction_Store2DBlock \n\
>> +// bspec: 63981 \n\
>> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies
>> both \n\
>> +// the block parameters and the 2D Surface parameters. \n\
>> +// src1 data payload format is selected by Data Size. \n\
>> +// Untyped2DBLOCKAddressPayload \n\
>> +// bspec: 63986 \n\
>> +// [243:240] Array Length: 0 (length is 1) \n\
>> +// [239:232] Block Height: 0 (height is 1) \n\
>> +// [231:224] Block Width: 0xf (width is 16) \n\
>> +// [223:192] Block Start Y: 0 \n\
>> +// [191:160] Block Start X: 0 \n\
>> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64
>> bytes) \n\
>> +// [127:96] Untyped 2D Surface Height: 0 (height is 1)
>> \n\
>> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64
>> bytes) \n\
>> +// [63:0] Untyped 2D Surface Base Address \n\
>> +// initialize register \n\
>> +(W) mov (8) r30.0<1>:uq 0x0:uq \n\
>> +// [0:31] Untyped 2D Surface Base Address low \n\
>> +(W) mov (1) r30.0<1>:ud ARG(0):ud \n\
>> +// [32:63] Untyped 2D Surface Base Address high \n\
>> +(W) mov (1) r30.1<1>:ud ARG(1):ud \n\
>> +// [95:64] Untyped 2D Surface Width: 0x3f \n\
>> +// (Width minus 1 (in bytes) of the 2D surface, it represents
>> 64) \n\
>> +(W) mov (1) r30.2<1>:ud 0x3f:ud \n\
>> +// [127:96] Untyped 2D Surface Height: 0x0 \n\
>> +// (Height minus 1 (in number of data elements) of \n\
>> +// the Untyped 2D surface, it represents 1) \n\
>> +(W) mov (1) r30.3<1>:ud 0x0:ud \n\
>> +// [159:128] Untyped 2D Surface Pitch: 0x3f \n\
>> +// (Pitch minus 1 (in bytes) of the 2D surface, it represents
>> 64) \n\
>> +(W) mov (1) r30.4<1>:ud 0x3f:ud \n\
>> +// [231:224] Block Width: 0xf (15) \n\
>> +// (Specifies the width minus 1 (in number of data elements)
>> for this \n\
>> +// rectangular region, it represents 16) \n\
>> +// Block width (encoded_value + 1) must be a multiple of DW (4
>> bytes). \n\
>> +// [239:232] Block Height: 0 \n\
>> +// (Specifies the height minus 1 (in number of data elements)
>> for \n\
>> +// this rectangular region, it represents 1) \n\
>> +// [243:240] Array Length: 0 \n\
>> +// (Specifies Array Length minus 1 for Load2DBlockArray
>> messages, \n\
>> +// must be zero for 2D Block Store messages, it represents
>> 1) \n\
>> +(W) mov (1) r30.7<1>:ud 0xf:ud \n\
>> +// src1 data payload size \n\
>> +// Block Height x Block Width x Data size / GRF Register
>> size \n\
>> +// => 1 x 16 x 32bit / 512bit = 1 \n\
>> +// data payload size is 1 \n\
>> +(W) mov (8) r31.0<1>:uq 0x0:uq \n\
>> +(W) mov (1|M0) r31.0<1>:ud ARG(2):ud \n\
>> +(W) mov (1|M0) r31.1<1>:ud ARG(3):ud \n\
>> +(W) mov (1|M0) r31.2<1>:ud ARG(4):ud \n\
>> +(W) mov (1|M0) r31.3<1>:ud ARG(5):ud \n\
>> +// send.ugm Untyped 2D Block Array Store \n\
>> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc \n\
>> +// Execution Mask restriction: SIMT1 \n\
>> +// \n\
>> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D
>> Block) \n\
>> +// bspec: 67780 \n\
>> +// 0x0 => \n\
>> +// [32:22] Global Y_offset: 0 \n\
>> +// [21:12] Global X_offset: 0 \n\
>> +// \n\
>> +// Message Descriptor \n\
>> +// bspec: 63981 \n\
>> +// 0x2020407 => \n\
>> +// [30:29] Address Type: 0 (FLAT) \n\
>> +// [28:25] Src0 Length: 1 \n\
>> +// [24:20] Dest Length: 0 \n\
>> +// [19:16] Cache : 2 (L1UC_L3UC) \n\
>> +// [11:9] Data Size: 2 (D32) \n\
>> +// [5:0] Store Operation: 7 \n\
>> +(W) send.ugm (1) null r30 r31:1 0x0
>> 0x2020407 \n\
>> +#endif \n\
>> + ", offset & 0xffffffff, offset >> 32, value, value, value, value);
>
> with above change, and proper macros line above becomes:
> , lower_32_bits(offset), upper_32_bits(offset), value);
>
>> +}
>> +
>> /**
>> * gpgpu_shader__clear_exception:
>> * @shdr: shader to be modified
>> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
>> index c7c21c115..355b128b5 100644
>> --- a/lib/gpgpu_shader.h
>> +++ b/lib/gpgpu_shader.h
>> @@ -83,6 +83,8 @@ void gpgpu_shader__write_aip(struct gpgpu_shader
>> *shdr, uint32_t y_offset);
>> void gpgpu_shader__increase_aip(struct gpgpu_shader *shdr, uint32_t
>> value);
>> void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t
>> value,
>> uint32_t y_offset);
>> +void gpgpu_shader__write_offset(struct gpgpu_shader *shdr, uint64_t
>> ppgtt_offset,
>> + uint32_t value);
>> void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr,
>> uint32_t dw, uint32_t x_offset,
>> uint32_t y_offset, uint32_t mask, uint32_t
>> value);
>> void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
>> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
>> index 6638be07b..b23613ac4 100644
>> --- a/lib/iga64_generated_codes.c
>> +++ b/lib/iga64_generated_codes.c
>> @@ -3,7 +3,7 @@
>> #include "gpgpu_shader.h"
>> -#define MD5_SUM_IGA64_ASMS ec9d477415eebb7d6983395f1bcde78f
>> +#define MD5_SUM_IGA64_ASMS 4fcde43dedb9d3212f1d85b5b180b0c1
>> struct iga64_template const iga64_code_gpgpu_fill[] = {
>> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> @@ -323,6 +323,85 @@ struct iga64_template const
>> iga64_code_clear_exception[] = {
>> }}
>> };
>> +struct iga64_template const iga64_code_write_offset[] = {
>> + { .gen_ver = 2000, .size = 64, .code = (const uint32_t []) {
>> + 0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
>> + 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
>> + 0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
>> + 0x80000061, 0x1e354220, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
>> + 0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
>> + 0x800c0061, 0x1f054330, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
>> + 0x80000061, 0x1f154220, 0x00000000, 0xc0ded003,
>> + 0x80000061, 0x1f254220, 0x00000000, 0xc0ded004,
>> + 0x80000061, 0x1f354220, 0x00000000, 0xc0ded005,
>> + 0x80032031, 0x00000000, 0xf80e1e0c, 0x00801f0c,
>> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
>> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
>> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
>> + }},
>> + { .gen_ver = 1270, .size = 52, .code = (const uint32_t []) {
>> + 0x80030061, 0x1e054220, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
>> + 0x80000061, 0x1e254220, 0x00000000, 0xc0ded001,
>> + 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
>> + 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
>> + 0x80000061, 0x1f454220, 0x00000000, 0xc0ded004,
>> + 0x80000061, 0x1f654220, 0x00000000, 0xc0ded005,
>> + 0x80001d01, 0x00010000, 0x00000000, 0x00000000,
>> + 0x80044031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
>> + 0x80044131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
>> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
>> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
>> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
>> + }},
>> + { .gen_ver = 1260, .size = 48, .code = (const uint32_t []) {
>> + 0x800c0061, 0x1e054220, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
>> + 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
>> + 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
>> + 0x80000061, 0x1f154220, 0x00000000, 0xc0ded003,
>> + 0x80000061, 0x1f254220, 0x00000000, 0xc0ded004,
>> + 0x80000061, 0x1f354220, 0x00000000, 0xc0ded005,
>> + 0x8013a031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
>> + 0x8010c131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
>> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
>> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
>> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
>> + }},
>> + { .gen_ver = 1250, .size = 52, .code = (const uint32_t []) {
>> + 0x80030061, 0x1e054220, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
>> + 0x80000061, 0x1e254220, 0x00000000, 0xc0ded001,
>> + 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
>> + 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
>> + 0x80000061, 0x1f454220, 0x00000000, 0xc0ded004,
>> + 0x80000061, 0x1f654220, 0x00000000, 0xc0ded005,
>> + 0x80001d01, 0x00010000, 0x00000000, 0x00000000,
>> + 0x80044031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
>> + 0x80044131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
>> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
>> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
>> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
>> + }},
>> + { .gen_ver = 0, .size = 48, .code = (const uint32_t []) {
>> + 0x80030061, 0x1e054220, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
>> + 0x80000061, 0x1e254220, 0x00000000, 0xc0ded001,
>> + 0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
>> + 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
>> + 0x80000061, 0x1f454220, 0x00000000, 0xc0ded004,
>> + 0x80000061, 0x1f654220, 0x00000000, 0xc0ded005,
>> + 0x8004d031, 0x00000000, 0xc1fe1e0c, 0x03501f04,
>> + 0x80044131, 0x200c0000, 0xc1fe1e0c, 0x01400000,
>> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
>> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
>> + 0x80000101, 0x00010000, 0x00000000, 0x00000000,
>> + }}
>> +};
>> +
>> struct iga64_template const iga64_code_media_block_write[] = {
>> { .gen_ver = 2000, .size = 56, .code = (const uint32_t []) {
>> 0x80100061, 0x04054220, 0x00000000, 0x00000000,
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 2/4] lib/gpgpu_shader: Add causing a read pagefault from the eu thread
2024-11-18 13:08 ` Hajda, Andrzej
@ 2024-11-21 12:02 ` Gwan-gyeong Mun
0 siblings, 0 replies; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-21 12:02 UTC (permalink / raw)
To: Hajda, Andrzej, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
On 11/18/24 3:08 PM, Hajda, Andrzej wrote:
> W dniu 15.11.2024 o 15:11, Gwan-gyeong Mun pisze:
>> Create a function that causing a read pagefault using the eu thread load
>> instruction. If the given ppgtt address points to an unallocated ppgtt
>> virtual address, this shader can cause a read pagefault.
>> To directly use a 64-bit address as an argument, use the
>> Untyped 2D Block Array Load Instruction.
>>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> ---
>> lib/gpgpu_shader.c | 92 +++++++++++++++++++++++++++++++++++++
>> lib/gpgpu_shader.h | 1 +
>> lib/iga64_generated_codes.c | 21 ++++++++-
>> 3 files changed, 113 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
>> index 7a2f0d28d..d7c47be80 100644
>> --- a/lib/gpgpu_shader.c
>> +++ b/lib/gpgpu_shader.c
>> @@ -912,3 +912,95 @@ void
>> gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
>> ", 0x807fffff, /* leave breakpoint exception */
>> y_offset, value, 0x7fffff /* clear all exceptions */ );
>> }
>> +
>> +/**
>> + * gpgpu_shader__read_page_fault:
>> + * @shdr: shader to be modified
>> + * @ppgtt_addr: ppgtt virtual address to raise pagefault
>> + *
>> + * For a given arbitrary ppgtt virtual address, it raises a pagefault
>> using
>> + * the eu thread load instruction.
>> + */
>> +void gpgpu_shader__read_page_fault(struct gpgpu_shader *shdr,
>> uint64_t ppgtt_addr)
>> +{
>> + /* pagefault ppgtt virtual address */
>> + uint64_t addr = CANONICAL(ppgtt_addr);
>> +
>> + igt_assert_f((addr & 0x3) == 0, "address must be aligned to
>> DWord!\n");
>> +
>> + emit_iga64_code(shdr, read_page_fault, " \n\
>> +#if GEN_VER >= 2000 \n\
>> +// Unyped 2D Block Array Load \n\
>> +// Instruction_Load2DBlockArray \n\
>> +// bspec: 63972 \n\
>> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies
>> both \n\
>> +// the block parameters and the 2D Surface parameters. \n\
>> +// Untyped2DBLOCKAddressPayload \n\
>> +// bspec: 63986 \n\
>> +// [243:240] Array Length: 0 (length is 1) \n\
>> +// [239:232] Block Height: 0 (height is 1) \n\
>> +// [231:224] Block Width: 0xf (width is 16) \n\
>> +// [223:192] Block Start Y: 0 \n\
>> +// [191:160] Block Start X: 0 \n\
>> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64
>> bytes) \n\
>> +// [127:96] Untyped 2D Surface Height: 0 (height is 1)
>> \n\
>> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64
>> bytes) \n\
>> +// [63:0] Untyped 2D Surface Base Address \n\
>> +// initialize register \n\
>> +(W) mov (8) r30.0<1>:uq 0x0:uq \n\
>> +// [0:31] Untyped 2D Surface Base Address low \n\
>> +(W) mov (1) r30.0<1>:ud ARG(0):ud \n\
>> +// [32:63] Untyped 2D Surface Base Address high \n\
>> +(W) mov (1) r30.1<1>:ud ARG(1):ud \n\
>> +// [95:64] Untyped 2D Surface Width: 0x3f \n\
>> +// (Width minus 1 (in bytes) of the 2D surface, it represents
>> 64) \n\
>> +(W) mov (1) r30.2<1>:ud 0x3f:ud \n\
>> +// [127:96] Untyped 2D Surface Height: 0x0 \n\
>> +// (Height minus 1 (in number of data elements) of \n\
>> +// the Untyped 2D surface, it represents 1) \n\
>> +(W) mov (1) r30.3<1>:ud 0x0:ud \n\
>> +// [159:128] Untyped 2D Surface Pitch: 0x3f \n\
>> +// (Pitch minus 1 (in bytes) of the 2D surface, it represents
>> 64) \n\
>> +(W) mov (1) r30.4<1>:ud 0x3f:ud \n\
>> +// [231:224] Block Width: 0xf (15) \n\
>> +// (Specifies the width minus 1 (in number of data elements)
>> for this \n\
>> +// rectangular region, it represents 16) \n\
>> +// Block width (encoded_value + 1) must be a multiple of DW (4
>> bytes). \n\
>> +// [239:232] Block Height: 0 \n\
>> +// (Specifies the height minus 1 (in number of data elements)
>> for \n\
>> +// this rectangular region, it represents 1) \n\
>> +// [243:240] Array Length: 0 \n\
>> +// (Specifies Array Length minus 1 for Load2DBlockArray
>> messages, \n\
>> +// must be zero for 2D Block Store messages, it represents
>> 1) \n\
>> +(W) mov (1) r30.7<1>:ud 0xf:ud \n\
>
> It duplicates code from gpgpu_shader__write_offset, could be replaced
> with macros as in https://patchwork.freedesktop.org/series/141348/ , but
> no rush :)
>
Introducing macros will be done in another refactoring patch.
Thanks.
>> +// \n\
>> +// dest data payload format is selected by Data Size. \n\
>> +// Block Height x Block Width x Data size / GRF Register
>> size \n\
>> +// => 1 x 16 x 32bit / 512bit = 1 \n\
>> +// data payload format size is 1 GRF Register. \n\
>> +// \n\
>> +// send.ugm Untyped 2D Block Array Load \n\
>> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc \n\
>> +// Execution Mask restriction: SIMT1 \n\
>> +// \n\
>> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D
>> Block) \n\
>> +// bspec: 67780 \n\
>> +// 0x0 => \n\
>> +// [32:22] Global Y_offset: 0 \n\
>> +// [21:12] Global X_offset: 0 \n\
>> +// \n\
>> +// Message Descriptor \n\
>> +// bspec: 63972 \n\
>> +// 0x2128403 => \n\
>> +// [30:29] Address Type: 0 (FLAT) \n\
>> +// [28:25] Src0 Length: 1 \n\
>> +// [24:20] Dest Length: 1 \n\
>> +// [19:16] Cache : 2 (L1UC_L3UC) 10 \n\
>> +// [15] Transpose Block: 1 \n\
>> +// [11:9] Data Size: 2 (D32) 10 \n\
>> +// [7] VNNI Transform: 0 \n\
>> +// [5:0] Load Operation: 3 (Load 2D Block) 11 \n\
>> +(W) send.ugm (1) r31 r30 null 0x0 0x2128403 \n\
>> +#endif \n\
>> + ", lower_32_bits(addr), upper_32_bits(addr));
>> +}
>> \ No newline at end of file
>
> New line
>
>> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
>> index 355b128b5..318550c52 100644
>> --- a/lib/gpgpu_shader.h
>> +++ b/lib/gpgpu_shader.h
>> @@ -87,6 +87,7 @@ void gpgpu_shader__write_offset(struct gpgpu_shader
>> *shdr, uint64_t ppgtt_offset
>> uint32_t value);
>> void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr,
>> uint32_t dw, uint32_t x_offset,
>> uint32_t y_offset, uint32_t mask, uint32_t
>> value);
>> +void gpgpu_shader__read_page_fault(struct gpgpu_shader *shdr,
>> uint64_t ppgtt_addr);
>> void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
>> void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
>> void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
>> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
>> index b23613ac4..53a705358 100644
>> --- a/lib/iga64_generated_codes.c
>> +++ b/lib/iga64_generated_codes.c
>> @@ -3,7 +3,7 @@
>> #include "gpgpu_shader.h"
>> -#define MD5_SUM_IGA64_ASMS 4fcde43dedb9d3212f1d85b5b180b0c1
>> +#define MD5_SUM_IGA64_ASMS 01290b5ecda7a6e765463558d6f59952
>> struct iga64_template const iga64_code_gpgpu_fill[] = {
>> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> @@ -79,6 +79,25 @@ struct iga64_template const iga64_code_gpgpu_fill[]
>> = {
>> }}
>> };
>> +struct iga64_template const iga64_code_read_page_fault[] = {
>> + { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> + 0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
>> + 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
>> + 0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
>> + 0x80000061, 0x1e354220, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
>> + 0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
>> + 0x80032031, 0x1f0c0000, 0xf8061e0c, 0x00a00000,
>> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
>> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
>> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
>> + }},
>> + { .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
>> +
>> + }}
>> +};
>> +
>> struct iga64_template const
>> iga64_code_end_system_routine_step_if_eq[] = {
>> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> 0x80000966, 0x80018220, 0x02008000, 0x00008000,
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests
2024-11-19 8:10 ` Hajda, Andrzej
@ 2024-11-21 12:06 ` Gwan-gyeong Mun
0 siblings, 0 replies; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-21 12:06 UTC (permalink / raw)
To: Hajda, Andrzej, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
On 11/19/24 10:10 AM, Hajda, Andrzej wrote:
>
> W dniu 15.11.2024 o 15:11, Gwan-gyeong Mun pisze:
>> Add read and write pagefault tests to xe_eudebug_online that checks if a
>> pagefault event is submitted by the KMD debugger when a pagefault occurs.
>>
>> Test that read (load instruction) and write(store instruction) attempt to
>> load or store access to unallocated memory, causing a pagefault.
>> Examine the address causing the page fault and the number of eu threads
>> causing the pagefault.
>>
>> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> ---
>> tests/intel/xe_eudebug_online.c | 219 +++++++++++++++++++++++++++++++-
>> 1 file changed, 215 insertions(+), 4 deletions(-)
>>
>> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/
>> xe_eudebug_online.c
>> index 0ef0d8093..eae0eb520 100644
>> --- a/tests/intel/xe_eudebug_online.c
>> +++ b/tests/intel/xe_eudebug_online.c
>> @@ -36,6 +36,8 @@
>> #define BB_IN_VRAM (1 << 11)
>> #define TARGET_IN_SRAM (1 << 12)
>> #define TARGET_IN_VRAM (1 << 13)
>> +#define SHADER_PAGEFAULT_READ (1 << 14)
>> +#define SHADER_PAGEFAULT_WRITE (1 << 15)
>> #define TRIGGER_UFENCE_SET_BREAKPOINT (1 << 24)
>> #define TRIGGER_RESUME_SINGLE_WALK (1 << 25)
>> #define TRIGGER_RESUME_PARALLEL_WALK (1 << 26)
>> @@ -45,6 +47,7 @@
>> #define TRIGGER_RESUME_DSS (1 << 30)
>> #define TRIGGER_RESUME_ONE (1 << 31)
>> +#define SHADER_PAGEFAULT (SHADER_PAGEFAULT_READ |
>> SHADER_PAGEFAULT_WRITE)
>> #define BB_REGION_BITMASK (BB_IN_SRAM | BB_IN_VRAM)
>> #define TARGET_REGION_BITMASK (TARGET_IN_SRAM | TARGET_IN_VRAM)
>> @@ -61,6 +64,8 @@
>> #define CACHING_VALUE(n) (CACHING_INIT_VALUE + (n))
>> #define SHADER_CANARY 0x01010101
>> +#define BAD_CANARY 0xf1f1f1f
>> +#define BAD_OFFSET (0x12345678ull << 12)
>> #define WALKER_X_DIM 4
>> #define WALKER_ALIGNMENT 16
>> @@ -123,6 +128,9 @@ static int get_number_of_threads(uint64_t flags)
>> if (flags & SHADER_MIN_THREADS)
>> return 16;
>> + if (flags & SHADER_PAGEFAULT)
>> + return 16;
>> +
>> if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
>> TRIGGER_RESUME_PARALLEL_WALK | SHADER_CACHING_SRAM |
>> SHADER_CACHING_VRAM))
>> return 32;
>> @@ -179,6 +187,16 @@ static struct gpgpu_shader *get_shader(int fd,
>> const unsigned int flags)
>> gpgpu_shader__common_target_write_u32(shader, s_dim.y +
>> i, CACHING_VALUE(i));
>> gpgpu_shader__nop(shader);
>> gpgpu_shader__breakpoint(shader);
>> + } else if (flags & SHADER_PAGEFAULT) {
>> + if (flags & SHADER_PAGEFAULT_READ)
>> + gpgpu_shader__read_page_fault(shader, BAD_OFFSET);
>
>
> The name of the functions seems incorrect, it is bad offset which makes
> page_fault.
>
> So at least gpgpu_shader__read_offset, maybe gpgpu_shader__test_read ???
>
I will update the shader naming as gpgpu_shader__write_a64_dword() and
gpgpu_shader__read_a64_dword()
>
>> + else if (flags & SHADER_PAGEFAULT_WRITE)
>
> No need of "if (...)" - it suggests there should be another 'else' which
> is not true.
>
next version will fix it.
>
>> + gpgpu_shader__write_offset(shader, BAD_OFFSET, BAD_CANARY);
>> +
>> + gpgpu_shader__label(shader, 0);
>> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>> + gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
>> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>> }
>> gpgpu_shader__eot(shader);
>> @@ -217,6 +235,17 @@ static int count_set_bits(void *ptr, size_t size)
>> return count;
>> }
>> +static int
>> +eu_attentions_xor_count(const uint32_t *a, const uint32_t *b,
>> uint32_t size)
>> +{
>> + int count = 0;
>> +
>> + for (int i = 0; i < size / 4 ; i++)
>> + count += igt_hweight(a[i] ^ b[i]);
>> +
>> + return count;
>> +}
>> +
>> static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim,
>> uint32_t value)
>> {
>> int count = 0;
>> @@ -636,7 +665,7 @@ static void eu_attention_resume_trigger(struct
>> xe_eudebug_debugger *d,
>> }
>> }
>> - if (d->flags & SHADER_LOOP) {
>> + if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
>> uint32_t threads = get_number_of_threads(d->flags);
>> uint32_t val = STEERING_END_LOOP;
>> @@ -746,6 +775,43 @@ static void
>> eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
>> data->single_step_bitmask[i] &= ~att->bitmask[i];
>> }
>> +static void eu_attention_resume_pagefault_trigger(struct
>> xe_eudebug_debugger *d,
>> + struct drm_xe_eudebug_event *e)
>> +{
>> + struct drm_xe_eudebug_event_eu_attention *att = (void *) e;
>
>
> att = igt_container_of(e, att, base);
>
>> + struct online_debug_data *data = d->ptr;
>> + uint32_t bitmask_size = att->bitmask_size;
>> + uint8_t *bitmask;
>
> In safe world could be:
>
> uint8_t bitmask[att->bitmask_size];
> your approach seems safer, however.
>
>> +
>> + if (data->last_eu_control_seqno > att->base.seqno)
>> + return;
>> +
>> + bitmask = calloc(1, att->bitmask_size);
> igt_assert(bitmask);
>> +
>> + eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
>> + att->lrc_handle, bitmask, &bitmask_size);
>> + igt_assert(bitmask_size == att->bitmask_size);
>> +
>> + pthread_mutex_lock(&data->mutex);
>> +
>> + if (d->flags & SHADER_PAGEFAULT) {
>> + uint32_t threads = get_number_of_threads(d->flags);
>> + uint32_t val = STEERING_END_LOOP;
>> +
>> + igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
>> + data->target_offset + steering_offset(threads)),
>> + sizeof(uint32_t));
>> + fsync(data->vm_fd);
>> + }
>> + pthread_mutex_unlock(&data->mutex);
>> +
>> + data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd,
>> att->client_handle,
>> + att->exec_queue_handle, att->lrc_handle,
>> + bitmask, att->bitmask_size);
>> +
>> + free(bitmask);
>> +}
>> +
>> static void open_trigger(struct xe_eudebug_debugger *d,
>> struct drm_xe_eudebug_event *e)
>> {
>> @@ -1015,7 +1081,7 @@ static void run_online_client(struct
>> xe_eudebug_client *c)
>> struct intel_bb *ibb;
>> struct intel_buf *buf;
>> uint32_t *ptr;
>> - int fd;
>> + int fd, vm_flags;
>> metadata[0] = calloc(2, sizeof(*metadata));
>> metadata[1] = calloc(2, sizeof(*metadata));
>> @@ -1025,7 +1091,7 @@ static void run_online_client(struct
>> xe_eudebug_client *c)
>> fd = xe_eudebug_client_open_driver(c);
>> /* Additional memory for steering control */
>> - if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
>> + if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c-
>> >flags & SHADER_PAGEFAULT)
>> s_dim.y++;
>> /* Additional memory for caching check */
>> if ((c->flags & SHADER_CACHING_SRAM) || (c->flags &
>> SHADER_CACHING_VRAM))
>> @@ -1045,7 +1111,11 @@ static void run_online_client(struct
>> xe_eudebug_client *c)
>> DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
>> 2 * sizeof(*metadata), metadata[1]);
>> - create.vm_id = xe_eudebug_client_vm_create(c, fd,
>> DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
>> + vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
>> + vm_flags |= c->flags & SHADER_PAGEFAULT ?
>> DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
>> +
>> + create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
>> +
>> xe_eudebug_client_exec_queue_create(c, fd, &create);
>> ibb = xe_bb_create_on_offset(fd, create.exec_queue_id,
>> create.vm_id, bb_offset, bb_size,
>> @@ -1245,11 +1315,14 @@ match_attention_with_exec_queue(struct
>> xe_eudebug_event_log *log,
>> static void online_session_check(struct xe_eudebug_session *s, int
>> flags)
>> {
>> struct drm_xe_eudebug_event_eu_attention *ea = NULL;
>> + struct drm_xe_eudebug_event_pagefault *pf = NULL;
>> struct drm_xe_eudebug_event *event = NULL;
>> struct online_debug_data *data = s->client->ptr;
>> bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
>> int sum = 0;
>> int bitmask_size;
>> + int pagefault_threads = 0;
>> + uint32_t *ptr = NULL;
> ptr can be defined in else clause.
>> xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
>> XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
>> @@ -1265,6 +1338,16 @@ static void online_session_check(struct
>> xe_eudebug_session *s, int flags)
>> igt_assert_eq(ea->bitmask_size, bitmask_size);
>> sum += count_set_bits(ea->bitmask, bitmask_size);
>> igt_assert(match_attention_with_exec_queue(s->debugger-
>> >log, ea));
>> + } else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
>> + uint32_t after_offset = bitmask_size / sizeof(uint32_t);
>> + uint32_t resolved_offset = bitmask_size /
>> sizeof(uint32_t) * 2;
>> +
>> + pf = (struct drm_xe_eudebug_event_pagefault *)event;
>> + ptr = (uint32_t *) pf->bitmask;
>> + igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
>> + pagefault_threads += eu_attentions_xor_count(ptr +
>> after_offset,
>> + ptr + resolved_offset,
>> + bitmask_size);
>> }
>> }
>> @@ -1279,6 +1362,9 @@ static void online_session_check(struct
>> xe_eudebug_session *s, int flags)
>> igt_assert(sum > 0);
>> else
>> igt_assert(sum == 0);
>> +
>> + if (flags & SHADER_PAGEFAULT)
>> + igt_assert(pagefault_threads > 0);
>> }
>> static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
>> @@ -1302,6 +1388,55 @@ static void ufence_ack_set_bp_trigger(struct
>> xe_eudebug_debugger *d,
>> }
>> }
>> +static void pagefault_trigger(struct xe_eudebug_debugger *d,
>> + struct drm_xe_eudebug_event *e)
>> +{
>> + struct drm_xe_eudebug_event_pagefault *pf = (void *) e;
>> + int before_threads, after_threads, resolved_threads,
>> pagefault_threads;
>> + uint32_t attn_size = pf->bitmask_size / 3;
>> + uint32_t *ptr = (uint32_t *) pf->bitmask;
>> + uint32_t offset, before_offset = 0;
>> + uint32_t after_offset = attn_size / sizeof(uint32_t);
>> + uint32_t resolved_offset = attn_size / sizeof(uint32_t) * 2;
>> +
>> + before_threads = count_set_bits(ptr + before_offset, attn_size);
>> + after_threads = count_set_bits(ptr + after_offset, attn_size);
>> + resolved_threads = count_set_bits(ptr + resolved_offset, attn_size);
>> +
>> + pagefault_threads = eu_attentions_xor_count(ptr + after_offset,
>> + ptr + resolved_offset,
>> + attn_size);
>> +
>> + igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
>> + "resolved=%d, pagefault=%d] "
>> + "client[%llu], exec_queue[%llu], lrc[%llu],
>> bitmask_size[%d], "
>> + "pagefault_address[0x%llx]\n",
>> + pf->base.seqno, before_threads, after_threads,
>> resolved_threads,
>> + pagefault_threads, pf->client_handle, pf->exec_queue_handle,
>> + pf->lrc_handle, pf->bitmask_size,
>> + pf->pagefault_address);
>> +
>> + for (int idx = 0; idx < 3; idx++) {
>> + if (idx == 0) {
>> + igt_debug("=== Attentions before ===\n");
>> + offset = before_offset;
>> + } else if (idx == 1) {
>> + igt_debug("=== Attentions after ===\n");
>> + offset = after_offset;
>> + } else {
>> + igt_debug("=== Attentions resolved ===\n");
>> + offset = resolved_offset;
>> + }
>> +
>> + for (uint32_t i = 0; i < attn_size / sizeof(uint32_t); i += 2)
>> + igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
>> + ptr[offset + i], ptr[offset + i + 1]);
>> + }
>
> I have impression we can put most of it into arrays, and drop *_offset,
> kind of:
>
> int attn_size_32 = attn_size / sizeof(uint32_t);
>
> uint32_t *ptrs[3] = {ptr, ptr + attn_size_32, ptr + 2 * attn_size_32];
> int threads[3];
> const char * const name[3] = { "before", "after", "resolved" };
>
> for (int idx = 0; idx < 3; idx++)
> threads[i] = count_set_bits(ptr[i], attn_size);
>
> ...
> for (int idx = 0; idx < 3; idx++) {
> igt_debug("=== Attentions %s ===\n", name[idx]);
> for (...)
> igt_debug(..., ptr[idx][i]...);
> }
>
thanks for guiding readable / clean code style.
I'll follow on next version.
G.G.
>
> Regards
> Andrzej
>
>> +
>> + igt_assert(pagefault_threads > 0);
>> + igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
>> +}
>> +
>> /**
>> * SUBTEST: basic-breakpoint
>> * Description:
>> @@ -1383,6 +1518,77 @@ static void test_set_breakpoint_online(int fd,
>> struct drm_xe_engine_class_instan
>> online_debug_data_destroy(data);
>> }
>> +/**
>> + * SUBTEST: pagefault-read
>> + * Description:
>> + * Check whether KMD sends pagefault event for workload in debug
>> mode that
>> + * triggers a read pagefault.
>> + *
>> + * SUBTEST: pagefault-write
>> + * Description:
>> + * Check whether KMD sends pagefault event for workload in debug
>> mode that
>> + * triggers a write pagefault.
>> + */
>> +static void test_pagefault_online(int fd, struct
>> drm_xe_engine_class_instance *hwe,
>> + int flags)
>> +{
>> + struct xe_eudebug_session *s;
>> + struct online_debug_data *data;
>> + uint32_t val;
>> +
>> + data = online_debug_data_create(hwe);
>> + s = xe_eudebug_session_create(fd, run_online_client, flags, data);
>> +
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_OPEN,
>> + open_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
>> + exec_queue_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>> + eu_attention_debug_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>> + eu_attention_resume_pagefault_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_METADATA,
>> + create_metadata_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
>> + ufence_ack_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
>> + pagefault_trigger);
>> +
>> + igt_assert_eq(xe_eudebug_debugger_attach(s->debugger, s->client),
>> 0);
>> + xe_eudebug_debugger_start_worker(s->debugger);
>> + xe_eudebug_client_start(s->client);
>> +
>> + /* wait for workload to start */
>> + igt_for_milliseconds(STARTUP_TIMEOUT_MS) {
>> + /* collect needed data from triggers */
>> + if (READ_ONCE(data->vm_fd) == -1 || READ_ONCE(data-
>> >target_size) == 0)
>> + continue;
>> +
>> + if (pread(data->vm_fd, &val, sizeof(val), data-
>> >target_offset) == sizeof(val))
>> + if (val != 0)
>> + break;
>> + }
>> +
>> + pthread_mutex_lock(&data->mutex);
>> + igt_assert(data->client_handle != -1);
>> + igt_assert(data->exec_queue_handle != -1);
>> +
>> + pthread_mutex_unlock(&data->mutex);
>> +
>> + xe_eudebug_client_wait_done(s->client);
>> +
>> + xe_eudebug_debugger_stop_worker(s->debugger, 1);
>> +
>> + xe_eudebug_event_log_print(s->debugger->log, true);
>> + xe_eudebug_event_log_print(s->client->log, true);
>> +
>> + online_session_check(s, s->flags);
>> +
>> + xe_eudebug_session_destroy(s);
>> + online_debug_data_destroy(data);
>> +}
>> +
>> /**
>> * SUBTEST: preempt-breakpoint
>> * Description:
>> @@ -2344,6 +2550,11 @@ igt_main
>> igt_subtest("breakpoint-many-sessions-tiles")
>> test_many_sessions_on_tiles(fd, true);
>> + test_gt_render_or_compute("pagefault-read", fd, hwe)
>> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
>> + test_gt_render_or_compute("pagefault-write", fd, hwe)
>> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
>> +
>> igt_fixture {
>> xe_eudebug_enable(fd, was_enabled);
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 2/4] lib/gpgpu_shader: Add causing a read pagefault from the eu thread
2024-11-19 11:38 ` Manszewski, Christoph
@ 2024-11-21 12:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-21 12:07 UTC (permalink / raw)
To: Manszewski, Christoph, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
On 11/19/24 1:38 PM, Manszewski, Christoph wrote:
> Hi Gwan-gyeong,
>
> On 15.11.2024 15:11, Gwan-gyeong Mun wrote:
>> Create a function that causing a read pagefault using the eu thread load
>> instruction. If the given ppgtt address points to an unallocated ppgtt
>> virtual address, this shader can cause a read pagefault.
>> To directly use a 64-bit address as an argument, use the
>> Untyped 2D Block Array Load Instruction.
>>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> ---
>> lib/gpgpu_shader.c | 92 +++++++++++++++++++++++++++++++++++++
>> lib/gpgpu_shader.h | 1 +
>> lib/iga64_generated_codes.c | 21 ++++++++-
>> 3 files changed, 113 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
>> index 7a2f0d28d..d7c47be80 100644
>> --- a/lib/gpgpu_shader.c
>> +++ b/lib/gpgpu_shader.c
>> @@ -912,3 +912,95 @@ void
>> gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
>> ", 0x807fffff, /* leave breakpoint exception */
>> y_offset, value, 0x7fffff /* clear all exceptions */ );
>> }
>> +
>> +/**
>> + * gpgpu_shader__read_page_fault:
>> + * @shdr: shader to be modified
>> + * @ppgtt_addr: ppgtt virtual address to raise pagefault
>> + *
>> + * For a given arbitrary ppgtt virtual address, it raises a pagefault
>> using
>> + * the eu thread load instruction.
>> + */
>> +void gpgpu_shader__read_page_fault(struct gpgpu_shader *shdr,
>> uint64_t ppgtt_addr)
>
> I admit I haven't read much into the assembly however a question about
> the naming and intention of this function comes to mind - why does this
> function carry the "read_page_fault" suffix? Isn't this supposed to be a
> complementary "read" function to the previously introduced
> "gpgpu_shader__write_offset" function?
As I mentioned in another email reply, I'm going to change the naming of
these functions.
>
> It seems as if they both should just allow to read/write a specified
> ppgtt address and if it isn't bound then a page fault will occur. If
> that is the case I would suggest to use some matching naming, like
> "__write_ppgtt_offset/__read_ppgtt_offset" or some variation of what
> Andrzej suggested.
>
> Thanks,
> Christoph
>
>> +{
>> + /* pagefault ppgtt virtual address */
>> + uint64_t addr = CANONICAL(ppgtt_addr);
>> +
>> + igt_assert_f((addr & 0x3) == 0, "address must be aligned to
>> DWord!\n");
>> +
>> + emit_iga64_code(shdr, read_page_fault, " \n\
>> +#if GEN_VER >= 2000 \n\
>> +// Unyped 2D Block Array Load \n\
>> +// Instruction_Load2DBlockArray \n\
>> +// bspec: 63972 \n\
>> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies
>> both \n\
>> +// the block parameters and the 2D Surface parameters. \n\
>> +// Untyped2DBLOCKAddressPayload \n\
>> +// bspec: 63986 \n\
>> +// [243:240] Array Length: 0 (length is 1) \n\
>> +// [239:232] Block Height: 0 (height is 1) \n\
>> +// [231:224] Block Width: 0xf (width is 16) \n\
>> +// [223:192] Block Start Y: 0 \n\
>> +// [191:160] Block Start X: 0 \n\
>> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64
>> bytes) \n\
>> +// [127:96] Untyped 2D Surface Height: 0 (height is 1)
>> \n\
>> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64
>> bytes) \n\
>> +// [63:0] Untyped 2D Surface Base Address \n\
>> +// initialize register \n\
>> +(W) mov (8) r30.0<1>:uq 0x0:uq \n\
>> +// [0:31] Untyped 2D Surface Base Address low \n\
>> +(W) mov (1) r30.0<1>:ud ARG(0):ud \n\
>> +// [32:63] Untyped 2D Surface Base Address high \n\
>> +(W) mov (1) r30.1<1>:ud ARG(1):ud \n\
>> +// [95:64] Untyped 2D Surface Width: 0x3f \n\
>> +// (Width minus 1 (in bytes) of the 2D surface, it represents
>> 64) \n\
>> +(W) mov (1) r30.2<1>:ud 0x3f:ud \n\
>> +// [127:96] Untyped 2D Surface Height: 0x0 \n\
>> +// (Height minus 1 (in number of data elements) of \n\
>> +// the Untyped 2D surface, it represents 1) \n\
>> +(W) mov (1) r30.3<1>:ud 0x0:ud \n\
>> +// [159:128] Untyped 2D Surface Pitch: 0x3f \n\
>> +// (Pitch minus 1 (in bytes) of the 2D surface, it represents
>> 64) \n\
>> +(W) mov (1) r30.4<1>:ud 0x3f:ud \n\
>> +// [231:224] Block Width: 0xf (15) \n\
>> +// (Specifies the width minus 1 (in number of data elements)
>> for this \n\
>> +// rectangular region, it represents 16) \n\
>> +// Block width (encoded_value + 1) must be a multiple of DW (4
>> bytes). \n\
>> +// [239:232] Block Height: 0 \n\
>> +// (Specifies the height minus 1 (in number of data elements)
>> for \n\
>> +// this rectangular region, it represents 1) \n\
>> +// [243:240] Array Length: 0 \n\
>> +// (Specifies Array Length minus 1 for Load2DBlockArray
>> messages, \n\
>> +// must be zero for 2D Block Store messages, it represents
>> 1) \n\
>> +(W) mov (1) r30.7<1>:ud 0xf:ud \n\
>> +// \n\
>> +// dest data payload format is selected by Data Size. \n\
>> +// Block Height x Block Width x Data size / GRF Register
>> size \n\
>> +// => 1 x 16 x 32bit / 512bit = 1 \n\
>> +// data payload format size is 1 GRF Register. \n\
>> +// \n\
>> +// send.ugm Untyped 2D Block Array Load \n\
>> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc \n\
>> +// Execution Mask restriction: SIMT1 \n\
>> +// \n\
>> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D
>> Block) \n\
>> +// bspec: 67780 \n\
>> +// 0x0 => \n\
>> +// [32:22] Global Y_offset: 0 \n\
>> +// [21:12] Global X_offset: 0 \n\
>> +// \n\
>> +// Message Descriptor \n\
>> +// bspec: 63972 \n\
>> +// 0x2128403 => \n\
>> +// [30:29] Address Type: 0 (FLAT) \n\
>> +// [28:25] Src0 Length: 1 \n\
>> +// [24:20] Dest Length: 1 \n\
>> +// [19:16] Cache : 2 (L1UC_L3UC) 10 \n\
>> +// [15] Transpose Block: 1 \n\
>> +// [11:9] Data Size: 2 (D32) 10 \n\
>> +// [7] VNNI Transform: 0 \n\
>> +// [5:0] Load Operation: 3 (Load 2D Block) 11 \n\
>> +(W) send.ugm (1) r31 r30 null 0x0 0x2128403 \n\
>> +#endif \n\
>> + ", lower_32_bits(addr), upper_32_bits(addr));
>> +}
>> \ No newline at end of file
>> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
>> index 355b128b5..318550c52 100644
>> --- a/lib/gpgpu_shader.h
>> +++ b/lib/gpgpu_shader.h
>> @@ -87,6 +87,7 @@ void gpgpu_shader__write_offset(struct gpgpu_shader
>> *shdr, uint64_t ppgtt_offset
>> uint32_t value);
>> void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr,
>> uint32_t dw, uint32_t x_offset,
>> uint32_t y_offset, uint32_t mask, uint32_t
>> value);
>> +void gpgpu_shader__read_page_fault(struct gpgpu_shader *shdr,
>> uint64_t ppgtt_addr);
>> void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
>> void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
>> void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
>> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
>> index b23613ac4..53a705358 100644
>> --- a/lib/iga64_generated_codes.c
>> +++ b/lib/iga64_generated_codes.c
>> @@ -3,7 +3,7 @@
>> #include "gpgpu_shader.h"
>> -#define MD5_SUM_IGA64_ASMS 4fcde43dedb9d3212f1d85b5b180b0c1
>> +#define MD5_SUM_IGA64_ASMS 01290b5ecda7a6e765463558d6f59952
>> struct iga64_template const iga64_code_gpgpu_fill[] = {
>> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> @@ -79,6 +79,25 @@ struct iga64_template const iga64_code_gpgpu_fill[]
>> = {
>> }}
>> };
>> +struct iga64_template const iga64_code_read_page_fault[] = {
>> + { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> + 0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
>> + 0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
>> + 0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
>> + 0x80000061, 0x1e354220, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
>> + 0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
>> + 0x80032031, 0x1f0c0000, 0xf8061e0c, 0x00a00000,
>> + 0x80000001, 0x00010000, 0x20000000, 0x00000000,
>> + 0x80000001, 0x00010000, 0x30000000, 0x00000000,
>> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
>> + }},
>> + { .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
>> +
>> + }}
>> +};
>> +
>> struct iga64_template const
>> iga64_code_end_system_routine_step_if_eq[] = {
>> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> 0x80000966, 0x80018220, 0x02008000, 0x00008000,
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests
2024-11-19 15:58 ` Hajda, Andrzej
@ 2024-11-21 12:11 ` Gwan-gyeong Mun
0 siblings, 0 replies; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-21 12:11 UTC (permalink / raw)
To: Hajda, Andrzej, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
On 11/19/24 5:58 PM, Hajda, Andrzej wrote:
>
> W dniu 15.11.2024 o 15:11, Gwan-gyeong Mun pisze:
>> Add read and write pagefault tests to xe_eudebug_online that checks if a
>> pagefault event is submitted by the KMD debugger when a pagefault occurs.
>>
>> Test that read (load instruction) and write(store instruction) attempt to
>> load or store access to unallocated memory, causing a pagefault.
>> Examine the address causing the page fault and the number of eu threads
>> causing the pagefault.
>>
>> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> ---
>> tests/intel/xe_eudebug_online.c | 219 +++++++++++++++++++++++++++++++-
>> 1 file changed, 215 insertions(+), 4 deletions(-)
>>
>> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/
>> xe_eudebug_online.c
>> index 0ef0d8093..eae0eb520 100644
>> --- a/tests/intel/xe_eudebug_online.c
>> +++ b/tests/intel/xe_eudebug_online.c
>> @@ -36,6 +36,8 @@
>> #define BB_IN_VRAM (1 << 11)
>> #define TARGET_IN_SRAM (1 << 12)
>> #define TARGET_IN_VRAM (1 << 13)
>> +#define SHADER_PAGEFAULT_READ (1 << 14)
>> +#define SHADER_PAGEFAULT_WRITE (1 << 15)
>> #define TRIGGER_UFENCE_SET_BREAKPOINT (1 << 24)
>> #define TRIGGER_RESUME_SINGLE_WALK (1 << 25)
>> #define TRIGGER_RESUME_PARALLEL_WALK (1 << 26)
>> @@ -45,6 +47,7 @@
>> #define TRIGGER_RESUME_DSS (1 << 30)
>> #define TRIGGER_RESUME_ONE (1 << 31)
>> +#define SHADER_PAGEFAULT (SHADER_PAGEFAULT_READ |
>> SHADER_PAGEFAULT_WRITE)
>> #define BB_REGION_BITMASK (BB_IN_SRAM | BB_IN_VRAM)
>> #define TARGET_REGION_BITMASK (TARGET_IN_SRAM | TARGET_IN_VRAM)
>> @@ -61,6 +64,8 @@
>> #define CACHING_VALUE(n) (CACHING_INIT_VALUE + (n))
>> #define SHADER_CANARY 0x01010101
>> +#define BAD_CANARY 0xf1f1f1f
>> +#define BAD_OFFSET (0x12345678ull << 12)
>> #define WALKER_X_DIM 4
>> #define WALKER_ALIGNMENT 16
>> @@ -123,6 +128,9 @@ static int get_number_of_threads(uint64_t flags)
>> if (flags & SHADER_MIN_THREADS)
>> return 16;
>> + if (flags & SHADER_PAGEFAULT)
>> + return 16;
>> +
>> if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
>> TRIGGER_RESUME_PARALLEL_WALK | SHADER_CACHING_SRAM |
>> SHADER_CACHING_VRAM))
>> return 32;
>> @@ -179,6 +187,16 @@ static struct gpgpu_shader *get_shader(int fd,
>> const unsigned int flags)
>> gpgpu_shader__common_target_write_u32(shader, s_dim.y +
>> i, CACHING_VALUE(i));
>> gpgpu_shader__nop(shader);
>> gpgpu_shader__breakpoint(shader);
>> + } else if (flags & SHADER_PAGEFAULT) {
>> + if (flags & SHADER_PAGEFAULT_READ)
>> + gpgpu_shader__read_page_fault(shader, BAD_OFFSET);
>> + else if (flags & SHADER_PAGEFAULT_WRITE)
>> + gpgpu_shader__write_offset(shader, BAD_OFFSET, BAD_CANARY);
>> +
>> + gpgpu_shader__label(shader, 0);
>> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>> + gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
>> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>> }
>> gpgpu_shader__eot(shader);
>> @@ -217,6 +235,17 @@ static int count_set_bits(void *ptr, size_t size)
>> return count;
>> }
>> +static int
>> +eu_attentions_xor_count(const uint32_t *a, const uint32_t *b,
>> uint32_t size)
>> +{
>> + int count = 0;
>> +
>> + for (int i = 0; i < size / 4 ; i++)
>> + count += igt_hweight(a[i] ^ b[i]);
>> +
>> + return count;
>> +}
>> +
>> static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim,
>> uint32_t value)
>> {
>> int count = 0;
>> @@ -636,7 +665,7 @@ static void eu_attention_resume_trigger(struct
>> xe_eudebug_debugger *d,
>> }
>> }
>> - if (d->flags & SHADER_LOOP) {
>> + if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
>> uint32_t threads = get_number_of_threads(d->flags);
>> uint32_t val = STEERING_END_LOOP;
>> @@ -746,6 +775,43 @@ static void
>> eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
>> data->single_step_bitmask[i] &= ~att->bitmask[i];
>> }
>> +static void eu_attention_resume_pagefault_trigger(struct
>> xe_eudebug_debugger *d,
>> + struct drm_xe_eudebug_event *e)
>> +{
>> + struct drm_xe_eudebug_event_eu_attention *att = (void *) e;
>> + struct online_debug_data *data = d->ptr;
>> + uint32_t bitmask_size = att->bitmask_size;
>> + uint8_t *bitmask;
>> +
>> + if (data->last_eu_control_seqno > att->base.seqno)
>> + return;
>> +
>> + bitmask = calloc(1, att->bitmask_size);
>> +
>> + eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
>> + att->lrc_handle, bitmask, &bitmask_size);
>> + igt_assert(bitmask_size == att->bitmask_size);
>> +
>> + pthread_mutex_lock(&data->mutex);
>> +
>> + if (d->flags & SHADER_PAGEFAULT) {
>> + uint32_t threads = get_number_of_threads(d->flags);
>> + uint32_t val = STEERING_END_LOOP;
>> +
>> + igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
>> + data->target_offset + steering_offset(threads)),
>> + sizeof(uint32_t));
>> + fsync(data->vm_fd);
>> + }
>> + pthread_mutex_unlock(&data->mutex);
>> +
>> + data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd,
>> att->client_handle,
>> + att->exec_queue_handle, att->lrc_handle,
>> + bitmask, att->bitmask_size);
>> +
>> + free(bitmask);
>> +}
>> +
>> static void open_trigger(struct xe_eudebug_debugger *d,
>> struct drm_xe_eudebug_event *e)
>> {
>> @@ -1015,7 +1081,7 @@ static void run_online_client(struct
>> xe_eudebug_client *c)
>> struct intel_bb *ibb;
>> struct intel_buf *buf;
>> uint32_t *ptr;
>> - int fd;
>> + int fd, vm_flags;
>> metadata[0] = calloc(2, sizeof(*metadata));
>> metadata[1] = calloc(2, sizeof(*metadata));
>> @@ -1025,7 +1091,7 @@ static void run_online_client(struct
>> xe_eudebug_client *c)
>> fd = xe_eudebug_client_open_driver(c);
>> /* Additional memory for steering control */
>> - if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
>> + if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c-
>> >flags & SHADER_PAGEFAULT)
>> s_dim.y++;
>> /* Additional memory for caching check */
>> if ((c->flags & SHADER_CACHING_SRAM) || (c->flags &
>> SHADER_CACHING_VRAM))
>> @@ -1045,7 +1111,11 @@ static void run_online_client(struct
>> xe_eudebug_client *c)
>> DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
>> 2 * sizeof(*metadata), metadata[1]);
>> - create.vm_id = xe_eudebug_client_vm_create(c, fd,
>> DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
>> + vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
>> + vm_flags |= c->flags & SHADER_PAGEFAULT ?
>> DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
>> +
>> + create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
>> +
>> xe_eudebug_client_exec_queue_create(c, fd, &create);
>> ibb = xe_bb_create_on_offset(fd, create.exec_queue_id,
>> create.vm_id, bb_offset, bb_size,
>> @@ -1245,11 +1315,14 @@ match_attention_with_exec_queue(struct
>> xe_eudebug_event_log *log,
>> static void online_session_check(struct xe_eudebug_session *s, int
>> flags)
>> {
>> struct drm_xe_eudebug_event_eu_attention *ea = NULL;
>> + struct drm_xe_eudebug_event_pagefault *pf = NULL;
>> struct drm_xe_eudebug_event *event = NULL;
>> struct online_debug_data *data = s->client->ptr;
>> bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
>> int sum = 0;
>> int bitmask_size;
>> + int pagefault_threads = 0;
>> + uint32_t *ptr = NULL;
>> xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
>> XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
>> @@ -1265,6 +1338,16 @@ static void online_session_check(struct
>> xe_eudebug_session *s, int flags)
>> igt_assert_eq(ea->bitmask_size, bitmask_size);
>> sum += count_set_bits(ea->bitmask, bitmask_size);
>> igt_assert(match_attention_with_exec_queue(s->debugger-
>> >log, ea));
>> + } else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
>> + uint32_t after_offset = bitmask_size / sizeof(uint32_t);
>> + uint32_t resolved_offset = bitmask_size /
>> sizeof(uint32_t) * 2;
>> +
>> + pf = (struct drm_xe_eudebug_event_pagefault *)event;
>> + ptr = (uint32_t *) pf->bitmask;
>> + igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
>> + pagefault_threads += eu_attentions_xor_count(ptr +
>> after_offset,
>> + ptr + resolved_offset,
>> + bitmask_size);
>> }
>> }
>> @@ -1279,6 +1362,9 @@ static void online_session_check(struct
>> xe_eudebug_session *s, int flags)
>> igt_assert(sum > 0);
>> else
>> igt_assert(sum == 0);
>> +
>> + if (flags & SHADER_PAGEFAULT)
>> + igt_assert(pagefault_threads > 0);
>> }
>> static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
>> @@ -1302,6 +1388,55 @@ static void ufence_ack_set_bp_trigger(struct
>> xe_eudebug_debugger *d,
>> }
>> }
>> +static void pagefault_trigger(struct xe_eudebug_debugger *d,
>> + struct drm_xe_eudebug_event *e)
>> +{
>> + struct drm_xe_eudebug_event_pagefault *pf = (void *) e;
>> + int before_threads, after_threads, resolved_threads,
>> pagefault_threads;
>> + uint32_t attn_size = pf->bitmask_size / 3;
>> + uint32_t *ptr = (uint32_t *) pf->bitmask;
>> + uint32_t offset, before_offset = 0;
>> + uint32_t after_offset = attn_size / sizeof(uint32_t);
>> + uint32_t resolved_offset = attn_size / sizeof(uint32_t) * 2;
>> +
>> + before_threads = count_set_bits(ptr + before_offset, attn_size);
>> + after_threads = count_set_bits(ptr + after_offset, attn_size);
>> + resolved_threads = count_set_bits(ptr + resolved_offset, attn_size);
>> +
>> + pagefault_threads = eu_attentions_xor_count(ptr + after_offset,
>> + ptr + resolved_offset,
>> + attn_size);
>> +
>> + igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
>> + "resolved=%d, pagefault=%d] "
>> + "client[%llu], exec_queue[%llu], lrc[%llu],
>> bitmask_size[%d], "
>> + "pagefault_address[0x%llx]\n",
>> + pf->base.seqno, before_threads, after_threads,
>> resolved_threads,
>> + pagefault_threads, pf->client_handle, pf->exec_queue_handle,
>> + pf->lrc_handle, pf->bitmask_size,
>> + pf->pagefault_address);
>> +
>> + for (int idx = 0; idx < 3; idx++) {
>> + if (idx == 0) {
>> + igt_debug("=== Attentions before ===\n");
>> + offset = before_offset;
>> + } else if (idx == 1) {
>> + igt_debug("=== Attentions after ===\n");
>> + offset = after_offset;
>> + } else {
>> + igt_debug("=== Attentions resolved ===\n");
>> + offset = resolved_offset;
>> + }
>> +
>> + for (uint32_t i = 0; i < attn_size / sizeof(uint32_t); i += 2)
>> + igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
>> + ptr[offset + i], ptr[offset + i + 1]);
>> + }
>> +
>> + igt_assert(pagefault_threads > 0);
>
>
> Why not checking if pagefault_threads == num_of_threads ?
>
> I am not sure what is worth checking else, I wonder if we couldn't for
> example cause only some of test PF and check if they are reported
> correctly.
>
> Regarding the flow I see nothing suspicious, AFAIK.
>
In terms of identifying the eu thread that caused the pagefault, the igt
test case only verifies that there is at least one eu thread that caused
a pagefault, as there is only a guarantee that KMD will report the first
eu thread that caused a pagefault. Of course, if multiple eu threads
caused the pagefault while KMD was handling the pagefault, all of them
may be reported. The point here is that at least one eu thread is reported.
>
> Regards
>
> Andrzej
>
>
>> + igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
>> +}
>> +
>> /**
>> * SUBTEST: basic-breakpoint
>> * Description:
>> @@ -1383,6 +1518,77 @@ static void test_set_breakpoint_online(int fd,
>> struct drm_xe_engine_class_instan
>> online_debug_data_destroy(data);
>> }
>> +/**
>> + * SUBTEST: pagefault-read
>> + * Description:
>> + * Check whether KMD sends pagefault event for workload in debug
>> mode that
>> + * triggers a read pagefault.
>> + *
>> + * SUBTEST: pagefault-write
>> + * Description:
>> + * Check whether KMD sends pagefault event for workload in debug
>> mode that
>> + * triggers a write pagefault.
>> + */
>> +static void test_pagefault_online(int fd, struct
>> drm_xe_engine_class_instance *hwe,
>> + int flags)
>> +{
>> + struct xe_eudebug_session *s;
>> + struct online_debug_data *data;
>> + uint32_t val;
>> +
>> + data = online_debug_data_create(hwe);
>> + s = xe_eudebug_session_create(fd, run_online_client, flags, data);
>> +
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_OPEN,
>> + open_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
>> + exec_queue_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>> + eu_attention_debug_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>> + eu_attention_resume_pagefault_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_METADATA,
>> + create_metadata_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
>> + ufence_ack_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
>> + pagefault_trigger);
>> +
>> + igt_assert_eq(xe_eudebug_debugger_attach(s->debugger, s->client),
>> 0);
>> + xe_eudebug_debugger_start_worker(s->debugger);
>> + xe_eudebug_client_start(s->client);
>> +
>> + /* wait for workload to start */
>> + igt_for_milliseconds(STARTUP_TIMEOUT_MS) {
>> + /* collect needed data from triggers */
>> + if (READ_ONCE(data->vm_fd) == -1 || READ_ONCE(data-
>> >target_size) == 0)
>> + continue;
>> +
>> + if (pread(data->vm_fd, &val, sizeof(val), data-
>> >target_offset) == sizeof(val))
>> + if (val != 0)
>> + break;
>> + }
>> +
>> + pthread_mutex_lock(&data->mutex);
>> + igt_assert(data->client_handle != -1);
>> + igt_assert(data->exec_queue_handle != -1);
>> +
>> + pthread_mutex_unlock(&data->mutex);
>> +
>> + xe_eudebug_client_wait_done(s->client);
>> +
>> + xe_eudebug_debugger_stop_worker(s->debugger, 1);
>> +
>> + xe_eudebug_event_log_print(s->debugger->log, true);
>> + xe_eudebug_event_log_print(s->client->log, true);
>> +
>> + online_session_check(s, s->flags);
>> +
>> + xe_eudebug_session_destroy(s);
>> + online_debug_data_destroy(data);
>> +}
>> +
>> /**
>> * SUBTEST: preempt-breakpoint
>> * Description:
>> @@ -2344,6 +2550,11 @@ igt_main
>> igt_subtest("breakpoint-many-sessions-tiles")
>> test_many_sessions_on_tiles(fd, true);
>> + test_gt_render_or_compute("pagefault-read", fd, hwe)
>> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
>> + test_gt_render_or_compute("pagefault-write", fd, hwe)
>> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
>> +
>> igt_fixture {
>> xe_eudebug_enable(fd, was_enabled);
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests
2024-11-19 16:49 ` Manszewski, Christoph
@ 2024-11-21 12:15 ` Gwan-gyeong Mun
0 siblings, 0 replies; 24+ messages in thread
From: Gwan-gyeong Mun @ 2024-11-21 12:15 UTC (permalink / raw)
To: Manszewski, Christoph, igt-dev
Cc: jonathan.cavitt, mika.kuoppala, dominik.grzegorzek
On 11/19/24 6:49 PM, Manszewski, Christoph wrote:
> Hi Gwan-gyeong,
>
> On 15.11.2024 15:11, Gwan-gyeong Mun wrote:
>> Add read and write pagefault tests to xe_eudebug_online that checks if a
>> pagefault event is submitted by the KMD debugger when a pagefault occurs.
>
> For some reason when running the test with the '--debug' option it seems
> like there are events missing in the debugger log. I haven't been able
> to spot whether that's a problem on the kmd or igt side, but that seems
> only to be the case for the page fault tests.
>
> Yes, the test passing despite this... is not good. That inevitable igt
> event processing rewrite is nocking on the door. But the debugger log
> itself should report all events the debugger has sent - so that needs
> some attention.
>
When creating a vm with xe_eudebug_client_vm_create( ... ,
DRM_XE_VM_CREATE_FLAG_FAULT_MODE );, it is observed that some eudebug
events related to vm bind are not fully reported to the debugger, this
is an issue that should be checked in the KMD and is not an issue caused
by the pagefault kmd / igt test implementation. This issue requires a
separate KMD fix.
>>
>> Test that read (load instruction) and write(store instruction) attempt to
>> load or store access to unallocated memory, causing a pagefault.
>> Examine the address causing the page fault and the number of eu threads
>> causing the pagefault.
>>
>> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> ---
>> tests/intel/xe_eudebug_online.c | 219 +++++++++++++++++++++++++++++++-
>> 1 file changed, 215 insertions(+), 4 deletions(-)
>>
>> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/
>> xe_eudebug_online.c
>> index 0ef0d8093..eae0eb520 100644
>> --- a/tests/intel/xe_eudebug_online.c
>> +++ b/tests/intel/xe_eudebug_online.c
>> @@ -36,6 +36,8 @@
>> #define BB_IN_VRAM (1 << 11)
>> #define TARGET_IN_SRAM (1 << 12)
>> #define TARGET_IN_VRAM (1 << 13)
>> +#define SHADER_PAGEFAULT_READ (1 << 14)
>> +#define SHADER_PAGEFAULT_WRITE (1 << 15)
>> #define TRIGGER_UFENCE_SET_BREAKPOINT (1 << 24)
>> #define TRIGGER_RESUME_SINGLE_WALK (1 << 25)
>> #define TRIGGER_RESUME_PARALLEL_WALK (1 << 26)
>> @@ -45,6 +47,7 @@
>> #define TRIGGER_RESUME_DSS (1 << 30)
>> #define TRIGGER_RESUME_ONE (1 << 31)
>> +#define SHADER_PAGEFAULT (SHADER_PAGEFAULT_READ |
>> SHADER_PAGEFAULT_WRITE)
>> #define BB_REGION_BITMASK (BB_IN_SRAM | BB_IN_VRAM)
>> #define TARGET_REGION_BITMASK (TARGET_IN_SRAM | TARGET_IN_VRAM)
>> @@ -61,6 +64,8 @@
>> #define CACHING_VALUE(n) (CACHING_INIT_VALUE + (n))
>> #define SHADER_CANARY 0x01010101
>> +#define BAD_CANARY 0xf1f1f1f
>> +#define BAD_OFFSET (0x12345678ull << 12)
>> #define WALKER_X_DIM 4
>> #define WALKER_ALIGNMENT 16
>> @@ -123,6 +128,9 @@ static int get_number_of_threads(uint64_t flags)
>> if (flags & SHADER_MIN_THREADS)
>> return 16;
>> + if (flags & SHADER_PAGEFAULT)
>> + return 16;
>
> Nit: could be merged together with the above.
>
>> +
>> if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
>> TRIGGER_RESUME_PARALLEL_WALK | SHADER_CACHING_SRAM |
>> SHADER_CACHING_VRAM))
>> return 32;
>> @@ -179,6 +187,16 @@ static struct gpgpu_shader *get_shader(int fd,
>> const unsigned int flags)
>> gpgpu_shader__common_target_write_u32(shader, s_dim.y +
>> i, CACHING_VALUE(i));
>> gpgpu_shader__nop(shader);
>> gpgpu_shader__breakpoint(shader);
>> + } else if (flags & SHADER_PAGEFAULT) {
>> + if (flags & SHADER_PAGEFAULT_READ)
>> + gpgpu_shader__read_page_fault(shader, BAD_OFFSET);
>> + else if (flags & SHADER_PAGEFAULT_WRITE)
>> + gpgpu_shader__write_offset(shader, BAD_OFFSET, BAD_CANARY);
>> +
>> + gpgpu_shader__label(shader, 0);
>> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>> + gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
>> + gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>> }
>> gpgpu_shader__eot(shader);
>> @@ -217,6 +235,17 @@ static int count_set_bits(void *ptr, size_t size)
>> return count;
>> }
>> +static int
>> +eu_attentions_xor_count(const uint32_t *a, const uint32_t *b,
>> uint32_t size)
>
> Nit: the current checkpatch line limit is 100 characters which means
> this would fit in a single line.
>
>> +{
>> + int count = 0;
>> +
>> + for (int i = 0; i < size / 4 ; i++)
>> + count += igt_hweight(a[i] ^ b[i]);
>> +
>> + return count;
>> +}
>> +
>> static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim,
>> uint32_t value)
>> {
>> int count = 0;
>> @@ -636,7 +665,7 @@ static void eu_attention_resume_trigger(struct
>> xe_eudebug_debugger *d,
>> }
>> }
>> - if (d->flags & SHADER_LOOP) {
>> + if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
>> uint32_t threads = get_number_of_threads(d->flags);
>> uint32_t val = STEERING_END_LOOP;
>> @@ -746,6 +775,43 @@ static void
>> eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
>> data->single_step_bitmask[i] &= ~att->bitmask[i];
>> }
>> +static void eu_attention_resume_pagefault_trigger(struct
>> xe_eudebug_debugger *d,
>> + struct drm_xe_eudebug_event *e)
>> +{
>> + struct drm_xe_eudebug_event_eu_attention *att = (void *) e;
>> + struct online_debug_data *data = d->ptr;
>> + uint32_t bitmask_size = att->bitmask_size;
>> + uint8_t *bitmask;
>> +
>> + if (data->last_eu_control_seqno > att->base.seqno)
>> + return;
>> +
>> + bitmask = calloc(1, att->bitmask_size);
>> +
>> + eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
>> + att->lrc_handle, bitmask, &bitmask_size);
>> + igt_assert(bitmask_size == att->bitmask_size);
>> +
>> + pthread_mutex_lock(&data->mutex);
>> +
>> + if (d->flags & SHADER_PAGEFAULT) {
>> + uint32_t threads = get_number_of_threads(d->flags);
>> + uint32_t val = STEERING_END_LOOP;
>> +
>> + igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
>> + data->target_offset + steering_offset(threads)),
>> + sizeof(uint32_t));
>> + fsync(data->vm_fd);
>> + }
>> + pthread_mutex_unlock(&data->mutex);
>> +
>> + data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd,
>> att->client_handle,
>> + att->exec_queue_handle, att->lrc_handle,
>> + bitmask, att->bitmask_size);
>> +
>> + free(bitmask);
>> +}
>> +
>> static void open_trigger(struct xe_eudebug_debugger *d,
>> struct drm_xe_eudebug_event *e)
>> {
>> @@ -1015,7 +1081,7 @@ static void run_online_client(struct
>> xe_eudebug_client *c)
>> struct intel_bb *ibb;
>> struct intel_buf *buf;
>> uint32_t *ptr;
>> - int fd;
>> + int fd, vm_flags;
>> metadata[0] = calloc(2, sizeof(*metadata));
>> metadata[1] = calloc(2, sizeof(*metadata));
>> @@ -1025,7 +1091,7 @@ static void run_online_client(struct
>> xe_eudebug_client *c)
>> fd = xe_eudebug_client_open_driver(c);
>> /* Additional memory for steering control */
>> - if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
>> + if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c-
>> >flags & SHADER_PAGEFAULT)
>> s_dim.y++;
>> /* Additional memory for caching check */
>> if ((c->flags & SHADER_CACHING_SRAM) || (c->flags &
>> SHADER_CACHING_VRAM))
>> @@ -1045,7 +1111,11 @@ static void run_online_client(struct
>> xe_eudebug_client *c)
>> DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
>> 2 * sizeof(*metadata), metadata[1]);
>> - create.vm_id = xe_eudebug_client_vm_create(c, fd,
>> DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
>> + vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
>> + vm_flags |= c->flags & SHADER_PAGEFAULT ?
>> DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
>> +
>> + create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
>> +
>> xe_eudebug_client_exec_queue_create(c, fd, &create);
>> ibb = xe_bb_create_on_offset(fd, create.exec_queue_id,
>> create.vm_id, bb_offset, bb_size,
>> @@ -1245,11 +1315,14 @@ match_attention_with_exec_queue(struct
>> xe_eudebug_event_log *log,
>> static void online_session_check(struct xe_eudebug_session *s, int
>> flags)
>> {
>> struct drm_xe_eudebug_event_eu_attention *ea = NULL;
>> + struct drm_xe_eudebug_event_pagefault *pf = NULL;
>> struct drm_xe_eudebug_event *event = NULL;
>> struct online_debug_data *data = s->client->ptr;
>> bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
>> int sum = 0;
>> int bitmask_size;
>> + int pagefault_threads = 0;
>> + uint32_t *ptr = NULL;
>> xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
>> XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
>> @@ -1265,6 +1338,16 @@ static void online_session_check(struct
>> xe_eudebug_session *s, int flags)
>> igt_assert_eq(ea->bitmask_size, bitmask_size);
>> sum += count_set_bits(ea->bitmask, bitmask_size);
>> igt_assert(match_attention_with_exec_queue(s->debugger-
>> >log, ea));
>> + } else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
>> + uint32_t after_offset = bitmask_size / sizeof(uint32_t);
>> + uint32_t resolved_offset = bitmask_size /
>> sizeof(uint32_t) * 2;
>> +
>> + pf = (struct drm_xe_eudebug_event_pagefault *)event;
>> + ptr = (uint32_t *) pf->bitmask;
>> + igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
>> + pagefault_threads += eu_attentions_xor_count(ptr +
>> after_offset,
>> + ptr + resolved_offset,
>> + bitmask_size);
>> }
>> }
>> @@ -1279,6 +1362,9 @@ static void online_session_check(struct
>> xe_eudebug_session *s, int flags)
>> igt_assert(sum > 0);
>> else
>> igt_assert(sum == 0);
>> +
>> + if (flags & SHADER_PAGEFAULT)
>> + igt_assert(pagefault_threads > 0);
>> }
>> static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
>> @@ -1302,6 +1388,55 @@ static void ufence_ack_set_bp_trigger(struct
>> xe_eudebug_debugger *d,
>> }
>> }
>> +static void pagefault_trigger(struct xe_eudebug_debugger *d,
>> + struct drm_xe_eudebug_event *e)
>> +{
>> + struct drm_xe_eudebug_event_pagefault *pf = (void *) e;
>> + int before_threads, after_threads, resolved_threads,
>> pagefault_threads;
>> + uint32_t attn_size = pf->bitmask_size / 3;
>> + uint32_t *ptr = (uint32_t *) pf->bitmask;
>> + uint32_t offset, before_offset = 0;
>> + uint32_t after_offset = attn_size / sizeof(uint32_t);
>> + uint32_t resolved_offset = attn_size / sizeof(uint32_t) * 2;
>> +
>> + before_threads = count_set_bits(ptr + before_offset, attn_size);
>> + after_threads = count_set_bits(ptr + after_offset, attn_size);
>> + resolved_threads = count_set_bits(ptr + resolved_offset, attn_size);
>> +
>> + pagefault_threads = eu_attentions_xor_count(ptr + after_offset,
>> + ptr + resolved_offset,
>> + attn_size);
>> +
>> + igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
>> + "resolved=%d, pagefault=%d] "
>> + "client[%llu], exec_queue[%llu], lrc[%llu],
>> bitmask_size[%d], "
>> + "pagefault_address[0x%llx]\n",
>> + pf->base.seqno, before_threads, after_threads,
>> resolved_threads,
>> + pagefault_threads, pf->client_handle, pf->exec_queue_handle,
>> + pf->lrc_handle, pf->bitmask_size,
>> + pf->pagefault_address);
>> +
>> + for (int idx = 0; idx < 3; idx++) {
>> + if (idx == 0) {
>> + igt_debug("=== Attentions before ===\n");
>> + offset = before_offset;
>> + } else if (idx == 1) {
>> + igt_debug("=== Attentions after ===\n");
>> + offset = after_offset;
>> + } else {
>> + igt_debug("=== Attentions resolved ===\n");
>> + offset = resolved_offset;
>> + }
>> +
>> + for (uint32_t i = 0; i < attn_size / sizeof(uint32_t); i += 2)
>> + igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
>> + ptr[offset + i], ptr[offset + i + 1]);
>> + }
>> +
>> + igt_assert(pagefault_threads > 0);
>> + igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
>> +}
>> +
>> /**
>> * SUBTEST: basic-breakpoint
>> * Description:
>> @@ -1383,6 +1518,77 @@ static void test_set_breakpoint_online(int fd,
>> struct drm_xe_engine_class_instan
>> online_debug_data_destroy(data);
>> }
>> +/**
>> + * SUBTEST: pagefault-read
>> + * Description:
>> + * Check whether KMD sends pagefault event for workload in debug
>> mode that
>> + * triggers a read pagefault.
>> + *
>> + * SUBTEST: pagefault-write
>> + * Description:
>> + * Check whether KMD sends pagefault event for workload in debug
>> mode that
>> + * triggers a write pagefault.
>> + */
>> +static void test_pagefault_online(int fd, struct
>> drm_xe_engine_class_instance *hwe,
>> + int flags)
>> +{
>> + struct xe_eudebug_session *s;
>> + struct online_debug_data *data;
>> + uint32_t val;
>> +
>> + data = online_debug_data_create(hwe);
>> + s = xe_eudebug_session_create(fd, run_online_client, flags, data);
>> +
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_OPEN,
>> + open_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
>> + exec_queue_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>> + eu_attention_debug_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>> + eu_attention_resume_pagefault_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_METADATA,
>> + create_metadata_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
>> + ufence_ack_trigger);
>> + xe_eudebug_debugger_add_trigger(s->debugger,
>> DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
>> + pagefault_trigger);
>> +
>> + igt_assert_eq(xe_eudebug_debugger_attach(s->debugger, s->client),
>> 0);
>> + xe_eudebug_debugger_start_worker(s->debugger);
>> + xe_eudebug_client_start(s->client);
>> +
>> + /* wait for workload to start */
>> + igt_for_milliseconds(STARTUP_TIMEOUT_MS) {
>> + /* collect needed data from triggers */
>> + if (READ_ONCE(data->vm_fd) == -1 || READ_ONCE(data-
>> >target_size) == 0)
>> + continue;
>> +
>> + if (pread(data->vm_fd, &val, sizeof(val), data-
>> >target_offset) == sizeof(val))
>> + if (val != 0)
>> + break;
>> + }
>
> I think this is redundant. It looks like it copies the
> 'test_interrupt_all' function, but as far I'm concerned the waiting loop
> is there to interact with the client thread while the gpu workload is
> running. Since we don't do that here I think 'test_pagefault_online'
> should rather resemble the 'test_basic_online' function.
>
Good catch, I'll remove redundant code.
Many thanks,
G.G.
> Thanks,
> Christoph
>
>> +
>> + pthread_mutex_lock(&data->mutex);
>> + igt_assert(data->client_handle != -1);
>> + igt_assert(data->exec_queue_handle != -1);
>> +
>> + pthread_mutex_unlock(&data->mutex);
>> +
>> + xe_eudebug_client_wait_done(s->client);
>> +
>> + xe_eudebug_debugger_stop_worker(s->debugger, 1);
>> +
>> + xe_eudebug_event_log_print(s->debugger->log, true);
>> + xe_eudebug_event_log_print(s->client->log, true);
>> +
>> + online_session_check(s, s->flags);
>> +
>> + xe_eudebug_session_destroy(s);
>> + online_debug_data_destroy(data);
>> +}
>> +
>> /**
>> * SUBTEST: preempt-breakpoint
>> * Description:
>> @@ -2344,6 +2550,11 @@ igt_main
>> igt_subtest("breakpoint-many-sessions-tiles")
>> test_many_sessions_on_tiles(fd, true);
>> + test_gt_render_or_compute("pagefault-read", fd, hwe)
>> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
>> + test_gt_render_or_compute("pagefault-write", fd, hwe)
>> + test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
>> +
>> igt_fixture {
>> xe_eudebug_enable(fd, was_enabled);
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2024-11-21 12:16 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-11-15 14:11 [PATCH i-g-t 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Gwan-gyeong Mun
2024-11-15 14:11 ` [PATCH i-g-t 1/4] lib/gppgu_shader: Add write to ppgtt offset Gwan-gyeong Mun
2024-11-18 13:00 ` Hajda, Andrzej
2024-11-21 12:01 ` Gwan-gyeong Mun
2024-11-15 14:11 ` [PATCH i-g-t 2/4] lib/gpgpu_shader: Add causing a read pagefault from the eu thread Gwan-gyeong Mun
2024-11-18 13:08 ` Hajda, Andrzej
2024-11-21 12:02 ` Gwan-gyeong Mun
2024-11-19 11:38 ` Manszewski, Christoph
2024-11-21 12:07 ` Gwan-gyeong Mun
2024-11-15 14:11 ` [PATCH i-g-t 3/4] eudebug: Add eudebug pagefault event declarations Gwan-gyeong Mun
2024-11-18 16:52 ` Hajda, Andrzej
2024-11-19 8:50 ` Manszewski, Christoph
2024-11-19 12:26 ` Manszewski, Christoph
2024-11-15 14:11 ` [PATCH i-g-t 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests Gwan-gyeong Mun
2024-11-19 8:10 ` Hajda, Andrzej
2024-11-21 12:06 ` Gwan-gyeong Mun
2024-11-19 15:58 ` Hajda, Andrzej
2024-11-21 12:11 ` Gwan-gyeong Mun
2024-11-19 16:49 ` Manszewski, Christoph
2024-11-21 12:15 ` Gwan-gyeong Mun
2024-11-15 14:42 ` ✓ CI.xeBAT: success for tests/intel/xe_eudebug_online: Introduce read/write pagefault tests Patchwork
2024-11-15 14:48 ` ✓ Fi.CI.BAT: " Patchwork
2024-11-15 21:24 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-11-15 23:25 ` ✗ CI.xeFULL: " Patchwork
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