[igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[Chang, Bruce]

add the following invalid va access test cases:

	gpu fault	scratch page	command timeout
1) 	no		no		yes
2) 	no		yes		no
3) 	yes		no		yes
4) 	yes		yes		no

TODO: with futher improvement of xe_wait_ufence, the test
can check more specific error code from it.

v2: async vm/bind, and re-bind valid address
v3: added xe_wait_ufence check

Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 lib/xe/xe_ioctl.c             |  15 +++-
 lib/xe/xe_ioctl.h             |   3 +
 tests/meson.build             |   1 +
 tests/xe/xe_exec_invalid_va.c | 164 ++++++++++++++++++++++++++++++++++
 4 files changed, 180 insertions(+), 3 deletions(-)
 create mode 100644 tests/xe/xe_exec_invalid_va.c

diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 730dcfd16..022f0cf04 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -415,9 +415,9 @@ void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr)
 	syncobj_destroy(fd, sync.handle);
 }
 
-int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
+int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
 		       struct drm_xe_engine_class_instance *eci,
-		       int64_t timeout)
+		       int64_t timeout, bool timeout_assert)
 {
 	struct drm_xe_wait_user_fence wait = {
 		.addr = to_user_pointer(addr),
@@ -430,11 +430,20 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
 		.instances = eci ? to_user_pointer(eci) : 0,
 	};
 
-	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0);
+	if (igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait))
+		igt_assert (!timeout_assert && errno == ETIME);
 
 	return wait.timeout;
 }
 
+
+int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
+		       struct drm_xe_engine_class_instance *eci,
+		       int64_t timeout)
+{
+	return _xe_wait_ufence(fd, addr, value, eci, timeout, true);
+}
+
 /**
  * xe_wait_ufence_abstime:
  * @fd: xe device fd
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index 6c281b3bf..4bf7410a4 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -82,6 +82,9 @@ void xe_exec(int fd, struct drm_xe_exec *exec);
 void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr,
 		  struct drm_xe_sync *sync, uint32_t num_syncs);
 void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr);
+int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
+		       struct drm_xe_engine_class_instance *eci,
+		       int64_t timeout, bool timeout_assert);
 int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
 		       struct drm_xe_engine_class_instance *eci,
 		       int64_t timeout);
diff --git a/tests/meson.build b/tests/meson.build
index 4d325bed1..8861b6c5b 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -276,6 +276,7 @@ xe_progs = [
 	'xe_exec_reset',
 	'xe_exec_store',
 	'xe_exec_threads',
+	'xe_exec_invalid_va',
 	'xe_exercise_blt',
 	'xe_gpgpu_fill',
 	'xe_guc_pc',
diff --git a/tests/xe/xe_exec_invalid_va.c b/tests/xe/xe_exec_invalid_va.c
new file mode 100644
index 000000000..468b90c8a
--- /dev/null
+++ b/tests/xe/xe_exec_invalid_va.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+/**
+ * TEST: invalid va tests
+ * Category: Hardware building block
+ * Sub-category: execbuf
+ * Functionality: fault mode
+ * Test category: functionality test
+ * GPU requirements: GPU needs support for DRM_XE_VM_CREATE_FAULT_MODE
+ */
+
+#include <fcntl.h>
+
+#include "igt.h"
+#include "lib/igt_syncobj.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include <string.h>
+
+static void insert_store(uint32_t *bb, uint64_t va, uint64_t data)
+{
+	*bb++ = MI_STORE_DWORD_IMM_GEN4;
+	*bb++ = lower_32_bits(va);
+	*bb++ = upper_32_bits(va);
+	*bb++ = data;
+	*bb++ = MI_BATCH_BUFFER_END;
+}
+
+/**
+ * SUBTEST: invalid-va
+ * Description: Check driver handling of invalid va access
+ * Run type: FULL
+ *
+ * SUBTEST: invalid-va-scratch
+ * Description: Check driver handling of invalid va access with scratch page
+ * Run type: FULL
+ *
+ * SUBTEST: invalid-va-fault
+ * Description: Check driver handling of invalid va access with fault enabled
+ * Run type: FULL
+ *
+ * SUBTEST: invalid-va-fault-scratch
+ * Description: Check driver handling of invalid va access with fault + scratch page
+ * Run type: FULL
+ *
+ * arg[1]: for vm create flags
+ */
+static void test_exec(int fd, uint32_t flags)
+{
+	const uint64_t inv_addr = 0x20000000;
+	const uint64_t addr = 0x1a0000;
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+#define ONE_SEC			MS_TO_NS(1000)
+#define	STORE_DATA		0xDEADBEAF
+	struct _data {
+		uint32_t batch[16];
+		uint64_t vm_sync;
+		uint64_t sync;
+		uint64_t data;
+	} *data;
+	struct drm_xe_sync sync = {
+		.flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+		.timeline_value = USER_FENCE_VALUE,
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.address = addr,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&sync),
+	};
+	uint32_t vm;
+	uint32_t bo;
+	size_t bo_size;
+	struct drm_xe_engine_class_instance *eci;
+
+	eci = xe_hw_engine(fd, 0);
+	vm = xe_vm_create(fd, flags | DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+	bo_size = ALIGN(sizeof(*data), xe_get_default_alignment(fd));
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				all_memory_regions(fd) |
+				visible_vram_if_possible(fd, 0));
+	data = xe_bo_map(fd, bo, bo_size);
+	memset(data, 0, bo_size);
+
+	insert_store(data->batch, inv_addr + offsetof(struct _data, data), STORE_DATA);
+	exec.exec_queue_id = xe_exec_queue_create(fd, vm, eci, 0);
+	sync.addr = to_user_pointer(&data->vm_sync);
+	xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
+				addr, bo_size, &sync, 1,
+				XE_VM_BIND_FLAG_IMMEDIATE);
+	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+	data->vm_sync = 0;
+	sync.addr = addr + offsetof(struct _data, sync);
+	xe_exec(fd, &exec);
+	_xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC, false);
+	if (!(flags & DRM_XE_VM_CREATE_SCRATCH_PAGE))
+		assert(errno == ETIME);
+	else
+		assert(errno == 0);
+	data->sync = 0;
+
+	if ((flags & DRM_XE_VM_CREATE_FAULT_MODE) &&
+	    (flags & DRM_XE_VM_CREATE_SCRATCH_PAGE)) {
+		/* bind inv_addr after scratch page was created */
+		sync.addr = to_user_pointer(&data->vm_sync);
+		xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
+				inv_addr, bo_size, &sync, 1,
+				XE_VM_BIND_FLAG_IMMEDIATE);
+		xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+		data->vm_sync = 0;
+		data->data = 0;
+		sync.addr = addr + offsetof(struct _data, sync);
+		xe_exec(fd, &exec);
+		xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+		igt_assert_eq(data->data, STORE_DATA);
+	}
+
+	sync.addr = to_user_pointer(&data->vm_sync);
+	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
+	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+	data->vm_sync = 0;
+	xe_vm_unbind_async(fd, vm, 0, 0, inv_addr, bo_size, &sync, 1);
+	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+	xe_exec_queue_destroy(fd, exec.exec_queue_id);
+	munmap(data, bo_size);
+	gem_close(fd, bo);
+	xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+	const struct section {
+		const char *name;
+		unsigned int flags;
+	} sections[] = {
+		{ "invalid-va", 0 },
+		{ "invalid-va-scratch", DRM_XE_VM_CREATE_SCRATCH_PAGE },
+		{ "invalid-va-fault", DRM_XE_VM_CREATE_FAULT_MODE },
+		{ "invalid-va-fault-scratch", DRM_XE_VM_CREATE_FAULT_MODE |
+					      DRM_XE_VM_CREATE_SCRATCH_PAGE },
+		{ NULL },
+	};
+	int fd;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_XE);
+		igt_require(xe_supports_faults(fd));
+	}
+
+	for (const struct section *s = sections; s->name; s++) {
+		igt_subtest_f("%s", s->name)
+			test_exec(fd, s->flags);
+	}
+
+	igt_fixture
+		drm_close_driver(fd);
+}
+
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[Welty, Brian]

On 8/31/2023 4:46 PM, Chang, Bruce wrote:
> add the following invalid va access test cases:
> 
> 	gpu fault	scratch page	command timeout
> 1) 	no		no		yes
> 2) 	no		yes		no
> 3) 	yes		no		yes
> 4) 	yes		yes		no
> 
> TODO: with futher improvement of xe_wait_ufence, the test
> can check more specific error code from it.
> 

Typo with futher above.

Test looks good to me!
I note 2 issues below....
With those addressed:
   Reviewed-by: Brian Welty <brian.welty@intel.com>

But I don't know IGT process for adding new tests.
As this is brand new test, I hope there is gatekeeper making sure new
tests are truly needed (versus adding into some existing test)?  So
seems maintainer feedback or second reviewer who knows IGT better than 
me is best.

-Brian


> v2: async vm/bind, and re-bind valid address
> v3: added xe_wait_ufence check
> 
> Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> ---
>   lib/xe/xe_ioctl.c             |  15 +++-
>   lib/xe/xe_ioctl.h             |   3 +
>   tests/meson.build             |   1 +
>   tests/xe/xe_exec_invalid_va.c | 164 ++++++++++++++++++++++++++++++++++
>   4 files changed, 180 insertions(+), 3 deletions(-)
>   create mode 100644 tests/xe/xe_exec_invalid_va.c
> 
> diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
> index 730dcfd16..022f0cf04 100644
> --- a/lib/xe/xe_ioctl.c
> +++ b/lib/xe/xe_ioctl.c
> @@ -415,9 +415,9 @@ void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr)
>   	syncobj_destroy(fd, sync.handle);
>   }
>   
> -int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> +int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
>   		       struct drm_xe_engine_class_instance *eci,
> -		       int64_t timeout)
> +		       int64_t timeout, bool timeout_assert)
>   {
>   	struct drm_xe_wait_user_fence wait = {
>   		.addr = to_user_pointer(addr),
> @@ -430,11 +430,20 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
>   		.instances = eci ? to_user_pointer(eci) : 0,
>   	};
>   
> -	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0);
> +	if (igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait))
> +		igt_assert (!timeout_assert && errno == ETIME);

This doesn't look right to me...  I might be confused.

I think you want:
     igt_assert(!timeout_assert || errno == ETIME);

or:
    if (igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait) && 
timeout_assert)
         igt_assert(errno == ETIME);


>   
>   	return wait.timeout;
>   }
>   
> +
> +int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> +		       struct drm_xe_engine_class_instance *eci,
> +		       int64_t timeout)
> +{
> +	return _xe_wait_ufence(fd, addr, value, eci, timeout, true);
> +}
> +
>   /**
>    * xe_wait_ufence_abstime:
>    * @fd: xe device fd
> diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
> index 6c281b3bf..4bf7410a4 100644
> --- a/lib/xe/xe_ioctl.h
> +++ b/lib/xe/xe_ioctl.h
> @@ -82,6 +82,9 @@ void xe_exec(int fd, struct drm_xe_exec *exec);
>   void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr,
>   		  struct drm_xe_sync *sync, uint32_t num_syncs);
>   void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr);
> +int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> +		       struct drm_xe_engine_class_instance *eci,
> +		       int64_t timeout, bool timeout_assert);
>   int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
>   		       struct drm_xe_engine_class_instance *eci,
>   		       int64_t timeout);
> diff --git a/tests/meson.build b/tests/meson.build
> index 4d325bed1..8861b6c5b 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -276,6 +276,7 @@ xe_progs = [
>   	'xe_exec_reset',
>   	'xe_exec_store',
>   	'xe_exec_threads',
> +	'xe_exec_invalid_va',

I believe team wants these sorted alphabetically.

>   	'xe_exercise_blt',
>   	'xe_gpgpu_fill',
>   	'xe_guc_pc',
> diff --git a/tests/xe/xe_exec_invalid_va.c b/tests/xe/xe_exec_invalid_va.c
> new file mode 100644
> index 000000000..468b90c8a
> --- /dev/null
> +++ b/tests/xe/xe_exec_invalid_va.c
> @@ -0,0 +1,164 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +/**
> + * TEST: invalid va tests
> + * Category: Hardware building block
> + * Sub-category: execbuf
> + * Functionality: fault mode
> + * Test category: functionality test
> + * GPU requirements: GPU needs support for DRM_XE_VM_CREATE_FAULT_MODE
> + */
> +
> +#include <fcntl.h>
> +
> +#include "igt.h"
> +#include "lib/igt_syncobj.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include <string.h>
> +
> +static void insert_store(uint32_t *bb, uint64_t va, uint64_t data)
> +{
> +	*bb++ = MI_STORE_DWORD_IMM_GEN4;
> +	*bb++ = lower_32_bits(va);
> +	*bb++ = upper_32_bits(va);
> +	*bb++ = data;
> +	*bb++ = MI_BATCH_BUFFER_END;
> +}
> +
> +/**
> + * SUBTEST: invalid-va
> + * Description: Check driver handling of invalid va access
> + * Run type: FULL
> + *
> + * SUBTEST: invalid-va-scratch
> + * Description: Check driver handling of invalid va access with scratch page
> + * Run type: FULL
> + *
> + * SUBTEST: invalid-va-fault
> + * Description: Check driver handling of invalid va access with fault enabled
> + * Run type: FULL
> + *
> + * SUBTEST: invalid-va-fault-scratch
> + * Description: Check driver handling of invalid va access with fault + scratch page
> + * Run type: FULL
> + *
> + * arg[1]: for vm create flags
> + */
> +static void test_exec(int fd, uint32_t flags)
> +{
> +	const uint64_t inv_addr = 0x20000000;
> +	const uint64_t addr = 0x1a0000;
> +#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
> +#define ONE_SEC			MS_TO_NS(1000)
> +#define	STORE_DATA		0xDEADBEAF
> +	struct _data {
> +		uint32_t batch[16];
> +		uint64_t vm_sync;
> +		uint64_t sync;
> +		uint64_t data;
> +	} *data;
> +	struct drm_xe_sync sync = {
> +		.flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
> +		.timeline_value = USER_FENCE_VALUE,
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.address = addr,
> +		.num_syncs = 1,
> +		.syncs = to_user_pointer(&sync),
> +	};
> +	uint32_t vm;
> +	uint32_t bo;
> +	size_t bo_size;
> +	struct drm_xe_engine_class_instance *eci;
> +
> +	eci = xe_hw_engine(fd, 0);
> +	vm = xe_vm_create(fd, flags | DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> +	bo_size = ALIGN(sizeof(*data), xe_get_default_alignment(fd));
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				all_memory_regions(fd) |
> +				visible_vram_if_possible(fd, 0));
> +	data = xe_bo_map(fd, bo, bo_size);
> +	memset(data, 0, bo_size);
> +
> +	insert_store(data->batch, inv_addr + offsetof(struct _data, data), STORE_DATA);
> +	exec.exec_queue_id = xe_exec_queue_create(fd, vm, eci, 0);
> +	sync.addr = to_user_pointer(&data->vm_sync);
> +	xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
> +				addr, bo_size, &sync, 1,
> +				XE_VM_BIND_FLAG_IMMEDIATE);
> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +	data->vm_sync = 0;
> +	sync.addr = addr + offsetof(struct _data, sync);
> +	xe_exec(fd, &exec);
> +	_xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC, false);
> +	if (!(flags & DRM_XE_VM_CREATE_SCRATCH_PAGE))
> +		assert(errno == ETIME);
> +	else
> +		assert(errno == 0);
> +	data->sync = 0;
> +
> +	if ((flags & DRM_XE_VM_CREATE_FAULT_MODE) &&
> +	    (flags & DRM_XE_VM_CREATE_SCRATCH_PAGE)) {
> +		/* bind inv_addr after scratch page was created */
> +		sync.addr = to_user_pointer(&data->vm_sync);
> +		xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
> +				inv_addr, bo_size, &sync, 1,
> +				XE_VM_BIND_FLAG_IMMEDIATE);
> +		xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +		data->vm_sync = 0;
> +		data->data = 0;
> +		sync.addr = addr + offsetof(struct _data, sync);
> +		xe_exec(fd, &exec);
> +		xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +		igt_assert_eq(data->data, STORE_DATA);
> +	}
> +
> +	sync.addr = to_user_pointer(&data->vm_sync);
> +	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +	data->vm_sync = 0;
> +	xe_vm_unbind_async(fd, vm, 0, 0, inv_addr, bo_size, &sync, 1);
> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +	xe_exec_queue_destroy(fd, exec.exec_queue_id);
> +	munmap(data, bo_size);
> +	gem_close(fd, bo);
> +	xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> +	const struct section {
> +		const char *name;
> +		unsigned int flags;
> +	} sections[] = {
> +		{ "invalid-va", 0 },
> +		{ "invalid-va-scratch", DRM_XE_VM_CREATE_SCRATCH_PAGE },
> +		{ "invalid-va-fault", DRM_XE_VM_CREATE_FAULT_MODE },
> +		{ "invalid-va-fault-scratch", DRM_XE_VM_CREATE_FAULT_MODE |
> +					      DRM_XE_VM_CREATE_SCRATCH_PAGE },
> +		{ NULL },
> +	};
> +	int fd;
> +
> +	igt_fixture {
> +		fd = drm_open_driver(DRIVER_XE);
> +		igt_require(xe_supports_faults(fd));
> +	}
> +
> +	for (const struct section *s = sections; s->name; s++) {
> +		igt_subtest_f("%s", s->name)
> +			test_exec(fd, s->flags);
> +	}
> +
> +	igt_fixture
> +		drm_close_driver(fd);
> +}
> +

[igt-dev] ✓ CI.xeBAT: success for tests/xe add invalid va access tests (rev3)

[Patchwork]

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== Series Details ==

Series: tests/xe add invalid va access tests (rev3)
URL   : https://patchwork.freedesktop.org/series/122983/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7460_BAT -> XEIGTPW_9700_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_9700_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-adlp-7:         [PASS][1] -> [FAIL][2] ([Intel XE#480]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7460/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9700/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
  [Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480


Build changes
-------------

  * IGT: IGT_7460 -> IGTPW_9700
  * Linux: xe-348-72da4b45f58f2a95d45743801a10e1f1e1dcce05 -> xe-351-bca3262d221e1402c03a89bb4ba520d6aa610505

  IGTPW_9700: 9700
  IGT_7460: 30b4034ea562952039ba6af58106791d5c39999e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-348-72da4b45f58f2a95d45743801a10e1f1e1dcce05: 72da4b45f58f2a95d45743801a10e1f1e1dcce05
  xe-351-bca3262d221e1402c03a89bb4ba520d6aa610505: bca3262d221e1402c03a89bb4ba520d6aa610505

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9700/index.html

[-- Attachment #2: Type: text/html, Size: 2175 bytes --]

[igt-dev] ✗ GitLab.Pipeline: warning for tests/xe add invalid va access tests (rev3)

[Patchwork]

== Series Details ==

Series: tests/xe add invalid va access tests (rev3)
URL   : https://patchwork.freedesktop.org/series/122983/
State : warning

== Summary ==

Pipeline status: FAILED.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/974946 for the overview.

build-containers:build-debian-arm64 has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48335559):
  time="2023-09-01T00:31:55Z" level=fatal msg="Get https://registry.freedesktop.org/v2/gfx-ci/igt-ci-tags/build-debian-arm64/manifests/dockerfile-f370b1c77e386827453db413b775a4c9bff41794: dial tcp 147.75.198.156:443: i/o timeout" 
  Building!
  STEP 1: FROM debian:buster
  Getting image source signatures
  Copying blob sha256:d6b7393fb4f375905c31c483d81ce2a2905f88aba8cb198874da2b54035bc41d
  Copying config sha256:de08540e8ff0e470ff7956df4bed403725a5f45c186e9bf495da5344ff8fbe84
  Writing manifest to image destination
  Storing signatures
  STEP 2: RUN apt-get update
  error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-09-01T00:32:04Z" level=warning msg="signal: killed"
  time="2023-09-01T00:32:04Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
  container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
  : exit status 1
  Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1
  section_end:1693528325:step_script
  section_start:1693528325:cleanup_file_variables
  Cleaning up project directory and file based variables
  section_end:1693528325:cleanup_file_variables
  ERROR: Job failed: exit code 1
  

build-containers:build-debian-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48335560):
  time="2023-09-01T00:32:20Z" level=fatal msg="Error determining repository tags: Get https://registry.freedesktop.org/v2/gfx-ci/igt-ci-tags/build-debian-mips/tags/list?last=commit-7b81f2b10ec53d943e411f64005778683ca44650&n=100: dial tcp 147.75.198.156:443: i/o timeout" 
  Building!
  STEP 1: FROM debian:buster
  Getting image source signatures
  Copying blob sha256:d6b7393fb4f375905c31c483d81ce2a2905f88aba8cb198874da2b54035bc41d
  Copying config sha256:de08540e8ff0e470ff7956df4bed403725a5f45c186e9bf495da5344ff8fbe84
  Writing manifest to image destination
  Storing signatures
  STEP 2: RUN apt-get update
  error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-09-01T00:32:24Z" level=warning msg="signal: killed"
  time="2023-09-01T00:32:24Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
  container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
  : exit status 1
  Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1
  section_end:1693528345:step_script
  section_start:1693528345:cleanup_file_variables
  Cleaning up project directory and file based variables
  section_end:1693528345:cleanup_file_variables
  ERROR: Job failed: exit code 1
  

build-containers:build-fedora has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48335561):
  time="2023-09-01T00:48:05Z" level=fatal msg="Error determining repository tags: Get https://registry.freedesktop.org/v2/gfx-ci/igt-ci-tags/build-fedora/tags/list?last=commit-069790fa6dc8202b3a9a86021aac84c0f53a8967&n=100: read tcp 10.88.98.200:60028->147.75.198.156:443: read: connection timed out" 
  Building!
  STEP 1: FROM fedora:31
  Getting image source signatures
  Copying blob sha256:854946d575a439a894349addd141568875d7c1e673d3286b08250f3dde002e6a
  Copying config sha256:7e94ed77b448a8d2ff08b92d3ca743e4e862c744892d6886c73487581eb5863a
  Writing manifest to image destination
  Storing signatures
  STEP 2: RUN dnf install -y 	gcc flex bison libatomic meson ninja-build xdotool 	'pkgconfig(libdrm)' 	'pkgconfig(pciaccess)' 	'pkgconfig(libkmod)' 	'pkgconfig(libprocps)' 	'pkgconfig(libunwind)' 	'pkgconfig(libdw)' 	'pkgconfig(pixman-1)' 	'pkgconfig(valgrind)' 	'pkgconfig(cairo)' 	'pkgconfig(libudev)' 	'pkgconfig(glib-2.0)' 	'pkgconfig(gsl)' 	'pkgconfig(alsa)' 	'pkgconfig(xmlrpc)' 	'pkgconfig(xmlrpc_util)' 	'pkgconfig(xmlrpc_client)' 	'pkgconfig(json-c)' 	'pkgconfig(gtk-doc)' 	'pkgconfig(xv)' 	'pkgconfig(xrandr)' 	python3-docutils
  error running container: error creating container for [/bin/sh -c dnf install -y 	gcc flex bison libatomic meson ninja-build xdotool 	'pkgconfig(libdrm)' 	'pkgconfig(pciaccess)' 	'pkgconfig(libkmod)' 	'pkgconfig(libprocps)' 	'pkgconfig(libunwind)' 	'pkgconfig(libdw)' 	'pkgconfig(pixman-1)' 	'pkgconfig(valgrind)' 	'pkgconfig(cairo)' 	'pkgconfig(libudev)' 	'pkgconfig(glib-2.0)' 	'pkgconfig(gsl)' 	'pkgconfig(alsa)' 	'pkgconfig(xmlrpc)' 	'pkgconfig(xmlrpc_util)' 	'pkgconfig(xmlrpc_client)' 	'pkgconfig(json-c)' 	'pkgconfig(gtk-doc)' 	'pkgconfig(xv)' 	'pkgconfig(xrandr)' 	python3-docutils]: time="2023-09-01T00:48:11Z" level=warning msg="signal: killed"
  time="2023-09-01T00:48:11Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
  container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
  : exit status 1
  Error: error building at STEP "RUN dnf install -y 	gcc flex bison libatomic meson ninja-build xdotool 	'pkgconfig(libdrm)' 	'pkgconfig(pciaccess)' 	'pkgconfig(libkmod)' 	'pkgconfig(libprocps)' 	'pkgconfig(libunwind)' 	'pkgconfig(libdw)' 	'pkgconfig(pixman-1)' 	'pkgconfig(valgrind)' 	'pkgconfig(cairo)' 	'pkgconfig(libudev)' 	'pkgconfig(glib-2.0)' 	'pkgconfig(gsl)' 	'pkgconfig(alsa)' 	'pkgconfig(xmlrpc)' 	'pkgconfig(xmlrpc_util)' 	'pkgconfig(xmlrpc_client)' 	'pkgconfig(json-c)' 	'pkgconfig(gtk-doc)' 	'pkgconfig(xv)' 	'pkgconfig(xrandr)' 	python3-docutils": error while running runtime: exit status 1
  section_end:1693529291:step_script
  section_start:1693529291:cleanup_file_variables
  Cleaning up project directory and file based variables
  section_end:1693529292:cleanup_file_variables
  ERROR: Job failed: exit code 1

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/974946

[igt-dev] ✗ Fi.CI.BAT: failure for tests/xe add invalid va access tests (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10727 bytes --]

== Series Details ==

Series: tests/xe add invalid va access tests (rev3)
URL   : https://patchwork.freedesktop.org/series/122983/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13583 -> IGTPW_9700
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_9700 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_9700, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/index.html

Participating hosts (38 -> 39)
------------------------------

  Additional (2): fi-kbl-soraka bat-rpls-2 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_9700:

### IGT changes ###

#### Possible regressions ####

  * igt@dmabuf@all-tests@sanitycheck:
    - fi-skl-guc:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13583/fi-skl-guc/igt@dmabuf@all-tests@sanitycheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/fi-skl-guc/igt@dmabuf@all-tests@sanitycheck.html

  
Known issues
------------

  Here are the changes found in IGTPW_9700 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-rpls-2:         NOTRUN -> [SKIP][3] ([i915#7456])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@debugfs_test@basic-hwmon.html

  * igt@dmabuf@all-tests@dma_fence:
    - fi-skl-guc:         [PASS][4] -> [DMESG-FAIL][5] ([i915#8189])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13583/fi-skl-guc/igt@dmabuf@all-tests@dma_fence.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/fi-skl-guc/igt@dmabuf@all-tests@dma_fence.html

  * igt@fbdev@info:
    - bat-rpls-2:         NOTRUN -> [SKIP][6] ([i915#1849] / [i915#2582])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@fbdev@info.html

  * igt@fbdev@read:
    - bat-rpls-2:         NOTRUN -> [SKIP][7] ([i915#2582]) +3 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@fbdev@read.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - bat-rpls-2:         NOTRUN -> [ABORT][8] ([i915#7978] / [i915#8668])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-rpls-2:         NOTRUN -> [SKIP][11] ([i915#4613]) +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_tiled_pread_basic:
    - bat-rpls-2:         NOTRUN -> [SKIP][12] ([i915#3282])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - bat-rpls-2:         NOTRUN -> [SKIP][13] ([i915#7561])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
    - bat-rpls-2:         NOTRUN -> [SKIP][14] ([i915#6621])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-n3050:       [PASS][15] -> [ABORT][16] ([i915#7913])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13583/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/fi-bsw-n3050/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-apl-guc:         [PASS][17] -> [DMESG-FAIL][18] ([i915#5334])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13583/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
    - bat-rpls-2:         NOTRUN -> [DMESG-FAIL][19] ([i915#4258] / [i915#7913])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][20] ([i915#1886] / [i915#7913])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@requests:
    - bat-mtlp-8:         [PASS][21] -> [ABORT][22] ([i915#7982] / [i915#8865])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13583/bat-mtlp-8/igt@i915_selftest@live@requests.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-mtlp-8/igt@i915_selftest@live@requests.html

  * igt@kms_busy@basic:
    - bat-rpls-2:         NOTRUN -> [SKIP][23] ([i915#1845]) +15 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@kms_busy@basic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][24] ([fdo#109271]) +8 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-rpls-2:         NOTRUN -> [SKIP][25] ([i915#3637]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-rpls-2:         NOTRUN -> [SKIP][26] ([fdo#109285])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-rpls-2:         NOTRUN -> [SKIP][27] ([i915#1849])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-rpls-2:         NOTRUN -> [SKIP][28] ([i915#1072]) +3 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-rpls-2:         NOTRUN -> [SKIP][29] ([i915#3555])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-rpls-2:         NOTRUN -> [SKIP][30] ([fdo#109295] / [i915#1845] / [i915#3708])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-read:
    - bat-rpls-2:         NOTRUN -> [SKIP][31] ([fdo#109295] / [i915#3708]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rpls-2/igt@prime_vgem@basic-fence-read.html

  
#### Possible fixes ####

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - {bat-dg2-13}:       [DMESG-WARN][32] ([i915#7952]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13583/bat-dg2-13/igt@kms_chamelium_edid@hdmi-edid-read.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-dg2-13/igt@kms_chamelium_edid@hdmi-edid-read.html

  
#### Warnings ####

  * igt@kms_psr@primary_page_flip:
    - bat-rplp-1:         [SKIP][34] ([i915#1072]) -> [ABORT][35] ([i915#8442] / [i915#8668] / [i915#8860])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13583/bat-rplp-1/igt@kms_psr@primary_page_flip.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/bat-rplp-1/igt@kms_psr@primary_page_flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
  [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
  [i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
  [i915#8189]: https://gitlab.freedesktop.org/drm/intel/issues/8189
  [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8860]: https://gitlab.freedesktop.org/drm/intel/issues/8860
  [i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7460 -> IGTPW_9700

  CI-20190529: 20190529
  CI_DRM_13583: f299d7585a085ee36999da219c292e265da35886 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9700: 9700
  IGT_7460: 30b4034ea562952039ba6af58106791d5c39999e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+++ 59614 lines
--- 59610 lines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9700/index.html

[-- Attachment #2: Type: text/html, Size: 12821 bytes --]

Re: [igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[Kamil Konieczny]

Hi Bruce,

On 2023-08-31 at 23:46:54 +0000, Chang, Bruce wrote:
> add the following invalid va access test cases:
> 
> 	gpu fault	scratch page	command timeout
> 1) 	no		no		yes
> 2) 	no		yes		no
> 3) 	yes		no		yes
> 4) 	yes		yes		no
> 
> TODO: with futher improvement of xe_wait_ufence, the test
> can check more specific error code from it.
> 
> v2: async vm/bind, and re-bind valid address
> v3: added xe_wait_ufence check
> 
> Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> ---
>  lib/xe/xe_ioctl.c             |  15 +++-
>  lib/xe/xe_ioctl.h             |   3 +
>  tests/meson.build             |   1 +
>  tests/xe/xe_exec_invalid_va.c | 164 ++++++++++++++++++++++++++++++++++

Why not placing this in xe_vm.c as a subtest? We have too much
xe_exec tests. Or use other name like xe_vm_invalid.

>  4 files changed, 180 insertions(+), 3 deletions(-)
>  create mode 100644 tests/xe/xe_exec_invalid_va.c
> 
> diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
> index 730dcfd16..022f0cf04 100644
> --- a/lib/xe/xe_ioctl.c
> +++ b/lib/xe/xe_ioctl.c
> @@ -415,9 +415,9 @@ void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr)
>  	syncobj_destroy(fd, sync.handle);
>  }
>  
> -int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> +int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
>  		       struct drm_xe_engine_class_instance *eci,
> -		       int64_t timeout)
> +		       int64_t timeout, bool timeout_assert)
------------------------------- ^
Do not instroduce a bool parameter, rather make __function
which will return errno in case of ioctl error, so later you may
use it like:
        ret = __xe_wait_ufence(..., &val);
        igt_assert_f(!ret || ret == -ETIME, "error %d\n", ret);


int __xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
		       struct drm_xe_engine_class_instance *eci,
		       int64_t timeout)
		       int64_t timeout,
               int64_t *retval)
{
        ...
        ret = igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait);
        if (!ret)
                *retval = wait.timeout;

        return ret;
}

uint64_t xe_wait_ufence(...)
{
        uint64_t val;

        igt_assert_eq(__xe_wait_ufence(..., &val), 0);

        return val;
}

Add description to each new/old library function you re/write.

>  {
>  	struct drm_xe_wait_user_fence wait = {
>  		.addr = to_user_pointer(addr),
> @@ -430,11 +430,20 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
>  		.instances = eci ? to_user_pointer(eci) : 0,
>  	};
>  
> -	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0);
> +	if (igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait))
> +		igt_assert (!timeout_assert && errno == ETIME);
>  
>  	return wait.timeout;
>  }
>  
> +
> +int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> +		       struct drm_xe_engine_class_instance *eci,
> +		       int64_t timeout)
> +{
> +	return _xe_wait_ufence(fd, addr, value, eci, timeout, true);
> +}
> +
>  /**
>   * xe_wait_ufence_abstime:
>   * @fd: xe device fd
> diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
> index 6c281b3bf..4bf7410a4 100644
> --- a/lib/xe/xe_ioctl.h
> +++ b/lib/xe/xe_ioctl.h
> @@ -82,6 +82,9 @@ void xe_exec(int fd, struct drm_xe_exec *exec);
>  void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr,
>  		  struct drm_xe_sync *sync, uint32_t num_syncs);
>  void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr);
> +int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> +		       struct drm_xe_engine_class_instance *eci,
> +		       int64_t timeout, bool timeout_assert);
>  int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
>  		       struct drm_xe_engine_class_instance *eci,
>  		       int64_t timeout);
> diff --git a/tests/meson.build b/tests/meson.build
> index 4d325bed1..8861b6c5b 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -276,6 +276,7 @@ xe_progs = [
>  	'xe_exec_reset',
>  	'xe_exec_store',
>  	'xe_exec_threads',
> +	'xe_exec_invalid_va',
>  	'xe_exercise_blt',
>  	'xe_gpgpu_fill',
>  	'xe_guc_pc',
> diff --git a/tests/xe/xe_exec_invalid_va.c b/tests/xe/xe_exec_invalid_va.c
> new file mode 100644
> index 000000000..468b90c8a
> --- /dev/null
> +++ b/tests/xe/xe_exec_invalid_va.c
> @@ -0,0 +1,164 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +/**
> + * TEST: invalid va tests
> + * Category: Hardware building block
> + * Sub-category: execbuf
> + * Functionality: fault mode
> + * Test category: functionality test
> + * GPU requirements: GPU needs support for DRM_XE_VM_CREATE_FAULT_MODE
> + */
> +
> +#include <fcntl.h>
> +
> +#include "igt.h"
> +#include "lib/igt_syncobj.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include <string.h>
----------- ^
Move above after <fcntl.h>

> +
> +static void insert_store(uint32_t *bb, uint64_t va, uint64_t data)
> +{
> +	*bb++ = MI_STORE_DWORD_IMM_GEN4;
> +	*bb++ = lower_32_bits(va);
> +	*bb++ = upper_32_bits(va);
> +	*bb++ = data;
> +	*bb++ = MI_BATCH_BUFFER_END;
> +}
> +
> +/**
> + * SUBTEST: invalid-va
> + * Description: Check driver handling of invalid va access
> + * Run type: FULL
> + *
> + * SUBTEST: invalid-va-scratch
> + * Description: Check driver handling of invalid va access with scratch page
> + * Run type: FULL
> + *
> + * SUBTEST: invalid-va-fault
> + * Description: Check driver handling of invalid va access with fault enabled
> + * Run type: FULL
> + *
> + * SUBTEST: invalid-va-fault-scratch
> + * Description: Check driver handling of invalid va access with fault + scratch page
> + * Run type: FULL
> + *
> + * arg[1]: for vm create flags
> + */
> +static void test_exec(int fd, uint32_t flags)
> +{
> +	const uint64_t inv_addr = 0x20000000;
> +	const uint64_t addr = 0x1a0000;
> +#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
------------------------------^
imho better in uppercase

> +#define ONE_SEC			MS_TO_NS(1000)
> +#define	STORE_DATA		0xDEADBEAF
----------------------------- ^
Inconsistent, use either upper or lower case.

Regards,
Kamil

> +	struct _data {
> +		uint32_t batch[16];
> +		uint64_t vm_sync;
> +		uint64_t sync;
> +		uint64_t data;
> +	} *data;
> +	struct drm_xe_sync sync = {
> +		.flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
> +		.timeline_value = USER_FENCE_VALUE,
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.address = addr,
> +		.num_syncs = 1,
> +		.syncs = to_user_pointer(&sync),
> +	};
> +	uint32_t vm;
> +	uint32_t bo;
> +	size_t bo_size;
> +	struct drm_xe_engine_class_instance *eci;
> +
> +	eci = xe_hw_engine(fd, 0);
> +	vm = xe_vm_create(fd, flags | DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> +	bo_size = ALIGN(sizeof(*data), xe_get_default_alignment(fd));
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				all_memory_regions(fd) |
> +				visible_vram_if_possible(fd, 0));
> +	data = xe_bo_map(fd, bo, bo_size);
> +	memset(data, 0, bo_size);
> +
> +	insert_store(data->batch, inv_addr + offsetof(struct _data, data), STORE_DATA);
> +	exec.exec_queue_id = xe_exec_queue_create(fd, vm, eci, 0);
> +	sync.addr = to_user_pointer(&data->vm_sync);
> +	xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
> +				addr, bo_size, &sync, 1,
> +				XE_VM_BIND_FLAG_IMMEDIATE);
> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +	data->vm_sync = 0;
> +	sync.addr = addr + offsetof(struct _data, sync);
> +	xe_exec(fd, &exec);
> +	_xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC, false);
> +	if (!(flags & DRM_XE_VM_CREATE_SCRATCH_PAGE))
> +		assert(errno == ETIME);
> +	else
> +		assert(errno == 0);
> +	data->sync = 0;
> +
> +	if ((flags & DRM_XE_VM_CREATE_FAULT_MODE) &&
> +	    (flags & DRM_XE_VM_CREATE_SCRATCH_PAGE)) {
> +		/* bind inv_addr after scratch page was created */
> +		sync.addr = to_user_pointer(&data->vm_sync);
> +		xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
> +				inv_addr, bo_size, &sync, 1,
> +				XE_VM_BIND_FLAG_IMMEDIATE);
> +		xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +		data->vm_sync = 0;
> +		data->data = 0;
> +		sync.addr = addr + offsetof(struct _data, sync);
> +		xe_exec(fd, &exec);
> +		xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +		igt_assert_eq(data->data, STORE_DATA);
> +	}
> +
> +	sync.addr = to_user_pointer(&data->vm_sync);
> +	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +	data->vm_sync = 0;
> +	xe_vm_unbind_async(fd, vm, 0, 0, inv_addr, bo_size, &sync, 1);
> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +	xe_exec_queue_destroy(fd, exec.exec_queue_id);
> +	munmap(data, bo_size);
> +	gem_close(fd, bo);
> +	xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> +	const struct section {
> +		const char *name;
> +		unsigned int flags;
> +	} sections[] = {
> +		{ "invalid-va", 0 },
> +		{ "invalid-va-scratch", DRM_XE_VM_CREATE_SCRATCH_PAGE },
> +		{ "invalid-va-fault", DRM_XE_VM_CREATE_FAULT_MODE },
> +		{ "invalid-va-fault-scratch", DRM_XE_VM_CREATE_FAULT_MODE |
> +					      DRM_XE_VM_CREATE_SCRATCH_PAGE },
> +		{ NULL },
> +	};
> +	int fd;
> +
> +	igt_fixture {
> +		fd = drm_open_driver(DRIVER_XE);
> +		igt_require(xe_supports_faults(fd));
> +	}
> +
> +	for (const struct section *s = sections; s->name; s++) {
> +		igt_subtest_f("%s", s->name)
> +			test_exec(fd, s->flags);
> +	}
> +
> +	igt_fixture
> +		drm_close_driver(fd);
> +}
> +
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[Chang, Yu bruce]

> -----Original Message-----
> From: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Sent: Friday, September 1, 2023 5:16 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Chang, Yu bruce <yu.bruce.chang@intel.com>; Zeng, Oak
> <oak.zeng@intel.com>; Welty, Brian <brian.welty@intel.com>
> Subject: Re: [igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests
> 
> Hi Bruce,
> 
> On 2023-08-31 at 23:46:54 +0000, Chang, Bruce wrote:
> > add the following invalid va access test cases:
> >
> > 	gpu fault	scratch page	command timeout
> > 1) 	no		no		yes
> > 2) 	no		yes		no
> > 3) 	yes		no		yes
> > 4) 	yes		yes		no
> >
> > TODO: with futher improvement of xe_wait_ufence, the test can check
> > more specific error code from it.
> >
> > v2: async vm/bind, and re-bind valid address
> > v3: added xe_wait_ufence check
> >
> > Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com>
> > Cc: Oak Zeng <oak.zeng@intel.com>
> > Cc: Brian Welty <brian.welty@intel.com>
> > Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> > Cc: Matthew Brost <matthew.brost@intel.com>
> > ---
> >  lib/xe/xe_ioctl.c             |  15 +++-
> >  lib/xe/xe_ioctl.h             |   3 +
> >  tests/meson.build             |   1 +
> >  tests/xe/xe_exec_invalid_va.c | 164
> > ++++++++++++++++++++++++++++++++++
> 
> Why not placing this in xe_vm.c as a subtest? We have too much xe_exec tests.
> Or use other name like xe_vm_invalid.
>

xe_vm_invalid makes sense to me since this is really testing vm feature.
 
> >  4 files changed, 180 insertions(+), 3 deletions(-)  create mode
> > 100644 tests/xe/xe_exec_invalid_va.c
> >
> > diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c index
> > 730dcfd16..022f0cf04 100644
> > --- a/lib/xe/xe_ioctl.c
> > +++ b/lib/xe/xe_ioctl.c
> > @@ -415,9 +415,9 @@ void xe_exec_wait(int fd, uint32_t exec_queue,
> uint64_t addr)
> >  	syncobj_destroy(fd, sync.handle);
> >  }
> >
> > -int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> > +int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> >  		       struct drm_xe_engine_class_instance *eci,
> > -		       int64_t timeout)
> > +		       int64_t timeout, bool timeout_assert)
> ------------------------------- ^
> Do not instroduce a bool parameter, rather make __function which will return
> errno in case of ioctl error, so later you may use it like:
>         ret = __xe_wait_ufence(..., &val);
>         igt_assert_f(!ret || ret == -ETIME, "error %d\n", ret);
> 
Agree, was just following the original function convention. I can make this change.

> 
> int __xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> 		       struct drm_xe_engine_class_instance *eci,
> 		       int64_t timeout)
> 		       int64_t timeout,
>                int64_t *retval)
> {
>         ...
>         ret = igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait);
>         if (!ret)
>                 *retval = wait.timeout;
> 
>         return ret;
> }
> 
> uint64_t xe_wait_ufence(...)
> {
>         uint64_t val;
> 
>         igt_assert_eq(__xe_wait_ufence(..., &val), 0);
> 
>         return val;
> }
> 
> Add description to each new/old library function you re/write.
> 
Sure.

> >  {
> >  	struct drm_xe_wait_user_fence wait = {
> >  		.addr = to_user_pointer(addr),
> > @@ -430,11 +430,20 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr,
> uint64_t value,
> >  		.instances = eci ? to_user_pointer(eci) : 0,
> >  	};
> >
> > -	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE,
> &wait), 0);
> > +	if (igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait))
> > +		igt_assert (!timeout_assert && errno == ETIME);
> >
> >  	return wait.timeout;
> >  }
> >
> > +
> > +int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> > +		       struct drm_xe_engine_class_instance *eci,
> > +		       int64_t timeout)
> > +{
> > +	return _xe_wait_ufence(fd, addr, value, eci, timeout, true); }
> > +
> >  /**
> >   * xe_wait_ufence_abstime:
> >   * @fd: xe device fd
> > diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h index
> > 6c281b3bf..4bf7410a4 100644
> > --- a/lib/xe/xe_ioctl.h
> > +++ b/lib/xe/xe_ioctl.h
> > @@ -82,6 +82,9 @@ void xe_exec(int fd, struct drm_xe_exec *exec);
> > void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr,
> >  		  struct drm_xe_sync *sync, uint32_t num_syncs);  void
> > xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr);
> > +int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> > +		       struct drm_xe_engine_class_instance *eci,
> > +		       int64_t timeout, bool timeout_assert);
> >  int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> >  		       struct drm_xe_engine_class_instance *eci,
> >  		       int64_t timeout);
> > diff --git a/tests/meson.build b/tests/meson.build index
> > 4d325bed1..8861b6c5b 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -276,6 +276,7 @@ xe_progs = [
> >  	'xe_exec_reset',
> >  	'xe_exec_store',
> >  	'xe_exec_threads',
> > +	'xe_exec_invalid_va',
> >  	'xe_exercise_blt',
> >  	'xe_gpgpu_fill',
> >  	'xe_guc_pc',
> > diff --git a/tests/xe/xe_exec_invalid_va.c
> > b/tests/xe/xe_exec_invalid_va.c new file mode 100644 index
> > 000000000..468b90c8a
> > --- /dev/null
> > +++ b/tests/xe/xe_exec_invalid_va.c
> > @@ -0,0 +1,164 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2023 Intel Corporation  */
> > +
> > +/**
> > + * TEST: invalid va tests
> > + * Category: Hardware building block
> > + * Sub-category: execbuf
> > + * Functionality: fault mode
> > + * Test category: functionality test
> > + * GPU requirements: GPU needs support for
> > +DRM_XE_VM_CREATE_FAULT_MODE  */
> > +
> > +#include <fcntl.h>
> > +
> > +#include "igt.h"
> > +#include "lib/igt_syncobj.h"
> > +#include "lib/intel_reg.h"
> > +#include "xe_drm.h"
> > +
> > +#include "xe/xe_ioctl.h"
> > +#include "xe/xe_query.h"
> > +#include <string.h>
> ----------- ^
> Move above after <fcntl.h>
> 

Will do.

> > +
> > +static void insert_store(uint32_t *bb, uint64_t va, uint64_t data) {
> > +	*bb++ = MI_STORE_DWORD_IMM_GEN4;
> > +	*bb++ = lower_32_bits(va);
> > +	*bb++ = upper_32_bits(va);
> > +	*bb++ = data;
> > +	*bb++ = MI_BATCH_BUFFER_END;
> > +}
> > +
> > +/**
> > + * SUBTEST: invalid-va
> > + * Description: Check driver handling of invalid va access
> > + * Run type: FULL
> > + *
> > + * SUBTEST: invalid-va-scratch
> > + * Description: Check driver handling of invalid va access with
> > +scratch page
> > + * Run type: FULL
> > + *
> > + * SUBTEST: invalid-va-fault
> > + * Description: Check driver handling of invalid va access with fault
> > +enabled
> > + * Run type: FULL
> > + *
> > + * SUBTEST: invalid-va-fault-scratch
> > + * Description: Check driver handling of invalid va access with fault
> > ++ scratch page
> > + * Run type: FULL
> > + *
> > + * arg[1]: for vm create flags
> > + */
> > +static void test_exec(int fd, uint32_t flags) {
> > +	const uint64_t inv_addr = 0x20000000;
> > +	const uint64_t addr = 0x1a0000;
> > +#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
> ------------------------------^
> imho better in uppercase
> 
> > +#define ONE_SEC			MS_TO_NS(1000)
> > +#define	STORE_DATA		0xDEADBEAF
> ----------------------------- ^
> Inconsistent, use either upper or lower case.
> 

Sure, will use upper case for both case.
Thanks,
Bruce

> Regards,
> Kamil

[igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[Chang, Bruce]

add the following invalid va access test cases:

	gpu fault	scrach page
1) 	no		no
2) 	no		yes
3) 	yes		no
4) 	yes		yes

v2: async vm/bind, and re-bind valid addres

Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 lib/xe/xe_ioctl.c             |  15 +++-
 lib/xe/xe_ioctl.h             |   3 +
 tests/meson.build             |   1 +
 tests/xe/xe_exec_invalid_va.c | 160 ++++++++++++++++++++++++++++++++++
 4 files changed, 176 insertions(+), 3 deletions(-)
 create mode 100644 tests/xe/xe_exec_invalid_va.c

diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 730dcfd16..022f0cf04 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -415,9 +415,9 @@ void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr)
 	syncobj_destroy(fd, sync.handle);
 }
 
-int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
+int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
 		       struct drm_xe_engine_class_instance *eci,
-		       int64_t timeout)
+		       int64_t timeout, bool timeout_assert)
 {
 	struct drm_xe_wait_user_fence wait = {
 		.addr = to_user_pointer(addr),
@@ -430,11 +430,20 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
 		.instances = eci ? to_user_pointer(eci) : 0,
 	};
 
-	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0);
+	if (igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait))
+		igt_assert (!timeout_assert && errno == ETIME);
 
 	return wait.timeout;
 }
 
+
+int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
+		       struct drm_xe_engine_class_instance *eci,
+		       int64_t timeout)
+{
+	return _xe_wait_ufence(fd, addr, value, eci, timeout, true);
+}
+
 /**
  * xe_wait_ufence_abstime:
  * @fd: xe device fd
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index 6c281b3bf..4bf7410a4 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -82,6 +82,9 @@ void xe_exec(int fd, struct drm_xe_exec *exec);
 void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr,
 		  struct drm_xe_sync *sync, uint32_t num_syncs);
 void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr);
+int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
+		       struct drm_xe_engine_class_instance *eci,
+		       int64_t timeout, bool timeout_assert);
 int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
 		       struct drm_xe_engine_class_instance *eci,
 		       int64_t timeout);
diff --git a/tests/meson.build b/tests/meson.build
index 4d325bed1..8861b6c5b 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -276,6 +276,7 @@ xe_progs = [
 	'xe_exec_reset',
 	'xe_exec_store',
 	'xe_exec_threads',
+	'xe_exec_invalid_va',
 	'xe_exercise_blt',
 	'xe_gpgpu_fill',
 	'xe_guc_pc',
diff --git a/tests/xe/xe_exec_invalid_va.c b/tests/xe/xe_exec_invalid_va.c
new file mode 100644
index 000000000..974672e75
--- /dev/null
+++ b/tests/xe/xe_exec_invalid_va.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+/**
+ * TEST: invalid va tests
+ * Category: Hardware building block
+ * Sub-category: execbuf
+ * Functionality: fault mode
+ * Test category: functionality test
+ * GPU requirements: GPU needs support for DRM_XE_VM_CREATE_FAULT_MODE
+ */
+
+#include <fcntl.h>
+
+#include "igt.h"
+#include "lib/igt_syncobj.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include <string.h>
+
+static void insert_store(uint32_t *bb, uint64_t va, uint64_t data)
+{
+	*bb++ = MI_STORE_DWORD_IMM_GEN4;
+	*bb++ = lower_32_bits(va);
+	*bb++ = upper_32_bits(va);
+	*bb++ = data;
+	*bb++ = MI_BATCH_BUFFER_END;
+}
+
+/**
+ * SUBTEST: invalid-va
+ * Description: Check driver handling of invalid va access
+ * Run type: FULL
+ *
+ * SUBTEST: invalid-va-scratch
+ * Description: Check driver handling of invalid va access with scratch page
+ * Run type: FULL
+ *
+ * SUBTEST: invalid-va-fault
+ * Description: Check driver handling of invalid va access with fault enabled
+ * Run type: FULL
+ *
+ * SUBTEST: invalid-va-fault-scratch
+ * Description: Check driver handling of invalid va access with fault + scratch page
+ * Run type: FULL
+ *
+ * arg[1]: for vm create flags
+ */
+static void test_exec(int fd, uint32_t flags)
+{
+	const uint64_t inv_addr = 0x20000000;
+	const uint64_t addr = 0x1a0000;
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+#define ONE_SEC			MS_TO_NS(1000)
+#define	STORE_DATA		0xDEADBEAF
+	struct _data {
+		uint32_t batch[16];
+		uint64_t vm_sync;
+		uint64_t sync;
+		uint64_t data;
+	} *data;
+	struct drm_xe_sync sync = {
+		.flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+		.timeline_value = USER_FENCE_VALUE,
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.address = addr,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&sync),
+	};
+	uint32_t vm;
+	uint32_t bo;
+	size_t bo_size;
+	struct drm_xe_engine_class_instance *eci;
+
+	eci = xe_hw_engine(fd, 0);
+	vm = xe_vm_create(fd, flags | DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+	bo_size = ALIGN(sizeof(*data), xe_get_default_alignment(fd));
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				all_memory_regions(fd) |
+				visible_vram_if_possible(fd, 0));
+	data = xe_bo_map(fd, bo, bo_size);
+	memset(data, 0, bo_size);
+
+	insert_store(data->batch, inv_addr + offsetof(struct _data, data), STORE_DATA);
+	exec.exec_queue_id = xe_exec_queue_create(fd, vm, eci, 0);
+	sync.addr = to_user_pointer(&data->vm_sync);
+	xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
+				addr, bo_size, &sync, 1,
+				XE_VM_BIND_FLAG_IMMEDIATE);
+	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+	data->vm_sync = 0;
+	sync.addr = addr + offsetof(struct _data, sync);
+	xe_exec(fd, &exec);
+        _xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC, false);
+	data->sync = 0;
+
+	if ((flags & DRM_XE_VM_CREATE_FAULT_MODE) &&
+	    (flags & DRM_XE_VM_CREATE_SCRATCH_PAGE)) {
+		/* bind inv_addr after scratch page was created */
+		sync.addr = to_user_pointer(&data->vm_sync);
+		xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
+				inv_addr, bo_size, &sync, 1,
+				XE_VM_BIND_FLAG_IMMEDIATE);
+		xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+		data->vm_sync = 0;
+		data->data = 0;
+		sync.addr = addr + offsetof(struct _data, sync);
+		xe_exec(fd, &exec);
+		xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+		igt_assert_eq(data->data, STORE_DATA);
+	}
+
+	sync.addr = to_user_pointer(&data->vm_sync);
+	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
+	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+	data->vm_sync = 0;
+	xe_vm_unbind_async(fd, vm, 0, 0, inv_addr, bo_size, &sync, 1);
+	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
+	xe_exec_queue_destroy(fd, exec.exec_queue_id);
+	munmap(data, bo_size);
+	gem_close(fd, bo);
+	xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+	const struct section {
+		const char *name;
+		unsigned int flags;
+	} sections[] = {
+		{ "invalid-va", 0 },
+		{ "invalid-va-scratch", DRM_XE_VM_CREATE_SCRATCH_PAGE },
+		{ "invalid-va-fault", DRM_XE_VM_CREATE_FAULT_MODE },
+		{ "invalid-va-fault-scratch", DRM_XE_VM_CREATE_FAULT_MODE |
+					      DRM_XE_VM_CREATE_SCRATCH_PAGE },
+		{ NULL },
+	};
+	int fd;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_XE);
+		igt_require(xe_supports_faults(fd));
+	}
+
+	for (const struct section *s = sections; s->name; s++) {
+		igt_subtest_f("%s", s->name)
+			test_exec(fd, s->flags);
+	}
+
+	igt_fixture
+		drm_close_driver(fd);
+}
+
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[Welty, Brian]

On 8/29/2023 4:05 PM, Chang, Bruce wrote:
> add the following invalid va access test cases:
> 
> 	gpu fault	scrach page
> 1) 	no		no
> 2) 	no		yes
> 3) 	yes		no
> 4) 	yes		yes

Can you elaborate... the expected outcome after xe_exec encounters the 
bad address?


> 
> v2: async vm/bind, and re-bind valid addres

A couple typos above.   'addres', 'scrach'.

> 
> Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com>
> Cc: Oak Zeng <oak.zeng@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> ---
>   lib/xe/xe_ioctl.c             |  15 +++-
>   lib/xe/xe_ioctl.h             |   3 +
>   tests/meson.build             |   1 +
>   tests/xe/xe_exec_invalid_va.c | 160 ++++++++++++++++++++++++++++++++++
>   4 files changed, 176 insertions(+), 3 deletions(-)
>   create mode 100644 tests/xe/xe_exec_invalid_va.c
> 
> diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
> index 730dcfd16..022f0cf04 100644
> --- a/lib/xe/xe_ioctl.c
> +++ b/lib/xe/xe_ioctl.c
> @@ -415,9 +415,9 @@ void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr)
>   	syncobj_destroy(fd, sync.handle);
>   }
>   
> -int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> +int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
>   		       struct drm_xe_engine_class_instance *eci,
> -		       int64_t timeout)
> +		       int64_t timeout, bool timeout_assert)
>   {
>   	struct drm_xe_wait_user_fence wait = {
>   		.addr = to_user_pointer(addr),
> @@ -430,11 +430,20 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
>   		.instances = eci ? to_user_pointer(eci) : 0,
>   	};
>   
> -	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0);
> +	if (igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait))
> +		igt_assert (!timeout_assert && errno == ETIME);
>   
>   	return wait.timeout;
>   }
>   
> +
> +int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> +		       struct drm_xe_engine_class_instance *eci,
> +		       int64_t timeout)
> +{
> +	return _xe_wait_ufence(fd, addr, value, eci, timeout, true);
> +}
> +
>   /**
>    * xe_wait_ufence_abstime:
>    * @fd: xe device fd
> diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
> index 6c281b3bf..4bf7410a4 100644
> --- a/lib/xe/xe_ioctl.h
> +++ b/lib/xe/xe_ioctl.h
> @@ -82,6 +82,9 @@ void xe_exec(int fd, struct drm_xe_exec *exec);
>   void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr,
>   		  struct drm_xe_sync *sync, uint32_t num_syncs);
>   void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr);
> +int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> +		       struct drm_xe_engine_class_instance *eci,
> +		       int64_t timeout, bool timeout_assert);
>   int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
>   		       struct drm_xe_engine_class_instance *eci,
>   		       int64_t timeout);
> diff --git a/tests/meson.build b/tests/meson.build
> index 4d325bed1..8861b6c5b 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -276,6 +276,7 @@ xe_progs = [
>   	'xe_exec_reset',
>   	'xe_exec_store',
>   	'xe_exec_threads',
> +	'xe_exec_invalid_va',
>   	'xe_exercise_blt',
>   	'xe_gpgpu_fill',
>   	'xe_guc_pc',
> diff --git a/tests/xe/xe_exec_invalid_va.c b/tests/xe/xe_exec_invalid_va.c
> new file mode 100644
> index 000000000..974672e75
> --- /dev/null
> +++ b/tests/xe/xe_exec_invalid_va.c
> @@ -0,0 +1,160 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +/**
> + * TEST: invalid va tests
> + * Category: Hardware building block
> + * Sub-category: execbuf
> + * Functionality: fault mode
> + * Test category: functionality test
> + * GPU requirements: GPU needs support for DRM_XE_VM_CREATE_FAULT_MODE
> + */
> +
> +#include <fcntl.h>
> +
> +#include "igt.h"
> +#include "lib/igt_syncobj.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include <string.h>
> +
> +static void insert_store(uint32_t *bb, uint64_t va, uint64_t data)
> +{
> +	*bb++ = MI_STORE_DWORD_IMM_GEN4;
> +	*bb++ = lower_32_bits(va);
> +	*bb++ = upper_32_bits(va);
> +	*bb++ = data;
> +	*bb++ = MI_BATCH_BUFFER_END;
> +}
> +
> +/**
> + * SUBTEST: invalid-va
> + * Description: Check driver handling of invalid va access
> + * Run type: FULL
> + *
> + * SUBTEST: invalid-va-scratch
> + * Description: Check driver handling of invalid va access with scratch page
> + * Run type: FULL
> + *
> + * SUBTEST: invalid-va-fault
> + * Description: Check driver handling of invalid va access with fault enabled
> + * Run type: FULL
> + *
> + * SUBTEST: invalid-va-fault-scratch
> + * Description: Check driver handling of invalid va access with fault + scratch page
> + * Run type: FULL
> + *
> + * arg[1]: for vm create flags
> + */
> +static void test_exec(int fd, uint32_t flags)
> +{
> +	const uint64_t inv_addr = 0x20000000;
> +	const uint64_t addr = 0x1a0000;
> +#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
> +#define ONE_SEC			MS_TO_NS(1000)
> +#define	STORE_DATA		0xDEADBEAF
> +	struct _data {
> +		uint32_t batch[16];
> +		uint64_t vm_sync;
> +		uint64_t sync;
> +		uint64_t data;
> +	} *data;
> +	struct drm_xe_sync sync = {
> +		.flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
> +		.timeline_value = USER_FENCE_VALUE,
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.address = addr,
> +		.num_syncs = 1,
> +		.syncs = to_user_pointer(&sync),
> +	};
> +	uint32_t vm;
> +	uint32_t bo;
> +	size_t bo_size;
> +	struct drm_xe_engine_class_instance *eci;
> +
> +	eci = xe_hw_engine(fd, 0);
> +	vm = xe_vm_create(fd, flags | DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> +	bo_size = ALIGN(sizeof(*data), xe_get_default_alignment(fd));
> +	bo = xe_bo_create_flags(fd, vm, bo_size,
> +				all_memory_regions(fd) |
> +				visible_vram_if_possible(fd, 0));
> +	data = xe_bo_map(fd, bo, bo_size);
> +	memset(data, 0, bo_size);
> +
> +	insert_store(data->batch, inv_addr + offsetof(struct _data, data), STORE_DATA);
> +	exec.exec_queue_id = xe_exec_queue_create(fd, vm, eci, 0);
> +	sync.addr = to_user_pointer(&data->vm_sync);
> +	xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
> +				addr, bo_size, &sync, 1,
> +				XE_VM_BIND_FLAG_IMMEDIATE);

I guess the vm_bind isn't really needed as addr isn't used?
But on other hand, seems this is more like what a buggy application 
would be doing.

> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +	data->vm_sync = 0;
> +	sync.addr = addr + offsetof(struct _data, sync);
> +	xe_exec(fd, &exec);
> +        _xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC, false);

Indentation seems extra above.

> +	data->sync = 0;

Do we need some verification here that driver did proper thing when 
encountering invalid va.  Meaning there was some different behavior with 
scratch page we can observe?
Without DRM_XE_VM_CREATE_SCRATCH_PAGE, program is terminated?  Are we 
banning the context like i915 was doing?

> +
> +	if ((flags & DRM_XE_VM_CREATE_FAULT_MODE) &&
> +	    (flags & DRM_XE_VM_CREATE_SCRATCH_PAGE)) {
> +		/* bind inv_addr after scratch page was created */
> +		sync.addr = to_user_pointer(&data->vm_sync);
> +		xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
> +				inv_addr, bo_size, &sync, 1,
> +				XE_VM_BIND_FLAG_IMMEDIATE);
> +		xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +		data->vm_sync = 0;
> +		data->data = 0;
> +		sync.addr = addr + offsetof(struct _data, sync);
> +		xe_exec(fd, &exec);
> +		xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +		igt_assert_eq(data->data, STORE_DATA);
> +	}
> +
> +	sync.addr = to_user_pointer(&data->vm_sync);
> +	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +	data->vm_sync = 0;
> +	xe_vm_unbind_async(fd, vm, 0, 0, inv_addr, bo_size, &sync, 1);
> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC);
> +	xe_exec_queue_destroy(fd, exec.exec_queue_id);
> +	munmap(data, bo_size);
> +	gem_close(fd, bo);
> +	xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> +	const struct section {
> +		const char *name;
> +		unsigned int flags;
> +	} sections[] = {
> +		{ "invalid-va", 0 },
> +		{ "invalid-va-scratch", DRM_XE_VM_CREATE_SCRATCH_PAGE },
> +		{ "invalid-va-fault", DRM_XE_VM_CREATE_FAULT_MODE },
> +		{ "invalid-va-fault-scratch", DRM_XE_VM_CREATE_FAULT_MODE |
> +					      DRM_XE_VM_CREATE_SCRATCH_PAGE },
> +		{ NULL },
> +	};
> +	int fd;
> +
> +	igt_fixture {
> +		fd = drm_open_driver(DRIVER_XE);
> +		igt_require(xe_supports_faults(fd));
> +	}
> +
> +	for (const struct section *s = sections; s->name; s++) {
> +		igt_subtest_f("%s", s->name)
> +			test_exec(fd, s->flags);
> +	}
> +
> +	igt_fixture
> +		drm_close_driver(fd);
> +}
> +

Re: [igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[Chang, Yu bruce]

> -----Original Message-----
> From: Welty, Brian <brian.welty@intel.com>
> Sent: Wednesday, August 30, 2023 3:57 PM
> To: Chang, Yu bruce <yu.bruce.chang@intel.com>; igt-
> dev@lists.freedesktop.org
> Cc: Zeng, Oak <oak.zeng@intel.com>; Vishwanathapura, Niranjana
> <niranjana.vishwanathapura@intel.com>; Brost, Matthew
> <matthew.brost@intel.com>
> Subject: Re: [PATCH i-g-t] tests/xe add invalid va access tests
> 
> 
> 
> On 8/29/2023 4:05 PM, Chang, Bruce wrote:
> > add the following invalid va access test cases:
> >
> > 	gpu fault	scrach page
> > 1) 	no		no
> > 2) 	no		yes
> > 3) 	yes		no
> > 4) 	yes		yes
> 
> Can you elaborate... the expected outcome after xe_exec encounters the
> bad address?
>

Without scratch page, the command will encounter a failure and hence a reset
Like below

[82208.343150] xe 0000:8c:00.0: [drm] Engine reset: guc_id=2

With scratch page, depending on the commands, for this particular igt, the failure
will be hidden and the test will just run fine.

I will add one column to indicate the expected results. 
> 
> >
> > v2: async vm/bind, and re-bind valid addres
> 
> A couple typos above.   'addres', 'scrach'.
>
will fix
 
> >
> > Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com>
> > Cc: Oak Zeng <oak.zeng@intel.com>
> > Cc: Brian Welty <brian.welty@intel.com>
> > Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> > Cc: Matthew Brost <matthew.brost@intel.com>
> > ---
> >   lib/xe/xe_ioctl.c             |  15 +++-
> >   lib/xe/xe_ioctl.h             |   3 +
> >   tests/meson.build             |   1 +
> >   tests/xe/xe_exec_invalid_va.c | 160
> ++++++++++++++++++++++++++++++++++
> >   4 files changed, 176 insertions(+), 3 deletions(-)
> >   create mode 100644 tests/xe/xe_exec_invalid_va.c
> >
> > diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
> > index 730dcfd16..022f0cf04 100644
> > --- a/lib/xe/xe_ioctl.c
> > +++ b/lib/xe/xe_ioctl.c
> > @@ -415,9 +415,9 @@ void xe_exec_wait(int fd, uint32_t exec_queue,
> uint64_t addr)
> >   	syncobj_destroy(fd, sync.handle);
> >   }
> >
> > -int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> > +int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> >   		       struct drm_xe_engine_class_instance *eci,
> > -		       int64_t timeout)
> > +		       int64_t timeout, bool timeout_assert)
> >   {
> >   	struct drm_xe_wait_user_fence wait = {
> >   		.addr = to_user_pointer(addr),
> > @@ -430,11 +430,20 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr,
> uint64_t value,
> >   		.instances = eci ? to_user_pointer(eci) : 0,
> >   	};
> >
> > -	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE,
> &wait), 0);
> > +	if (igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait))
> > +		igt_assert (!timeout_assert && errno == ETIME);
> >
> >   	return wait.timeout;
> >   }
> >
> > +
> > +int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> > +		       struct drm_xe_engine_class_instance *eci,
> > +		       int64_t timeout)
> > +{
> > +	return _xe_wait_ufence(fd, addr, value, eci, timeout, true);
> > +}
> > +
> >   /**
> >    * xe_wait_ufence_abstime:
> >    * @fd: xe device fd
> > diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
> > index 6c281b3bf..4bf7410a4 100644
> > --- a/lib/xe/xe_ioctl.h
> > +++ b/lib/xe/xe_ioctl.h
> > @@ -82,6 +82,9 @@ void xe_exec(int fd, struct drm_xe_exec *exec);
> >   void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr,
> >   		  struct drm_xe_sync *sync, uint32_t num_syncs);
> >   void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr);
> > +int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> > +		       struct drm_xe_engine_class_instance *eci,
> > +		       int64_t timeout, bool timeout_assert);
> >   int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
> >   		       struct drm_xe_engine_class_instance *eci,
> >   		       int64_t timeout);
> > diff --git a/tests/meson.build b/tests/meson.build
> > index 4d325bed1..8861b6c5b 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -276,6 +276,7 @@ xe_progs = [
> >   	'xe_exec_reset',
> >   	'xe_exec_store',
> >   	'xe_exec_threads',
> > +	'xe_exec_invalid_va',
> >   	'xe_exercise_blt',
> >   	'xe_gpgpu_fill',
> >   	'xe_guc_pc',
> > diff --git a/tests/xe/xe_exec_invalid_va.c b/tests/xe/xe_exec_invalid_va.c
> > new file mode 100644
> > index 000000000..974672e75
> > --- /dev/null
> > +++ b/tests/xe/xe_exec_invalid_va.c
> > @@ -0,0 +1,160 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2023 Intel Corporation
> > + */
> > +
> > +/**
> > + * TEST: invalid va tests
> > + * Category: Hardware building block
> > + * Sub-category: execbuf
> > + * Functionality: fault mode
> > + * Test category: functionality test
> > + * GPU requirements: GPU needs support for
> DRM_XE_VM_CREATE_FAULT_MODE
> > + */
> > +
> > +#include <fcntl.h>
> > +
> > +#include "igt.h"
> > +#include "lib/igt_syncobj.h"
> > +#include "lib/intel_reg.h"
> > +#include "xe_drm.h"
> > +
> > +#include "xe/xe_ioctl.h"
> > +#include "xe/xe_query.h"
> > +#include <string.h>
> > +
> > +static void insert_store(uint32_t *bb, uint64_t va, uint64_t data)
> > +{
> > +	*bb++ = MI_STORE_DWORD_IMM_GEN4;
> > +	*bb++ = lower_32_bits(va);
> > +	*bb++ = upper_32_bits(va);
> > +	*bb++ = data;
> > +	*bb++ = MI_BATCH_BUFFER_END;
> > +}
> > +
> > +/**
> > + * SUBTEST: invalid-va
> > + * Description: Check driver handling of invalid va access
> > + * Run type: FULL
> > + *
> > + * SUBTEST: invalid-va-scratch
> > + * Description: Check driver handling of invalid va access with scratch page
> > + * Run type: FULL
> > + *
> > + * SUBTEST: invalid-va-fault
> > + * Description: Check driver handling of invalid va access with fault enabled
> > + * Run type: FULL
> > + *
> > + * SUBTEST: invalid-va-fault-scratch
> > + * Description: Check driver handling of invalid va access with fault + scratch
> page
> > + * Run type: FULL
> > + *
> > + * arg[1]: for vm create flags
> > + */
> > +static void test_exec(int fd, uint32_t flags)
> > +{
> > +	const uint64_t inv_addr = 0x20000000;
> > +	const uint64_t addr = 0x1a0000;
> > +#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
> > +#define ONE_SEC			MS_TO_NS(1000)
> > +#define	STORE_DATA		0xDEADBEAF
> > +	struct _data {
> > +		uint32_t batch[16];
> > +		uint64_t vm_sync;
> > +		uint64_t sync;
> > +		uint64_t data;
> > +	} *data;
> > +	struct drm_xe_sync sync = {
> > +		.flags = DRM_XE_SYNC_USER_FENCE |
> DRM_XE_SYNC_SIGNAL,
> > +		.timeline_value = USER_FENCE_VALUE,
> > +	};
> > +	struct drm_xe_exec exec = {
> > +		.num_batch_buffer = 1,
> > +		.address = addr,
> > +		.num_syncs = 1,
> > +		.syncs = to_user_pointer(&sync),
> > +	};
> > +	uint32_t vm;
> > +	uint32_t bo;
> > +	size_t bo_size;
> > +	struct drm_xe_engine_class_instance *eci;
> > +
> > +	eci = xe_hw_engine(fd, 0);
> > +	vm = xe_vm_create(fd, flags |
> DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> > +	bo_size = ALIGN(sizeof(*data), xe_get_default_alignment(fd));
> > +	bo = xe_bo_create_flags(fd, vm, bo_size,
> > +				all_memory_regions(fd) |
> > +				visible_vram_if_possible(fd, 0));
> > +	data = xe_bo_map(fd, bo, bo_size);
> > +	memset(data, 0, bo_size);
> > +
> > +	insert_store(data->batch, inv_addr + offsetof(struct _data, data),
> STORE_DATA);
> > +	exec.exec_queue_id = xe_exec_queue_create(fd, vm, eci, 0);
> > +	sync.addr = to_user_pointer(&data->vm_sync);
> > +	xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
> > +				addr, bo_size, &sync, 1,
> > +				XE_VM_BIND_FLAG_IMMEDIATE);
> 
> I guess the vm_bind isn't really needed as addr isn't used?
> But on other hand, seems this is more like what a buggy application
> would be doing.
> 

addr is actually used for the command itself, and also for sync object as well.

> > +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL,
> ONE_SEC);
> > +	data->vm_sync = 0;
> > +	sync.addr = addr + offsetof(struct _data, sync);
> > +	xe_exec(fd, &exec);
> > +        _xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL,
> ONE_SEC, false);
> 
> Indentation seems extra above.
> 

Yes, space issue, will fix

> > +	data->sync = 0;
> 
> Do we need some verification here that driver did proper thing when
> encountering invalid va.  Meaning there was some different behavior with
> scratch page we can observe?
> Without DRM_XE_VM_CREATE_SCRATCH_PAGE, program is terminated?  Are
> we
> banning the context like i915 was doing?
>

Good point, now is a manual check for the log for a reset message, I can look into
To automate it.

Thanks,
Bruce

> > +
> > +	if ((flags & DRM_XE_VM_CREATE_FAULT_MODE) &&
> > +	    (flags & DRM_XE_VM_CREATE_SCRATCH_PAGE)) {
> > +		/* bind inv_addr after scratch page was created */
> > +		sync.addr = to_user_pointer(&data->vm_sync);
> > +		xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
> > +				inv_addr, bo_size, &sync, 1,
> > +				XE_VM_BIND_FLAG_IMMEDIATE);
> > +		xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE,
> NULL, ONE_SEC);
> > +		data->vm_sync = 0;
> > +		data->data = 0;
> > +		sync.addr = addr + offsetof(struct _data, sync);
> > +		xe_exec(fd, &exec);
> > +		xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL,
> ONE_SEC);
> > +		igt_assert_eq(data->data, STORE_DATA);
> > +	}
> > +
> > +	sync.addr = to_user_pointer(&data->vm_sync);
> > +	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
> > +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL,
> ONE_SEC);
> > +	data->vm_sync = 0;
> > +	xe_vm_unbind_async(fd, vm, 0, 0, inv_addr, bo_size, &sync, 1);
> > +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL,
> ONE_SEC);
> > +	xe_exec_queue_destroy(fd, exec.exec_queue_id);
> > +	munmap(data, bo_size);
> > +	gem_close(fd, bo);
> > +	xe_vm_destroy(fd, vm);
> > +}
> > +
> > +igt_main
> > +{
> > +	const struct section {
> > +		const char *name;
> > +		unsigned int flags;
> > +	} sections[] = {
> > +		{ "invalid-va", 0 },
> > +		{ "invalid-va-scratch", DRM_XE_VM_CREATE_SCRATCH_PAGE
> },
> > +		{ "invalid-va-fault", DRM_XE_VM_CREATE_FAULT_MODE },
> > +		{ "invalid-va-fault-scratch",
> DRM_XE_VM_CREATE_FAULT_MODE |
> > +
> DRM_XE_VM_CREATE_SCRATCH_PAGE },
> > +		{ NULL },
> > +	};
> > +	int fd;
> > +
> > +	igt_fixture {
> > +		fd = drm_open_driver(DRIVER_XE);
> > +		igt_require(xe_supports_faults(fd));
> > +	}
> > +
> > +	for (const struct section *s = sections; s->name; s++) {
> > +		igt_subtest_f("%s", s->name)
> > +			test_exec(fd, s->flags);
> > +	}
> > +
> > +	igt_fixture
> > +		drm_close_driver(fd);
> > +}
> > +

Re: [igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[Welty, Brian]

On 8/30/2023 5:26 PM, Chang, Yu bruce wrote:
> 
> 
...
>>
>> Do we need some verification here that driver did proper thing when
>> encountering invalid va.  Meaning there was some different behavior with
>> scratch page we can observe?
>> Without DRM_XE_VM_CREATE_SCRATCH_PAGE, program is terminated?  Are
>> we
>> banning the context like i915 was doing?
>>
> 
> Good point, now is a manual check for the log for a reset message, I can look into
> To automate it.
> 

Isn't the xe_wait_ufence() supposed to somehow inform that something 
actually failed with the xe_exec?
I notice you are using _xe_wait_ufence instead of xe_wait_ufence().
It gives an error?

You mentioned that the engine was reset....  was is the effect of that?
Maybe a subsequent xe_exec() will fail?   Just grasping at some 
user-space visible things you can try easily.  I don't know myself, new 
code...

-Brian


> Thanks,
> Bruce
> 
>>> +
>>> +	if ((flags & DRM_XE_VM_CREATE_FAULT_MODE) &&
>>> +	    (flags & DRM_XE_VM_CREATE_SCRATCH_PAGE)) {
>>> +		/* bind inv_addr after scratch page was created */
>>> +		sync.addr = to_user_pointer(&data->vm_sync);
>>> +		xe_vm_bind_async_flags(fd, vm, 0, bo, 0,
>>> +				inv_addr, bo_size, &sync, 1,
>>> +				XE_VM_BIND_FLAG_IMMEDIATE);
>>> +		xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE,
>> NULL, ONE_SEC);
>>> +		data->vm_sync = 0;
>>> +		data->data = 0;
>>> +		sync.addr = addr + offsetof(struct _data, sync);
>>> +		xe_exec(fd, &exec);
>>> +		xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL,
>> ONE_SEC);
>>> +		igt_assert_eq(data->data, STORE_DATA);
>>> +	}
>>> +
>>> +	sync.addr = to_user_pointer(&data->vm_sync);
>>> +	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
>>> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL,
>> ONE_SEC);
>>> +	data->vm_sync = 0;
>>> +	xe_vm_unbind_async(fd, vm, 0, 0, inv_addr, bo_size, &sync, 1);
>>> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, NULL,
>> ONE_SEC);
>>> +	xe_exec_queue_destroy(fd, exec.exec_queue_id);
>>> +	munmap(data, bo_size);
>>> +	gem_close(fd, bo);
>>> +	xe_vm_destroy(fd, vm);
>>> +}
>>> +
>>> +igt_main
>>> +{
>>> +	const struct section {
>>> +		const char *name;
>>> +		unsigned int flags;
>>> +	} sections[] = {
>>> +		{ "invalid-va", 0 },
>>> +		{ "invalid-va-scratch", DRM_XE_VM_CREATE_SCRATCH_PAGE
>> },
>>> +		{ "invalid-va-fault", DRM_XE_VM_CREATE_FAULT_MODE },
>>> +		{ "invalid-va-fault-scratch",
>> DRM_XE_VM_CREATE_FAULT_MODE |
>>> +
>> DRM_XE_VM_CREATE_SCRATCH_PAGE },
>>> +		{ NULL },
>>> +	};
>>> +	int fd;
>>> +
>>> +	igt_fixture {
>>> +		fd = drm_open_driver(DRIVER_XE);
>>> +		igt_require(xe_supports_faults(fd));
>>> +	}
>>> +
>>> +	for (const struct section *s = sections; s->name; s++) {
>>> +		igt_subtest_f("%s", s->name)
>>> +			test_exec(fd, s->flags);
>>> +	}
>>> +
>>> +	igt_fixture
>>> +		drm_close_driver(fd);
>>> +}
>>> +

Re: [igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[Chang, Yu bruce]

> -----Original Message-----
> From: Welty, Brian <brian.welty@intel.com>
> Sent: Wednesday, August 30, 2023 6:11 PM
> To: Chang, Yu bruce <yu.bruce.chang@intel.com>; igt-
> dev@lists.freedesktop.org
> Cc: Zeng, Oak <oak.zeng@intel.com>; Vishwanathapura, Niranjana
> <niranjana.vishwanathapura@intel.com>; Brost, Matthew
> <matthew.brost@intel.com>
> Subject: Re: [PATCH i-g-t] tests/xe add invalid va access tests
> On 8/30/2023 5:26 PM, Chang, Yu bruce wrote:
> >>
> >> Do we need some verification here that driver did proper thing when
> >> encountering invalid va.  Meaning there was some different behavior
> >> with scratch page we can observe?
> >> Without DRM_XE_VM_CREATE_SCRATCH_PAGE, program is terminated?
> Are we
> >> banning the context like i915 was doing?
> >>
> >
> > Good point, now is a manual check for the log for a reset message, I
> > can look into To automate it.
> >
> 
> Isn't the xe_wait_ufence() supposed to somehow inform that something
> actually failed with the xe_exec?
> I notice you are using _xe_wait_ufence instead of xe_wait_ufence().
> It gives an error?
> 
> You mentioned that the engine was reset....  was is the effect of that?
> Maybe a subsequent xe_exec() will fail?   Just grasping at some
> user-space visible things you can try easily.  I don't know myself, new code...
> 
> -Brian
> 
Actually the reset is just to make sure the existing stuck command got
cleaned up. The next command should still go through.

The v3 patch now can validate the return code from _xe_wait_ufence.
It now only have ETIME and 0.
There is a separate follow up task to include reset, Banned, or other error code.

-Bruce 

[igt-dev] [PATCH i-g-t] tests/xe add invalid va access tests

[Chang, Bruce]

add the following invalid va access test cases:

	gpu fault	scrach page
1) 	no		no
2) 	no		yes
3) 	yes		no
4) 	yes		yes

Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 lib/xe/xe_ioctl.c             |  15 +++-
 lib/xe/xe_ioctl.h             |   3 +
 tests/meson.build             |   1 +
 tests/xe/xe_exec_invalid_va.c | 136 ++++++++++++++++++++++++++++++++++
 4 files changed, 152 insertions(+), 3 deletions(-)
 create mode 100644 tests/xe/xe_exec_invalid_va.c

diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 730dcfd16..022f0cf04 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -415,9 +415,9 @@ void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr)
 	syncobj_destroy(fd, sync.handle);
 }
 
-int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
+int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
 		       struct drm_xe_engine_class_instance *eci,
-		       int64_t timeout)
+		       int64_t timeout, bool timeout_assert)
 {
 	struct drm_xe_wait_user_fence wait = {
 		.addr = to_user_pointer(addr),
@@ -430,11 +430,20 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
 		.instances = eci ? to_user_pointer(eci) : 0,
 	};
 
-	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0);
+	if (igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait))
+		igt_assert (!timeout_assert && errno == ETIME);
 
 	return wait.timeout;
 }
 
+
+int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
+		       struct drm_xe_engine_class_instance *eci,
+		       int64_t timeout)
+{
+	return _xe_wait_ufence(fd, addr, value, eci, timeout, true);
+}
+
 /**
  * xe_wait_ufence_abstime:
  * @fd: xe device fd
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index 6c281b3bf..4bf7410a4 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -82,6 +82,9 @@ void xe_exec(int fd, struct drm_xe_exec *exec);
 void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr,
 		  struct drm_xe_sync *sync, uint32_t num_syncs);
 void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr);
+int64_t _xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
+		       struct drm_xe_engine_class_instance *eci,
+		       int64_t timeout, bool timeout_assert);
 int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
 		       struct drm_xe_engine_class_instance *eci,
 		       int64_t timeout);
diff --git a/tests/meson.build b/tests/meson.build
index 4d325bed1..8861b6c5b 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -276,6 +276,7 @@ xe_progs = [
 	'xe_exec_reset',
 	'xe_exec_store',
 	'xe_exec_threads',
+	'xe_exec_invalid_va',
 	'xe_exercise_blt',
 	'xe_gpgpu_fill',
 	'xe_guc_pc',
diff --git a/tests/xe/xe_exec_invalid_va.c b/tests/xe/xe_exec_invalid_va.c
new file mode 100644
index 000000000..bd9338bd9
--- /dev/null
+++ b/tests/xe/xe_exec_invalid_va.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+/**
+ * TEST: invalid va tests
+ * Category: Hardware building block
+ * Sub-category: execbuf
+ * Functionality: fault mode
+ * Test category: functionality test
+ * GPU requirements: GPU needs support for DRM_XE_VM_CREATE_FAULT_MODE
+ */
+
+#include <fcntl.h>
+
+#include "igt.h"
+#include "lib/igt_syncobj.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include <string.h>
+
+static void insert_atomic_inc(uint32_t *bb, uint64_t va)
+{
+	*bb++ = MI_STORE_DWORD_IMM_GEN4;
+	*bb++ = MI_ATOMIC | MI_ATOMIC_INC;
+	*bb++ = lower_32_bits(va);
+	*bb++ = upper_32_bits(va);
+	*bb++ = MI_BATCH_BUFFER_END;
+}
+
+/**
+ * SUBTEST: invalid-va
+ * Description: Check driver handling of invalid va access
+ * Run type: FULL
+ *
+ * SUBTEST: invalid-va-scratch
+ * Description: Check driver handling of invalid va access with scratch page
+ * Run type: FULL
+ *
+ * SUBTEST: invalid-va-fault
+ * Description: Check driver handling of invalid va access with fault enabled
+ * Run type: FULL
+ *
+ * SUBTEST: invalid-va-fault-scratch
+ * Description: Check driver handling of invalid va access with fault + scratch page
+ * Run type: FULL
+ *
+ * arg[1]: for vm create flags
+ */
+static void test_exec(int fd, uint32_t flags)
+{
+	const uint64_t inv_addr = 0x20000000;
+	const uint64_t addr = 0x1a0000;
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+#define ONE_SEC			MS_TO_NS(1000)
+	struct _data {
+		uint32_t batch[16];
+		uint64_t sync;
+		uint64_t data;
+	} *data;
+	struct drm_xe_sync sync = {
+		.flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+		.timeline_value = USER_FENCE_VALUE,
+		.addr = addr + offsetof(struct _data, sync),
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.address = addr,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&sync),
+	};
+	uint32_t vm;
+	uint32_t bo;
+	size_t bo_size;
+	struct drm_xe_engine_class_instance *eci;
+
+	eci = xe_hw_engine(fd, 0);
+	vm = xe_vm_create(fd, flags, 0);
+	bo_size = ALIGN(sizeof(*data), xe_get_default_alignment(fd));
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				all_memory_regions(fd) |
+				visible_vram_if_possible(fd, 0));
+	data = xe_bo_map(fd, bo, bo_size);
+
+	insert_atomic_inc(data->batch, inv_addr + offsetof(struct _data, data));
+	if(flags & DRM_XE_VM_CREATE_FAULT_MODE)
+		xe_vm_bind(fd, vm, bo, 0, addr, bo_size, 0, 0);
+	else
+		xe_vm_bind_sync(fd, vm, bo, 0, addr, bo_size);
+	exec.exec_queue_id = xe_exec_queue_create(fd, vm, eci, 0);
+	xe_exec(fd, &exec);
+        _xe_wait_ufence(fd, &data->sync, USER_FENCE_VALUE, NULL, ONE_SEC, false);
+
+	if(flags & DRM_XE_VM_CREATE_FAULT_MODE)
+		xe_vm_unbind(fd, vm, 0, addr, bo_size, 0, 0);
+	else
+		xe_vm_unbind_sync(fd, vm, 0, addr, bo_size);
+	xe_exec_queue_destroy(fd, exec.exec_queue_id);
+	munmap(data, bo_size);
+	gem_close(fd, bo);
+	xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+	const struct section {
+		const char *name;
+		unsigned int flags;
+	} sections[] = {
+		{ "invalid-va", 0 },
+		{ "invalid-va-scratch", DRM_XE_VM_CREATE_SCRATCH_PAGE },
+		{ "invalid-va-fault", DRM_XE_VM_CREATE_FAULT_MODE },
+		{ "invalid-va-fault-scratch", DRM_XE_VM_CREATE_FAULT_MODE |
+					      DRM_XE_VM_CREATE_SCRATCH_PAGE },
+		{ NULL },
+	};
+	int fd;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_XE);
+		igt_require(xe_supports_faults(fd));
+	}
+
+	for (const struct section *s = sections; s->name; s++) {
+		igt_subtest_f("%s", s->name)
+			test_exec(fd, s->flags);
+	}
+
+	igt_fixture
+		drm_close_driver(fd);
+}
+
-- 
2.25.1