* [igt-dev] [PATCH i-g-t 0/3] Add support for intel_ctx_t in intel_bb
@ 2022-10-21 8:54 Karolina Drobnik
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_batchbuffer: Extend __intel_bb_create to handle context config Karolina Drobnik
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Karolina Drobnik @ 2022-10-21 8:54 UTC (permalink / raw)
To: igt-dev
Currently, intel_bb assumes that context has a fixed set of engines, which
might not be the case for contexts passed from the userspace. They may use
a custom engines layout, so the legacy flags like I915_EXEC_BLT wouldn't
match the actual engine indices.
To address this issue, the series adds an additional field to intel_bb,
intel_ctx_cfg_t (intel_ctx_t configuration), that describes the engine
instances, together with an engine index lookup function, find_engine().
The function added in the second patch is used by intel_bb_flush_render()
and intel_bb_flush_blit() helpers.
The last patch in the series adds a test where we define a context with
the blitter engine at index 0 (1 in the legacy mode) to verify that
(1) intel_bb can indeed handle external contexts, and (2) intel_bb_exec gets
the correct engine id in intel_bb_flush_blit().
Karolina Drobnik (3):
lib/intel_batchbuffer: Extend __intel_bb_create to handle context
config
lib/intel_batchbuffer: Add support for custom engine layouts
tests/api_intel_bb: Add misplaced_blitter test
lib/igt_draw.c | 2 +-
lib/intel_batchbuffer.c | 86 +++++++++++++++++++++++++--------
lib/intel_batchbuffer.h | 6 ++-
lib/media_fill.c | 2 +-
tests/i915/api_intel_bb.c | 36 +++++++++++++-
tests/i915/gem_ppgtt.c | 2 +-
tests/i915/gem_pxp.c | 16 +++---
tests/i915/kms_fence_pin_leak.c | 2 +-
tests/i915/perf.c | 18 +++----
9 files changed, 126 insertions(+), 44 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [igt-dev] [PATCH i-g-t 1/3] lib/intel_batchbuffer: Extend __intel_bb_create to handle context config
2022-10-21 8:54 [igt-dev] [PATCH i-g-t 0/3] Add support for intel_ctx_t in intel_bb Karolina Drobnik
@ 2022-10-21 8:54 ` Karolina Drobnik
2022-10-24 6:37 ` Zbigniew Kempczyński
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_batchbuffer: Add support for custom engine layouts Karolina Drobnik
` (3 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Karolina Drobnik @ 2022-10-21 8:54 UTC (permalink / raw)
To: igt-dev
Currently, intel_bb stores context id with no information about the context
itself. This means that intel batchbuffer can only execute on a fixed set
of engines with pre-defined indices (so called legacy mode). To accommodate
contexts with custom engine layouts, save the context configuration in
intel_bb struct.
Update function calls to reflect that change.
Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
---
lib/igt_draw.c | 2 +-
lib/intel_batchbuffer.c | 41 ++++++++++++++++++++++-----------
lib/intel_batchbuffer.h | 6 ++++-
lib/media_fill.c | 2 +-
tests/i915/api_intel_bb.c | 2 +-
tests/i915/gem_ppgtt.c | 2 +-
tests/i915/gem_pxp.c | 16 ++++++-------
tests/i915/kms_fence_pin_leak.c | 2 +-
tests/i915/perf.c | 18 +++++++--------
9 files changed, 55 insertions(+), 36 deletions(-)
diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 1124cadc..975d65cd 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -780,7 +780,7 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
src = create_buf(fd, cmd_data->bops, &tmp, I915_TILING_NONE);
dst = create_buf(fd, cmd_data->bops, buf, tiling);
- ibb = intel_bb_create_with_context(fd, cmd_data->ctx, PAGE_SIZE);
+ ibb = intel_bb_create_with_context(fd, cmd_data->ctx, NULL, PAGE_SIZE);
rendercopy(ibb, src, 0, 0, rect->w, rect->h, dst, rect->x, rect->y);
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index bb2503bb..70d819aa 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1304,7 +1304,8 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
/**
* __intel_bb_create:
* @i915: drm fd
- * @ctx: context
+ * @ctx: context id
+ * @cfg: intel_ctx configuration, NULL for default context or legacy mode
* @size: size of the batchbuffer
* @do_relocs: use relocations or allocator
* @allocator_type: allocator type, must be INTEL_ALLOCATOR_NONE for relocations
@@ -1338,18 +1339,22 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
*
* If we do reset with purging caches allocator entries are freed as well.
*
+ * __intel_bb_create checks if a context configuration for intel_ctx_t was
+ * passed in. If this is the case, it copies the information over to the
+ * newly created batch buffer.
+ *
* Returns:
*
* Pointer the intel_bb, asserts on failure.
*/
static struct intel_bb *
-__intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
+__intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
+ uint32_t size, bool do_relocs,
uint64_t start, uint64_t end,
uint8_t allocator_type, enum allocator_strategy strategy)
{
struct drm_i915_gem_exec_object2 *object;
struct intel_bb *ibb = calloc(1, sizeof(*ibb));
-
igt_assert(ibb);
ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
@@ -1399,6 +1404,13 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
ibb->ptr = ibb->batch;
ibb->fence = -1;
+ /* Cache context configuration */
+ if (cfg) {
+ ibb->cfg = malloc(sizeof(*cfg));
+ igt_assert(ibb->cfg);
+ memcpy(ibb->cfg, cfg, sizeof(*cfg));
+ }
+
ibb->gtt_size = gem_aperture_size(i915);
if ((ibb->gtt_size - 1) >> 32)
ibb->supports_48b_address = true;
@@ -1446,7 +1458,7 @@ struct intel_bb *intel_bb_create_full(int i915, uint32_t ctx, uint32_t size,
uint8_t allocator_type,
enum allocator_strategy strategy)
{
- return __intel_bb_create(i915, ctx, size, false, start, end,
+ return __intel_bb_create(i915, ctx, NULL, size, false, start, end,
allocator_type, strategy);
}
@@ -1469,7 +1481,7 @@ struct intel_bb *intel_bb_create_with_allocator(int i915, uint32_t ctx,
uint32_t size,
uint8_t allocator_type)
{
- return __intel_bb_create(i915, ctx, size, false, 0, 0,
+ return __intel_bb_create(i915, ctx, NULL, size, false, 0, 0,
allocator_type, ALLOC_STRATEGY_HIGH_TO_LOW);
}
@@ -1502,7 +1514,7 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
{
bool relocs = gem_has_relocations(i915);
- return __intel_bb_create(i915, 0, size,
+ return __intel_bb_create(i915, 0, NULL, size,
relocs && !aux_needs_softpin(i915), 0, 0,
INTEL_ALLOCATOR_SIMPLE,
ALLOC_STRATEGY_HIGH_TO_LOW);
@@ -1511,21 +1523,23 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
/**
* intel_bb_create_with_context:
* @i915: drm fd
- * @ctx: context
+ * @ctx: context id
+ * @cfg: intel_ctx configuration, NULL for default context or legacy mode
* @size: size of the batchbuffer
*
- * Creates bb with context passed in @ctx.
+ * Creates bb with context passed in @ctx and @cfg configuration (when
+ * working with custom engines layout).
*
* Returns:
*
* Pointer the intel_bb, asserts on failure.
*/
struct intel_bb *
-intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size)
+intel_bb_create_with_context(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg, uint32_t size)
{
bool relocs = gem_has_relocations(i915);
- return __intel_bb_create(i915, ctx, size,
+ return __intel_bb_create(i915, ctx, cfg, size,
relocs && !aux_needs_softpin(i915), 0, 0,
INTEL_ALLOCATOR_SIMPLE,
ALLOC_STRATEGY_HIGH_TO_LOW);
@@ -1547,7 +1561,7 @@ struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
{
igt_require(gem_has_relocations(i915));
- return __intel_bb_create(i915, 0, size, true, 0, 0,
+ return __intel_bb_create(i915, 0, NULL, size, true, 0, 0,
INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
}
@@ -1569,7 +1583,7 @@ intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size)
{
igt_require(gem_has_relocations(i915));
- return __intel_bb_create(i915, ctx, size, true, 0, 0,
+ return __intel_bb_create(i915, ctx, NULL, size, true, 0, 0,
INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
}
@@ -1589,7 +1603,7 @@ struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size)
{
igt_require(gem_uses_full_ppgtt(i915));
- return __intel_bb_create(i915, 0, size, false, 0, 0,
+ return __intel_bb_create(i915, 0, NULL, size, false, 0, 0,
INTEL_ALLOCATOR_SIMPLE,
ALLOC_STRATEGY_HIGH_TO_LOW);
}
@@ -1670,6 +1684,7 @@ void intel_bb_destroy(struct intel_bb *ibb)
close(ibb->fence);
free(ibb->batch);
+ free(ibb->cfg);
free(ibb);
}
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 36b6b61d..68054495 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -486,6 +486,9 @@ struct intel_bb {
uint32_t ctx;
uint32_t vm_id;
+ /* Context configuration */
+ intel_ctx_cfg_t *cfg;
+
/* Cache */
void *root;
@@ -522,7 +525,8 @@ intel_bb_create_with_allocator(int i915, uint32_t ctx,
uint32_t size, uint8_t allocator_type);
struct intel_bb *intel_bb_create(int i915, uint32_t size);
struct intel_bb *
-intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size);
+intel_bb_create_with_context(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
+ uint32_t size);
struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
struct intel_bb *
intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size);
diff --git a/lib/media_fill.c b/lib/media_fill.c
index d758f1f5..4f8b50e8 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -309,7 +309,7 @@ __gen11_media_vme_func(int i915,
struct intel_bb *ibb;
uint32_t curbe_buffer, interface_descriptor;
- ibb = intel_bb_create_with_context(i915, ctx, PAGE_SIZE);
+ ibb = intel_bb_create_with_context(i915, ctx, NULL, PAGE_SIZE);
intel_bb_add_intel_buf(ibb, dst, true);
intel_bb_add_intel_buf(ibb, src, false);
diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
index 1f663d2a..6ba1fd1b 100644
--- a/tests/i915/api_intel_bb.c
+++ b/tests/i915/api_intel_bb.c
@@ -202,7 +202,7 @@ static void simple_bb(struct buf_ops *bops, bool use_context)
if (use_context) {
ctx = gem_context_create(i915);
intel_bb_destroy(ibb);
- ibb = intel_bb_create_with_context(i915, ctx, PAGE_SIZE);
+ ibb = intel_bb_create_with_context(i915, ctx, NULL, PAGE_SIZE);
intel_bb_out(ibb, MI_BATCH_BUFFER_END);
intel_bb_ptr_align(ibb, 8);
intel_bb_exec(ibb, intel_bb_offset(ibb),
diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
index 0a06e9ec..9673ce22 100644
--- a/tests/i915/gem_ppgtt.c
+++ b/tests/i915/gem_ppgtt.c
@@ -112,7 +112,7 @@ static void fork_rcs_copy(int timeout, uint32_t final,
ctx = gem_context_create(buf_ops_get_fd(dst[child]->bops));
ibb = intel_bb_create_with_context(buf_ops_get_fd(dst[child]->bops),
- ctx, 4096);
+ ctx, NULL, 4096);
i = 0;
igt_until_timeout(timeout) {
src = create_bo(dst[child]->bops,
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 65618556..b43273c9 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -457,7 +457,7 @@ static void test_render_baseline(int i915)
/* Perform a regular 3d copy as a control checkpoint */
ret = create_ctx_with_params(i915, false, false, false, false, &ctx);
igt_assert_eq(ret, 0);
- ibb = intel_bb_create_with_context(i915, ctx, 4096);
+ ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
igt_assert(ibb);
dstbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_INITCOLOR1);
@@ -506,7 +506,7 @@ static void __test_render_pxp_src_to_protdest(int i915, uint32_t *outpixels, int
ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
igt_assert_eq(ret, 0);
igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
- ibb = intel_bb_create_with_context(i915, ctx, 4096);
+ ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
igt_assert(ibb);
intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
@@ -567,7 +567,7 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
igt_assert_eq(ret, 0);
igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
- ibb = intel_bb_create_with_context(i915, ctx, 4096);
+ ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
igt_assert(ibb);
intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
@@ -655,7 +655,7 @@ static void test_pxp_dmabuffshare_refcnt(void)
ret = create_ctx_with_params(fd[n], true, true, true, false, &ctx[n]);
igt_assert_eq(ret, 0);
igt_assert_eq(get_ctx_protected_param(fd[n], ctx[n]), 1);
- ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], 4096);
+ ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], NULL, 4096);
intel_bb_set_pxp(ibb[n], true, DISPLAY_APPTYPE,
I915_PROTECTED_CONTENT_DEFAULT_SESSION);
@@ -820,7 +820,7 @@ static void prepare_exec_assets(int i915, struct simple_exec_assets *data, bool
ret = create_ctx_with_params(i915, false, false, false, false, &(data->ctx));
igt_assert_eq(ret, 0);
igt_assert_eq(get_ctx_protected_param(i915, data->ctx), ctx_pxp);
- data->ibb = intel_bb_create_with_context(i915, data->ctx, 4096);
+ data->ibb = intel_bb_create_with_context(i915, data->ctx, NULL, 4096);
igt_assert(data->ibb);
data->fencebo = alloc_and_fill_dest_buff(i915, buf_pxp, 4096, 0);
@@ -900,7 +900,7 @@ static void test_pxp_stale_buf_execution(int i915)
ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
igt_assert_eq(ret, 0);
igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
- ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
+ ibb2 = intel_bb_create_with_context(i915, ctx2, NULL, 4096);
igt_assert(ibb2);
intel_bb_remove_intel_buf(data.ibb, data.fencebuf);
intel_bb_add_intel_buf(ibb2, data.fencebuf, true);
@@ -979,7 +979,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
igt_assert_eq(ret, 0);
igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
- ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
+ ibb2 = intel_bb_create_with_context(i915, ctx2, NULL, 4096);
igt_assert(ibb2);
intel_bb_remove_intel_buf(data[1].ibb, data[1].fencebuf);
intel_bb_add_intel_buf(ibb2, data[1].fencebuf, true);
@@ -1043,7 +1043,7 @@ static void setup_protected_fb(int i915, int width, int height, igt_fb_t *fb, ui
fb->plane_bpp[0], 0,
igt_fb_mod_to_tiling(fb->modifier), 0);
- ibb = intel_bb_create_with_context(i915, ctx, 4096);
+ ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
igt_assert(ibb);
ibb->pxp.enabled = true;
diff --git a/tests/i915/kms_fence_pin_leak.c b/tests/i915/kms_fence_pin_leak.c
index f1eac1c6..1972a699 100644
--- a/tests/i915/kms_fence_pin_leak.c
+++ b/tests/i915/kms_fence_pin_leak.c
@@ -62,7 +62,7 @@ static void exec_nop(data_t *data, struct igt_fb *fb, uint32_t ctx)
intel_buf_set_ownership(dst, true);
ibb = intel_bb_create_with_context(buf_ops_get_fd(data->bops),
- ctx, 4096);
+ ctx, NULL, 4096);
/* add the reloc to make sure the kernel will think we write to dst */
intel_bb_add_intel_buf(ibb, dst, true);
diff --git a/tests/i915/perf.c b/tests/i915/perf.c
index 5502a3fb..9ef52690 100644
--- a/tests/i915/perf.c
+++ b/tests/i915/perf.c
@@ -1586,7 +1586,7 @@ static void load_helper_init(void)
lh.context_id = gem_context_create(drm_fd);
igt_assert_neq(lh.context_id, 0xffffffff);
- lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, BATCH_SZ);
+ lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, NULL, BATCH_SZ);
scratch_buf_init(lh.bops, &lh.dst, 1920, 1080, 0);
scratch_buf_init(lh.bops, &lh.src, 1920, 1080, 0);
@@ -3011,7 +3011,7 @@ gen12_test_mi_rpc(void)
igt_assert_neq(ctx_id, INVALID_CTX_ID);
properties[1] = ctx_id;
- ibb = intel_bb_create_with_context(drm_fd, ctx_id, BATCH_SZ);
+ ibb = intel_bb_create_with_context(drm_fd, ctx_id, NULL, BATCH_SZ);
buf = intel_buf_create(bops, 4096, 1, 8, 64,
I915_TILING_NONE, I915_COMPRESSION_NONE);
@@ -3090,7 +3090,7 @@ test_mi_rpc(void)
ctx_id = gem_context_create(drm_fd);
- ibb = intel_bb_create_with_context(drm_fd, ctx_id, BATCH_SZ);
+ ibb = intel_bb_create_with_context(drm_fd, ctx_id, NULL, BATCH_SZ);
buf = intel_buf_create(bops, 4096, 1, 8, 64,
I915_TILING_NONE, I915_COMPRESSION_NONE);
@@ -3217,8 +3217,8 @@ hsw_test_single_ctx_counters(void)
*/
context0_id = gem_context_create(drm_fd);
context1_id = gem_context_create(drm_fd);
- ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
- ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
+ ibb0 = intel_bb_create_with_context(drm_fd, context0_id, NULL, BATCH_SZ);
+ ibb1 = intel_bb_create_with_context(drm_fd, context1_id, NULL, BATCH_SZ);
igt_debug("submitting warm up render_copy\n");
@@ -3461,8 +3461,8 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
context0_id = gem_context_create(drm_fd);
context1_id = gem_context_create(drm_fd);
- ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
- ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
+ ibb0 = intel_bb_create_with_context(drm_fd, context0_id, NULL, BATCH_SZ);
+ ibb1 = intel_bb_create_with_context(drm_fd, context1_id, NULL, BATCH_SZ);
igt_debug("submitting warm up render_copy\n");
@@ -3866,8 +3866,8 @@ static void gen12_single_ctx_helper(void)
context0_id = gem_context_create(drm_fd);
context1_id = gem_context_create(drm_fd);
- ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
- ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
+ ibb0 = intel_bb_create_with_context(drm_fd, context0_id, NULL, BATCH_SZ);
+ ibb1 = intel_bb_create_with_context(drm_fd, context1_id, NULL, BATCH_SZ);
igt_debug("submitting warm up render_copy\n");
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [igt-dev] [PATCH i-g-t 2/3] lib/intel_batchbuffer: Add support for custom engine layouts
2022-10-21 8:54 [igt-dev] [PATCH i-g-t 0/3] Add support for intel_ctx_t in intel_bb Karolina Drobnik
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_batchbuffer: Extend __intel_bb_create to handle context config Karolina Drobnik
@ 2022-10-21 8:54 ` Karolina Drobnik
2022-10-24 6:40 ` Zbigniew Kempczyński
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 3/3] tests/api_intel_bb: Add misplaced_blitter test Karolina Drobnik
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Karolina Drobnik @ 2022-10-21 8:54 UTC (permalink / raw)
To: igt-dev
Don't assume fixed engine ids and use context configuration in
intel_bb to find the appropriate engine when executing the batchbuffer.
Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
---
lib/intel_batchbuffer.c | 45 +++++++++++++++++++++++++++++++++--------
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 70d819aa..20b7e255 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1490,6 +1490,31 @@ static bool aux_needs_softpin(int i915)
return intel_gen(intel_get_drm_devid(i915)) >= 12;
}
+static bool has_ctx_cfg(struct intel_bb *ibb)
+{
+ return ibb->cfg && (ibb->cfg->num_engines > 0);
+}
+
+static bool find_engine(struct intel_bb *ibb, unsigned int class, uint32_t *ring)
+{
+ intel_ctx_cfg_t *cfg;
+ int i;
+
+ /* Use legacy engines when there is no context config */
+ if (!has_ctx_cfg(ibb))
+ return false;
+
+ cfg = ibb->cfg;
+ for (i = 0; i < cfg->num_engines; i++) {
+ if (cfg->engines[i].engine_class == class) {
+ *ring = i;
+ return true;
+ }
+ }
+
+ return false;
+}
+
/**
* intel_bb_create:
* @i915: drm fd
@@ -2790,34 +2815,38 @@ void intel_bb_flush(struct intel_bb *ibb, uint32_t ring)
* intel_bb_flush_render:
* @ibb: batchbuffer
*
- * If batch is not empty emit batch buffer end, execute on render ring
- * and reset the batch. Context used to execute is batch context.
+ * If batch is not empty emit batch buffer end, find the render engine id,
+ * execute on the ring and reset the batch. Context used to execute
+ * is batch context.
*/
void intel_bb_flush_render(struct intel_bb *ibb)
{
+ uint32_t ring = I915_EXEC_RENDER;
+
if (intel_bb_emit_flush_common(ibb) == 0)
return;
- intel_bb_exec_with_ring(ibb, I915_EXEC_RENDER);
+ find_engine(ibb, I915_ENGINE_CLASS_RENDER, &ring);
+ intel_bb_exec_with_ring(ibb, ring);
}
/*
* intel_bb_flush_blit:
* @ibb: batchbuffer
*
- * If batch is not empty emit batch buffer end, execute on default/blit ring
- * (depends on gen) and reset the batch.
+ * If batch is not empty emit batch buffer end, find a suitable ring
+ * (depending on gen and context configuration) and reset the batch.
* Context used to execute is batch context.
*/
void intel_bb_flush_blit(struct intel_bb *ibb)
{
- uint32_t ring = I915_EXEC_DEFAULT;
+ uint32_t ring;
if (intel_bb_emit_flush_common(ibb) == 0)
return;
- if (HAS_BLT_RING(ibb->devid))
- ring = I915_EXEC_BLT;
+ ring = HAS_BLT_RING(ibb->devid) ? I915_EXEC_BLT : I915_EXEC_DEFAULT;
+ find_engine(ibb, I915_ENGINE_CLASS_COPY, &ring);
intel_bb_exec_with_ring(ibb, ring);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [igt-dev] [PATCH i-g-t 3/3] tests/api_intel_bb: Add misplaced_blitter test
2022-10-21 8:54 [igt-dev] [PATCH i-g-t 0/3] Add support for intel_ctx_t in intel_bb Karolina Drobnik
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_batchbuffer: Extend __intel_bb_create to handle context config Karolina Drobnik
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_batchbuffer: Add support for custom engine layouts Karolina Drobnik
@ 2022-10-21 8:54 ` Karolina Drobnik
2022-10-24 6:46 ` Zbigniew Kempczyński
2022-10-21 10:42 ` [igt-dev] ✓ Fi.CI.BAT: success for Add support for intel_ctx_t in intel_bb Patchwork
2022-10-21 16:18 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 1 reply; 14+ messages in thread
From: Karolina Drobnik @ 2022-10-21 8:54 UTC (permalink / raw)
To: igt-dev
Exercise intel_bb with a custom context engines layout.
Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
---
tests/i915/api_intel_bb.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
index 6ba1fd1b..42959880 100644
--- a/tests/i915/api_intel_bb.c
+++ b/tests/i915/api_intel_bb.c
@@ -1209,6 +1209,36 @@ static void full_batch(struct buf_ops *bops)
intel_bb_destroy(ibb);
}
+static void misplaced_blitter(struct buf_ops *bops)
+{
+ int i915 = buf_ops_get_fd(bops);
+ struct intel_bb *ibb;
+
+ gem_require_contexts(i915);
+
+ /* Use custom configuration with blitter at index 0 */
+ const intel_ctx_cfg_t cfg = (intel_ctx_cfg_t) {
+ .num_engines = 2,
+ .engines = {
+ { .engine_class = I915_ENGINE_CLASS_COPY,
+ .engine_instance = 0
+ },
+ { .engine_class = I915_ENGINE_CLASS_RENDER,
+ .engine_instance = 0
+ },
+ },
+ };
+ const intel_ctx_t *ctx = intel_ctx_create(i915, &cfg);
+
+ ibb = intel_bb_create_with_context(i915, ctx->id, &ctx->cfg, PAGE_SIZE);
+
+ intel_bb_emit_bbe(ibb);
+ intel_bb_flush_blit(ibb);
+
+ intel_bb_destroy(ibb);
+ intel_ctx_destroy(i915, ctx);
+}
+
static int render(struct buf_ops *bops, uint32_t tiling, bool do_reloc,
uint32_t width, uint32_t height)
{
@@ -1581,6 +1611,10 @@ igt_main_args("dpibc:", NULL, help_str, opt_handler, NULL)
igt_subtest("full-batch")
full_batch(bops);
+ igt_describe("Execute intel_bb with set of engines provided by userspace");
+ igt_subtest("misplaced-blitter")
+ misplaced_blitter(bops);
+
igt_subtest_with_dynamic("render") {
for (i = 0; i < ARRAY_SIZE(tests); i++) {
const struct test *t = &tests[i];
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add support for intel_ctx_t in intel_bb
2022-10-21 8:54 [igt-dev] [PATCH i-g-t 0/3] Add support for intel_ctx_t in intel_bb Karolina Drobnik
` (2 preceding siblings ...)
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 3/3] tests/api_intel_bb: Add misplaced_blitter test Karolina Drobnik
@ 2022-10-21 10:42 ` Patchwork
2022-10-21 16:18 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2022-10-21 10:42 UTC (permalink / raw)
To: Karolina Drobnik; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 7053 bytes --]
== Series Details ==
Series: Add support for intel_ctx_t in intel_bb
URL : https://patchwork.freedesktop.org/series/109993/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12272 -> IGTPW_7996
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/index.html
Participating hosts (45 -> 42)
------------------------------
Additional (1): fi-tgl-dsi
Missing (4): fi-ctg-p8600 fi-icl-u2 fi-bdw-samus fi-hsw-4200u
Known issues
------------
Here are the changes found in IGTPW_7996 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [PASS][1] -> [FAIL][2] ([i915#7229])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-apl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/fi-apl-guc/igt@i915_suspend@basic-s2idle-without-i915.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/fi-apl-guc/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][5] -> [INCOMPLETE][6] ([i915#4817] / [i915#5982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
- fi-bdw-5557u: [PASS][7] -> [INCOMPLETE][8] ([i915#146] / [i915#6712])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/fi-bdw-5557u/igt@i915_suspend@basic-s3-without-i915.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/fi-bdw-5557u/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [PASS][9] -> [FAIL][10] ([i915#6298])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][11] ([i915#2867]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-adlm-1}: [DMESG-WARN][13] ([i915#2867]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/bat-adlm-1/igt@gem_exec_suspend@basic-s3@smem.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/bat-adlm-1/igt@gem_exec_suspend@basic-s3@smem.html
- {bat-rpls-1}: [DMESG-WARN][15] ([i915#6687]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_huc_copy@huc-copy:
- {bat-dg2-8}: [FAIL][17] ([i915#7029]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/bat-dg2-8/igt@gem_huc_copy@huc-copy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/bat-dg2-8/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-bdw-5557u: [DMESG-FAIL][19] ([i915#5334]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
- fi-bxt-dsi: [DMESG-FAIL][21] ([i915#5334]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6712]: https://gitlab.freedesktop.org/drm/intel/issues/6712
[i915#6856]: https://gitlab.freedesktop.org/drm/intel/issues/6856
[i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
[i915#7125]: https://gitlab.freedesktop.org/drm/intel/issues/7125
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7021 -> IGTPW_7996
CI-20190529: 20190529
CI_DRM_12272: 168aff13f677d0e72ad071851f2305a836696ae3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7996: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/index.html
IGT_7021: b99f94fc3652f6838b8803032373a419372b17b1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@api_intel_bb@misplaced-blitter
-igt@gem_create@create-ext-placement-alignment
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/index.html
[-- Attachment #2: Type: text/html, Size: 6961 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Add support for intel_ctx_t in intel_bb
2022-10-21 8:54 [igt-dev] [PATCH i-g-t 0/3] Add support for intel_ctx_t in intel_bb Karolina Drobnik
` (3 preceding siblings ...)
2022-10-21 10:42 ` [igt-dev] ✓ Fi.CI.BAT: success for Add support for intel_ctx_t in intel_bb Patchwork
@ 2022-10-21 16:18 ` Patchwork
4 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2022-10-21 16:18 UTC (permalink / raw)
To: Karolina Drobnik; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 100243 bytes --]
== Series Details ==
Series: Add support for intel_ctx_t in intel_bb
URL : https://patchwork.freedesktop.org/series/109993/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12272_full -> IGTPW_7996_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/index.html
Participating hosts (9 -> 8)
------------------------------
Additional (2): shard-rkl shard-dg1
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
New tests
---------
New tests have been introduced between CI_DRM_12272_full and IGTPW_7996_full:
### New IGT tests (453) ###
* igt@api_intel_bb@misplaced-blitter:
- Statuses : 6 pass(s)
- Exec time: [0.00, 0.01] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-linear-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-linear-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-linear-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-linear-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-linear-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-x-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-x-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-x-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-x-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-x-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.30] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.30] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.25] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.67] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-yf-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-linear-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-linear-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-linear-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-linear-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-linear-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-x-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-x-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-x-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-x-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-x-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.25] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.30] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-y-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.53] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-b-yf-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-linear-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-linear-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-linear-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-x-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-x-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-x-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-y-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-y-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-y-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.25] s
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-c-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.58] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-linear-to-linear:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-linear-to-x:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-linear-to-y:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-linear-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-linear-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-linear-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-linear-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-x-to-linear:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-x-to-x:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-x-to-y:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-x-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-x-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-x-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-x-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-rc_ccs-cc-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-rc_ccs-cc-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-rc_ccs-cc-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-rc_ccs-cc-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-rc_ccs-cc-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-rc_ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.08] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-rc_ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-rc_ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-rc_ccs-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.25] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-rc_ccs-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-to-linear:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-to-x:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-to-y:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.08] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-y-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.40] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-a-yf-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-linear-to-linear:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-linear-to-x:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-linear-to-y:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-linear-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-linear-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-linear-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-linear-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-x-to-linear:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-x-to-x:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-x-to-y:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-x-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-x-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-x-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-x-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-rc_ccs-cc-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-rc_ccs-cc-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-rc_ccs-cc-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-rc_ccs-cc-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-rc_ccs-cc-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-rc_ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-rc_ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-rc_ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-rc_ccs-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [1.28] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-rc_ccs-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-to-linear:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-to-x:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-to-y:
- Statuses : 2 pass(s)
- Exec time: [0.10, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-y-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [1.34] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-yf-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-linear-to-linear:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-linear-to-x:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-linear-to-y:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-linear-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-linear-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-linear-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-linear-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-x-to-linear:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-x-to-x:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-x-to-y:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-x-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-x-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-x-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-x-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-rc_ccs-cc-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.08] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-rc_ccs-cc-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-rc_ccs-cc-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-rc_ccs-cc-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-rc_ccs-cc-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-rc_ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.08] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-rc_ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-rc_ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-rc_ccs-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [1.30] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-rc_ccs-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-to-linear:
- Statuses : 2 pass(s)
- Exec time: [0.08, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-to-x:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-to-y:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-y-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [1.37] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-c-yf-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-linear-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.08] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-linear-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.08] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-linear-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.08] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-linear-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-linear-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-x-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.08] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-x-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.08] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-x-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-x-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-x-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-rc_ccs-cc-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-rc_ccs-cc-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-rc_ccs-cc-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-rc_ccs-cc-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-rc_ccs-cc-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-rc_ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-rc_ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-rc_ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-rc_ccs-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [1.27] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-rc_ccs-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-to-y-rc_ccs:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-d-y-to-y-rc_ccs-cc:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-linear-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-linear-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-linear-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-linear-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-linear-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-x-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-x-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-x-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-x-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-x-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.24] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-y-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.92] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-a-yf-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-linear-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-linear-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-linear-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-linear-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-linear-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-x-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-x-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-x-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-x-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-x-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-y-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.46] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-b-yf-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-linear-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-linear-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-linear-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-x-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-x-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-x-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-y-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-y-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-y-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-c-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.55] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-linear-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-linear-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-linear-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-linear-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-linear-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-x-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-x-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-x-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-x-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-x-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.34] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.26] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-y-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.39] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.21] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-a-yf-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-linear-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.11] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-linear-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-linear-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-linear-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-linear-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-x-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-x-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-x-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-x-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-x-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-y-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-ccs-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-ccs-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-ccs-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-ccs-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-ccs-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-ccs-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.38] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-to-y-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-b-yf-to-yf-ccs:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-linear-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-linear-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-linear-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-linear-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-x-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.11] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-x-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-x-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.17] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-x-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-y-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-y-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-y-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-y-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-yf-to-linear:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-yf-to-x:
- Statuses : 1 pass(s)
- Exec time: [0.15] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-yf-to-y:
- Statuses : 1 pass(s)
- Exec time: [0.18] s
* igt@kms_flip_tiling@flip-change-tiling@hdmi-a-2-pipe-c-yf-to-yf:
- Statuses : 1 pass(s)
- Exec time: [0.40] s
* igt@kms_invalid_mode@bad-htotal:
- Statuses :
- Exec time: [None] s
* igt@kms_invalid_mode@bad-vsync-end:
- Statuses :
- Exec time: [None] s
* igt@kms_invalid_mode@bad-vsync-start:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_invalid_mode@bad-vtotal:
- Statuses :
- Exec time: [None] s
* igt@kms_invalid_mode@clock-too-high:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_invalid_mode@uint-max-clock:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_invalid_mode@zero-hdisplay:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_7996_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-3x:
- shard-iclb: NOTRUN -> [SKIP][1] ([i915#1839])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb1/igt@feature_discovery@display-3x.html
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][2] ([i915#4991])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl7/igt@gem_create@create-massive.html
- shard-tglb: NOTRUN -> [DMESG-WARN][3] ([i915#4991])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb8/igt@gem_create@create-massive.html
- shard-glk: NOTRUN -> [DMESG-WARN][4] ([i915#4991])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk2/igt@gem_create@create-massive.html
- shard-iclb: NOTRUN -> [DMESG-WARN][5] ([i915#4991])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb7/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@hang:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-snb6/igt@gem_ctx_persistence@hang.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: NOTRUN -> [SKIP][7] ([i915#4525]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb8/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +4 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb4/igt@gem_exec_balancer@parallel-keep-in-fence.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglb: NOTRUN -> [FAIL][10] ([i915#6117])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb6/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-tglb: NOTRUN -> [FAIL][13] ([i915#2842]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb5/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: NOTRUN -> [FAIL][14] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk8/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb5/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-glk8/igt@gem_exec_fair@basic-pace@vcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk7/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4613]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb3/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#4613]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb7/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
- shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk1/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl2/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-iclb: NOTRUN -> [SKIP][23] ([i915#4270])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb1/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
- shard-tglb: NOTRUN -> [SKIP][24] ([i915#4270])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb8/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_render_copy@y-tiled-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#768]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb6/igt@gem_render_copy@y-tiled-to-vebox-y-tiled.html
* igt@gem_userptr_blits@coherency-sync:
- shard-iclb: NOTRUN -> [SKIP][26] ([fdo#109290])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb5/igt@gem_userptr_blits@coherency-sync.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#2527] / [i915#2856]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb8/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-start-param:
- shard-iclb: NOTRUN -> [SKIP][28] ([i915#2856]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb3/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pipe_stress@stress-xrgb8888-untiled:
- shard-apl: NOTRUN -> [FAIL][29] ([i915#7036])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl6/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-iclb: NOTRUN -> [SKIP][30] ([i915#6590])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb5/igt@i915_pm_freq_mult@media-freq@gt0.html
- shard-tglb: NOTRUN -> [SKIP][31] ([i915#6590])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb5/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109289]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb2/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: NOTRUN -> [WARN][33] ([i915#2684])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
- shard-tglb: NOTRUN -> [WARN][34] ([i915#2681])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb7/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-tglb: NOTRUN -> [SKIP][35] ([fdo#109303])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb5/igt@i915_query@query-topology-known-pci-ids.html
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109303])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb5/igt@i915_query@query-topology-known-pci-ids.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#180])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-apl2/igt@i915_suspend@debugfs-reader.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl2/igt@i915_suspend@debugfs-reader.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1:
- shard-glk: [PASS][39] -> [FAIL][40] ([i915#2521])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-glk7/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk3/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
* igt@kms_atomic@atomic_plane_damage:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#4765])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb8/igt@kms_atomic@atomic_plane_damage.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][42] ([i915#5286])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb3/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
- shard-iclb: NOTRUN -> [SKIP][43] ([i915#5286])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb4/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#110725] / [fdo#111614])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb1/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-0:
- shard-glk: [PASS][45] -> [FAIL][46] ([i915#5138])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-glk5/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk6/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-tglb: NOTRUN -> [SKIP][47] ([fdo#111615]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#110723])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_joiner@2x-modeset:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#2705])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb5/igt@kms_big_joiner@2x-modeset.html
* igt@kms_big_joiner@basic:
- shard-iclb: NOTRUN -> [SKIP][50] ([i915#2705]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb3/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#3886]) +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl2/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109278]) +17 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_dg2_rc_ccs:
- shard-tglb: NOTRUN -> [SKIP][53] ([i915#3689] / [i915#6095]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb5/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109278] / [i915#3886]) +3 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb1/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][55] ([i915#3689]) +5 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb3/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
- shard-tglb: NOTRUN -> [SKIP][56] ([i915#6095]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb7/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#3886]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
- shard-tglb: NOTRUN -> [SKIP][58] ([i915#3689] / [i915#3886])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb7/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-frame-dump:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [fdo#111827]) +5 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl7/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_chamelium@hdmi-hpd-after-suspend:
- shard-tglb: NOTRUN -> [SKIP][60] ([fdo#109284] / [fdo#111827]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb3/igt@kms_chamelium@hdmi-hpd-after-suspend.html
- shard-glk: NOTRUN -> [SKIP][61] ([fdo#109271] / [fdo#111827]) +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk1/igt@kms_chamelium@hdmi-hpd-after-suspend.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-snb: NOTRUN -> [SKIP][62] ([fdo#109271] / [fdo#111827]) +4 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-snb4/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109284] / [fdo#111827]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb7/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_color@ctm-0-75@pipe-a-edp-1:
- shard-iclb: NOTRUN -> [FAIL][64] ([i915#315] / [i915#6946]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb6/igt@kms_color@ctm-0-75@pipe-a-edp-1.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-iclb: NOTRUN -> [SKIP][65] ([i915#3116])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb4/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@lic@pipe-a-dp-1:
- shard-apl: NOTRUN -> [INCOMPLETE][66] ([i915#7121] / [i915#7173])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl2/igt@kms_content_protection@lic@pipe-a-dp-1.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#3359])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb3/igt@kms_cursor_crc@cursor-onscreen-512x512.html
- shard-tglb: NOTRUN -> [SKIP][68] ([i915#3359])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb7/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271]) +114 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl7/igt@kms_cursor_crc@cursor-sliding-32x32.html
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#3555]) +4 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb2/igt@kms_cursor_crc@cursor-sliding-32x32.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-tglb: NOTRUN -> [SKIP][71] ([fdo#109274] / [fdo#111825])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb2/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#7205])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl6/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-iclb: NOTRUN -> [SKIP][73] ([fdo#109274]) +3 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb1/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-tglb: NOTRUN -> [SKIP][74] ([fdo#109274] / [fdo#111825] / [i915#3637]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb3/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][75] ([i915#2587] / [i915#2672]) +4 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#2587] / [i915#2672]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][77] ([i915#2672]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][78] ([i915#6497]) +4 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-glk: NOTRUN -> [SKIP][79] ([fdo#109271]) +82 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109280]) +23 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-fullscreen:
- shard-tglb: NOTRUN -> [SKIP][81] ([fdo#109280] / [fdo#111825]) +16 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-fullscreen.html
* igt@kms_hdr@static-toggle-dpms:
- shard-iclb: NOTRUN -> [SKIP][82] ([i915#3555]) +5 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb1/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_invalid_mode@zero-hdisplay (NEW):
- {shard-rkl}: NOTRUN -> [SKIP][83] ([i915#1845] / [i915#4098]) +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-rkl-2/igt@kms_invalid_mode@zero-hdisplay.html
* igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
- shard-tglb: NOTRUN -> [SKIP][84] ([fdo#109289])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb7/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html
* igt@kms_plane_lowres@tiling-yf@pipe-b-edp-1:
- shard-iclb: NOTRUN -> [SKIP][85] ([i915#3536]) +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb5/igt@kms_plane_lowres@tiling-yf@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-edp-1:
- shard-iclb: NOTRUN -> [SKIP][86] ([i915#5176]) +5 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-d-edp-1:
- shard-tglb: NOTRUN -> [SKIP][87] ([i915#5176]) +3 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb8/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-edp-1:
- shard-iclb: NOTRUN -> [SKIP][88] ([i915#5235]) +2 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb4/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-edp-1:
- shard-tglb: NOTRUN -> [SKIP][89] ([i915#5235]) +3 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb3/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-edp-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][90] -> [SKIP][91] ([i915#5235]) +2 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_prime@basic-crc-hybrid:
- shard-iclb: NOTRUN -> [SKIP][92] ([i915#6524])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb2/igt@kms_prime@basic-crc-hybrid.html
- shard-tglb: NOTRUN -> [SKIP][93] ([i915#6524])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb8/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: NOTRUN -> [SKIP][94] ([i915#2920])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#111068] / [i915#658]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#658]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
- shard-snb: NOTRUN -> [SKIP][97] ([fdo#109271]) +150 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-snb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
- shard-tglb: NOTRUN -> [SKIP][98] ([i915#2920]) +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
- shard-glk: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#658]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
- shard-iclb: NOTRUN -> [SKIP][100] ([i915#658])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][101] -> [SKIP][102] ([fdo#109441])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109441])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
* igt@prime_vgem@fence-read-hang:
- shard-iclb: NOTRUN -> [SKIP][104] ([fdo#109295])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb8/igt@prime_vgem@fence-read-hang.html
- shard-tglb: NOTRUN -> [SKIP][105] ([fdo#109295])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb6/igt@prime_vgem@fence-read-hang.html
* igt@sysfs_clients@pidname:
- shard-apl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2994]) +2 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl3/igt@sysfs_clients@pidname.html
- shard-tglb: NOTRUN -> [SKIP][107] ([i915#2994]) +2 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb2/igt@sysfs_clients@pidname.html
- shard-glk: NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#2994]) +2 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk9/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@split-10:
- shard-iclb: NOTRUN -> [SKIP][109] ([i915#2994]) +3 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb2/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@i915_suspend@basic-s3-without-i915:
- shard-snb: [INCOMPLETE][110] ([i915#4528] / [i915#4817]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-snb6/igt@i915_suspend@basic-s3-without-i915.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-snb7/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][112] ([i915#2346]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][114] ([i915#79]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-apl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-apl2/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl7/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [SKIP][118] ([fdo#109441]) -> [PASS][119] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb5/igt@kms_psr@psr2_cursor_plane_onoff.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
#### Warnings ####
* igt@gem_pwrite@basic-exhaustion:
- shard-tglb: [INCOMPLETE][120] ([i915#7248]) -> [WARN][121] ([i915#2658])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-tglb5/igt@gem_pwrite@basic-exhaustion.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-tglb2/igt@gem_pwrite@basic-exhaustion.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][122] ([i915#180] / [i915#1982] / [i915#4939]) -> [INCOMPLETE][123] ([i915#180] / [i915#4939])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@runner@aborted:
- shard-iclb: ([FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130]) ([i915#3002] / [i915#4312]) -> ([FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#3002] / [i915#4312] / [i915#7300])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb8/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb7/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb4/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb3/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb3/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb4/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12272/shard-iclb6/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb8/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb7/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb7/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb6/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb5/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb5/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb5/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/shard-iclb2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4765]: https://gitlab.freedesktop.org/drm/intel/issues/4765
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7036]: https://gitlab.freedesktop.org/drm/intel/issues/7036
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7121]: https://gitlab.freedesktop.org/drm/intel/issues/7121
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
[i915#7205]: https://gitlab.freedesktop.org/drm/intel/issues/7205
[i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
[i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
[i915#7300]: https://gitlab.freedesktop.org/drm/intel/issues/7300
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7021 -> IGTPW_7996
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12272: 168aff13f677d0e72ad071851f2305a836696ae3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7996: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/index.html
IGT_7021: b99f94fc3652f6838b8803032373a419372b17b1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7996/index.html
[-- Attachment #2: Type: text/html, Size: 118313 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/3] lib/intel_batchbuffer: Extend __intel_bb_create to handle context config
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_batchbuffer: Extend __intel_bb_create to handle context config Karolina Drobnik
@ 2022-10-24 6:37 ` Zbigniew Kempczyński
2022-10-24 12:55 ` Karolina Drobnik
0 siblings, 1 reply; 14+ messages in thread
From: Zbigniew Kempczyński @ 2022-10-24 6:37 UTC (permalink / raw)
To: Karolina Drobnik; +Cc: igt-dev
On Fri, Oct 21, 2022 at 10:54:41AM +0200, Karolina Drobnik wrote:
> Currently, intel_bb stores context id with no information about the context
> itself. This means that intel batchbuffer can only execute on a fixed set
> of engines with pre-defined indices (so called legacy mode). To accommodate
> contexts with custom engine layouts, save the context configuration in
> intel_bb struct.
>
> Update function calls to reflect that change.
>
> Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
> ---
> lib/igt_draw.c | 2 +-
> lib/intel_batchbuffer.c | 41 ++++++++++++++++++++++-----------
> lib/intel_batchbuffer.h | 6 ++++-
> lib/media_fill.c | 2 +-
> tests/i915/api_intel_bb.c | 2 +-
> tests/i915/gem_ppgtt.c | 2 +-
> tests/i915/gem_pxp.c | 16 ++++++-------
> tests/i915/kms_fence_pin_leak.c | 2 +-
> tests/i915/perf.c | 18 +++++++--------
> 9 files changed, 55 insertions(+), 36 deletions(-)
>
> diff --git a/lib/igt_draw.c b/lib/igt_draw.c
> index 1124cadc..975d65cd 100644
> --- a/lib/igt_draw.c
> +++ b/lib/igt_draw.c
> @@ -780,7 +780,7 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
>
> src = create_buf(fd, cmd_data->bops, &tmp, I915_TILING_NONE);
> dst = create_buf(fd, cmd_data->bops, buf, tiling);
> - ibb = intel_bb_create_with_context(fd, cmd_data->ctx, PAGE_SIZE);
> + ibb = intel_bb_create_with_context(fd, cmd_data->ctx, NULL, PAGE_SIZE);
>
> rendercopy(ibb, src, 0, 0, rect->w, rect->h, dst, rect->x, rect->y);
>
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index bb2503bb..70d819aa 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -1304,7 +1304,8 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
> /**
> * __intel_bb_create:
> * @i915: drm fd
> - * @ctx: context
> + * @ctx: context id
> + * @cfg: intel_ctx configuration, NULL for default context or legacy mode
> * @size: size of the batchbuffer
> * @do_relocs: use relocations or allocator
> * @allocator_type: allocator type, must be INTEL_ALLOCATOR_NONE for relocations
> @@ -1338,18 +1339,22 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
> *
> * If we do reset with purging caches allocator entries are freed as well.
> *
> + * __intel_bb_create checks if a context configuration for intel_ctx_t was
> + * passed in. If this is the case, it copies the information over to the
> + * newly created batch buffer.
> + *
> * Returns:
> *
> * Pointer the intel_bb, asserts on failure.
> */
> static struct intel_bb *
> -__intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
> +__intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
> + uint32_t size, bool do_relocs,
> uint64_t start, uint64_t end,
> uint8_t allocator_type, enum allocator_strategy strategy)
> {
> struct drm_i915_gem_exec_object2 *object;
> struct intel_bb *ibb = calloc(1, sizeof(*ibb));
> -
Noise.
> igt_assert(ibb);
>
> ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
> @@ -1399,6 +1404,13 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
> ibb->ptr = ibb->batch;
> ibb->fence = -1;
>
> + /* Cache context configuration */
> + if (cfg) {
> + ibb->cfg = malloc(sizeof(*cfg));
> + igt_assert(ibb->cfg);
> + memcpy(ibb->cfg, cfg, sizeof(*cfg));
> + }
> +
> ibb->gtt_size = gem_aperture_size(i915);
> if ((ibb->gtt_size - 1) >> 32)
> ibb->supports_48b_address = true;
> @@ -1446,7 +1458,7 @@ struct intel_bb *intel_bb_create_full(int i915, uint32_t ctx, uint32_t size,
> uint8_t allocator_type,
> enum allocator_strategy strategy)
> {
> - return __intel_bb_create(i915, ctx, size, false, start, end,
> + return __intel_bb_create(i915, ctx, NULL, size, false, start, end,
> allocator_type, strategy);
> }
>
> @@ -1469,7 +1481,7 @@ struct intel_bb *intel_bb_create_with_allocator(int i915, uint32_t ctx,
> uint32_t size,
> uint8_t allocator_type)
> {
> - return __intel_bb_create(i915, ctx, size, false, 0, 0,
> + return __intel_bb_create(i915, ctx, NULL, size, false, 0, 0,
> allocator_type, ALLOC_STRATEGY_HIGH_TO_LOW);
> }
>
> @@ -1502,7 +1514,7 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
> {
> bool relocs = gem_has_relocations(i915);
>
> - return __intel_bb_create(i915, 0, size,
> + return __intel_bb_create(i915, 0, NULL, size,
> relocs && !aux_needs_softpin(i915), 0, 0,
> INTEL_ALLOCATOR_SIMPLE,
> ALLOC_STRATEGY_HIGH_TO_LOW);
> @@ -1511,21 +1523,23 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
> /**
> * intel_bb_create_with_context:
> * @i915: drm fd
> - * @ctx: context
> + * @ctx: context id
> + * @cfg: intel_ctx configuration, NULL for default context or legacy mode
> * @size: size of the batchbuffer
> *
> - * Creates bb with context passed in @ctx.
> + * Creates bb with context passed in @ctx and @cfg configuration (when
> + * working with custom engines layout).
> *
> * Returns:
> *
> * Pointer the intel_bb, asserts on failure.
> */
> struct intel_bb *
> -intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size)
> +intel_bb_create_with_context(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg, uint32_t size)
> {
> bool relocs = gem_has_relocations(i915);
>
> - return __intel_bb_create(i915, ctx, size,
> + return __intel_bb_create(i915, ctx, cfg, size,
> relocs && !aux_needs_softpin(i915), 0, 0,
> INTEL_ALLOCATOR_SIMPLE,
> ALLOC_STRATEGY_HIGH_TO_LOW);
> @@ -1547,7 +1561,7 @@ struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
> {
> igt_require(gem_has_relocations(i915));
>
> - return __intel_bb_create(i915, 0, size, true, 0, 0,
> + return __intel_bb_create(i915, 0, NULL, size, true, 0, 0,
> INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
> }
>
> @@ -1569,7 +1583,7 @@ intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size)
> {
> igt_require(gem_has_relocations(i915));
>
> - return __intel_bb_create(i915, ctx, size, true, 0, 0,
> + return __intel_bb_create(i915, ctx, NULL, size, true, 0, 0,
> INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
Currently this function is not used but if it would ctx + NULL (cfg) might
be not correct. I think you should extend it with cfg.
--
Zbigniew
> }
>
> @@ -1589,7 +1603,7 @@ struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size)
> {
> igt_require(gem_uses_full_ppgtt(i915));
>
> - return __intel_bb_create(i915, 0, size, false, 0, 0,
> + return __intel_bb_create(i915, 0, NULL, size, false, 0, 0,
> INTEL_ALLOCATOR_SIMPLE,
> ALLOC_STRATEGY_HIGH_TO_LOW);
> }
> @@ -1670,6 +1684,7 @@ void intel_bb_destroy(struct intel_bb *ibb)
> close(ibb->fence);
>
> free(ibb->batch);
> + free(ibb->cfg);
> free(ibb);
> }
>
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index 36b6b61d..68054495 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -486,6 +486,9 @@ struct intel_bb {
> uint32_t ctx;
> uint32_t vm_id;
>
> + /* Context configuration */
> + intel_ctx_cfg_t *cfg;
> +
> /* Cache */
> void *root;
>
> @@ -522,7 +525,8 @@ intel_bb_create_with_allocator(int i915, uint32_t ctx,
> uint32_t size, uint8_t allocator_type);
> struct intel_bb *intel_bb_create(int i915, uint32_t size);
> struct intel_bb *
> -intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size);
> +intel_bb_create_with_context(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
> + uint32_t size);
> struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
> struct intel_bb *
> intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size);
> diff --git a/lib/media_fill.c b/lib/media_fill.c
> index d758f1f5..4f8b50e8 100644
> --- a/lib/media_fill.c
> +++ b/lib/media_fill.c
> @@ -309,7 +309,7 @@ __gen11_media_vme_func(int i915,
> struct intel_bb *ibb;
> uint32_t curbe_buffer, interface_descriptor;
>
> - ibb = intel_bb_create_with_context(i915, ctx, PAGE_SIZE);
> + ibb = intel_bb_create_with_context(i915, ctx, NULL, PAGE_SIZE);
> intel_bb_add_intel_buf(ibb, dst, true);
> intel_bb_add_intel_buf(ibb, src, false);
>
> diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
> index 1f663d2a..6ba1fd1b 100644
> --- a/tests/i915/api_intel_bb.c
> +++ b/tests/i915/api_intel_bb.c
> @@ -202,7 +202,7 @@ static void simple_bb(struct buf_ops *bops, bool use_context)
> if (use_context) {
> ctx = gem_context_create(i915);
> intel_bb_destroy(ibb);
> - ibb = intel_bb_create_with_context(i915, ctx, PAGE_SIZE);
> + ibb = intel_bb_create_with_context(i915, ctx, NULL, PAGE_SIZE);
> intel_bb_out(ibb, MI_BATCH_BUFFER_END);
> intel_bb_ptr_align(ibb, 8);
> intel_bb_exec(ibb, intel_bb_offset(ibb),
> diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
> index 0a06e9ec..9673ce22 100644
> --- a/tests/i915/gem_ppgtt.c
> +++ b/tests/i915/gem_ppgtt.c
> @@ -112,7 +112,7 @@ static void fork_rcs_copy(int timeout, uint32_t final,
> ctx = gem_context_create(buf_ops_get_fd(dst[child]->bops));
>
> ibb = intel_bb_create_with_context(buf_ops_get_fd(dst[child]->bops),
> - ctx, 4096);
> + ctx, NULL, 4096);
> i = 0;
> igt_until_timeout(timeout) {
> src = create_bo(dst[child]->bops,
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index 65618556..b43273c9 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -457,7 +457,7 @@ static void test_render_baseline(int i915)
> /* Perform a regular 3d copy as a control checkpoint */
> ret = create_ctx_with_params(i915, false, false, false, false, &ctx);
> igt_assert_eq(ret, 0);
> - ibb = intel_bb_create_with_context(i915, ctx, 4096);
> + ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
> igt_assert(ibb);
>
> dstbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_INITCOLOR1);
> @@ -506,7 +506,7 @@ static void __test_render_pxp_src_to_protdest(int i915, uint32_t *outpixels, int
> ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
> igt_assert_eq(ret, 0);
> igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
> - ibb = intel_bb_create_with_context(i915, ctx, 4096);
> + ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
> igt_assert(ibb);
> intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
>
> @@ -567,7 +567,7 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
> ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
> igt_assert_eq(ret, 0);
> igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
> - ibb = intel_bb_create_with_context(i915, ctx, 4096);
> + ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
> igt_assert(ibb);
> intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
>
> @@ -655,7 +655,7 @@ static void test_pxp_dmabuffshare_refcnt(void)
> ret = create_ctx_with_params(fd[n], true, true, true, false, &ctx[n]);
> igt_assert_eq(ret, 0);
> igt_assert_eq(get_ctx_protected_param(fd[n], ctx[n]), 1);
> - ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], 4096);
> + ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], NULL, 4096);
> intel_bb_set_pxp(ibb[n], true, DISPLAY_APPTYPE,
> I915_PROTECTED_CONTENT_DEFAULT_SESSION);
>
> @@ -820,7 +820,7 @@ static void prepare_exec_assets(int i915, struct simple_exec_assets *data, bool
> ret = create_ctx_with_params(i915, false, false, false, false, &(data->ctx));
> igt_assert_eq(ret, 0);
> igt_assert_eq(get_ctx_protected_param(i915, data->ctx), ctx_pxp);
> - data->ibb = intel_bb_create_with_context(i915, data->ctx, 4096);
> + data->ibb = intel_bb_create_with_context(i915, data->ctx, NULL, 4096);
> igt_assert(data->ibb);
>
> data->fencebo = alloc_and_fill_dest_buff(i915, buf_pxp, 4096, 0);
> @@ -900,7 +900,7 @@ static void test_pxp_stale_buf_execution(int i915)
> ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
> igt_assert_eq(ret, 0);
> igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
> - ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
> + ibb2 = intel_bb_create_with_context(i915, ctx2, NULL, 4096);
> igt_assert(ibb2);
> intel_bb_remove_intel_buf(data.ibb, data.fencebuf);
> intel_bb_add_intel_buf(ibb2, data.fencebuf, true);
> @@ -979,7 +979,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
> ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
> igt_assert_eq(ret, 0);
> igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
> - ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
> + ibb2 = intel_bb_create_with_context(i915, ctx2, NULL, 4096);
> igt_assert(ibb2);
> intel_bb_remove_intel_buf(data[1].ibb, data[1].fencebuf);
> intel_bb_add_intel_buf(ibb2, data[1].fencebuf, true);
> @@ -1043,7 +1043,7 @@ static void setup_protected_fb(int i915, int width, int height, igt_fb_t *fb, ui
> fb->plane_bpp[0], 0,
> igt_fb_mod_to_tiling(fb->modifier), 0);
>
> - ibb = intel_bb_create_with_context(i915, ctx, 4096);
> + ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
> igt_assert(ibb);
>
> ibb->pxp.enabled = true;
> diff --git a/tests/i915/kms_fence_pin_leak.c b/tests/i915/kms_fence_pin_leak.c
> index f1eac1c6..1972a699 100644
> --- a/tests/i915/kms_fence_pin_leak.c
> +++ b/tests/i915/kms_fence_pin_leak.c
> @@ -62,7 +62,7 @@ static void exec_nop(data_t *data, struct igt_fb *fb, uint32_t ctx)
> intel_buf_set_ownership(dst, true);
>
> ibb = intel_bb_create_with_context(buf_ops_get_fd(data->bops),
> - ctx, 4096);
> + ctx, NULL, 4096);
>
> /* add the reloc to make sure the kernel will think we write to dst */
> intel_bb_add_intel_buf(ibb, dst, true);
> diff --git a/tests/i915/perf.c b/tests/i915/perf.c
> index 5502a3fb..9ef52690 100644
> --- a/tests/i915/perf.c
> +++ b/tests/i915/perf.c
> @@ -1586,7 +1586,7 @@ static void load_helper_init(void)
> lh.context_id = gem_context_create(drm_fd);
> igt_assert_neq(lh.context_id, 0xffffffff);
>
> - lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, BATCH_SZ);
> + lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, NULL, BATCH_SZ);
>
> scratch_buf_init(lh.bops, &lh.dst, 1920, 1080, 0);
> scratch_buf_init(lh.bops, &lh.src, 1920, 1080, 0);
> @@ -3011,7 +3011,7 @@ gen12_test_mi_rpc(void)
> igt_assert_neq(ctx_id, INVALID_CTX_ID);
> properties[1] = ctx_id;
>
> - ibb = intel_bb_create_with_context(drm_fd, ctx_id, BATCH_SZ);
> + ibb = intel_bb_create_with_context(drm_fd, ctx_id, NULL, BATCH_SZ);
> buf = intel_buf_create(bops, 4096, 1, 8, 64,
> I915_TILING_NONE, I915_COMPRESSION_NONE);
>
> @@ -3090,7 +3090,7 @@ test_mi_rpc(void)
>
> ctx_id = gem_context_create(drm_fd);
>
> - ibb = intel_bb_create_with_context(drm_fd, ctx_id, BATCH_SZ);
> + ibb = intel_bb_create_with_context(drm_fd, ctx_id, NULL, BATCH_SZ);
> buf = intel_buf_create(bops, 4096, 1, 8, 64,
> I915_TILING_NONE, I915_COMPRESSION_NONE);
>
> @@ -3217,8 +3217,8 @@ hsw_test_single_ctx_counters(void)
> */
> context0_id = gem_context_create(drm_fd);
> context1_id = gem_context_create(drm_fd);
> - ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
> - ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
> + ibb0 = intel_bb_create_with_context(drm_fd, context0_id, NULL, BATCH_SZ);
> + ibb1 = intel_bb_create_with_context(drm_fd, context1_id, NULL, BATCH_SZ);
>
> igt_debug("submitting warm up render_copy\n");
>
> @@ -3461,8 +3461,8 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>
> context0_id = gem_context_create(drm_fd);
> context1_id = gem_context_create(drm_fd);
> - ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
> - ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
> + ibb0 = intel_bb_create_with_context(drm_fd, context0_id, NULL, BATCH_SZ);
> + ibb1 = intel_bb_create_with_context(drm_fd, context1_id, NULL, BATCH_SZ);
>
> igt_debug("submitting warm up render_copy\n");
>
> @@ -3866,8 +3866,8 @@ static void gen12_single_ctx_helper(void)
>
> context0_id = gem_context_create(drm_fd);
> context1_id = gem_context_create(drm_fd);
> - ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
> - ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
> + ibb0 = intel_bb_create_with_context(drm_fd, context0_id, NULL, BATCH_SZ);
> + ibb1 = intel_bb_create_with_context(drm_fd, context1_id, NULL, BATCH_SZ);
>
> igt_debug("submitting warm up render_copy\n");
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/3] lib/intel_batchbuffer: Add support for custom engine layouts
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_batchbuffer: Add support for custom engine layouts Karolina Drobnik
@ 2022-10-24 6:40 ` Zbigniew Kempczyński
2022-10-24 13:16 ` Karolina Drobnik
0 siblings, 1 reply; 14+ messages in thread
From: Zbigniew Kempczyński @ 2022-10-24 6:40 UTC (permalink / raw)
To: Karolina Drobnik; +Cc: igt-dev
On Fri, Oct 21, 2022 at 10:54:42AM +0200, Karolina Drobnik wrote:
> Don't assume fixed engine ids and use context configuration in
> intel_bb to find the appropriate engine when executing the batchbuffer.
>
> Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
> ---
> lib/intel_batchbuffer.c | 45 +++++++++++++++++++++++++++++++++--------
> 1 file changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index 70d819aa..20b7e255 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -1490,6 +1490,31 @@ static bool aux_needs_softpin(int i915)
> return intel_gen(intel_get_drm_devid(i915)) >= 12;
> }
>
> +static bool has_ctx_cfg(struct intel_bb *ibb)
> +{
> + return ibb->cfg && (ibb->cfg->num_engines > 0);
> +}
> +
> +static bool find_engine(struct intel_bb *ibb, unsigned int class, uint32_t *ring)
Why not:
static uint32_t find_engine(struct intel_bb *ibb, unsigned int class)
then all logic with selecting legacy/user engine hide here in the
implementation? Especially you're not using return value in any form.
--
Zbigniew
> +{
> + intel_ctx_cfg_t *cfg;
> + int i;
> +
> + /* Use legacy engines when there is no context config */
> + if (!has_ctx_cfg(ibb))
> + return false;
> +
> + cfg = ibb->cfg;
> + for (i = 0; i < cfg->num_engines; i++) {
> + if (cfg->engines[i].engine_class == class) {
> + *ring = i;
> + return true;
> + }
> + }
> +
> + return false;
> +}
> +
> /**
> * intel_bb_create:
> * @i915: drm fd
> @@ -2790,34 +2815,38 @@ void intel_bb_flush(struct intel_bb *ibb, uint32_t ring)
> * intel_bb_flush_render:
> * @ibb: batchbuffer
> *
> - * If batch is not empty emit batch buffer end, execute on render ring
> - * and reset the batch. Context used to execute is batch context.
> + * If batch is not empty emit batch buffer end, find the render engine id,
> + * execute on the ring and reset the batch. Context used to execute
> + * is batch context.
> */
> void intel_bb_flush_render(struct intel_bb *ibb)
> {
> + uint32_t ring = I915_EXEC_RENDER;
> +
> if (intel_bb_emit_flush_common(ibb) == 0)
> return;
>
> - intel_bb_exec_with_ring(ibb, I915_EXEC_RENDER);
> + find_engine(ibb, I915_ENGINE_CLASS_RENDER, &ring);
> + intel_bb_exec_with_ring(ibb, ring);
> }
>
> /*
> * intel_bb_flush_blit:
> * @ibb: batchbuffer
> *
> - * If batch is not empty emit batch buffer end, execute on default/blit ring
> - * (depends on gen) and reset the batch.
> + * If batch is not empty emit batch buffer end, find a suitable ring
> + * (depending on gen and context configuration) and reset the batch.
> * Context used to execute is batch context.
> */
> void intel_bb_flush_blit(struct intel_bb *ibb)
> {
> - uint32_t ring = I915_EXEC_DEFAULT;
> + uint32_t ring;
>
> if (intel_bb_emit_flush_common(ibb) == 0)
> return;
>
> - if (HAS_BLT_RING(ibb->devid))
> - ring = I915_EXEC_BLT;
> + ring = HAS_BLT_RING(ibb->devid) ? I915_EXEC_BLT : I915_EXEC_DEFAULT;
> + find_engine(ibb, I915_ENGINE_CLASS_COPY, &ring);
>
> intel_bb_exec_with_ring(ibb, ring);
> }
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/3] tests/api_intel_bb: Add misplaced_blitter test
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 3/3] tests/api_intel_bb: Add misplaced_blitter test Karolina Drobnik
@ 2022-10-24 6:46 ` Zbigniew Kempczyński
2022-10-24 13:19 ` Karolina Drobnik
0 siblings, 1 reply; 14+ messages in thread
From: Zbigniew Kempczyński @ 2022-10-24 6:46 UTC (permalink / raw)
To: Karolina Drobnik; +Cc: igt-dev
On Fri, Oct 21, 2022 at 10:54:43AM +0200, Karolina Drobnik wrote:
> Exercise intel_bb with a custom context engines layout.
>
> Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
> ---
> tests/i915/api_intel_bb.c | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
> index 6ba1fd1b..42959880 100644
> --- a/tests/i915/api_intel_bb.c
> +++ b/tests/i915/api_intel_bb.c
> @@ -1209,6 +1209,36 @@ static void full_batch(struct buf_ops *bops)
> intel_bb_destroy(ibb);
> }
>
> +static void misplaced_blitter(struct buf_ops *bops)
> +{
> + int i915 = buf_ops_get_fd(bops);
> + struct intel_bb *ibb;
> +
> + gem_require_contexts(i915);
> +
> + /* Use custom configuration with blitter at index 0 */
> + const intel_ctx_cfg_t cfg = (intel_ctx_cfg_t) {
> + .num_engines = 2,
> + .engines = {
> + { .engine_class = I915_ENGINE_CLASS_COPY,
> + .engine_instance = 0
> + },
> + { .engine_class = I915_ENGINE_CLASS_RENDER,
> + .engine_instance = 0
> + },
> + },
> + };
> + const intel_ctx_t *ctx = intel_ctx_create(i915, &cfg);
> +
> + ibb = intel_bb_create_with_context(i915, ctx->id, &ctx->cfg, PAGE_SIZE);
> +
> + intel_bb_emit_bbe(ibb);
> + intel_bb_flush_blit(ibb);
BBE will work on each engine, can you prove it was executed on blitter?
--
Zbigniew
> +
> + intel_bb_destroy(ibb);
> + intel_ctx_destroy(i915, ctx);
> +}
> +
> static int render(struct buf_ops *bops, uint32_t tiling, bool do_reloc,
> uint32_t width, uint32_t height)
> {
> @@ -1581,6 +1611,10 @@ igt_main_args("dpibc:", NULL, help_str, opt_handler, NULL)
> igt_subtest("full-batch")
> full_batch(bops);
>
> + igt_describe("Execute intel_bb with set of engines provided by userspace");
> + igt_subtest("misplaced-blitter")
> + misplaced_blitter(bops);
> +
> igt_subtest_with_dynamic("render") {
> for (i = 0; i < ARRAY_SIZE(tests); i++) {
> const struct test *t = &tests[i];
> --
> 2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/3] lib/intel_batchbuffer: Extend __intel_bb_create to handle context config
2022-10-24 6:37 ` Zbigniew Kempczyński
@ 2022-10-24 12:55 ` Karolina Drobnik
0 siblings, 0 replies; 14+ messages in thread
From: Karolina Drobnik @ 2022-10-24 12:55 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 24.10.2022 08:37, Zbigniew Kempczyński wrote:
> On Fri, Oct 21, 2022 at 10:54:41AM +0200, Karolina Drobnik wrote:
>> Currently, intel_bb stores context id with no information about the context
>> itself. This means that intel batchbuffer can only execute on a fixed set
>> of engines with pre-defined indices (so called legacy mode). To accommodate
>> contexts with custom engine layouts, save the context configuration in
>> intel_bb struct.
>>
>> Update function calls to reflect that change.
>>
>> Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
>> ---
>> lib/igt_draw.c | 2 +-
>> lib/intel_batchbuffer.c | 41 ++++++++++++++++++++++-----------
>> lib/intel_batchbuffer.h | 6 ++++-
>> lib/media_fill.c | 2 +-
>> tests/i915/api_intel_bb.c | 2 +-
>> tests/i915/gem_ppgtt.c | 2 +-
>> tests/i915/gem_pxp.c | 16 ++++++-------
>> tests/i915/kms_fence_pin_leak.c | 2 +-
>> tests/i915/perf.c | 18 +++++++--------
>> 9 files changed, 55 insertions(+), 36 deletions(-)
>>
>> diff --git a/lib/igt_draw.c b/lib/igt_draw.c
>> index 1124cadc..975d65cd 100644
>> --- a/lib/igt_draw.c
>> +++ b/lib/igt_draw.c
>> @@ -780,7 +780,7 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
>>
>> src = create_buf(fd, cmd_data->bops, &tmp, I915_TILING_NONE);
>> dst = create_buf(fd, cmd_data->bops, buf, tiling);
>> - ibb = intel_bb_create_with_context(fd, cmd_data->ctx, PAGE_SIZE);
>> + ibb = intel_bb_create_with_context(fd, cmd_data->ctx, NULL, PAGE_SIZE);
>>
>> rendercopy(ibb, src, 0, 0, rect->w, rect->h, dst, rect->x, rect->y);
>>
>> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
>> index bb2503bb..70d819aa 100644
>> --- a/lib/intel_batchbuffer.c
>> +++ b/lib/intel_batchbuffer.c
>> @@ -1304,7 +1304,8 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
>> /**
>> * __intel_bb_create:
>> * @i915: drm fd
>> - * @ctx: context
>> + * @ctx: context id
>> + * @cfg: intel_ctx configuration, NULL for default context or legacy mode
>> * @size: size of the batchbuffer
>> * @do_relocs: use relocations or allocator
>> * @allocator_type: allocator type, must be INTEL_ALLOCATOR_NONE for relocations
>> @@ -1338,18 +1339,22 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
>> *
>> * If we do reset with purging caches allocator entries are freed as well.
>> *
>> + * __intel_bb_create checks if a context configuration for intel_ctx_t was
>> + * passed in. If this is the case, it copies the information over to the
>> + * newly created batch buffer.
>> + *
>> * Returns:
>> *
>> * Pointer the intel_bb, asserts on failure.
>> */
>> static struct intel_bb *
>> -__intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
>> +__intel_bb_create(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
>> + uint32_t size, bool do_relocs,
>> uint64_t start, uint64_t end,
>> uint8_t allocator_type, enum allocator_strategy strategy)
>> {
>> struct drm_i915_gem_exec_object2 *object;
>> struct intel_bb *ibb = calloc(1, sizeof(*ibb));
>> -
>
> Noise.
Whoops
>> igt_assert(ibb);
>>
>> ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
>> @@ -1399,6 +1404,13 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
>> ibb->ptr = ibb->batch;
>> ibb->fence = -1;
>>
>> + /* Cache context configuration */
>> + if (cfg) {
>> + ibb->cfg = malloc(sizeof(*cfg));
>> + igt_assert(ibb->cfg);
>> + memcpy(ibb->cfg, cfg, sizeof(*cfg));
>> + }
>> +
>> ibb->gtt_size = gem_aperture_size(i915);
>> if ((ibb->gtt_size - 1) >> 32)
>> ibb->supports_48b_address = true;
>> @@ -1446,7 +1458,7 @@ struct intel_bb *intel_bb_create_full(int i915, uint32_t ctx, uint32_t size,
>> uint8_t allocator_type,
>> enum allocator_strategy strategy)
>> {
>> - return __intel_bb_create(i915, ctx, size, false, start, end,
>> + return __intel_bb_create(i915, ctx, NULL, size, false, start, end,
>> allocator_type, strategy);
>> }
>>
>> @@ -1469,7 +1481,7 @@ struct intel_bb *intel_bb_create_with_allocator(int i915, uint32_t ctx,
>> uint32_t size,
>> uint8_t allocator_type)
>> {
>> - return __intel_bb_create(i915, ctx, size, false, 0, 0,
>> + return __intel_bb_create(i915, ctx, NULL, size, false, 0, 0,
>> allocator_type, ALLOC_STRATEGY_HIGH_TO_LOW);
>> }
>>
>> @@ -1502,7 +1514,7 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
>> {
>> bool relocs = gem_has_relocations(i915);
>>
>> - return __intel_bb_create(i915, 0, size,
>> + return __intel_bb_create(i915, 0, NULL, size,
>> relocs && !aux_needs_softpin(i915), 0, 0,
>> INTEL_ALLOCATOR_SIMPLE,
>> ALLOC_STRATEGY_HIGH_TO_LOW);
>> @@ -1511,21 +1523,23 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
>> /**
>> * intel_bb_create_with_context:
>> * @i915: drm fd
>> - * @ctx: context
>> + * @ctx: context id
>> + * @cfg: intel_ctx configuration, NULL for default context or legacy mode
>> * @size: size of the batchbuffer
>> *
>> - * Creates bb with context passed in @ctx.
>> + * Creates bb with context passed in @ctx and @cfg configuration (when
>> + * working with custom engines layout).
>> *
>> * Returns:
>> *
>> * Pointer the intel_bb, asserts on failure.
>> */
>> struct intel_bb *
>> -intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size)
>> +intel_bb_create_with_context(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg, uint32_t size)
>> {
>> bool relocs = gem_has_relocations(i915);
>>
>> - return __intel_bb_create(i915, ctx, size,
>> + return __intel_bb_create(i915, ctx, cfg, size,
>> relocs && !aux_needs_softpin(i915), 0, 0,
>> INTEL_ALLOCATOR_SIMPLE,
>> ALLOC_STRATEGY_HIGH_TO_LOW);
>> @@ -1547,7 +1561,7 @@ struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size)
>> {
>> igt_require(gem_has_relocations(i915));
>>
>> - return __intel_bb_create(i915, 0, size, true, 0, 0,
>> + return __intel_bb_create(i915, 0, NULL, size, true, 0, 0,
>> INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
>> }
>>
>> @@ -1569,7 +1583,7 @@ intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size)
>> {
>> igt_require(gem_has_relocations(i915));
>>
>> - return __intel_bb_create(i915, ctx, size, true, 0, 0,
>> + return __intel_bb_create(i915, ctx, NULL, size, true, 0, 0,
>> INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
>
> Currently this function is not used but if it would ctx + NULL (cfg) might
> be not correct. I think you should extend it with cfg.
I'll extend intel_bb_create_with_relocs_and_context() with cfg param,
and leave it up to the user to pass context configuration
Thanks,
Karolina
> --
> Zbigniew
>
>> }
>>
>> @@ -1589,7 +1603,7 @@ struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size)
>> {
>> igt_require(gem_uses_full_ppgtt(i915));
>>
>> - return __intel_bb_create(i915, 0, size, false, 0, 0,
>> + return __intel_bb_create(i915, 0, NULL, size, false, 0, 0,
>> INTEL_ALLOCATOR_SIMPLE,
>> ALLOC_STRATEGY_HIGH_TO_LOW);
>> }
>> @@ -1670,6 +1684,7 @@ void intel_bb_destroy(struct intel_bb *ibb)
>> close(ibb->fence);
>>
>> free(ibb->batch);
>> + free(ibb->cfg);
>> free(ibb);
>> }
>>
>> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
>> index 36b6b61d..68054495 100644
>> --- a/lib/intel_batchbuffer.h
>> +++ b/lib/intel_batchbuffer.h
>> @@ -486,6 +486,9 @@ struct intel_bb {
>> uint32_t ctx;
>> uint32_t vm_id;
>>
>> + /* Context configuration */
>> + intel_ctx_cfg_t *cfg;
>> +
>> /* Cache */
>> void *root;
>>
>> @@ -522,7 +525,8 @@ intel_bb_create_with_allocator(int i915, uint32_t ctx,
>> uint32_t size, uint8_t allocator_type);
>> struct intel_bb *intel_bb_create(int i915, uint32_t size);
>> struct intel_bb *
>> -intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size);
>> +intel_bb_create_with_context(int i915, uint32_t ctx, const intel_ctx_cfg_t *cfg,
>> + uint32_t size);
>> struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
>> struct intel_bb *
>> intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size);
>> diff --git a/lib/media_fill.c b/lib/media_fill.c
>> index d758f1f5..4f8b50e8 100644
>> --- a/lib/media_fill.c
>> +++ b/lib/media_fill.c
>> @@ -309,7 +309,7 @@ __gen11_media_vme_func(int i915,
>> struct intel_bb *ibb;
>> uint32_t curbe_buffer, interface_descriptor;
>>
>> - ibb = intel_bb_create_with_context(i915, ctx, PAGE_SIZE);
>> + ibb = intel_bb_create_with_context(i915, ctx, NULL, PAGE_SIZE);
>> intel_bb_add_intel_buf(ibb, dst, true);
>> intel_bb_add_intel_buf(ibb, src, false);
>>
>> diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
>> index 1f663d2a..6ba1fd1b 100644
>> --- a/tests/i915/api_intel_bb.c
>> +++ b/tests/i915/api_intel_bb.c
>> @@ -202,7 +202,7 @@ static void simple_bb(struct buf_ops *bops, bool use_context)
>> if (use_context) {
>> ctx = gem_context_create(i915);
>> intel_bb_destroy(ibb);
>> - ibb = intel_bb_create_with_context(i915, ctx, PAGE_SIZE);
>> + ibb = intel_bb_create_with_context(i915, ctx, NULL, PAGE_SIZE);
>> intel_bb_out(ibb, MI_BATCH_BUFFER_END);
>> intel_bb_ptr_align(ibb, 8);
>> intel_bb_exec(ibb, intel_bb_offset(ibb),
>> diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
>> index 0a06e9ec..9673ce22 100644
>> --- a/tests/i915/gem_ppgtt.c
>> +++ b/tests/i915/gem_ppgtt.c
>> @@ -112,7 +112,7 @@ static void fork_rcs_copy(int timeout, uint32_t final,
>> ctx = gem_context_create(buf_ops_get_fd(dst[child]->bops));
>>
>> ibb = intel_bb_create_with_context(buf_ops_get_fd(dst[child]->bops),
>> - ctx, 4096);
>> + ctx, NULL, 4096);
>> i = 0;
>> igt_until_timeout(timeout) {
>> src = create_bo(dst[child]->bops,
>> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
>> index 65618556..b43273c9 100644
>> --- a/tests/i915/gem_pxp.c
>> +++ b/tests/i915/gem_pxp.c
>> @@ -457,7 +457,7 @@ static void test_render_baseline(int i915)
>> /* Perform a regular 3d copy as a control checkpoint */
>> ret = create_ctx_with_params(i915, false, false, false, false, &ctx);
>> igt_assert_eq(ret, 0);
>> - ibb = intel_bb_create_with_context(i915, ctx, 4096);
>> + ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
>> igt_assert(ibb);
>>
>> dstbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_INITCOLOR1);
>> @@ -506,7 +506,7 @@ static void __test_render_pxp_src_to_protdest(int i915, uint32_t *outpixels, int
>> ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
>> igt_assert_eq(ret, 0);
>> igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
>> - ibb = intel_bb_create_with_context(i915, ctx, 4096);
>> + ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
>> igt_assert(ibb);
>> intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
>>
>> @@ -567,7 +567,7 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
>> ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
>> igt_assert_eq(ret, 0);
>> igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
>> - ibb = intel_bb_create_with_context(i915, ctx, 4096);
>> + ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
>> igt_assert(ibb);
>> intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
>>
>> @@ -655,7 +655,7 @@ static void test_pxp_dmabuffshare_refcnt(void)
>> ret = create_ctx_with_params(fd[n], true, true, true, false, &ctx[n]);
>> igt_assert_eq(ret, 0);
>> igt_assert_eq(get_ctx_protected_param(fd[n], ctx[n]), 1);
>> - ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], 4096);
>> + ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], NULL, 4096);
>> intel_bb_set_pxp(ibb[n], true, DISPLAY_APPTYPE,
>> I915_PROTECTED_CONTENT_DEFAULT_SESSION);
>>
>> @@ -820,7 +820,7 @@ static void prepare_exec_assets(int i915, struct simple_exec_assets *data, bool
>> ret = create_ctx_with_params(i915, false, false, false, false, &(data->ctx));
>> igt_assert_eq(ret, 0);
>> igt_assert_eq(get_ctx_protected_param(i915, data->ctx), ctx_pxp);
>> - data->ibb = intel_bb_create_with_context(i915, data->ctx, 4096);
>> + data->ibb = intel_bb_create_with_context(i915, data->ctx, NULL, 4096);
>> igt_assert(data->ibb);
>>
>> data->fencebo = alloc_and_fill_dest_buff(i915, buf_pxp, 4096, 0);
>> @@ -900,7 +900,7 @@ static void test_pxp_stale_buf_execution(int i915)
>> ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
>> igt_assert_eq(ret, 0);
>> igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
>> - ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
>> + ibb2 = intel_bb_create_with_context(i915, ctx2, NULL, 4096);
>> igt_assert(ibb2);
>> intel_bb_remove_intel_buf(data.ibb, data.fencebuf);
>> intel_bb_add_intel_buf(ibb2, data.fencebuf, true);
>> @@ -979,7 +979,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>> ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
>> igt_assert_eq(ret, 0);
>> igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
>> - ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
>> + ibb2 = intel_bb_create_with_context(i915, ctx2, NULL, 4096);
>> igt_assert(ibb2);
>> intel_bb_remove_intel_buf(data[1].ibb, data[1].fencebuf);
>> intel_bb_add_intel_buf(ibb2, data[1].fencebuf, true);
>> @@ -1043,7 +1043,7 @@ static void setup_protected_fb(int i915, int width, int height, igt_fb_t *fb, ui
>> fb->plane_bpp[0], 0,
>> igt_fb_mod_to_tiling(fb->modifier), 0);
>>
>> - ibb = intel_bb_create_with_context(i915, ctx, 4096);
>> + ibb = intel_bb_create_with_context(i915, ctx, NULL, 4096);
>> igt_assert(ibb);
>>
>> ibb->pxp.enabled = true;
>> diff --git a/tests/i915/kms_fence_pin_leak.c b/tests/i915/kms_fence_pin_leak.c
>> index f1eac1c6..1972a699 100644
>> --- a/tests/i915/kms_fence_pin_leak.c
>> +++ b/tests/i915/kms_fence_pin_leak.c
>> @@ -62,7 +62,7 @@ static void exec_nop(data_t *data, struct igt_fb *fb, uint32_t ctx)
>> intel_buf_set_ownership(dst, true);
>>
>> ibb = intel_bb_create_with_context(buf_ops_get_fd(data->bops),
>> - ctx, 4096);
>> + ctx, NULL, 4096);
>>
>> /* add the reloc to make sure the kernel will think we write to dst */
>> intel_bb_add_intel_buf(ibb, dst, true);
>> diff --git a/tests/i915/perf.c b/tests/i915/perf.c
>> index 5502a3fb..9ef52690 100644
>> --- a/tests/i915/perf.c
>> +++ b/tests/i915/perf.c
>> @@ -1586,7 +1586,7 @@ static void load_helper_init(void)
>> lh.context_id = gem_context_create(drm_fd);
>> igt_assert_neq(lh.context_id, 0xffffffff);
>>
>> - lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, BATCH_SZ);
>> + lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, NULL, BATCH_SZ);
>>
>> scratch_buf_init(lh.bops, &lh.dst, 1920, 1080, 0);
>> scratch_buf_init(lh.bops, &lh.src, 1920, 1080, 0);
>> @@ -3011,7 +3011,7 @@ gen12_test_mi_rpc(void)
>> igt_assert_neq(ctx_id, INVALID_CTX_ID);
>> properties[1] = ctx_id;
>>
>> - ibb = intel_bb_create_with_context(drm_fd, ctx_id, BATCH_SZ);
>> + ibb = intel_bb_create_with_context(drm_fd, ctx_id, NULL, BATCH_SZ);
>> buf = intel_buf_create(bops, 4096, 1, 8, 64,
>> I915_TILING_NONE, I915_COMPRESSION_NONE);
>>
>> @@ -3090,7 +3090,7 @@ test_mi_rpc(void)
>>
>> ctx_id = gem_context_create(drm_fd);
>>
>> - ibb = intel_bb_create_with_context(drm_fd, ctx_id, BATCH_SZ);
>> + ibb = intel_bb_create_with_context(drm_fd, ctx_id, NULL, BATCH_SZ);
>> buf = intel_buf_create(bops, 4096, 1, 8, 64,
>> I915_TILING_NONE, I915_COMPRESSION_NONE);
>>
>> @@ -3217,8 +3217,8 @@ hsw_test_single_ctx_counters(void)
>> */
>> context0_id = gem_context_create(drm_fd);
>> context1_id = gem_context_create(drm_fd);
>> - ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
>> - ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
>> + ibb0 = intel_bb_create_with_context(drm_fd, context0_id, NULL, BATCH_SZ);
>> + ibb1 = intel_bb_create_with_context(drm_fd, context1_id, NULL, BATCH_SZ);
>>
>> igt_debug("submitting warm up render_copy\n");
>>
>> @@ -3461,8 +3461,8 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>>
>> context0_id = gem_context_create(drm_fd);
>> context1_id = gem_context_create(drm_fd);
>> - ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
>> - ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
>> + ibb0 = intel_bb_create_with_context(drm_fd, context0_id, NULL, BATCH_SZ);
>> + ibb1 = intel_bb_create_with_context(drm_fd, context1_id, NULL, BATCH_SZ);
>>
>> igt_debug("submitting warm up render_copy\n");
>>
>> @@ -3866,8 +3866,8 @@ static void gen12_single_ctx_helper(void)
>>
>> context0_id = gem_context_create(drm_fd);
>> context1_id = gem_context_create(drm_fd);
>> - ibb0 = intel_bb_create_with_context(drm_fd, context0_id, BATCH_SZ);
>> - ibb1 = intel_bb_create_with_context(drm_fd, context1_id, BATCH_SZ);
>> + ibb0 = intel_bb_create_with_context(drm_fd, context0_id, NULL, BATCH_SZ);
>> + ibb1 = intel_bb_create_with_context(drm_fd, context1_id, NULL, BATCH_SZ);
>>
>> igt_debug("submitting warm up render_copy\n");
>>
>> --
>> 2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/3] lib/intel_batchbuffer: Add support for custom engine layouts
2022-10-24 6:40 ` Zbigniew Kempczyński
@ 2022-10-24 13:16 ` Karolina Drobnik
2022-10-24 19:26 ` Zbigniew Kempczyński
0 siblings, 1 reply; 14+ messages in thread
From: Karolina Drobnik @ 2022-10-24 13:16 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 24.10.2022 08:40, Zbigniew Kempczyński wrote:
> On Fri, Oct 21, 2022 at 10:54:42AM +0200, Karolina Drobnik wrote:
>> Don't assume fixed engine ids and use context configuration in
>> intel_bb to find the appropriate engine when executing the batchbuffer.
>>
>> Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
>> ---
>> lib/intel_batchbuffer.c | 45 +++++++++++++++++++++++++++++++++--------
>> 1 file changed, 37 insertions(+), 8 deletions(-)
>>
>> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
>> index 70d819aa..20b7e255 100644
>> --- a/lib/intel_batchbuffer.c
>> +++ b/lib/intel_batchbuffer.c
>> @@ -1490,6 +1490,31 @@ static bool aux_needs_softpin(int i915)
>> return intel_gen(intel_get_drm_devid(i915)) >= 12;
>> }
>>
>> +static bool has_ctx_cfg(struct intel_bb *ibb)
>> +{
>> + return ibb->cfg && (ibb->cfg->num_engines > 0);
>> +}
>> +
>> +static bool find_engine(struct intel_bb *ibb, unsigned int class, uint32_t *ring)
>
> Why not:
>
> static uint32_t find_engine(struct intel_bb *ibb, unsigned int class)
>
> then all logic with selecting legacy/user engine hide here in the
> implementation? Especially you're not using return value in any form.
I wanted to avoid checking for cfg in two functions, and return early if
there is no config. But there is another problem with my approach -- we
silently allow legacy engine id if no suitable engine was found in the
config. Should we return -1 is such case, and check for it in
intel_bb_flush_render() and intel_bb_flush_blit()?
All the best,
Karolina
>
> --
> Zbigniew
>
>> +{
>> + intel_ctx_cfg_t *cfg;
>> + int i;
>> +
>> + /* Use legacy engines when there is no context config */
>> + if (!has_ctx_cfg(ibb))
>> + return false;
>> +
>> + cfg = ibb->cfg;
>> + for (i = 0; i < cfg->num_engines; i++) {
>> + if (cfg->engines[i].engine_class == class) {
>> + *ring = i;
>> + return true;
>> + }
>> + }
>> +
>> + return false;
>> +}
>> +
>> /**
>> * intel_bb_create:
>> * @i915: drm fd
>> @@ -2790,34 +2815,38 @@ void intel_bb_flush(struct intel_bb *ibb, uint32_t ring)
>> * intel_bb_flush_render:
>> * @ibb: batchbuffer
>> *
>> - * If batch is not empty emit batch buffer end, execute on render ring
>> - * and reset the batch. Context used to execute is batch context.
>> + * If batch is not empty emit batch buffer end, find the render engine id,
>> + * execute on the ring and reset the batch. Context used to execute
>> + * is batch context.
>> */
>> void intel_bb_flush_render(struct intel_bb *ibb)
>> {
>> + uint32_t ring = I915_EXEC_RENDER;
>> +
>> if (intel_bb_emit_flush_common(ibb) == 0)
>> return;
>>
>> - intel_bb_exec_with_ring(ibb, I915_EXEC_RENDER);
>> + find_engine(ibb, I915_ENGINE_CLASS_RENDER, &ring);
>> + intel_bb_exec_with_ring(ibb, ring);
>> }
>>
>> /*
>> * intel_bb_flush_blit:
>> * @ibb: batchbuffer
>> *
>> - * If batch is not empty emit batch buffer end, execute on default/blit ring
>> - * (depends on gen) and reset the batch.
>> + * If batch is not empty emit batch buffer end, find a suitable ring
>> + * (depending on gen and context configuration) and reset the batch.
>> * Context used to execute is batch context.
>> */
>> void intel_bb_flush_blit(struct intel_bb *ibb)
>> {
>> - uint32_t ring = I915_EXEC_DEFAULT;
>> + uint32_t ring;
>>
>> if (intel_bb_emit_flush_common(ibb) == 0)
>> return;
>>
>> - if (HAS_BLT_RING(ibb->devid))
>> - ring = I915_EXEC_BLT;
>> + ring = HAS_BLT_RING(ibb->devid) ? I915_EXEC_BLT : I915_EXEC_DEFAULT;
>> + find_engine(ibb, I915_ENGINE_CLASS_COPY, &ring);
>>
>> intel_bb_exec_with_ring(ibb, ring);
>> }
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/3] tests/api_intel_bb: Add misplaced_blitter test
2022-10-24 6:46 ` Zbigniew Kempczyński
@ 2022-10-24 13:19 ` Karolina Drobnik
0 siblings, 0 replies; 14+ messages in thread
From: Karolina Drobnik @ 2022-10-24 13:19 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 24.10.2022 08:46, Zbigniew Kempczyński wrote:
> On Fri, Oct 21, 2022 at 10:54:43AM +0200, Karolina Drobnik wrote:
>> Exercise intel_bb with a custom context engines layout.
>>
>> Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
>> ---
>> tests/i915/api_intel_bb.c | 34 ++++++++++++++++++++++++++++++++++
>> 1 file changed, 34 insertions(+)
>>
>> diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
>> index 6ba1fd1b..42959880 100644
>> --- a/tests/i915/api_intel_bb.c
>> +++ b/tests/i915/api_intel_bb.c
>> @@ -1209,6 +1209,36 @@ static void full_batch(struct buf_ops *bops)
>> intel_bb_destroy(ibb);
>> }
>>
>> +static void misplaced_blitter(struct buf_ops *bops)
>> +{
>> + int i915 = buf_ops_get_fd(bops);
>> + struct intel_bb *ibb;
>> +
>> + gem_require_contexts(i915);
>> +
>> + /* Use custom configuration with blitter at index 0 */
>> + const intel_ctx_cfg_t cfg = (intel_ctx_cfg_t) {
>> + .num_engines = 2,
>> + .engines = {
>> + { .engine_class = I915_ENGINE_CLASS_COPY,
>> + .engine_instance = 0
>> + },
>> + { .engine_class = I915_ENGINE_CLASS_RENDER,
>> + .engine_instance = 0
>> + },
>> + },
>> + };
>> + const intel_ctx_t *ctx = intel_ctx_create(i915, &cfg);
>> +
>> + ibb = intel_bb_create_with_context(i915, ctx->id, &ctx->cfg, PAGE_SIZE);
>> +
>> + intel_bb_emit_bbe(ibb);
>> + intel_bb_flush_blit(ibb);
>
> BBE will work on each engine, can you prove it was executed on blitter?
Good point. We should add an additional instruction that would work only
on blitter. Will correct it, thanks.
All the best,
Karolina
> --
> Zbigniew
>
>> +
>> + intel_bb_destroy(ibb);
>> + intel_ctx_destroy(i915, ctx);
>> +}
>> +
>> static int render(struct buf_ops *bops, uint32_t tiling, bool do_reloc,
>> uint32_t width, uint32_t height)
>> {
>> @@ -1581,6 +1611,10 @@ igt_main_args("dpibc:", NULL, help_str, opt_handler, NULL)
>> igt_subtest("full-batch")
>> full_batch(bops);
>>
>> + igt_describe("Execute intel_bb with set of engines provided by userspace");
>> + igt_subtest("misplaced-blitter")
>> + misplaced_blitter(bops);
>> +
>> igt_subtest_with_dynamic("render") {
>> for (i = 0; i < ARRAY_SIZE(tests); i++) {
>> const struct test *t = &tests[i];
>> --
>> 2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/3] lib/intel_batchbuffer: Add support for custom engine layouts
2022-10-24 13:16 ` Karolina Drobnik
@ 2022-10-24 19:26 ` Zbigniew Kempczyński
2022-10-25 6:10 ` Karolina Drobnik
0 siblings, 1 reply; 14+ messages in thread
From: Zbigniew Kempczyński @ 2022-10-24 19:26 UTC (permalink / raw)
To: Karolina Drobnik; +Cc: igt-dev
On Mon, Oct 24, 2022 at 03:16:16PM +0200, Karolina Drobnik wrote:
> On 24.10.2022 08:40, Zbigniew Kempczyński wrote:
> > On Fri, Oct 21, 2022 at 10:54:42AM +0200, Karolina Drobnik wrote:
> > > Don't assume fixed engine ids and use context configuration in
> > > intel_bb to find the appropriate engine when executing the batchbuffer.
> > >
> > > Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
> > > ---
> > > lib/intel_batchbuffer.c | 45 +++++++++++++++++++++++++++++++++--------
> > > 1 file changed, 37 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> > > index 70d819aa..20b7e255 100644
> > > --- a/lib/intel_batchbuffer.c
> > > +++ b/lib/intel_batchbuffer.c
> > > @@ -1490,6 +1490,31 @@ static bool aux_needs_softpin(int i915)
> > > return intel_gen(intel_get_drm_devid(i915)) >= 12;
> > > }
> > > +static bool has_ctx_cfg(struct intel_bb *ibb)
> > > +{
> > > + return ibb->cfg && (ibb->cfg->num_engines > 0);
> > > +}
> > > +
> > > +static bool find_engine(struct intel_bb *ibb, unsigned int class, uint32_t *ring)
> >
> > Why not:
> >
> > static uint32_t find_engine(struct intel_bb *ibb, unsigned int class)
> >
> > then all logic with selecting legacy/user engine hide here in the
> > implementation? Especially you're not using return value in any form.
>
> I wanted to avoid checking for cfg in two functions, and return early if
> there is no config. But there is another problem with my approach -- we
> silently allow legacy engine id if no suitable engine was found in the
> config. Should we return -1 is such case, and check for it in
> intel_bb_flush_render() and intel_bb_flush_blit()?
If there's no cfg we have legacy context, and if user will call
ring = find_engine(ibb, I915_ENGINE_CLASS_RENDER);
find_engine() should simply return I915_EXEC_RENDER whereas for
I915_ENGINE_CLASS_COPY return I915_EXEC_BLT/DEFAULT according to
current conditional code (and so on for other engines).
When cfg doesn't contain dedicated class configured I think we
should assert because there's no option to satisfy the caller
according to requested engine.
--
Zbigniew
>
> All the best,
> Karolina
>
> >
> > --
> > Zbigniew
> >
> > > +{
> > > + intel_ctx_cfg_t *cfg;
> > > + int i;
> > > +
> > > + /* Use legacy engines when there is no context config */
> > > + if (!has_ctx_cfg(ibb))
> > > + return false;
> > > +
> > > + cfg = ibb->cfg;
> > > + for (i = 0; i < cfg->num_engines; i++) {
> > > + if (cfg->engines[i].engine_class == class) {
> > > + *ring = i;
> > > + return true;
> > > + }
> > > + }
> > > +
> > > + return false;
> > > +}
> > > +
> > > /**
> > > * intel_bb_create:
> > > * @i915: drm fd
> > > @@ -2790,34 +2815,38 @@ void intel_bb_flush(struct intel_bb *ibb, uint32_t ring)
> > > * intel_bb_flush_render:
> > > * @ibb: batchbuffer
> > > *
> > > - * If batch is not empty emit batch buffer end, execute on render ring
> > > - * and reset the batch. Context used to execute is batch context.
> > > + * If batch is not empty emit batch buffer end, find the render engine id,
> > > + * execute on the ring and reset the batch. Context used to execute
> > > + * is batch context.
> > > */
> > > void intel_bb_flush_render(struct intel_bb *ibb)
> > > {
> > > + uint32_t ring = I915_EXEC_RENDER;
> > > +
> > > if (intel_bb_emit_flush_common(ibb) == 0)
> > > return;
> > > - intel_bb_exec_with_ring(ibb, I915_EXEC_RENDER);
> > > + find_engine(ibb, I915_ENGINE_CLASS_RENDER, &ring);
> > > + intel_bb_exec_with_ring(ibb, ring);
> > > }
> > > /*
> > > * intel_bb_flush_blit:
> > > * @ibb: batchbuffer
> > > *
> > > - * If batch is not empty emit batch buffer end, execute on default/blit ring
> > > - * (depends on gen) and reset the batch.
> > > + * If batch is not empty emit batch buffer end, find a suitable ring
> > > + * (depending on gen and context configuration) and reset the batch.
> > > * Context used to execute is batch context.
> > > */
> > > void intel_bb_flush_blit(struct intel_bb *ibb)
> > > {
> > > - uint32_t ring = I915_EXEC_DEFAULT;
> > > + uint32_t ring;
> > > if (intel_bb_emit_flush_common(ibb) == 0)
> > > return;
> > > - if (HAS_BLT_RING(ibb->devid))
> > > - ring = I915_EXEC_BLT;
> > > + ring = HAS_BLT_RING(ibb->devid) ? I915_EXEC_BLT : I915_EXEC_DEFAULT;
> > > + find_engine(ibb, I915_ENGINE_CLASS_COPY, &ring);
> > > intel_bb_exec_with_ring(ibb, ring);
> > > }
> > > --
> > > 2.25.1
> > >
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/3] lib/intel_batchbuffer: Add support for custom engine layouts
2022-10-24 19:26 ` Zbigniew Kempczyński
@ 2022-10-25 6:10 ` Karolina Drobnik
0 siblings, 0 replies; 14+ messages in thread
From: Karolina Drobnik @ 2022-10-25 6:10 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 24.10.2022 21:26, Zbigniew Kempczyński wrote:
> On Mon, Oct 24, 2022 at 03:16:16PM +0200, Karolina Drobnik wrote:
>> On 24.10.2022 08:40, Zbigniew Kempczyński wrote:
>>> On Fri, Oct 21, 2022 at 10:54:42AM +0200, Karolina Drobnik wrote:
>>>> Don't assume fixed engine ids and use context configuration in
>>>> intel_bb to find the appropriate engine when executing the batchbuffer.
>>>>
>>>> Signed-off-by: Karolina Drobnik <karolina.drobnik@intel.com>
>>>> ---
>>>> lib/intel_batchbuffer.c | 45 +++++++++++++++++++++++++++++++++--------
>>>> 1 file changed, 37 insertions(+), 8 deletions(-)
>>>>
>>>> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
>>>> index 70d819aa..20b7e255 100644
>>>> --- a/lib/intel_batchbuffer.c
>>>> +++ b/lib/intel_batchbuffer.c
>>>> @@ -1490,6 +1490,31 @@ static bool aux_needs_softpin(int i915)
>>>> return intel_gen(intel_get_drm_devid(i915)) >= 12;
>>>> }
>>>> +static bool has_ctx_cfg(struct intel_bb *ibb)
>>>> +{
>>>> + return ibb->cfg && (ibb->cfg->num_engines > 0);
>>>> +}
>>>> +
>>>> +static bool find_engine(struct intel_bb *ibb, unsigned int class, uint32_t *ring)
>>>
>>> Why not:
>>>
>>> static uint32_t find_engine(struct intel_bb *ibb, unsigned int class)
>>>
>>> then all logic with selecting legacy/user engine hide here in the
>>> implementation? Especially you're not using return value in any form.
>>
>> I wanted to avoid checking for cfg in two functions, and return early if
>> there is no config. But there is another problem with my approach -- we
>> silently allow legacy engine id if no suitable engine was found in the
>> config. Should we return -1 is such case, and check for it in
>> intel_bb_flush_render() and intel_bb_flush_blit()?
>
> If there's no cfg we have legacy context, and if user will call
>
> ring = find_engine(ibb, I915_ENGINE_CLASS_RENDER);
>
> find_engine() should simply return I915_EXEC_RENDER whereas for
> I915_ENGINE_CLASS_COPY return I915_EXEC_BLT/DEFAULT according to
> current conditional code (and so on for other engines).
>
> When cfg doesn't contain dedicated class configured I think we
> should assert because there's no option to satisfy the caller
> according to requested engine.
Sounds like a plan, will incorporate it in v2.
All the best,
Karolina
> --
> Zbigniew
>
>>
>> All the best,
>> Karolina
>>
>>>
>>> --
>>> Zbigniew
>>>
>>>> +{
>>>> + intel_ctx_cfg_t *cfg;
>>>> + int i;
>>>> +
>>>> + /* Use legacy engines when there is no context config */
>>>> + if (!has_ctx_cfg(ibb))
>>>> + return false;
>>>> +
>>>> + cfg = ibb->cfg;
>>>> + for (i = 0; i < cfg->num_engines; i++) {
>>>> + if (cfg->engines[i].engine_class == class) {
>>>> + *ring = i;
>>>> + return true;
>>>> + }
>>>> + }
>>>> +
>>>> + return false;
>>>> +}
>>>> +
>>>> /**
>>>> * intel_bb_create:
>>>> * @i915: drm fd
>>>> @@ -2790,34 +2815,38 @@ void intel_bb_flush(struct intel_bb *ibb, uint32_t ring)
>>>> * intel_bb_flush_render:
>>>> * @ibb: batchbuffer
>>>> *
>>>> - * If batch is not empty emit batch buffer end, execute on render ring
>>>> - * and reset the batch. Context used to execute is batch context.
>>>> + * If batch is not empty emit batch buffer end, find the render engine id,
>>>> + * execute on the ring and reset the batch. Context used to execute
>>>> + * is batch context.
>>>> */
>>>> void intel_bb_flush_render(struct intel_bb *ibb)
>>>> {
>>>> + uint32_t ring = I915_EXEC_RENDER;
>>>> +
>>>> if (intel_bb_emit_flush_common(ibb) == 0)
>>>> return;
>>>> - intel_bb_exec_with_ring(ibb, I915_EXEC_RENDER);
>>>> + find_engine(ibb, I915_ENGINE_CLASS_RENDER, &ring);
>>>> + intel_bb_exec_with_ring(ibb, ring);
>>>> }
>>>> /*
>>>> * intel_bb_flush_blit:
>>>> * @ibb: batchbuffer
>>>> *
>>>> - * If batch is not empty emit batch buffer end, execute on default/blit ring
>>>> - * (depends on gen) and reset the batch.
>>>> + * If batch is not empty emit batch buffer end, find a suitable ring
>>>> + * (depending on gen and context configuration) and reset the batch.
>>>> * Context used to execute is batch context.
>>>> */
>>>> void intel_bb_flush_blit(struct intel_bb *ibb)
>>>> {
>>>> - uint32_t ring = I915_EXEC_DEFAULT;
>>>> + uint32_t ring;
>>>> if (intel_bb_emit_flush_common(ibb) == 0)
>>>> return;
>>>> - if (HAS_BLT_RING(ibb->devid))
>>>> - ring = I915_EXEC_BLT;
>>>> + ring = HAS_BLT_RING(ibb->devid) ? I915_EXEC_BLT : I915_EXEC_DEFAULT;
>>>> + find_engine(ibb, I915_ENGINE_CLASS_COPY, &ring);
>>>> intel_bb_exec_with_ring(ibb, ring);
>>>> }
>>>> --
>>>> 2.25.1
>>>>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-10-25 6:10 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-10-21 8:54 [igt-dev] [PATCH i-g-t 0/3] Add support for intel_ctx_t in intel_bb Karolina Drobnik
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_batchbuffer: Extend __intel_bb_create to handle context config Karolina Drobnik
2022-10-24 6:37 ` Zbigniew Kempczyński
2022-10-24 12:55 ` Karolina Drobnik
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_batchbuffer: Add support for custom engine layouts Karolina Drobnik
2022-10-24 6:40 ` Zbigniew Kempczyński
2022-10-24 13:16 ` Karolina Drobnik
2022-10-24 19:26 ` Zbigniew Kempczyński
2022-10-25 6:10 ` Karolina Drobnik
2022-10-21 8:54 ` [igt-dev] [PATCH i-g-t 3/3] tests/api_intel_bb: Add misplaced_blitter test Karolina Drobnik
2022-10-24 6:46 ` Zbigniew Kempczyński
2022-10-24 13:19 ` Karolina Drobnik
2022-10-21 10:42 ` [igt-dev] ✓ Fi.CI.BAT: success for Add support for intel_ctx_t in intel_bb Patchwork
2022-10-21 16:18 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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