[PATCH i-g-t v6 0/5] Compression support for Lunarlake

[PATCH i-g-t v6 0/5] Compression support for Lunarlake

[Akshata Jahagirdar]

Series enables the compression feature for Lunarlake and address various
changes of the feature from Gen12. The Main-to-CCS ratio has been
changed to 512:1. This changes the calculations and value for fields
such as CCS Copy size for blitter command APIs. 
This patch series updates tests xe_ccs and gem_ccs for XE2.
This series doesn't solve "in-place" and "suspend-resume" subtests.

These changes are based on top of the "vm_bind pat_index" patch here:
https://patchwork.freedesktop.org/series/124667/

v2: Lots of improvements/tweaks (Kamil)
    Addressed review comments (Matthew, Karolina)
v3: Reused dg2_xy_fast_copy definition for defing xe2_cmds_info struct(Karolina)
    Split the patch to address ccs_size calculation and updating
pat_index, updated the intel_get_pat_idx_uc_comp function as per review
comments (Kamil)
v4: Addressed review comments (Karolina)
    Rebase. Removed few unnecessary conditions, plus few fixes.
v5: Addressed Review comments (Matthew, Zbigniew)
    Rebase, Fixes for pre-merge IGT tests.
v6: Addressed Review comments (Matthew)

Akshata Jahagirdar (5):
  lib: Add blt command properties for lunarlake
  lib/intel_blt: Update calculation of ccs_size and size_of_ctrl_copy
  lib/intel_pat: Add uc_comp pat_index
  lib/intel_blt: Update caching mode and pat_index
  tests/intel/xe_ccs: Add compression support for Lunarlake

 lib/intel_blt.c         | 24 +++++++++++++++------
 lib/intel_blt.h         |  2 +-
 lib/intel_cmds_info.c   | 16 ++++++++++++++
 lib/intel_cmds_info.h   |  1 +
 lib/intel_device_info.c |  2 +-
 lib/intel_pat.c         | 14 +++++++++++-
 lib/intel_pat.h         |  2 ++
 tests/intel/gem_ccs.c   |  2 +-
 tests/intel/xe_ccs.c    | 47 ++++++++++++++++++++++++-----------------
 9 files changed, 80 insertions(+), 30 deletions(-)

-- 
2.34.1

✓ CI.xeBAT: success for Compression support for Lunarlake

[Patchwork]

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== Series Details ==

Series: Compression support for Lunarlake
URL   : https://patchwork.freedesktop.org/series/127739/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7638_BAT -> XEIGTPW_10410_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_10410_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
    - bat-adlp-7:         [PASS][1] -> [FAIL][2] ([Intel XE#480]) +2 other tests fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7638/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10410/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html

  * igt@xe_prime_self_import@basic-with_one_bo:
    - bat-pvc-2:          [PASS][3] -> [FAIL][4] ([Intel XE#999]) +1 other test fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7638/bat-pvc-2/igt@xe_prime_self_import@basic-with_one_bo.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10410/bat-pvc-2/igt@xe_prime_self_import@basic-with_one_bo.html

  
#### Possible fixes ####

  * igt@xe_prime_self_import@basic-with_fd_dup:
    - bat-atsm-2:         [FAIL][5] ([Intel XE#999]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7638/bat-atsm-2/igt@xe_prime_self_import@basic-with_fd_dup.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10410/bat-atsm-2/igt@xe_prime_self_import@basic-with_fd_dup.html

  
  [Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480
  [Intel XE#999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/999


Build changes
-------------

  * IGT: IGT_7638 -> IGTPW_10410

  IGTPW_10410: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/index.html
  IGT_7638: 52ca619dfeae57348b957778dcfdd8117d8ff9f0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-577-5cd1893366708380854f4694ae57417192458a6b: 5cd1893366708380854f4694ae57417192458a6b

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10410/index.html

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✗ Fi.CI.BAT: failure for Compression support for Lunarlake

[Patchwork]

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== Series Details ==

Series: Compression support for Lunarlake
URL   : https://patchwork.freedesktop.org/series/127739/
State : failure

== Summary ==

CI Bug Log - changes from IGT_7638 -> IGTPW_10410
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_10410 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_10410, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/index.html

Participating hosts (32 -> 30)
------------------------------

  Additional (1): bat-mtlp-8 
  Missing    (3): bat-kbl-2 bat-jsl-1 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_10410:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@gt_lrc:
    - fi-tgl-1115g4:      [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7638/fi-tgl-1115g4/igt@i915_selftest@live@gt_lrc.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/fi-tgl-1115g4/igt@i915_selftest@live@gt_lrc.html

  
Known issues
------------

  Here are the changes found in IGTPW_10410 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-mtlp-8:         NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-mtlp-8:         NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@gem_mmap_gtt@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-mtlp-8:         NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@i915_pm_rps@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-mtlp-8:         NOTRUN -> [SKIP][9] ([i915#6645])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][10] ([i915#5190])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][11] ([i915#4212]) +8 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][12] ([i915#4213]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][13] ([i915#3555] / [i915#3840] / [i915#9159])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-mtlp-8:         NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-mtlp-8:         NOTRUN -> [SKIP][15] ([i915#5274])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-mtlp-8:         NOTRUN -> [SKIP][16] ([i915#3555] / [i915#8809])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-mtlp-8:         NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - bat-mtlp-8:         NOTRUN -> [SKIP][18] ([i915#3708]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7638 -> IGTPW_10410

  CI-20190529: 20190529
  CI_DRM_14011: 8e97d53327d4a17de2f8ac6c307c8ddd980f6125 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_10410: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/index.html
  IGT_7638: 52ca619dfeae57348b957778dcfdd8117d8ff9f0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10410/index.html

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[PATCH i-g-t v6 1/5] lib: Add blt command properties for lunarlake

[Akshata Jahagirdar]

Add blt_cmd_info struct to describe properties of XY_BLOCK_COPY for XE2 platform.
Reuse XY_FAST_COPY struct from DG2 and Update the definitions for Lunarlake.

Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>

Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_cmds_info.c   | 16 ++++++++++++++++
 lib/intel_cmds_info.h   |  1 +
 lib/intel_device_info.c |  2 +-
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c
index 2e51ec081..56073bd6d 100644
--- a/lib/intel_cmds_info.c
+++ b/lib/intel_cmds_info.c
@@ -67,6 +67,15 @@ static const struct blt_cmd_info
 						 BLT_CMD_EXTENDED |
 						 BLT_CMD_SUPPORTS_COMPRESSION);
 
+static const struct blt_cmd_info
+		xe2_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY,
+						 BIT(T_LINEAR) |
+						 BIT(T_XMAJOR) |
+						 BIT(T_TILE4)  |
+						 BIT(T_TILE64),
+						 BLT_CMD_EXTENDED |
+						 BLT_CMD_SUPPORTS_COMPRESSION);
+
 static const struct blt_cmd_info
 		mtl_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY,
 						 BIT(T_LINEAR) |
@@ -169,6 +178,13 @@ const struct intel_cmds_info gen12_pvc_cmds_info = {
 	}
 };
 
+const struct intel_cmds_info xe2_cmds_info  = {
+	.blt_cmds = {
+		[XY_FAST_COPY] = &dg2_xy_fast_copy,
+		[XY_BLOCK_COPY] = &xe2_xy_block_copy,
+	}
+};
+
 const struct blt_cmd_info *blt_get_cmd_info(const struct intel_cmds_info *cmds_info,
 					    enum blt_cmd_type cmd)
 {
diff --git a/lib/intel_cmds_info.h b/lib/intel_cmds_info.h
index f9e3932d1..0a83b6a44 100644
--- a/lib/intel_cmds_info.h
+++ b/lib/intel_cmds_info.h
@@ -55,6 +55,7 @@ extern const struct intel_cmds_info gen12_cmds_info;
 extern const struct intel_cmds_info gen12_dg2_cmds_info;
 extern const struct intel_cmds_info gen12_mtl_cmds_info;
 extern const struct intel_cmds_info gen12_pvc_cmds_info;
+extern const struct intel_cmds_info xe2_cmds_info;
 
 #define for_each_tiling(__tiling) \
 	for (__tiling = T_LINEAR; __tiling < __BLT_MAX_TILING; __tiling++)
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 34817f7b6..a669797c3 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -511,7 +511,7 @@ static const struct intel_device_info intel_lunarlake_info = {
 	.has_4tile = true,
 	.is_lunarlake = true,
 	.codename = "lunarlake",
-	.cmds_info = &gen12_pvc_cmds_info,
+	.cmds_info = &xe2_cmds_info,
 };
 
 static const struct pci_id_match intel_device_match[] = {
-- 
2.34.1

[PATCH i-g-t v6 2/5] lib/intel_blt: Update calculation of ccs_size and size_of_ctrl_copy

[Akshata Jahagirdar]

The Main-to-CCS Ratio for XE2 has been changed to 512:1.
Update the CCS_RATIO macro to select relevant ratio based on platform.
Update the ccs_ratio call in gem_ccs and xe_ccs tests
based on previous change.

Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
---
 lib/intel_blt.c       | 13 ++++++++-----
 lib/intel_blt.h       |  2 +-
 tests/intel/gem_ccs.c |  2 +-
 tests/intel/xe_ccs.c  |  2 +-
 4 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 1116c978e..1be289ad6 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -948,15 +948,16 @@ int blt_block_copy(int fd,
 	return ret;
 }
 
-static uint16_t __ccs_size(const struct blt_ctrl_surf_copy_data *surf)
+static uint16_t __ccs_size(int fd, const struct blt_ctrl_surf_copy_data *surf)
 {
 	uint32_t src_size, dst_size;
+	uint16_t ccsratio = CCS_RATIO(fd);
 
 	src_size = surf->src.access_type == DIRECT_ACCESS ?
-				surf->src.size : surf->src.size / CCS_RATIO;
+				surf->src.size : surf->src.size / ccsratio;
 
 	dst_size = surf->dst.access_type == DIRECT_ACCESS ?
-				surf->dst.size : surf->dst.size / CCS_RATIO;
+				surf->dst.size : surf->dst.size / ccsratio;
 
 	igt_assert_f(src_size <= dst_size, "dst size must be >= src size for CCS copy\n");
 
@@ -1118,6 +1119,8 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
 	uint64_t dst_offset, src_offset, bb_offset, alignment;
 	uint32_t bbe = MI_BATCH_BUFFER_END;
 	uint32_t *bb;
+	uint16_t num_ccs_blocks = (ip_ver >= IP_VER(20, 0)) ?
+				(xe_get_default_alignment(fd) / CCS_RATIO(fd)) : CCS_RATIO(fd);
 
 	igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n");
 	igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n");
@@ -1136,7 +1139,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
 		data.xe2.dw00.dst_access_type = surf->dst.access_type;
 
 		/* Ensure dst has size capable to keep src ccs aux */
-		data.xe2.dw00.size_of_ctrl_copy = __ccs_size(surf) / CCS_RATIO - 1;
+		data.xe2.dw00.size_of_ctrl_copy = __ccs_size(fd, surf) / num_ccs_blocks - 1;
 		data.xe2.dw00.length = 0x3;
 
 		data.xe2.dw01.src_address_lo = src_offset;
@@ -1155,7 +1158,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
 		data.gen12.dw00.dst_access_type = surf->dst.access_type;
 
 		/* Ensure dst has size capable to keep src ccs aux */
-		data.gen12.dw00.size_of_ctrl_copy = __ccs_size(surf) / CCS_RATIO - 1;
+		data.gen12.dw00.size_of_ctrl_copy = __ccs_size(fd, surf) / num_ccs_blocks - 1;
 		data.gen12.dw00.length = 0x3;
 
 		data.gen12.dw01.src_address_lo = src_offset;
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index 5934ccd67..d9be22fdf 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -52,7 +52,7 @@
 #include "igt.h"
 #include "intel_cmds_info.h"
 
-#define CCS_RATIO 256
+#define CCS_RATIO(fd) (AT_LEAST_GEN(intel_get_drm_devid(fd), 20) ? 512 : 256)
 
 enum blt_color_depth {
 	CD_8bit,
diff --git a/tests/intel/gem_ccs.c b/tests/intel/gem_ccs.c
index 0a691778d..80a29ecab 100644
--- a/tests/intel/gem_ccs.c
+++ b/tests/intel/gem_ccs.c
@@ -99,7 +99,7 @@ static void surf_copy(int i915,
 	struct blt_block_copy_data_ext ext = {};
 	struct blt_ctrl_surf_copy_data surf = {};
 	uint32_t bb1, bb2, ccs, ccs2, *ccsmap, *ccsmap2;
-	uint64_t bb_size, ccssize = mid->size / CCS_RATIO;
+	uint64_t bb_size, ccssize = mid->size / CCS_RATIO(i915);
 	uint32_t *ccscopy;
 	uint8_t uc_mocs = intel_get_uc_mocs_index(i915);
 	int result;
diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
index 77d3020bc..ac0805017 100644
--- a/tests/intel/xe_ccs.c
+++ b/tests/intel/xe_ccs.c
@@ -95,7 +95,7 @@ static void surf_copy(int xe,
 	struct blt_block_copy_data_ext ext = {};
 	struct blt_ctrl_surf_copy_data surf = {};
 	uint32_t bb1, bb2, ccs, ccs2, *ccsmap, *ccsmap2;
-	uint64_t bb_size, ccssize = mid->size / CCS_RATIO;
+	uint64_t bb_size, ccssize = mid->size / CCS_RATIO(xe);
 	uint32_t *ccscopy;
 	uint8_t uc_mocs = intel_get_uc_mocs_index(xe);
 	uint32_t sysmem = system_memory(xe);
-- 
2.34.1

Re: [PATCH i-g-t v6 2/5] lib/intel_blt: Update calculation of ccs_size and size_of_ctrl_copy

[Zbigniew Kempczyński]

On Wed, Dec 13, 2023 at 11:55:06AM -0800, Akshata Jahagirdar wrote:
> The Main-to-CCS Ratio for XE2 has been changed to 512:1.
> Update the CCS_RATIO macro to select relevant ratio based on platform.
> Update the ccs_ratio call in gem_ccs and xe_ccs tests
> based on previous change.
> 
> Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>

LGTM now:

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

> ---
>  lib/intel_blt.c       | 13 ++++++++-----
>  lib/intel_blt.h       |  2 +-
>  tests/intel/gem_ccs.c |  2 +-
>  tests/intel/xe_ccs.c  |  2 +-
>  4 files changed, 11 insertions(+), 8 deletions(-)
> 
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index 1116c978e..1be289ad6 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -948,15 +948,16 @@ int blt_block_copy(int fd,
>  	return ret;
>  }
>  
> -static uint16_t __ccs_size(const struct blt_ctrl_surf_copy_data *surf)
> +static uint16_t __ccs_size(int fd, const struct blt_ctrl_surf_copy_data *surf)
>  {
>  	uint32_t src_size, dst_size;
> +	uint16_t ccsratio = CCS_RATIO(fd);
>  
>  	src_size = surf->src.access_type == DIRECT_ACCESS ?
> -				surf->src.size : surf->src.size / CCS_RATIO;
> +				surf->src.size : surf->src.size / ccsratio;
>  
>  	dst_size = surf->dst.access_type == DIRECT_ACCESS ?
> -				surf->dst.size : surf->dst.size / CCS_RATIO;
> +				surf->dst.size : surf->dst.size / ccsratio;
>  
>  	igt_assert_f(src_size <= dst_size, "dst size must be >= src size for CCS copy\n");
>  
> @@ -1118,6 +1119,8 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
>  	uint64_t dst_offset, src_offset, bb_offset, alignment;
>  	uint32_t bbe = MI_BATCH_BUFFER_END;
>  	uint32_t *bb;
> +	uint16_t num_ccs_blocks = (ip_ver >= IP_VER(20, 0)) ?
> +				(xe_get_default_alignment(fd) / CCS_RATIO(fd)) : CCS_RATIO(fd);
>  
>  	igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n");
>  	igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n");
> @@ -1136,7 +1139,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
>  		data.xe2.dw00.dst_access_type = surf->dst.access_type;
>  
>  		/* Ensure dst has size capable to keep src ccs aux */
> -		data.xe2.dw00.size_of_ctrl_copy = __ccs_size(surf) / CCS_RATIO - 1;
> +		data.xe2.dw00.size_of_ctrl_copy = __ccs_size(fd, surf) / num_ccs_blocks - 1;
>  		data.xe2.dw00.length = 0x3;
>  
>  		data.xe2.dw01.src_address_lo = src_offset;
> @@ -1155,7 +1158,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
>  		data.gen12.dw00.dst_access_type = surf->dst.access_type;
>  
>  		/* Ensure dst has size capable to keep src ccs aux */
> -		data.gen12.dw00.size_of_ctrl_copy = __ccs_size(surf) / CCS_RATIO - 1;
> +		data.gen12.dw00.size_of_ctrl_copy = __ccs_size(fd, surf) / num_ccs_blocks - 1;
>  		data.gen12.dw00.length = 0x3;
>  
>  		data.gen12.dw01.src_address_lo = src_offset;
> diff --git a/lib/intel_blt.h b/lib/intel_blt.h
> index 5934ccd67..d9be22fdf 100644
> --- a/lib/intel_blt.h
> +++ b/lib/intel_blt.h
> @@ -52,7 +52,7 @@
>  #include "igt.h"
>  #include "intel_cmds_info.h"
>  
> -#define CCS_RATIO 256
> +#define CCS_RATIO(fd) (AT_LEAST_GEN(intel_get_drm_devid(fd), 20) ? 512 : 256)
>  
>  enum blt_color_depth {
>  	CD_8bit,
> diff --git a/tests/intel/gem_ccs.c b/tests/intel/gem_ccs.c
> index 0a691778d..80a29ecab 100644
> --- a/tests/intel/gem_ccs.c
> +++ b/tests/intel/gem_ccs.c
> @@ -99,7 +99,7 @@ static void surf_copy(int i915,
>  	struct blt_block_copy_data_ext ext = {};
>  	struct blt_ctrl_surf_copy_data surf = {};
>  	uint32_t bb1, bb2, ccs, ccs2, *ccsmap, *ccsmap2;
> -	uint64_t bb_size, ccssize = mid->size / CCS_RATIO;
> +	uint64_t bb_size, ccssize = mid->size / CCS_RATIO(i915);
>  	uint32_t *ccscopy;
>  	uint8_t uc_mocs = intel_get_uc_mocs_index(i915);
>  	int result;
> diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
> index 77d3020bc..ac0805017 100644
> --- a/tests/intel/xe_ccs.c
> +++ b/tests/intel/xe_ccs.c
> @@ -95,7 +95,7 @@ static void surf_copy(int xe,
>  	struct blt_block_copy_data_ext ext = {};
>  	struct blt_ctrl_surf_copy_data surf = {};
>  	uint32_t bb1, bb2, ccs, ccs2, *ccsmap, *ccsmap2;
> -	uint64_t bb_size, ccssize = mid->size / CCS_RATIO;
> +	uint64_t bb_size, ccssize = mid->size / CCS_RATIO(xe);
>  	uint32_t *ccscopy;
>  	uint8_t uc_mocs = intel_get_uc_mocs_index(xe);
>  	uint32_t sysmem = system_memory(xe);
> -- 
> 2.34.1
> 

[PATCH i-g-t v6 3/5] lib/intel_pat: Add uc_comp pat_index

[Akshata Jahagirdar]

Compression in XE2 is programmed through pat-index attribute.
Add a dedicated pat-index for compression for XE2 and later platforms.
The caller to this helper function ensures GFX version is correct.

Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
 lib/intel_pat.c | 14 +++++++++++++-
 lib/intel_pat.h |  2 ++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/lib/intel_pat.c b/lib/intel_pat.c
index 2b892ee52..041952bd8 100644
--- a/lib/intel_pat.c
+++ b/lib/intel_pat.c
@@ -11,7 +11,7 @@ struct intel_pat_cache {
 	uint8_t uc; /* UC + COH_NONE */
 	uint8_t wt; /* WT + COH_NONE */
 	uint8_t wb; /* WB + COH_AT_LEAST_1WAY */
-
+	uint8_t uc_comp; /* UC + COH_NONE + COMPRESSION, XE2 and later*/
 	uint8_t max_index;
 };
 
@@ -23,6 +23,7 @@ static void intel_get_pat_idx(int fd, struct intel_pat_cache *pat)
 		pat->uc = 3;
 		pat->wt = 15; /* Compressed + WB-transient */
 		pat->wb = 2;
+		pat->uc_comp = 12; /* Compressed + UC, XE2 and later */
 		pat->max_index = 31;
 	} else if (IS_METEORLAKE(dev_id)) {
 		pat->uc = 2;
@@ -60,6 +61,17 @@ uint8_t intel_get_pat_idx_uc(int fd)
 	return pat.uc;
 }
 
+uint8_t intel_get_pat_idx_uc_comp(int fd)
+{
+	struct intel_pat_cache pat = {};
+	uint16_t dev_id = intel_get_drm_devid(fd);
+
+	igt_assert(AT_LEAST_GEN(dev_id, 20));
+
+	intel_get_pat_idx(fd, &pat);
+	return pat.uc_comp;
+}
+
 uint8_t intel_get_pat_idx_wt(int fd)
 {
 	struct intel_pat_cache pat = {};
diff --git a/lib/intel_pat.h b/lib/intel_pat.h
index c24dbc275..eb48cbc65 100644
--- a/lib/intel_pat.h
+++ b/lib/intel_pat.h
@@ -16,4 +16,6 @@ uint8_t intel_get_pat_idx_uc(int fd);
 uint8_t intel_get_pat_idx_wt(int fd);
 uint8_t intel_get_pat_idx_wb(int fd);
 
+uint8_t intel_get_pat_idx_uc_comp(int fd);
+
 #endif /* INTEL_PAT_H */
-- 
2.34.1

[PATCH i-g-t v6 4/5] lib/intel_blt: Update caching mode and pat_index

[Akshata Jahagirdar]

The pat-index and caching mode for compression need to change to uc_comp in case
of compression, else they just take the default value of pat_index and caching.

Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
Acked-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
 lib/intel_blt.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 1be289ad6..e41e261ea 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1797,6 +1797,7 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region,
 	uint64_t size = width * height * bpp / 8;
 	uint32_t stride = tiling == T_LINEAR ? width * 4 : width;
 	uint32_t handle;
+	uint8_t pat_index = DEFAULT_PAT_INDEX;
 
 	igt_assert_f(blt->driver, "Driver isn't set, have you called blt_copy_init()?\n");
 
@@ -1806,18 +1807,24 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region,
 
 	if (blt->driver == INTEL_DRIVER_XE) {
 		uint64_t flags = 0;
+		uint16_t cpu_caching = __xe_default_cpu_caching(blt->fd, region, flags);
 
 		if (create_mapping && region != system_memory(blt->fd))
 			flags |= DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
 
+		if (AT_LEAST_GEN(intel_get_drm_devid(blt->fd), 20) && compression) {
+			pat_index = intel_get_pat_idx_uc_comp(blt->fd);
+			cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
+		}
+
 		size = ALIGN(size, xe_get_default_alignment(blt->fd));
-		handle = xe_bo_create(blt->fd, 0, size, region, flags);
+		handle = xe_bo_create_caching(blt->fd, 0, size, region, flags, cpu_caching);
 	} else {
 		igt_assert(__gem_create_in_memory_regions(blt->fd, &handle,
 							  &size, region) == 0);
 	}
 
-	blt_set_object(obj, handle, size, region, mocs_index, DEFAULT_PAT_INDEX, tiling,
+	blt_set_object(obj, handle, size, region, mocs_index, pat_index, tiling,
 		       compression, compression_type);
 	blt_set_geom(obj, stride, 0, 0, width, height, 0, 0);
 
-- 
2.34.1

[PATCH i-g-t v6 5/5] tests/intel/xe_ccs: Add compression support for Lunarlake

[Akshata Jahagirdar]

In XE2 IGFX platform, sysmem also participates in compression.
So create all blt objects in sysmem itself, and update the pat-index to reflect
the compression status. Since we need to align the buffer object size with page
size and also have the src size and dst size of CCS copy to be equal,
change the default width and height to 1024.

Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
---
 tests/intel/xe_ccs.c | 45 ++++++++++++++++++++++++++------------------
 1 file changed, 27 insertions(+), 18 deletions(-)

diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
index ac0805017..a780140fd 100644
--- a/tests/intel/xe_ccs.c
+++ b/tests/intel/xe_ccs.c
@@ -63,8 +63,8 @@ static struct param {
 	.write_png = false,
 	.print_bb = false,
 	.print_surface_info = false,
-	.width = 512,
-	.height = 512,
+	.width = 1024,
+	.height = 1024,
 };
 
 struct test_config {
@@ -99,17 +99,23 @@ static void surf_copy(int xe,
 	uint32_t *ccscopy;
 	uint8_t uc_mocs = intel_get_uc_mocs_index(xe);
 	uint32_t sysmem = system_memory(xe);
+	uint8_t comp_pat_index = DEFAULT_PAT_INDEX;
+	uint16_t cpu_caching = __xe_default_cpu_caching(xe, sysmem, 0);
 	int result;
 
 	igt_assert(mid->compression);
+	if (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) && mid->compression) {
+		comp_pat_index  = intel_get_pat_idx_uc_comp(xe);
+		cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
+	}
 	ccscopy = (uint32_t *) malloc(ccssize);
-	ccs = xe_bo_create(xe, 0, ccssize, sysmem, 0);
-	ccs2 = xe_bo_create(xe, 0, ccssize, sysmem, 0);
+	ccs = xe_bo_create_caching(xe, 0, ccssize, sysmem, 0, cpu_caching);
+	ccs2 = xe_bo_create_caching(xe, 0, ccssize, sysmem, 0, cpu_caching);
 
 	blt_ctrl_surf_copy_init(xe, &surf);
 	surf.print_bb = param.print_bb;
 	blt_set_ctrl_surf_object(&surf.src, mid->handle, mid->region, mid->size,
-				 uc_mocs, DEFAULT_PAT_INDEX, BLT_INDIRECT_ACCESS);
+				 uc_mocs, comp_pat_index, BLT_INDIRECT_ACCESS);
 	blt_set_ctrl_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs,
 				 DEFAULT_PAT_INDEX, DIRECT_ACCESS);
 	bb_size = xe_get_default_alignment(xe);
@@ -157,7 +163,7 @@ static void surf_copy(int xe,
 	blt_set_ctrl_surf_object(&surf.src, ccs, sysmem, ccssize,
 				 uc_mocs, DEFAULT_PAT_INDEX, DIRECT_ACCESS);
 	blt_set_ctrl_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
-				 uc_mocs, DEFAULT_PAT_INDEX, INDIRECT_ACCESS);
+				 uc_mocs, comp_pat_index, INDIRECT_ACCESS);
 	blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
 	intel_ctx_xe_sync(ctx, true);
 
@@ -234,10 +240,10 @@ static int blt_block_copy3(int xe,
 	igt_assert_f(blt3, "block-copy3 requires data to do blit\n");
 
 	alignment = xe_get_default_alignment(xe);
-	get_offset(ahnd, blt3->src.handle, blt3->src.size, alignment);
-	get_offset(ahnd, blt3->mid.handle, blt3->mid.size, alignment);
-	get_offset(ahnd, blt3->dst.handle, blt3->dst.size, alignment);
-	get_offset(ahnd, blt3->final.handle, blt3->final.size, alignment);
+	get_offset_pat_index(ahnd, blt3->src.handle, blt3->src.size, alignment, blt3->src.pat_index);
+	get_offset_pat_index(ahnd, blt3->mid.handle, blt3->mid.size, alignment, blt3->mid.pat_index);
+	get_offset_pat_index(ahnd, blt3->dst.handle, blt3->dst.size, alignment, blt3->dst.pat_index);
+	get_offset_pat_index(ahnd, blt3->final.handle, blt3->final.size, alignment, blt3->final.pat_index);
 	bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment);
 
 	/* First blit src -> mid */
@@ -291,8 +297,9 @@ static void block_copy(int xe,
 	uint64_t bb_size = xe_get_default_alignment(xe);
 	uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
 	uint32_t run_id = mid_tiling;
-	uint32_t mid_region = region2, bb;
-	uint32_t width = param.width, height = param.height;
+	uint32_t mid_region = (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) &
+							!xe_has_vram(xe)) ? region1 : region2;
+	uint32_t width = param.width, height = param.height, bb;
 	enum blt_compression mid_compression = config->compression;
 	int mid_compression_format = param.compression_format;
 	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
@@ -413,8 +420,9 @@ static void block_multicopy(int xe,
 	uint64_t bb_size = xe_get_default_alignment(xe);
 	uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
 	uint32_t run_id = mid_tiling;
-	uint32_t mid_region = region2, bb;
-	uint32_t width = param.width, height = param.height;
+	uint32_t mid_region = (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) &
+							!xe_has_vram(xe)) ? region1 : region2;
+	uint32_t width = param.width, height = param.height, bb;
 	enum blt_compression mid_compression = config->compression;
 	int mid_compression_format = param.compression_format;
 	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
@@ -539,8 +547,9 @@ static void block_copy_test(int xe,
 			region1 = igt_collection_get_value(regions, 0);
 			region2 = igt_collection_get_value(regions, 1);
 
-			/* Compressed surface must be in device memory */
-			if (config->compression && !XE_IS_VRAM_MEMORY_REGION(xe, region2))
+			/* if not XE2, then Compressed surface must be in device memory */
+			if (config->compression && !(AT_LEAST_GEN((intel_get_drm_devid(xe)), 20)) &&
+									!XE_IS_VRAM_MEMORY_REGION(xe, region2))
 				continue;
 
 			regtxt = xe_memregion_dynamic_subtest_name(xe, regions);
@@ -621,8 +630,8 @@ const char *help_str =
 	"  -p\tWrite PNG\n"
 	"  -s\tPrint surface info\n"
 	"  -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n"
-	"  -W\tWidth (default 512)\n"
-	"  -H\tHeight (default 512)"
+	"  -W\tWidth (default 1024)\n"
+	"  -H\tHeight (default 1024)"
 	;
 
 igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
-- 
2.34.1

Re: [PATCH i-g-t v6 5/5] tests/intel/xe_ccs: Add compression support for Lunarlake

[Zbigniew Kempczyński]

On Wed, Dec 13, 2023 at 11:55:09AM -0800, Akshata Jahagirdar wrote:
> In XE2 IGFX platform, sysmem also participates in compression.
> So create all blt objects in sysmem itself, and update the pat-index to reflect
> the compression status. Since we need to align the buffer object size with page
> size and also have the src size and dst size of CCS copy to be equal,
> change the default width and height to 1024.

To be honest 512 x 512 x 32bpp looks much more interesting. From my
calculations:

num_pages = 512 * 512 * 4 / 4096 -> 256

256 pages, 8B compression each gives 2048B so regardless page
granularity this also should work. If not we need to fix the blt
library.

--
Zbigniew

> 
> Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
> ---
>  tests/intel/xe_ccs.c | 45 ++++++++++++++++++++++++++------------------
>  1 file changed, 27 insertions(+), 18 deletions(-)
> 
> diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
> index ac0805017..a780140fd 100644
> --- a/tests/intel/xe_ccs.c
> +++ b/tests/intel/xe_ccs.c
> @@ -63,8 +63,8 @@ static struct param {
>  	.write_png = false,
>  	.print_bb = false,
>  	.print_surface_info = false,
> -	.width = 512,
> -	.height = 512,
> +	.width = 1024,
> +	.height = 1024,
>  };
>  
>  struct test_config {
> @@ -99,17 +99,23 @@ static void surf_copy(int xe,
>  	uint32_t *ccscopy;
>  	uint8_t uc_mocs = intel_get_uc_mocs_index(xe);
>  	uint32_t sysmem = system_memory(xe);
> +	uint8_t comp_pat_index = DEFAULT_PAT_INDEX;
> +	uint16_t cpu_caching = __xe_default_cpu_caching(xe, sysmem, 0);
>  	int result;
>  
>  	igt_assert(mid->compression);
> +	if (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) && mid->compression) {
> +		comp_pat_index  = intel_get_pat_idx_uc_comp(xe);
> +		cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
> +	}
>  	ccscopy = (uint32_t *) malloc(ccssize);
> -	ccs = xe_bo_create(xe, 0, ccssize, sysmem, 0);
> -	ccs2 = xe_bo_create(xe, 0, ccssize, sysmem, 0);
> +	ccs = xe_bo_create_caching(xe, 0, ccssize, sysmem, 0, cpu_caching);
> +	ccs2 = xe_bo_create_caching(xe, 0, ccssize, sysmem, 0, cpu_caching);
>  
>  	blt_ctrl_surf_copy_init(xe, &surf);
>  	surf.print_bb = param.print_bb;
>  	blt_set_ctrl_surf_object(&surf.src, mid->handle, mid->region, mid->size,
> -				 uc_mocs, DEFAULT_PAT_INDEX, BLT_INDIRECT_ACCESS);
> +				 uc_mocs, comp_pat_index, BLT_INDIRECT_ACCESS);
>  	blt_set_ctrl_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs,
>  				 DEFAULT_PAT_INDEX, DIRECT_ACCESS);
>  	bb_size = xe_get_default_alignment(xe);
> @@ -157,7 +163,7 @@ static void surf_copy(int xe,
>  	blt_set_ctrl_surf_object(&surf.src, ccs, sysmem, ccssize,
>  				 uc_mocs, DEFAULT_PAT_INDEX, DIRECT_ACCESS);
>  	blt_set_ctrl_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
> -				 uc_mocs, DEFAULT_PAT_INDEX, INDIRECT_ACCESS);
> +				 uc_mocs, comp_pat_index, INDIRECT_ACCESS);
>  	blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
>  	intel_ctx_xe_sync(ctx, true);
>  
> @@ -234,10 +240,10 @@ static int blt_block_copy3(int xe,
>  	igt_assert_f(blt3, "block-copy3 requires data to do blit\n");
>  
>  	alignment = xe_get_default_alignment(xe);
> -	get_offset(ahnd, blt3->src.handle, blt3->src.size, alignment);
> -	get_offset(ahnd, blt3->mid.handle, blt3->mid.size, alignment);
> -	get_offset(ahnd, blt3->dst.handle, blt3->dst.size, alignment);
> -	get_offset(ahnd, blt3->final.handle, blt3->final.size, alignment);
> +	get_offset_pat_index(ahnd, blt3->src.handle, blt3->src.size, alignment, blt3->src.pat_index);
> +	get_offset_pat_index(ahnd, blt3->mid.handle, blt3->mid.size, alignment, blt3->mid.pat_index);
> +	get_offset_pat_index(ahnd, blt3->dst.handle, blt3->dst.size, alignment, blt3->dst.pat_index);
> +	get_offset_pat_index(ahnd, blt3->final.handle, blt3->final.size, alignment, blt3->final.pat_index);
>  	bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment);
>  
>  	/* First blit src -> mid */
> @@ -291,8 +297,9 @@ static void block_copy(int xe,
>  	uint64_t bb_size = xe_get_default_alignment(xe);
>  	uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
>  	uint32_t run_id = mid_tiling;
> -	uint32_t mid_region = region2, bb;
> -	uint32_t width = param.width, height = param.height;
> +	uint32_t mid_region = (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) &
> +							!xe_has_vram(xe)) ? region1 : region2;
> +	uint32_t width = param.width, height = param.height, bb;
>  	enum blt_compression mid_compression = config->compression;
>  	int mid_compression_format = param.compression_format;
>  	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
> @@ -413,8 +420,9 @@ static void block_multicopy(int xe,
>  	uint64_t bb_size = xe_get_default_alignment(xe);
>  	uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
>  	uint32_t run_id = mid_tiling;
> -	uint32_t mid_region = region2, bb;
> -	uint32_t width = param.width, height = param.height;
> +	uint32_t mid_region = (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) &
> +							!xe_has_vram(xe)) ? region1 : region2;
> +	uint32_t width = param.width, height = param.height, bb;
>  	enum blt_compression mid_compression = config->compression;
>  	int mid_compression_format = param.compression_format;
>  	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
> @@ -539,8 +547,9 @@ static void block_copy_test(int xe,
>  			region1 = igt_collection_get_value(regions, 0);
>  			region2 = igt_collection_get_value(regions, 1);
>  
> -			/* Compressed surface must be in device memory */
> -			if (config->compression && !XE_IS_VRAM_MEMORY_REGION(xe, region2))
> +			/* if not XE2, then Compressed surface must be in device memory */
> +			if (config->compression && !(AT_LEAST_GEN((intel_get_drm_devid(xe)), 20)) &&
> +									!XE_IS_VRAM_MEMORY_REGION(xe, region2))
>  				continue;
>  
>  			regtxt = xe_memregion_dynamic_subtest_name(xe, regions);
> @@ -621,8 +630,8 @@ const char *help_str =
>  	"  -p\tWrite PNG\n"
>  	"  -s\tPrint surface info\n"
>  	"  -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n"
> -	"  -W\tWidth (default 512)\n"
> -	"  -H\tHeight (default 512)"
> +	"  -W\tWidth (default 1024)\n"
> +	"  -H\tHeight (default 1024)"
>  	;
>  
>  igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
> -- 
> 2.34.1
> 

Re: [PATCH i-g-t v6 5/5] tests/intel/xe_ccs: Add compression support for Lunarlake

[Jahagirdar, Akshata]

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On 12/13/2023 1:02 AM, Zbigniew Kempczyński wrote:
> On Wed, Dec 13, 2023 at 11:55:09AM -0800, Akshata Jahagirdar wrote:
>> In XE2 IGFX platform, sysmem also participates in compression.
>> So create all blt objects in sysmem itself, and update the pat-index to reflect
>> the compression status. Since we need to align the buffer object size with page
>> size and also have the src size and dst size of CCS copy to be equal,
>> change the default width and height to 1024.
> To be honest 512 x 512 x 32bpp looks much more interesting. From my
> calculations:
>
> num_pages = 512 * 512 * 4 / 4096 -> 256
>
> 256 pages, 8B compression each gives 2048B so regardless page
> granularity this also should work. If not we need to fix the blt
> library.
>
> --
> Zbigniew

Hi, thank you for your comment.

In case of 512 x 512 x 32bpp that is the compressed blt object size.

the ccs size for this blt object = 512 * 512 * 4 / 512 = 2048

While creating the ccs bo of size 2048, it doesn't align properly with 
our page size, thats where the test fails.

Best,

Akshata

>> Signed-off-by: Akshata Jahagirdar<akshata.jahagirdar@intel.com>
>> ---
>>   tests/intel/xe_ccs.c | 45 ++++++++++++++++++++++++++------------------
>>   1 file changed, 27 insertions(+), 18 deletions(-)
>>
>> diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
>> index ac0805017..a780140fd 100644
>> --- a/tests/intel/xe_ccs.c
>> +++ b/tests/intel/xe_ccs.c
>> @@ -63,8 +63,8 @@ static struct param {
>>   	.write_png = false,
>>   	.print_bb = false,
>>   	.print_surface_info = false,
>> -	.width = 512,
>> -	.height = 512,
>> +	.width = 1024,
>> +	.height = 1024,
>>   };
>>   
>>   struct test_config {
>> @@ -99,17 +99,23 @@ static void surf_copy(int xe,
>>   	uint32_t *ccscopy;
>>   	uint8_t uc_mocs = intel_get_uc_mocs_index(xe);
>>   	uint32_t sysmem = system_memory(xe);
>> +	uint8_t comp_pat_index = DEFAULT_PAT_INDEX;
>> +	uint16_t cpu_caching = __xe_default_cpu_caching(xe, sysmem, 0);
>>   	int result;
>>   
>>   	igt_assert(mid->compression);
>> +	if (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) && mid->compression) {
>> +		comp_pat_index  = intel_get_pat_idx_uc_comp(xe);
>> +		cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
>> +	}
>>   	ccscopy = (uint32_t *) malloc(ccssize);
>> -	ccs = xe_bo_create(xe, 0, ccssize, sysmem, 0);
>> -	ccs2 = xe_bo_create(xe, 0, ccssize, sysmem, 0);
>> +	ccs = xe_bo_create_caching(xe, 0, ccssize, sysmem, 0, cpu_caching);
>> +	ccs2 = xe_bo_create_caching(xe, 0, ccssize, sysmem, 0, cpu_caching);
>>   
>>   	blt_ctrl_surf_copy_init(xe, &surf);
>>   	surf.print_bb = param.print_bb;
>>   	blt_set_ctrl_surf_object(&surf.src, mid->handle, mid->region, mid->size,
>> -				 uc_mocs, DEFAULT_PAT_INDEX, BLT_INDIRECT_ACCESS);
>> +				 uc_mocs, comp_pat_index, BLT_INDIRECT_ACCESS);
>>   	blt_set_ctrl_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs,
>>   				 DEFAULT_PAT_INDEX, DIRECT_ACCESS);
>>   	bb_size = xe_get_default_alignment(xe);
>> @@ -157,7 +163,7 @@ static void surf_copy(int xe,
>>   	blt_set_ctrl_surf_object(&surf.src, ccs, sysmem, ccssize,
>>   				 uc_mocs, DEFAULT_PAT_INDEX, DIRECT_ACCESS);
>>   	blt_set_ctrl_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
>> -				 uc_mocs, DEFAULT_PAT_INDEX, INDIRECT_ACCESS);
>> +				 uc_mocs, comp_pat_index, INDIRECT_ACCESS);
>>   	blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
>>   	intel_ctx_xe_sync(ctx, true);
>>   
>> @@ -234,10 +240,10 @@ static int blt_block_copy3(int xe,
>>   	igt_assert_f(blt3, "block-copy3 requires data to do blit\n");
>>   
>>   	alignment = xe_get_default_alignment(xe);
>> -	get_offset(ahnd, blt3->src.handle, blt3->src.size, alignment);
>> -	get_offset(ahnd, blt3->mid.handle, blt3->mid.size, alignment);
>> -	get_offset(ahnd, blt3->dst.handle, blt3->dst.size, alignment);
>> -	get_offset(ahnd, blt3->final.handle, blt3->final.size, alignment);
>> +	get_offset_pat_index(ahnd, blt3->src.handle, blt3->src.size, alignment, blt3->src.pat_index);
>> +	get_offset_pat_index(ahnd, blt3->mid.handle, blt3->mid.size, alignment, blt3->mid.pat_index);
>> +	get_offset_pat_index(ahnd, blt3->dst.handle, blt3->dst.size, alignment, blt3->dst.pat_index);
>> +	get_offset_pat_index(ahnd, blt3->final.handle, blt3->final.size, alignment, blt3->final.pat_index);
>>   	bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment);
>>   
>>   	/* First blit src -> mid */
>> @@ -291,8 +297,9 @@ static void block_copy(int xe,
>>   	uint64_t bb_size = xe_get_default_alignment(xe);
>>   	uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
>>   	uint32_t run_id = mid_tiling;
>> -	uint32_t mid_region = region2, bb;
>> -	uint32_t width = param.width, height = param.height;
>> +	uint32_t mid_region = (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) &
>> +							!xe_has_vram(xe)) ? region1 : region2;
>> +	uint32_t width = param.width, height = param.height, bb;
>>   	enum blt_compression mid_compression = config->compression;
>>   	int mid_compression_format = param.compression_format;
>>   	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
>> @@ -413,8 +420,9 @@ static void block_multicopy(int xe,
>>   	uint64_t bb_size = xe_get_default_alignment(xe);
>>   	uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
>>   	uint32_t run_id = mid_tiling;
>> -	uint32_t mid_region = region2, bb;
>> -	uint32_t width = param.width, height = param.height;
>> +	uint32_t mid_region = (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) &
>> +							!xe_has_vram(xe)) ? region1 : region2;
>> +	uint32_t width = param.width, height = param.height, bb;
>>   	enum blt_compression mid_compression = config->compression;
>>   	int mid_compression_format = param.compression_format;
>>   	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
>> @@ -539,8 +547,9 @@ static void block_copy_test(int xe,
>>   			region1 = igt_collection_get_value(regions, 0);
>>   			region2 = igt_collection_get_value(regions, 1);
>>   
>> -			/* Compressed surface must be in device memory */
>> -			if (config->compression && !XE_IS_VRAM_MEMORY_REGION(xe, region2))
>> +			/* if not XE2, then Compressed surface must be in device memory */
>> +			if (config->compression && !(AT_LEAST_GEN((intel_get_drm_devid(xe)), 20)) &&
>> +									!XE_IS_VRAM_MEMORY_REGION(xe, region2))
>>   				continue;
>>   
>>   			regtxt = xe_memregion_dynamic_subtest_name(xe, regions);
>> @@ -621,8 +630,8 @@ const char *help_str =
>>   	"  -p\tWrite PNG\n"
>>   	"  -s\tPrint surface info\n"
>>   	"  -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n"
>> -	"  -W\tWidth (default 512)\n"
>> -	"  -H\tHeight (default 512)"
>> +	"  -W\tWidth (default 1024)\n"
>> +	"  -H\tHeight (default 1024)"
>>   	;
>>   
>>   igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
>> -- 
>> 2.34.1
>>

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Re: [PATCH i-g-t v6 5/5] tests/intel/xe_ccs: Add compression support for Lunarlake

[Kamil Konieczny]

Hi Akshata,
On 2023-12-13 at 11:55:09 -0800, Akshata Jahagirdar wrote:
> In XE2 IGFX platform, sysmem also participates in compression.
-------- ^^^^ ---------------- ^^^^
On iGPGX you have only sysmem, or am I missing something? So this should be:

In XE2 iGFX platform only sysmem participates in compression.

Second concern is why do impose only sysmen for all platforms,
including dGPU?

Regards,
Kamil

> So create all blt objects in sysmem itself, and update the pat-index to reflect
> the compression status. Since we need to align the buffer object size with page
> size and also have the src size and dst size of CCS copy to be equal,
> change the default width and height to 1024.
> 
> Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
> ---
>  tests/intel/xe_ccs.c | 45 ++++++++++++++++++++++++++------------------
>  1 file changed, 27 insertions(+), 18 deletions(-)
> 
> diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
> index ac0805017..a780140fd 100644
> --- a/tests/intel/xe_ccs.c
> +++ b/tests/intel/xe_ccs.c
> @@ -63,8 +63,8 @@ static struct param {
>  	.write_png = false,
>  	.print_bb = false,
>  	.print_surface_info = false,
> -	.width = 512,
> -	.height = 512,
> +	.width = 1024,
> +	.height = 1024,
>  };
>  
>  struct test_config {
> @@ -99,17 +99,23 @@ static void surf_copy(int xe,
>  	uint32_t *ccscopy;
>  	uint8_t uc_mocs = intel_get_uc_mocs_index(xe);
>  	uint32_t sysmem = system_memory(xe);
> +	uint8_t comp_pat_index = DEFAULT_PAT_INDEX;
> +	uint16_t cpu_caching = __xe_default_cpu_caching(xe, sysmem, 0);
>  	int result;
>  
>  	igt_assert(mid->compression);
> +	if (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) && mid->compression) {
> +		comp_pat_index  = intel_get_pat_idx_uc_comp(xe);
> +		cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
> +	}
>  	ccscopy = (uint32_t *) malloc(ccssize);
> -	ccs = xe_bo_create(xe, 0, ccssize, sysmem, 0);
> -	ccs2 = xe_bo_create(xe, 0, ccssize, sysmem, 0);
> +	ccs = xe_bo_create_caching(xe, 0, ccssize, sysmem, 0, cpu_caching);
> +	ccs2 = xe_bo_create_caching(xe, 0, ccssize, sysmem, 0, cpu_caching);
>  
>  	blt_ctrl_surf_copy_init(xe, &surf);
>  	surf.print_bb = param.print_bb;
>  	blt_set_ctrl_surf_object(&surf.src, mid->handle, mid->region, mid->size,
> -				 uc_mocs, DEFAULT_PAT_INDEX, BLT_INDIRECT_ACCESS);
> +				 uc_mocs, comp_pat_index, BLT_INDIRECT_ACCESS);
>  	blt_set_ctrl_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs,
>  				 DEFAULT_PAT_INDEX, DIRECT_ACCESS);
>  	bb_size = xe_get_default_alignment(xe);
> @@ -157,7 +163,7 @@ static void surf_copy(int xe,
>  	blt_set_ctrl_surf_object(&surf.src, ccs, sysmem, ccssize,
>  				 uc_mocs, DEFAULT_PAT_INDEX, DIRECT_ACCESS);
>  	blt_set_ctrl_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
> -				 uc_mocs, DEFAULT_PAT_INDEX, INDIRECT_ACCESS);
> +				 uc_mocs, comp_pat_index, INDIRECT_ACCESS);
>  	blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
>  	intel_ctx_xe_sync(ctx, true);
>  
> @@ -234,10 +240,10 @@ static int blt_block_copy3(int xe,
>  	igt_assert_f(blt3, "block-copy3 requires data to do blit\n");
>  
>  	alignment = xe_get_default_alignment(xe);
> -	get_offset(ahnd, blt3->src.handle, blt3->src.size, alignment);
> -	get_offset(ahnd, blt3->mid.handle, blt3->mid.size, alignment);
> -	get_offset(ahnd, blt3->dst.handle, blt3->dst.size, alignment);
> -	get_offset(ahnd, blt3->final.handle, blt3->final.size, alignment);
> +	get_offset_pat_index(ahnd, blt3->src.handle, blt3->src.size, alignment, blt3->src.pat_index);
> +	get_offset_pat_index(ahnd, blt3->mid.handle, blt3->mid.size, alignment, blt3->mid.pat_index);
> +	get_offset_pat_index(ahnd, blt3->dst.handle, blt3->dst.size, alignment, blt3->dst.pat_index);
> +	get_offset_pat_index(ahnd, blt3->final.handle, blt3->final.size, alignment, blt3->final.pat_index);
>  	bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment);
>  
>  	/* First blit src -> mid */
> @@ -291,8 +297,9 @@ static void block_copy(int xe,
>  	uint64_t bb_size = xe_get_default_alignment(xe);
>  	uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
>  	uint32_t run_id = mid_tiling;
> -	uint32_t mid_region = region2, bb;
> -	uint32_t width = param.width, height = param.height;
> +	uint32_t mid_region = (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) &
> +							!xe_has_vram(xe)) ? region1 : region2;
> +	uint32_t width = param.width, height = param.height, bb;
>  	enum blt_compression mid_compression = config->compression;
>  	int mid_compression_format = param.compression_format;
>  	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
> @@ -413,8 +420,9 @@ static void block_multicopy(int xe,
>  	uint64_t bb_size = xe_get_default_alignment(xe);
>  	uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
>  	uint32_t run_id = mid_tiling;
> -	uint32_t mid_region = region2, bb;
> -	uint32_t width = param.width, height = param.height;
> +	uint32_t mid_region = (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) &
> +							!xe_has_vram(xe)) ? region1 : region2;
> +	uint32_t width = param.width, height = param.height, bb;
>  	enum blt_compression mid_compression = config->compression;
>  	int mid_compression_format = param.compression_format;
>  	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
> @@ -539,8 +547,9 @@ static void block_copy_test(int xe,
>  			region1 = igt_collection_get_value(regions, 0);
>  			region2 = igt_collection_get_value(regions, 1);
>  
> -			/* Compressed surface must be in device memory */
> -			if (config->compression && !XE_IS_VRAM_MEMORY_REGION(xe, region2))
> +			/* if not XE2, then Compressed surface must be in device memory */
> +			if (config->compression && !(AT_LEAST_GEN((intel_get_drm_devid(xe)), 20)) &&
> +									!XE_IS_VRAM_MEMORY_REGION(xe, region2))
>  				continue;
>  
>  			regtxt = xe_memregion_dynamic_subtest_name(xe, regions);
> @@ -621,8 +630,8 @@ const char *help_str =
>  	"  -p\tWrite PNG\n"
>  	"  -s\tPrint surface info\n"
>  	"  -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n"
> -	"  -W\tWidth (default 512)\n"
> -	"  -H\tHeight (default 512)"
> +	"  -W\tWidth (default 1024)\n"
> +	"  -H\tHeight (default 1024)"
>  	;
>  
>  igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
> -- 
> 2.34.1
> 

Re: [PATCH i-g-t v6 5/5] tests/intel/xe_ccs: Add compression support for Lunarlake

[Jahagirdar, Akshata]

On 12/13/2023 6:15 AM, Kamil Konieczny wrote:
> Hi Akshata,
> On 2023-12-13 at 11:55:09 -0800, Akshata Jahagirdar wrote:
>> In XE2 IGFX platform, sysmem also participates in compression.
> -------- ^^^^ ---------------- ^^^^
> On iGPGX you have only sysmem, or am I missing something? So this should be:
>
> In XE2 iGFX platform only sysmem participates in compression.
Yep, this is correct. Will change it.
> Second concern is why do impose only sysmen for all platforms,
> including dGPU?
>
> Regards,
> Kamil

In case of XE2 iGFX, we are creating the blt objects in sysmem. For all 
other platforms, we will be creating in vram itself (as per previous 
implementation)

>> So create all blt objects in sysmem itself, and update the pat-index to reflect
>> the compression status. Since we need to align the buffer object size with page
>> size and also have the src size and dst size of CCS copy to be equal,
>> change the default width and height to 1024.
>>
>> Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
>> ---
>>   tests/intel/xe_ccs.c | 45 ++++++++++++++++++++++++++------------------
>>   1 file changed, 27 insertions(+), 18 deletions(-)
>>
>> diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
>> index ac0805017..a780140fd 100644
>> --- a/tests/intel/xe_ccs.c
>> +++ b/tests/intel/xe_ccs.c
>> @@ -63,8 +63,8 @@ static struct param {
>>   	.write_png = false,
>>   	.print_bb = false,
>>   	.print_surface_info = false,
>> -	.width = 512,
>> -	.height = 512,
>> +	.width = 1024,
>> +	.height = 1024,
>>   };
>>   
>>   struct test_config {
>> @@ -99,17 +99,23 @@ static void surf_copy(int xe,
>>   	uint32_t *ccscopy;
>>   	uint8_t uc_mocs = intel_get_uc_mocs_index(xe);
>>   	uint32_t sysmem = system_memory(xe);
>> +	uint8_t comp_pat_index = DEFAULT_PAT_INDEX;
>> +	uint16_t cpu_caching = __xe_default_cpu_caching(xe, sysmem, 0);
>>   	int result;
>>   
>>   	igt_assert(mid->compression);
>> +	if (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) && mid->compression) {
>> +		comp_pat_index  = intel_get_pat_idx_uc_comp(xe);
>> +		cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
>> +	}
>>   	ccscopy = (uint32_t *) malloc(ccssize);
>> -	ccs = xe_bo_create(xe, 0, ccssize, sysmem, 0);
>> -	ccs2 = xe_bo_create(xe, 0, ccssize, sysmem, 0);
>> +	ccs = xe_bo_create_caching(xe, 0, ccssize, sysmem, 0, cpu_caching);
>> +	ccs2 = xe_bo_create_caching(xe, 0, ccssize, sysmem, 0, cpu_caching);
>>   
>>   	blt_ctrl_surf_copy_init(xe, &surf);
>>   	surf.print_bb = param.print_bb;
>>   	blt_set_ctrl_surf_object(&surf.src, mid->handle, mid->region, mid->size,
>> -				 uc_mocs, DEFAULT_PAT_INDEX, BLT_INDIRECT_ACCESS);
>> +				 uc_mocs, comp_pat_index, BLT_INDIRECT_ACCESS);
>>   	blt_set_ctrl_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs,
>>   				 DEFAULT_PAT_INDEX, DIRECT_ACCESS);
>>   	bb_size = xe_get_default_alignment(xe);
>> @@ -157,7 +163,7 @@ static void surf_copy(int xe,
>>   	blt_set_ctrl_surf_object(&surf.src, ccs, sysmem, ccssize,
>>   				 uc_mocs, DEFAULT_PAT_INDEX, DIRECT_ACCESS);
>>   	blt_set_ctrl_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
>> -				 uc_mocs, DEFAULT_PAT_INDEX, INDIRECT_ACCESS);
>> +				 uc_mocs, comp_pat_index, INDIRECT_ACCESS);
>>   	blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
>>   	intel_ctx_xe_sync(ctx, true);
>>   
>> @@ -234,10 +240,10 @@ static int blt_block_copy3(int xe,
>>   	igt_assert_f(blt3, "block-copy3 requires data to do blit\n");
>>   
>>   	alignment = xe_get_default_alignment(xe);
>> -	get_offset(ahnd, blt3->src.handle, blt3->src.size, alignment);
>> -	get_offset(ahnd, blt3->mid.handle, blt3->mid.size, alignment);
>> -	get_offset(ahnd, blt3->dst.handle, blt3->dst.size, alignment);
>> -	get_offset(ahnd, blt3->final.handle, blt3->final.size, alignment);
>> +	get_offset_pat_index(ahnd, blt3->src.handle, blt3->src.size, alignment, blt3->src.pat_index);
>> +	get_offset_pat_index(ahnd, blt3->mid.handle, blt3->mid.size, alignment, blt3->mid.pat_index);
>> +	get_offset_pat_index(ahnd, blt3->dst.handle, blt3->dst.size, alignment, blt3->dst.pat_index);
>> +	get_offset_pat_index(ahnd, blt3->final.handle, blt3->final.size, alignment, blt3->final.pat_index);
>>   	bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment);
>>   
>>   	/* First blit src -> mid */
>> @@ -291,8 +297,9 @@ static void block_copy(int xe,
>>   	uint64_t bb_size = xe_get_default_alignment(xe);
>>   	uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
>>   	uint32_t run_id = mid_tiling;
>> -	uint32_t mid_region = region2, bb;
>> -	uint32_t width = param.width, height = param.height;
>> +	uint32_t mid_region = (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) &
>> +							!xe_has_vram(xe)) ? region1 : region2;
>> +	uint32_t width = param.width, height = param.height, bb;
>>   	enum blt_compression mid_compression = config->compression;
>>   	int mid_compression_format = param.compression_format;
>>   	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
>> @@ -413,8 +420,9 @@ static void block_multicopy(int xe,
>>   	uint64_t bb_size = xe_get_default_alignment(xe);
>>   	uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
>>   	uint32_t run_id = mid_tiling;
>> -	uint32_t mid_region = region2, bb;
>> -	uint32_t width = param.width, height = param.height;
>> +	uint32_t mid_region = (AT_LEAST_GEN(intel_get_drm_devid(xe), 20) &
>> +							!xe_has_vram(xe)) ? region1 : region2;
>> +	uint32_t width = param.width, height = param.height, bb;
>>   	enum blt_compression mid_compression = config->compression;
>>   	int mid_compression_format = param.compression_format;
>>   	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
>> @@ -539,8 +547,9 @@ static void block_copy_test(int xe,
>>   			region1 = igt_collection_get_value(regions, 0);
>>   			region2 = igt_collection_get_value(regions, 1);
>>   
>> -			/* Compressed surface must be in device memory */
>> -			if (config->compression && !XE_IS_VRAM_MEMORY_REGION(xe, region2))
>> +			/* if not XE2, then Compressed surface must be in device memory */
>> +			if (config->compression && !(AT_LEAST_GEN((intel_get_drm_devid(xe)), 20)) &&
>> +									!XE_IS_VRAM_MEMORY_REGION(xe, region2))
>>   				continue;
>>   
>>   			regtxt = xe_memregion_dynamic_subtest_name(xe, regions);
>> @@ -621,8 +630,8 @@ const char *help_str =
>>   	"  -p\tWrite PNG\n"
>>   	"  -s\tPrint surface info\n"
>>   	"  -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n"
>> -	"  -W\tWidth (default 512)\n"
>> -	"  -H\tHeight (default 512)"
>> +	"  -W\tWidth (default 1024)\n"
>> +	"  -H\tHeight (default 1024)"
>>   	;
>>   
>>   igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
>> -- 
>> 2.34.1
>>