[PATCH v2 i-g-t] lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe

[PATCH v2 i-g-t] lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe

[himanshu.girotra]

From: Himanshu Girotra <himanshu.girotra@intel.com>

IGT should treat the kernel as authoritative for PAT configuration
rather than replicating platform-specific logic and workaround
adjustments in hardcoded tables, which is error-prone as PAT layouts
vary across platforms.

For Xe devices, query pat_sw_config from debugfs instead of using
hardcoded PAT indices. Remove the Xe-only hardcoded entries and
retain the i915 fallback for older platforms.

Drop the now-redundant max_index assert in pat_sanity().

v2: Drop redundant index asserts; instead validate actual PAT register contents for correct cache types (Matt Roper)

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Xin Wang <x.wang@intel.com>
Signed-off-by: Himanshu Girotra <himanshu.girotra@intel.com>
---
 lib/intel_pat.c      | 37 ++++++++++----------
 tests/intel/xe_pat.c | 81 ++++++++++++++++++++++++++++++++++++++++----
 2 files changed, 94 insertions(+), 24 deletions(-)

diff --git a/lib/intel_pat.c b/lib/intel_pat.c
index 9815efc18..8660a2515 100644
--- a/lib/intel_pat.c
+++ b/lib/intel_pat.c
@@ -96,24 +96,27 @@ int32_t xe_get_pat_sw_config(int drm_fd, struct intel_pat_cache *xe_pat_cache)
 
 static void intel_get_pat_idx(int fd, struct intel_pat_cache *pat)
 {
-	uint16_t dev_id = intel_get_drm_devid(fd);
+	uint16_t dev_id;
+
+	/*
+	 * For Xe driver, query the kernel's PAT software configuration
+	 * via debugfs. The kernel is the authoritative source for PAT
+	 * indices, accounting for platform-specific workarounds
+	 * (e.g. Wa_16023588340) at runtime.
+	 */
+	if (is_xe_device(fd)) {
+		int32_t parsed = xe_get_pat_sw_config(fd, pat);
+
+		igt_assert_f(parsed > 0,
+			     "Failed to get PAT sw_config from debugfs (parsed=%d)\n",
+			     parsed);
+		return;
+	}
 
-	if (intel_graphics_ver(dev_id) == IP_VER(35, 11)) {
-		pat->uc = 3;
-		pat->wb = 2;
-		pat->max_index = 31;
-	} else if (intel_get_device_info(dev_id)->graphics_ver == 30 ||
-		   intel_get_device_info(dev_id)->graphics_ver == 20) {
-		pat->uc = 3;
-		pat->wt = 15; /* Compressed + WB-transient */
-		pat->wb = 2;
-		pat->uc_comp = 12; /* Compressed + UC, XE2 and later */
-		pat->max_index = 31;
-
-		/* Wa_16023588340: CLOS3 entries at end of table are unusable */
-		if (intel_graphics_ver(dev_id) == IP_VER(20, 1))
-			pat->max_index -= 4;
-	} else if (IS_METEORLAKE(dev_id)) {
+	/* i915 fallback: hardcoded PAT indices */
+	dev_id = intel_get_drm_devid(fd);
+
+	if (IS_METEORLAKE(dev_id)) {
 		pat->uc = 2;
 		pat->wt = 1;
 		pat->wb = 3;
diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
index 21547c84e..6ad6adab7 100644
--- a/tests/intel/xe_pat.c
+++ b/tests/intel/xe_pat.c
@@ -103,6 +103,57 @@ static void userptr_coh_none(int fd)
 #define COH_MODE_1WAY		2
 #define COH_MODE_2WAY		3
 
+/* Pre-Xe2 PAT bit fields (from kernel xe_pat.c) */
+#define XELP_MEM_TYPE_MASK	GENMASK(1, 0)
+
+static bool pat_entry_is_uc(unsigned int gfx_ver, uint32_t pat)
+{
+	if (gfx_ver >= IP_VER(20, 0))
+		return REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_UC &&
+		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
+
+	if (gfx_ver >= IP_VER(12, 70))
+		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
+
+	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 0;
+}
+
+static bool pat_entry_is_wb(unsigned int gfx_ver, uint32_t pat)
+{
+	if (gfx_ver >= IP_VER(20, 0)) {
+		uint32_t l3 = REG_FIELD_GET(XE2_L3_POLICY, pat);
+
+		return l3 == L3_CACHE_POLICY_WB || l3 == L3_CACHE_POLICY_XD;
+	}
+
+	if (gfx_ver >= IP_VER(12, 70))
+		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WB;
+
+	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 3;
+}
+
+static bool pat_entry_is_wt(unsigned int gfx_ver, uint32_t pat)
+{
+	if (gfx_ver >= IP_VER(20, 0))
+		return REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_XD &&
+		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WT;
+
+	if (gfx_ver >= IP_VER(12, 70))
+		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WT;
+
+	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 2;
+}
+
+static bool pat_entry_is_uc_comp(unsigned int gfx_ver, uint32_t pat)
+{
+	if (gfx_ver >= IP_VER(20, 0))
+		return !!(pat & XE2_COMP_EN) &&
+		       REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_UC &&
+		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
+
+	return false;
+}
+
 static int xe_fetch_pat_sw_config(int fd, struct intel_pat_cache *pat_sw_config)
 {
 	int32_t parsed = xe_get_pat_sw_config(fd, pat_sw_config);
@@ -120,13 +171,14 @@ static int xe_fetch_pat_sw_config(int fd, struct intel_pat_cache *pat_sw_config)
 static void pat_sanity(int fd)
 {
 	uint16_t dev_id = intel_get_drm_devid(fd);
+	unsigned int gfx_ver = intel_graphics_ver(dev_id);
 	struct intel_pat_cache pat_sw_config = {};
 	int32_t parsed;
 	bool has_uc_comp = false, has_wt = false;
 
 	parsed = xe_fetch_pat_sw_config(fd, &pat_sw_config);
 
-	if (intel_graphics_ver(dev_id) >= IP_VER(20, 0)) {
+	if (gfx_ver >= IP_VER(20, 0)) {
 		for (int i = 0; i < parsed; i++) {
 			uint32_t pat = pat_sw_config.entries[i].pat;
 			if (pat_sw_config.entries[i].rsvd)
@@ -144,13 +196,28 @@ static void pat_sanity(int fd)
 	} else {
 		has_wt = true;
 	}
-	igt_assert_eq(pat_sw_config.max_index, intel_get_max_pat_index(fd));
-	igt_assert_eq(pat_sw_config.uc, intel_get_pat_idx_uc(fd));
-	igt_assert_eq(pat_sw_config.wb, intel_get_pat_idx_wb(fd));
+
+	/*
+	 * Validate that the selected PAT indices actually have the expected
+	 * cache types rather than comparing against hardcoded values.
+	 */
+	igt_assert_f(pat_entry_is_uc(gfx_ver, pat_sw_config.entries[pat_sw_config.uc].pat),
+		     "UC index %d does not point to an uncached entry (pat=0x%x)\n",
+		     pat_sw_config.uc, pat_sw_config.entries[pat_sw_config.uc].pat);
+	igt_assert_f(pat_entry_is_wb(gfx_ver, pat_sw_config.entries[pat_sw_config.wb].pat),
+		     "WB index %d does not point to a WB/XA/XD entry (pat=0x%x)\n",
+		     pat_sw_config.wb, pat_sw_config.entries[pat_sw_config.wb].pat);
 	if (has_wt)
-		igt_assert_eq(pat_sw_config.wt, intel_get_pat_idx_wt(fd));
-	if (has_uc_comp)
-		igt_assert_eq(pat_sw_config.uc_comp, intel_get_pat_idx_uc_comp(fd));
+		igt_assert_f(pat_entry_is_wt(gfx_ver, pat_sw_config.entries[pat_sw_config.wt].pat),
+			     "WT index %d does not point to a WT entry (pat=0x%x)\n",
+			     pat_sw_config.wt, pat_sw_config.entries[pat_sw_config.wt].pat);
+	if (has_uc_comp) {
+		uint32_t uc_comp_pat = pat_sw_config.entries[pat_sw_config.uc_comp].pat;
+
+		igt_assert_f(pat_entry_is_uc_comp(gfx_ver, uc_comp_pat),
+			     "UC_COMP index %d does not point to a compressed UC entry (pat=0x%x)\n",
+			     pat_sw_config.uc_comp, uc_comp_pat);
+	}
 }
 
 /**
-- 
2.50.1

Re: [PATCH v2 i-g-t] lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe

[Wang, X]

On 2/24/2026 09:07, himanshu.girotra@intel.com wrote:
> From: Himanshu Girotra <himanshu.girotra@intel.com>
>
> IGT should treat the kernel as authoritative for PAT configuration
> rather than replicating platform-specific logic and workaround
> adjustments in hardcoded tables, which is error-prone as PAT layouts
> vary across platforms.
>
> For Xe devices, query pat_sw_config from debugfs instead of using
> hardcoded PAT indices. Remove the Xe-only hardcoded entries and
> retain the i915 fallback for older platforms.
>
> Drop the now-redundant max_index assert in pat_sanity().
>
> v2: Drop redundant index asserts; instead validate actual PAT register contents for correct cache types (Matt Roper)
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Xin Wang <x.wang@intel.com>
> Signed-off-by: Himanshu Girotra <himanshu.girotra@intel.com>
> ---
>   lib/intel_pat.c      | 37 ++++++++++----------
>   tests/intel/xe_pat.c | 81 ++++++++++++++++++++++++++++++++++++++++----
>   2 files changed, 94 insertions(+), 24 deletions(-)
>
> diff --git a/lib/intel_pat.c b/lib/intel_pat.c
> index 9815efc18..8660a2515 100644
> --- a/lib/intel_pat.c
> +++ b/lib/intel_pat.c
> @@ -96,24 +96,27 @@ int32_t xe_get_pat_sw_config(int drm_fd, struct intel_pat_cache *xe_pat_cache)
>   
>   static void intel_get_pat_idx(int fd, struct intel_pat_cache *pat)
>   {
> -	uint16_t dev_id = intel_get_drm_devid(fd);
> +	uint16_t dev_id;
> +
> +	/*
> +	 * For Xe driver, query the kernel's PAT software configuration
> +	 * via debugfs. The kernel is the authoritative source for PAT
> +	 * indices, accounting for platform-specific workarounds
> +	 * (e.g. Wa_16023588340) at runtime.
> +	 */
> +	if (is_xe_device(fd)) {
> +		int32_t parsed = xe_get_pat_sw_config(fd, pat);
> +
> +		igt_assert_f(parsed > 0,
> +			     "Failed to get PAT sw_config from debugfs (parsed=%d)\n",
> +			     parsed);
> +		return;
> +	}
>   
> -	if (intel_graphics_ver(dev_id) == IP_VER(35, 11)) {
> -		pat->uc = 3;
> -		pat->wb = 2;
> -		pat->max_index = 31;
> -	} else if (intel_get_device_info(dev_id)->graphics_ver == 30 ||
> -		   intel_get_device_info(dev_id)->graphics_ver == 20) {
> -		pat->uc = 3;
> -		pat->wt = 15; /* Compressed + WB-transient */
> -		pat->wb = 2;
> -		pat->uc_comp = 12; /* Compressed + UC, XE2 and later */
> -		pat->max_index = 31;
> -
> -		/* Wa_16023588340: CLOS3 entries at end of table are unusable */
> -		if (intel_graphics_ver(dev_id) == IP_VER(20, 1))
> -			pat->max_index -= 4;
> -	} else if (IS_METEORLAKE(dev_id)) {
> +	/* i915 fallback: hardcoded PAT indices */
Actually, from the very beginning when I modified the intel_pat library,
I wanted to remove this IGT code
(https://patchwork.freedesktop.org/series/157481/#rev2).
However, there was a problem: in the IGT test, the xe_oa test would drop
root privileges before starting the test. You can see the specific issue
in the CI.FULL fail case of your first version
(https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14590/shard-bmg-2/igt@xe_oa@mmio-triggered-reports@oag-0.html).
I previously tried caching the read pat table to prevent it from being 
read again after
dropping the root. However, while caching at the library level is 
advisable, cached
data can become problematic, especially when running on different GPUs. 
Therefore,
I didn't modify this part. Instead, I validated this data in pat_santiy 
to prevent errors
caused by not updating it in the IGT in a timely manner.

Xin


> +	dev_id = intel_get_drm_devid(fd);
> +
> +	if (IS_METEORLAKE(dev_id)) {
>   		pat->uc = 2;
>   		pat->wt = 1;
>   		pat->wb = 3;
> diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
> index 21547c84e..6ad6adab7 100644
> --- a/tests/intel/xe_pat.c
> +++ b/tests/intel/xe_pat.c
> @@ -103,6 +103,57 @@ static void userptr_coh_none(int fd)
>   #define COH_MODE_1WAY		2
>   #define COH_MODE_2WAY		3
>   
> +/* Pre-Xe2 PAT bit fields (from kernel xe_pat.c) */
> +#define XELP_MEM_TYPE_MASK	GENMASK(1, 0)
> +
> +static bool pat_entry_is_uc(unsigned int gfx_ver, uint32_t pat)
> +{
> +	if (gfx_ver >= IP_VER(20, 0))
> +		return REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_UC &&
> +		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
> +
> +	if (gfx_ver >= IP_VER(12, 70))
> +		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
> +
> +	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 0;
> +}
> +
> +static bool pat_entry_is_wb(unsigned int gfx_ver, uint32_t pat)
> +{
> +	if (gfx_ver >= IP_VER(20, 0)) {
> +		uint32_t l3 = REG_FIELD_GET(XE2_L3_POLICY, pat);
> +
> +		return l3 == L3_CACHE_POLICY_WB || l3 == L3_CACHE_POLICY_XD;
> +	}
> +
> +	if (gfx_ver >= IP_VER(12, 70))
> +		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WB;
> +
> +	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 3;
> +}
> +
> +static bool pat_entry_is_wt(unsigned int gfx_ver, uint32_t pat)
> +{
> +	if (gfx_ver >= IP_VER(20, 0))
> +		return REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_XD &&
> +		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WT;
> +
> +	if (gfx_ver >= IP_VER(12, 70))
> +		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WT;
> +
> +	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 2;
> +}
> +
> +static bool pat_entry_is_uc_comp(unsigned int gfx_ver, uint32_t pat)
> +{
> +	if (gfx_ver >= IP_VER(20, 0))
> +		return !!(pat & XE2_COMP_EN) &&
> +		       REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_UC &&
> +		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
> +
> +	return false;
> +}
> +
>   static int xe_fetch_pat_sw_config(int fd, struct intel_pat_cache *pat_sw_config)
>   {
>   	int32_t parsed = xe_get_pat_sw_config(fd, pat_sw_config);
> @@ -120,13 +171,14 @@ static int xe_fetch_pat_sw_config(int fd, struct intel_pat_cache *pat_sw_config)
>   static void pat_sanity(int fd)
>   {
>   	uint16_t dev_id = intel_get_drm_devid(fd);
> +	unsigned int gfx_ver = intel_graphics_ver(dev_id);
>   	struct intel_pat_cache pat_sw_config = {};
>   	int32_t parsed;
>   	bool has_uc_comp = false, has_wt = false;
>   
>   	parsed = xe_fetch_pat_sw_config(fd, &pat_sw_config);
>   
> -	if (intel_graphics_ver(dev_id) >= IP_VER(20, 0)) {
> +	if (gfx_ver >= IP_VER(20, 0)) {
>   		for (int i = 0; i < parsed; i++) {
>   			uint32_t pat = pat_sw_config.entries[i].pat;
>   			if (pat_sw_config.entries[i].rsvd)
> @@ -144,13 +196,28 @@ static void pat_sanity(int fd)
>   	} else {
>   		has_wt = true;
>   	}
> -	igt_assert_eq(pat_sw_config.max_index, intel_get_max_pat_index(fd));
> -	igt_assert_eq(pat_sw_config.uc, intel_get_pat_idx_uc(fd));
> -	igt_assert_eq(pat_sw_config.wb, intel_get_pat_idx_wb(fd));
> +
> +	/*
> +	 * Validate that the selected PAT indices actually have the expected
> +	 * cache types rather than comparing against hardcoded values.
> +	 */
> +	igt_assert_f(pat_entry_is_uc(gfx_ver, pat_sw_config.entries[pat_sw_config.uc].pat),
> +		     "UC index %d does not point to an uncached entry (pat=0x%x)\n",
> +		     pat_sw_config.uc, pat_sw_config.entries[pat_sw_config.uc].pat);
> +	igt_assert_f(pat_entry_is_wb(gfx_ver, pat_sw_config.entries[pat_sw_config.wb].pat),
> +		     "WB index %d does not point to a WB/XA/XD entry (pat=0x%x)\n",
> +		     pat_sw_config.wb, pat_sw_config.entries[pat_sw_config.wb].pat);
>   	if (has_wt)
> -		igt_assert_eq(pat_sw_config.wt, intel_get_pat_idx_wt(fd));
> -	if (has_uc_comp)
> -		igt_assert_eq(pat_sw_config.uc_comp, intel_get_pat_idx_uc_comp(fd));
> +		igt_assert_f(pat_entry_is_wt(gfx_ver, pat_sw_config.entries[pat_sw_config.wt].pat),
> +			     "WT index %d does not point to a WT entry (pat=0x%x)\n",
> +			     pat_sw_config.wt, pat_sw_config.entries[pat_sw_config.wt].pat);
> +	if (has_uc_comp) {
> +		uint32_t uc_comp_pat = pat_sw_config.entries[pat_sw_config.uc_comp].pat;
> +
> +		igt_assert_f(pat_entry_is_uc_comp(gfx_ver, uc_comp_pat),
> +			     "UC_COMP index %d does not point to a compressed UC entry (pat=0x%x)\n",
> +			     pat_sw_config.uc_comp, uc_comp_pat);
> +	}
>   }
>   
>   /**

Re: [PATCH v2 i-g-t] lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe

[Matt Roper]

On Tue, Feb 24, 2026 at 11:00:05AM -0800, Wang, X wrote:
> 
> On 2/24/2026 09:07, himanshu.girotra@intel.com wrote:
> > From: Himanshu Girotra <himanshu.girotra@intel.com>
> > 
> > IGT should treat the kernel as authoritative for PAT configuration
> > rather than replicating platform-specific logic and workaround
> > adjustments in hardcoded tables, which is error-prone as PAT layouts
> > vary across platforms.
> > 
> > For Xe devices, query pat_sw_config from debugfs instead of using
> > hardcoded PAT indices. Remove the Xe-only hardcoded entries and
> > retain the i915 fallback for older platforms.
> > 
> > Drop the now-redundant max_index assert in pat_sanity().
> > 
> > v2: Drop redundant index asserts; instead validate actual PAT register contents for correct cache types (Matt Roper)
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Xin Wang <x.wang@intel.com>
> > Signed-off-by: Himanshu Girotra <himanshu.girotra@intel.com>
> > ---
> >   lib/intel_pat.c      | 37 ++++++++++----------
> >   tests/intel/xe_pat.c | 81 ++++++++++++++++++++++++++++++++++++++++----
> >   2 files changed, 94 insertions(+), 24 deletions(-)
> > 
> > diff --git a/lib/intel_pat.c b/lib/intel_pat.c
> > index 9815efc18..8660a2515 100644
> > --- a/lib/intel_pat.c
> > +++ b/lib/intel_pat.c
> > @@ -96,24 +96,27 @@ int32_t xe_get_pat_sw_config(int drm_fd, struct intel_pat_cache *xe_pat_cache)
> >   static void intel_get_pat_idx(int fd, struct intel_pat_cache *pat)
> >   {
> > -	uint16_t dev_id = intel_get_drm_devid(fd);
> > +	uint16_t dev_id;
> > +
> > +	/*
> > +	 * For Xe driver, query the kernel's PAT software configuration
> > +	 * via debugfs. The kernel is the authoritative source for PAT
> > +	 * indices, accounting for platform-specific workarounds
> > +	 * (e.g. Wa_16023588340) at runtime.
> > +	 */
> > +	if (is_xe_device(fd)) {
> > +		int32_t parsed = xe_get_pat_sw_config(fd, pat);
> > +
> > +		igt_assert_f(parsed > 0,
> > +			     "Failed to get PAT sw_config from debugfs (parsed=%d)\n",
> > +			     parsed);
> > +		return;
> > +	}
> > -	if (intel_graphics_ver(dev_id) == IP_VER(35, 11)) {
> > -		pat->uc = 3;
> > -		pat->wb = 2;
> > -		pat->max_index = 31;
> > -	} else if (intel_get_device_info(dev_id)->graphics_ver == 30 ||
> > -		   intel_get_device_info(dev_id)->graphics_ver == 20) {
> > -		pat->uc = 3;
> > -		pat->wt = 15; /* Compressed + WB-transient */
> > -		pat->wb = 2;
> > -		pat->uc_comp = 12; /* Compressed + UC, XE2 and later */
> > -		pat->max_index = 31;
> > -
> > -		/* Wa_16023588340: CLOS3 entries at end of table are unusable */
> > -		if (intel_graphics_ver(dev_id) == IP_VER(20, 1))
> > -			pat->max_index -= 4;
> > -	} else if (IS_METEORLAKE(dev_id)) {
> > +	/* i915 fallback: hardcoded PAT indices */
> Actually, from the very beginning when I modified the intel_pat library,
> I wanted to remove this IGT code
> (https://patchwork.freedesktop.org/series/157481/#rev2).
> However, there was a problem: in the IGT test, the xe_oa test would drop
> root privileges before starting the test. You can see the specific issue
> in the CI.FULL fail case of your first version
> (https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14590/shard-bmg-2/igt@xe_oa@mmio-triggered-reports@oag-0.html).
> I previously tried caching the read pat table to prevent it from being read
> again after
> dropping the root. However, while caching at the library level is advisable,
> cached
> data can become problematic, especially when running on different GPUs.
> Therefore,
> I didn't modify this part. Instead, I validated this data in pat_santiy to
> prevent errors
> caused by not updating it in the IGT in a timely manner.

I think this is really just a bug in the xe_oa test.  The test itself
should be collecting the information it needs (including figuring out
appropriate PAT indices) before it drops privileges and loses access to
that information.

Part of the problem with xe_oa in general is that it isn't even using
the Xe programming model but rather is trying to use the bufops library
which was really intended mostly for i915.  bufops does run on Xe in
order to provide compatibility for display tests and such that need to
execute on both drivers, but if you use it you lose the ability to
directly control buffer mappings (including PAT), synchronization, etc.
because the library tries to handle that all implicitly internally. So
that also means the bufops just isn't compatible with tests like xe_oa
that drop privilege because the library doesn't have the necessary
permissions to perform some of the operations it wants to and doesn't
provide a way for the test to pass in the necessary information.


Matt

> 
> Xin
> 
> 
> > +	dev_id = intel_get_drm_devid(fd);
> > +
> > +	if (IS_METEORLAKE(dev_id)) {
> >   		pat->uc = 2;
> >   		pat->wt = 1;
> >   		pat->wb = 3;
> > diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
> > index 21547c84e..6ad6adab7 100644
> > --- a/tests/intel/xe_pat.c
> > +++ b/tests/intel/xe_pat.c
> > @@ -103,6 +103,57 @@ static void userptr_coh_none(int fd)
> >   #define COH_MODE_1WAY		2
> >   #define COH_MODE_2WAY		3
> > +/* Pre-Xe2 PAT bit fields (from kernel xe_pat.c) */
> > +#define XELP_MEM_TYPE_MASK	GENMASK(1, 0)
> > +
> > +static bool pat_entry_is_uc(unsigned int gfx_ver, uint32_t pat)
> > +{
> > +	if (gfx_ver >= IP_VER(20, 0))
> > +		return REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_UC &&
> > +		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
> > +
> > +	if (gfx_ver >= IP_VER(12, 70))
> > +		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
> > +
> > +	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 0;
> > +}
> > +
> > +static bool pat_entry_is_wb(unsigned int gfx_ver, uint32_t pat)
> > +{
> > +	if (gfx_ver >= IP_VER(20, 0)) {
> > +		uint32_t l3 = REG_FIELD_GET(XE2_L3_POLICY, pat);
> > +
> > +		return l3 == L3_CACHE_POLICY_WB || l3 == L3_CACHE_POLICY_XD;
> > +	}
> > +
> > +	if (gfx_ver >= IP_VER(12, 70))
> > +		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WB;
> > +
> > +	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 3;
> > +}
> > +
> > +static bool pat_entry_is_wt(unsigned int gfx_ver, uint32_t pat)
> > +{
> > +	if (gfx_ver >= IP_VER(20, 0))
> > +		return REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_XD &&
> > +		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WT;
> > +
> > +	if (gfx_ver >= IP_VER(12, 70))
> > +		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WT;
> > +
> > +	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 2;
> > +}
> > +
> > +static bool pat_entry_is_uc_comp(unsigned int gfx_ver, uint32_t pat)
> > +{
> > +	if (gfx_ver >= IP_VER(20, 0))
> > +		return !!(pat & XE2_COMP_EN) &&
> > +		       REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_UC &&
> > +		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
> > +
> > +	return false;
> > +}
> > +
> >   static int xe_fetch_pat_sw_config(int fd, struct intel_pat_cache *pat_sw_config)
> >   {
> >   	int32_t parsed = xe_get_pat_sw_config(fd, pat_sw_config);
> > @@ -120,13 +171,14 @@ static int xe_fetch_pat_sw_config(int fd, struct intel_pat_cache *pat_sw_config)
> >   static void pat_sanity(int fd)
> >   {
> >   	uint16_t dev_id = intel_get_drm_devid(fd);
> > +	unsigned int gfx_ver = intel_graphics_ver(dev_id);
> >   	struct intel_pat_cache pat_sw_config = {};
> >   	int32_t parsed;
> >   	bool has_uc_comp = false, has_wt = false;
> >   	parsed = xe_fetch_pat_sw_config(fd, &pat_sw_config);
> > -	if (intel_graphics_ver(dev_id) >= IP_VER(20, 0)) {
> > +	if (gfx_ver >= IP_VER(20, 0)) {
> >   		for (int i = 0; i < parsed; i++) {
> >   			uint32_t pat = pat_sw_config.entries[i].pat;
> >   			if (pat_sw_config.entries[i].rsvd)
> > @@ -144,13 +196,28 @@ static void pat_sanity(int fd)
> >   	} else {
> >   		has_wt = true;
> >   	}
> > -	igt_assert_eq(pat_sw_config.max_index, intel_get_max_pat_index(fd));
> > -	igt_assert_eq(pat_sw_config.uc, intel_get_pat_idx_uc(fd));
> > -	igt_assert_eq(pat_sw_config.wb, intel_get_pat_idx_wb(fd));
> > +
> > +	/*
> > +	 * Validate that the selected PAT indices actually have the expected
> > +	 * cache types rather than comparing against hardcoded values.
> > +	 */
> > +	igt_assert_f(pat_entry_is_uc(gfx_ver, pat_sw_config.entries[pat_sw_config.uc].pat),
> > +		     "UC index %d does not point to an uncached entry (pat=0x%x)\n",
> > +		     pat_sw_config.uc, pat_sw_config.entries[pat_sw_config.uc].pat);
> > +	igt_assert_f(pat_entry_is_wb(gfx_ver, pat_sw_config.entries[pat_sw_config.wb].pat),
> > +		     "WB index %d does not point to a WB/XA/XD entry (pat=0x%x)\n",
> > +		     pat_sw_config.wb, pat_sw_config.entries[pat_sw_config.wb].pat);
> >   	if (has_wt)
> > -		igt_assert_eq(pat_sw_config.wt, intel_get_pat_idx_wt(fd));
> > -	if (has_uc_comp)
> > -		igt_assert_eq(pat_sw_config.uc_comp, intel_get_pat_idx_uc_comp(fd));
> > +		igt_assert_f(pat_entry_is_wt(gfx_ver, pat_sw_config.entries[pat_sw_config.wt].pat),
> > +			     "WT index %d does not point to a WT entry (pat=0x%x)\n",
> > +			     pat_sw_config.wt, pat_sw_config.entries[pat_sw_config.wt].pat);
> > +	if (has_uc_comp) {
> > +		uint32_t uc_comp_pat = pat_sw_config.entries[pat_sw_config.uc_comp].pat;
> > +
> > +		igt_assert_f(pat_entry_is_uc_comp(gfx_ver, uc_comp_pat),
> > +			     "UC_COMP index %d does not point to a compressed UC entry (pat=0x%x)\n",
> > +			     pat_sw_config.uc_comp, uc_comp_pat);
> > +	}
> >   }
> >   /**

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

✗ Xe.CI.BAT: failure for lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1706 bytes --]

== Series Details ==

Series: lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe (rev2)
URL   : https://patchwork.freedesktop.org/series/161927/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8769_BAT -> XEIGTPW_14610_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_14610_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_14610_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 14)
------------------------------

  Additional (1): bat-bmg-3 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_14610_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_multigpu_svm@mgpu-xgpu-access-basic:
    - bat-bmg-3:          NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/bat-bmg-3/igt@xe_multigpu_svm@mgpu-xgpu-access-basic.html

  


Build changes
-------------

  * IGT: IGT_8769 -> IGTPW_14610
  * Linux: xe-4607-189174b3312588d97dc467dca7cfb9dce42ab81b -> xe-4609-4caa4c7d4ff7bd4d24bca8e795773e460eb8bbfe

  IGTPW_14610: 14610
  IGT_8769: 8769
  xe-4607-189174b3312588d97dc467dca7cfb9dce42ab81b: 189174b3312588d97dc467dca7cfb9dce42ab81b
  xe-4609-4caa4c7d4ff7bd4d24bca8e795773e460eb8bbfe: 4caa4c7d4ff7bd4d24bca8e795773e460eb8bbfe

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/index.html

[-- Attachment #2: Type: text/html, Size: 2301 bytes --]

✗ i915.CI.BAT: failure for lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3036 bytes --]

== Series Details ==

Series: lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe (rev2)
URL   : https://patchwork.freedesktop.org/series/161927/
State : failure

== Summary ==

CI Bug Log - changes from IGT_8769 -> IGTPW_14610
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_14610 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_14610, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14610/index.html

Participating hosts (43 -> 41)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_14610:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_lmem_swapping@basic:
    - bat-dg2-8:          [PASS][1] -> [ABORT][2] +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8769/bat-dg2-8/igt@gem_lmem_swapping@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14610/bat-dg2-8/igt@gem_lmem_swapping@basic.html

  
Known issues
------------

  Here are the changes found in IGTPW_14610 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-2:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8769/bat-arlh-2/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14610/bat-arlh-2/igt@i915_selftest@live@workarounds.html
    - bat-atsm-1:         NOTRUN -> [DMESG-FAIL][5] ([i915#12061]) +1 other test dmesg-fail
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14610/bat-atsm-1/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-atsm-1:         [ABORT][6] -> [PASS][7] +1 other test pass
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8769/bat-atsm-1/igt@gem_lmem_swapping@parallel-random-engines.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14610/bat-atsm-1/igt@gem_lmem_swapping@parallel-random-engines.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8769 -> IGTPW_14610
  * Linux: CI_DRM_18038 -> CI_DRM_18040

  CI-20190529: 20190529
  CI_DRM_18038: 189174b3312588d97dc467dca7cfb9dce42ab81b @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_18040: 4caa4c7d4ff7bd4d24bca8e795773e460eb8bbfe @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_14610: 14610
  IGT_8769: 8769

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14610/index.html

[-- Attachment #2: Type: text/html, Size: 3787 bytes --]

✗ Xe.CI.FULL: failure for lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9948 bytes --]

== Series Details ==

Series: lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe (rev2)
URL   : https://patchwork.freedesktop.org/series/161927/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8769_FULL -> XEIGTPW_14610_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_14610_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_14610_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_14610_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-race-prefetch:
    - shard-bmg:          NOTRUN -> [ABORT][1] +23 other tests abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-6/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-prefetch.html

  * igt@xe_exec_system_allocator@threads-many-large-execqueues-malloc-prefetch-madvise:
    - shard-lnl:          NOTRUN -> [ABORT][2] +23 other tests abort
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-2/igt@xe_exec_system_allocator@threads-many-large-execqueues-malloc-prefetch-madvise.html

  
Known issues
------------

  Here are the changes found in XEIGTPW_14610_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#2887])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-3/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2887])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-1/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#373])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-3/igt@kms_chamelium_hpd@hdmi-hpd-fast.html
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2252])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-8/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-bmg:          NOTRUN -> [FAIL][7] ([Intel XE#1178] / [Intel XE#3304]) +1 other test fail
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-2/igt@kms_content_protection@atomic-hdcp14.html
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#6973])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-8/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_cursor_crc@cursor-sliding-32x32:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1424])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-6/igt@kms_cursor_crc@cursor-sliding-32x32.html
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2320])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-1/igt@kms_cursor_crc@cursor-sliding-32x32.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#7178])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#7178])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#6312] / [Intel XE#651]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#4141])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2311]) +2 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#5020])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-2/igt@kms_plane_multiple@tiling-y.html
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#5020])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-7/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#870])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-8/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#1406] / [Intel XE#1489])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-8/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-pr-cursor-plane-move:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#1406]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-2/igt@kms_psr@fbc-pr-cursor-plane-move.html

  * igt@kms_psr@pr-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-8/igt@kms_psr@pr-sprite-plane-onoff.html

  * igt@xe_exec_basic@multigpu-once-null-defer-bind:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#1392]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-3/igt@xe_exec_basic@multigpu-once-null-defer-bind.html

  * igt@xe_exec_basic@multigpu-once-null-defer-mmap:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2322]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-2/igt@xe_exec_basic@multigpu-once-null-defer-mmap.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-basic:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#6874]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-5/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-basic.html
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#6874]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-5/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-basic.html

  * igt@xe_oa@syncs-userptr-wait:
    - shard-bmg:          NOTRUN -> [ABORT][26] ([Intel XE#7270]) +1 other test abort
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-bmg-4/igt@xe_oa@syncs-userptr-wait.html
    - shard-lnl:          NOTRUN -> [ABORT][27] ([Intel XE#7270]) +1 other test abort
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/shard-lnl-1/igt@xe_oa@syncs-userptr-wait.html

  
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6973]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6973
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7270]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7270
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870


Build changes
-------------

  * IGT: IGT_8769 -> IGTPW_14610
  * Linux: xe-4607-189174b3312588d97dc467dca7cfb9dce42ab81b -> xe-4609-4caa4c7d4ff7bd4d24bca8e795773e460eb8bbfe

  IGTPW_14610: 14610
  IGT_8769: 8769
  xe-4607-189174b3312588d97dc467dca7cfb9dce42ab81b: 189174b3312588d97dc467dca7cfb9dce42ab81b
  xe-4609-4caa4c7d4ff7bd4d24bca8e795773e460eb8bbfe: 4caa4c7d4ff7bd4d24bca8e795773e460eb8bbfe

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14610/index.html

[-- Attachment #2: Type: text/html, Size: 11460 bytes --]

Re: [PATCH v2 i-g-t] lib/intel_pat: use kernel debugfs as authoritative PAT source for Xe

[Matt Roper]

On Tue, Feb 24, 2026 at 10:37:37PM +0530, himanshu.girotra@intel.com wrote:
> From: Himanshu Girotra <himanshu.girotra@intel.com>
> 
> IGT should treat the kernel as authoritative for PAT configuration
> rather than replicating platform-specific logic and workaround
> adjustments in hardcoded tables, which is error-prone as PAT layouts
> vary across platforms.
> 
> For Xe devices, query pat_sw_config from debugfs instead of using
> hardcoded PAT indices. Remove the Xe-only hardcoded entries and
> retain the i915 fallback for older platforms.
> 
> Drop the now-redundant max_index assert in pat_sanity().
> 
> v2: Drop redundant index asserts; instead validate actual PAT register contents for correct cache types (Matt Roper)
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Xin Wang <x.wang@intel.com>
> Signed-off-by: Himanshu Girotra <himanshu.girotra@intel.com>
> ---
>  lib/intel_pat.c      | 37 ++++++++++----------
>  tests/intel/xe_pat.c | 81 ++++++++++++++++++++++++++++++++++++++++----
>  2 files changed, 94 insertions(+), 24 deletions(-)
> 
> diff --git a/lib/intel_pat.c b/lib/intel_pat.c
> index 9815efc18..8660a2515 100644
> --- a/lib/intel_pat.c
> +++ b/lib/intel_pat.c
> @@ -96,24 +96,27 @@ int32_t xe_get_pat_sw_config(int drm_fd, struct intel_pat_cache *xe_pat_cache)
>  
>  static void intel_get_pat_idx(int fd, struct intel_pat_cache *pat)
>  {
> -	uint16_t dev_id = intel_get_drm_devid(fd);
> +	uint16_t dev_id;
> +
> +	/*
> +	 * For Xe driver, query the kernel's PAT software configuration
> +	 * via debugfs. The kernel is the authoritative source for PAT
> +	 * indices, accounting for platform-specific workarounds
> +	 * (e.g. Wa_16023588340) at runtime.
> +	 */
> +	if (is_xe_device(fd)) {
> +		int32_t parsed = xe_get_pat_sw_config(fd, pat);
> +
> +		igt_assert_f(parsed > 0,
> +			     "Failed to get PAT sw_config from debugfs (parsed=%d)\n",
> +			     parsed);
> +		return;
> +	}
>  
> -	if (intel_graphics_ver(dev_id) == IP_VER(35, 11)) {
> -		pat->uc = 3;
> -		pat->wb = 2;
> -		pat->max_index = 31;
> -	} else if (intel_get_device_info(dev_id)->graphics_ver == 30 ||
> -		   intel_get_device_info(dev_id)->graphics_ver == 20) {
> -		pat->uc = 3;
> -		pat->wt = 15; /* Compressed + WB-transient */
> -		pat->wb = 2;
> -		pat->uc_comp = 12; /* Compressed + UC, XE2 and later */
> -		pat->max_index = 31;
> -
> -		/* Wa_16023588340: CLOS3 entries at end of table are unusable */
> -		if (intel_graphics_ver(dev_id) == IP_VER(20, 1))
> -			pat->max_index -= 4;
> -	} else if (IS_METEORLAKE(dev_id)) {
> +	/* i915 fallback: hardcoded PAT indices */
> +	dev_id = intel_get_drm_devid(fd);
> +
> +	if (IS_METEORLAKE(dev_id)) {
>  		pat->uc = 2;
>  		pat->wt = 1;
>  		pat->wb = 3;
> diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
> index 21547c84e..6ad6adab7 100644
> --- a/tests/intel/xe_pat.c
> +++ b/tests/intel/xe_pat.c
> @@ -103,6 +103,57 @@ static void userptr_coh_none(int fd)
>  #define COH_MODE_1WAY		2
>  #define COH_MODE_2WAY		3
>  
> +/* Pre-Xe2 PAT bit fields (from kernel xe_pat.c) */
> +#define XELP_MEM_TYPE_MASK	GENMASK(1, 0)
> +
> +static bool pat_entry_is_uc(unsigned int gfx_ver, uint32_t pat)
> +{
> +	if (gfx_ver >= IP_VER(20, 0))
> +		return REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_UC &&
> +		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
> +
> +	if (gfx_ver >= IP_VER(12, 70))
> +		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
> +
> +	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 0;
> +}
> +
> +static bool pat_entry_is_wb(unsigned int gfx_ver, uint32_t pat)
> +{
> +	if (gfx_ver >= IP_VER(20, 0)) {
> +		uint32_t l3 = REG_FIELD_GET(XE2_L3_POLICY, pat);
> +
> +		return l3 == L3_CACHE_POLICY_WB || l3 == L3_CACHE_POLICY_XD;
> +	}
> +
> +	if (gfx_ver >= IP_VER(12, 70))
> +		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WB;
> +
> +	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 3;
> +}
> +
> +static bool pat_entry_is_wt(unsigned int gfx_ver, uint32_t pat)
> +{
> +	if (gfx_ver >= IP_VER(20, 0))
> +		return REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_XD &&
> +		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WT;
> +
> +	if (gfx_ver >= IP_VER(12, 70))
> +		return REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_WT;
> +
> +	return REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat) == 2;
> +}
> +
> +static bool pat_entry_is_uc_comp(unsigned int gfx_ver, uint32_t pat)
> +{
> +	if (gfx_ver >= IP_VER(20, 0))
> +		return !!(pat & XE2_COMP_EN) &&
> +		       REG_FIELD_GET(XE2_L3_POLICY, pat) == L3_CACHE_POLICY_UC &&
> +		       REG_FIELD_GET(XE2_L4_POLICY, pat) == L4_CACHE_POLICY_UC;
> +
> +	return false;

Minor nitpick:  I think it's slightly more common to use an "early
bailout" pattern (and it reduces indentation a bit for the interesting
case).  I.e.,

        if (gfx_ver < IP_VER(20, 0))
                return false;

        return ...

For simplicity, I'd also just make this helper function check whether a
PAT is compressed and not worry about the UC part.  The caller can
simply do

        pat_entry_is_compressed() && pat_entry_is_uc()

to test for uc_comp


> +}
> +
>  static int xe_fetch_pat_sw_config(int fd, struct intel_pat_cache *pat_sw_config)
>  {
>  	int32_t parsed = xe_get_pat_sw_config(fd, pat_sw_config);
> @@ -120,13 +171,14 @@ static int xe_fetch_pat_sw_config(int fd, struct intel_pat_cache *pat_sw_config)
>  static void pat_sanity(int fd)
>  {
>  	uint16_t dev_id = intel_get_drm_devid(fd);
> +	unsigned int gfx_ver = intel_graphics_ver(dev_id);
>  	struct intel_pat_cache pat_sw_config = {};
>  	int32_t parsed;
>  	bool has_uc_comp = false, has_wt = false;
>  
>  	parsed = xe_fetch_pat_sw_config(fd, &pat_sw_config);
>  
> -	if (intel_graphics_ver(dev_id) >= IP_VER(20, 0)) {
> +	if (gfx_ver >= IP_VER(20, 0)) {
>  		for (int i = 0; i < parsed; i++) {
>  			uint32_t pat = pat_sw_config.entries[i].pat;
>  			if (pat_sw_config.entries[i].rsvd)
> @@ -144,13 +196,28 @@ static void pat_sanity(int fd)
>  	} else {
>  		has_wt = true;
>  	}
> -	igt_assert_eq(pat_sw_config.max_index, intel_get_max_pat_index(fd));
> -	igt_assert_eq(pat_sw_config.uc, intel_get_pat_idx_uc(fd));
> -	igt_assert_eq(pat_sw_config.wb, intel_get_pat_idx_wb(fd));
> +
> +	/*
> +	 * Validate that the selected PAT indices actually have the expected
> +	 * cache types rather than comparing against hardcoded values.
> +	 */
> +	igt_assert_f(pat_entry_is_uc(gfx_ver, pat_sw_config.entries[pat_sw_config.uc].pat),
> +		     "UC index %d does not point to an uncached entry (pat=0x%x)\n",

Nitpick:  It's slightly more idiomatic to use "%#x" to have the "0x"
prefix added automatically.


Anyway, the overall changes look good to me, so up to you if you want to
make any of the suggestions above or not.  Either way,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>



Matt

> +		     pat_sw_config.uc, pat_sw_config.entries[pat_sw_config.uc].pat);
> +	igt_assert_f(pat_entry_is_wb(gfx_ver, pat_sw_config.entries[pat_sw_config.wb].pat),
> +		     "WB index %d does not point to a WB/XA/XD entry (pat=0x%x)\n",
> +		     pat_sw_config.wb, pat_sw_config.entries[pat_sw_config.wb].pat);
>  	if (has_wt)
> -		igt_assert_eq(pat_sw_config.wt, intel_get_pat_idx_wt(fd));
> -	if (has_uc_comp)
> -		igt_assert_eq(pat_sw_config.uc_comp, intel_get_pat_idx_uc_comp(fd));
> +		igt_assert_f(pat_entry_is_wt(gfx_ver, pat_sw_config.entries[pat_sw_config.wt].pat),
> +			     "WT index %d does not point to a WT entry (pat=0x%x)\n",
> +			     pat_sw_config.wt, pat_sw_config.entries[pat_sw_config.wt].pat);
> +	if (has_uc_comp) {
> +		uint32_t uc_comp_pat = pat_sw_config.entries[pat_sw_config.uc_comp].pat;
> +
> +		igt_assert_f(pat_entry_is_uc_comp(gfx_ver, uc_comp_pat),
> +			     "UC_COMP index %d does not point to a compressed UC entry (pat=0x%x)\n",
> +			     pat_sw_config.uc_comp, uc_comp_pat);
> +	}
>  }
>  
>  /**
> -- 
> 2.50.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation