[PATCH v10 0/2] lib/intel_device_info: get the xe .graphics_rel from GMD_ID

[PATCH v10 0/2] lib/intel_device_info: get the xe .graphics_rel from GMD_ID

[Xin Wang]

This series enables IGT to retrieve the accurate IP minor version
(graphics_rel) at runtime for xe platforms with GMD_ID support,
instead of relying on hardcoded values in the PCI device table.

Background:
-----------
Current IGT uses static PCI device tables with hardcoded graphics_rel
values. For Xe2 platforms, Different device instances may have
different graphics_rel (minor version) values

The kernel's GMD_ID ioctl provides accurate runtime IP version
information (ip_ver_major.ip_ver_minor) which should be used for
platform-specific workarounds and feature detection.

Solution:
---------
This series adds support to query xe device info at runtime:

Patch 1/2: Get runtime xe device graphics version from GMD_ID
- Populate graphics versions in xe_device from GMD_ID ioctl
- Cache device ipver by devid in global map for efficient lookup
- Provide xe_ipver_cache_lookup() API for other components

Patch 2/2: Query runtime xe device graphics versions
- Use runtime xe device ipver for Gen20+ platforms
- Use weak symbol linkage to avoid breaking static library builds
- Remove hardcoded graphics_rel from static table for xe platforms

Benefits:
---------
- Accurate IP version for platform-specific workarounds
- Proper feature detection for hardware variants
- Unified device info API between i915 and xe drivers
- No changes needed to existing test code

V2:
- set the graphics version info in xe_device_get() don't copy 
  the whole struct of the intel_device_info 
- update the graphics_rel when the info is already in the cache
V3:
- Optimize the coding style
V4:
- add braces around the else statement body
V5:
- add new struct xe_device_ipver to hold the ipver info
- separate cache map to eliminate collision (Roper, Matthew D)
- changed function name to xe_ipver_cache_lookup() to avoid 
  confusion (Roper, Matthew D)
V6:
- optimize the coding style. (Summers, Stuart)
V7:
- rebased to latest mainline

Xin Wang (2):
  lib/xe/xe_query: Get runtime xe device graphics version from GMD_ID
  lib/intel_device_info: Query runtime xe device graphics versions

 lib/intel_chipset.h     |  6 +++++
 lib/intel_device_info.c | 26 +++++++++++++++++---
 lib/xe/xe_query.c       | 54 ++++++++++++++++++++++++++++++++++++++++-
 lib/xe/xe_query.h       |  4 +++
 4 files changed, 86 insertions(+), 4 deletions(-)

-- 
2.43.0

[PATCH v10 1/2] lib/xe/xe_query: Get runtime xe device graphics version from GMD_ID

[Xin Wang]

This allows IGT to query the exact IP version for xe platforms.

Key changes:
- Add xe_device_ipver field to xe_device structure
- set the graphics versions based on the GMD_ID
- Cache device ipver in global map indexed by devid for efficient lookup
- Implement xe_ipver_cache_lookup() to retrieve cached ipver by devid
- Clean up cached device ipver when xe_device is released

V2:
- add new struct xe_device_ipver to hold the ipver info
- separate cache map to eliminate collision (Roper, Matthew D)
- changed function name to xe_ipver_cache_lookup() to avoid
  confusion (Roper, Matthew D)

V3:
- optimize the coding style. (Summers, Stuart)

Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Xin Wang <x.wang@intel.com>
Reviewed-by: Ravi Kumar V <ravi.kumar.vodapalli@intel.com>
---
 lib/intel_chipset.h |  6 +++++
 lib/xe/xe_query.c   | 54 ++++++++++++++++++++++++++++++++++++++++++++-
 lib/xe/xe_query.h   |  4 ++++
 3 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index cc2225110..424811f7c 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -100,6 +100,12 @@ struct intel_device_info {
 	const char *codename;
 };
 
+struct xe_device_ipver {
+	uint32_t devid;
+	uint16_t graphics_ver;
+	uint16_t graphics_rel;
+};
+
 const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
 
 const struct intel_cmds_info *intel_get_cmds_info(uint16_t devid) __attribute__((pure));
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 981d76948..823a29f2d 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -210,6 +210,22 @@ static struct xe_device_cache {
 	struct igt_map *map;
 } cache;
 
+static struct xe_ipver_cache {
+	pthread_mutex_t mutex;
+	struct igt_map *map;
+} xe_ipver;
+
+struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid)
+{
+	struct xe_device_ipver *ipver;
+
+	pthread_mutex_lock(&xe_ipver.mutex);
+	ipver = igt_map_search(xe_ipver.map, &devid);
+	pthread_mutex_unlock(&xe_ipver.mutex);
+
+	return ipver;
+}
+
 static struct xe_device *find_in_cache_unlocked(int fd)
 {
 	return igt_map_search(cache.map, &fd);
@@ -270,6 +286,24 @@ struct xe_device *xe_device_get(int fd)
 	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
 		xe_dev->gt_mask |= (1ull << xe_dev->gt_list->gt_list[gt].gt_id);
 
+	/*
+	 * Set graphics_ver and graphics_rel based on the main GT's GMD_ID.
+	 * We should use the hardcoded value for the non-GMD_ID platforms (ip_ver_major == 0)
+	 */
+	xe_dev->ipver.devid = 0;
+	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++) {
+		if (xe_dev->gt_list->gt_list[gt].type == DRM_XE_QUERY_GT_TYPE_MAIN &&
+		    xe_dev->gt_list->gt_list[gt].ip_ver_major) {
+			igt_debug("Setting graphics_ver to %u and graphics_rel to %u\n",
+				  xe_dev->gt_list->gt_list[gt].ip_ver_major,
+				  xe_dev->gt_list->gt_list[gt].ip_ver_minor);
+			xe_dev->ipver.graphics_ver = xe_dev->gt_list->gt_list[gt].ip_ver_major;
+			xe_dev->ipver.graphics_rel = xe_dev->gt_list->gt_list[gt].ip_ver_minor;
+			xe_dev->ipver.devid = xe_dev->dev_id;
+			break;
+		}
+	}
+
 	/* Tile IDs may be non-consecutive; keep a mask of valid IDs */
 	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
 		xe_dev->tile_mask |= (1ull << xe_dev->gt_list->gt_list[gt].tile_id);
@@ -304,6 +338,11 @@ struct xe_device *xe_device_get(int fd)
 	prev = find_in_cache_unlocked(fd);
 	if (!prev) {
 		igt_map_insert(cache.map, &xe_dev->fd, xe_dev);
+		if (xe_dev->ipver.devid) {
+			pthread_mutex_lock(&xe_ipver.mutex);
+			igt_map_insert(xe_ipver.map, &xe_dev->ipver.devid, &xe_dev->ipver);
+			pthread_mutex_unlock(&xe_ipver.mutex);
+		}
 	} else {
 		xe_device_free(xe_dev);
 		xe_dev = prev;
@@ -315,7 +354,15 @@ struct xe_device *xe_device_get(int fd)
 
 static void delete_in_cache(struct igt_map_entry *entry)
 {
-	xe_device_free((struct xe_device *)entry->data);
+	struct xe_device *xe_dev = (struct xe_device *)entry->data;
+
+	if (xe_dev->ipver.devid) {
+		pthread_mutex_lock(&xe_ipver.mutex);
+		igt_map_remove(xe_ipver.map, &xe_dev->ipver.devid, NULL);
+		pthread_mutex_unlock(&xe_ipver.mutex);
+	}
+
+	xe_device_free(xe_dev);
 }
 
 /**
@@ -365,13 +412,18 @@ static void xe_device_destroy_cache(void)
 	pthread_mutex_lock(&cache.cache_mutex);
 	igt_map_destroy(cache.map, delete_in_cache);
 	pthread_mutex_unlock(&cache.cache_mutex);
+	pthread_mutex_lock(&xe_ipver.mutex);
+	igt_map_destroy(xe_ipver.map, NULL);
+	pthread_mutex_unlock(&xe_ipver.mutex);
 }
 
 static void xe_device_cache_init(void)
 {
 	pthread_mutex_init(&cache.cache_mutex, NULL);
+	pthread_mutex_init(&xe_ipver.mutex, NULL);
 	xe_device_destroy_cache();
 	cache.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
+	xe_ipver.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
 }
 
 #define xe_dev_FN(_NAME, _FIELD, _TYPE) \
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index d7a9f95f9..19690cff3 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -74,6 +74,9 @@ struct xe_device {
 
 	/** @dev_id: Device id of xe device */
 	uint16_t dev_id;
+
+	/** @ipver: Device ip version */
+	struct xe_device_ipver ipver;
 };
 
 #define xe_for_each_engine(__fd, __hwe) \
@@ -181,6 +184,7 @@ static inline void *xe_query_device(int fd, uint32_t type, uint32_t *size)
 }
 
 struct xe_device *xe_device_get(int fd);
+struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid);
 void xe_device_put(int fd);
 
 int xe_query_eu_count(int fd, int gt);
-- 
2.43.0

Re: [PATCH v10 1/2] lib/xe/xe_query: Get runtime xe device graphics version from GMD_ID

[Zbigniew Kempczyński]

On Mon, Jan 12, 2026 at 07:17:31PM +0000, Xin Wang wrote:
> This allows IGT to query the exact IP version for xe platforms.
> 
> Key changes:
> - Add xe_device_ipver field to xe_device structure
> - set the graphics versions based on the GMD_ID
> - Cache device ipver in global map indexed by devid for efficient lookup
> - Implement xe_ipver_cache_lookup() to retrieve cached ipver by devid
> - Clean up cached device ipver when xe_device is released
> 
> V2:
> - add new struct xe_device_ipver to hold the ipver info
> - separate cache map to eliminate collision (Roper, Matthew D)
> - changed function name to xe_ipver_cache_lookup() to avoid
>   confusion (Roper, Matthew D)
> 
> V3:
> - optimize the coding style. (Summers, Stuart)
> 
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Xin Wang <x.wang@intel.com>
> Reviewed-by: Ravi Kumar V <ravi.kumar.vodapalli@intel.com>
> ---
>  lib/intel_chipset.h |  6 +++++
>  lib/xe/xe_query.c   | 54 ++++++++++++++++++++++++++++++++++++++++++++-
>  lib/xe/xe_query.h   |  4 ++++
>  3 files changed, 63 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> index cc2225110..424811f7c 100644
> --- a/lib/intel_chipset.h
> +++ b/lib/intel_chipset.h
> @@ -100,6 +100,12 @@ struct intel_device_info {
>  	const char *codename;
>  };
>  
> +struct xe_device_ipver {
> +	uint32_t devid;
> +	uint16_t graphics_ver;
> +	uint16_t graphics_rel;
> +};
> +
>  const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
>  
>  const struct intel_cmds_info *intel_get_cmds_info(uint16_t devid) __attribute__((pure));
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index 981d76948..823a29f2d 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -210,6 +210,22 @@ static struct xe_device_cache {
>  	struct igt_map *map;
>  } cache;
>  
> +static struct xe_ipver_cache {
> +	pthread_mutex_t mutex;
> +	struct igt_map *map;
> +} xe_ipver;
> +
> +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid)
> +{
> +	struct xe_device_ipver *ipver;
> +
> +	pthread_mutex_lock(&xe_ipver.mutex);
> +	ipver = igt_map_search(xe_ipver.map, &devid);
> +	pthread_mutex_unlock(&xe_ipver.mutex);
> +
> +	return ipver;
> +}
> +

Please forgive me for sharing my thoughts only now.

I wondered about this a bit and according to current code shape
I don't like this design - especially ip_ver cache in xe_query.
I mean I don't like to use external cache which might or might not
be filled at time of calling intel_get_device_info().

At the moment I see following options:

1. Provide update function intel_device_info_update(devid, ver, rel)
   allowing to update rel field during xe_device_get(). This still
   keeps intel_device_info.c independent but rel field might be
   incorrect. BTW I would set it in static definition to -1 (max
   unsigned) to catch it is not set/updated properly during
   intel_get_device_info().

2. Add new function intel_get_device_info_by_fd() which will support
   passing fd instead devid and migrate code to use it. Most of our code
   uses fd to acquire device id before calling intel_get_device_info()
   [exception is igt_device_scan which uses pci devid directly]. This
   will break intel_device_info.c independency because we start calling
   driver functions, but maybe it is time to do this (GMD_ID).

   Digression: It seems when INTEL_DEVID_OVERRIDE won't work properly
   but I wouldn't care about it for now.

3. Mix 1 and 2 but build hash map from intel_device_match[] in the
   constructor and update it during xe_device_get(). Pros of this
   is we could stop using 'static __thread' for caching last info.

--
Zbigniew

>  static struct xe_device *find_in_cache_unlocked(int fd)
>  {
>  	return igt_map_search(cache.map, &fd);
> @@ -270,6 +286,24 @@ struct xe_device *xe_device_get(int fd)
>  	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
>  		xe_dev->gt_mask |= (1ull << xe_dev->gt_list->gt_list[gt].gt_id);
>  
> +	/*
> +	 * Set graphics_ver and graphics_rel based on the main GT's GMD_ID.
> +	 * We should use the hardcoded value for the non-GMD_ID platforms (ip_ver_major == 0)
> +	 */
> +	xe_dev->ipver.devid = 0;
> +	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++) {
> +		if (xe_dev->gt_list->gt_list[gt].type == DRM_XE_QUERY_GT_TYPE_MAIN &&
> +		    xe_dev->gt_list->gt_list[gt].ip_ver_major) {
> +			igt_debug("Setting graphics_ver to %u and graphics_rel to %u\n",
> +				  xe_dev->gt_list->gt_list[gt].ip_ver_major,
> +				  xe_dev->gt_list->gt_list[gt].ip_ver_minor);
> +			xe_dev->ipver.graphics_ver = xe_dev->gt_list->gt_list[gt].ip_ver_major;
> +			xe_dev->ipver.graphics_rel = xe_dev->gt_list->gt_list[gt].ip_ver_minor;
> +			xe_dev->ipver.devid = xe_dev->dev_id;
> +			break;
> +		}
> +	}
> +
>  	/* Tile IDs may be non-consecutive; keep a mask of valid IDs */
>  	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
>  		xe_dev->tile_mask |= (1ull << xe_dev->gt_list->gt_list[gt].tile_id);
> @@ -304,6 +338,11 @@ struct xe_device *xe_device_get(int fd)
>  	prev = find_in_cache_unlocked(fd);
>  	if (!prev) {
>  		igt_map_insert(cache.map, &xe_dev->fd, xe_dev);
> +		if (xe_dev->ipver.devid) {
> +			pthread_mutex_lock(&xe_ipver.mutex);
> +			igt_map_insert(xe_ipver.map, &xe_dev->ipver.devid, &xe_dev->ipver);
> +			pthread_mutex_unlock(&xe_ipver.mutex);
> +		}
>  	} else {
>  		xe_device_free(xe_dev);
>  		xe_dev = prev;
> @@ -315,7 +354,15 @@ struct xe_device *xe_device_get(int fd)
>  
>  static void delete_in_cache(struct igt_map_entry *entry)
>  {
> -	xe_device_free((struct xe_device *)entry->data);
> +	struct xe_device *xe_dev = (struct xe_device *)entry->data;
> +
> +	if (xe_dev->ipver.devid) {
> +		pthread_mutex_lock(&xe_ipver.mutex);
> +		igt_map_remove(xe_ipver.map, &xe_dev->ipver.devid, NULL);
> +		pthread_mutex_unlock(&xe_ipver.mutex);
> +	}
> +
> +	xe_device_free(xe_dev);
>  }
>  
>  /**
> @@ -365,13 +412,18 @@ static void xe_device_destroy_cache(void)
>  	pthread_mutex_lock(&cache.cache_mutex);
>  	igt_map_destroy(cache.map, delete_in_cache);
>  	pthread_mutex_unlock(&cache.cache_mutex);
> +	pthread_mutex_lock(&xe_ipver.mutex);
> +	igt_map_destroy(xe_ipver.map, NULL);
> +	pthread_mutex_unlock(&xe_ipver.mutex);
>  }
>  
>  static void xe_device_cache_init(void)
>  {
>  	pthread_mutex_init(&cache.cache_mutex, NULL);
> +	pthread_mutex_init(&xe_ipver.mutex, NULL);
>  	xe_device_destroy_cache();
>  	cache.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
> +	xe_ipver.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
>  }
>  
>  #define xe_dev_FN(_NAME, _FIELD, _TYPE) \
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index d7a9f95f9..19690cff3 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -74,6 +74,9 @@ struct xe_device {
>  
>  	/** @dev_id: Device id of xe device */
>  	uint16_t dev_id;
> +
> +	/** @ipver: Device ip version */
> +	struct xe_device_ipver ipver;
>  };
>  
>  #define xe_for_each_engine(__fd, __hwe) \
> @@ -181,6 +184,7 @@ static inline void *xe_query_device(int fd, uint32_t type, uint32_t *size)
>  }
>  
>  struct xe_device *xe_device_get(int fd);
> +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid);
>  void xe_device_put(int fd);
>  
>  int xe_query_eu_count(int fd, int gt);
> -- 
> 2.43.0
> 

Re: [PATCH v10 1/2] lib/xe/xe_query: Get runtime xe device graphics version from GMD_ID

[Wang, X]

Hi Zbigniew,
On 1/15/2026 00:00, Zbigniew Kempczyński wrote:
> On Mon, Jan 12, 2026 at 07:17:31PM +0000, Xin Wang wrote:
>> This allows IGT to query the exact IP version for xe platforms.
>>
>> Key changes:
>> - Add xe_device_ipver field to xe_device structure
>> - set the graphics versions based on the GMD_ID
>> - Cache device ipver in global map indexed by devid for efficient lookup
>> - Implement xe_ipver_cache_lookup() to retrieve cached ipver by devid
>> - Clean up cached device ipver when xe_device is released
>>
>> V2:
>> - add new struct xe_device_ipver to hold the ipver info
>> - separate cache map to eliminate collision (Roper, Matthew D)
>> - changed function name to xe_ipver_cache_lookup() to avoid
>>    confusion (Roper, Matthew D)
>>
>> V3:
>> - optimize the coding style. (Summers, Stuart)
>>
>> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Xin Wang <x.wang@intel.com>
>> Reviewed-by: Ravi Kumar V <ravi.kumar.vodapalli@intel.com>
>> ---
>>   lib/intel_chipset.h |  6 +++++
>>   lib/xe/xe_query.c   | 54 ++++++++++++++++++++++++++++++++++++++++++++-
>>   lib/xe/xe_query.h   |  4 ++++
>>   3 files changed, 63 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
>> index cc2225110..424811f7c 100644
>> --- a/lib/intel_chipset.h
>> +++ b/lib/intel_chipset.h
>> @@ -100,6 +100,12 @@ struct intel_device_info {
>>   	const char *codename;
>>   };
>>   
>> +struct xe_device_ipver {
>> +	uint32_t devid;
>> +	uint16_t graphics_ver;
>> +	uint16_t graphics_rel;
>> +};
>> +
>>   const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
>>   
>>   const struct intel_cmds_info *intel_get_cmds_info(uint16_t devid) __attribute__((pure));
>> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
>> index 981d76948..823a29f2d 100644
>> --- a/lib/xe/xe_query.c
>> +++ b/lib/xe/xe_query.c
>> @@ -210,6 +210,22 @@ static struct xe_device_cache {
>>   	struct igt_map *map;
>>   } cache;
>>   
>> +static struct xe_ipver_cache {
>> +	pthread_mutex_t mutex;
>> +	struct igt_map *map;
>> +} xe_ipver;
>> +
>> +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid)
>> +{
>> +	struct xe_device_ipver *ipver;
>> +
>> +	pthread_mutex_lock(&xe_ipver.mutex);
>> +	ipver = igt_map_search(xe_ipver.map, &devid);
>> +	pthread_mutex_unlock(&xe_ipver.mutex);
>> +
>> +	return ipver;
>> +}
>> +
> Please forgive me for sharing my thoughts only now.
>
> I wondered about this a bit and according to current code shape
> I don't like this design - especially ip_ver cache in xe_query.
> I mean I don't like to use external cache which might or might not
> be filled at time of calling intel_get_device_info().
>
> At the moment I see following options:
>
> 1. Provide update function intel_device_info_update(devid, ver, rel)
>     allowing to update rel field during xe_device_get(). This still
>     keeps intel_device_info.c independent but rel field might be
>     incorrect. BTW I would set it in static definition to -1 (max
>     unsigned) to catch it is not set/updated properly during
>     intel_get_device_info().
>
> 2. Add new function intel_get_device_info_by_fd() which will support
>     passing fd instead devid and migrate code to use it. Most of our code
>     uses fd to acquire device id before calling intel_get_device_info()
>     [exception is igt_device_scan which uses pci devid directly]. This
>     will break intel_device_info.c independency because we start calling
>     driver functions, but maybe it is time to do this (GMD_ID).
>
>     Digression: It seems when INTEL_DEVID_OVERRIDE won't work properly
>     but I wouldn't care about it for now.
>
> 3. Mix 1 and 2 but build hash map from intel_device_match[] in the
>     constructor and update it during xe_device_get(). Pros of this
>     is we could stop using 'static __thread' for caching last info.
>
> --
> Zbigniew
Thanks for the review. In the first version of the patch
(https://patchwork.freedesktop.org/series/155527/#rev2), I
introduced three new APIs specifically for Xe devices
(gen >= 20). However, the Xe.CI Full runs reported many
failures, and it became clear that a proper fix would
require changes across more components than I initially
expected.

For this series, my goal is to provide the smallest and
least-intrusive set of changes needed to resolve the
immediate issue, without triggering a broader refactor of
the device-info infrastructure.

I would like to try option 3 to address the current
solution.

>>   static struct xe_device *find_in_cache_unlocked(int fd)
>>   {
>> ...cut...
>>

Re: [PATCH v10 1/2] lib/xe/xe_query: Get runtime xe device graphics version from GMD_ID

[Matt Roper]

On Thu, Jan 15, 2026 at 09:00:53AM +0100, Zbigniew Kempczyński wrote:
> On Mon, Jan 12, 2026 at 07:17:31PM +0000, Xin Wang wrote:
> > This allows IGT to query the exact IP version for xe platforms.
> > 
> > Key changes:
> > - Add xe_device_ipver field to xe_device structure
> > - set the graphics versions based on the GMD_ID
> > - Cache device ipver in global map indexed by devid for efficient lookup
> > - Implement xe_ipver_cache_lookup() to retrieve cached ipver by devid
> > - Clean up cached device ipver when xe_device is released
> > 
> > V2:
> > - add new struct xe_device_ipver to hold the ipver info
> > - separate cache map to eliminate collision (Roper, Matthew D)
> > - changed function name to xe_ipver_cache_lookup() to avoid
> >   confusion (Roper, Matthew D)
> > 
> > V3:
> > - optimize the coding style. (Summers, Stuart)
> > 
> > Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Xin Wang <x.wang@intel.com>
> > Reviewed-by: Ravi Kumar V <ravi.kumar.vodapalli@intel.com>
> > ---
> >  lib/intel_chipset.h |  6 +++++
> >  lib/xe/xe_query.c   | 54 ++++++++++++++++++++++++++++++++++++++++++++-
> >  lib/xe/xe_query.h   |  4 ++++
> >  3 files changed, 63 insertions(+), 1 deletion(-)
> > 
> > diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> > index cc2225110..424811f7c 100644
> > --- a/lib/intel_chipset.h
> > +++ b/lib/intel_chipset.h
> > @@ -100,6 +100,12 @@ struct intel_device_info {
> >  	const char *codename;
> >  };
> >  
> > +struct xe_device_ipver {
> > +	uint32_t devid;
> > +	uint16_t graphics_ver;
> > +	uint16_t graphics_rel;
> > +};
> > +
> >  const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
> >  
> >  const struct intel_cmds_info *intel_get_cmds_info(uint16_t devid) __attribute__((pure));
> > diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> > index 981d76948..823a29f2d 100644
> > --- a/lib/xe/xe_query.c
> > +++ b/lib/xe/xe_query.c
> > @@ -210,6 +210,22 @@ static struct xe_device_cache {
> >  	struct igt_map *map;
> >  } cache;
> >  
> > +static struct xe_ipver_cache {
> > +	pthread_mutex_t mutex;
> > +	struct igt_map *map;
> > +} xe_ipver;
> > +
> > +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid)
> > +{
> > +	struct xe_device_ipver *ipver;
> > +
> > +	pthread_mutex_lock(&xe_ipver.mutex);
> > +	ipver = igt_map_search(xe_ipver.map, &devid);
> > +	pthread_mutex_unlock(&xe_ipver.mutex);
> > +
> > +	return ipver;
> > +}
> > +
> 
> Please forgive me for sharing my thoughts only now.
> 
> I wondered about this a bit and according to current code shape
> I don't like this design - especially ip_ver cache in xe_query.
> I mean I don't like to use external cache which might or might not
> be filled at time of calling intel_get_device_info().
> 
> At the moment I see following options:
> 
> 1. Provide update function intel_device_info_update(devid, ver, rel)
>    allowing to update rel field during xe_device_get(). This still
>    keeps intel_device_info.c independent but rel field might be
>    incorrect. BTW I would set it in static definition to -1 (max
>    unsigned) to catch it is not set/updated properly during
>    intel_get_device_info().
> 
> 2. Add new function intel_get_device_info_by_fd() which will support
>    passing fd instead devid and migrate code to use it. Most of our code
>    uses fd to acquire device id before calling intel_get_device_info()
>    [exception is igt_device_scan which uses pci devid directly]. This
>    will break intel_device_info.c independency because we start calling
>    driver functions, but maybe it is time to do this (GMD_ID).
> 
>    Digression: It seems when INTEL_DEVID_OVERRIDE won't work properly
>    but I wouldn't care about it for now.
> 
> 3. Mix 1 and 2 but build hash map from intel_device_match[] in the
>    constructor and update it during xe_device_get(). Pros of this
>    is we could stop using 'static __thread' for caching last info.

The problem is that "graphics version" and "media version" are not
supposed to be a characteristic of a general device type anymore.  An
individual device will have some version number, but another device of
the same "type" with the same PCI ID can can potentially have a
different IP version.  We've been lucky enough so far to still have
unique PCI IDs for cases where the version numbers are different (at
least for production parts), but this is not something that we're
supposed to be relying on since the IP disaggregation happened around
the MTL timeframe.  Personally I think that hacks that keep treating
versions as something associated with a device type are just making the
problem harder to untangle.

For a proper solution, I think we really need to separate the concept of
"traits associated with a type of device" (which is the stuff we have in
the device info structure which can be accurately looked up by PCI ID)
from "IP version associated with a specific device instance" (which on
modern platforms can only be accurately looked up in the context of a
specific device handle such as a FD).

So aside from a few special cases, we want IGT to stop translating PCI
IDs into version numbers and instead start translating fd's into version
numbers.  The special case exceptions I can think of that don't really
have a way to do fd-based lookups are: 

 * tools/tests that bypass the driver entirely (possibly running without
   the driver loaded) and just use libpciaccess for direct BAR access.
   Most of these either don't have version-based conditions or only have
   version conditions matching against very old platforms (where a
   PCIID-based lookup is "safe")

 * the old i915-era error dump decoder tool just reads its information
   (including PCI ID) from a dump file on disk.  The tool might be
   executed on a completely different machine from where the dump was
   originally captured.  I don't think this tool has been updated since
   gen8 (everyone switched over to using the Mesa tool instead), and I
   don't think it would function at all on any of our modern platforms.
   So if this tool is still useful at all, it would only be on ancient
   i915 platforms where a PCIID-based lookup is "safe."


The solution I suggested during an earlier review of this series was:

 * Create separate "version from PCI ID" APIs that can be used in the
   few special cases listed above, and migrate those uses over.

 * Change the signature of intel_gen / intel_graphics_ver to take an FD
   rather than a PCI ID; when running on Xe this would do the lookup via
   the query ioctl to get an accurate value.

 * Update intel_gen / intel_graphics_ver:
     - If running on i915, fall back to the device_info lookup that
       we've always used.  That's safe for all i915 platforms except
       MTL/ARL, and we were lucky enough that they never created any
       production MTL/ARL platforms where a single PCI ID had different
       possible versions, so it winds up being safe there too.

    - If running on Xe, use the query ioctl to obtain the version
      number.  This will return the proper value for all platforms
      officially supported by Xe (i.e., Xe2 and later).  It will return
      0 on pre-MTL platforms (which aren't officially supported), but in
      that case IGT can fall back to the i915 approach above.

I did a mockup of the first two parts several months ago:

  https://github.com/mattrope/intel-gpu-tools/commits/forupstream/version_query/

Since the function interface is changing, it's a lot of churn, but most
of it can be auto-converted quickly via Coccinelle.


Matt

> 
> --
> Zbigniew
> 
> >  static struct xe_device *find_in_cache_unlocked(int fd)
> >  {
> >  	return igt_map_search(cache.map, &fd);
> > @@ -270,6 +286,24 @@ struct xe_device *xe_device_get(int fd)
> >  	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
> >  		xe_dev->gt_mask |= (1ull << xe_dev->gt_list->gt_list[gt].gt_id);
> >  
> > +	/*
> > +	 * Set graphics_ver and graphics_rel based on the main GT's GMD_ID.
> > +	 * We should use the hardcoded value for the non-GMD_ID platforms (ip_ver_major == 0)
> > +	 */
> > +	xe_dev->ipver.devid = 0;
> > +	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++) {
> > +		if (xe_dev->gt_list->gt_list[gt].type == DRM_XE_QUERY_GT_TYPE_MAIN &&
> > +		    xe_dev->gt_list->gt_list[gt].ip_ver_major) {
> > +			igt_debug("Setting graphics_ver to %u and graphics_rel to %u\n",
> > +				  xe_dev->gt_list->gt_list[gt].ip_ver_major,
> > +				  xe_dev->gt_list->gt_list[gt].ip_ver_minor);
> > +			xe_dev->ipver.graphics_ver = xe_dev->gt_list->gt_list[gt].ip_ver_major;
> > +			xe_dev->ipver.graphics_rel = xe_dev->gt_list->gt_list[gt].ip_ver_minor;
> > +			xe_dev->ipver.devid = xe_dev->dev_id;
> > +			break;
> > +		}
> > +	}
> > +
> >  	/* Tile IDs may be non-consecutive; keep a mask of valid IDs */
> >  	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
> >  		xe_dev->tile_mask |= (1ull << xe_dev->gt_list->gt_list[gt].tile_id);
> > @@ -304,6 +338,11 @@ struct xe_device *xe_device_get(int fd)
> >  	prev = find_in_cache_unlocked(fd);
> >  	if (!prev) {
> >  		igt_map_insert(cache.map, &xe_dev->fd, xe_dev);
> > +		if (xe_dev->ipver.devid) {
> > +			pthread_mutex_lock(&xe_ipver.mutex);
> > +			igt_map_insert(xe_ipver.map, &xe_dev->ipver.devid, &xe_dev->ipver);
> > +			pthread_mutex_unlock(&xe_ipver.mutex);
> > +		}
> >  	} else {
> >  		xe_device_free(xe_dev);
> >  		xe_dev = prev;
> > @@ -315,7 +354,15 @@ struct xe_device *xe_device_get(int fd)
> >  
> >  static void delete_in_cache(struct igt_map_entry *entry)
> >  {
> > -	xe_device_free((struct xe_device *)entry->data);
> > +	struct xe_device *xe_dev = (struct xe_device *)entry->data;
> > +
> > +	if (xe_dev->ipver.devid) {
> > +		pthread_mutex_lock(&xe_ipver.mutex);
> > +		igt_map_remove(xe_ipver.map, &xe_dev->ipver.devid, NULL);
> > +		pthread_mutex_unlock(&xe_ipver.mutex);
> > +	}
> > +
> > +	xe_device_free(xe_dev);
> >  }
> >  
> >  /**
> > @@ -365,13 +412,18 @@ static void xe_device_destroy_cache(void)
> >  	pthread_mutex_lock(&cache.cache_mutex);
> >  	igt_map_destroy(cache.map, delete_in_cache);
> >  	pthread_mutex_unlock(&cache.cache_mutex);
> > +	pthread_mutex_lock(&xe_ipver.mutex);
> > +	igt_map_destroy(xe_ipver.map, NULL);
> > +	pthread_mutex_unlock(&xe_ipver.mutex);
> >  }
> >  
> >  static void xe_device_cache_init(void)
> >  {
> >  	pthread_mutex_init(&cache.cache_mutex, NULL);
> > +	pthread_mutex_init(&xe_ipver.mutex, NULL);
> >  	xe_device_destroy_cache();
> >  	cache.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
> > +	xe_ipver.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
> >  }
> >  
> >  #define xe_dev_FN(_NAME, _FIELD, _TYPE) \
> > diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> > index d7a9f95f9..19690cff3 100644
> > --- a/lib/xe/xe_query.h
> > +++ b/lib/xe/xe_query.h
> > @@ -74,6 +74,9 @@ struct xe_device {
> >  
> >  	/** @dev_id: Device id of xe device */
> >  	uint16_t dev_id;
> > +
> > +	/** @ipver: Device ip version */
> > +	struct xe_device_ipver ipver;
> >  };
> >  
> >  #define xe_for_each_engine(__fd, __hwe) \
> > @@ -181,6 +184,7 @@ static inline void *xe_query_device(int fd, uint32_t type, uint32_t *size)
> >  }
> >  
> >  struct xe_device *xe_device_get(int fd);
> > +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid);
> >  void xe_device_put(int fd);
> >  
> >  int xe_query_eu_count(int fd, int gt);
> > -- 
> > 2.43.0
> > 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v10 1/2] lib/xe/xe_query: Get runtime xe device graphics version from GMD_ID

[Wang, X]

On 1/16/2026 13:33, Matt Roper wrote:
> On Thu, Jan 15, 2026 at 09:00:53AM +0100, Zbigniew Kempczyński wrote:
>> On Mon, Jan 12, 2026 at 07:17:31PM +0000, Xin Wang wrote:
>>> This allows IGT to query the exact IP version for xe platforms.
>>>
>>> Key changes:
>>> - Add xe_device_ipver field to xe_device structure
>>> - set the graphics versions based on the GMD_ID
>>> - Cache device ipver in global map indexed by devid for efficient lookup
>>> - Implement xe_ipver_cache_lookup() to retrieve cached ipver by devid
>>> - Clean up cached device ipver when xe_device is released
>>>
>>> V2:
>>> - add new struct xe_device_ipver to hold the ipver info
>>> - separate cache map to eliminate collision (Roper, Matthew D)
>>> - changed function name to xe_ipver_cache_lookup() to avoid
>>>    confusion (Roper, Matthew D)
>>>
>>> V3:
>>> - optimize the coding style. (Summers, Stuart)
>>>
>>> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Signed-off-by: Xin Wang <x.wang@intel.com>
>>> Reviewed-by: Ravi Kumar V <ravi.kumar.vodapalli@intel.com>
>>> ---
>>>   lib/intel_chipset.h |  6 +++++
>>>   lib/xe/xe_query.c   | 54 ++++++++++++++++++++++++++++++++++++++++++++-
>>>   lib/xe/xe_query.h   |  4 ++++
>>>   3 files changed, 63 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
>>> index cc2225110..424811f7c 100644
>>> --- a/lib/intel_chipset.h
>>> +++ b/lib/intel_chipset.h
>>> @@ -100,6 +100,12 @@ struct intel_device_info {
>>>   	const char *codename;
>>>   };
>>>   
>>> +struct xe_device_ipver {
>>> +	uint32_t devid;
>>> +	uint16_t graphics_ver;
>>> +	uint16_t graphics_rel;
>>> +};
>>> +
>>>   const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
>>>   
>>>   const struct intel_cmds_info *intel_get_cmds_info(uint16_t devid) __attribute__((pure));
>>> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
>>> index 981d76948..823a29f2d 100644
>>> --- a/lib/xe/xe_query.c
>>> +++ b/lib/xe/xe_query.c
>>> @@ -210,6 +210,22 @@ static struct xe_device_cache {
>>>   	struct igt_map *map;
>>>   } cache;
>>>   
>>> +static struct xe_ipver_cache {
>>> +	pthread_mutex_t mutex;
>>> +	struct igt_map *map;
>>> +} xe_ipver;
>>> +
>>> +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid)
>>> +{
>>> +	struct xe_device_ipver *ipver;
>>> +
>>> +	pthread_mutex_lock(&xe_ipver.mutex);
>>> +	ipver = igt_map_search(xe_ipver.map, &devid);
>>> +	pthread_mutex_unlock(&xe_ipver.mutex);
>>> +
>>> +	return ipver;
>>> +}
>>> +
>> Please forgive me for sharing my thoughts only now.
>>
>> I wondered about this a bit and according to current code shape
>> I don't like this design - especially ip_ver cache in xe_query.
>> I mean I don't like to use external cache which might or might not
>> be filled at time of calling intel_get_device_info().
>>
>> At the moment I see following options:
>>
>> 1. Provide update function intel_device_info_update(devid, ver, rel)
>>     allowing to update rel field during xe_device_get(). This still
>>     keeps intel_device_info.c independent but rel field might be
>>     incorrect. BTW I would set it in static definition to -1 (max
>>     unsigned) to catch it is not set/updated properly during
>>     intel_get_device_info().
>>
>> 2. Add new function intel_get_device_info_by_fd() which will support
>>     passing fd instead devid and migrate code to use it. Most of our code
>>     uses fd to acquire device id before calling intel_get_device_info()
>>     [exception is igt_device_scan which uses pci devid directly]. This
>>     will break intel_device_info.c independency because we start calling
>>     driver functions, but maybe it is time to do this (GMD_ID).
>>
>>     Digression: It seems when INTEL_DEVID_OVERRIDE won't work properly
>>     but I wouldn't care about it for now.
>>
>> 3. Mix 1 and 2 but build hash map from intel_device_match[] in the
>>     constructor and update it during xe_device_get(). Pros of this
>>     is we could stop using 'static __thread' for caching last info.
> The problem is that "graphics version" and "media version" are not
> supposed to be a characteristic of a general device type anymore.  An
> individual device will have some version number, but another device of
> the same "type" with the same PCI ID can can potentially have a
> different IP version.  We've been lucky enough so far to still have
> unique PCI IDs for cases where the version numbers are different (at
> least for production parts), but this is not something that we're
> supposed to be relying on since the IP disaggregation happened around
> the MTL timeframe.  Personally I think that hacks that keep treating
> versions as something associated with a device type are just making the
> problem harder to untangle.
>
> For a proper solution, I think we really need to separate the concept of
> "traits associated with a type of device" (which is the stuff we have in
> the device info structure which can be accurately looked up by PCI ID)
> from "IP version associated with a specific device instance" (which on
> modern platforms can only be accurately looked up in the context of a
> specific device handle such as a FD).
>
> So aside from a few special cases, we want IGT to stop translating PCI
> IDs into version numbers and instead start translating fd's into version
> numbers.  The special case exceptions I can think of that don't really
> have a way to do fd-based lookups are:
>
>   * tools/tests that bypass the driver entirely (possibly running without
>     the driver loaded) and just use libpciaccess for direct BAR access.
>     Most of these either don't have version-based conditions or only have
>     version conditions matching against very old platforms (where a
>     PCIID-based lookup is "safe")
>
>   * the old i915-era error dump decoder tool just reads its information
>     (including PCI ID) from a dump file on disk.  The tool might be
>     executed on a completely different machine from where the dump was
>     originally captured.  I don't think this tool has been updated since
>     gen8 (everyone switched over to using the Mesa tool instead), and I
>     don't think it would function at all on any of our modern platforms.
>     So if this tool is still useful at all, it would only be on ancient
>     i915 platforms where a PCIID-based lookup is "safe."
>
>
> The solution I suggested during an earlier review of this series was:
>
>   * Create separate "version from PCI ID" APIs that can be used in the
>     few special cases listed above, and migrate those uses over.
>
>   * Change the signature of intel_gen / intel_graphics_ver to take an FD
>     rather than a PCI ID; when running on Xe this would do the lookup via
>     the query ioctl to get an accurate value.
>
>   * Update intel_gen / intel_graphics_ver:
>       - If running on i915, fall back to the device_info lookup that
>         we've always used.  That's safe for all i915 platforms except
>         MTL/ARL, and we were lucky enough that they never created any
>         production MTL/ARL platforms where a single PCI ID had different
>         possible versions, so it winds up being safe there too.
>
>      - If running on Xe, use the query ioctl to obtain the version
>        number.  This will return the proper value for all platforms
>        officially supported by Xe (i.e., Xe2 and later).  It will return
>        0 on pre-MTL platforms (which aren't officially supported), but in
>        that case IGT can fall back to the i915 approach above.
>
> I did a mockup of the first two parts several months ago:
>
>    https://github.com/mattrope/intel-gpu-tools/commits/forupstream/version_query/
>
> Since the function interface is changing, it's a lot of churn, but most
> of it can be auto-converted quickly via Coccinelle.
>
>
> Matt

I created 2 series:

fd-based API:
https://patchwork.freedesktop.org/series/160271/

inject the graphics ver from xe_device_get(), keep the API unchanged
https://patchwork.freedesktop.org/series/160239/

>> --
>> Zbigniew
>>
>>>   static struct xe_device *find_in_cache_unlocked(int fd)
>>>   {
>>>   	return igt_map_search(cache.map, &fd);
>>> @@ -270,6 +286,24 @@ struct xe_device *xe_device_get(int fd)
>>>   	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
>>>   		xe_dev->gt_mask |= (1ull << xe_dev->gt_list->gt_list[gt].gt_id);
>>>   
>>> +	/*
>>> +	 * Set graphics_ver and graphics_rel based on the main GT's GMD_ID.
>>> +	 * We should use the hardcoded value for the non-GMD_ID platforms (ip_ver_major == 0)
>>> +	 */
>>> +	xe_dev->ipver.devid = 0;
>>> +	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++) {
>>> +		if (xe_dev->gt_list->gt_list[gt].type == DRM_XE_QUERY_GT_TYPE_MAIN &&
>>> +		    xe_dev->gt_list->gt_list[gt].ip_ver_major) {
>>> +			igt_debug("Setting graphics_ver to %u and graphics_rel to %u\n",
>>> +				  xe_dev->gt_list->gt_list[gt].ip_ver_major,
>>> +				  xe_dev->gt_list->gt_list[gt].ip_ver_minor);
>>> +			xe_dev->ipver.graphics_ver = xe_dev->gt_list->gt_list[gt].ip_ver_major;
>>> +			xe_dev->ipver.graphics_rel = xe_dev->gt_list->gt_list[gt].ip_ver_minor;
>>> +			xe_dev->ipver.devid = xe_dev->dev_id;
>>> +			break;
>>> +		}
>>> +	}
>>> +
>>>   	/* Tile IDs may be non-consecutive; keep a mask of valid IDs */
>>>   	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
>>>   		xe_dev->tile_mask |= (1ull << xe_dev->gt_list->gt_list[gt].tile_id);
>>> @@ -304,6 +338,11 @@ struct xe_device *xe_device_get(int fd)
>>>   	prev = find_in_cache_unlocked(fd);
>>>   	if (!prev) {
>>>   		igt_map_insert(cache.map, &xe_dev->fd, xe_dev);
>>> +		if (xe_dev->ipver.devid) {
>>> +			pthread_mutex_lock(&xe_ipver.mutex);
>>> +			igt_map_insert(xe_ipver.map, &xe_dev->ipver.devid, &xe_dev->ipver);
>>> +			pthread_mutex_unlock(&xe_ipver.mutex);
>>> +		}
>>>   	} else {
>>>   		xe_device_free(xe_dev);
>>>   		xe_dev = prev;
>>> @@ -315,7 +354,15 @@ struct xe_device *xe_device_get(int fd)
>>>   
>>>   static void delete_in_cache(struct igt_map_entry *entry)
>>>   {
>>> -	xe_device_free((struct xe_device *)entry->data);
>>> +	struct xe_device *xe_dev = (struct xe_device *)entry->data;
>>> +
>>> +	if (xe_dev->ipver.devid) {
>>> +		pthread_mutex_lock(&xe_ipver.mutex);
>>> +		igt_map_remove(xe_ipver.map, &xe_dev->ipver.devid, NULL);
>>> +		pthread_mutex_unlock(&xe_ipver.mutex);
>>> +	}
>>> +
>>> +	xe_device_free(xe_dev);
>>>   }
>>>   
>>>   /**
>>> @@ -365,13 +412,18 @@ static void xe_device_destroy_cache(void)
>>>   	pthread_mutex_lock(&cache.cache_mutex);
>>>   	igt_map_destroy(cache.map, delete_in_cache);
>>>   	pthread_mutex_unlock(&cache.cache_mutex);
>>> +	pthread_mutex_lock(&xe_ipver.mutex);
>>> +	igt_map_destroy(xe_ipver.map, NULL);
>>> +	pthread_mutex_unlock(&xe_ipver.mutex);
>>>   }
>>>   
>>>   static void xe_device_cache_init(void)
>>>   {
>>>   	pthread_mutex_init(&cache.cache_mutex, NULL);
>>> +	pthread_mutex_init(&xe_ipver.mutex, NULL);
>>>   	xe_device_destroy_cache();
>>>   	cache.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
>>> +	xe_ipver.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
>>>   }
>>>   
>>>   #define xe_dev_FN(_NAME, _FIELD, _TYPE) \
>>> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
>>> index d7a9f95f9..19690cff3 100644
>>> --- a/lib/xe/xe_query.h
>>> +++ b/lib/xe/xe_query.h
>>> @@ -74,6 +74,9 @@ struct xe_device {
>>>   
>>>   	/** @dev_id: Device id of xe device */
>>>   	uint16_t dev_id;
>>> +
>>> +	/** @ipver: Device ip version */
>>> +	struct xe_device_ipver ipver;
>>>   };
>>>   
>>>   #define xe_for_each_engine(__fd, __hwe) \
>>> @@ -181,6 +184,7 @@ static inline void *xe_query_device(int fd, uint32_t type, uint32_t *size)
>>>   }
>>>   
>>>   struct xe_device *xe_device_get(int fd);
>>> +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid);
>>>   void xe_device_put(int fd);
>>>   
>>>   int xe_query_eu_count(int fd, int gt);
>>> -- 
>>> 2.43.0
>>>

Re: [PATCH v10 1/2] lib/xe/xe_query: Get runtime xe device graphics version from GMD_ID

[Zbigniew Kempczyński]

On Fri, Jan 16, 2026 at 01:33:58PM -0800, Matt Roper wrote:
> On Thu, Jan 15, 2026 at 09:00:53AM +0100, Zbigniew Kempczyński wrote:
> > On Mon, Jan 12, 2026 at 07:17:31PM +0000, Xin Wang wrote:
> > > This allows IGT to query the exact IP version for xe platforms.
> > > 
> > > Key changes:
> > > - Add xe_device_ipver field to xe_device structure
> > > - set the graphics versions based on the GMD_ID
> > > - Cache device ipver in global map indexed by devid for efficient lookup
> > > - Implement xe_ipver_cache_lookup() to retrieve cached ipver by devid
> > > - Clean up cached device ipver when xe_device is released
> > > 
> > > V2:
> > > - add new struct xe_device_ipver to hold the ipver info
> > > - separate cache map to eliminate collision (Roper, Matthew D)
> > > - changed function name to xe_ipver_cache_lookup() to avoid
> > >   confusion (Roper, Matthew D)
> > > 
> > > V3:
> > > - optimize the coding style. (Summers, Stuart)
> > > 
> > > Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Xin Wang <x.wang@intel.com>
> > > Reviewed-by: Ravi Kumar V <ravi.kumar.vodapalli@intel.com>
> > > ---
> > >  lib/intel_chipset.h |  6 +++++
> > >  lib/xe/xe_query.c   | 54 ++++++++++++++++++++++++++++++++++++++++++++-
> > >  lib/xe/xe_query.h   |  4 ++++
> > >  3 files changed, 63 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> > > index cc2225110..424811f7c 100644
> > > --- a/lib/intel_chipset.h
> > > +++ b/lib/intel_chipset.h
> > > @@ -100,6 +100,12 @@ struct intel_device_info {
> > >  	const char *codename;
> > >  };
> > >  
> > > +struct xe_device_ipver {
> > > +	uint32_t devid;
> > > +	uint16_t graphics_ver;
> > > +	uint16_t graphics_rel;
> > > +};
> > > +
> > >  const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
> > >  
> > >  const struct intel_cmds_info *intel_get_cmds_info(uint16_t devid) __attribute__((pure));
> > > diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> > > index 981d76948..823a29f2d 100644
> > > --- a/lib/xe/xe_query.c
> > > +++ b/lib/xe/xe_query.c
> > > @@ -210,6 +210,22 @@ static struct xe_device_cache {
> > >  	struct igt_map *map;
> > >  } cache;
> > >  
> > > +static struct xe_ipver_cache {
> > > +	pthread_mutex_t mutex;
> > > +	struct igt_map *map;
> > > +} xe_ipver;
> > > +
> > > +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid)
> > > +{
> > > +	struct xe_device_ipver *ipver;
> > > +
> > > +	pthread_mutex_lock(&xe_ipver.mutex);
> > > +	ipver = igt_map_search(xe_ipver.map, &devid);
> > > +	pthread_mutex_unlock(&xe_ipver.mutex);
> > > +
> > > +	return ipver;
> > > +}
> > > +
> > 
> > Please forgive me for sharing my thoughts only now.
> > 
> > I wondered about this a bit and according to current code shape
> > I don't like this design - especially ip_ver cache in xe_query.
> > I mean I don't like to use external cache which might or might not
> > be filled at time of calling intel_get_device_info().
> > 
> > At the moment I see following options:
> > 
> > 1. Provide update function intel_device_info_update(devid, ver, rel)
> >    allowing to update rel field during xe_device_get(). This still
> >    keeps intel_device_info.c independent but rel field might be
> >    incorrect. BTW I would set it in static definition to -1 (max
> >    unsigned) to catch it is not set/updated properly during
> >    intel_get_device_info().
> > 
> > 2. Add new function intel_get_device_info_by_fd() which will support
> >    passing fd instead devid and migrate code to use it. Most of our code
> >    uses fd to acquire device id before calling intel_get_device_info()
> >    [exception is igt_device_scan which uses pci devid directly]. This
> >    will break intel_device_info.c independency because we start calling
> >    driver functions, but maybe it is time to do this (GMD_ID).
> > 
> >    Digression: It seems when INTEL_DEVID_OVERRIDE won't work properly
> >    but I wouldn't care about it for now.
> > 
> > 3. Mix 1 and 2 but build hash map from intel_device_match[] in the
> >    constructor and update it during xe_device_get(). Pros of this
> >    is we could stop using 'static __thread' for caching last info.
> 
> The problem is that "graphics version" and "media version" are not
> supposed to be a characteristic of a general device type anymore.  An
> individual device will have some version number, but another device of
> the same "type" with the same PCI ID can can potentially have a
> different IP version.  We've been lucky enough so far to still have
> unique PCI IDs for cases where the version numbers are different (at
> least for production parts), but this is not something that we're
> supposed to be relying on since the IP disaggregation happened around
> the MTL timeframe.  Personally I think that hacks that keep treating
> versions as something associated with a device type are just making the
> problem harder to untangle.

Thanks for explaining this. I wasn't aware same PCI ID may map to
different IP versions. If I'm not wrong atm kernel also doesn't have
this addressed yet (pciidlist[] still maps PCI ID to some device
characteristics). Is it possible the opossite that same ver/rel may map
to different PCI IDs? This would complicate things even more, especially
we heavily depend on some flags set for device (has_flatccs, etc). Or
ver/rel will uniquely determine other device characteristics? If yes
may we replace PCI ID to ver/rel as a key for device info?

> 
> For a proper solution, I think we really need to separate the concept of
> "traits associated with a type of device" (which is the stuff we have in
> the device info structure which can be accurately looked up by PCI ID)
> from "IP version associated with a specific device instance" (which on
> modern platforms can only be accurately looked up in the context of a
> specific device handle such as a FD).

I'm not sure what you've written is equal to my previous comment? I mean
ver/rel is a device characteristic key?

--
Zbigniew

> 
> So aside from a few special cases, we want IGT to stop translating PCI
> IDs into version numbers and instead start translating fd's into version
> numbers.  The special case exceptions I can think of that don't really
> have a way to do fd-based lookups are: 
> 
>  * tools/tests that bypass the driver entirely (possibly running without
>    the driver loaded) and just use libpciaccess for direct BAR access.
>    Most of these either don't have version-based conditions or only have
>    version conditions matching against very old platforms (where a
>    PCIID-based lookup is "safe")
> 
>  * the old i915-era error dump decoder tool just reads its information
>    (including PCI ID) from a dump file on disk.  The tool might be
>    executed on a completely different machine from where the dump was
>    originally captured.  I don't think this tool has been updated since
>    gen8 (everyone switched over to using the Mesa tool instead), and I
>    don't think it would function at all on any of our modern platforms.
>    So if this tool is still useful at all, it would only be on ancient
>    i915 platforms where a PCIID-based lookup is "safe."
> 
> 
> The solution I suggested during an earlier review of this series was:
> 
>  * Create separate "version from PCI ID" APIs that can be used in the
>    few special cases listed above, and migrate those uses over.
> 
>  * Change the signature of intel_gen / intel_graphics_ver to take an FD
>    rather than a PCI ID; when running on Xe this would do the lookup via
>    the query ioctl to get an accurate value.
> 
>  * Update intel_gen / intel_graphics_ver:
>      - If running on i915, fall back to the device_info lookup that
>        we've always used.  That's safe for all i915 platforms except
>        MTL/ARL, and we were lucky enough that they never created any
>        production MTL/ARL platforms where a single PCI ID had different
>        possible versions, so it winds up being safe there too.
> 
>     - If running on Xe, use the query ioctl to obtain the version
>       number.  This will return the proper value for all platforms
>       officially supported by Xe (i.e., Xe2 and later).  It will return
>       0 on pre-MTL platforms (which aren't officially supported), but in
>       that case IGT can fall back to the i915 approach above.
> 
> I did a mockup of the first two parts several months ago:
> 
>   https://github.com/mattrope/intel-gpu-tools/commits/forupstream/version_query/
> 
> Since the function interface is changing, it's a lot of churn, but most
> of it can be auto-converted quickly via Coccinelle.
> 
> 
> Matt
> 
> > 
> > --
> > Zbigniew
> > 
> > >  static struct xe_device *find_in_cache_unlocked(int fd)
> > >  {
> > >  	return igt_map_search(cache.map, &fd);
> > > @@ -270,6 +286,24 @@ struct xe_device *xe_device_get(int fd)
> > >  	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
> > >  		xe_dev->gt_mask |= (1ull << xe_dev->gt_list->gt_list[gt].gt_id);
> > >  
> > > +	/*
> > > +	 * Set graphics_ver and graphics_rel based on the main GT's GMD_ID.
> > > +	 * We should use the hardcoded value for the non-GMD_ID platforms (ip_ver_major == 0)
> > > +	 */
> > > +	xe_dev->ipver.devid = 0;
> > > +	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++) {
> > > +		if (xe_dev->gt_list->gt_list[gt].type == DRM_XE_QUERY_GT_TYPE_MAIN &&
> > > +		    xe_dev->gt_list->gt_list[gt].ip_ver_major) {
> > > +			igt_debug("Setting graphics_ver to %u and graphics_rel to %u\n",
> > > +				  xe_dev->gt_list->gt_list[gt].ip_ver_major,
> > > +				  xe_dev->gt_list->gt_list[gt].ip_ver_minor);
> > > +			xe_dev->ipver.graphics_ver = xe_dev->gt_list->gt_list[gt].ip_ver_major;
> > > +			xe_dev->ipver.graphics_rel = xe_dev->gt_list->gt_list[gt].ip_ver_minor;
> > > +			xe_dev->ipver.devid = xe_dev->dev_id;
> > > +			break;
> > > +		}
> > > +	}
> > > +
> > >  	/* Tile IDs may be non-consecutive; keep a mask of valid IDs */
> > >  	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
> > >  		xe_dev->tile_mask |= (1ull << xe_dev->gt_list->gt_list[gt].tile_id);
> > > @@ -304,6 +338,11 @@ struct xe_device *xe_device_get(int fd)
> > >  	prev = find_in_cache_unlocked(fd);
> > >  	if (!prev) {
> > >  		igt_map_insert(cache.map, &xe_dev->fd, xe_dev);
> > > +		if (xe_dev->ipver.devid) {
> > > +			pthread_mutex_lock(&xe_ipver.mutex);
> > > +			igt_map_insert(xe_ipver.map, &xe_dev->ipver.devid, &xe_dev->ipver);
> > > +			pthread_mutex_unlock(&xe_ipver.mutex);
> > > +		}
> > >  	} else {
> > >  		xe_device_free(xe_dev);
> > >  		xe_dev = prev;
> > > @@ -315,7 +354,15 @@ struct xe_device *xe_device_get(int fd)
> > >  
> > >  static void delete_in_cache(struct igt_map_entry *entry)
> > >  {
> > > -	xe_device_free((struct xe_device *)entry->data);
> > > +	struct xe_device *xe_dev = (struct xe_device *)entry->data;
> > > +
> > > +	if (xe_dev->ipver.devid) {
> > > +		pthread_mutex_lock(&xe_ipver.mutex);
> > > +		igt_map_remove(xe_ipver.map, &xe_dev->ipver.devid, NULL);
> > > +		pthread_mutex_unlock(&xe_ipver.mutex);
> > > +	}
> > > +
> > > +	xe_device_free(xe_dev);
> > >  }
> > >  
> > >  /**
> > > @@ -365,13 +412,18 @@ static void xe_device_destroy_cache(void)
> > >  	pthread_mutex_lock(&cache.cache_mutex);
> > >  	igt_map_destroy(cache.map, delete_in_cache);
> > >  	pthread_mutex_unlock(&cache.cache_mutex);
> > > +	pthread_mutex_lock(&xe_ipver.mutex);
> > > +	igt_map_destroy(xe_ipver.map, NULL);
> > > +	pthread_mutex_unlock(&xe_ipver.mutex);
> > >  }
> > >  
> > >  static void xe_device_cache_init(void)
> > >  {
> > >  	pthread_mutex_init(&cache.cache_mutex, NULL);
> > > +	pthread_mutex_init(&xe_ipver.mutex, NULL);
> > >  	xe_device_destroy_cache();
> > >  	cache.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
> > > +	xe_ipver.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
> > >  }
> > >  
> > >  #define xe_dev_FN(_NAME, _FIELD, _TYPE) \
> > > diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> > > index d7a9f95f9..19690cff3 100644
> > > --- a/lib/xe/xe_query.h
> > > +++ b/lib/xe/xe_query.h
> > > @@ -74,6 +74,9 @@ struct xe_device {
> > >  
> > >  	/** @dev_id: Device id of xe device */
> > >  	uint16_t dev_id;
> > > +
> > > +	/** @ipver: Device ip version */
> > > +	struct xe_device_ipver ipver;
> > >  };
> > >  
> > >  #define xe_for_each_engine(__fd, __hwe) \
> > > @@ -181,6 +184,7 @@ static inline void *xe_query_device(int fd, uint32_t type, uint32_t *size)
> > >  }
> > >  
> > >  struct xe_device *xe_device_get(int fd);
> > > +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid);
> > >  void xe_device_put(int fd);
> > >  
> > >  int xe_query_eu_count(int fd, int gt);
> > > -- 
> > > 2.43.0
> > > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

Re: [PATCH v10 1/2] lib/xe/xe_query: Get runtime xe device graphics version from GMD_ID

[Matt Roper]

On Mon, Jan 19, 2026 at 11:36:27AM +0100, Zbigniew Kempczyński wrote:
> On Fri, Jan 16, 2026 at 01:33:58PM -0800, Matt Roper wrote:
> > On Thu, Jan 15, 2026 at 09:00:53AM +0100, Zbigniew Kempczyński wrote:
> > > On Mon, Jan 12, 2026 at 07:17:31PM +0000, Xin Wang wrote:
> > > > This allows IGT to query the exact IP version for xe platforms.
> > > > 
> > > > Key changes:
> > > > - Add xe_device_ipver field to xe_device structure
> > > > - set the graphics versions based on the GMD_ID
> > > > - Cache device ipver in global map indexed by devid for efficient lookup
> > > > - Implement xe_ipver_cache_lookup() to retrieve cached ipver by devid
> > > > - Clean up cached device ipver when xe_device is released
> > > > 
> > > > V2:
> > > > - add new struct xe_device_ipver to hold the ipver info
> > > > - separate cache map to eliminate collision (Roper, Matthew D)
> > > > - changed function name to xe_ipver_cache_lookup() to avoid
> > > >   confusion (Roper, Matthew D)
> > > > 
> > > > V3:
> > > > - optimize the coding style. (Summers, Stuart)
> > > > 
> > > > Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Signed-off-by: Xin Wang <x.wang@intel.com>
> > > > Reviewed-by: Ravi Kumar V <ravi.kumar.vodapalli@intel.com>
> > > > ---
> > > >  lib/intel_chipset.h |  6 +++++
> > > >  lib/xe/xe_query.c   | 54 ++++++++++++++++++++++++++++++++++++++++++++-
> > > >  lib/xe/xe_query.h   |  4 ++++
> > > >  3 files changed, 63 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> > > > index cc2225110..424811f7c 100644
> > > > --- a/lib/intel_chipset.h
> > > > +++ b/lib/intel_chipset.h
> > > > @@ -100,6 +100,12 @@ struct intel_device_info {
> > > >  	const char *codename;
> > > >  };
> > > >  
> > > > +struct xe_device_ipver {
> > > > +	uint32_t devid;
> > > > +	uint16_t graphics_ver;
> > > > +	uint16_t graphics_rel;
> > > > +};
> > > > +
> > > >  const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
> > > >  
> > > >  const struct intel_cmds_info *intel_get_cmds_info(uint16_t devid) __attribute__((pure));
> > > > diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> > > > index 981d76948..823a29f2d 100644
> > > > --- a/lib/xe/xe_query.c
> > > > +++ b/lib/xe/xe_query.c
> > > > @@ -210,6 +210,22 @@ static struct xe_device_cache {
> > > >  	struct igt_map *map;
> > > >  } cache;
> > > >  
> > > > +static struct xe_ipver_cache {
> > > > +	pthread_mutex_t mutex;
> > > > +	struct igt_map *map;
> > > > +} xe_ipver;
> > > > +
> > > > +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid)
> > > > +{
> > > > +	struct xe_device_ipver *ipver;
> > > > +
> > > > +	pthread_mutex_lock(&xe_ipver.mutex);
> > > > +	ipver = igt_map_search(xe_ipver.map, &devid);
> > > > +	pthread_mutex_unlock(&xe_ipver.mutex);
> > > > +
> > > > +	return ipver;
> > > > +}
> > > > +
> > > 
> > > Please forgive me for sharing my thoughts only now.
> > > 
> > > I wondered about this a bit and according to current code shape
> > > I don't like this design - especially ip_ver cache in xe_query.
> > > I mean I don't like to use external cache which might or might not
> > > be filled at time of calling intel_get_device_info().
> > > 
> > > At the moment I see following options:
> > > 
> > > 1. Provide update function intel_device_info_update(devid, ver, rel)
> > >    allowing to update rel field during xe_device_get(). This still
> > >    keeps intel_device_info.c independent but rel field might be
> > >    incorrect. BTW I would set it in static definition to -1 (max
> > >    unsigned) to catch it is not set/updated properly during
> > >    intel_get_device_info().
> > > 
> > > 2. Add new function intel_get_device_info_by_fd() which will support
> > >    passing fd instead devid and migrate code to use it. Most of our code
> > >    uses fd to acquire device id before calling intel_get_device_info()
> > >    [exception is igt_device_scan which uses pci devid directly]. This
> > >    will break intel_device_info.c independency because we start calling
> > >    driver functions, but maybe it is time to do this (GMD_ID).
> > > 
> > >    Digression: It seems when INTEL_DEVID_OVERRIDE won't work properly
> > >    but I wouldn't care about it for now.
> > > 
> > > 3. Mix 1 and 2 but build hash map from intel_device_match[] in the
> > >    constructor and update it during xe_device_get(). Pros of this
> > >    is we could stop using 'static __thread' for caching last info.
> > 
> > The problem is that "graphics version" and "media version" are not
> > supposed to be a characteristic of a general device type anymore.  An
> > individual device will have some version number, but another device of
> > the same "type" with the same PCI ID can can potentially have a
> > different IP version.  We've been lucky enough so far to still have
> > unique PCI IDs for cases where the version numbers are different (at
> > least for production parts), but this is not something that we're
> > supposed to be relying on since the IP disaggregation happened around
> > the MTL timeframe.  Personally I think that hacks that keep treating
> > versions as something associated with a device type are just making the
> > problem harder to untangle.
> 
> Thanks for explaining this. I wasn't aware same PCI ID may map to
> different IP versions. If I'm not wrong atm kernel also doesn't have
> this addressed yet (pciidlist[] still maps PCI ID to some device
> characteristics).

I think the kernel should support this all properly today.  In xe_pci.c,
we track two different sets of characteristics and look them up
independently.  PCI ID is only used to pick xe_device_desc structures
that have "platform" and "subplatform" characteristics (e.g.,
"BMG-G21").  That's roughly equivalent to the IGT device info
structures.  For modern platforms with official version numbers reported
via GMD_ID, we independently map the GMD_ID values reported by hardware
into xe_graphics_desc and xe_media_desc descriptors that provide
characteristics for the IP (e.g., "Xe2_HPG").  Anything that's tied to
the graphics/media IP itself (usually GT-level stuff) uses fields from
the graphics/media descriptors and is unaffected by what the PCI ID
indicates the platform is.  Conversely, anything tied to the
platform/SoC uses fields from the platform descriptors and is unaffected
by what the GMD_ID registers claim the IP blocks are.

If some new variant of LNL were to show up tomorrow that integrated Xe3
IP instead of Xe2 IP, the KMD should handle that properly, even if the
PCI ID was the same as one of our regular Xe2-based LNL's.

Before GMD_ID showed up in MTL/ARL, there used to truly be a fixed
association between "platform" and "graphics/media IP block."  In the
XeKMD those old platforms are handled by directly assigning the
appropriate IP descriptor to .pre_gmdid_graphics_ip and
.pre_gmdid_media_ip fields in the device descriptor.  For modern GMD_ID
platforms, those fields are left NULL so that the proper IPs are
selected according to GMD_ID value at runtime.

> Is it possible the opossite that same ver/rel may map
> to different PCI IDs? 

Yeah, this happens all the time.  There are about 13 different PCI IDs
associated with the BMG platform and subplatforms, and today all such
BMG devices are using either graphics version 20.01 or 20.02.  So a
single IP ver+rel can appear on lots of different PCI IDs. We shouldn't
assume that other IP versions won't show up in the future (possibly even
paired with some of the existing PCI IDs), but that's where things stand
today.

We've been pretty lucky so far that even though we're not supposed to
tie PCI ID directly to IP version, the products that have been created
so far have tended to keep using new PCI IDs in cases where new they
also start integrating a new IP version with a different GMD_ID.  That
isn't something they guarantee they'll continue doing, and I think there
have already been a few cases in early pre-production hardware where
we've had multiple devices with the same PCI but different GMD_IDs.

> This would complicate things even more, especially
> we heavily depend on some flags set for device (has_flatccs, etc). Or
> ver/rel will uniquely determine other device characteristics? If yes
> may we replace PCI ID to ver/rel as a key for device info?

I think IGT, like the KMD, needs to track two different sets of
characteristics:

  PCI ID:  Platform/Subplatform Information:
     - "IS_FOOLAKE" platform identity checks
     - is_discrete
     - has_lmem
     - has_flattcs
     - has_display
     - userspace workarounds listed against an SoC stepping (not sure if
       any such workarounds actually exist; these are rare even on the
       KMD side)
     - ...etc...

  GMD_ID:  IP Information (usually GT-specific);
     - GPU instructions supported (and field details)
     - behavior & field layout of userspace-accessible registers
     - userspace workarounds listed against a graphics/media release
       (using GMD_ID value match specific release(s) affected)

For the graphics/media IP items, we don't always need to set them as
fields in a descriptor structure if the code has access to the GMD_ID
value reported by the hardware since a lot of times the code can just do
a >= version check instead.

> 
> > 
> > For a proper solution, I think we really need to separate the concept of
> > "traits associated with a type of device" (which is the stuff we have in
> > the device info structure which can be accurately looked up by PCI ID)
> > from "IP version associated with a specific device instance" (which on
> > modern platforms can only be accurately looked up in the context of a
> > specific device handle such as a FD).
> 
> I'm not sure what you've written is equal to my previous comment? I mean
> ver/rel is a device characteristic key?

I was trying to distinguish type of device (e.g., "BMG") from a specific
instance of that device type (i.e., the specific BMG card I'm running
these tests on right now).  Given a PCI ID, we know the type of device
since PCI ID ranges mapped to device type.  But for device-instance
information, we need to read a register on the device itself to see the
version number that it self-reports, and then make other decisions based
on that (either by comparing the version number directly, or by using a
separate GMD_ID -> table lookup).


Matt

> 
> --
> Zbigniew
> 
> > 
> > So aside from a few special cases, we want IGT to stop translating PCI
> > IDs into version numbers and instead start translating fd's into version
> > numbers.  The special case exceptions I can think of that don't really
> > have a way to do fd-based lookups are: 
> > 
> >  * tools/tests that bypass the driver entirely (possibly running without
> >    the driver loaded) and just use libpciaccess for direct BAR access.
> >    Most of these either don't have version-based conditions or only have
> >    version conditions matching against very old platforms (where a
> >    PCIID-based lookup is "safe")
> > 
> >  * the old i915-era error dump decoder tool just reads its information
> >    (including PCI ID) from a dump file on disk.  The tool might be
> >    executed on a completely different machine from where the dump was
> >    originally captured.  I don't think this tool has been updated since
> >    gen8 (everyone switched over to using the Mesa tool instead), and I
> >    don't think it would function at all on any of our modern platforms.
> >    So if this tool is still useful at all, it would only be on ancient
> >    i915 platforms where a PCIID-based lookup is "safe."
> > 
> > 
> > The solution I suggested during an earlier review of this series was:
> > 
> >  * Create separate "version from PCI ID" APIs that can be used in the
> >    few special cases listed above, and migrate those uses over.
> > 
> >  * Change the signature of intel_gen / intel_graphics_ver to take an FD
> >    rather than a PCI ID; when running on Xe this would do the lookup via
> >    the query ioctl to get an accurate value.
> > 
> >  * Update intel_gen / intel_graphics_ver:
> >      - If running on i915, fall back to the device_info lookup that
> >        we've always used.  That's safe for all i915 platforms except
> >        MTL/ARL, and we were lucky enough that they never created any
> >        production MTL/ARL platforms where a single PCI ID had different
> >        possible versions, so it winds up being safe there too.
> > 
> >     - If running on Xe, use the query ioctl to obtain the version
> >       number.  This will return the proper value for all platforms
> >       officially supported by Xe (i.e., Xe2 and later).  It will return
> >       0 on pre-MTL platforms (which aren't officially supported), but in
> >       that case IGT can fall back to the i915 approach above.
> > 
> > I did a mockup of the first two parts several months ago:
> > 
> >   https://github.com/mattrope/intel-gpu-tools/commits/forupstream/version_query/
> > 
> > Since the function interface is changing, it's a lot of churn, but most
> > of it can be auto-converted quickly via Coccinelle.
> > 
> > 
> > Matt
> > 
> > > 
> > > --
> > > Zbigniew
> > > 
> > > >  static struct xe_device *find_in_cache_unlocked(int fd)
> > > >  {
> > > >  	return igt_map_search(cache.map, &fd);
> > > > @@ -270,6 +286,24 @@ struct xe_device *xe_device_get(int fd)
> > > >  	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
> > > >  		xe_dev->gt_mask |= (1ull << xe_dev->gt_list->gt_list[gt].gt_id);
> > > >  
> > > > +	/*
> > > > +	 * Set graphics_ver and graphics_rel based on the main GT's GMD_ID.
> > > > +	 * We should use the hardcoded value for the non-GMD_ID platforms (ip_ver_major == 0)
> > > > +	 */
> > > > +	xe_dev->ipver.devid = 0;
> > > > +	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++) {
> > > > +		if (xe_dev->gt_list->gt_list[gt].type == DRM_XE_QUERY_GT_TYPE_MAIN &&
> > > > +		    xe_dev->gt_list->gt_list[gt].ip_ver_major) {
> > > > +			igt_debug("Setting graphics_ver to %u and graphics_rel to %u\n",
> > > > +				  xe_dev->gt_list->gt_list[gt].ip_ver_major,
> > > > +				  xe_dev->gt_list->gt_list[gt].ip_ver_minor);
> > > > +			xe_dev->ipver.graphics_ver = xe_dev->gt_list->gt_list[gt].ip_ver_major;
> > > > +			xe_dev->ipver.graphics_rel = xe_dev->gt_list->gt_list[gt].ip_ver_minor;
> > > > +			xe_dev->ipver.devid = xe_dev->dev_id;
> > > > +			break;
> > > > +		}
> > > > +	}
> > > > +
> > > >  	/* Tile IDs may be non-consecutive; keep a mask of valid IDs */
> > > >  	for (int gt = 0; gt < xe_dev->gt_list->num_gt; gt++)
> > > >  		xe_dev->tile_mask |= (1ull << xe_dev->gt_list->gt_list[gt].tile_id);
> > > > @@ -304,6 +338,11 @@ struct xe_device *xe_device_get(int fd)
> > > >  	prev = find_in_cache_unlocked(fd);
> > > >  	if (!prev) {
> > > >  		igt_map_insert(cache.map, &xe_dev->fd, xe_dev);
> > > > +		if (xe_dev->ipver.devid) {
> > > > +			pthread_mutex_lock(&xe_ipver.mutex);
> > > > +			igt_map_insert(xe_ipver.map, &xe_dev->ipver.devid, &xe_dev->ipver);
> > > > +			pthread_mutex_unlock(&xe_ipver.mutex);
> > > > +		}
> > > >  	} else {
> > > >  		xe_device_free(xe_dev);
> > > >  		xe_dev = prev;
> > > > @@ -315,7 +354,15 @@ struct xe_device *xe_device_get(int fd)
> > > >  
> > > >  static void delete_in_cache(struct igt_map_entry *entry)
> > > >  {
> > > > -	xe_device_free((struct xe_device *)entry->data);
> > > > +	struct xe_device *xe_dev = (struct xe_device *)entry->data;
> > > > +
> > > > +	if (xe_dev->ipver.devid) {
> > > > +		pthread_mutex_lock(&xe_ipver.mutex);
> > > > +		igt_map_remove(xe_ipver.map, &xe_dev->ipver.devid, NULL);
> > > > +		pthread_mutex_unlock(&xe_ipver.mutex);
> > > > +	}
> > > > +
> > > > +	xe_device_free(xe_dev);
> > > >  }
> > > >  
> > > >  /**
> > > > @@ -365,13 +412,18 @@ static void xe_device_destroy_cache(void)
> > > >  	pthread_mutex_lock(&cache.cache_mutex);
> > > >  	igt_map_destroy(cache.map, delete_in_cache);
> > > >  	pthread_mutex_unlock(&cache.cache_mutex);
> > > > +	pthread_mutex_lock(&xe_ipver.mutex);
> > > > +	igt_map_destroy(xe_ipver.map, NULL);
> > > > +	pthread_mutex_unlock(&xe_ipver.mutex);
> > > >  }
> > > >  
> > > >  static void xe_device_cache_init(void)
> > > >  {
> > > >  	pthread_mutex_init(&cache.cache_mutex, NULL);
> > > > +	pthread_mutex_init(&xe_ipver.mutex, NULL);
> > > >  	xe_device_destroy_cache();
> > > >  	cache.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
> > > > +	xe_ipver.map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
> > > >  }
> > > >  
> > > >  #define xe_dev_FN(_NAME, _FIELD, _TYPE) \
> > > > diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> > > > index d7a9f95f9..19690cff3 100644
> > > > --- a/lib/xe/xe_query.h
> > > > +++ b/lib/xe/xe_query.h
> > > > @@ -74,6 +74,9 @@ struct xe_device {
> > > >  
> > > >  	/** @dev_id: Device id of xe device */
> > > >  	uint16_t dev_id;
> > > > +
> > > > +	/** @ipver: Device ip version */
> > > > +	struct xe_device_ipver ipver;
> > > >  };
> > > >  
> > > >  #define xe_for_each_engine(__fd, __hwe) \
> > > > @@ -181,6 +184,7 @@ static inline void *xe_query_device(int fd, uint32_t type, uint32_t *size)
> > > >  }
> > > >  
> > > >  struct xe_device *xe_device_get(int fd);
> > > > +struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid);
> > > >  void xe_device_put(int fd);
> > > >  
> > > >  int xe_query_eu_count(int fd, int gt);
> > > > -- 
> > > > 2.43.0
> > > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v10 2/2] lib/intel_device_info: Query runtime xe device graphics versions

[Xin Wang]

For platforms with graphics_ver >= 20, query the runtime xe device ver
instead of relying solely on hardcoded values from the PCI device table.
This enables accurate IP minor version (graphics_rel) detection for
platforms like Xe2 where different steppings have different IP versions.

Implementation details:
- Use weak symbol linkage for xe_ipver_cache_lookup() to handle static
  library compilation (libigt_chipset.a, libigt_device_scan.a) without
  xe_query.c dependencies which are used for i915 tools (i915_perf and
  intel_gpu_top)
- Provide a weak stub that returns NULL when xe_query is not linked
- For Gen20+ platforms, prefer runtime xe device versions over static data
- Fall back to PCI table if xe device info is unavailable
- Reset cache on query failure to allow retry

Remove hardcoded graphics_rel from static table entries for xe devices
as they will be populated at runtime from GMD_ID.

This unifies device info handling between i915 and xe drivers, enabling:
- Platform-specific workarounds based on accurate IP versions
- Consistent device info API across both drivers

Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Xin Wang <x.wang@intel.com>
Reviewed-by: Ravi Kumar V <ravi.kumar.vodapalli@intel.com>
---
 lib/intel_device_info.c | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 20147479a..3bc20ab68 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -3,6 +3,16 @@
 #include "i915_pciids_local.h"
 
 #include <strings.h> /* ffs() */
+#include <stddef.h>
+#include <string.h>
+
+/* Weak symbol stub - will be overridden if xe_query.c is linked */
+struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid) __attribute__((weak));
+
+struct xe_device_ipver *xe_ipver_cache_lookup(uint32_t devid)
+{
+	return NULL;
+}
 
 static const struct intel_device_info intel_generic_info = {
 	.graphics_ver = 0,
@@ -505,7 +515,6 @@ static const struct intel_device_info intel_pontevecchio_info = {
 
 static const struct intel_device_info intel_lunarlake_info = {
 	.graphics_ver = 20,
-	.graphics_rel = 4,
 	.display_ver = 20,
 	.has_4tile = true,
 	.has_flatccs = true,
@@ -517,7 +526,6 @@ static const struct intel_device_info intel_lunarlake_info = {
 
 static const struct intel_device_info intel_battlemage_info = {
 	.graphics_ver = 20,
-	.graphics_rel = 1,
 	.display_ver = 14,
 	.has_4tile = true,
 	.has_flatccs = true,
@@ -529,7 +537,6 @@ static const struct intel_device_info intel_battlemage_info = {
 
 static const struct intel_device_info intel_pantherlake_info = {
 	.graphics_ver = 30,
-	.graphics_rel = 0,
 	.display_ver = 30,
 	.has_4tile = true,
 	.has_flatccs = true,
@@ -700,6 +707,8 @@ const struct intel_device_info *intel_get_device_info(uint16_t devid)
 {
 	static __thread const struct intel_device_info *cache = &intel_generic_info;
 	static __thread uint16_t cached_devid;
+	static __thread struct intel_device_info xe_dev_info;
+	struct xe_device_ipver *ipver;
 	int i;
 
 	if (cached_devid == devid)
@@ -714,6 +723,17 @@ const struct intel_device_info *intel_get_device_info(uint16_t devid)
 	cached_devid = devid;
 	cache = (void *)intel_device_match[i].match_data;
 
+	if (cache->graphics_ver >= 20) {
+		ipver = xe_ipver_cache_lookup(devid);
+		if (ipver && ipver->devid == devid) {
+			memcpy(&xe_dev_info, cache, sizeof(struct intel_device_info));
+			xe_dev_info.graphics_ver = ipver->graphics_ver;
+			xe_dev_info.graphics_rel = ipver->graphics_rel;
+			cache = &xe_dev_info;
+		} else {
+			cached_devid = 0;
+		}
+	}
 out:
 	return cache;
 }
-- 
2.43.0

✓ Xe.CI.BAT: success for lib/intel_device_info: get the xe .graphics_rel from GMD_ID

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1491 bytes --]

== Series Details ==

Series: lib/intel_device_info: get the xe .graphics_rel from GMD_ID
URL   : https://patchwork.freedesktop.org/series/159978/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8697_BAT -> XEIGTPW_14326_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_14326_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [PASS][1] -> [FAIL][2] ([Intel XE#6520])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * IGT: IGT_8697 -> IGTPW_14326
  * Linux: xe-4368-e9383891a008f23b432b7b3c4ca2d7dd0f49824d -> xe-4370-fb2e525015f1b65b83809995601ea7827ee08ab9

  IGTPW_14326: 14326
  IGT_8697: 8697
  xe-4368-e9383891a008f23b432b7b3c4ca2d7dd0f49824d: e9383891a008f23b432b7b3c4ca2d7dd0f49824d
  xe-4370-fb2e525015f1b65b83809995601ea7827ee08ab9: fb2e525015f1b65b83809995601ea7827ee08ab9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/index.html

[-- Attachment #2: Type: text/html, Size: 2067 bytes --]

✗ i915.CI.BAT: failure for lib/intel_device_info: get the xe .graphics_rel from GMD_ID

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4226 bytes --]

== Series Details ==

Series: lib/intel_device_info: get the xe .graphics_rel from GMD_ID
URL   : https://patchwork.freedesktop.org/series/159978/
State : failure

== Summary ==

CI Bug Log - changes from IGT_8697 -> IGTPW_14326
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_14326 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_14326, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14326/index.html

Participating hosts (42 -> 40)
------------------------------

  Additional (1): fi-kbl-7567u 
  Missing    (3): bat-dg2-13 fi-snb-2520m bat-adls-6 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_14326:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_rpm@module-reload:
    - bat-dg2-9:          [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8697/bat-dg2-9/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14326/bat-dg2-9/igt@i915_pm_rpm@module-reload.html

  
Known issues
------------

  Here are the changes found in IGTPW_14326 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-7567u:       NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14326/fi-kbl-7567u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-7567u:       NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14326/fi-kbl-7567u/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8697/bat-mtlp-8/igt@i915_selftest@live.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14326/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@kms_dsc@dsc-basic:
    - fi-kbl-7567u:       NOTRUN -> [SKIP][7] +12 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14326/fi-kbl-7567u/igt@kms_dsc@dsc-basic.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-14:         [DMESG-FAIL][8] ([i915#12061]) -> [PASS][9] +1 other test pass
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8697/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14326/bat-dg2-14/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [DMESG-FAIL][10] ([i915#12061]) -> [PASS][11] +1 other test pass
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8697/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14326/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
    - bat-arls-6:         [DMESG-FAIL][12] ([i915#12061]) -> [PASS][13] +1 other test pass
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8697/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14326/bat-arls-6/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8697 -> IGTPW_14326
  * Linux: CI_DRM_17808 -> CI_DRM_17809

  CI-20190529: 20190529
  CI_DRM_17808: 630dc29de423d3640e7b2ee4a7125e0433d9eb7f @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_17809: 38e0a7138ef62d49ddc449601fc5456099ef33b2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_14326: 14326
  IGT_8697: 8697

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14326/index.html

[-- Attachment #2: Type: text/html, Size: 5228 bytes --]

✓ Xe.CI.Full: success for lib/intel_device_info: get the xe .graphics_rel from GMD_ID

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 34636 bytes --]

== Series Details ==

Series: lib/intel_device_info: get the xe .graphics_rel from GMD_ID
URL   : https://patchwork.freedesktop.org/series/159978/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8697_FULL -> XEIGTPW_14326_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_14326_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_3d@basic:
    - shard-lnl:          NOTRUN -> [SKIP][1] ([Intel XE#6011])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-2/igt@kms_3d@basic.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1:
    - shard-lnl:          [PASS][2] -> [FAIL][3] ([Intel XE#5993]) +3 other tests fail
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-2/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2370])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2328])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#610])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-7/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +5 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2314] / [Intel XE#2894]) +2 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-6/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#367])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-10/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#2887]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2887]) +17 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2652] / [Intel XE#787]) +17 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_chamelium_frames@hdmi-cmp-planes-random:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2252]) +5 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@kms_chamelium_frames@hdmi-cmp-planes-random.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2320]) +4 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_crc@cursor-random-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#1424]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-8/igt@kms_cursor_crc@cursor-random-128x42.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-bmg:          [PASS][18] -> [DMESG-WARN][19] ([Intel XE#5254])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-9/igt@kms_dp_link_training@non-uhbr-sst.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-bmg:          [PASS][20] -> [FAIL][21] ([Intel XE#4367])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-4/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-6/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2244])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-4/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#4422])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#4422]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_fbcon_fbt@psr:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#776])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-8/igt@kms_fbcon_fbt@psr.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2293] / [Intel XE#2380]) +6 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2293]) +6 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#4141]) +14 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2311]) +21 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#651])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2313]) +26 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#656]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_hdr@bpc-switch:
    - shard-bmg:          [PASS][33] -> [ABORT][34] ([Intel XE#6740]) +3 other tests abort
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-10/igt@kms_hdr@bpc-switch.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-8/igt@kms_hdr@bpc-switch.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#6901])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2925])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-10/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#5020])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2938])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-6/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [PASS][39] -> [FAIL][40] ([Intel XE#718])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-lnl-4/igt@kms_pm_dc@dc6-psr.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-1/igt@kms_pm_dc@dc6-psr.html
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2392])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#1406] / [Intel XE#1489]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#1406] / [Intel XE#2387])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-6/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@pr-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +9 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@kms_psr@pr-sprite-plane-onoff.html
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#1406])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-7/igt@kms_psr@pr-sprite-plane-onoff.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#1406] / [Intel XE#2234])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-6/igt@kms_psr@psr2-primary-render.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#3414] / [Intel XE#3904])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-10/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2413])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-10/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_sharpness_filter@filter-modifiers:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#6503]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-7/igt@kms_sharpness_filter@filter-modifiers.html

  * igt@kms_vrr@flip-basic:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#1499])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@kms_vrr@flip-basic.html

  * igt@xe_eudebug@basic-vm-bind-extended-discovery:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#4837])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-7/igt@xe_eudebug@basic-vm-bind-extended-discovery.html

  * igt@xe_eudebug@basic-vm-bind-metadata-discovery:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#4837]) +7 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html

  * igt@xe_eudebug_online@pagefault-one-of-many:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#6665])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@xe_eudebug_online@pagefault-one-of-many.html

  * igt@xe_eudebug_online@resume-one:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#4837] / [Intel XE#6665]) +2 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-4/igt@xe_eudebug_online@resume-one.html

  * igt@xe_evict@evict-large-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#688])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-3/igt@xe_evict@evict-large-multi-vm.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][57] -> [INCOMPLETE][58] ([Intel XE#6321])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-1/igt@xe_evict@evict-mixed-many-threads-small.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#2322]) +7 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind.html

  * igt@xe_exec_basic@multigpu-once-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#1392]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-8/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html

  * igt@xe_exec_multi_queue@one-queue-dyn-priority-smem:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#6874]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-3/igt@xe_exec_multi_queue@one-queue-dyn-priority-smem.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#6874]) +24 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem.html

  * igt@xe_exec_system_allocator@many-64k-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#5007])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html

  * igt@xe_exec_system_allocator@many-execqueues-mmap-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#4943]) +26 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@xe_exec_system_allocator@many-execqueues-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@process-many-execqueues-mmap-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#4943]) +2 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-5/igt@xe_exec_system_allocator@process-many-execqueues-mmap-huge-nomemset.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#586])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-10/igt@xe_mmap@small-bar.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91]) -> ([PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [SKIP][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117]) ([Intel XE#2457])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-10/igt@xe_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-1/igt@xe_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-3/igt@xe_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-6/igt@xe_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-2/igt@xe_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-7/igt@xe_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-2/igt@xe_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-8/igt@xe_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-4/igt@xe_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-8/igt@xe_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-8/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-1/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-1/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-9/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-2/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-10/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-3/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-4/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-9/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-6/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-9/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-10/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-7/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-9/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-7/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-6/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-8/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-10/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-7/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-8/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-7/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-10/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-10/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-6/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-4/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-4/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-7/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-6/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@xe_module_load@load.html

  * igt@xe_multigpu_svm@mgpu-atomic-op-basic:
    - shard-bmg:          NOTRUN -> [SKIP][118] ([Intel XE#6964]) +2 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@xe_multigpu_svm@mgpu-atomic-op-basic.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          NOTRUN -> [SKIP][119] ([Intel XE#2245])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][120] ([Intel XE#2284]) +2 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-4/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pxp@pxp-termination-key-update-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][121] ([Intel XE#4733])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@xe_pxp@pxp-termination-key-update-post-termination-irq.html

  * igt@xe_query@multigpu-query-engines:
    - shard-bmg:          NOTRUN -> [SKIP][122] ([Intel XE#944])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-10/igt@xe_query@multigpu-query-engines.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-bmg:          [PASS][123] -> [FAIL][124] ([Intel XE#6569])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-7/igt@xe_sriov_flr@flr-each-isolation.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@xe_sriov_flr@flr-each-isolation.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2:
    - shard-bmg:          [FAIL][125] -> [PASS][126] +1 other test pass
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-10/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][127] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][128] +1 other test pass
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_hdr@static-swap:
    - shard-bmg:          [ABORT][129] ([Intel XE#6740]) -> [PASS][130] +5 other tests pass
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-9/igt@kms_hdr@static-swap.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-3/igt@kms_hdr@static-swap.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-bmg:          [INCOMPLETE][131] ([Intel XE#1035]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-6/igt@kms_plane@plane-panning-bottom-right-suspend.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a:
    - shard-bmg:          [SKIP][133] -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html

  * igt@kms_pm_rpm@i2c:
    - shard-bmg:          [FAIL][135] ([Intel XE#5099]) -> [PASS][136]
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-6/igt@kms_pm_rpm@i2c.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@kms_pm_rpm@i2c.html

  * igt@xe_compute_preempt@compute-preempt-many-vram-evict@engine-drm_xe_engine_class_compute:
    - shard-bmg:          [ABORT][137] ([Intel XE#3970]) -> [PASS][138] +1 other test pass
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-10/igt@xe_compute_preempt@compute-preempt-many-vram-evict@engine-drm_xe_engine_class_compute.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-2/igt@xe_compute_preempt@compute-preempt-many-vram-evict@engine-drm_xe_engine_class_compute.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
    - shard-lnl:          [FAIL][139] ([Intel XE#6353]) -> [PASS][140]
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-lnl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html

  * igt@xe_sriov_auto_provisioning@fair-allocation@numvfs-random:
    - shard-bmg:          [FAIL][141] ([Intel XE#5937]) -> [PASS][142] +4 other tests pass
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-2/igt@xe_sriov_auto_provisioning@fair-allocation@numvfs-random.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-9/igt@xe_sriov_auto_provisioning@fair-allocation@numvfs-random.html

  
#### Warnings ####

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][143] ([Intel XE#3544]) -> [SKIP][144] ([Intel XE#3374] / [Intel XE#3544])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8697/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1035
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4367
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5099]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5099
  [Intel XE#5254]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5254
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
  [Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
  [Intel XE#6011]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6011
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6353
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8697 -> IGTPW_14326
  * Linux: xe-4368-e9383891a008f23b432b7b3c4ca2d7dd0f49824d -> xe-4370-fb2e525015f1b65b83809995601ea7827ee08ab9

  IGTPW_14326: 14326
  IGT_8697: 8697
  xe-4368-e9383891a008f23b432b7b3c4ca2d7dd0f49824d: e9383891a008f23b432b7b3c4ca2d7dd0f49824d
  xe-4370-fb2e525015f1b65b83809995601ea7827ee08ab9: fb2e525015f1b65b83809995601ea7827ee08ab9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14326/index.html

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