From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
To: Adrian Hunter <adrian.hunter@intel.com>,
Haibo Chen <haibo.chen@nxp.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>
Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
s32@nxp.com
Subject: Re: [PATCH 1/3] mmc: sdhci-esdhc-imx: disable card detect wake for S32G based platforms
Date: Thu, 11 Jul 2024 17:25:48 +0300 [thread overview]
Message-ID: <123ce7e1-1981-4a41-a131-168f4f7b5417@oss.nxp.com> (raw)
In-Reply-To: <6a577d6c-04ad-4c12-bfad-815e811deee3@intel.com>
On 7/10/2024 3:34 PM, Adrian Hunter wrote:
> On 8/07/24 15:10, Ciprian Costea wrote:
>> In case of S32G based platforms, GPIO CD used for card detect
>> wake mechanism is not available.
>>
>> For this scenario the newly introduced flag
>> 'ESDHC_FLAG_SKIP_CD_WAKE' is used.
>>
>> Signed-off-by: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Should have:
>
> - put the patch set version number (v2) in the subject e.g.
> [PATCH v2 1/3] mmc: sdhci-esdhc-imx: disable card detect wake for S32G based platforms
>
> - added Haibo Chen's Reviewed-by tag
>
> Anyway:
>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>
Hello Adrian,
Sorry for bothering you with this question, but should I send a new
patchset adding the new version or what is the process after this step ?
For example, should I send this patchset again with V3 adding all the
ACKs & Reviewed-by tags to each commit from the patchset ?
Best Regards,
Ciprian
>
>> ---
>> drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
>> index 40a6e2f8145a..21d984a77be8 100644
>> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
>> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
>> @@ -201,6 +201,9 @@
>> /* ERR004536 is not applicable for the IP */
>> #define ESDHC_FLAG_SKIP_ERR004536 BIT(17)
>>
>> +/* The IP does not have GPIO CD wake capabilities */
>> +#define ESDHC_FLAG_SKIP_CD_WAKE BIT(18)
>> +
>> enum wp_types {
>> ESDHC_WP_NONE, /* no WP, neither controller nor gpio */
>> ESDHC_WP_CONTROLLER, /* mmc controller internal WP */
>> @@ -298,7 +301,7 @@ static struct esdhc_soc_data usdhc_s32g2_data = {
>> .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
>> | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
>> | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
>> - | ESDHC_FLAG_SKIP_ERR004536,
>> + | ESDHC_FLAG_SKIP_ERR004536 | ESDHC_FLAG_SKIP_CD_WAKE,
>> };
>>
>> static struct esdhc_soc_data usdhc_imx7ulp_data = {
>> @@ -1726,7 +1729,8 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
>> host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
>>
>> /* GPIO CD can be set as a wakeup source */
>> - host->mmc->caps |= MMC_CAP_CD_WAKE;
>> + if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_CD_WAKE))
>> + host->mmc->caps |= MMC_CAP_CD_WAKE;
>>
>> if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
>> host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
>
next prev parent reply other threads:[~2024-07-11 14:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-08 12:10 [PATCH 0/3] address S32G2/S32G3 SoC based boards particularities Ciprian Costea
2024-07-08 12:10 ` [PATCH 1/3] mmc: sdhci-esdhc-imx: disable card detect wake for S32G based platforms Ciprian Costea
2024-07-10 12:34 ` Adrian Hunter
2024-07-11 14:25 ` Ciprian Marian Costea [this message]
2024-07-11 15:55 ` Ulf Hansson
2024-07-08 12:10 ` [PATCH 2/3] mmc: sdhci-esdhc-imx: obtain the 'per' clock rate after its enablement Ciprian Costea
2024-07-10 12:33 ` Adrian Hunter
2024-07-10 12:50 ` Ciprian Marian Costea
2024-07-10 13:18 ` Adrian Hunter
2024-07-08 12:10 ` [PATCH 3/3] MAINTAINERS: add 's32@nxp.com' as relevant mailing list for 'sdhci-esdhc-imx' driver Ciprian Costea
2024-07-10 13:19 ` Adrian Hunter
2024-07-12 2:34 ` Bough Chen
2024-07-12 9:09 ` [PATCH 0/3] address S32G2/S32G3 SoC based boards particularities Ulf Hansson
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