From: Frank Li <Frank.Li@nxp.com>
To: krzysztof.kozlowski@linaro.org
Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org,
devicetree@vger.kernel.org, festevam@gmail.com,
helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev,
kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org,
kw@linux.com, l.stach@pengutronix.de,
linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org,
robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org
Subject: [PATCH v4 06/15] PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
Date: Sun, 17 Dec 2023 00:12:01 -0500 [thread overview]
Message-ID: <20231217051210.754832-7-Frank.Li@nxp.com> (raw)
In-Reply-To: <20231217051210.754832-1-Frank.Li@nxp.com>
Add drvdata::mode_off and drvdata::mode_mask to simple
imx6_pcie_configure_type() logic.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Notes:
Change from v2 to v3
- none
Change from v1 to v2
- use ffs() to fixe build error.
drivers/pci/controller/dwc/pci-imx6.c | 60 ++++++++++++++++++---------
1 file changed, 40 insertions(+), 20 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 79d892836a24d..49b98593326f9 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -68,6 +68,7 @@ enum imx6_pcie_variants {
#define IMX6_PCIE_MAX_CLKS 6
+#define IMX6_PCIE_MAX_INSTANCES 2
struct imx6_pcie_drvdata {
enum imx6_pcie_variants variant;
enum dw_pcie_device_mode mode;
@@ -77,6 +78,8 @@ struct imx6_pcie_drvdata {
const char *clk_names[IMX6_PCIE_MAX_CLKS];
const u32 ltssm_off;
const u32 ltssm_mask;
+ const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
+ const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
};
struct imx6_pcie {
@@ -174,32 +177,25 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
{
- unsigned int mask, val, mode;
+ const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
+ unsigned int mask, val, mode, id;
- if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE)
+ if (drvdata->mode == DW_PCIE_EP_TYPE)
mode = PCI_EXP_TYPE_ENDPOINT;
else
mode = PCI_EXP_TYPE_ROOT_PORT;
- switch (imx6_pcie->drvdata->variant) {
- case IMX8MQ:
- case IMX8MQ_EP:
- if (imx6_pcie->controller_id == 1) {
- mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
- val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
- mode);
- } else {
- mask = IMX6Q_GPR12_DEVICE_TYPE;
- val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
- }
- break;
- default:
- mask = IMX6Q_GPR12_DEVICE_TYPE;
- val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
- break;
- }
+ id = imx6_pcie->controller_id;
+
+ /* If mode_mask[id] is zero, means each controller have its individual gpr */
+ if (!drvdata->mode_mask[id])
+ id = 0;
+
+ mask = drvdata->mode_mask[id];
+ /* FIELD_PREP mask have been constant */
+ val = mode << (ffs(mask) - 1);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
+ regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
}
static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
@@ -1376,6 +1372,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.clk_names = {IMX6_CLKS_NO_PHYDRV},
.ltssm_off = IOMUXC_GPR12,
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
+ .mode_off[0] = IOMUXC_GPR12,
+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
},
[IMX6SX] = {
.variant = IMX6SX,
@@ -1386,6 +1384,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_inbound_axi"},
.ltssm_off = IOMUXC_GPR12,
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
+ .mode_off[0] = IOMUXC_GPR12,
+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
},
[IMX6QP] = {
.variant = IMX6QP,
@@ -1397,6 +1397,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.clk_names = {IMX6_CLKS_NO_PHYDRV},
.ltssm_off = IOMUXC_GPR12,
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
+ .mode_off[0] = IOMUXC_GPR12,
+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
},
[IMX7D] = {
.variant = IMX7D,
@@ -1405,6 +1407,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
IMX6_PCIE_FLAG_HAS_PHY_RESET,
.gpr = "fsl,imx7d-iomuxc-gpr",
.clk_names = {IMX6_CLKS_NO_PHYDRV},
+ .mode_off[0] = IOMUXC_GPR12,
+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
},
[IMX8MQ] = {
.variant = IMX8MQ,
@@ -1412,6 +1416,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
IMX6_PCIE_FLAG_HAS_PHY_RESET,
.gpr = "fsl,imx8mq-iomuxc-gpr",
.clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_aux"},
+ .mode_off[0] = IOMUXC_GPR12,
+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+ .mode_off[1] = IOMUXC_GPR12,
+ .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
},
[IMX8MM] = {
.variant = IMX8MM,
@@ -1420,6 +1428,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
IMX6_PCIE_FLAG_HAS_APP_RESET,
.gpr = "fsl,imx8mm-iomuxc-gpr",
.clk_names = {IMX6_CLKS_COMMON, "pcie_aux"},
+ .mode_off[0] = IOMUXC_GPR12,
+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
},
[IMX8MP] = {
.variant = IMX8MP,
@@ -1428,6 +1438,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
IMX6_PCIE_FLAG_HAS_APP_RESET,
.gpr = "fsl,imx8mp-iomuxc-gpr",
.clk_names = {IMX6_CLKS_COMMON, "pcie_aux"},
+ .mode_off[0] = IOMUXC_GPR12,
+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
},
[IMX8MQ_EP] = {
.variant = IMX8MQ_EP,
@@ -1436,6 +1448,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mq-iomuxc-gpr",
.clk_names = {IMX6_CLKS_NO_PHYDRV, "pcie_aux"},
+ .mode_off[0] = IOMUXC_GPR12,
+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+ .mode_off[1] = IOMUXC_GPR12,
+ .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
},
[IMX8MM_EP] = {
.variant = IMX8MM_EP,
@@ -1443,6 +1459,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mm-iomuxc-gpr",
.clk_names = {IMX6_CLKS_COMMON, "pcie_aux"},
+ .mode_off[0] = IOMUXC_GPR12,
+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
},
[IMX8MP_EP] = {
.variant = IMX8MP_EP,
@@ -1450,6 +1468,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mp-iomuxc-gpr",
.clk_names = {IMX6_CLKS_COMMON, "pcie_aux"},
+ .mode_off[0] = IOMUXC_GPR12,
+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
},
};
--
2.34.1
next prev parent reply other threads:[~2023-12-17 5:13 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-17 5:11 [PATCH v4 00/15] PCI: imx6: Clean up and add imx95 pci support Frank Li
2023-12-17 5:11 ` [PATCH v4 01/15] PCI: imx6: Simplify clock handling by using bulk_clk_*() function Frank Li
2023-12-17 17:06 ` Manivannan Sadhasivam
2023-12-18 14:28 ` Frank Li
2023-12-17 5:11 ` [PATCH v4 02/15] PCI: imx6: Simplify phy handling by using by using IMX6_PCIE_FLAG_HAS_PHY Frank Li
2023-12-17 17:18 ` Manivannan Sadhasivam
2023-12-18 14:35 ` Frank Li
2023-12-17 5:11 ` [PATCH v4 03/15] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET Frank Li
2023-12-17 17:34 ` Manivannan Sadhasivam
2023-12-17 5:11 ` [PATCH v4 04/15] PCI: imx6: Using "linux,pci-domain" as slot ID Frank Li
2023-12-17 17:51 ` Manivannan Sadhasivam
2023-12-17 5:12 ` [PATCH v4 05/15] PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask Frank Li
2023-12-17 5:12 ` Frank Li [this message]
2023-12-17 5:12 ` [PATCH v4 07/15] PCI: imx6: Simplify switch-case logic by involve init_phy callback Frank Li
2023-12-17 5:12 ` [PATCH v4 08/15] dt-bindings: imx6q-pcie: Clean up irrationality clocks check Frank Li
2023-12-17 5:12 ` [PATCH v4 09/15] dt-bindings: imx6q-pcie: remove reg and reg-name Frank Li
2023-12-20 15:46 ` Rob Herring
2023-12-20 15:54 ` Rob Herring
2023-12-17 5:12 ` [PATCH v4 10/15] dt-bindings: imx6q-pcie: Add imx95 pcie compatible string Frank Li
2023-12-17 5:12 ` [PATCH v4 11/15] PCI: imx6: Add iMX95 PCIe support Frank Li
2023-12-17 5:12 ` [PATCH v4 12/15] PCI: imx6: Clean up get addr_space code Frank Li
2023-12-17 5:12 ` [PATCH v4 13/15] PCI: imx6: Add epc_features in imx6_pcie_drvdata Frank Li
2023-12-17 5:12 ` [PATCH v4 14/15] dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string Frank Li
2023-12-17 5:12 ` [PATCH v4 15/15] PCI: imx6: Add iMX95 Endpoint (EP) function support Frank Li
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