[PATCH v4 0/3] add FlexCAN support for S32G2/S32G3 SoCs

[PATCH v4 0/3] add FlexCAN support for S32G2/S32G3 SoCs

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

S32G2 and S32G3 SoCs share the FlexCAN module with i.MX SoCs, with some
hardware integration particularities.

Main difference covered by this patchset relates to interrupt management.
On S32G2/S32G3 SoC, there are separate interrupts for state change, bus
errors, MBs 0-7 and MBs 8-127 respectively.

Changes in V4:
- Updated irq description in bindings documentation
- Fixed some small issues with the proposed changes in the flexcan
  binding documentation

Changes in V3:
- Added Vincent Mailhol's Reviewed-by tag on the second patch
- Changed to 'platform_get_irq_byname' for second range of mailboxes
- Made several rephasing in bindings doc
- Removed Frank Li's Reviewed-by tags since changes were made afterwards.

Changes in V2:
- Separated 'FLEXCAN_QUIRK_NR_IRQ_3' quirk addition from S32G SoC Flexcan
  support.
- Provided more information in dt-bindings documentation with respect to
  FlexCAN module integration on S32G SoCs.
- Fixed and irq resource freeing management issue.

Ciprian Marian Costea (3):
  dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support
  can: flexcan: Add quirk to handle separate interrupt lines for
    mailboxes
  can: flexcan: add NXP S32G2/S32G3 SoC support

 .../bindings/net/can/fsl,flexcan.yaml         | 44 +++++++++++++++++--
 drivers/net/can/flexcan/flexcan-core.c        | 35 ++++++++++++++-
 drivers/net/can/flexcan/flexcan.h             |  5 +++
 3 files changed, 79 insertions(+), 5 deletions(-)

-- 
2.45.2

[PATCH v4 1/3] dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Add S32G2/S32G3 SoCs compatible strings.

A particularity for these SoCs is the presence of separate interrupts for
state change, bus errors, MBs 0-7 and MBs 8-127 respectively.

Increase maxItems of 'interrupts' to 4 for S32G based SoCs and keep the
same restriction for other SoCs.

Also, as part of this commit, move the 'allOf' after the required
properties to make the documentation easier to read.

Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
 .../bindings/net/can/fsl,flexcan.yaml         | 44 +++++++++++++++++--
 1 file changed, 40 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml b/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
index 97dd1a7c5ed2..73252fe56fe6 100644
--- a/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
+++ b/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
@@ -10,9 +10,6 @@ title:
 maintainers:
   - Marc Kleine-Budde <mkl@pengutronix.de>
 
-allOf:
-  - $ref: can-controller.yaml#
-
 properties:
   compatible:
     oneOf:
@@ -28,6 +25,7 @@ properties:
           - fsl,vf610-flexcan
           - fsl,ls1021ar2-flexcan
           - fsl,lx2160ar1-flexcan
+          - nxp,s32g2-flexcan
       - items:
           - enum:
               - fsl,imx53-flexcan
@@ -43,12 +41,21 @@ properties:
           - enum:
               - fsl,ls1028ar1-flexcan
           - const: fsl,lx2160ar1-flexcan
+      - items:
+          - enum:
+              - nxp,s32g3-flexcan
+          - const: nxp,s32g2-flexcan
 
   reg:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    maxItems: 4
+
+  interrupt-names:
+    minItems: 1
+    maxItems: 4
 
   clocks:
     maxItems: 2
@@ -136,6 +143,35 @@ required:
   - reg
   - interrupts
 
+allOf:
+  - $ref: can-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nxp,s32g2-flexcan
+    then:
+      properties:
+        interrupts:
+          items:
+            - description: Message Buffer interrupt for mailboxes 0-7 and Enhanced RX FIFO
+            - description: Device state change
+            - description: Bus Error detection
+            - description: Message Buffer interrupt for mailboxes 8-127
+        interrupt-names:
+          items:
+            - const: mb-0
+            - const: state
+            - const: berr
+            - const: mb-1
+      required:
+        - interrupt-names
+    else:
+      properties:
+        interrupts:
+          maxItems: 1
+        interrupt-names: false
+
 additionalProperties: false
 
 examples:
-- 
2.45.2

[PATCH v4 2/3] can: flexcan: Add quirk to handle separate interrupt lines for mailboxes

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Introduce 'FLEXCAN_QUIRK_SECONDARY_MB_IRQ' quirk to handle a FlexCAN
hardware module integration particularity where two ranges of mailboxes
are controlled by separate hardware interrupt lines.
The same 'flexcan_irq' handler is used for both separate mailbox interrupt
lines, with no other changes.

Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
---
 drivers/net/can/flexcan/flexcan-core.c | 24 +++++++++++++++++++++++-
 drivers/net/can/flexcan/flexcan.h      |  5 +++++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c
index ac1a860986df..3ae54305bf33 100644
--- a/drivers/net/can/flexcan/flexcan-core.c
+++ b/drivers/net/can/flexcan/flexcan-core.c
@@ -1762,14 +1762,25 @@ static int flexcan_open(struct net_device *dev)
 			goto out_free_irq_boff;
 	}
 
+	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ) {
+		err = request_irq(priv->irq_secondary_mb,
+				  flexcan_irq, IRQF_SHARED, dev->name, dev);
+		if (err)
+			goto out_free_irq_err;
+	}
+
 	flexcan_chip_interrupts_enable(dev);
 
 	netif_start_queue(dev);
 
 	return 0;
 
+ out_free_irq_err:
+	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3)
+		free_irq(priv->irq_err, dev);
  out_free_irq_boff:
-	free_irq(priv->irq_boff, dev);
+	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3)
+		free_irq(priv->irq_boff, dev);
  out_free_irq:
 	free_irq(dev->irq, dev);
  out_can_rx_offload_disable:
@@ -1799,6 +1810,9 @@ static int flexcan_close(struct net_device *dev)
 		free_irq(priv->irq_boff, dev);
 	}
 
+	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ)
+		free_irq(priv->irq_secondary_mb, dev);
+
 	free_irq(dev->irq, dev);
 	can_rx_offload_disable(&priv->offload);
 	flexcan_chip_stop_disable_on_error(dev);
@@ -2187,6 +2201,14 @@ static int flexcan_probe(struct platform_device *pdev)
 		}
 	}
 
+	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ) {
+		priv->irq_secondary_mb = platform_get_irq_byname(pdev, "mb-1");
+		if (priv->irq_secondary_mb < 0) {
+			err = priv->irq_secondary_mb;
+			goto failed_platform_get_irq;
+		}
+	}
+
 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
 		priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
 			CAN_CTRLMODE_FD_NON_ISO;
diff --git a/drivers/net/can/flexcan/flexcan.h b/drivers/net/can/flexcan/flexcan.h
index 4933d8c7439e..2cf886618c96 100644
--- a/drivers/net/can/flexcan/flexcan.h
+++ b/drivers/net/can/flexcan/flexcan.h
@@ -70,6 +70,10 @@
 #define FLEXCAN_QUIRK_SUPPORT_RX_FIFO BIT(16)
 /* Setup stop mode with ATF SCMI protocol to support wakeup */
 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI BIT(17)
+/* Device has two separate interrupt lines for two mailbox ranges, which
+ * both need to have an interrupt handler registered.
+ */
+#define FLEXCAN_QUIRK_SECONDARY_MB_IRQ	BIT(18)
 
 struct flexcan_devtype_data {
 	u32 quirks;		/* quirks needed for different IP cores */
@@ -107,6 +111,7 @@ struct flexcan_priv {
 
 	int irq_boff;
 	int irq_err;
+	int irq_secondary_mb;
 
 	/* IPC handle when setup stop mode by System Controller firmware(scfw) */
 	struct imx_sc_ipc *sc_ipc_handle;
-- 
2.45.2

[PATCH v4 3/3] can: flexcan: add NXP S32G2/S32G3 SoC support

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Add device type data for S32G2/S32G3 SoC.

FlexCAN module from S32G2/S32G3 is similar with i.MX SoCs, but interrupt
management is different.

On S32G2/S32G3 SoC, there are separate interrupts for state change, bus
errors, Mailboxes 0-7 and Mailboxes 8-127 respectively.
In order to handle this FlexCAN hardware particularity, first reuse the
'FLEXCAN_QUIRK_NR_IRQ_3' quirk provided by mcf5441x's irq handling
support. Secondly, use the newly introduced
'FLEXCAN_QUIRK_SECONDARY_MB_IRQ' quirk which handles the case where two
separate mailbox ranges are controlled by independent hardware interrupt
lines.

Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
 drivers/net/can/flexcan/flexcan-core.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c
index 3ae54305bf33..282297c55502 100644
--- a/drivers/net/can/flexcan/flexcan-core.c
+++ b/drivers/net/can/flexcan/flexcan-core.c
@@ -386,6 +386,16 @@ static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
 };
 
+static const struct flexcan_devtype_data nxp_s32g2_devtype_data = {
+	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
+		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
+		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
+		FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_NR_IRQ_3 |
+		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
+		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR |
+		FLEXCAN_QUIRK_SECONDARY_MB_IRQ,
+};
+
 static const struct can_bittiming_const flexcan_bittiming_const = {
 	.name = DRV_NAME,
 	.tseg1_min = 4,
@@ -2055,6 +2065,7 @@ static const struct of_device_id flexcan_of_match[] = {
 	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
 	{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
 	{ .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
+	{ .compatible = "nxp,s32g2-flexcan", .data = &nxp_s32g2_devtype_data, },
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, flexcan_of_match);
-- 
2.45.2

Re: [PATCH v4 3/3] can: flexcan: add NXP S32G2/S32G3 SoC support

[Marc Kleine-Budde]

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On 04.12.2024 09:49:15, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> 
> Add device type data for S32G2/S32G3 SoC.
> 
> FlexCAN module from S32G2/S32G3 is similar with i.MX SoCs, but interrupt
> management is different.
> 
> On S32G2/S32G3 SoC, there are separate interrupts for state change, bus
> errors, Mailboxes 0-7 and Mailboxes 8-127 respectively.
> In order to handle this FlexCAN hardware particularity, first reuse the
> 'FLEXCAN_QUIRK_NR_IRQ_3' quirk provided by mcf5441x's irq handling
> support. Secondly, use the newly introduced
> 'FLEXCAN_QUIRK_SECONDARY_MB_IRQ' quirk which handles the case where two
> separate mailbox ranges are controlled by independent hardware interrupt
> lines.
> 
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---

Looks good to me!

Unrelated to this patch, but I want to extend the "FLEXCAN hardware
feature flags" table in "flexcan.h". Can you provide the needed
information?

> /* FLEXCAN hardware feature flags
>  *
>  * Below is some version info we got:
>  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece-   FD Mode     MB
>  *                                Filter? connected?  Passive detection  ption in MB Supported?
>  * MCF5441X FlexCAN2  ?               no       yes        no       no        no           no     16
>  *    MX25  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
>  *    MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no           no     64
>  *    MX35  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
>  *    MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no           no     64
>  *    MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes           no     64
>  *    MX8QM FlexCAN3  03.00.23.00    yes       yes        no       no       yes          yes     64
>  *    MX8MP FlexCAN3  03.00.17.01    yes       yes        no      yes       yes          yes     64
>  *    VF610 FlexCAN3  ?               no       yes        no      yes       yes?          no     64
>  *  LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes           no     64
>  *  LX2160A FlexCAN3  03.00.23.00     no       yes        no      yes       yes          yes     64
>  *
>  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
>  */

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

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Re: [PATCH v4 3/3] can: flexcan: add NXP S32G2/S32G3 SoC support

[Ciprian Marian Costea]

On 12/4/2024 10:05 AM, Marc Kleine-Budde wrote:
> On 04.12.2024 09:49:15, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> Add device type data for S32G2/S32G3 SoC.
>>
>> FlexCAN module from S32G2/S32G3 is similar with i.MX SoCs, but interrupt
>> management is different.
>>
>> On S32G2/S32G3 SoC, there are separate interrupts for state change, bus
>> errors, Mailboxes 0-7 and Mailboxes 8-127 respectively.
>> In order to handle this FlexCAN hardware particularity, first reuse the
>> 'FLEXCAN_QUIRK_NR_IRQ_3' quirk provided by mcf5441x's irq handling
>> support. Secondly, use the newly introduced
>> 'FLEXCAN_QUIRK_SECONDARY_MB_IRQ' quirk which handles the case where two
>> separate mailbox ranges are controlled by independent hardware interrupt
>> lines.
>>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> ---
> 
> Looks good to me!
> 
> Unrelated to this patch, but I want to extend the "FLEXCAN hardware
> feature flags" table in "flexcan.h". Can you provide the needed
> information?
> 

Hello Marc,

I would say the following S32G related information could be added:

>> /* FLEXCAN hardware feature flags
>>   *
>>   * Below is some version info we got:
>>   *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece-   FD Mode     MB
>>   *                                Filter? connected?  Passive detection  ption in MB Supported?
>>   * MCF5441X FlexCAN2  ?               no       yes        no       no        no           no     16
>>   *    MX25  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
>>   *    MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no           no     64
>>   *    MX35  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
>>   *    MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no           no     64
>>   *    MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes           no     64
>>   *    MX8QM FlexCAN3  03.00.23.00    yes       yes        no       no       yes          yes     64
>>   *    MX8MP FlexCAN3  03.00.17.01    yes       yes        no      yes       yes          yes     64
>>   *    VF610 FlexCAN3  ?               no       yes        no      yes       yes?          no     64
>>   *  LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes           no     64
>>   *  LX2160A FlexCAN3  03.00.23.00     no       yes        no      yes       yes          yes     64
      *  S32G2/S32G3 FlexCAN3  03.00.39.00     no       yes        no 
   yes       yes          yes     128
>>   *
>>   * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
>>   */
> 
> regards,
> Marc
> 

Would you like me to send another version of this patchset with above 
information included ?

Best Regards,
Ciprian

Re: [PATCH v4 3/3] can: flexcan: add NXP S32G2/S32G3 SoC support

[Marc Kleine-Budde]

[-- Attachment #1: Type: text/plain, Size: 2561 bytes --]

On 04.12.2024 13:38:51, Ciprian Marian Costea wrote:
> > Unrelated to this patch, but I want to extend the "FLEXCAN hardware
> > feature flags" table in "flexcan.h". Can you provide the needed
> > information?
> > 
> 
> I would say the following S32G related information could be added:
> 
> > > /* FLEXCAN hardware feature flags
> > >   *
> > >   * Below is some version info we got:
> > >   *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece-   FD Mode     MB
> > >   *                                Filter? connected?  Passive detection  ption in MB Supported?
> > >   * MCF5441X FlexCAN2  ?               no       yes        no       no        no           no     16
> > >   *    MX25  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
> > >   *    MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no           no     64
> > >   *    MX35  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
> > >   *    MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no           no     64
> > >   *    MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes           no     64
> > >   *    MX8QM FlexCAN3  03.00.23.00    yes       yes        no       no       yes          yes     64
> > >   *    MX8MP FlexCAN3  03.00.17.01    yes       yes        no      yes       yes          yes     64
> > >   *    VF610 FlexCAN3  ?               no       yes        no      yes       yes?          no     64
> > >   *  LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes           no     64
> > >   *  LX2160A FlexCAN3  03.00.23.00     no       yes        no      yes       yes          yes     64
>       *  S32G2/S32G3 FlexCAN3 03.00.39.00  no       yes        no      yes       yes          yes    128
> > >   *
> > >   * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
> > >   */
> 
> Would you like me to send another version of this patchset with above
> information included ?

No. Once we have Krzysztof's ACK for the DT binding changes, I'll take
this series.

I think we'll make that a separate patch and maybe add more information.

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

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Re: [PATCH v4 1/3] dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support

[Conor Dooley]

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On Wed, Dec 04, 2024 at 09:49:13AM +0200, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> 
> Add S32G2/S32G3 SoCs compatible strings.
> 
> A particularity for these SoCs is the presence of separate interrupts for
> state change, bus errors, MBs 0-7 and MBs 8-127 respectively.
> 
> Increase maxItems of 'interrupts' to 4 for S32G based SoCs and keep the
> same restriction for other SoCs.
> 
> Also, as part of this commit, move the 'allOf' after the required
> properties to make the documentation easier to read.
> 
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH v4 3/3] can: flexcan: add NXP S32G2/S32G3 SoC support

[Ciprian Marian Costea]

On 12/4/2024 1:48 PM, Marc Kleine-Budde wrote:
> On 04.12.2024 13:38:51, Ciprian Marian Costea wrote:
>>> Unrelated to this patch, but I want to extend the "FLEXCAN hardware
>>> feature flags" table in "flexcan.h". Can you provide the needed
>>> information?
>>>
>>
>> I would say the following S32G related information could be added:
>>
>>>> /* FLEXCAN hardware feature flags
>>>>    *
>>>>    * Below is some version info we got:
>>>>    *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece-   FD Mode     MB
>>>>    *                                Filter? connected?  Passive detection  ption in MB Supported?
>>>>    * MCF5441X FlexCAN2  ?               no       yes        no       no        no           no     16
>>>>    *    MX25  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
>>>>    *    MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no           no     64
>>>>    *    MX35  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
>>>>    *    MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no           no     64
>>>>    *    MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes           no     64
>>>>    *    MX8QM FlexCAN3  03.00.23.00    yes       yes        no       no       yes          yes     64
>>>>    *    MX8MP FlexCAN3  03.00.17.01    yes       yes        no      yes       yes          yes     64
>>>>    *    VF610 FlexCAN3  ?               no       yes        no      yes       yes?          no     64
>>>>    *  LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes           no     64
>>>>    *  LX2160A FlexCAN3  03.00.23.00     no       yes        no      yes       yes          yes     64
>>        *  S32G2/S32G3 FlexCAN3 03.00.39.00  no       yes        no      yes       yes          yes    128
>>>>    *
>>>>    * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
>>>>    */
>>
>> Would you like me to send another version of this patchset with above
>> information included ?
> 
> No. Once we have Krzysztof's ACK for the DT binding changes, I'll take
> this series.
> 
> I think we'll make that a separate patch and maybe add more information.
> 
> regards,
> Marc
> 

Hello Krzysztof,

I've addressed your feedback from the previous version of this patchset.

Is the current version ok from your point of view with respect to DT 
bindings changes?

Regards,
Ciprian

Re: [PATCH v4 1/3] dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support

[Marc Kleine-Budde]

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Hello Krzysztof,

can you (and you bot) take a look at this patch?

Thanks,
Marc

On 04.12.2024 09:49:13, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> 
> Add S32G2/S32G3 SoCs compatible strings.
> 
> A particularity for these SoCs is the presence of separate interrupts for
> state change, bus errors, MBs 0-7 and MBs 8-127 respectively.
> 
> Increase maxItems of 'interrupts' to 4 for S32G based SoCs and keep the
> same restriction for other SoCs.
> 
> Also, as part of this commit, move the 'allOf' after the required
> properties to make the documentation easier to read.
> 
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---
>  .../bindings/net/can/fsl,flexcan.yaml         | 44 +++++++++++++++++--
>  1 file changed, 40 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml b/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
> index 97dd1a7c5ed2..73252fe56fe6 100644
> --- a/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
> +++ b/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
> @@ -10,9 +10,6 @@ title:
>  maintainers:
>    - Marc Kleine-Budde <mkl@pengutronix.de>
>  
> -allOf:
> -  - $ref: can-controller.yaml#
> -
>  properties:
>    compatible:
>      oneOf:
> @@ -28,6 +25,7 @@ properties:
>            - fsl,vf610-flexcan
>            - fsl,ls1021ar2-flexcan
>            - fsl,lx2160ar1-flexcan
> +          - nxp,s32g2-flexcan
>        - items:
>            - enum:
>                - fsl,imx53-flexcan
> @@ -43,12 +41,21 @@ properties:
>            - enum:
>                - fsl,ls1028ar1-flexcan
>            - const: fsl,lx2160ar1-flexcan
> +      - items:
> +          - enum:
> +              - nxp,s32g3-flexcan
> +          - const: nxp,s32g2-flexcan
>  
>    reg:
>      maxItems: 1
>  
>    interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 4
> +
> +  interrupt-names:
> +    minItems: 1
> +    maxItems: 4
>  
>    clocks:
>      maxItems: 2
> @@ -136,6 +143,35 @@ required:
>    - reg
>    - interrupts
>  
> +allOf:
> +  - $ref: can-controller.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: nxp,s32g2-flexcan
> +    then:
> +      properties:
> +        interrupts:
> +          items:
> +            - description: Message Buffer interrupt for mailboxes 0-7 and Enhanced RX FIFO
> +            - description: Device state change
> +            - description: Bus Error detection
> +            - description: Message Buffer interrupt for mailboxes 8-127
> +        interrupt-names:
> +          items:
> +            - const: mb-0
> +            - const: state
> +            - const: berr
> +            - const: mb-1
> +      required:
> +        - interrupt-names
> +    else:
> +      properties:
> +        interrupts:
> +          maxItems: 1
> +        interrupt-names: false
> +
>  additionalProperties: false
>  
>  examples:
> -- 
> 2.45.2
> 
> 
> 

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

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