[PATCH v2 0/4] few small change for flexspi setting in dts file

[PATCH v2 0/4] few small change for flexspi setting in dts file

[Haibo Chen]

PATCH1 adjust the compatible string to align with yaml
PATCH2/3/4 limit the nor max frequency accroding to data sheet

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
Changes in v2:
- PATCH1: small change of the commit log according to Fabio's comment
- PATCH2~4: fix type and split into 3 patches and add fix tag accordingly.
- Link to v1: https://lore.kernel.org/r/20250916-flexspi-dts-v1-0-61567f969165@nxp.com

---
Haibo Chen (4):
      arm64: dts: correct the flexspi compatible string to match with yaml
      arm64: dts: imx8mn-evk: limit the max frequency of spi nor chip
      arm64: dts: imx8mm-evk: limit the max frequency of spi nor chip
      arm64: dts: imx8mp-evk: limit the max frequency of spi nor chip

 arch/arm64/boot/dts/freescale/imx8mm-evk.dts       | 2 +-
 arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi      | 2 +-
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts       | 2 +-
 arch/arm64/boot/dts/freescale/imx91_93_common.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/imx95.dtsi           | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)
---
base-commit: c3067c2c38316c3ef013636c93daa285ee6aaa2e
change-id: 20250916-flexspi-dts-24af8b6bf468

Best regards,
-- 
Haibo Chen <haibo.chen@nxp.com>

[PATCH v2 1/4] arm64: dts: correct the flexspi compatible string to match with yaml

[Haibo Chen]

According to Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml,
imx93/imx95 should use it's own compatible string and fallback
compatible with imx8mm.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx91_93_common.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/imx95.dtsi           | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
index 52da571f26c4e8a2703e4476b5541fa7aca52f10..7958cef353766a430df5e626ff2403dc05a974b1 100644
--- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
@@ -706,7 +706,7 @@ flexcan2: can@425b0000 {
 			};
 
 			flexspi1: spi@425e0000 {
-				compatible = "nxp,imx8mm-fspi";
+				compatible = "nxp,imx93-fspi", "nxp,imx8mm-fspi";
 				reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
 				reg-names = "fspi_base", "fspi_mmap";
 				#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 1292677cbe4eb8c5f3ec2874a17ad6efd0111192..a0ff7002be9fa0529ba5712df4c056c56f0e3242 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -945,7 +945,7 @@ flexcan3: can@42600000 {
 			};
 
 			flexspi1: spi@425e0000 {
-				compatible = "nxp,imx8mm-fspi";
+				compatible = "nxp,imx95-fspi", "nxp,imx8mm-fspi";
 				reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>;
 				reg-names = "fspi_base", "fspi_mmap";
 				#address-cells = <1>;

-- 
2.34.1

Re: [PATCH v2 1/4] arm64: dts: correct the flexspi compatible string to match with yaml

[Frank Li]

On Wed, Sep 17, 2025 at 04:42:27PM +0800, Haibo Chen wrote:
> According to Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml,
> imx93/imx95 should use it's own compatible string and fallback
> compatible with imx8mm.
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  arch/arm64/boot/dts/freescale/imx91_93_common.dtsi | 2 +-
>  arch/arm64/boot/dts/freescale/imx95.dtsi           | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
> index 52da571f26c4e8a2703e4476b5541fa7aca52f10..7958cef353766a430df5e626ff2403dc05a974b1 100644
> --- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
> @@ -706,7 +706,7 @@ flexcan2: can@425b0000 {
>  			};
>
>  			flexspi1: spi@425e0000 {
> -				compatible = "nxp,imx8mm-fspi";
> +				compatible = "nxp,imx93-fspi", "nxp,imx8mm-fspi";
>  				reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
>  				reg-names = "fspi_base", "fspi_mmap";
>  				#address-cells = <1>;
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 1292677cbe4eb8c5f3ec2874a17ad6efd0111192..a0ff7002be9fa0529ba5712df4c056c56f0e3242 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -945,7 +945,7 @@ flexcan3: can@42600000 {
>  			};
>
>  			flexspi1: spi@425e0000 {
> -				compatible = "nxp,imx8mm-fspi";
> +				compatible = "nxp,imx95-fspi", "nxp,imx8mm-fspi";
>  				reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>;
>  				reg-names = "fspi_base", "fspi_mmap";
>  				#address-cells = <1>;
>
> --
> 2.34.1
>

[PATCH v2 2/4] arm64: dts: imx8mn-evk: limit the max frequency of spi nor chip

[Haibo Chen]

The spi nor on imx8mn evk board works under SDR mode, and
driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
According to the datasheet, there is IO limitation on this chip,
the max frequency of such case is 66MHz, so add the limitation
here to align with datasheet.

Refer to 3.9.9 FlexSPI timing parameters on page 65.
https://www.nxp.com/docs/en/data-sheet/IMX8MNCEC.pdf

Fixes: 579df4288896 ("arm64: dts: imx8mn-evk: add QSPI flash")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 145355ff91b454795478b504eb403b0590848d46..fa43238e7b917a5b5f0bd9af96bd900f6dbacb8d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -199,7 +199,7 @@ flash0: flash@0 {
 		reg = <0>;
 		#address-cells = <1>;
 		#size-cells = <1>;
-		spi-max-frequency = <166000000>;
+		spi-max-frequency = <66000000>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 	};

-- 
2.34.1

Re: [PATCH v2 2/4] arm64: dts: imx8mn-evk: limit the max frequency of spi nor chip

[Frank Li]

On Wed, Sep 17, 2025 at 04:42:28PM +0800, Haibo Chen wrote:
> The spi nor on imx8mn evk board works under SDR mode, and
> driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
> According to the datasheet, there is IO limitation on this chip,

'chip' means spi-nor flash or imx8mn SoC? Looks like it is 8mn according
to below refers. can you change 'chip' to i.MX8MN

> the max frequency of such case is 66MHz, so add the limitation
> here to align with datasheet.
>
> Refer to 3.9.9 FlexSPI timing parameters on page 65.
> https://www.nxp.com/docs/en/data-sheet/IMX8MNCEC.pdf
>
> Fixes: 579df4288896 ("arm64: dts: imx8mn-evk: add QSPI flash")
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> index 145355ff91b454795478b504eb403b0590848d46..fa43238e7b917a5b5f0bd9af96bd900f6dbacb8d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> @@ -199,7 +199,7 @@ flash0: flash@0 {
>  		reg = <0>;
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> -		spi-max-frequency = <166000000>;
> +		spi-max-frequency = <66000000>;

Looks like flash's limiation, any common property in spi controller to limit
frequency?

Frank
>  		spi-tx-bus-width = <4>;
>  		spi-rx-bus-width = <4>;
>  	};
>
> --
> 2.34.1
>

[PATCH v2 3/4] arm64: dts: imx8mm-evk: limit the max frequency of spi nor chip

[Haibo Chen]

The spi nor on imx8mm evk board works under SDR mode, and
driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
According to the datasheet, there is IO limitation on this chip,
the max frequency of such case is 66MHz, so add the limitation
here to align with datasheet.

Refer to 3.9.10 FlexSPI timing parameters on page 59.
https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf

Fixes: fa1652340af8 ("arm64: dts: imx8mm-evk: Add flexspi support")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index b68954bcc383cfc799877ff64c5d9a59dd863907..bb57c1db7c64adb20c996bbc2e3996e1fde5b98a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -47,7 +47,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
-		spi-max-frequency = <80000000>;
+		spi-max-frequency = <66000000>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
 	};

-- 
2.34.1

Re: [PATCH v2 3/4] arm64: dts: imx8mm-evk: limit the max frequency of spi nor chip

[Peng Fan]

On Wed, Sep 17, 2025 at 04:42:29PM +0800, Haibo Chen wrote:
>The spi nor on imx8mm evk board works under SDR mode, and
>driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
>According to the datasheet, there is IO limitation on this chip,
>the max frequency of such case is 66MHz, so add the limitation
>here to align with datasheet.
>
>Refer to 3.9.10 FlexSPI timing parameters on page 59.
>https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf

The SoC SDR mode max supports 66MHz, 133MHz. DDR mode max supports 33MHz and
66MHz. Saying the driver now only use RXCLKSRC 0 to restrict the
device tree to 66MHz is not that correct.

The SoC max frequency could be coded in driver per my understanding.

For the QSPI-NOR chip, the spi-max-frequency should represent the NOR chip
frequency. But that chip supports SDR/DDR, so a new property
spi-ddr-max-frequency, if we take spi-max-frequency as the max NOR
CHIP SDR mode frequency?

So if spi-max-frequency is the maximum NOR chip SDR frequency, the driver
should also be update dthat DDR mode is not supported as of now.

Just my thoughts.

Regards
Peng.

Re: [PATCH v2 3/4] arm64: dts: imx8mm-evk: limit the max frequency of spi nor chip

[Michael Walle]

[-- Attachment #1: Type: text/plain, Size: 1585 bytes --]

Hi,

On Thu Sep 18, 2025 at 11:01 AM CEST, Peng Fan wrote:
> On Wed, Sep 17, 2025 at 04:42:29PM +0800, Haibo Chen wrote:
> >The spi nor on imx8mm evk board works under SDR mode, and
> >driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
> >According to the datasheet, there is IO limitation on this chip,
> >the max frequency of such case is 66MHz, so add the limitation
> >here to align with datasheet.
> >
> >Refer to 3.9.10 FlexSPI timing parameters on page 59.
> >https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf
>
> The SoC SDR mode max supports 66MHz, 133MHz. DDR mode max supports 33MHz and
> 66MHz. Saying the driver now only use RXCLKSRC 0 to restrict the
> device tree to 66MHz is not that correct.
>
> The SoC max frequency could be coded in driver per my understanding.

Yes that is correct. The spi-max-frequency property is for the
device, not the capabilities of the controller. I.e. the flash chip
on the board.

> For the QSPI-NOR chip, the spi-max-frequency should represent the NOR chip
> frequency. But that chip supports SDR/DDR, so a new property
> spi-ddr-max-frequency, if we take spi-max-frequency as the max NOR
> CHIP SDR mode frequency?

Which chip is it? I'm not sure that this is required because the
supported modes might be in the SFDP data and we just support the
8d8d8d mode backed by the JEDEC standard.

-michael

> So if spi-max-frequency is the maximum NOR chip SDR frequency, the driver
> should also be update dthat DDR mode is not supported as of now.
>
> Just my thoughts.
>
> Regards
> Peng.


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Re: [PATCH v2 3/4] arm64: dts: imx8mm-evk: limit the max frequency of spi nor chip

[Peng Fan]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=unknown-8bit, Size: 2044 bytes --]

On Fri, Sep 19, 2025 at 09:29:41AM +0200, Michael Walle wrote:
>Hi,
>
>On Thu Sep 18, 2025 at 11:01 AM CEST, Peng Fan wrote:
>> On Wed, Sep 17, 2025 at 04:42:29PM +0800, Haibo Chen wrote:
>> >The spi nor on imx8mm evk board works under SDR mode, and
>> >driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
>> >According to the datasheet, there is IO limitation on this chip,
>> >the max frequency of such case is 66MHz, so add the limitation
>> >here to align with datasheet.
>> >
>> >Refer to 3.9.10 FlexSPI timing parameters on page 59.
>> >https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf
>>
>> The SoC SDR mode max supports 66MHz, 133MHz. DDR mode max supports 33MHz and
>> 66MHz. Saying the driver now only use RXCLKSRC 0 to restrict the
>> device tree to 66MHz is not that correct.
>>
>> The SoC max frequency could be coded in driver per my understanding.
>
>Yes that is correct. The spi-max-frequency property is for the
>device, not the capabilities of the controller. I.e. the flash chip
>on the board.
>
>> For the QSPI-NOR chip, the spi-max-frequency should represent the NOR chip
>> frequency. But that chip supports SDR/DDR, so a new property
>> spi-ddr-max-frequency, if we take spi-max-frequency as the max NOR
>> CHIP SDR mode frequency?
>
>Which chip is it? I'm not sure that this is required because the
>supported modes might be in the SFDP data and we just support the
>8d8d8d mode backed by the JEDEC standard.

MT25QU256ABA
Clock frequency
– 166 MHz (MAX) for all protocols in STR
– 90 MHz (MAX) for all protocols in DTR

Current spi-max-frequency does not indicate it is STR or DDR.

If device tree has spi-max-frequency as 166MHz, but driver configures
the working mode as DDR, there might be issues. I not look into details
on SFDP or 8d8d8d8d, so my understandings might be wrong.

Thanks,
Peng

>
>-michael
>
>> So if spi-max-frequency is the maximum NOR chip SDR frequency, the driver
>> should also be update dthat DDR mode is not supported as of now.
>>
>> Just my thoughts.
>>
>> Regards
>> Peng.
>

RE: [PATCH v2 3/4] arm64: dts: imx8mm-evk: limit the max frequency of spi nor chip

[Bough Chen]

> -----Original Message-----
> From: Peng Fan (OSS) <peng.fan@oss.nxp.com>
> Sent: 2025年9月19日 17:31
> To: Michael Walle <michael@walle.cc>
> Cc: Bough Chen <haibo.chen@nxp.com>; Rob Herring <robh@kernel.org>;
> Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
> <conor+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Sascha Hauer
> <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan
> <peng.fan@nxp.com>; Frank Li <frank.li@nxp.com>; Marco Felsch
> <m.felsch@pengutronix.de>; Han Xu <han.xu@nxp.com>;
> devicetree@vger.kernel.org; imx@lists.linux.dev;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 3/4] arm64: dts: imx8mm-evk: limit the max frequency of
> spi nor chip
> 
> On Fri, Sep 19, 2025 at 09:29:41AM +0200, Michael Walle wrote:
> >Hi,
> >
> >On Thu Sep 18, 2025 at 11:01 AM CEST, Peng Fan wrote:
> >> On Wed, Sep 17, 2025 at 04:42:29PM +0800, Haibo Chen wrote:
> >> >The spi nor on imx8mm evk board works under SDR mode, and driver use
> >> >FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
> >> >According to the datasheet, there is IO limitation on this chip, the
> >> >max frequency of such case is 66MHz, so add the limitation here to
> >> >align with datasheet.
> >> >
> >> >Refer to 3.9.10 FlexSPI timing parameters on page 59.
> >> >https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf
> >>
> >> The SoC SDR mode max supports 66MHz, 133MHz. DDR mode max supports
> >> 33MHz and 66MHz. Saying the driver now only use RXCLKSRC 0 to
> >> restrict the device tree to 66MHz is not that correct.
> >>
> >> The SoC max frequency could be coded in driver per my understanding.
> >
> >Yes that is correct. The spi-max-frequency property is for the device,
> >not the capabilities of the controller. I.e. the flash chip on the
> >board.

Okay, I will add the rate limitation in host driver.

> >
> >> For the QSPI-NOR chip, the spi-max-frequency should represent the NOR
> >> chip frequency. But that chip supports SDR/DDR, so a new property
> >> spi-ddr-max-frequency, if we take spi-max-frequency as the max NOR
> >> CHIP SDR mode frequency?
> >
> >Which chip is it? I'm not sure that this is required because the
> >supported modes might be in the SFDP data and we just support the
> >8d8d8d mode backed by the JEDEC standard.
> 
> MT25QU256ABA
> Clock frequency
> – 166 MHz (MAX) for all protocols in STR – 90 MHz (MAX) for all protocols in
> DTR
> 
> Current spi-max-frequency does not indicate it is STR or DDR.
> 
> If device tree has spi-max-frequency as 166MHz, but driver configures the
> working mode as DDR, there might be issues. I not look into details on SFDP or
> 8d8d8d8d, so my understandings might be wrong.

Micron MT35x has more complicate limitation:
• Clock frequency:
– 166 MHz (MAX) in SDR (166 MB/s) (1.8V)
– 200 MHz (MAX) in DDR (400 MB/s) with DQS (1.8V)
– 133 MHz (MAX) in SDR (133 MB/s) (3.0V)
– 133 MHz (MAX) in DDR (266MB/s) with DQS (3.0V)

Seems need add this rate limitation in spi-nor driver for different chips.

Regards
Haibo Chen
> 
> Thanks,
> Peng
> 
> >
> >-michael
> >
> >> So if spi-max-frequency is the maximum NOR chip SDR frequency, the
> >> driver should also be update dthat DDR mode is not supported as of now.
> >>
> >> Just my thoughts.
> >>
> >> Regards
> >> Peng.
> >
> 

[PATCH v2 4/4] arm64: dts: imx8mp-evk: limit the max frequency of spi nor chip

[Haibo Chen]

The spi nor on imx8mp evk board works under SDR mode, and
driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
According to the datasheet, there is IO limitation on this chip,
the max frequency of such case is 66MHz, so add the limitation here
to align with datasheet.

Refer to 3.8.12 FlexSPI timing parameters on page 72.
https://www.nxp.com/webapp/sps/download/preDownload.jsp?render=true

Fixes: 7a2f7d763d94 ("arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 3730792daf5010213cbb9f6869a8110ea28eb48a..0b47d72cae9900ad53eed04c810a9ea8af795446 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -272,7 +272,7 @@ &flexspi {
 	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <80000000>;
+		spi-max-frequency = <66000000>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
 	};

-- 
2.34.1