[PATCH v1] arm: dts: imx: Add watchdog support for early boot stages

[PATCH v1] arm: dts: imx: Add watchdog support for early boot stages

[alice.guo]

From: Alice Guo <alice.guo@nxp.com>

Add bootph-all property to watchdog nodes to enable them in U-Boot's
early boot phases. This allows U-Boot to utilize these watchdogs for
system monitoring and reset functionality during boot.

The bootph-all property ensures these watchdog devices are available
across all U-Boot boot phases (TPL, SPL, and U-Boot proper).

Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
 arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi             | 11 +++++++++++
 arch/arm64/boot/dts/freescale/imx8ulp.dtsi         |  1 +
 arch/arm64/boot/dts/freescale/imx91_93_common.dtsi |  3 +++
 arch/arm64/boot/dts/freescale/imx94.dtsi           | 12 ++++++++++++
 arch/arm64/boot/dts/freescale/imx95.dtsi           | 11 +++++++++++
 arch/arm64/boot/dts/freescale/imx952.dtsi          | 11 +++++++++++
 6 files changed, 49 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
index 1355feda1aa7..c29a767df925 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
@@ -325,6 +325,17 @@ smc1: clock-controller@40410000 {
 			clock-names = "divcore", "hsrun_divcore";
 		};
 
+		wdog2: watchdog@40430000 {
+			compatible = "fsl,imx7ulp-wdt";
+			reg = <0x40430000 0x10000>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
+			timeout-sec = <40>;
+			status = "disabled";
+		};
+
 		pcc3: clock-controller@40b30000 {
 			compatible = "fsl,imx7ulp-pcc3";
 			reg = <0x40b30000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 1de3ad60c6aa..df06f03624d6 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -302,6 +302,7 @@ wdog3: watchdog@292a0000 {
 				assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
 				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
 				timeout-sec = <40>;
+				bootph-all;
 			};
 
 			cgc1: clock-controller@292c0000 {
diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
index 46a5d2df074d..a1a7e6a0571b 100644
--- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
@@ -525,6 +525,7 @@ wdog3: watchdog@42490000 {
 				clocks = <&clk IMX93_CLK_WDOG3_GATE>;
 				timeout-sec = <40>;
 				status = "disabled";
+				bootph-all;
 			};
 
 			wdog4: watchdog@424a0000 {
@@ -534,6 +535,7 @@ wdog4: watchdog@424a0000 {
 				clocks = <&clk IMX93_CLK_WDOG4_GATE>;
 				timeout-sec = <40>;
 				status = "disabled";
+				bootph-all;
 			};
 
 			wdog5: watchdog@424b0000 {
@@ -543,6 +545,7 @@ wdog5: watchdog@424b0000 {
 				clocks = <&clk IMX93_CLK_WDOG5_GATE>;
 				timeout-sec = <40>;
 				status = "disabled";
+				bootph-all;
 			};
 
 			tpm3: pwm@424e0000 {
diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index c460ece6070f..9420519b5be1 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -1283,6 +1283,18 @@ wdog3: watchdog@49220000 {
 				timeout-sec = <40>;
 				fsl,ext-reset-output;
 				status = "disabled";
+				bootph-all;
+			};
+
+			wdog4: watchdog@49230000 {
+				compatible = "fsl,imx94-wdt", "fsl,imx93-wdt";
+				reg = <0x49230000 0x10000>;
+				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>;
+				timeout-sec = <40>;
+				fsl,ext-reset-output;
+				status = "disabled";
+				bootph-all;
 			};
 		};
 
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 71394871d8dd..7caacdc819c4 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -795,6 +795,17 @@ wdog3: watchdog@42490000 {
 				clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
 				timeout-sec = <40>;
 				status = "disabled";
+				bootph-all;
+			};
+
+			wdog4: watchdog@424a0000 {
+				compatible = "fsl,imx93-wdt";
+				reg = <0x424a0000 0x10000>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+				timeout-sec = <40>;
+				status = "disabled";
+				bootph-all;
 			};
 
 			tpm3: pwm@424e0000 {
diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi
index b30707837f35..59f829004000 100644
--- a/arch/arm64/boot/dts/freescale/imx952.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx952.dtsi
@@ -349,6 +349,17 @@ wdog3: watchdog@420b0000 {
 				clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
 				timeout-sec = <40>;
 				status = "disabled";
+				bootph-all;
+			};
+
+			wdog4: watchdog@420c0000 {
+				compatible = "fsl,imx93-wdt";
+				reg = <0x420c0000 0x10000>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+				timeout-sec = <40>;
+				status = "disabled";
+				bootph-all;
 			};
 
 			tpm3: pwm@42100000 {
-- 
2.34.1

Re: [PATCH v1] arm: dts: imx: Add watchdog support for early boot stages

[Fabio Estevam]

On Mon, May 11, 2026 at 11:46 PM <alice.guo@oss.nxp.com> wrote:

> --- a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
> @@ -325,6 +325,17 @@ smc1: clock-controller@40410000 {
>                         clock-names = "divcore", "hsrun_divcore";
>                 };
>
> +               wdog2: watchdog@40430000 {
> +                       compatible = "fsl,imx7ulp-wdt";
> +                       reg = <0x40430000 0x10000>;
> +                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
> +                       assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
> +                       assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
> +                       timeout-sec = <40>;
> +                       status = "disabled";

You missed passing bootph-all here.

Adding wdog2 would probably make more sense on a separate patch.

Re: [PATCH v1] arm: dts: imx: Add watchdog support for early boot stages

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Hardware IRQ conflict: wdog4 and ddr-pmu share the same interrupt in imx94.dtsi.
- [Medium] Missing bootph-all property on the newly added wdog2 node in imx7ulp.dtsi.
- [Medium] Undocumented addition of multiple new watchdog hardware nodes.
--

commit 566f5af2df66e555eb4881057449fc8955a46103
Author: Alice Guo <alice.guo@nxp.com>

arm: dts: imx: Add watchdog support for early boot stages

This commit adds the bootph-all property to watchdog nodes across several
i.MX device trees to make them available during U-Boot's early boot phases.
It also introduces several new watchdog nodes to the device trees.

> diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
> index 880b9a4f32b08..5e3e562225e58 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
> @@ -297,6 +297,17 @@ smc1: clock-controller@40410000 {
>  			clock-names = "divcore", "hsrun_divcore";
>  		};
>  
> +		wdog2: watchdog@40430000 {
> +			compatible = "fsl,imx7ulp-wdt";
> +			reg = <0x40430000 0x10000>;
> +			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
> +			timeout-sec = <40>;
> +			status = "disabled";
> +		};

Was the bootph-all property intentionally omitted from this node?

The commit message explicitly states the purpose of the patch is to add
the bootph-all property to watchdog nodes, but it appears to be missing
from this newly added wdog2 node.

Additionally, is adding completely new hardware nodes expected within
this patch?

The commit message notes that the patch adds the bootph-all property
to watchdog nodes, but the diff reveals the patch actually introduces
entirely new watchdog nodes (such as wdog2 in imx7ulp.dtsi, and wdog4
in imx94.dtsi, imx95.dtsi, and imx952.dtsi).

Should the commit message be updated to explicitly document the
addition of these new hardware nodes, or should these additions be split
into a separate preparatory patch?

[ ... ]

> diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
> index d2f31c8caf6eb..be366af8ac912 100644
> --- a/arch/arm64/boot/dts/freescale/imx94.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
> @@ -1220,6 +1220,18 @@ wdog3: watchdog@49220000 {
>  				timeout-sec = <40>;
>  				fsl,ext-reset-output;
>  				status = "disabled";
> +				bootph-all;
> +			};
> +
> +			wdog4: watchdog@49230000 {
> +				compatible = "fsl,imx94-wdt", "fsl,imx93-wdt";
> +				reg = <0x49230000 0x10000>;
> +				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;

Could this interrupt assignment conflict with existing hardware?

Looking at the same imx94.dtsi file, GIC_SPI 91 is already assigned to the
ddr-pmu node:

		ddr-pmu@4e090dc0 {
			compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu";
			reg = <0x0 0x4e090dc0 0x0 0x200>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		};

Sharing a GIC SPI interrupt between independent hardware blocks like a
watchdog and a PMU is an unusual hardware description unless they are
explicitly designed to share IRQ handling.

Does this need to be updated to the correct hardware interrupt to prevent
issues if the watchdog driver is updated to request this IRQ?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260512024850.904551-1-alice.guo@oss.nxp.com?part=1