[PATCH v2 0/3] Add DMA support for i.MX94 and improve AHB read performance

[PATCH v2 0/3] Add DMA support for i.MX94 and improve AHB read performance

[han.xu]

This series adds DMA support to the NXP XSPI controller on i.MX94
and enables the use of DMA for AHB read operations to improve
performance.

On i.MX943 EVK, the measured read throughput improves 4x higher, from
approximately 70 MB/s to 290 MB/s when DMA is used.

Changes in v2:
- Reorder the patch series.
- Adjust DT binding patch subject lines to match SPI subsystem conventions.
- Update commit message to include ~4x AHB read performance improvement.
- Rename DMA timeout macro to indicate time unit and document timeout selection.
- Simplify DMA channel initialization flow.
- Add CPU fallback path when DMA read fails.
- Clarify/fix DMA alignment handling based on DMA engine requirements.
- Drop unrelated formatting change in probe().

Signed-off-by: Han Xu <han.xu@nxp.com>
---
Han Xu (3):
      spi: dt-bindings: nxp,imx94-xspi: add DMA properties
      spi: nxp-xspi: Improve AHB read performance with DMA
      arm64: dts: imx94-xspi: add the DMA channels

 .../devicetree/bindings/spi/nxp,imx94-xspi.yaml    |  10 ++
 arch/arm64/boot/dts/freescale/imx94.dtsi           |   4 +
 drivers/spi/spi-nxp-xspi.c                         | 130 ++++++++++++++++++++-
 3 files changed, 141 insertions(+), 3 deletions(-)
---
base-commit: 2c2900017f2486e7b46795e80d7c8f3f8fbe0236
change-id: 20260621-xspi_dma_upstream-324c07d4c116

Best regards,
--  
Han Xu <han.xu@nxp.com>

[PATCH v2 1/3] spi: dt-bindings: nxp,imx94-xspi: add DMA properties

[han.xu]

From: Han Xu <han.xu@nxp.com>

Add dmas and dma-names to describe TX and RX DMA channels for the i.MX94
XSPI controller.

Signed-off-by: Han Xu <han.xu@nxp.com>
---
 Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml b/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml
index 16a0598c6d033..ccf841f194c06 100644
--- a/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml
+++ b/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml
@@ -30,6 +30,16 @@ properties:
       - const: base
       - const: mmap
 
+  dmas:
+    items:
+      - description: Transmit DMA
+      - description: Receive DMA
+
+  dma-names:
+    items:
+      - const: tx
+      - const: rx
+
   interrupts:
     items:
       - description: interrupt for EENV0

-- 
2.34.1

[PATCH v2 2/3] spi: nxp-xspi: Improve AHB read performance with DMA

[han.xu]

From: Han Xu <han.xu@nxp.com>

Use eDMA for XSPI AHB read to improve the performance.

Read with CPU
root@imx943evk:~# dd if=/dev/mtd0 of=/dev/null bs=32M count=1
1+0 records in
1+0 records out
33554432 bytes (34 MB, 32 MiB) copied, 0.479719 s, 69.9 MB/s

Read with DMA
root@imx943evk:~# dd if=/dev/mtd0 of=/dev/null bs=32M count=1
1+0 records in
1+0 records out
33554432 bytes (34 MB, 32 MiB) copied, 0.115788 s, 290 MB/s

Signed-off-by: Han Xu <han.xu@nxp.com>
---
 drivers/spi/spi-nxp-xspi.c | 130 +++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 127 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-nxp-xspi.c b/drivers/spi/spi-nxp-xspi.c
index 037eac24e6fd2..0658c0557ff17 100644
--- a/drivers/spi/spi-nxp-xspi.c
+++ b/drivers/spi/spi-nxp-xspi.c
@@ -35,6 +35,8 @@
 #include <linux/clk.h>
 #include <linux/completion.h>
 #include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
 #include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/interrupt.h>
@@ -303,6 +305,12 @@
 	(opr)) << (((idx) % 2) * OPRND_SHIFT))
 
 #define NXP_XSPI_MIN_IOMAP	SZ_4M
+/*
+ * It takes 0.5s to access the entire area with DMA,
+ * leaving a 10x safety margin
+ */
+#define NXP_XSPI_DMA_TOUT_MS	5000
+#define NXP_XSPI_DMA_TOUT	msecs_to_jiffies(NXP_XSPI_DMA_TOUT_MS)
 #define NXP_XSPI_MAX_CHIPSELECT		2
 #define POLL_TOUT_US		5000
 
@@ -336,6 +344,9 @@ struct nxp_xspi {
 	/* mutex lock for each operation */
 	struct mutex lock;
 	int selected;
+	int dma_copy_align;
+	struct dma_chan *dma_rx;
+	struct completion dma_rx_c;
 #define XSPI_DTR_PROTO		BIT(0)
 	int flags;
 	/* Save the previous operation clock rate */
@@ -796,6 +807,82 @@ static int nxp_xspi_ahb_read(struct nxp_xspi *xspi, const struct spi_mem_op *op)
 	return 0;
 }
 
+static int nxp_xspi_dma_init(struct device *dev, struct nxp_xspi *xspi)
+{
+	struct dma_chan *rx;
+
+	rx = dma_request_chan(dev, "rx");
+	if (IS_ERR(rx)) {
+		int ret = PTR_ERR(rx);
+
+		if (ret == -EPROBE_DEFER)
+			return ret;
+		dev_dbg(dev, "NO DMA RX channel, falling back to CPU read\n");
+		xspi->dma_copy_align = 1;
+		return 0;
+	}
+
+	xspi->dma_rx = rx;
+	init_completion(&xspi->dma_rx_c);
+	xspi->dma_copy_align = 1 << rx->device->copy_align;
+
+	return 0;
+}
+
+static void nxp_xspi_dma_rx_callback(void *data)
+{
+	struct nxp_xspi *xspi = data;
+
+	complete(&xspi->dma_rx_c);
+}
+
+static int nxp_xspi_ahb_dma_read(struct nxp_xspi *xspi,
+				 const struct spi_mem_op *op)
+{
+	struct dma_async_tx_descriptor *desc;
+	struct dma_chan *chan = xspi->dma_rx;
+	unsigned long timeout;
+	dma_addr_t dma_addr;
+	int ret = 0;
+
+	dma_addr = dma_map_single(chan->device->dev,
+				  op->data.buf.in, op->data.nbytes,
+				  DMA_FROM_DEVICE);
+
+	if (dma_mapping_error(chan->device->dev, dma_addr)) {
+		dev_err(xspi->dev, "failed to map DMA buffer for AHB read\n");
+		return -ENOMEM;
+	}
+
+	desc = dmaengine_prep_dma_memcpy(chan, dma_addr,
+					 xspi->memmap_phy + op->addr.val,
+					 op->data.nbytes,
+					 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!desc) {
+		dev_err(xspi->dev, "failed to prepare AHB RX DMA descriptor\n");
+		ret = -EIO;
+		goto err_unmap;
+	}
+	desc->callback = nxp_xspi_dma_rx_callback;
+	desc->callback_param = xspi;
+	reinit_completion(&xspi->dma_rx_c);
+	dmaengine_submit(desc);
+	dma_async_issue_pending(chan);
+
+	timeout = wait_for_completion_timeout(&xspi->dma_rx_c, NXP_XSPI_DMA_TOUT);
+	if (!timeout) {
+		dev_err(xspi->dev, "AHB RX DMA timeout\n");
+		dmaengine_terminate_sync(chan);
+		ret = -ETIMEDOUT;
+	}
+
+err_unmap:
+	dma_unmap_single(chan->device->dev, dma_addr,
+			 op->data.nbytes, DMA_FROM_DEVICE);
+
+	return ret;
+}
+
 static int nxp_xspi_fill_txfifo(struct nxp_xspi *xspi,
 				 const struct spi_mem_op *op)
 {
@@ -1016,10 +1103,21 @@ static int nxp_xspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 	 *     all use IP write.
 	 */
 	if ((op->data.dir == SPI_MEM_DATA_IN) && !needs_ip_only(xspi)
-		&& ((op->addr.val + op->data.nbytes) <= xspi->memmap_phy_size))
-		err = nxp_xspi_ahb_read(xspi, op);
-	else
+		&& ((op->addr.val + op->data.nbytes) <= xspi->memmap_phy_size)) {
+		/* use DMA for transfers no less than ahb_buf_size, when DMA is available */
+		if (xspi->dma_rx && op->data.nbytes >= xspi->devtype_data->ahb_buf_size) {
+			err = nxp_xspi_ahb_dma_read(xspi, op);
+			if (err) {
+				dev_warn_ratelimited(xspi->dev,
+					"DMA read failed (%d), falling back to CPU read\n", err);
+				err = nxp_xspi_ahb_read(xspi, op);
+			}
+		} else {
+			err = nxp_xspi_ahb_read(xspi, op);
+		}
+	} else {
 		err = nxp_xspi_do_op(xspi, op);
+	}
 
 	nxp_xspi_sw_reset(xspi);
 
@@ -1029,6 +1127,7 @@ static int nxp_xspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 static int nxp_xspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
 {
 	struct nxp_xspi *xspi = spi_controller_get_devdata(mem->spi->controller);
+	int alignment = xspi->dma_copy_align;
 
 	if (op->data.dir == SPI_MEM_DATA_OUT) {
 		if (op->data.nbytes > xspi->devtype_data->txfifo)
@@ -1042,6 +1141,22 @@ static int nxp_xspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
 		if (!needs_ip_only(xspi) && (op->addr.val < xspi->memmap_phy_size)
 			&& ((op->addr.val + op->data.nbytes) > xspi->memmap_phy_size))
 			op->data.nbytes = xspi->memmap_phy_size - op->addr.val;
+
+		/*
+		 * For AHB DMA read, align the transfer to the DMA alignment
+		 * boundaries. If the start address is unaligned, shorten this
+		 * transfer so the next one starts on an aligned boundary.
+		 * Otherwise, if the length is unaligned, round it down.
+		 */
+		if (xspi->dma_rx && !needs_ip_only(xspi) &&
+		    (op->data.nbytes >= xspi->devtype_data->ahb_buf_size)) {
+			if (op->addr.val % alignment)
+				op->data.nbytes =
+					ALIGN(op->addr.val, alignment) - op->addr.val;
+			else if (op->data.nbytes % alignment)
+				op->data.nbytes =
+					ALIGN_DOWN(op->data.nbytes, alignment);
+		}
 	}
 
 	return 0;
@@ -1203,6 +1318,10 @@ static void nxp_xspi_cleanup(void *data)
 
 	if (xspi->ahb_addr)
 		iounmap(xspi->ahb_addr);
+	if (xspi->dma_rx) {
+		dmaengine_terminate_sync(xspi->dma_rx);
+		dma_release_channel(xspi->dma_rx);
+	}
 }
 
 static int nxp_xspi_probe(struct platform_device *pdev)
@@ -1252,6 +1371,11 @@ static int nxp_xspi_probe(struct platform_device *pdev)
 	if (irq < 0)
 		return dev_err_probe(dev, irq,  "Failed to get irq source");
 
+	/* DMA is optional, failure(other than -EPROBE_DEFER) falls back to CPU */
+	ret = nxp_xspi_dma_init(dev, xspi);
+	if (ret == -EPROBE_DEFER)
+		return ret;
+
 	pm_runtime_set_autosuspend_delay(dev, XSPI_RPM_TIMEOUT_MS);
 	pm_runtime_use_autosuspend(dev);
 	ret = devm_pm_runtime_enable(dev);

-- 
2.34.1

[PATCH v2 3/3] arm64: dts: imx94-xspi: add the DMA channels

[han.xu]

From: Han Xu <han.xu@nxp.com>

Add the DMA channels for iMX94 XSPI controller.

Signed-off-by: Han Xu <han.xu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx94.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index a6cb5a6e848b3..70c9dbf10fa5e 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -827,6 +827,8 @@ xspi1: spi@42b90000 {
 				#size-cells = <0>;
 				clocks = <&scmi_clk IMX94_CLK_XSPI1>;
 				clock-names = "per";
+				dmas = <&edma2 27 0 0>, <&edma2 28 0 FSL_EDMA_RX>;
+				dma-names = "tx", "rx";
 				status = "disabled";
 			};
 
@@ -843,6 +845,8 @@ xspi2: spi@42be0000 {
 				#size-cells = <0>;
 				clocks = <&scmi_clk IMX94_CLK_XSPI2>;
 				clock-names = "per";
+				dmas = <&edma4 42 0 0>, <&edma4 43 0 FSL_EDMA_RX>;
+				dma-names = "tx", "rx";
 				status = "disabled";
 			};
 		};

-- 
2.34.1

Re: [PATCH v2 2/3] spi: nxp-xspi: Improve AHB read performance with DMA

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:

New issues:
- [High] Resource Leak of DMA Channel on probe failure
- [Medium] Missing dma_map_resource for AHB physical address
- [Low] Build Failure: 64-bit modulo by 32-bit variable on 32-bit platforms

Pre-existing issues:
- [High] Data Truncation of physical memory-mapped address
--

--- Patch [2]: [PATCH v2 2/3] spi: nxp-xspi: Improve AHB read performance with DMA ---
commit e55bddd05b9c54ad3776775a32876cb677ace5d2
Author: Han Xu <han.xu@nxp.com>

spi: nxp-xspi: Improve AHB read performance with DMA

Use eDMA for XSPI AHB read to improve the performance.

> diff --git a/drivers/spi/spi-nxp-xspi.c b/drivers/spi/spi-nxp-xspi.c
> index 037eac24e6fd2..0658c0557ff17 100644
> --- a/drivers/spi/spi-nxp-xspi.c
> +++ b/drivers/spi/spi-nxp-xspi.c
[ ... ]
> @@ -796,6 +807,82 @@ static int nxp_xspi_ahb_read(struct nxp_xspi *xspi, const struct spi_mem_op *op)
[ ... ]
> +static int nxp_xspi_ahb_dma_read(struct nxp_xspi *xspi,
> +				 const struct spi_mem_op *op)
> +{
> +	struct dma_async_tx_descriptor *desc;
> +	struct dma_chan *chan = xspi->dma_rx;
> +	unsigned long timeout;
> +	dma_addr_t dma_addr;
> +	int ret = 0;
> +
> +	dma_addr = dma_map_single(chan->device->dev,
> +				  op->data.buf.in, op->data.nbytes,
> +				  DMA_FROM_DEVICE);
> +
> +	if (dma_mapping_error(chan->device->dev, dma_addr)) {
> +		dev_err(xspi->dev, "failed to map DMA buffer for AHB read\n");
> +		return -ENOMEM;
> +	}
> +
> +	desc = dmaengine_prep_dma_memcpy(chan, dma_addr,
> +					 xspi->memmap_phy + op->addr.val,
> +					 op->data.nbytes,
> +					 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

[Severity: High]
This is a pre-existing issue, but since memmap_phy is declared as a u32 in
struct nxp_xspi, will physical addresses located above the 4GB boundary be
silently truncated to 32 bits? If so, this addition to op->addr.val might
cause the DMA controller to access the wrong physical memory.

[Severity: Medium]
If the eDMA controller operates behind an IOMMU that does not identity-map
this MMIO region, will this raw physical address trigger an IOMMU translation
fault?

Should xspi->memmap_phy + op->addr.val be mapped via dma_map_resource()
to obtain a dma_addr_t before being passed into dmaengine_prep_dma_memcpy()?

> +	if (!desc) {
> +		dev_err(xspi->dev, "failed to prepare AHB RX DMA descriptor\n");
> +		ret = -EIO;
> +		goto err_unmap;
> +	}
[ ... ]
> @@ -1029,6 +1127,7 @@ static int nxp_xspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
>  static int nxp_xspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
>  {
[ ... ]
> +		/*
> +		 * For AHB DMA read, align the transfer to the DMA alignment
> +		 * boundaries. If the start address is unaligned, shorten this
> +		 * transfer so the next one starts on an aligned boundary.
> +		 * Otherwise, if the length is unaligned, round it down.
> +		 */
> +		if (xspi->dma_rx && !needs_ip_only(xspi) &&
> +		    (op->data.nbytes >= xspi->devtype_data->ahb_buf_size)) {
> +			if (op->addr.val % alignment)
> +				op->data.nbytes =
> +					ALIGN(op->addr.val, alignment) - op->addr.val;

[Severity: Low]
Because op->addr.val is a 64-bit integer (u64) and alignment is a 32-bit
integer, will this modulo operation cause an unresolved symbol error for
__umoddi3 or __aeabi_uldivmod during the final link stage on 32-bit
architectures?

> +			else if (op->data.nbytes % alignment)
> +				op->data.nbytes =
> +					ALIGN_DOWN(op->data.nbytes, alignment);
> +		}
>  	}
>  
>  	return 0;
[ ... ]
> @@ -1252,6 +1371,11 @@ static int nxp_xspi_probe(struct platform_device *pdev)
>  	if (irq < 0)
>  		return dev_err_probe(dev, irq,  "Failed to get irq source");
>  
> +	/* DMA is optional, failure(other than -EPROBE_DEFER) falls back to CPU */
> +	ret = nxp_xspi_dma_init(dev, xspi);
> +	if (ret == -EPROBE_DEFER)
> +		return ret;
> +
>  	pm_runtime_set_autosuspend_delay(dev, XSPI_RPM_TIMEOUT_MS);
>  	pm_runtime_use_autosuspend(dev);
>  	ret = devm_pm_runtime_enable(dev);

[Severity: High]
Since nxp_xspi_cleanup() is registered via devm_add_action_or_reset() at the
end of nxp_xspi_probe():

    init_completion(&xspi->c);
    ret = devm_request_irq(dev, irq,
            nxp_xspi_irq_handler, 0, pdev->name, xspi);
    ...
    ret = devm_add_action_or_reset(dev, nxp_xspi_cleanup, xspi);

what happens if devm_pm_runtime_enable() (or any other initialization step
before the cleanup action is registered) fails? Will the DMA channel
allocated in nxp_xspi_dma_init() leak on these early error returns?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260721-xspi_dma_upstream-v2-0-9e19d80e7762@nxp.com?part=2

Re: [PATCH v2 1/3] spi: dt-bindings: nxp,imx94-xspi: add DMA properties

[Frank Li]

On Tue, Jul 21, 2026 at 04:01:42PM -0500, han.xu@oss.nxp.com wrote:
> From: Han Xu <han.xu@nxp.com>
>
> Add dmas and dma-names to describe TX and RX DMA channels for the i.MX94
> XSPI controller.
>
> Signed-off-by: Han Xu <han.xu@nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml b/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml
> index 16a0598c6d033..ccf841f194c06 100644
> --- a/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml
> @@ -30,6 +30,16 @@ properties:
>        - const: base
>        - const: mmap
>
> +  dmas:
> +    items:
> +      - description: Transmit DMA
> +      - description: Receive DMA
> +
> +  dma-names:
> +    items:
> +      - const: tx
> +      - const: rx
> +
>    interrupts:
>      items:
>        - description: interrupt for EENV0
>
> --
> 2.34.1
>
>

Re: [PATCH v2 1/3] spi: dt-bindings: nxp,imx94-xspi: add DMA properties

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1146 bytes --]

On Tue, Jul 21, 2026 at 04:01:42PM -0500, han.xu@oss.nxp.com wrote:
> From: Han Xu <han.xu@nxp.com>
> 
> Add dmas and dma-names to describe TX and RX DMA channels for the i.MX94
> XSPI controller.
> 
> Signed-off-by: Han Xu <han.xu@nxp.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

> ---
>  Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml b/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml
> index 16a0598c6d033..ccf841f194c06 100644
> --- a/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml
> @@ -30,6 +30,16 @@ properties:
>        - const: base
>        - const: mmap
>  
> +  dmas:
> +    items:
> +      - description: Transmit DMA
> +      - description: Receive DMA
> +
> +  dma-names:
> +    items:
> +      - const: tx
> +      - const: rx
> +
>    interrupts:
>      items:
>        - description: interrupt for EENV0
> 
> -- 
> 2.34.1
> 

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