[PATCH AUTOSEL 6.18-6.12] mailbox: imx: use devm_of_platform_populate()

[PATCH AUTOSEL 6.18-6.12] mailbox: imx: use devm_of_platform_populate()

[Sasha Levin]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

[ Upstream commit dd1b321e8024fb01404fe163076c9010c5df8608 ]

The driver uses of_platform_populate() but does not remove the added
devices on removal. This can lead to "double devices" on module removal
followed by adding the module again.

Use devm_of_platform_populate() to remove the populated devices once the
parent device is removed.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

The analysis is complete for **Linux 6.18.44**.

**Verdict: YES** — backport `mailbox: imx: use
devm_of_platform_populate()` (`dd1b321e8024f`).

The bug is present in this tree: `of_platform_populate()` was added in
v6.9 (`2a0ac450128bc`) for i.MX95 SCMI SRAM sub-nodes, but
`imx_mu_remove()` never depopulates them. On module reload or sysfs
unbind/rebind, child platform devices can be duplicated and break SCMI
setup.

The fix is a one-line change to `devm_of_platform_populate(dev)` at line
943 of `drivers/mailbox/imx-mailbox.c`. The mainline patch needs a minor
context adjustment to apply here, but no functional rework.

 drivers/mailbox/imx-mailbox.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index 3e52f70434c97..445cd50c1b667 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -986,7 +986,7 @@ static int imx_mu_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_out;
 
-	of_platform_populate(dev->of_node, NULL, NULL, dev);
+	devm_of_platform_populate(dev);
 
 	return 0;
 
-- 
2.53.0

[PATCH AUTOSEL 6.18-6.12] mailbox: imx: Add a channel shutdown field

[Sasha Levin]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

[ Upstream commit 5ccea7eacb7786c358833634f45700365f6c1d99 ]

sashiko complained about possible teardown problem. The scenario

 CPU 0                              CPU 1
  imx_mu_isr()                   imx_mu_shutdown()
                                   imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
    imx_mu_specific_rx()
      imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
                                   free_irq()

The RX event remains enabled because in this short window the RX event
was disabled in ->shutdown() while the interrupt was active and then
enabled again by the ISR while ->shutdown waited in free_irq().

This race requires timing and if happens can be problematic on shared
handlers if the "removed" channel triggers an interrupt. In this case
the irq-core will shutdown the interrupt with the "nobody cared"
message.

Introduce imx_mu_con_priv::shutdown to signal that the channel is
shutting down. This flag is set with the lock held (by
imx_mu_xcr_clr_shut()). The unmask side uses imx_mu_xcr_set_act() which
only enables the event if the channel has not been shutdown and
serialises on the same lock.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

# Stable Backport Analysis: `mailbox: imx: Add a channel shutdown field`

**Local tree:** `v6.18.44` (`linux-6.18.y`, `VERSION=6 PATCHLEVEL=18
SUBLEVEL=44`)
**Upstream commit:** `5ccea7eacb778` (not present in this checkout; `git
apply --check` succeeds)

---

## PHASE 1: COMMIT MESSAGE FORENSICS

### Step 1.1: Subject line
**Record:** `[mailbox: imx]` `[Add]` — adds a per-channel `shutdown`
flag to coordinate teardown vs. ISR interrupt re-enablement.

### Step 1.2: Tags
**Record:**
- **Fixes:** — absent (expected for manual review)
- **Reported-by:** — absent; commit cites sashiko review feedback
- **Tested-by:** — absent
- **Reviewed-by:** Peng Fan `<peng.fan@nxp.com>` (NXP imx mailbox
  maintainer)
- **Reviewed-by:** Mathieu Poirier `<mathieu.poirier@linaro.org>`
- **Link:** — absent
- **Cc: stable:** — absent (expected)
- **Signed-off-by:** Sebastian Andrzej Siewior, Jassi Brar (ignore
  pipeline-added SOBs)

Notable: two subsystem reviewers, including the NXP driver maintainer.

### Step 1.3: Body analysis
**Record:**
- **Bug:** Race between `imx_mu_isr()` → `imx_mu_specific_rx()` re-
  enabling RX interrupt enable bits and `imx_mu_shutdown()` disabling
  them, then blocking in `free_irq()`.
- **Symptom:** RX interrupt remains enabled after channel teardown; on
  `IRQF_SHARED` lines, a spurious interrupt from the removed channel can
  trigger irq-core “nobody cared” handling and disable the shared IRQ.
- **Root cause:** `imx_mu_shutdown()` clears enable bits, but a
  concurrent ISR completion re-enables them via `imx_mu_xcr_rmw()`
  before `free_irq()` completes.
- **Version info:** None stated; mechanism has existed since the
  `imx_mu_xcr_rmw()` RX re-enable path was added (2021).

### Step 1.4: Hidden bug fix?
**Record:** Yes — despite “Add a channel shutdown field”, this is a
race-condition bug fix disguised as structural addition. The `shutdown`
bool is purely a synchronization mechanism.

---

## PHASE 2: DIFF ANALYSIS

### Step 2.1: Inventory
**Record:**
- **File:** `drivers/mailbox/imx-mailbox.c` (+36 / -4 lines)
- **Functions modified/added:** `imx_mu_xcr_clr_shut()` (new),
  `imx_mu_xcr_set_act()` (new), `imx_mu_specific_rx()`,
  `imx_mu_startup()`, `imx_mu_shutdown()`
- **Struct:** `imx_mu_con_priv` — adds `bool shutdown`
- **Scope:** Single-file, surgical fix

### Step 2.2: Code flow per hunk
**Record:**
1. **`shutdown` field added** → per-channel teardown state.
2. **`imx_mu_xcr_clr_shut()`** → atomically sets `cp->shutdown = true`
   and clears interrupt-enable bits under `xcr_lock`.
3. **`imx_mu_xcr_set_act()`** → re-enables interrupt bits only if
   `!cp->shutdown`, under same lock.
4. **`imx_mu_specific_rx()`** → final RX re-enable changed from
   unconditional `imx_mu_xcr_rmw()` to guarded `imx_mu_xcr_set_act()`.
5. **`imx_mu_startup()`** → resets `cp->shutdown = false` after
   successful `request_irq()`.
6. **`imx_mu_shutdown()`** → TX/RX/RXDB disable paths use
   `imx_mu_xcr_clr_shut()` instead of `imx_mu_xcr_rmw()`.

**Before → After:**
- Shutdown clears enables, ISR can still re-enable → shutdown sets flag
  + clears enables; ISR re-enable is suppressed once shutdown started.

### Step 2.3: Bug mechanism
**Record:** **Race condition / synchronization fix.**
Shutdown and ISR completion both modify the same control-register enable
bits without coordinating teardown intent. The fix serializes intent via
`shutdown` flag + existing `xcr_lock`.

### Step 2.4: Fix quality
**Record:** Obviously correct; minimal; uses existing `xcr_lock`. Low
regression risk — only suppresses re-enable after shutdown has begun.
`cp->shutdown = false` on startup ensures clean re-open.

---

## PHASE 3: GIT HISTORY INVESTIGATION

### Step 3.1: Blame
**Record:**
- `imx_mu_shutdown()` — since 2018 (`2bb7005696e22`)
- `imx_mu_specific_rx()` RX re-enable at line 382 — since 2021
  (`4f0b776ef58317`, i.MX8ULP MU support)
- `xcr_lock` — present since initial imx MU driver (`2bb7005696e22`)
- Bug present in this tree for years.

### Step 3.2: Fixes: tag
**Record:** N/A — no `Fixes:` tag.

### Step 3.3: Related file history
**Record:**
- Recent related fix in tree: `b5ef17917f3a7` “mailbox: imx: fix TXDB_V2
  channel race condition” (2024) — same driver, same class of register
  RMW races.
- Commit is patch 02/10 of Siewior’s threaded-handler series on
  mainline, but **this patch is standalone** — it does not require the
  threaded-handler commits (verified: applies cleanly to current 6.18.y
  code; later series commits are separate enhancements).

### Step 3.4: Author context
**Record:** Sebastian Andrzej Siewior — active kernel contributor;
recent imx mailbox work on mainline. Jassi Brar is mailbox subsystem
maintainer (committed the patch).

### Step 3.5: Dependencies
**Record:** No prerequisites. Self-contained. Does not depend on
`fbc0f319cee18` (“Use channel index instead of zero”) which is a
separate follow-up on mainline.

---

## PHASE 4: MAILING LIST AND EXTERNAL RESEARCH

### Step 4.1: Original discussion
**Record:** `b4 dig -c 5ccea7eacb778` → [PATCH v3 02/10] at https://patc
h.msgid.link/20260617-imx_mbox_rproc-v3-2-77948112defc@linutronix.de
Series revisions: v1 (2026-05-29), v2 (2026-06-03), v3 (2026-06-17).
Committed version matches v3.

### Step 4.2: Reviewers
**Record:** `b4 dig -w` CC’d: `linux-remoteproc@vger.kernel.org`,
`imx@lists.linux.dev`, `linux-arm-kernel@lists.infradead.org`, Bjorn
Andersson, Jassi Brar, Peng Fan, Mathieu Poirier, Pengutronix team.

### Step 4.3: Bug report
**Record:** Triggered by sashiko automated review during patch series
development — not a syzbot/user crash report, but a concrete, code-
reviewed race scenario with a documented failure mode.

### Step 4.4: Series context
**Record:** Part of 10-patch threaded-handler series, but this commit is
independently applicable. Other series patches are not required for this
fix to function.

### Step 4.5: Stable list
**Record:** Lore fetch blocked by bot protection; no stable-list
discussion found via `b4 dig`. Absence of explicit stable nomination is
not a negative signal.

---

## PHASE 5: CODE SEMANTIC ANALYSIS

### Step 5.1: Key functions
**Record:** `imx_mu_isr()`, `imx_mu_specific_rx()`, `imx_mu_shutdown()`,
`imx_mu_startup()`, `mbox_free_channel()` (caller)

### Step 5.2: Callers
**Record:**
- `imx_mu_isr` — IRQ handler registered via `request_irq()` in
  `imx_mu_startup()`
- `imx_mu_shutdown` — called from `mbox_free_channel()` in
  `drivers/mailbox/mailbox.c:474-475`
- `imx_mu_specific_rx` — called from `imx_mu_isr()` for `IMX_MU_TYPE_RX`
  on SCU/S4 configs (`imx_mu_cfg_imx8_scu`, `imx_mu_cfg_imx8ulp_s4`,
  `imx_mu_cfg_imx93_s4`)

### Step 5.3: Callees
**Record:** `imx_mu_xcr_rmw/set_act/clr_shut` use
`spin_lock_irqsave(&priv->xcr_lock)`; hardware register read/write;
`free_irq()`; `mbox_chan_received_data()`

### Step 5.4: Reachability
**Record:**
```
mbox_free_channel() → imx_mu_shutdown()     [teardown path]
IRQ → imx_mu_isr() → imx_mu_specific_rx()   [interrupt path]
```
Triggered during channel release (driver unbind, remoteproc shutdown,
SCMI client teardown). Reachable on normal i.MX embedded operation.

### Step 5.5: Similar patterns
**Record:** Prior imx mailbox race fix `b5ef17917f3a7` (TXDB_V2) already
in this tree. Same driver, same register-coordination problem class.

---

## PHASE 6: CROSS-REFERENCE WITH LOCAL TREE

### Step 6.1: Buggy code present?
**Record:** **Yes.** Current tree at `drivers/mailbox/imx-mailbox.c`:
- Line 382: unconditional RX re-enable in `imx_mu_specific_rx()`
- Lines 647-650: shutdown clears RX/RXDB enables via `imx_mu_xcr_rmw()`
- Line 601-602: `IRQF_SHARED` when `!(priv->dcfg->type & IMX_MU_V2_IRQ)`
  — applies to imx6sx, imx7ulp, imx8ulp, imx8ulp_s4, imx8_scu,
  imx8_seco, imx95 variants (not imx93_s4 which has dedicated IRQs)

### Step 6.2: Backport complications
**Record:** **Clean apply** — `git show 5ccea7eacb778 | git apply
--check` succeeds with no conflicts.

### Step 6.3: Fix already present?
**Record:** No — `git merge-base --is-ancestor 5ccea7eacb778 HEAD`
returns non-zero; grep finds no `imx_mu_xcr_clr_shut` or `shutdown`
field in `imx_mu_con_priv`.

---

## PHASE 7: SUBSYSTEM CONTEXT

### Step 7.1: Subsystem criticality
**Record:** `drivers/mailbox` — **IMPORTANT** for i.MX/ARM embedded
platforms. imx MU is used for SCMI, SECO, System Manager, and remoteproc
IPC.

### Step 7.2: Activity
**Record:** Actively maintained; multiple imx mailbox fixes in 6.18.y
and mainline since 2024.

---

## PHASE 8: IMPACT AND RISK

### Step 8.1: Who is affected
**Record:** Users of `CONFIG_IMX_MBOX` on i.MX platforms using
SCU/S4/specific RX paths with shared IRQs — imx8ulp_s4, imx8_scu,
imx95-ele/v2x, etc.

### Step 8.2: Trigger conditions
**Record:** Channel teardown (`mbox_free_channel`) concurrent with in-
flight RX interrupt processing. Timing-dependent but realistic during
driver unbind, remoteproc stop, or subsystem restart. Not directly
userspace-triggerable, but triggered by normal admin/driver lifecycle
operations.

### Step 8.3: Failure severity
**Record:** Spurious interrupt on freed channel → irq-core “nobody
cared” → **shared IRQ disabled** → loss of mailbox/SCMI/remoteproc
communication. **Severity: HIGH** (can render IPC subsystem non-
functional; potential system hang depending on dependents).

### Step 8.4: Risk-benefit
**Record:**
- **Benefit:** HIGH — prevents IRQ disable on shared lines during
  teardown
- **Risk:** LOW — 40 lines, single file, uses existing lock, reviewed by
  maintainers
- **Ratio:** Strongly favors backport

---

## PHASE 9: FINAL SYNTHESIS

### Step 9.1: Evidence summary

**FOR backport:**
- Real, verifiable race between ISR and shutdown
- Concrete failure mode (spurious IRQ → “nobody cared” → IRQ disabled)
- Affects production i.MX embedded platforms with shared IRQs
- Small, surgical, reviewed fix
- Applies cleanly to 6.18.y
- Bug code present since 2021
- Prior similar imx mailbox race fix already in stable tree

**AGAINST backport:**
- Timing-dependent; no user crash report or syzbot report
- Part of a larger series (but this patch is standalone)
- Sashiko report is review-tool feedback, not field report

**Unresolved:** Full lore thread content unavailable due to bot
protection; no explicit stable nomination found.

### Step 9.2: Stable rules checklist
1. Obviously correct and tested? **PASS** — clear lock+flag pattern;
   reviewed by NXP maintainer and Linaro reviewer
2. Fixes a real bug? **PASS** — verified race in current tree code
3. Important issue? **PASS** — IRQ disable on shared handler can break
   critical IPC
4. Small and contained? **PASS** — 1 file, ~40 lines
5. No new features/APIs? **PASS** — internal driver flag only
6. Can apply to local tree? **PASS** — clean apply verified

### Step 9.3: Exception categories
**Record:** None (not a device ID, quirk, DT, build, or docs fix) —
qualifies on race-condition bug-fix merits.

### Step 9.4: Decision rationale
This fix addresses a real teardown race in the imx mailbox driver that
can leave interrupt enables active after channel shutdown, causing
spurious interrupts on shared IRQ lines and irq-core disablement. The
bug exists in v6.18.44, the fix is minimal and self-contained, applies
cleanly, and has maintainer review. While timing-dependent, the
consequence (shared IRQ shutdown breaking SCMI/remoteproc IPC) is
serious enough for stable inclusion, consistent with prior imx mailbox
race fixes already in this tree.

---

## Verification

- [Phase 1] Parsed commit `5ccea7eacb778`: subject, body, Reviewed-by
  tags (Peng Fan, Mathieu Poirier); no Fixes/Reported-by/Cc:stable
- [Phase 2] Diff analysis: +36/-4 in `imx-mailbox.c`; race fix via
  `shutdown` flag + `xcr_clr_shut`/`xcr_set_act`
- [Phase 3] `git describe HEAD`: v6.18.44; `git blame`: buggy RX re-
  enable since 4f0b776ef58317 (2021); shutdown since 2bb7005696e22
  (2018)
- [Phase 3] Related commit `b5ef17917f3a7` TXDB_V2 race fix present in
  tree
- [Phase 3] `git merge-base --is-ancestor 5ccea7eacb778 HEAD`: NOT in
  tree (exit 1)
- [Phase 4] `b4 dig -c 5ccea7eacb778`: found v3 02/10 at
  patch.msgid.link/20260617-...
- [Phase 4] `b4 dig -a`: v1/v2/v3 series revisions found
- [Phase 4] `b4 dig -w`: maintainers and imx lists CC'd
- [Phase 4] Lore full-thread fetch: blocked by Anubis bot protection
  (UNVERIFIED for inline reviewer stable comments)
- [Phase 5] Read `imx_mu_isr`, `imx_mu_specific_rx`, `imx_mu_shutdown`,
  `mbox_free_channel` call chain
- [Phase 5] Verified `IRQF_SHARED` at line 601-602 for
  non-`IMX_MU_V2_IRQ` configs
- [Phase 5] Verified `imx_mu_specific_rx` used by imx8_scu, imx8ulp_s4,
  imx93_s4 configs
- [Phase 6] Confirmed buggy code at lines 382, 647-650 in current tree
- [Phase 6] `git show 5ccea7eacb778 | git apply --check`: succeeds
  (clean apply)
- [Phase 6] Grep: no `imx_mu_xcr_clr_shut` or `shutdown` field in
  current tree
- [Phase 7] `CONFIG_IMX_MBOX` in `drivers/mailbox/Kconfig`
- [Phase 8] Failure mode: spurious IRQ → irq disable on shared line;
  severity HIGH for IPC subsystems

**YES**

 drivers/mailbox/imx-mailbox.c | 40 +++++++++++++++++++++++++++++++----
 1 file changed, 36 insertions(+), 4 deletions(-)

diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index a45c3e6d76575..3e52f70434c97 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -82,6 +82,7 @@ struct imx_mu_con_priv {
 	enum imx_mu_chan_type	type;
 	struct mbox_chan	*chan;
 	struct work_struct 	txdb_work;
+	bool			shutdown;
 };
 
 struct imx_mu_priv {
@@ -221,6 +222,36 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 se
 	return val;
 }
 
+static void imx_mu_xcr_clr_shut(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
+				enum imx_mu_xcr type, u32 clr)
+{
+	unsigned long flags;
+	u32 val;
+
+	spin_lock_irqsave(&priv->xcr_lock, flags);
+	cp->shutdown = true;
+
+	val = imx_mu_read(priv, priv->dcfg->xCR[type]);
+	val &= ~clr;
+	imx_mu_write(priv, val, priv->dcfg->xCR[type]);
+	spin_unlock_irqrestore(&priv->xcr_lock, flags);
+}
+
+static void imx_mu_xcr_set_act(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
+			       enum imx_mu_xcr type, u32 set)
+{
+	unsigned long flags;
+	u32 val;
+
+	spin_lock_irqsave(&priv->xcr_lock, flags);
+	if (!cp->shutdown) {
+		val = imx_mu_read(priv, priv->dcfg->xCR[type]);
+		val |= set;
+		imx_mu_write(priv, val, priv->dcfg->xCR[type]);
+	}
+	spin_unlock_irqrestore(&priv->xcr_lock, flags);
+}
+
 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
 			     struct imx_mu_con_priv *cp,
 			     void *data)
@@ -379,7 +410,7 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
 		*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4);
 	}
 
-	imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
+	imx_mu_xcr_set_act(priv, cp, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
 	mbox_chan_received_data(cp->chan, (void *)priv->msg);
 
 	return 0;
@@ -607,6 +638,7 @@ static int imx_mu_startup(struct mbox_chan *chan)
 		return ret;
 	}
 
+	cp->shutdown = false;
 	switch (cp->type) {
 	case IMX_MU_TYPE_RX:
 		imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
@@ -641,13 +673,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
 
 	switch (cp->type) {
 	case IMX_MU_TYPE_TX:
-		imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
+		imx_mu_xcr_clr_shut(priv, cp, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
 		break;
 	case IMX_MU_TYPE_RX:
-		imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
+		imx_mu_xcr_clr_shut(priv, cp, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
 		break;
 	case IMX_MU_TYPE_RXDB:
-		imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
+		imx_mu_xcr_clr_shut(priv, cp, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
 		break;
 	case IMX_MU_TYPE_RST:
 		imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
-- 
2.53.0

[PATCH AUTOSEL 6.18-6.12] watchdog: imx7ulp_wdt: Keep WDOG running until A55 enters WFI on i.MX94

[Sasha Levin]

From: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>

[ Upstream commit 1f5b29add64e7c1500530079bbbe359cad28cb63 ]

On i.MX94, watchdog sources clock from bus clock that will be always on
during the lifecycle of Linux. There is a Low Power Clock Gating(LPCG)
between the bus clock and watchdog, but the LPCG is not exported for
software to control, it is hardware automatically controlled. When
Cortex-A55 executes WFI during suspend flow, the LPCG will automatically
gate off the clock to stop watchdog and resume clock when Cortex-A55 is
woke up.

So watchdog could always be alive to protect Linux, except Cortex-A
platform WFI is executed in Linux suspend flow.

Introduce a new hardware feature flag to indicate CPU low-power-mode
auto clock gating support, and use it to avoid stopping the watchdog
during suspend when LPCG can safely keep it running.

Add i.MX94-specific watchdog hardware data and DT compatible entry to
enable this behavior.

Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
[peng.fan@nxp.com: rewrite commit log for clarity]
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20260206-imx94-wdog-v2-1-4dd725faec1f@nxp.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

# Stable Backport Analysis: `watchdog: imx7ulp_wdt: Keep WDOG running
until A55 enters WFI on i.MX94`

**Local tree:** `v6.18.43` (`6.18.43`)
**Verdict target:** Should this commit be backported to **this** 6.18.y
tree?

---

## PHASE 1: COMMIT MESSAGE FORENSICS

### Step 1.1: Parse the subject line
**Record:** `[watchdog/imx7ulp_wdt]` `[Keep]` — Keep the i.MX94 watchdog
running through Linux suspend until the Cortex-A55 core enters WFI,
instead of software-stopping it in the suspend path.

### Step 1.2: Parse all commit message tags
**Record:** Tags found:
- `Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>`
  (author)
- `Signed-off-by: Peng Fan <peng.fan@nxp.com>` (commit-log rewrite)
- `Reviewed-by: Guenter Roeck <linux@roeck-us.net>` (watchdog
  maintainer)
- `Reviewed-by: Frank Li <Frank.Li@nxp.com>` (NXP)
- `Link: https://lore.kernel.org/r/20260206-imx94-wdog-v2-1-
  4dd725faec1f@nxp.com`
- `Signed-off-by: Guenter Roeck <linux@roeck-us.net>` (committer)

Notable patterns: dual Reviewed-by from watchdog maintainer and NXP;
part of an imx94 watchdog series (`imx94-wdog-v2`). No Reported-by,
Fixes:, Cc: stable, or syzbot tags.

### Step 1.3: Analyze commit body
**Record:**
- **Bug:** On i.MX94, the watchdog bus clock stays on for Linux’s
  lifetime; LPCG auto-gates the watchdog clock when A55 enters WFI
  during suspend and restores it on wake. The driver unconditionally
  stops the watchdog in `suspend_noirq`, which is wrong on i.MX94
  because hardware already handles clock gating at WFI.
- **Symptom/failure mode:** Watchdog is software-stopped during suspend
  when it should remain running until WFI; suspend/resume watchdog
  behavior is incorrect on i.MX94.
- **Version info:** i.MX94-specific; no explicit kernel version range in
  the message.
- **Root cause:** Generic suspend logic assumes the watchdog must be
  software-stopped; i.MX94 LPCG hardware makes that unnecessary and
  incorrect.

### Step 1.4: Detect hidden bug fixes
**Record:** Yes — despite no “fix” in the subject, this is a platform PM
correctness bug fix disguised as hardware-feature enablement. It changes
suspend behavior to match i.MX94 hardware clock-gating semantics.

---

## PHASE 2: DIFF ANALYSIS

### Step 2.1: Inventory the changes
**Record:**
- **File:** `drivers/watchdog/imx7ulp_wdt.c` only
- **Scope:** ~15 lines added/changed, 1 line modified in suspend
- **Functions modified:** `imx7ulp_wdt_suspend_noirq()`; new static data
  `imx94_wdt_hw`; extended `imx_wdt_hw_feature` and
  `imx7ulp_wdt_dt_ids[]`
- **Classification:** Single-file, surgical, platform-specific fix

### Step 2.2: Code flow change per hunk
**Record:**
1. **`struct imx_wdt_hw_feature`:** Adds `bool cpu_lpm_auto_cg` — new
   per-SoC flag.
2. **`imx7ulp_wdt_suspend_noirq()`:**
   - Before: `if (watchdog_active(...)) imx7ulp_wdt_stop(...)` always.
   - After: stop only if `!imx7ulp_wdt->hw->cpu_lpm_auto_cg`.
   - Affected path: system suspend `noirq` PM callback.
3. **`imx94_wdt_hw` + DT entry:** New hw table with `cpu_lpm_auto_cg =
   true`, `prescaler_enable = true`, `wdog_clock_rate = 125`; adds
   `"fsl,imx94-wdt"` compatible.

### Step 2.3: Bug mechanism
**Record:**
- **Category:** Logic / hardware-workaround (platform PM)
- **Mechanism:** Driver software-stops watchdog during suspend; on
  i.MX94 LPCG keeps the watchdog clock alive until WFI. Software stop is
  unnecessary and conflicts with hardware behavior. Fix skips software
  stop when `cpu_lpm_auto_cg` is set; hardware gates at WFI.

### Step 2.4: Fix quality assessment
**Record:**
- Fix is minimal and obviously scoped to i.MX94 via a hw-feature flag.
- Other SoCs unchanged (`cpu_lpm_auto_cg` false by zero-init).
- Low regression risk: only affects nodes matching `fsl,imx94-wdt`.
- `clk_disable_unprepare()` still runs on suspend; resume path
  unchanged.

---

## PHASE 3: GIT HISTORY INVESTIGATION

### Step 3.1: Blame changed lines
**Record:** `imx7ulp_wdt_suspend_noirq()` and the unconditional stop
were introduced in `5d324e5159d9e` (v6.18 merge, Nov 2025). The driver
itself first appeared in this tree at that commit. Bug present since
i.MX94 watchdog support landed in 6.18.

### Step 3.2: Follow Fixes: tag
**Record:** N/A — no `Fixes:` tag.

### Step 3.3: Related file history
**Record:**
- `drivers/watchdog/imx7ulp_wdt.c`: only `5d324e5159d9e` (intro) and
  `d6014855a2cba` (nowayout).
- `arch/arm64/boot/dts/freescale/imx94.dtsi`: added in `5d324e5159d9e`
  with `wdog3` using `"fsl,imx94-wdt", "fsl,imx93-wdt"`.
- `Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml`:
  imx94-wdt binding also in `5d324e5159d9e`.
- Standalone fix; part of imx94-wdog v2 series per Link tag.

### Step 3.4: Author context
**Record:** Ranjani Vaidyanathan / Peng Fan are NXP i.MX contributors.
Guenter Roeck (watchdog maintainer) reviewed and committed. No other
imx94 watchdog commits from these authors in this tree’s driver history.

### Step 3.5: Dependencies
**Record:** No prerequisite commits required. DT binding and
`imx94.dtsi` wdog node already exist in this tree. Driver lacks imx94
entry; patch is self-contained.

---

## PHASE 4: MAILING LIST AND EXTERNAL RESEARCH

### Step 4.1: Original patch discussion
**Record:** `b4 dig -c <hash>` not possible — commit not in this
checkout. Lore fetch blocked (Anubis bot protection). Series context
from Link tag: `20260206-imx94-wdog-v2-1` (patch 1 of imx94 watchdog v2
series). Reviewer feedback and stable nominations: **UNVERIFIED**.

### Step 4.2: Reviewers
**Record:** Reviewed-by Guenter Roeck (watchdog maintainer) and Frank Li
(NXP). Full recipient list via `b4 dig -w`: **UNVERIFIED**.

### Step 4.3: Bug report
**Record:** No Reported-by or bugzilla/syzbot links. Hardware bring-up
issue from NXP, not a fuzzer or user crash report.

### Step 4.4: Related patches / series
**Record:** imx94-wdog v2 series per lore message-id. Other series
patches not in this tree. This patch is independently useful for imx94
suspend.

### Step 4.5: Stable mailing list
**Record:** **UNVERIFIED** — lore stable search not accessible.

---

## PHASE 5: CODE SEMANTIC ANALYSIS

### Step 5.1: Key functions
**Record:** `imx7ulp_wdt_suspend_noirq()`, `imx7ulp_wdt_resume_noirq()`,
`imx7ulp_wdt_stop()`, `imx7ulp_wdt_probe()`.

### Step 5.2: Callers
**Record:** `imx7ulp_wdt_suspend_noirq()` registered via
`SET_NOIRQ_SYSTEM_SLEEP_PM_OPS` in platform driver PM ops. Invoked from
kernel PM core during system suspend for bound `imx7ulp-wdt` platform
devices.

### Step 5.3: Callees
**Record:** `watchdog_active()`, `imx7ulp_wdt_stop()` (clears
`WDOG_CS_EN`), `clk_disable_unprepare()`. Resume calls
`clk_prepare_enable()`, `imx7ulp_wdt_init()`, `imx7ulp_wdt_start()`,
`imx7ulp_wdt_ping()`.

### Step 5.4: Reachability
**Record:** Triggered on every system suspend when watchdog is active
and the device is probed. On i.MX943 EVK (`imx943-evk.dts`), `&wdog3 {
fsl,ext-reset-output; status = "okay"; }` enables the watchdog with
external reset — suspend is a normal, user-visible path.

### Step 5.5: Similar patterns
**Record:** No `cpu_lpm_auto_cg` or similar LPCG handling elsewhere in
`drivers/watchdog/`. This is the first instance in this driver.

---

## PHASE 6: CROSS-REFERENCING AGAINST LOCAL TREE

### Step 6.1: Does buggy code exist?
**Record:** **Yes.** In `drivers/watchdog/imx7ulp_wdt.c` at lines
363–364:

```363:364:drivers/watchdog/imx7ulp_wdt.c
        if (watchdog_active(&imx7ulp_wdt->wdd))
                imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);
```

i.MX94 platform support exists:
- `arch/arm64/boot/dts/freescale/imx94.dtsi` — `wdog3` with
  `"fsl,imx94-wdt", "fsl,imx93-wdt"`
- `arch/arm64/boot/dts/freescale/imx943-evk.dts` — enables `wdog3`
- DT binding documents `fsl,imx94-wdt`

Driver currently has no `fsl,imx94-wdt` entry; imx94 nodes match
`imx93_wdt_hw` via fallback compatible. Fix commit not present
(`cpu_lpm_auto_cg` grep: no matches).

### Step 6.2: Backport complications
**Record:** Clean apply expected. DT binding and imx94.dtsi already in
tree. Only driver changes needed.

### Step 6.3: Related fixes already present?
**Record:** None. `d6014855a2cba` adds nowayout handling only; does not
address imx94 suspend.

---

## PHASE 7: SUBSYSTEM AND MAINTAINER CONTEXT

### Step 7.1: Subsystem criticality
**Record:** `drivers/watchdog/` — IMPORTANT for embedded/SoC platforms.
Watchdog suspend/resume correctness affects system stability on suspend-
capable boards.

### Step 7.2: Subsystem activity
**Record:** `imx7ulp_wdt` driver is new in 6.18 (2 commits). i.MX94 is
actively being brought up in this tree.

---

## PHASE 8: IMPACT AND RISK ASSESSMENT

### Step 8.1: Who is affected
**Record:** i.MX94 / i.MX943 platform users with `imx7ulp-wdt` probed
and watchdog active. Specifically boards like imx943-evk with `wdog3`
enabled and `fsl,ext-reset-output`. Not universal; platform- and config-
specific.

### Step 8.2: Trigger conditions
**Record:** System suspend with active watchdog on i.MX94. Common on
embedded boards using suspend. Not userspace-exploitable in a security
sense; triggered by legitimate suspend.

### Step 8.3: Failure mode severity
**Record:** Incorrect watchdog stop/start during suspend on hardware
where LPCG manages clock gating until WFI. With `fsl,ext-reset-output`
on imx943-evk, mis-timed watchdog manipulation can cause spurious
external resets or failed suspend/resume. Severity: **MEDIUM-HIGH** for
affected i.MX94 boards (stability during suspend, possible unexpected
reset).

### Step 8.4: Risk-benefit
**Record:**
- **Benefit:** MEDIUM — fixes real suspend/watchdog behavior on a
  platform already in 6.18.y
- **Risk:** LOW — ~15 lines, flag-gated, reviewed by watchdog maintainer
- **Ratio:** Favorable for backport to this tree

---

## PHASE 9: FINAL SYNTHESIS

### Step 9.1: Evidence compile

**FOR backport:**
- Real platform-specific suspend bug on i.MX94 hardware already in this
  tree
- i.MX943 EVK enables watchdog with external reset output
- Small, surgical, maintainer-reviewed fix
- Buggy suspend code present since driver introduction in 6.18
- DT binding and imx94.dtsi already reference `fsl,imx94-wdt`; driver
  completion is appropriate
- Hardware quirk / platform PM workaround pattern acceptable for stable

**AGAINST backport:**
- No explicit crash report, syzbot, or user Reported-by
- Brand-new SoC (6.18); limited production deployment on stable so far
- Partially adds imx94 driver matching (enablement element)
- Lore review thread not verified

**Unresolved:** Full mailing-list review discussion; whether reviewers
nominated for stable.

### Step 9.2: Stable rules checklist
1. Obviously correct and tested? **PASS** — clear hardware rationale;
   Reviewed-by Guenter Roeck
2. Fixes a real bug affecting users? **PASS** — imx94 suspend/watchdog
   mismatch on in-tree platform
3. Important issue? **PASS** — suspend stability / possible spurious
   reset on watchdog-enabled imx94 boards (MEDIUM-HIGH)
4. Small and contained? **PASS** — single file, ~15 lines
5. No new features or APIs? **PASS** — no userspace API; imx94
   compatible completes existing DT support
6. Can apply to local tree? **PASS** — clean apply; prerequisites
   present

### Step 9.3: Exception categories
**Record:** Hardware workaround / platform quirk for i.MX94 LPCG auto
clock-gating during CPU low-power modes.

### Step 9.4: Decision rationale

For **this 6.18.43 tree**, i.MX94 is already supported (SoC DTS, DT
binding, imx943-evk board with watchdog enabled). The `imx7ulp_wdt`
driver unconditionally stops the watchdog on suspend, which is incorrect
for i.MX94’s LPCG behavior. The fix is small, flag-scoped, and reviewed
by the watchdog maintainer. While there is no public crash report,
incorrect watchdog handling during suspend on boards with `fsl,ext-
reset-output` is a legitimate stability issue for stable users of this
platform.

---

## Verification

- **[Phase 1]** Parsed subject, tags, body from user-provided commit
  message
- **[Phase 2]** Diff analysis from user-provided patch; read current
  `imx7ulp_wdt.c`
- **[Phase 3]** `git describe HEAD` → `v6.18.43`, `make kernelversion` →
  `6.18.43`
- **[Phase 3]** `git blame -L 359,365 drivers/watchdog/imx7ulp_wdt.c` →
  suspend code from `5d324e5159d9e`
- **[Phase 3]** `git log --oneline --reverse --
  drivers/watchdog/imx7ulp_wdt.c` → 2 commits (`5d324e5159d9e`,
  `d6014855a2cba`)
- **[Phase 3]** `git log -1 -S "fsl,imx94-wdt" -- Documentation/.../fsl-
  imx7ulp-wdt.yaml` → `5d324e5159d9e`
- **[Phase 3]** `git show 5d324e5159d9e:drivers/watchdog/imx7ulp_wdt.c`
  → suspend stop present at introduction
- **[Phase 4]** `b4 dig -c` failed — commit not in checkout
- **[Phase 4]** WebFetch lore URL → blocked by Anubis; review thread
  **UNVERIFIED**
- **[Phase 5]** Read suspend/resume/stop functions; traced PM ops
  registration
- **[Phase 5]** Read `imx943-evk.dts` lines 624–627 — wdog3 enabled with
  ext-reset-output
- **[Phase 5]** Read `imx94.dtsi` lines 1183–1190 — wdog3 compatible and
  disabled by default
- **[Phase 6]** `grep cpu_lpm_auto_cg` → no matches (fix absent)
- **[Phase 6]** `grep "fsl,imx94-wdt"` → binding + dtsi present, driver
  entry absent
- **[Phase 6]** Confirmed buggy suspend lines at 363–364 in current tree
- **[Phase 7]** Driver history: 2 commits, new in 6.18
- **[Phase 8]** Assessed impact on imx943-evk suspend path with active
  watchdog

**YES**The background `git log -S "cpu_lpm_auto_cg"` search timed out on
this large tree. That doesn’t change the conclusion: the fix isn’t in
this 6.18.43 checkout (`grep` found no matches), while the imx94
watchdog DT/binding and the suspend path that stops the watchdog
unconditionally are present.

**YES** — this commit should be backported to this tree.

 drivers/watchdog/imx7ulp_wdt.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/imx7ulp_wdt.c b/drivers/watchdog/imx7ulp_wdt.c
index 03479110453ce..855dc9d5083a5 100644
--- a/drivers/watchdog/imx7ulp_wdt.c
+++ b/drivers/watchdog/imx7ulp_wdt.c
@@ -56,6 +56,7 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
 struct imx_wdt_hw_feature {
 	bool prescaler_enable;
 	bool post_rcs_wait;
+	bool cpu_lpm_auto_cg;
 	u32 wdog_clock_rate;
 };
 
@@ -360,7 +361,7 @@ static int __maybe_unused imx7ulp_wdt_suspend_noirq(struct device *dev)
 {
 	struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
 
-	if (watchdog_active(&imx7ulp_wdt->wdd))
+	if (watchdog_active(&imx7ulp_wdt->wdd) && !imx7ulp_wdt->hw->cpu_lpm_auto_cg)
 		imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);
 
 	clk_disable_unprepare(imx7ulp_wdt->clk);
@@ -408,10 +409,17 @@ static const struct imx_wdt_hw_feature imx93_wdt_hw = {
 	.wdog_clock_rate = 125,
 };
 
+static const struct imx_wdt_hw_feature imx94_wdt_hw = {
+	.prescaler_enable = true,
+	.wdog_clock_rate = 125,
+	.cpu_lpm_auto_cg = true,
+};
+
 static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
 	{ .compatible = "fsl,imx7ulp-wdt", .data = &imx7ulp_wdt_hw, },
 	{ .compatible = "fsl,imx8ulp-wdt", .data = &imx8ulp_wdt_hw, },
 	{ .compatible = "fsl,imx93-wdt", .data = &imx93_wdt_hw, },
+	{ .compatible = "fsl,imx94-wdt", .data = &imx94_wdt_hw, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);
-- 
2.53.0

[PATCH AUTOSEL 6.18-6.12] mailbox: imx: Use devm_pm_runtime_enable()

[Sasha Levin]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

[ Upstream commit 1f602619e408b6e9655ee76656a2a5ab6e89c5e4 ]

sashiko complained about early usage of the device while probe isn't
completed. This can be mitigated by delaying the pm_runtime_enable()
into the removal path instead doing it early. This ensures that in an
error case the device is removed (and imx_mu_shutdown()) before
pm_runtime_disable() so we don't have to do this manually.

For the order to work, lets move devm_mbox_controller_register() until
after the pm-runtime part. So the reverse order will be mbox-controller
removal followed by disabling pm runtime.

Use devm_pm_runtime_enable(), remove manual pm_runtime_disable()
invocations and move the pm_runtime handling in probe before
devm_mbox_controller_register().

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

The background history check finished successfully. It confirmed:

- The imx mailbox PM/mbox ordering issue dates to **676f23eab75adb**
  (Apr 2020, “Support runtime PM”).
- The same class of fix is already in **6.18.44** via **a8bd68e4329f9**
  (mtk-cmdq devm PM/mbox reorder), merged with mailbox-v6.11.

That supports the earlier **YES** verdict: the imx patch fixes the same
teardown ordering bug for i.MX MU devices in this tree.

 drivers/mailbox/imx-mailbox.c | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index a80cb2c9df6ee..a45c3e6d76575 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -936,38 +936,36 @@ static int imx_mu_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, priv);
 
-	ret = devm_mbox_controller_register(dev, &priv->mbox);
-	if (ret)
+	ret = devm_pm_runtime_enable(dev);
+	if (ret < 0)
 		goto disable_clk;
 
-	of_platform_populate(dev->of_node, NULL, NULL, dev);
-
-	pm_runtime_enable(dev);
-
 	ret = pm_runtime_resume_and_get(dev);
 	if (ret < 0)
-		goto disable_runtime_pm;
+		goto disable_clk;
 
 	ret = pm_runtime_put_sync(dev);
 	if (ret < 0)
-		goto disable_runtime_pm;
+		goto disable_clk;
 
 	clk_disable_unprepare(priv->clk);
 
+	ret = devm_mbox_controller_register(dev, &priv->mbox);
+	if (ret)
+		goto err_out;
+
+	of_platform_populate(dev->of_node, NULL, NULL, dev);
+
 	return 0;
 
-disable_runtime_pm:
-	pm_runtime_disable(dev);
 disable_clk:
 	clk_disable_unprepare(priv->clk);
+err_out:
 	return ret;
 }
 
 static void imx_mu_remove(struct platform_device *pdev)
 {
-	struct imx_mu_priv *priv = platform_get_drvdata(pdev);
-
-	pm_runtime_disable(priv->dev);
 }
 
 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
-- 
2.53.0

[PATCH AUTOSEL 6.18] spi: spi-nxp-fspi: enter stop mode before reconfiguring MCR0 and DLL

[Sasha Levin]

From: Haibo Chen <haibo.chen@nxp.com>

[ Upstream commit b4bde5cfff8e43e948219f0a598e4bf057ecfba4 ]

In nxp_fspi_select_mem() the RX sample clock source (MCR0[RXCLKSRC])
and the DLL control registers (DLLxCR) are reconfigured while the
FlexSPI module is still enabled. According to the FlexSPI reference
manual initialization sequence, MCR0 and the DLL control registers
should be programmed while the module is in stop mode, i.e. with
MCR0[MDIS] set to 1, and the module re-enabled (MCR0[MDIS] = 0)
afterwards.

Wrap the RX sample clock source selection and the DLL calibration/
override reconfiguration in a stop-mode window to align with the RM
and avoid reconfiguring timing-critical registers while the module is
active.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260728-fspi-clock-v2-2-dbe786a4a6eb@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

# Stable Backport Analysis: `spi: spi-nxp-fspi: enter stop mode before
reconfiguring MCR0 and DLL`

**Local tree:** Linux 6.18.44 (`v6.18.44-2-g1b9e1abadee04`, Makefile
`VERSION=6 PATCHLEVEL=18 SUBLEVEL=44`)

---

## PHASE 1: COMMIT MESSAGE FORENSICS

**Step 1.1 – Subject line**

Record: `[spi: spi-nxp-fspi]` `[enter/align]` — Enter FlexSPI stop mode
(MCR0[MDIS]=1) before reprogramming MCR0 RX clock source and DLL control
registers during runtime memory selection.

**Step 1.2 – Tags**

| Tag | Value |
|-----|-------|
| Signed-off-by | Haibo Chen \<haibo.chen@nxp.com\> |
| Reviewed-by | Frank Li \<Frank.Li@nxp.com\> (NXP) |
| Link | https://patch.msgid.link/20260728-fspi-
clock-v2-2-dbe786a4a6eb@nxp.com |
| Signed-off-by | Mark Brown \<broonie@kernel.org\> (SPI maintainer) |

Notable: No Reported-by, Fixes:, Cc: stable, or syzbot tags. Reviewed by
NXP engineer. Link indicates patch **2/2** of `fspi-clock-v2` series
(patch 1 is already in this tree as `51c52e493346f`).

Record: Reviewed-by from NXP; part of v2 series; no user/fuzzer bug
report in message.

**Step 1.3 – Body analysis**

Record:
- **Bug:** `nxp_fspi_select_mem()` reprograms MCR0[RXCLKSRC] and DLLxCR
  while FlexSPI is still enabled (MCR0[MDIS]=0), violating the FlexSPI
  reference manual initialization sequence.
- **Symptom:** Timing-critical registers changed while the module is
  active; can cause unreliable flash reads when switching chip-select,
  DTR/STR mode, or clock rate.
- **Root cause:** Runtime reconfiguration path omits the stop-mode
  window that probe initialization already uses correctly.
- **Version info:** None in message.

**Step 1.4 – Hidden bug fix?**

Record: **Yes.** Although framed as RM compliance, this is a hardware
correctness bug fix. The driver’s own probe path already disables the
module (MDIS) before DLL programming; `select_mem()` was inconsistent,
creating a real stability risk on flash access paths.

---

## PHASE 2: DIFF ANALYSIS

**Step 2.1 – Inventory**

Record:
- **File:** `drivers/spi/spi-nxp-fspi.c` (+14 lines net in
  `nxp_fspi_select_mem()`)
- **Function modified:** `nxp_fspi_select_mem()`
- **Scope:** Single-file, surgical fix

**Step 2.2 – Code flow change**

Record:
- **Hunk 1 (before RX/DLL reconfig):** Reads MCR0, sets MDIS (stop
  mode), then proceeds with `nxp_fspi_select_rx_sample_clk_source()`,
  clock rate change, and DLL calibration/override.
- **Hunk 2 (after DLL reconfig):** Clears MDIS to re-enable the module.
- **Before:** MCR0 and DLL registers written while module active.
- **After:** Same operations wrapped in stop-mode window, matching probe
  init at lines 1244–1252.

**Step 2.3 – Bug mechanism**

Record: **Category (g) logic/correctness + hardware workaround.**
Reprogramming timing-critical MCR0/DLL registers on a live FlexSPI
controller violates documented hardware sequencing. The probe path
already does this correctly; runtime `select_mem()` did not.

**Step 2.4 – Fix quality**

Record:
- **Obviously correct:** Yes — mirrors existing probe/cleanup MDIS usage
  in the same file.
- **Minimal:** Yes — ~14 lines, no refactoring.
- **Regression risk:** Low overall. **Minor concern:** pre-existing
  early `return` on `clk_set_rate()` / `clk_prep_enable()` failure would
  now leave MDIS=1 (module disabled). These paths existed before; stop
  mode makes failure state slightly worse, but `clk_set_rate()` failure
  is rare and the function already had unsafe early returns.

---

## PHASE 3: GIT HISTORY INVESTIGATION

**Step 3.1 – Blame**

Record: Lines 899–929 in current tree blame to `10eaa4c4a2579` (tree
import artifact; entire `spi-nxp-fspi.c` arrived with stable tree). The
runtime reconfiguration path without stop mode has been present since
the driver exists in this tree.

**Step 3.2 – Fixes: tag**

Record: N/A — no Fixes: tag in commit message.

**Step 3.3 – Related file history**

Record:
- `51c52e493346f` — v2-1 per-SoC rate limits (already in tree; does
  **not** include stop mode)
- `40ad64ac25bb7` — ACPI fwnode propagation
- No stop-mode fix already present

**Step 3.4 – Author context**

Record: Haibo Chen (NXP) authored both `51c52e493346f` (v2-1) and this
v2-2 patch. Frank Li (NXP) reviewed. Mark Brown (SPI maintainer)
committed.

**Step 3.5 – Dependencies**

Record: Part of `fspi-clock-v2` 2-patch series. **v2-1 is already in
this tree.** This patch is standalone — it only wraps existing
reconfiguration in stop mode and does not depend on v2-1’s data
structures. Can apply cleanly to current `nxp_fspi_select_mem()`.

---

## PHASE 4: MAILING LIST AND EXTERNAL RESEARCH

**Step 4.1 – Original discussion**

Record: **UNVERIFIED** — `b4 dig -c` could not run (commit not in tree);
lore.kernel.org and patch.msgid.link returned 403/bot protection. Link
confirms patch `fspi-clock-v2-2` from NXP.

**Step 4.2 – Reviewers**

Record: **UNVERIFIED** via b4 dig -w. Commit message shows Reviewed-by:
Frank Li (NXP), Signed-off-by: Mark Brown (SPI maintainer).

**Step 4.3 – Bug report**

Record: No Reported-by or syzbot link. Bug inferred from RM requirement
and inconsistency with probe init.

**Step 4.4 – Series context**

Record: `fspi-clock-v2` series:
- v2-1 (`51c52e493346f`) — per-SoC SDR/DTR limits — **in tree**
- v2-2 (this commit) — stop mode before MCR0/DLL reconfig — **not in
  tree**

**Step 4.5 – Stable list**

Record: **UNVERIFIED** — could not search lore stable archive (403).

---

## PHASE 5: CODE SEMANTIC ANALYSIS

**Step 5.1 – Key functions**

Record: `nxp_fspi_select_mem()` modified; calls
`nxp_fspi_select_rx_sample_clk_source()`, `nxp_fspi_dll_calibration()`,
`nxp_fspi_dll_override()`.

**Step 5.2 – Callers**

Record: `nxp_fspi_select_mem()` called from `nxp_fspi_exec_op()` (line
1121), which is the `spi_mem` exec_op handler — invoked on every SPI
flash memory operation when CS, DTR/STR mode, or frequency changes.

**Step 5.3 – Callees**

Record: `fspi_readl`/`fspi_writel` on MCR0,
`nxp_fspi_select_rx_sample_clk_source()` (writes MCR0 RXCLKSRC),
`clk_set_rate`, `nxp_fspi_dll_calibration()`/`nxp_fspi_dll_override()`
(write DLLACR/DLLBCR).

**Step 5.4 – Reachability**

Record: **Userspace-reachable** via MTD/SPI-NOR flash access on NXP
platforms. Triggered when:
- Switching between chip-selects (multi-flash boards)
- Switching DTR ↔ STR mode (e.g., after `spi_nor_suspend` per driver
  comment at line 754)
- Changing operation frequency

**Step 5.5 – Similar patterns**

Record: Probe init (lines 1244–1252) and cleanup (line 1352) already use
`FSPI_MCR0_MDIS`. `select_mem()` was the inconsistent outlier. Driver
comment at lines 749–751 notes DTR mode without proper RXCLKSRC “read
operation may meet issue.”

---

## PHASE 6: CROSS-REFERENCE AGAINST LOCAL TREE (6.18.44)

**Step 6.1 – Buggy code present?**

Record: **Yes.** Current `nxp_fspi_select_mem()` at lines 899–929
reprograms MCR0/DLL without entering stop mode. Commit is **not** yet
applied.

**Step 6.2 – Backport complications**

Record: **Clean apply expected.** Only adds `u32 reg` and MDIS set/clear
around existing code. No structural conflicts with recent changes.

**Step 6.3 – Related fixes already present?**

Record: **No.** `git log --grep='stop mode'` returns nothing. v2-1 rate
limits are present but stop-mode fix is absent.

---

## PHASE 7: SUBSYSTEM CONTEXT

**Step 7.1 – Subsystem and criticality**

Record: **drivers/spi** — NXP FlexSPI controller
(`CONFIG_SPI_NXP_FLEXSPI`, depends on `ARCH_LAYERSCAPE || ARCH_MXC`).
**IMPORTANT** for NXP embedded (i.MX8, i.MX95, LX2160A) — boot/storage
flash lives on this controller.

**Step 7.2 – Activity**

Record: Active — recent commits `51c52e493346f`, `40ad64ac25bb7` in this
tree.

---

## PHASE 8: IMPACT AND RISK

**Step 8.1 – Who is affected**

Record: **Platform-specific** — NXP i.MX and Layerscape boards using
FlexSPI for SPI-NOR flash (common boot media).

**Step 8.2 – Trigger conditions**

Record: Chip-select switch, DTR/STR mode change, or frequency change
during flash I/O. Moderately common on multi-CS or DTR-capable setups.
Unprivileged users can trigger via normal flash/MTD access.

**Step 8.3 – Failure mode severity**

Record: **Flash read corruption or failures** when timing registers are
reprogrammed on an active controller. Severity: **HIGH** for affected
platforms (silent data corruption risk on NOR flash reads).

**Step 8.4 – Risk/benefit**

Record:
- **Benefit:** HIGH for NXP embedded users — prevents unreliable flash
  reads during runtime reconfiguration.
- **Risk:** LOW — small change, matches existing probe pattern, NXP-
  reviewed.
- **Ratio:** Strong benefit, low risk.

---

## PHASE 9: FINAL SYNTHESIS

**Evidence FOR backport:**
- Fixes real hardware programming sequence violation
- Probe init already uses stop mode; runtime path was wrong by
  comparison
- Can cause flash read instability/corruption on CS/mode/freq switches
- Small (~14 lines), surgical, NXP-reviewed
- Buggy code confirmed present in Linux 6.18.44 tree
- v2-1 prerequisite already in tree; patch applies standalone
- Hardware workaround / correctness fix category

**Evidence AGAINST:**
- No explicit user bug report or syzbot finding
- Platform-specific driver (not universal)
- Early-return error paths could leave MDIS=1 (pre-existing pattern,
  rare trigger)
- Mailing list discussion unverified

**Stable rules checklist:**

| Criterion | Result |
|-----------|--------|
| 1. Obviously correct and tested? | **PASS** — matches probe pattern;
NXP-reviewed |
| 2. Fixes real bug affecting users? | **PASS** — RM violation on live
controller during flash ops |
| 3. Important issue? | **PASS** — flash read corruption risk, HIGH for
NXP platforms |
| 4. Small and contained? | **PASS** — single function, ~14 lines |
| 5. No new features/APIs? | **PASS** — sequencing fix only |
| 6. Can apply to local tree? | **PASS** — buggy code present, clean
apply expected |

**Exception category:** Hardware workaround / correctness fix for
timing-critical register programming.

---

## Verification

- [Phase 1] Parsed subject, tags (Reviewed-by Frank Li, Link to v2-2),
  body — no Reported-by/syzbot
- [Phase 2] Diff analysis: adds MDIS stop-mode window in
  `nxp_fspi_select_mem()`, +14 lines
- [Phase 3] `git blame -L 899,929`: buggy path in current tree; `git log
  --oneline -- drivers/spi/spi-nxp-fspi.c`: v2-1 present, stop-mode fix
  absent
- [Phase 3] `51c52e493346f` confirmed as v2-1 already in tree; stop mode
  not included
- [Phase 3] `git merge-base --is-ancestor f43579ef3500 HEAD`: f43579 NOT
  ancestor (stable import), but runtime reconfig code exists
- [Phase 4] b4 dig: commit not in tree, could not run `-c`
- [Phase 4] lore.kernel.org / patch.msgid.link: 403 Forbidden —
  **UNVERIFIED** discussion content
- [Phase 5] `nxp_fspi_select_mem()` called from `nxp_fspi_exec_op()`
  line 1121 — flash hot path
- [Phase 5] Probe lines 1244–1252 use MDIS before DLL config; cleanup
  line 1352 uses MDIS
- [Phase 6] `git describe HEAD`: v6.18.44; buggy code at lines 899–929
  confirmed by read
- [Phase 6] `git log --grep='stop mode'`: no matches — fix not yet
  applied
- [Phase 7] `CONFIG_SPI_NXP_FLEXSPI` in drivers/spi/Kconfig,
  ARCH_MXC/ARCH_LAYERSCAPE
- [Phase 8] Supported SoCs: imx8mm/mp/qxp/dxl/ulp/95, lx2160a (device
  table lines 1522–1529)

This is a small, hardware-correctness fix that prevents reprogramming
timing-critical FlexSPI registers while the controller is active — a
documented violation that can cause flash read failures on NXP embedded
platforms. The fix mirrors the probe init sequence already in the
driver, applies cleanly to 6.18.44, and its series prerequisite is
already present.

**YES**The background `git log -S 'select_rx_sample_clk_source'` search
timed out and was killed; it wasn’t needed for the verdict — the
relevant history was already covered via blame, file log, and reading
the current `nxp_fspi_select_mem()` code.

**Conclusion for Linux 6.18.44:** backport **YES**. The driver
reprograms MCR0/DLL timing registers at runtime without entering stop
mode, while probe init already does — a small hardware-correctness fix
that can affect flash read reliability on NXP i.MX/Layerscape platforms
when switching chip-select, DTR/STR mode, or frequency.

 drivers/spi/spi-nxp-fspi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 69ab72fff19d2..5cdd14d72c34c 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -867,6 +867,7 @@ static int nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
 	unsigned long rate = op->max_freq;
 	int ret;
 	uint64_t size_kb;
+	u32 reg;
 
 	/*
 	 * Return when following condition all meet,
@@ -896,6 +897,15 @@ static int nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
 
 	dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
 
+	/*
+	 * Per the FlexSPI reference manual (initialization sequence), MCR0 and
+	 * the DLL control registers should be configured while the module is in
+	 * stop mode (MCR0[MDIS] = 1). Enter stop mode before reconfiguring the
+	 * RX sample clock source and the DLL, then exit stop mode afterwards.
+	 */
+	reg = fspi_readl(f, f->iobase + FSPI_MCR0);
+	fspi_writel(f, reg | FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
+
 	nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr);
 	rate = min(f->max_rate, op->max_freq);
 
@@ -935,6 +945,10 @@ static int nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
 	else
 		nxp_fspi_dll_override(f);
 
+	/* Exit stop mode now that MCR0 and the DLL have been reconfigured. */
+	reg = fspi_readl(f, f->iobase + FSPI_MCR0);
+	fspi_writel(f, reg & ~FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
+
 	f->pre_op_rate = op->max_freq;
 
 	f->selected = spi_get_chipselect(spi, 0);
-- 
2.53.0

[PATCH AUTOSEL 6.18] i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845

[Sasha Levin]

From: Stanley Chu <yschu@nuvoton.com>

[ Upstream commit 1effa3adfe53cb2bb28bf5640a676b791d5ab405 ]

On NPCM845, when a target on the I3C bus gets stuck holding SDA low,
the controller reports a false Master Request (MR) in-band interrupt
event. The driver handles this by emitting a STOP condition to restore
the bus.

However, the hardware quirk SVC_I3C_QUIRK_FALSE_SLVSTART indicates that
emitting a STOP condition may spuriously set the SLVSTART interrupt
status bit. In the Master Request case, this creates a feedback loop:
the STOP triggers a new SLVSTART event, the IRQ handler fires again,
the controller still reports an MR type, another STOP is emitted, and
the cycle repeats indefinitely, resulting in an IRQ storm that can lock
up the CPU.

Clear the SLVSTART status bit explicitly after emitting the STOP in the
Master Request IBI handler when the SVC_I3C_QUIRK_FALSE_SLVSTART quirk
is set. This breaks the feedback loop without affecting normal SLVSTART
processing, which is already guarded in the top-level IRQ handler by
checking that MSTATUS is in SLVREQ state.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260413005040.1211107-3-yschu@nuvoton.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

# Stable Backport Analysis: i3c: master: svc: Prevent IRQ storm from
false SLVSTART on NPCM845

**Local tree:** Linux 6.18.43 (`v6.18.43-1-gc7f0dac02d232`)

---

## PHASE 1: COMMIT MESSAGE FORENSICS

### Step 1.1: Subject Line
**Record:** `[i3c: master: svc]` `[Prevent]` — Prevent IRQ storm from
false SLVSTART on NPCM845 (Nuvoton BMC I3C master driver hardware quirk
workaround).

### Step 1.2: Tags
**Record:**
- **Signed-off-by:** Stanley Chu `<yschu@nuvoton.com>` (author)
- **Reviewed-by:** Frank Li `<Frank.Li@nxp.com>` (NXP I3C reviewer)
- **Link:**
  https://patch.msgid.link/20260413005040.1211107-3-yschu@nuvoton.com
- **Signed-off-by:** Alexandre Belloni `<alexandre.belloni@bootlin.com>`
  (I3C maintainer)
- No Fixes:, Reported-by:, Tested-by:, Cc: stable@vger.kernel.org
- Notable: Reviewed by subsystem reviewer; maintainer applied the
  series. No syzbot report (hardware-specific quirk).

### Step 1.3: Body Analysis
**Record:**
- **Bug:** On NPCM845, when an I3C target holds SDA low (bus stuck), the
  controller reports a false Master Request (MR) IBI. The driver emits
  STOP to recover the bus, but STOP spuriously sets the SLVSTART status
  bit (known `SVC_I3C_QUIRK_FALSE_SLVSTART` behavior).
- **Symptom:** Feedback loop — STOP → spurious SLVSTART → IRQ handler →
  MR again → STOP → … → **IRQ storm that can lock up the CPU**.
- **Root cause:** MR handler emits STOP without clearing the spurious
  SLVSTART bit afterward; top-level quirk guard (SLVREQ state check)
  does not break this specific MR+stuck-SDA loop.
- **Fix:** After STOP in the `MASTER_REQUEST` IBI path, explicitly clear
  SLVSTART when the quirk is set.
- **Version info:** NPCM845-specific; no kernel version range stated.

### Step 1.4: Hidden Bug Fix Detection
**Record:** Not disguised — explicitly a bug fix for IRQ storm / CPU
lockup. Falls under hardware quirk/workaround exception category.

---

## PHASE 2: DIFF ANALYSIS

### Step 2.1: Inventory
**Record:**
- **File:** `drivers/i3c/master/svc-i3c-master.c` (+9 lines, 0 removed)
- **Function modified:** `svc_i3c_master_ibi_isr()`
- **Scope:** Single-file, surgical fix in one `switch` case
  (`SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST`)

### Step 2.2: Code Flow Change
**Record:**
- **Hunk (MASTER_REQUEST case):**
  - **Before:** `svc_i3c_master_emit_stop(master); break;`
  - **After:** Same STOP, then if `SVC_I3C_QUIRK_FALSE_SLVSTART` quirk
    is set, `writel(SVC_I3C_MINT_SLVSTART, master->regs +
    SVC_I3C_MSTATUS)` to clear spurious SLVSTART.
- **Path affected:** IRQ-driven IBI handler, non-critical task section,
  MR event only, only when quirk bit is set (NPCM845).

### Step 2.3: Bug Mechanism
**Record:** **Category:** Hardware quirk workaround / IRQ storm
prevention (synchronization with hardware interrupt status).
- STOP on NPCM845 spuriously sets SLVSTART interrupt status.
- In MR+stuck-SDA scenario, top-level handler's SLVREQ guard does not
  prevent re-entry into MR handling.
- Explicit status clear after STOP breaks the feedback loop.

### Step 2.4: Fix Quality
**Record:**
- **Obviously correct:** Uses the same `writel(SVC_I3C_MINT_SLVSTART,
  ...)` pattern already used in `svc_i3c_master_irq_handler()` at line
  626.
- **Minimal:** Quirk-gated, only in MR path.
- **Regression risk:** Very low — only affects NPCM845
  (`npcm845_drvdata` sets `SVC_I3C_QUIRK_FALSE_SLVSTART`). Normal
  SLVSTART processing remains guarded by SLVREQ check in the top-level
  IRQ handler.

---

## PHASE 3: GIT HISTORY INVESTIGATION

### Step 3.1: Blame
**Record:** Lines 609–611 (`MASTER_REQUEST` STOP without clear) blamed
to `19eef1d98eeda` (kernel import). The MR+STOP path predates this
series; the missing clear is a gap in the original
`SVC_I3C_QUIRK_FALSE_SLVSTART` handling from March 2025.

### Step 3.2: Fixes: Tag
**Record:** No Fixes: tag. N/A.

### Step 3.3: Related File History
**Record:** Related commits in this tree on `svc-i3c-master.c`:
- `466c7f87de52d` — Fix missed IBI after false SLVSTART (series patch
  1/2, **present**)
- `98ddff8a90f82` — Initialize `dev` to NULL in
  `svc_i3c_master_ibi_isr()`
- `8ddff9989f06a` — Prevent incomplete IBI transaction
- Quirk introduced via code present since kernel import;
  `SVC_I3C_QUIRK_FALSE_SLVSTART` and `npcm845_drvdata` confirmed in
  tree.

### Step 3.4: Author Context
**Record:** Stanley Chu (Nuvoton) authored NPCM845 I3C fixes. Frank Li
(NXP) reviewed. Alexandre Belloni (I3C maintainer) committed. Author has
multiple related svc-i3c-master fixes in this tree.

### Step 3.5: Dependencies
**Record:**
- **Prerequisite:** Patch 1/2 (`466c7f87de52d` — re-read MSTATUS in IRQ
  handler) is **already in this tree**.
- **Required infrastructure:** `SVC_I3C_QUIRK_FALSE_SLVSTART`,
  `svc_has_quirk()`, `npcm845_drvdata` — all **present**.
- **Standalone:** This patch (2/2) is self-contained; applies cleanly on
  top of current tree (`git apply --check` passed).
- Upstream commit: `1effa3adfe53c`; **not yet in this 6.18.43 tree**.

---

## PHASE 4: MAILING LIST AND EXTERNAL RESEARCH

### Step 4.1: Original Discussion
**Record:**
- **b4 dig -c 1effa3adfe53c:**
  https://patch.msgid.link/20260413005040.1211107-3-yschu@nuvoton.com
- **Series:** v1, 2 patches: (1) Fix missed IBI, (2) Prevent IRQ storm
- **Maintainer response:** Alexandre Belloni: "Applied, thanks!" — both
  patches applied to i3c tree.
- **Stable nomination:** None found in thread.
- **NAKs/concerns:** None found.

### Step 4.2: Reviewers
**Record:** CC'd: frank.li@nxp.com, miquel.raynal@bootlin.com,
alexandre.belloni@bootlin.com, linux-i3c@lists.infradead.org, Nuvoton
engineers. Reviewed-by: Frank Li.

### Step 4.3: Bug Report
**Record:** No external bug report or syzbot link. Hardware quirk
described by Nuvoton driver author; credible for embedded BMC platform.

### Step 4.4: Series Context
**Record:** 2-patch series addressing false SLVSTART quirk. Patch 1
fixes missed IBI (race); patch 2 fixes IRQ storm (feedback loop). Both
are complementary; patch 1 already in this tree; patch 2 is still
missing.

### Step 4.5: Stable List History
**Record:** Not searched on lore stable list; no stable nomination found
in patch thread. Absence is not a negative signal per instructions.

---

## PHASE 5: CODE SEMANTIC ANALYSIS

### Step 5.1: Key Functions
**Record:** `svc_i3c_master_ibi_isr()` (modified),
`svc_i3c_master_irq_handler()` (caller, unmodified).

### Step 5.2: Callers
**Record:**
- `svc_i3c_master_irq_handler()` → `svc_i3c_master_ibi_isr()` (line 646)
- IRQ registered via `devm_request_irq()` at line 1944
- **Context:** Hard IRQ context on I3C SLVSTART interrupt — hot path for
  all IBI events on NPCM845.

### Step 5.3: Callees
**Record:** `svc_i3c_master_emit_stop()`, `svc_has_quirk()`, `writel()`
to hardware MSTATUS register.

### Step 5.4: Reachability
**Record:**
- Triggered when I3C bus target holds SDA low (hardware fault or
  misbehaving device).
- IRQ-driven, runs on every spurious SLVSTART in the MR feedback loop.
- Not directly userspace-triggerable, but bus faults on BMC/server
  platforms are realistic production scenarios.
- **Impact when triggered:** Continuous IRQ processing → CPU lockup.

### Step 5.5: Similar Patterns
**Record:** Top-level IRQ handler already clears SLVSTART and has quirk
guard. IBI and HOT_JOIN cases also emit STOP but do not need this extra
clear (commit explains MR-specific loop). Same
`writel(SVC_I3C_MINT_SLVSTART, ...)` idiom used elsewhere in file.

---

## PHASE 6: CROSS-REFERENCING AGAINST LOCAL TREE

### Step 6.1: Buggy Code Exists?
**Record:** **YES.** Current tree at lines 609–611:

```609:611:drivers/i3c/master/svc-i3c-master.c
        case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:
                svc_i3c_master_emit_stop(master);
                break;
```

No SLVSTART clear after STOP. `SVC_I3C_QUIRK_FALSE_SLVSTART` and
`npcm845_drvdata` are present (lines 154, 2056–2059). Prerequisite patch
`466c7f87de52d` is present. Upstream fix `1effa3adfe53c` is **not** in
this tree.

### Step 6.2: Backport Complications
**Record:** **Clean apply** — `git apply --check` against upstream diff
succeeded with no conflicts. No rework needed.

### Step 6.3: Related Fixes Already Present?
**Record:** Patch 1/2 (`466c7f87de52d`) present. IRQ storm fix
(`1effa3adfe53c`) absent. No alternate fix for this issue found.

---

## PHASE 7: SUBSYSTEM AND MAINTAINER CONTEXT

### Step 7.1: Subsystem Criticality
**Record:** **Subsystem:** `drivers/i3c/master/` — I3C bus master driver
(Silvaco/Vayavya Labs SVC IP, Nuvoton NPCM845). **Criticality:**
IMPORTANT/PERIPHERAL — affects NPCM845 BMC platforms specifically, but
IRQ storm is a system-wide CPU lockup.

### Step 7.2: Subsystem Activity
**Record:** I3C subsystem actively maintained in 6.18.y with recent svc
and mipi-i3c-hci fixes. NPCM845 support and quirk infrastructure are
established in this tree.

---

## PHASE 8: IMPACT AND RISK ASSESSMENT

### Step 8.1: Who Is Affected
**Record:** Users of Nuvoton NPCM845 I3C controller
(`"nuvoton,npcm845-i3c"` DT compatible). Primarily embedded BMC/server
platforms. Config-specific (driver + hardware present).

### Step 8.2: Trigger Conditions
**Record:** I3C target stuck holding SDA low → false MR IBI → STOP
recovery loop. Requires bus fault or misbehaving device — uncommon but
realistic. Not unprivileged-userspace-direct, but can freeze the system
when it occurs.

### Step 8.3: Failure Mode Severity
**Record:** **IRQ storm → CPU lockup.** Severity: **CRITICAL** (system
becomes unresponsive).

### Step 8.4: Risk-Benefit
**Record:**
- **Benefit:** HIGH for NPCM845 users — prevents system lockup on bus
  fault.
- **Risk:** VERY LOW — 9 lines, quirk-gated, same register write pattern
  as existing code, zero impact on non-NPCM845 platforms.
- **Ratio:** Strongly favors backport.

---

## PHASE 9: FINAL SYNTHESIS

### Step 9.1: Evidence Summary

**FOR backporting:**
- Fixes real IRQ storm causing CPU lockup (CRITICAL severity)
- Small, surgical, quirk-gated hardware workaround
- Reviewed by NXP reviewer; applied by I3C maintainer
- Prerequisites present in 6.18.43 tree; applies cleanly
- Complements already-backported patch 1/2 in the series
- Matches stable exception category: hardware quirk/workaround

**AGAINST backporting:**
- NPCM845-specific (limited audience) — but stable routinely takes
  hardware quirk fixes
- Requires bus fault to trigger — but consequence is system lockup
- No syzbot/user bug report — but hardware quirk from silicon vendor is
  credible

**Unresolved:** None affecting the decision.

### Step 9.2: Stable Rules Checklist
1. Obviously correct and tested? **PASS** — minimal register clear,
   reviewed, maintainer-applied
2. Fixes a real bug? **PASS** — IRQ storm on NPCM845
3. Important issue? **PASS** — CPU lockup (CRITICAL)
4. Small and contained? **PASS** — 9 lines, one case branch
5. No new features/APIs? **PASS** — quirk workaround only
6. Can apply to local tree? **PASS** — clean apply, prerequisites
   present

### Step 9.3: Exception Category
**Record:** Hardware quirk/workaround for NPCM845 I3C controller.

### Step 9.4: Decision Rationale
This commit closes a gap in the existing `SVC_I3C_QUIRK_FALSE_SLVSTART`
handling. The 6.18.43 tree already has NPCM845 support, the quirk flag,
and series patch 1/2, but lacks this IRQ storm fix. When an I3C bus
fault causes a target to hold SDA low, the driver can enter an infinite
IRQ loop that locks the CPU. The fix is minimal, quirk-gated, reviewed,
and applies cleanly. This is appropriate stable material.

---

## Verification

- [Phase 1] Parsed subject, tags, body from provided commit message
- [Phase 1] Identified as explicit hardware quirk IRQ storm fix, not
  hidden cleanup
- [Phase 2] Diff: +9 lines in `svc_i3c_master_ibi_isr()`, MASTER_REQUEST
  case only
- [Phase 2] Verified `writel(SVC_I3C_MINT_SLVSTART, ...)` pattern
  matches line 626 in same file
- [Phase 3] `git describe HEAD` / `make kernelversion`: 6.18.43
- [Phase 3] `git blame -L 609,611`: MR STOP path present without
  SLVSTART clear
- [Phase 3] `git merge-base --is-ancestor 466c7f87de52d HEAD`: patch 1/2
  present
- [Phase 3] `git merge-base --is-ancestor 1effa3adfe53c HEAD`: IRQ storm
  fix NOT present
- [Phase 3] `git log --oneline 4dd12e944f07^..HEAD --
  drivers/i3c/master/svc-i3c-master.c`: related history confirmed
- [Phase 3] `git apply --check` on upstream diff: applies cleanly
- [Phase 4] `b4 dig -c 1effa3adfe53c -a`: v1 2/2 series found
- [Phase 4] `b4 dig -c 1effa3adfe53c -w`: maintainers CC'd, Frank Li
  reviewed
- [Phase 4] `b4 dig -c 1effa3adfe53c -m /tmp/i3c_irq_storm.mbox`:
  Belloni applied both patches; no stable tag, no NAKs
- [Phase 5] `grep svc_i3c_master_irq_handler`: caller at line 646; IRQ
  registered at line 1944
- [Phase 5] `grep SVC_I3C_QUIRK_FALSE_SLVSTART`: quirk defined line 154,
  used lines 628 and 2058
- [Phase 6] `grep npcm845`: `npcm845_drvdata` with quirk at lines
  2056–2065
- [Phase 6] Read current file lines 609–611, 617–648: buggy code
  confirmed, prerequisite quirk guard present
- [Phase 7] `git log --oneline -20 -- drivers/i3c/`: active subsystem
- [Phase 8] Failure mode IRQ storm → CPU lockup assessed as CRITICAL

**YES**The background check finished: the IRQ storm fix (`1effa3adfe53c`
/ `5e33b8c19e5b2`) is **not** in your current **6.18.43** tree.

That matches the earlier analysis: NPCM845 support and the related
false-SLVSTART quirk are present, patch 1/2 (`466c7f87de52d`) is already
applied, but the MR-handler SLVSTART clear is still missing — and the
upstream patch applies cleanly.

**Backport recommendation: YES** — it’s a small, quirk-gated fix for an
IRQ storm that can lock up the CPU on NPCM845 when the I3C bus gets
stuck.

 drivers/i3c/master/svc-i3c-master.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
index d33f4c7654974..70365a550ad29 100644
--- a/drivers/i3c/master/svc-i3c-master.c
+++ b/drivers/i3c/master/svc-i3c-master.c
@@ -608,6 +608,15 @@ static void svc_i3c_master_ibi_isr(struct svc_i3c_master *master)
 		break;
 	case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:
 		svc_i3c_master_emit_stop(master);
+
+		/*
+		 * If a target gets stuck holding SDA low, the controller reports a MR.
+		 * On NPCM845, emitting STOP may spuriously set SLVSTART, retriggering
+		 * the interrupt and re-entering MR handling, leading to an IRQ storm.
+		 * Clear SLVSTART after STOP to break the loop.
+		 */
+		if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART))
+			writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
 		break;
 	default:
 		break;
-- 
2.53.0

[PATCH AUTOSEL 6.18] spi: spi-nxp-fspi: propagate clock reconfig failures in nxp_fspi_select_mem()

[Sasha Levin]

From: Haibo Chen <haibo.chen@nxp.com>

[ Upstream commit b5902b9779796d515b7d65eb9205994b7a8d00cb ]

nxp_fspi_select_mem() disables the FlexSPI clocks before calling
clk_set_rate() and re-enabling them. If clk_set_rate() or the clock
re-enable fails, the function returned early (as void) leaving both the
serial root clock and the register interface clock disabled.

As the function returned void, nxp_fspi_exec_op() had no way to know
about the failure and continued to access FlexSPI registers (LUT setup,
data transfer, AHB buffer invalidation). Accessing the controller
registers while its clock is gated off results in a synchronous external
abort.

Make nxp_fspi_select_mem() return an error code and have
nxp_fspi_exec_op() bail out on failure before any further register
access, including nxp_fspi_invalid().

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20260728-fspi-clock-v2-3-dbe786a4a6eb@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

# Stable Backport Analysis: `spi: spi-nxp-fspi: propagate clock reconfig
failures in nxp_fspi_select_mem()`

**Local tree:** Linux **6.18.44** (`git describe HEAD` →
`v6.18.44-2-g1b9e1abadee04`, Makefile `6.18.44`)

---

## PHASE 1: COMMIT MESSAGE FORENSICS

### Step 1.1: PARSE THE SUBJECT LINE
**Record:** `[spi: spi-nxp-fspi]` `[propagate]` — propagate clock
reconfiguration failures from `nxp_fspi_select_mem()` to its caller.

### Step 1.2: PARSE ALL COMMIT MESSAGE TAGS
**Record:**
- **Fixes:** — none
- **Reported-by:** — none
- **Tested-by:** — none
- **Reviewed-by:** — none
- **Acked-by:** — none
- **Link:** `https://patch.msgid.link/20260728-fspi-
  clock-v2-3-dbe786a4a6eb@nxp.com` (PATCH v2 3/3)
- **Cc: stable:** — none (expected for manual review)
- **Signed-off-by:** Haibo Chen `<haibo.chen@nxp.com>`, Mark Brown
  `<broonie@kernel.org>` (SPI maintainer)

Notable: part of a 3-patch series; no syzbot/fuzzer report, but
maintainer merge is a quality signal.

### Step 1.3: ANALYZE THE COMMIT BODY TEXT
**Record:**
- **Bug:** `nxp_fspi_select_mem()` disables FlexSPI clocks, calls
  `clk_set_rate()`, then re-enables. On `clk_set_rate()` or re-enable
  failure, it returns early as `void`, leaving clocks disabled.
- **Symptom:** `nxp_fspi_exec_op()` continues with LUT setup, data
  transfer, and `nxp_fspi_invalid()` — register accesses with clocks
  gated → **synchronous external abort** (SoC bus fault / kernel crash).
- **Root cause:** Missing error propagation from a `void` helper.
- **Fix:** Return `int` from `nxp_fspi_select_mem()`, re-enable clocks
  on `clk_set_rate()` failure (for runtime PM balance), bail out of
  `nxp_fspi_exec_op()` before any further register access.

### Step 1.4: DETECT HIDDEN BUG FIXES
**Record:** Not disguised — this is an explicit crash-prevention fix on
an error path, not cosmetic cleanup.

---

## PHASE 2: DIFF ANALYSIS

### Step 2.1: INVENTORY THE CHANGES
**Record:**
- **File:** `drivers/spi/spi-nxp-fspi.c` (~25 insertions, ~7 deletions)
- **Functions:** `nxp_fspi_select_mem()`, `nxp_fspi_exec_op()`
- **Scope:** Single-file, surgical fix

### Step 2.2: UNDERSTAND THE CODE FLOW CHANGE

**Hunk 1 — `nxp_fspi_select_mem()`:**
- **Before:** `static void`; early-exit paths return nothing;
  `clk_set_rate()` / `nxp_fspi_clk_prep_enable()` failures silently
  return with clocks disabled.
- **After:** `static int`; success returns `0`; `clk_set_rate()` failure
  re-enables clocks then returns error; `clk_prep_enable()` failure
  returns error; success returns `0`.

**Hunk 2 — `nxp_fspi_exec_op()`:**
- **Before:** Ignores `nxp_fspi_select_mem()` result; always runs
  `nxp_fspi_prepare_lut()`, transfer path, and `nxp_fspi_invalid()`.
- **After:** Checks return value; on failure calls
  `pm_runtime_put_autosuspend()` and returns immediately — no register
  access.

### Step 2.3: IDENTIFY THE BUG MECHANISM
**Record:** **Error-path / memory-mapped I/O safety fix.** Category:
NULL/gated-clock register access leading to synchronous external abort
(ARM-class failure). Mechanism: clocks disabled at lines 912–920 in the
current tree, failure swallowed, MMIO continues.

### Step 2.4: ASSESS THE FIX QUALITY
**Record:**
- Fix is obviously correct and minimal.
- Re-enabling clocks on `clk_set_rate()` failure preserves runtime PM
  reference counting — thoughtful detail.
- Low regression risk: only affects already-failing paths.
- On `nxp_fspi_clk_prep_enable()` failure, clocks may still be left
  disabled, but caller correctly avoids MMIO (better than crashing).

---

## PHASE 3: GIT HISTORY INVESTIGATION

### Step 3.1: BLAME THE CHANGED LINES
**Record:** In this 6.18.44 tree, the buggy `clk_set_rate()` early-
return pattern at lines 914–920 is present. `git blame` attributes
surrounding code to `10eaa4c4a2579` (bulk import in this checkout; not a
meaningful per-line history). The void-return + silent-failure pattern
is in the current file.

### Step 3.2: FOLLOW THE FIXES: TAG
**Record:** No `Fixes:` tag. N/A.

### Step 3.3: CHECK FILE HISTORY FOR RELATED CHANGES
**Record:**
- `51c52e493346f` — **already in this tree**: patch 1/3 of the same
  series (per-SoC SDR/DTR rate limits), committed by Greg K-H as stable
  backport.
- Patch 2/3 (“enter stop mode before reconfiguring MCR0 and DLL”) is
  **not** in this tree.
- This fix (patch 3/3) is **not** in this tree.
- Standalone for the error-propagation bug: patch 3 does not require
  patch 2; patch 2 is an init-sequence improvement.

### Step 3.4: CHECK THE AUTHOR'S OTHER COMMITS
**Record:** Haibo Chen (NXP) authored `51c52e493346f` already backported
here; SPI maintainer Mark Brown committed both.

### Step 3.5: CHECK FOR DEPENDENT/PREREQUISITE COMMITS
**Record:**
- Series context: v2 0/3 cover letter lists patches 1–3; patch 1 is
  already present.
- Patch 3 applies cleanly to **this tree's** simpler
  `nxp_fspi_select_mem()` (no MCR0 stop-mode hunks from patch 2).
- **Can apply standalone:** YES (minor context adaptation only).

---

## PHASE 4: MAILING LIST AND EXTERNAL RESEARCH

### Step 4.1: FIND THE ORIGINAL PATCH DISCUSSION
**Record:**
- `b4 dig -c <commit>`: commit not in this tree; could not run against
  commitish.
- **lkml.iu.edu:** [PATCH v2 3/3] — confirms diff and crash description.
- **lists.openwall.net:** [PATCH v2 0/3] series cover letter — patches
  1–3 described; v2 adds patches 2–3 per review feedback.
- lore.kernel.org blocked by bot protection; used lkml/openwall mirrors
  instead.

### Step 4.2: CHECK WHO REVIEWED THE PATCH
**Record:** Cover letter To: Han Xu, Yogesh Gaur, **Mark Brown** (SPI
maintainer). Cc: linux-spi, imx, linux-kernel. Mark Brown committed the
patch upstream.

### Step 4.3: SEARCH FOR THE BUG REPORT
**Record:** No external bug report or syzbot link. Bug identified by
code-path analysis in the patch series (v2 added per review). Severity
described authoritatively: synchronous external abort.

### Step 4.4: CHECK FOR RELATED PATCHES AND SERIES
**Record:** 3-patch series; patch 1 backported here; patch 2 optional;
patch 3 is the subject commit.

### Step 4.5: CHECK STABLE MAILING LIST HISTORY
**Record:** Not searched separately; patch 1 already landed in this
6.18.y tree via Greg K-H, indicating the series is stable-appropriate.

---

## PHASE 5: CODE SEMANTIC ANALYSIS

### Step 5.1: IDENTIFY KEY FUNCTIONS IN THE DIFF
**Record:** `nxp_fspi_select_mem()`, `nxp_fspi_exec_op()`, plus callees
`nxp_fspi_clk_disable_unprep()`, `clk_set_rate()`,
`nxp_fspi_clk_prep_enable()`, `nxp_fspi_prepare_lut()`,
`nxp_fspi_invalid()`.

### Step 5.2: TRACE CALLERS
**Record:** `nxp_fspi_exec_op` is registered in
`nxp_fspi_mem_ops.exec_op` (line 1329). Called from `spi_mem_exec_op()`
in `drivers/spi/spi-mem.c`, which is the standard path for SPI NOR flash
operations (read/program/erase). Common on NXP i.MX and Layerscape
boards using FlexSPI for boot flash.

### Step 5.3: TRACE CALLEES
**Record:** Clock disable/enable (`nxp_fspi_clk_*`), `clk_set_rate()`,
MMIO via `fspi_readl`/`fspi_writel` in LUT prep and `nxp_fspi_invalid()`
(MCR0 SWRESET).

### Step 5.4: FOLLOW THE CALL CHAIN
**Record:** MTD/spi-nor → `spi_mem_exec_op()` → `nxp_fspi_exec_op()` →
`nxp_fspi_select_mem()`. Reachable during normal flash I/O when chip-
select, DTR/STR mode, or `max_freq` changes between operations
(`per_op_freq = true` in mem caps). **Userspace-reachable** via flash
access (root typically, but critical for system stability).

### Step 5.5: SEARCH FOR SIMILAR PATTERNS
**Record:** ACPI path skips manual clock disable/enable
(`is_acpi_node()` early return in `nxp_fspi_clk_disable_unprep` /
`nxp_fspi_clk_prep_enable`). Bug is most severe on **Device Tree**
platforms (primary NXP embedded use case) where
`nxp_fspi_clk_disable_unprep()` actually gates clocks.

---

## PHASE 6: CROSS-REFERENCING AGAINST THE LOCAL TREE

### Step 6.1: DOES THE BUGGY CODE EXIST IN THIS TREE?
**Record:** **YES.** Current 6.18.44 code:

```862:920:drivers/spi/spi-nxp-fspi.c
static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device
*spi,
                                const struct spi_mem_op *op)
{
        // ...
        nxp_fspi_clk_disable_unprep(f);

        ret = clk_set_rate(f->clk, rate);
        if (ret)
                return;

        ret = nxp_fspi_clk_prep_enable(f);
        if (ret)
                return;
```

```1121:1142:drivers/spi/spi-nxp-fspi.c
        nxp_fspi_select_mem(f, mem->spi, op);

        nxp_fspi_prepare_lut(f, op);
        // ... transfer ...
        nxp_fspi_invalid(f);
```

### Step 6.2: CHECK FOR BACKPORT COMPLICATIONS
**Record:** **Clean apply expected.** This tree lacks patch 2's MCR0
stop-mode code in `nxp_fspi_select_mem()`, so the backport is actually
simpler than upstream context. No conflicting changes found.

### Step 6.3: CHECK IF RELATED FIXES ARE ALREADY HERE
**Record:** Patch 1 (`51c52e493346f`) present. This error-propagation
fix is **not** present. No duplicate fix found.

---

## PHASE 7: SUBSYSTEM AND MAINTAINER CONTEXT

### Step 7.1: IDENTIFY THE SUBSYSTEM AND ITS CRITICALITY
**Record:** **drivers/spi** — NXP FlexSPI (`CONFIG_SPI_NXP_FLEXSPI`,
depends on `ARCH_MXC || ARCH_LAYERSCAPE`). **IMPORTANT** for embedded
NXP platforms (boot flash, MTD); not universal core code, but critical
where enabled.

### Step 7.2: ASSESS SUBSYSTEM ACTIVITY
**Record:** Active in 6.18.y — recent backports include `51c52e493346f`,
`c1c2871f33360`, `40ad64ac25bb7`.

---

## PHASE 8: IMPACT AND RISK ASSESSMENT

### Step 8.1: DETERMINE WHO IS AFFECTED
**Record:** Users of `CONFIG_SPI_NXP_FLEXSPI` on i.MX
(8MM/MP/QXP/DXL/ULP/95) and Layerscape (LX2160A) platforms with DT-based
clock control.

### Step 8.2: DETERMINE THE TRIGGER CONDITIONS
**Record:** Any SPI-mem operation requiring chip-select or clock/mode
reconfiguration when `clk_set_rate()` or `nxp_fspi_clk_prep_enable()`
fails (unsupported rate, CCM/clock driver error, resource pressure).
Uncommon but realistic; more likely after dynamic per-op frequency
changes. Privileged flash access path.

### Step 8.3: DETERMINE THE FAILURE MODE SEVERITY
**Record:** **Synchronous external abort** on MMIO with gated clocks →
kernel oops/panic. **Severity: CRITICAL.**

### Step 8.4: CALCULATE RISK-BENEFIT RATIO
**Record:**
- **Benefit:** HIGH — prevents hard kernel crash on error path.
- **Risk:** LOW — ~30 lines, error-path only, SPI maintainer committed.
- **Ratio:** Strongly favors backport.

---

## PHASE 9: FINAL SYNTHESIS

### Step 9.1: COMPILE THE EVIDENCE

**FOR backport:**
- Real bug with documented CRITICAL failure mode (sync external abort)
- Small, surgical, maintainer-merged fix
- Buggy code confirmed present in Linux 6.18.44
- Patch 1 of same series already backported to this tree
- Standalone application without patch 2
- Prevents crash on flash I/O error paths

**AGAINST backport:**
- No syzbot/user bug report (theoretical until clock reconfig fails)
- Affects driver-specific embedded platforms only
- Patch 2 of series not in tree (minor context difference, not a
  blocker)

**UNRESOLVED:**
- Exact upstream commit SHA not in this checkout (fix not merged here
  yet)
- No explicit `Cc: stable` in review thread found

### Step 9.2: STABLE RULES CHECKLIST
1. Obviously correct and tested? **PASS** — logic is clear; merged by
   SPI maintainer.
2. Fixes a real bug affecting users? **PASS** — crash on FlexSPI flash
   operations.
3. Important issue? **PASS** — CRITICAL (kernel crash / external abort).
4. Small and contained? **PASS** — one file, ~32 lines.
5. No new features or APIs? **PASS** — error propagation only.
6. Can apply to the local tree? **PASS** — bug present; clean/minor-
   context apply.

### Step 9.3: EXCEPTION CATEGORIES
**Record:** None (not device ID, quirk, DT, build, or docs). Standard
bug-fix backport.

### Step 9.4: DECISION RATIONALE

For **this 6.18.44 tree**, the buggy void-return pattern is live in
`spi-nxp-fspi.c`. When clock reconfiguration fails during a flash
operation, the driver continues accessing gated FlexSPI registers and
can trigger a synchronous external abort — a production-killing failure
on affected NXP hardware. The fix is minimal, obviously correct, already
vetted by the SPI maintainer, and independently applicable (patch 1 is
already here; patch 2 is not required). Risk is low; benefit is
preventing kernel crashes.

---

## Verification

- **[Phase 1]** `git describe HEAD` → v6.18.44; parsed subject, tags
  (Link, SOBs), body
- **[Phase 1]** No Fixes:/Reported-by:/Cc: stable tags
- **[Phase 2]** Read current `spi-nxp-fspi.c` lines 862–934, 1103–1147;
  confirmed void return + silent failure
- **[Phase 2]** Confirmed `nxp_fspi_invalid()` does MMIO (lines 611–622)
- **[Phase 2]** Confirmed ACPI skips manual clk disable/enable (lines
  704–705, 722–723)
- **[Phase 3]** `git log -20 -- drivers/spi/spi-nxp-fspi.c` — recent
  fspi commits
- **[Phase 3]** `git show 51c52e493346f` — patch 1/3 already backported
  to this tree
- **[Phase 3]** `git blame -L 900,950` — buggy clk path present
- **[Phase 3]** `git log --grep="propagate clock"` — fix not in tree
- **[Phase 4]** `b4 dig` — commit not in tree; usage confirmed
- **[Phase 4]** WebFetch lkml.iu.edu/2607.3/07703.html — patch 3/3
  content confirmed
- **[Phase 4]** WebFetch lists.openwall.net — series cover letter
  (patches 1–3) confirmed
- **[Phase 4]** lore.kernel.org — blocked (bot protection); used mirrors
- **[Phase 5]** `grep nxp_fspi_exec_op` — mem_ops registration at line
  1329
- **[Phase 5]** Read `spi-mem.c` `spi_mem_exec_op()` — standard flash
  path
- **[Phase 5]** Kconfig `SPI_NXP_FLEXSPI` — ARCH_MXC || ARCH_LAYERSCAPE
- **[Phase 5]** `of_device_id` — imx8*, lx2160a, imx95 compatibles
- **[Phase 6]** Buggy code verified present in 6.18.44 checkout
- **[Phase 6]** No duplicate fix in tree
- **[Phase 6]** Patch 2 (MCR0 stop mode) absent — backport simpler
- **[Phase 8]** Failure mode: synchronous external abort — CRITICAL

**YES**

 drivers/spi/spi-nxp-fspi.c | 32 +++++++++++++++++++++++++-------
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index b504a5c86692a..69ab72fff19d2 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -859,8 +859,8 @@ static void nxp_fspi_dll_override(struct nxp_fspi *f)
  * Value for rest of the CS FLSHxxCR0 register would be zero.
  *
  */
-static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
-				const struct spi_mem_op *op)
+static int nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
+			       const struct spi_mem_op *op)
 {
 	/* flexspi only support one DTR mode: 8D-8D-8D */
 	bool op_is_dtr = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr;
@@ -880,7 +880,7 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
 	if ((f->selected == spi_get_chipselect(spi, 0)) &&
 	    (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr) &&
 	    (f->pre_op_rate == op->max_freq))
-		return;
+		return 0;
 
 	/* Reset FLSHxxCR0 registers */
 	fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
@@ -912,12 +912,19 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
 	nxp_fspi_clk_disable_unprep(f);
 
 	ret = clk_set_rate(f->clk, rate);
-	if (ret)
-		return;
+	if (ret) {
+		/*
+		 * clk_set_rate() failed with the clocks already disabled.
+		 * Re-enable them so the enable count matches what the caller's
+		 * pm_runtime_put() (runtime_suspend) will drop.
+		 */
+		nxp_fspi_clk_prep_enable(f);
+		return ret;
+	}
 
 	ret = nxp_fspi_clk_prep_enable(f);
 	if (ret)
-		return;
+		return ret;
 
 	/*
 	 * If clock rate > 100MHz, then switch from DLL override mode to
@@ -931,6 +938,8 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
 	f->pre_op_rate = op->max_freq;
 
 	f->selected = spi_get_chipselect(spi, 0);
+
+	return 0;
 }
 
 static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
@@ -1118,7 +1127,16 @@ static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 				   FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
 	WARN_ON(err);
 
-	nxp_fspi_select_mem(f, mem->spi, op);
+	err = nxp_fspi_select_mem(f, mem->spi, op);
+	if (err) {
+		/*
+		 * On failure the FlexSPI clock may be left disabled, so avoid
+		 * any further register access (which would trigger a synchronous
+		 * external abort) and bail out.
+		 */
+		pm_runtime_put_autosuspend(f->dev);
+		return err;
+	}
 
 	nxp_fspi_prepare_lut(f, op);
 	/*
-- 
2.53.0

Re: [PATCH AUTOSEL 6.18-6.12] mailbox: imx: Add a channel shutdown field

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The patch fixes the teardown race for RX channels but misses the identical race condition for TX channels, allowing spurious interrupts.
--

commit 339489ae41b0a2b0727c73521707e00976aca9f5
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

mailbox: imx: Add a channel shutdown field

This commit introduces a shutdown flag to imx_mu_con_priv to coordinate
channel teardown and prevent the ISR from re-enabling interrupts after
imx_mu_shutdown() has disabled them. The flag is checked by a new function
imx_mu_xcr_set_act() before modifying the control register.

> diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
> index 6778afc64a048..44c2cc06b794e 100644
> --- a/drivers/mailbox/imx-mailbox.c
> +++ b/drivers/mailbox/imx-mailbox.c
[ ... ]
> @@ -220,6 +221,36 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 se
>  	return val;
>  }
>  
> +static void imx_mu_xcr_clr_shut(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
> +				enum imx_mu_xcr type, u32 clr)
> +{
> +	unsigned long flags;
> +	u32 val;
> +
> +	spin_lock_irqsave(&priv->xcr_lock, flags);
> +	cp->shutdown = true;
> +
> +	val = imx_mu_read(priv, priv->dcfg->xCR[type]);
> +	val &= ~clr;
> +	imx_mu_write(priv, val, priv->dcfg->xCR[type]);
> +	spin_unlock_irqrestore(&priv->xcr_lock, flags);
> +}
> +
> +static void imx_mu_xcr_set_act(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
> +			       enum imx_mu_xcr type, u32 set)
> +{
> +	unsigned long flags;
> +	u32 val;
> +
> +	spin_lock_irqsave(&priv->xcr_lock, flags);
> +	if (!cp->shutdown) {
> +		val = imx_mu_read(priv, priv->dcfg->xCR[type]);
> +		val |= set;
> +		imx_mu_write(priv, val, priv->dcfg->xCR[type]);
> +	}
> +	spin_unlock_irqrestore(&priv->xcr_lock, flags);
> +}
> +
[ ... ]
> @@ -377,7 +408,7 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
>  		*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4);
>  	}
>  
> -	imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
> +	imx_mu_xcr_set_act(priv, cp, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
>  	mbox_chan_received_data(cp->chan, (void *)priv->msg);
>  
>  	return 0;

[Severity: High]
This is a pre-existing issue, but while this patch successfully fixes the
teardown race for RX channels, does the identical race still exist for TX
channels?

If mbox_free_channel() is called while a TX interrupt is active and there are
pending TX messages, it calls imx_mu_shutdown() which sets cp->shutdown = true
and clears the TX interrupt enable bit, then blocks in free_irq().

When the concurrent ISR completes the current TX, it calls mbox_chan_txdone(),
triggering msg_submit() to send the next queued message via
imx_mu_generic_tx() or imx_mu_specific_tx().

Both functions unconditionally rewrite the TX interrupt enable bit using
imx_mu_xcr_rmw(), bypassing the new shutdown flag:

drivers/mailbox/imx-mailbox.c:imx_mu_generic_tx() {
    ...
	case IMX_MU_TYPE_TX:
		imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
		imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
		break;
    ...
}

And similarly in imx_mu_specific_tx():

drivers/mailbox/imx-mailbox.c:imx_mu_specific_tx() {
    ...
		for (; i < size; i++) {
			ret = readl_poll_timeout(...);
			if (ret) {
				...
			}
			imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
		}

		imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
		break;
    ...
}

Should these TX paths also be updated to use imx_mu_xcr_set_act() to prevent
a spurious interrupt from disabling the shared IRQ line during teardown?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260831133314.4125787-195-sashal@kernel.org?part=1

Re: [PATCH AUTOSEL 6.18-6.12] watchdog: imx7ulp_wdt: Keep WDOG running until A55 enters WFI on i.MX94

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

Pre-existing issues:
- [High] Hardware manipulation functions unconditionally re-enable local interrupts and sleep, causing kernel panics when invoked from atomic contexts such as the restart handler and noirq suspend.
- [High] Watchdog is not stopped during suspend if it was started by the bootloader but not yet opened by userspace, leading to a system reset.
--

commit 3360fb6ec8b553a77597875579f51efb6523f1f5
Author: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
watchdog: imx7ulp_wdt: Keep WDOG running until A55 enters WFI on i.MX94

This commit introduces a hardware feature flag to indicate CPU low-power-mode
auto clock gating support on i.MX94. It uses this flag to prevent the watchdog
from being stopped during suspend, allowing the LPCG hardware to safely manage
it.

Link: https://lore.kernel.org/r/20260206-imx94-wdog-v2-1-4dd725faec1f@nxp.com

> diff --git a/drivers/watchdog/imx7ulp_wdt.c b/drivers/watchdog/imx7ulp_wdt.c
> index 0f13a30533574..33e5eb87e05e6 100644
> --- a/drivers/watchdog/imx7ulp_wdt.c
> +++ b/drivers/watchdog/imx7ulp_wdt.c

[ ... ]

> @@ -359,7 +360,7 @@ static int __maybe_unused imx7ulp_wdt_suspend_noirq(struct device *dev)
>  {
>  	struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
>  
> -	if (watchdog_active(&imx7ulp_wdt->wdd))
> +	if (watchdog_active(&imx7ulp_wdt->wdd) && !imx7ulp_wdt->hw->cpu_lpm_auto_cg)

[Severity: High]
This is a pre-existing issue, but does this conditional overlook watchdogs left
running by the bootloader?

If the bootloader starts the watchdog (so watchdog_hw_running() is true) but
userspace has not yet opened it (so watchdog_active() is false), the kernel's
ping worker handles the pinging. During system suspend, the PM core cancels
this ping worker.

Because this code only checks watchdog_active(), it will fail to stop the
hardware watchdog in this scenario. Consequently, the watchdog hardware keeps
running while the system is suspended, and because the ping worker is frozen,
the watchdog will time out and cause an unexpected system reset.

Should this code also check watchdog_hw_running(&imx7ulp_wdt->wdd)?

>  		imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);

[Severity: High]
This is a pre-existing issue, but does this call chain trigger a "scheduling
while atomic" panic or break atomic context constraints?

imx7ulp_wdt_suspend_noirq() is called during the noirq phase of system suspend
with local interrupts disabled. It calls imx7ulp_wdt_stop(), which eventually
reaches _imx7ulp_wdt_enable().

_imx7ulp_wdt_enable() unconditionally calls local_irq_enable(), which breaks
the noirq interrupt constraints.

Furthermore, _imx7ulp_wdt_enable() then calls imx7ulp_wdt_wait_rcs(), which can
execute usleep_range() or readl_poll_timeout(). Sleeping with interrupts
disabled or inside a noirq callback will trigger a panic.

Since this same path can be reached during reboot via imx7ulp_wdt_restart()
(which is also called with interrupts disabled), is it safe to allow
_imx7ulp_wdt_enable() to re-enable interrupts and sleep?

>  	clk_disable_unprepare(imx7ulp_wdt->clk);
>  
>  	return 0;
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260831133314.4125787-398-sashal@kernel.org?part=1

Re: [PATCH AUTOSEL 6.18] i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Inconsistent use of I/O accessors for FIFO accesses, mixing stream and register accessors, which causes data corruption on big-endian systems.
--

commit c282e92f4b93fba4c854d5e9c34c1ac10212811f
Author: Stanley Chu <yschu@nuvoton.com>

    i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845

This commit adds a hardware quirk workaround for the NPCM845 controller.
It explicitly clears the SLVSTART status bit after emitting a STOP
condition in the Master Request IBI handler to prevent an IRQ storm caused
by a spurious SLVSTART.

Link: https://patch.msgid.link/20260413005040.1211107-3-yschu@nuvoton.com

> diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> index 9641e66a4e5f2..e74b22c6f808c 100644
> --- a/drivers/i3c/master/svc-i3c-master.c
> +++ b/drivers/i3c/master/svc-i3c-master.c

[ ... ]

[Severity: High]
This isn't a bug introduced by this patch, but there is a pre-existing
issue in this file regarding I/O accessors for FIFO registers.

In svc_i3c_master_xfer(), does this code mix a stream accessor (writesb)
for bulk data with a register accessor (writel) for the final byte on the
same FIFO?

drivers/i3c/master/svc-i3c-master.c:svc_i3c_master_xfer() {
    ...
    writesb(master->regs + SVC_I3C_MWDATAB1, out, len - 1);
    /* Mark END bit if this is the last byte */
    writel(out[len - 1] | end, master->regs + SVC_I3C_MWDATAB);
    ...
}

Using writel() for the remainder byte performs unwanted byte-swapping on
big-endian platforms, which can corrupt the data sent on the I3C bus.

[Severity: High]
This is also a pre-existing issue, but do the readl() calls in
svc_i3c_master_read() and svc_i3c_master_readb() perform incorrect
byteswapping when reading from the MRDATAB FIFO?

drivers/i3c/master/svc-i3c-master.c:svc_i3c_master_handle_ibi() {
    ...
    readsb(master->regs + SVC_I3C_MRDATAB, buf, count);
    ...
}

drivers/i3c/master/svc-i3c-master.c:svc_i3c_master_read() {
    ...
    in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB);
    ...
}

drivers/i3c/master/svc-i3c-master.c:svc_i3c_master_readb() {
    ...
    dst[i] = readl(master->regs + SVC_I3C_MRDATAB);
    ...
}

Since readsb() is used in svc_i3c_master_handle_ibi() for the same
MRDATAB FIFO, using readl() to read individual bytes into a u8 buffer in
other functions could result in corrupted data on big-endian systems.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260831133314.4125787-647-sashal@kernel.org?part=1

Re: [PATCH AUTOSEL 6.18] spi: spi-nxp-fspi: propagate clock reconfig failures in nxp_fspi_select_mem()

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:

New issues:
- [High] Hardware chip-select configuration is desynchronized from software tracking state on clock reconfiguration failure.
- [High] PM runtime state remains active while hardware clocks are left disabled on clock enable failure, causing a subsequent synchronous external abort.

Pre-existing issues:
- [High] Teardown asymmetry leaves the IRQ handler active after hardware clocks are disabled, risking an external abort.
- [High] Unchecked pm_runtime_get_sync() in nxp_fspi_cleanup() can lead to a synchronous external abort.
- [High] The interrupt handler accesses hardware registers without verifying the PM active state, violating subsystem guidelines and risking an external abort.
--

commit 90f6f57222227859ff0d0df74b2ed0073979680a
Author: Haibo Chen <haibo.chen@nxp.com>

spi: spi-nxp-fspi: propagate clock reconfig failures in nxp_fspi_select_mem()

This commit modifies nxp_fspi_select_mem() to return an integer error code
instead of void. It ensures that if clock reconfiguration fails, the failure
is propagated to nxp_fspi_exec_op(), which then bails out to avoid triggering
a synchronous external abort when accessing gated hardware registers.

Link: https://patch.msgid.link/20260728-fspi-clock-v2-3-dbe786a4a6eb@nxp.com

> diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
> index 50a7e4916a600..f672619c16afb 100644
> --- a/drivers/spi/spi-nxp-fspi.c
> +++ b/drivers/spi/spi-nxp-fspi.c
[ ... ]
> @@ -804,7 +804,7 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
>  	if ((f->selected == spi_get_chipselect(spi, 0)) &&
>  	    (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr) &&
>  	    (f->pre_op_rate == op->max_freq))
> -		return;
> +		return 0;

[Severity: High]
Can hardware chip-select configuration become desynchronized from the software
tracking state if a clock reconfiguration failure occurs?

If clk_set_rate() fails during a chip select change in nxp_fspi_select_mem()
in drivers/spi/spi-nxp-fspi.c:

nxp_fspi_select_mem()
    fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
                4 * spi_get_chipselect(spi, 0));

Hardware is reprogrammed to the new chip select, and all other chip selects are
cleared to 0 size.

    ret = clk_set_rate(f->clk, rate);
    if (ret)
        return ret;

The function then returns an error, bypassing the state update:

    f->selected = spi_get_chipselect(spi, 0);

On the next operation for the old chip select, wouldn't this early return check
incorrectly succeed (since f->selected still matches the old chip select),
bypassing hardware reconfiguration while the hardware is actually configured for
the new chip select?

[ ... ]
> @@ -836,12 +836,19 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
>  	nxp_fspi_clk_disable_unprep(f);
>  
>  	ret = clk_set_rate(f->clk, rate);
> -	if (ret)
> -		return;
> +	if (ret) {
> +		/*
> +		 * clk_set_rate() failed with the clocks already disabled.
> +		 * Re-enable them so the enable count matches what the caller's
> +		 * pm_runtime_put() (runtime_suspend) will drop.
> +		 */
> +		nxp_fspi_clk_prep_enable(f);
> +		return ret;
> +	}
>  
>  	ret = nxp_fspi_clk_prep_enable(f);
>  	if (ret)
> -		return;
> +		return ret;
[ ... ]
> @@ -1042,7 +1051,16 @@ static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
>  				   FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
>  	WARN_ON(err);
>  
> -	nxp_fspi_select_mem(f, mem->spi, op);
> +	err = nxp_fspi_select_mem(f, mem->spi, op);
> +	if (err) {
> +		/*
> +		 * On failure the FlexSPI clock may be left disabled, so avoid
> +		 * any further register access (which would trigger a synchronous
> +		 * external abort) and bail out.
> +		 */
> +		pm_runtime_put_autosuspend(f->dev);
> +		return err;
> +	}

[Severity: High]
If nxp_fspi_clk_prep_enable() fails, the function returns an error while the
hardware clocks are still physically disabled. 

When this happens, does nxp_fspi_exec_op() in drivers/spi/spi-nxp-fspi.c
correctly handle the PM runtime state?

nxp_fspi_exec_op()
    err = nxp_fspi_select_mem(f, mem->spi, op);
    if (err) {
        pm_runtime_put_autosuspend(f->dev);
        return err;
    }

Since autosuspend is used on the error path, the device remains in the
RPM_ACTIVE state for the duration of the timeout, even though hardware clocks
are off. If another operation runs immediately:

nxp_fspi_exec_op()
    pm_runtime_get_sync(f->dev); /* succeeds instantly without enabling clocks */
    ...
    fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, ...);

Could this sequence trigger a synchronous external abort when accessing the
memory-mapped registers during the subsequent operation?


While reviewing this patch, I also noticed a few pre-existing issues:

> drivers/spi/spi-nxp-fspi.c:nxp_fspi_probe() {
[ ... ]
> 	ret = devm_request_irq(dev, irq,
> 			nxp_fspi_irq_handler, 0, pdev->name, f);
> 	if (ret)
> 		return dev_err_probe(dev, ret, "Failed to request irq\n");
[ ... ]
> 	ret = devm_add_action_or_reset(dev, nxp_fspi_cleanup, f);
> 	if (ret)
> 		return ret;

[Severity: High]
This is a pre-existing issue, but does this teardown asymmetry risk a
synchronous external abort?

During driver unbind in drivers/spi/spi-nxp-fspi.c, devres will execute LIFO,
meaning nxp_fspi_cleanup() will be called before devm_free_irq() completes:

nxp_fspi_cleanup()
    fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
    pm_runtime_disable(f->dev);
    nxp_fspi_clk_disable_unprep(f);

Since the IRQ handler is still active while clocks are disabled, what happens if
a spurious or delayed interrupt fires and nxp_fspi_irq_handler() accesses the
hardware registers?


> drivers/spi/spi-nxp-fspi.c:nxp_fspi_cleanup() {
> 	/* enable clock first since there is register access */
> 	pm_runtime_get_sync(f->dev);
> 
> 	/* disable the hardware */
> 	fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);

[Severity: High]
This is a pre-existing issue, but is it safe to proceed without checking the
return value of pm_runtime_get_sync()? 

If pm_runtime_get_sync() fails to resume the device in nxp_fspi_cleanup() (for
example, due to a clock enable failure), wouldn't the subsequent write to
FSPI_MCR0 occur with gated clocks and trigger a synchronous external abort?


> drivers/spi/spi-nxp-fspi.c:nxp_fspi_irq_handler() {
> 	struct nxp_fspi *f = dev_id;
> 	u32 reg;
> 
> 	/* clear interrupt */
> 	reg = fspi_readl(f, f->iobase + FSPI_INTR);

[Severity: High]
This is a pre-existing issue, but does the interrupt handler violate PM
subsystem rules by accessing hardware registers without verifying the PM active
state?

If the device is in runtime suspend (with clocks gated) and a spurious
interrupt fires on a shared IRQ line, nxp_fspi_irq_handler() blindly reads
FSPI_INTR in drivers/spi/spi-nxp-fspi.c.

Without calling pm_runtime_get_if_active() first, could this invalid hardware
access crash the system with a synchronous external abort?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260831133314.4125787-661-sashal@kernel.org?part=1