Re: [PATCH v8 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `wm8904` codec references an unconfigured and incorrect clock (`IMX7D_AUDIO_MCLK_ROOT_DIV`) instead of the actual physical clock providing its MCLK.
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commit 1b158b02c4e2ef7937d25acb3234a66676fd29b6
Author: Stefano Radaelli <stefano.r@variscite.com>
Subject: ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support

This commit adds device tree support for the Variscite VAR-SOM-MX7 system
on module. It introduces the common SoM description along with support for
eMMC, NAND, WM8731, WM8904, and the V2 hardware revision.

Link: https://variscite.com/system-on-module-som/i-mx-7/var-som-mx7/

> diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8904.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8904.dtsi
> new file mode 100644
> index 0000000000000..b56f3680edcff
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8904.dtsi
[ ... ]
> @@ -0,0 +1,118 @@
[ ... ]
> +&i2c2 {
> +	wm8904: audio-codec@1a {
> +		compatible = "wlf,wm8904";
> +		reg = <0x1a>;
> +		#sound-dai-cells = <0>;
> +		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;

[Severity: Medium]
Does this code assign the wrong clock to the wm8904 codec's mclk?

The codec is configured to use IMX7D_AUDIO_MCLK_ROOT_DIV, but shouldn't this
point to the clock actually driving the MCLK pad (such as
IMX7D_SAI1_ROOT_CLK)?

If the driver queries the frequency of this incorrect clock tree node (which
defaults to 24MHz) instead of the actual 12.288MHz rate driven by the SAI1
pad, it may miscalculate its internal PLL/FLL configuration. 

Could this result in incorrect audio playback speeds or a failure to lock
the FLL when the audio subsystem initializes?

> +		clock-names = "mclk";
> +		AVDD-supply = <&vgen6_reg>;
> +		CPVDD-supply = <&vgen6_reg>;
[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/cover.1788184274.git.stefano.r@variscite.com?part=2