Re: [PATCH v8 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support

[Stefano Radaelli <stefano.radaelli21@gmail.com>]

On Mon, Aug 31, 2026 at 11:10:41PM +0000, sashiko-bot@kernel.org wrote:
> 
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8904.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8904.dtsi
> > new file mode 100644
> > index 0000000000000..b56f3680edcff
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8904.dtsi
> [ ... ]
> > @@ -0,0 +1,118 @@
> [ ... ]
> > +&i2c2 {
> > +	wm8904: audio-codec@1a {
> > +		compatible = "wlf,wm8904";
> > +		reg = <0x1a>;
> > +		#sound-dai-cells = <0>;
> > +		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
> 
> [Severity: Medium]
> Does this code assign the wrong clock to the wm8904 codec's mclk?
> 
> The codec is configured to use IMX7D_AUDIO_MCLK_ROOT_DIV, but shouldn't this
> point to the clock actually driving the MCLK pad (such as
> IMX7D_SAI1_ROOT_CLK)?
> 
> If the driver queries the frequency of this incorrect clock tree node (which
> defaults to 24MHz) instead of the actual 12.288MHz rate driven by the SAI1
> pad, it may miscalculate its internal PLL/FLL configuration. 
> 
> Could this result in incorrect audio playback speeds or a failure to lock
> the FLL when the audio subsystem initializes?
> 

This is intentional. The WM8904 MCLK is provided by the dedicated audio
MCLK root, while the SAI1 root clock is configured separately for the
SAI interface.
The fact that the pad is muxed as SAI1_MCLK does not imply that the
codec clock provider must be IMX7D_SAI1_ROOT_CLK.
This configuration has been validated on the hardware.

Stefano